Commit | Line | Data |
---|---|---|
ccdc7bf9 SO |
1 | /* |
2 | * OMAP2 McSPI controller driver | |
3 | * | |
4 | * Copyright (C) 2005, 2006 Nokia Corporation | |
5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and | |
1a5d8190 | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
ccdc7bf9 SO |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/dma-mapping.h> | |
53741ed8 RK |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/omap-dma.h> | |
ccdc7bf9 SO |
33 | #include <linux/platform_device.h> |
34 | #include <linux/err.h> | |
35 | #include <linux/clk.h> | |
36 | #include <linux/io.h> | |
5a0e3ad6 | 37 | #include <linux/slab.h> |
1f1a4384 | 38 | #include <linux/pm_runtime.h> |
d5a80031 BC |
39 | #include <linux/of.h> |
40 | #include <linux/of_device.h> | |
d33f473d | 41 | #include <linux/gcd.h> |
ccdc7bf9 SO |
42 | |
43 | #include <linux/spi/spi.h> | |
44 | ||
2203747c | 45 | #include <linux/platform_data/spi-omap2-mcspi.h> |
ccdc7bf9 SO |
46 | |
47 | #define OMAP2_MCSPI_MAX_FREQ 48000000 | |
d33f473d IS |
48 | #define OMAP2_MCSPI_MAX_FIFODEPTH 64 |
49 | #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF | |
27b5284c | 50 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
ccdc7bf9 SO |
51 | |
52 | #define OMAP2_MCSPI_REVISION 0x00 | |
ccdc7bf9 SO |
53 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
54 | #define OMAP2_MCSPI_IRQSTATUS 0x18 | |
55 | #define OMAP2_MCSPI_IRQENABLE 0x1c | |
56 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 | |
57 | #define OMAP2_MCSPI_SYST 0x24 | |
58 | #define OMAP2_MCSPI_MODULCTRL 0x28 | |
d33f473d | 59 | #define OMAP2_MCSPI_XFERLEVEL 0x7c |
ccdc7bf9 SO |
60 | |
61 | /* per-channel banks, 0x14 bytes each, first is: */ | |
62 | #define OMAP2_MCSPI_CHCONF0 0x2c | |
63 | #define OMAP2_MCSPI_CHSTAT0 0x30 | |
64 | #define OMAP2_MCSPI_CHCTRL0 0x34 | |
65 | #define OMAP2_MCSPI_TX0 0x38 | |
66 | #define OMAP2_MCSPI_RX0 0x3c | |
67 | ||
68 | /* per-register bitmasks: */ | |
d33f473d | 69 | #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17) |
ccdc7bf9 | 70 | |
7a8fa725 JH |
71 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
72 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) | |
73 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) | |
ccdc7bf9 | 74 | |
7a8fa725 JH |
75 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
76 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) | |
ccdc7bf9 | 77 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
7a8fa725 | 78 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
ccdc7bf9 | 79 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
7a8fa725 JH |
80 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
81 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) | |
ccdc7bf9 | 82 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
7a8fa725 JH |
83 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
84 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) | |
85 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) | |
86 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) | |
87 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) | |
88 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) | |
89 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) | |
d33f473d IS |
90 | #define OMAP2_MCSPI_CHCONF_FFET BIT(27) |
91 | #define OMAP2_MCSPI_CHCONF_FFER BIT(28) | |
ccdc7bf9 | 92 | |
7a8fa725 JH |
93 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
94 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) | |
95 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) | |
d33f473d | 96 | #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3) |
ccdc7bf9 | 97 | |
7a8fa725 | 98 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
ccdc7bf9 | 99 | |
7a8fa725 | 100 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
ccdc7bf9 SO |
101 | |
102 | /* We have 2 DMA channels per CS, one for RX and one for TX */ | |
103 | struct omap2_mcspi_dma { | |
53741ed8 RK |
104 | struct dma_chan *dma_tx; |
105 | struct dma_chan *dma_rx; | |
ccdc7bf9 SO |
106 | |
107 | int dma_tx_sync_dev; | |
108 | int dma_rx_sync_dev; | |
109 | ||
110 | struct completion dma_tx_completion; | |
111 | struct completion dma_rx_completion; | |
74f3aaad MP |
112 | |
113 | char dma_rx_ch_name[14]; | |
114 | char dma_tx_ch_name[14]; | |
ccdc7bf9 SO |
115 | }; |
116 | ||
117 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and | |
118 | * cache operations; better heuristics consider wordsize and bitrate. | |
119 | */ | |
8b66c134 | 120 | #define DMA_MIN_BYTES 160 |
ccdc7bf9 SO |
121 | |
122 | ||
1bd897f8 BC |
123 | /* |
124 | * Used for context save and restore, structure members to be updated whenever | |
125 | * corresponding registers are modified. | |
126 | */ | |
127 | struct omap2_mcspi_regs { | |
128 | u32 modulctrl; | |
129 | u32 wakeupenable; | |
130 | struct list_head cs; | |
131 | }; | |
132 | ||
ccdc7bf9 | 133 | struct omap2_mcspi { |
ccdc7bf9 | 134 | struct spi_master *master; |
ccdc7bf9 SO |
135 | /* Virtual base address of the controller */ |
136 | void __iomem *base; | |
e5480b73 | 137 | unsigned long phys; |
ccdc7bf9 SO |
138 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
139 | struct omap2_mcspi_dma *dma_channels; | |
1bd897f8 | 140 | struct device *dev; |
1bd897f8 | 141 | struct omap2_mcspi_regs ctx; |
d33f473d | 142 | int fifo_depth; |
0384e90b | 143 | unsigned int pin_dir:1; |
ccdc7bf9 SO |
144 | }; |
145 | ||
146 | struct omap2_mcspi_cs { | |
147 | void __iomem *base; | |
e5480b73 | 148 | unsigned long phys; |
ccdc7bf9 | 149 | int word_len; |
89c05372 | 150 | struct list_head node; |
a41ae1ad H |
151 | /* Context save and restore shadow register */ |
152 | u32 chconf0; | |
153 | }; | |
154 | ||
ccdc7bf9 SO |
155 | static inline void mcspi_write_reg(struct spi_master *master, |
156 | int idx, u32 val) | |
157 | { | |
158 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
159 | ||
160 | __raw_writel(val, mcspi->base + idx); | |
161 | } | |
162 | ||
163 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) | |
164 | { | |
165 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
166 | ||
167 | return __raw_readl(mcspi->base + idx); | |
168 | } | |
169 | ||
170 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, | |
171 | int idx, u32 val) | |
172 | { | |
173 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
174 | ||
175 | __raw_writel(val, cs->base + idx); | |
176 | } | |
177 | ||
178 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) | |
179 | { | |
180 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
181 | ||
182 | return __raw_readl(cs->base + idx); | |
183 | } | |
184 | ||
a41ae1ad H |
185 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
186 | { | |
187 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
188 | ||
189 | return cs->chconf0; | |
190 | } | |
191 | ||
192 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) | |
193 | { | |
194 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
195 | ||
196 | cs->chconf0 = val; | |
197 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); | |
a330ce20 | 198 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
a41ae1ad H |
199 | } |
200 | ||
56cd5c15 IS |
201 | static inline int mcspi_bytes_per_word(int word_len) |
202 | { | |
203 | if (word_len <= 8) | |
204 | return 1; | |
205 | else if (word_len <= 16) | |
206 | return 2; | |
207 | else /* word_len <= 32 */ | |
208 | return 4; | |
209 | } | |
210 | ||
ccdc7bf9 SO |
211 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
212 | int is_read, int enable) | |
213 | { | |
214 | u32 l, rw; | |
215 | ||
a41ae1ad | 216 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
217 | |
218 | if (is_read) /* 1 is read, 0 write */ | |
219 | rw = OMAP2_MCSPI_CHCONF_DMAR; | |
220 | else | |
221 | rw = OMAP2_MCSPI_CHCONF_DMAW; | |
222 | ||
af4e944d S |
223 | if (enable) |
224 | l |= rw; | |
225 | else | |
226 | l &= ~rw; | |
227 | ||
a41ae1ad | 228 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
229 | } |
230 | ||
231 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) | |
232 | { | |
233 | u32 l; | |
234 | ||
235 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; | |
236 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); | |
4743a0f8 RT |
237 | /* Flash post-writes */ |
238 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); | |
ccdc7bf9 SO |
239 | } |
240 | ||
241 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) | |
242 | { | |
243 | u32 l; | |
244 | ||
a41ae1ad | 245 | l = mcspi_cached_chconf0(spi); |
af4e944d S |
246 | if (cs_active) |
247 | l |= OMAP2_MCSPI_CHCONF_FORCE; | |
248 | else | |
249 | l &= ~OMAP2_MCSPI_CHCONF_FORCE; | |
250 | ||
a41ae1ad | 251 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
252 | } |
253 | ||
254 | static void omap2_mcspi_set_master_mode(struct spi_master *master) | |
255 | { | |
1bd897f8 BC |
256 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
257 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
258 | u32 l; |
259 | ||
1bd897f8 BC |
260 | /* |
261 | * Setup when switching from (reset default) slave mode | |
ccdc7bf9 SO |
262 | * to single-channel master mode |
263 | */ | |
264 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); | |
af4e944d S |
265 | l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS); |
266 | l |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
ccdc7bf9 | 267 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
a41ae1ad | 268 | |
1bd897f8 | 269 | ctx->modulctrl = l; |
a41ae1ad H |
270 | } |
271 | ||
d33f473d IS |
272 | static void omap2_mcspi_set_fifo(const struct spi_device *spi, |
273 | struct spi_transfer *t, int enable) | |
274 | { | |
275 | struct spi_master *master = spi->master; | |
276 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
277 | struct omap2_mcspi *mcspi; | |
278 | unsigned int wcnt; | |
5db542ed | 279 | int max_fifo_depth, fifo_depth, bytes_per_word; |
d33f473d IS |
280 | u32 chconf, xferlevel; |
281 | ||
282 | mcspi = spi_master_get_devdata(master); | |
283 | ||
284 | chconf = mcspi_cached_chconf0(spi); | |
285 | if (enable) { | |
286 | bytes_per_word = mcspi_bytes_per_word(cs->word_len); | |
287 | if (t->len % bytes_per_word != 0) | |
288 | goto disable_fifo; | |
289 | ||
5db542ed IS |
290 | if (t->rx_buf != NULL && t->tx_buf != NULL) |
291 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; | |
292 | else | |
293 | max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH; | |
294 | ||
295 | fifo_depth = gcd(t->len, max_fifo_depth); | |
d33f473d IS |
296 | if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0) |
297 | goto disable_fifo; | |
298 | ||
299 | wcnt = t->len / bytes_per_word; | |
300 | if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT) | |
301 | goto disable_fifo; | |
302 | ||
303 | xferlevel = wcnt << 16; | |
304 | if (t->rx_buf != NULL) { | |
305 | chconf |= OMAP2_MCSPI_CHCONF_FFER; | |
306 | xferlevel |= (fifo_depth - 1) << 8; | |
5db542ed IS |
307 | } |
308 | if (t->tx_buf != NULL) { | |
d33f473d IS |
309 | chconf |= OMAP2_MCSPI_CHCONF_FFET; |
310 | xferlevel |= fifo_depth - 1; | |
311 | } | |
312 | ||
313 | mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel); | |
314 | mcspi_write_chconf0(spi, chconf); | |
315 | mcspi->fifo_depth = fifo_depth; | |
316 | ||
317 | return; | |
318 | } | |
319 | ||
320 | disable_fifo: | |
321 | if (t->rx_buf != NULL) | |
322 | chconf &= ~OMAP2_MCSPI_CHCONF_FFER; | |
323 | else | |
324 | chconf &= ~OMAP2_MCSPI_CHCONF_FFET; | |
325 | ||
326 | mcspi_write_chconf0(spi, chconf); | |
327 | mcspi->fifo_depth = 0; | |
328 | } | |
329 | ||
a41ae1ad H |
330 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
331 | { | |
1bd897f8 BC |
332 | struct spi_master *spi_cntrl = mcspi->master; |
333 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
334 | struct omap2_mcspi_cs *cs; | |
a41ae1ad H |
335 | |
336 | /* McSPI: context restore */ | |
1bd897f8 BC |
337 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
338 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); | |
a41ae1ad | 339 | |
1bd897f8 | 340 | list_for_each_entry(cs, &ctx->cs, node) |
89c05372 | 341 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
a41ae1ad | 342 | } |
ccdc7bf9 | 343 | |
2764c500 IK |
344 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
345 | { | |
346 | unsigned long timeout; | |
347 | ||
348 | timeout = jiffies + msecs_to_jiffies(1000); | |
349 | while (!(__raw_readl(reg) & bit)) { | |
ff23fa3b SAS |
350 | if (time_after(jiffies, timeout)) { |
351 | if (!(__raw_readl(reg) & bit)) | |
352 | return -ETIMEDOUT; | |
353 | else | |
354 | return 0; | |
355 | } | |
2764c500 IK |
356 | cpu_relax(); |
357 | } | |
358 | return 0; | |
359 | } | |
360 | ||
53741ed8 RK |
361 | static void omap2_mcspi_rx_callback(void *data) |
362 | { | |
363 | struct spi_device *spi = data; | |
364 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
365 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
366 | ||
53741ed8 RK |
367 | /* We must disable the DMA RX request */ |
368 | omap2_mcspi_set_dma_req(spi, 1, 0); | |
830379e0 FB |
369 | |
370 | complete(&mcspi_dma->dma_rx_completion); | |
53741ed8 RK |
371 | } |
372 | ||
373 | static void omap2_mcspi_tx_callback(void *data) | |
374 | { | |
375 | struct spi_device *spi = data; | |
376 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); | |
377 | struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
378 | ||
53741ed8 RK |
379 | /* We must disable the DMA TX request */ |
380 | omap2_mcspi_set_dma_req(spi, 0, 0); | |
830379e0 FB |
381 | |
382 | complete(&mcspi_dma->dma_tx_completion); | |
53741ed8 RK |
383 | } |
384 | ||
d7b4394e S |
385 | static void omap2_mcspi_tx_dma(struct spi_device *spi, |
386 | struct spi_transfer *xfer, | |
387 | struct dma_slave_config cfg) | |
ccdc7bf9 SO |
388 | { |
389 | struct omap2_mcspi *mcspi; | |
ccdc7bf9 | 390 | struct omap2_mcspi_dma *mcspi_dma; |
8c7494a5 | 391 | unsigned int count; |
ccdc7bf9 SO |
392 | |
393 | mcspi = spi_master_get_devdata(spi->master); | |
394 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
d7b4394e | 395 | count = xfer->len; |
ccdc7bf9 | 396 | |
d7b4394e | 397 | if (mcspi_dma->dma_tx) { |
53741ed8 RK |
398 | struct dma_async_tx_descriptor *tx; |
399 | struct scatterlist sg; | |
400 | ||
401 | dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); | |
402 | ||
403 | sg_init_table(&sg, 1); | |
404 | sg_dma_address(&sg) = xfer->tx_dma; | |
405 | sg_dma_len(&sg) = xfer->len; | |
406 | ||
407 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1, | |
d7b4394e | 408 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
53741ed8 RK |
409 | if (tx) { |
410 | tx->callback = omap2_mcspi_tx_callback; | |
411 | tx->callback_param = spi; | |
412 | dmaengine_submit(tx); | |
413 | } else { | |
414 | /* FIXME: fall back to PIO? */ | |
415 | } | |
416 | } | |
d7b4394e S |
417 | dma_async_issue_pending(mcspi_dma->dma_tx); |
418 | omap2_mcspi_set_dma_req(spi, 0, 1); | |
419 | ||
d7b4394e | 420 | } |
53741ed8 | 421 | |
d7b4394e S |
422 | static unsigned |
423 | omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer, | |
424 | struct dma_slave_config cfg, | |
425 | unsigned es) | |
426 | { | |
427 | struct omap2_mcspi *mcspi; | |
428 | struct omap2_mcspi_dma *mcspi_dma; | |
d33f473d | 429 | unsigned int count, dma_count; |
d7b4394e S |
430 | u32 l; |
431 | int elements = 0; | |
432 | int word_len, element_count; | |
433 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
434 | mcspi = spi_master_get_devdata(spi->master); | |
435 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
436 | count = xfer->len; | |
d33f473d IS |
437 | dma_count = xfer->len; |
438 | ||
439 | if (mcspi->fifo_depth == 0) | |
440 | dma_count -= es; | |
441 | ||
d7b4394e S |
442 | word_len = cs->word_len; |
443 | l = mcspi_cached_chconf0(spi); | |
53741ed8 | 444 | |
d7b4394e S |
445 | if (word_len <= 8) |
446 | element_count = count; | |
447 | else if (word_len <= 16) | |
448 | element_count = count >> 1; | |
449 | else /* word_len <= 32 */ | |
450 | element_count = count >> 2; | |
451 | ||
452 | if (mcspi_dma->dma_rx) { | |
53741ed8 RK |
453 | struct dma_async_tx_descriptor *tx; |
454 | struct scatterlist sg; | |
53741ed8 RK |
455 | |
456 | dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); | |
457 | ||
d33f473d IS |
458 | if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) |
459 | dma_count -= es; | |
53741ed8 RK |
460 | |
461 | sg_init_table(&sg, 1); | |
462 | sg_dma_address(&sg) = xfer->rx_dma; | |
d33f473d | 463 | sg_dma_len(&sg) = dma_count; |
53741ed8 RK |
464 | |
465 | tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1, | |
d7b4394e S |
466 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | |
467 | DMA_CTRL_ACK); | |
53741ed8 RK |
468 | if (tx) { |
469 | tx->callback = omap2_mcspi_rx_callback; | |
470 | tx->callback_param = spi; | |
471 | dmaengine_submit(tx); | |
472 | } else { | |
d7b4394e | 473 | /* FIXME: fall back to PIO? */ |
2764c500 | 474 | } |
ccdc7bf9 SO |
475 | } |
476 | ||
d7b4394e S |
477 | dma_async_issue_pending(mcspi_dma->dma_rx); |
478 | omap2_mcspi_set_dma_req(spi, 1, 1); | |
4743a0f8 | 479 | |
d7b4394e S |
480 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
481 | dma_unmap_single(mcspi->dev, xfer->rx_dma, count, | |
482 | DMA_FROM_DEVICE); | |
d33f473d IS |
483 | |
484 | if (mcspi->fifo_depth > 0) | |
485 | return count; | |
486 | ||
d7b4394e | 487 | omap2_mcspi_set_enable(spi, 0); |
53741ed8 | 488 | |
d7b4394e | 489 | elements = element_count - 1; |
4743a0f8 | 490 | |
d7b4394e S |
491 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
492 | elements--; | |
4743a0f8 | 493 | |
57c5c28d | 494 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
d7b4394e | 495 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
57c5c28d EN |
496 | u32 w; |
497 | ||
498 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
499 | if (word_len <= 8) | |
d7b4394e | 500 | ((u8 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 501 | else if (word_len <= 16) |
d7b4394e | 502 | ((u16 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 503 | else /* word_len <= 32 */ |
d7b4394e | 504 | ((u32 *)xfer->rx_buf)[elements++] = w; |
57c5c28d | 505 | } else { |
56cd5c15 | 506 | int bytes_per_word = mcspi_bytes_per_word(word_len); |
a1829d2b | 507 | dev_err(&spi->dev, "DMA RX penultimate word empty\n"); |
56cd5c15 | 508 | count -= (bytes_per_word << 1); |
d7b4394e S |
509 | omap2_mcspi_set_enable(spi, 1); |
510 | return count; | |
57c5c28d | 511 | } |
ccdc7bf9 | 512 | } |
d7b4394e S |
513 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
514 | & OMAP2_MCSPI_CHSTAT_RXS)) { | |
515 | u32 w; | |
516 | ||
517 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); | |
518 | if (word_len <= 8) | |
519 | ((u8 *)xfer->rx_buf)[elements] = w; | |
520 | else if (word_len <= 16) | |
521 | ((u16 *)xfer->rx_buf)[elements] = w; | |
522 | else /* word_len <= 32 */ | |
523 | ((u32 *)xfer->rx_buf)[elements] = w; | |
524 | } else { | |
a1829d2b | 525 | dev_err(&spi->dev, "DMA RX last word empty\n"); |
56cd5c15 | 526 | count -= mcspi_bytes_per_word(word_len); |
d7b4394e S |
527 | } |
528 | omap2_mcspi_set_enable(spi, 1); | |
529 | return count; | |
530 | } | |
531 | ||
532 | static unsigned | |
533 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) | |
534 | { | |
535 | struct omap2_mcspi *mcspi; | |
536 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
537 | struct omap2_mcspi_dma *mcspi_dma; | |
538 | unsigned int count; | |
539 | u32 l; | |
540 | u8 *rx; | |
541 | const u8 *tx; | |
542 | struct dma_slave_config cfg; | |
543 | enum dma_slave_buswidth width; | |
544 | unsigned es; | |
d33f473d | 545 | u32 burst; |
e47a682a | 546 | void __iomem *chstat_reg; |
d33f473d IS |
547 | void __iomem *irqstat_reg; |
548 | int wait_res; | |
d7b4394e S |
549 | |
550 | mcspi = spi_master_get_devdata(spi->master); | |
551 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
552 | l = mcspi_cached_chconf0(spi); | |
553 | ||
554 | ||
555 | if (cs->word_len <= 8) { | |
556 | width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
557 | es = 1; | |
558 | } else if (cs->word_len <= 16) { | |
559 | width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
560 | es = 2; | |
561 | } else { | |
562 | width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
563 | es = 4; | |
564 | } | |
565 | ||
d33f473d IS |
566 | count = xfer->len; |
567 | burst = 1; | |
568 | ||
569 | if (mcspi->fifo_depth > 0) { | |
570 | if (count > mcspi->fifo_depth) | |
571 | burst = mcspi->fifo_depth / es; | |
572 | else | |
573 | burst = count / es; | |
574 | } | |
575 | ||
d7b4394e S |
576 | memset(&cfg, 0, sizeof(cfg)); |
577 | cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; | |
578 | cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; | |
579 | cfg.src_addr_width = width; | |
580 | cfg.dst_addr_width = width; | |
d33f473d IS |
581 | cfg.src_maxburst = burst; |
582 | cfg.dst_maxburst = burst; | |
d7b4394e S |
583 | |
584 | rx = xfer->rx_buf; | |
585 | tx = xfer->tx_buf; | |
586 | ||
d7b4394e S |
587 | if (tx != NULL) |
588 | omap2_mcspi_tx_dma(spi, xfer, cfg); | |
589 | ||
590 | if (rx != NULL) | |
e47a682a S |
591 | count = omap2_mcspi_rx_dma(spi, xfer, cfg, es); |
592 | ||
593 | if (tx != NULL) { | |
e47a682a S |
594 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
595 | dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len, | |
596 | DMA_TO_DEVICE); | |
597 | ||
d33f473d IS |
598 | if (mcspi->fifo_depth > 0) { |
599 | irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; | |
600 | ||
601 | if (mcspi_wait_for_reg_bit(irqstat_reg, | |
602 | OMAP2_MCSPI_IRQSTATUS_EOW) < 0) | |
603 | dev_err(&spi->dev, "EOW timed out\n"); | |
604 | ||
605 | mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, | |
606 | OMAP2_MCSPI_IRQSTATUS_EOW); | |
607 | } | |
608 | ||
e47a682a S |
609 | /* for TX_ONLY mode, be sure all words have shifted out */ |
610 | if (rx == NULL) { | |
d33f473d IS |
611 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
612 | if (mcspi->fifo_depth > 0) { | |
613 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
614 | OMAP2_MCSPI_CHSTAT_TXFFE); | |
615 | if (wait_res < 0) | |
616 | dev_err(&spi->dev, "TXFFE timed out\n"); | |
617 | } else { | |
618 | wait_res = mcspi_wait_for_reg_bit(chstat_reg, | |
619 | OMAP2_MCSPI_CHSTAT_TXS); | |
620 | if (wait_res < 0) | |
621 | dev_err(&spi->dev, "TXS timed out\n"); | |
622 | } | |
623 | if (wait_res >= 0 && | |
624 | (mcspi_wait_for_reg_bit(chstat_reg, | |
625 | OMAP2_MCSPI_CHSTAT_EOT) < 0)) | |
e47a682a S |
626 | dev_err(&spi->dev, "EOT timed out\n"); |
627 | } | |
628 | } | |
ccdc7bf9 SO |
629 | return count; |
630 | } | |
631 | ||
ccdc7bf9 SO |
632 | static unsigned |
633 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) | |
634 | { | |
635 | struct omap2_mcspi *mcspi; | |
636 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
637 | unsigned int count, c; | |
638 | u32 l; | |
639 | void __iomem *base = cs->base; | |
640 | void __iomem *tx_reg; | |
641 | void __iomem *rx_reg; | |
642 | void __iomem *chstat_reg; | |
643 | int word_len; | |
644 | ||
645 | mcspi = spi_master_get_devdata(spi->master); | |
646 | count = xfer->len; | |
647 | c = count; | |
648 | word_len = cs->word_len; | |
649 | ||
a41ae1ad | 650 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
651 | |
652 | /* We store the pre-calculated register addresses on stack to speed | |
653 | * up the transfer loop. */ | |
654 | tx_reg = base + OMAP2_MCSPI_TX0; | |
655 | rx_reg = base + OMAP2_MCSPI_RX0; | |
656 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; | |
657 | ||
adef658d MJ |
658 | if (c < (word_len>>3)) |
659 | return 0; | |
660 | ||
ccdc7bf9 SO |
661 | if (word_len <= 8) { |
662 | u8 *rx; | |
663 | const u8 *tx; | |
664 | ||
665 | rx = xfer->rx_buf; | |
666 | tx = xfer->tx_buf; | |
667 | ||
668 | do { | |
feed9bab | 669 | c -= 1; |
ccdc7bf9 SO |
670 | if (tx != NULL) { |
671 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
672 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
673 | dev_err(&spi->dev, "TXS timed out\n"); | |
674 | goto out; | |
675 | } | |
079a176d | 676 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
ccdc7bf9 | 677 | word_len, *tx); |
ccdc7bf9 SO |
678 | __raw_writel(*tx++, tx_reg); |
679 | } | |
680 | if (rx != NULL) { | |
681 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
682 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
683 | dev_err(&spi->dev, "RXS timed out\n"); | |
684 | goto out; | |
685 | } | |
4743a0f8 RT |
686 | |
687 | if (c == 1 && tx == NULL && | |
688 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
689 | omap2_mcspi_set_enable(spi, 0); | |
690 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 691 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
4743a0f8 | 692 | word_len, *(rx - 1)); |
4743a0f8 RT |
693 | if (mcspi_wait_for_reg_bit(chstat_reg, |
694 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
695 | dev_err(&spi->dev, | |
696 | "RXS timed out\n"); | |
697 | goto out; | |
698 | } | |
699 | c = 0; | |
700 | } else if (c == 0 && tx == NULL) { | |
701 | omap2_mcspi_set_enable(spi, 0); | |
702 | } | |
703 | ||
ccdc7bf9 | 704 | *rx++ = __raw_readl(rx_reg); |
079a176d | 705 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
ccdc7bf9 | 706 | word_len, *(rx - 1)); |
ccdc7bf9 | 707 | } |
95c5c3ab | 708 | } while (c); |
ccdc7bf9 SO |
709 | } else if (word_len <= 16) { |
710 | u16 *rx; | |
711 | const u16 *tx; | |
712 | ||
713 | rx = xfer->rx_buf; | |
714 | tx = xfer->tx_buf; | |
715 | do { | |
feed9bab | 716 | c -= 2; |
ccdc7bf9 SO |
717 | if (tx != NULL) { |
718 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
719 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
720 | dev_err(&spi->dev, "TXS timed out\n"); | |
721 | goto out; | |
722 | } | |
079a176d | 723 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
ccdc7bf9 | 724 | word_len, *tx); |
ccdc7bf9 SO |
725 | __raw_writel(*tx++, tx_reg); |
726 | } | |
727 | if (rx != NULL) { | |
728 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
729 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
730 | dev_err(&spi->dev, "RXS timed out\n"); | |
731 | goto out; | |
732 | } | |
4743a0f8 RT |
733 | |
734 | if (c == 2 && tx == NULL && | |
735 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
736 | omap2_mcspi_set_enable(spi, 0); | |
737 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 738 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
4743a0f8 | 739 | word_len, *(rx - 1)); |
4743a0f8 RT |
740 | if (mcspi_wait_for_reg_bit(chstat_reg, |
741 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
742 | dev_err(&spi->dev, | |
743 | "RXS timed out\n"); | |
744 | goto out; | |
745 | } | |
746 | c = 0; | |
747 | } else if (c == 0 && tx == NULL) { | |
748 | omap2_mcspi_set_enable(spi, 0); | |
749 | } | |
750 | ||
ccdc7bf9 | 751 | *rx++ = __raw_readl(rx_reg); |
079a176d | 752 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
ccdc7bf9 | 753 | word_len, *(rx - 1)); |
ccdc7bf9 | 754 | } |
95c5c3ab | 755 | } while (c >= 2); |
ccdc7bf9 SO |
756 | } else if (word_len <= 32) { |
757 | u32 *rx; | |
758 | const u32 *tx; | |
759 | ||
760 | rx = xfer->rx_buf; | |
761 | tx = xfer->tx_buf; | |
762 | do { | |
feed9bab | 763 | c -= 4; |
ccdc7bf9 SO |
764 | if (tx != NULL) { |
765 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
766 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
767 | dev_err(&spi->dev, "TXS timed out\n"); | |
768 | goto out; | |
769 | } | |
079a176d | 770 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
ccdc7bf9 | 771 | word_len, *tx); |
ccdc7bf9 SO |
772 | __raw_writel(*tx++, tx_reg); |
773 | } | |
774 | if (rx != NULL) { | |
775 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
776 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
777 | dev_err(&spi->dev, "RXS timed out\n"); | |
778 | goto out; | |
779 | } | |
4743a0f8 RT |
780 | |
781 | if (c == 4 && tx == NULL && | |
782 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { | |
783 | omap2_mcspi_set_enable(spi, 0); | |
784 | *rx++ = __raw_readl(rx_reg); | |
079a176d | 785 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
4743a0f8 | 786 | word_len, *(rx - 1)); |
4743a0f8 RT |
787 | if (mcspi_wait_for_reg_bit(chstat_reg, |
788 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { | |
789 | dev_err(&spi->dev, | |
790 | "RXS timed out\n"); | |
791 | goto out; | |
792 | } | |
793 | c = 0; | |
794 | } else if (c == 0 && tx == NULL) { | |
795 | omap2_mcspi_set_enable(spi, 0); | |
796 | } | |
797 | ||
ccdc7bf9 | 798 | *rx++ = __raw_readl(rx_reg); |
079a176d | 799 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
ccdc7bf9 | 800 | word_len, *(rx - 1)); |
ccdc7bf9 | 801 | } |
95c5c3ab | 802 | } while (c >= 4); |
ccdc7bf9 SO |
803 | } |
804 | ||
805 | /* for TX_ONLY mode, be sure all words have shifted out */ | |
806 | if (xfer->rx_buf == NULL) { | |
807 | if (mcspi_wait_for_reg_bit(chstat_reg, | |
808 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { | |
809 | dev_err(&spi->dev, "TXS timed out\n"); | |
810 | } else if (mcspi_wait_for_reg_bit(chstat_reg, | |
811 | OMAP2_MCSPI_CHSTAT_EOT) < 0) | |
812 | dev_err(&spi->dev, "EOT timed out\n"); | |
e1993ed6 JW |
813 | |
814 | /* disable chan to purge rx datas received in TX_ONLY transfer, | |
815 | * otherwise these rx datas will affect the direct following | |
816 | * RX_ONLY transfer. | |
817 | */ | |
818 | omap2_mcspi_set_enable(spi, 0); | |
ccdc7bf9 SO |
819 | } |
820 | out: | |
4743a0f8 | 821 | omap2_mcspi_set_enable(spi, 1); |
ccdc7bf9 SO |
822 | return count - c; |
823 | } | |
824 | ||
57d9c10d HH |
825 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
826 | { | |
827 | u32 div; | |
828 | ||
829 | for (div = 0; div < 15; div++) | |
830 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) | |
831 | return div; | |
832 | ||
833 | return 15; | |
834 | } | |
835 | ||
ccdc7bf9 SO |
836 | /* called only when no transfer is active to this device */ |
837 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, | |
838 | struct spi_transfer *t) | |
839 | { | |
840 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
841 | struct omap2_mcspi *mcspi; | |
a41ae1ad | 842 | struct spi_master *spi_cntrl; |
ccdc7bf9 SO |
843 | u32 l = 0, div = 0; |
844 | u8 word_len = spi->bits_per_word; | |
9bd4517d | 845 | u32 speed_hz = spi->max_speed_hz; |
ccdc7bf9 SO |
846 | |
847 | mcspi = spi_master_get_devdata(spi->master); | |
a41ae1ad | 848 | spi_cntrl = mcspi->master; |
ccdc7bf9 SO |
849 | |
850 | if (t != NULL && t->bits_per_word) | |
851 | word_len = t->bits_per_word; | |
852 | ||
853 | cs->word_len = word_len; | |
854 | ||
9bd4517d SE |
855 | if (t && t->speed_hz) |
856 | speed_hz = t->speed_hz; | |
857 | ||
57d9c10d HH |
858 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
859 | div = omap2_mcspi_calc_divisor(speed_hz); | |
ccdc7bf9 | 860 | |
a41ae1ad | 861 | l = mcspi_cached_chconf0(spi); |
ccdc7bf9 SO |
862 | |
863 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS | |
864 | * REVISIT: this controller could support SPI_3WIRE mode. | |
865 | */ | |
2cd45179 | 866 | if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { |
0384e90b DM |
867 | l &= ~OMAP2_MCSPI_CHCONF_IS; |
868 | l &= ~OMAP2_MCSPI_CHCONF_DPE1; | |
869 | l |= OMAP2_MCSPI_CHCONF_DPE0; | |
870 | } else { | |
871 | l |= OMAP2_MCSPI_CHCONF_IS; | |
872 | l |= OMAP2_MCSPI_CHCONF_DPE1; | |
873 | l &= ~OMAP2_MCSPI_CHCONF_DPE0; | |
874 | } | |
ccdc7bf9 SO |
875 | |
876 | /* wordlength */ | |
877 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; | |
878 | l |= (word_len - 1) << 7; | |
879 | ||
880 | /* set chipselect polarity; manage with FORCE */ | |
881 | if (!(spi->mode & SPI_CS_HIGH)) | |
882 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ | |
883 | else | |
884 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; | |
885 | ||
886 | /* set clock divisor */ | |
887 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; | |
888 | l |= div << 2; | |
889 | ||
890 | /* set SPI mode 0..3 */ | |
891 | if (spi->mode & SPI_CPOL) | |
892 | l |= OMAP2_MCSPI_CHCONF_POL; | |
893 | else | |
894 | l &= ~OMAP2_MCSPI_CHCONF_POL; | |
895 | if (spi->mode & SPI_CPHA) | |
896 | l |= OMAP2_MCSPI_CHCONF_PHA; | |
897 | else | |
898 | l &= ~OMAP2_MCSPI_CHCONF_PHA; | |
899 | ||
a41ae1ad | 900 | mcspi_write_chconf0(spi, l); |
ccdc7bf9 SO |
901 | |
902 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", | |
57d9c10d | 903 | OMAP2_MCSPI_MAX_FREQ >> div, |
ccdc7bf9 SO |
904 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
905 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); | |
906 | ||
907 | return 0; | |
908 | } | |
909 | ||
ddc5cdf1 TL |
910 | /* |
911 | * Note that we currently allow DMA only if we get a channel | |
912 | * for both rx and tx. Otherwise we'll do PIO for both rx and tx. | |
913 | */ | |
ccdc7bf9 SO |
914 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
915 | { | |
916 | struct spi_master *master = spi->master; | |
917 | struct omap2_mcspi *mcspi; | |
918 | struct omap2_mcspi_dma *mcspi_dma; | |
53741ed8 RK |
919 | dma_cap_mask_t mask; |
920 | unsigned sig; | |
ccdc7bf9 SO |
921 | |
922 | mcspi = spi_master_get_devdata(master); | |
923 | mcspi_dma = mcspi->dma_channels + spi->chip_select; | |
924 | ||
53741ed8 RK |
925 | init_completion(&mcspi_dma->dma_rx_completion); |
926 | init_completion(&mcspi_dma->dma_tx_completion); | |
927 | ||
928 | dma_cap_zero(mask); | |
929 | dma_cap_set(DMA_SLAVE, mask); | |
53741ed8 | 930 | sig = mcspi_dma->dma_rx_sync_dev; |
74f3aaad MP |
931 | |
932 | mcspi_dma->dma_rx = | |
933 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
934 | &sig, &master->dev, | |
935 | mcspi_dma->dma_rx_ch_name); | |
ddc5cdf1 TL |
936 | if (!mcspi_dma->dma_rx) |
937 | goto no_dma; | |
ccdc7bf9 | 938 | |
53741ed8 | 939 | sig = mcspi_dma->dma_tx_sync_dev; |
74f3aaad MP |
940 | mcspi_dma->dma_tx = |
941 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
942 | &sig, &master->dev, | |
943 | mcspi_dma->dma_tx_ch_name); | |
944 | ||
53741ed8 | 945 | if (!mcspi_dma->dma_tx) { |
53741ed8 RK |
946 | dma_release_channel(mcspi_dma->dma_rx); |
947 | mcspi_dma->dma_rx = NULL; | |
ddc5cdf1 | 948 | goto no_dma; |
ccdc7bf9 SO |
949 | } |
950 | ||
ccdc7bf9 | 951 | return 0; |
ddc5cdf1 TL |
952 | |
953 | no_dma: | |
954 | dev_warn(&spi->dev, "not using DMA for McSPI\n"); | |
955 | return -EAGAIN; | |
ccdc7bf9 SO |
956 | } |
957 | ||
ccdc7bf9 SO |
958 | static int omap2_mcspi_setup(struct spi_device *spi) |
959 | { | |
960 | int ret; | |
1bd897f8 BC |
961 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
962 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; | |
ccdc7bf9 SO |
963 | struct omap2_mcspi_dma *mcspi_dma; |
964 | struct omap2_mcspi_cs *cs = spi->controller_state; | |
965 | ||
ccdc7bf9 SO |
966 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
967 | ||
968 | if (!cs) { | |
10aa5a35 | 969 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
ccdc7bf9 SO |
970 | if (!cs) |
971 | return -ENOMEM; | |
972 | cs->base = mcspi->base + spi->chip_select * 0x14; | |
e5480b73 | 973 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
a41ae1ad | 974 | cs->chconf0 = 0; |
ccdc7bf9 | 975 | spi->controller_state = cs; |
89c05372 | 976 | /* Link this to context save list */ |
1bd897f8 | 977 | list_add_tail(&cs->node, &ctx->cs); |
ccdc7bf9 SO |
978 | } |
979 | ||
8c7494a5 | 980 | if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) { |
ccdc7bf9 | 981 | ret = omap2_mcspi_request_dma(spi); |
ddc5cdf1 | 982 | if (ret < 0 && ret != -EAGAIN) |
ccdc7bf9 SO |
983 | return ret; |
984 | } | |
985 | ||
034d3dc9 | 986 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
987 | if (ret < 0) |
988 | return ret; | |
a41ae1ad | 989 | |
86eeb6fe | 990 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
034d3dc9 S |
991 | pm_runtime_mark_last_busy(mcspi->dev); |
992 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
993 | |
994 | return ret; | |
995 | } | |
996 | ||
997 | static void omap2_mcspi_cleanup(struct spi_device *spi) | |
998 | { | |
999 | struct omap2_mcspi *mcspi; | |
1000 | struct omap2_mcspi_dma *mcspi_dma; | |
89c05372 | 1001 | struct omap2_mcspi_cs *cs; |
ccdc7bf9 SO |
1002 | |
1003 | mcspi = spi_master_get_devdata(spi->master); | |
ccdc7bf9 | 1004 | |
5e774943 SE |
1005 | if (spi->controller_state) { |
1006 | /* Unlink controller state from context save list */ | |
1007 | cs = spi->controller_state; | |
1008 | list_del(&cs->node); | |
89c05372 | 1009 | |
10aa5a35 | 1010 | kfree(cs); |
5e774943 | 1011 | } |
ccdc7bf9 | 1012 | |
99f1a43f SE |
1013 | if (spi->chip_select < spi->master->num_chipselect) { |
1014 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; | |
1015 | ||
53741ed8 RK |
1016 | if (mcspi_dma->dma_rx) { |
1017 | dma_release_channel(mcspi_dma->dma_rx); | |
1018 | mcspi_dma->dma_rx = NULL; | |
99f1a43f | 1019 | } |
53741ed8 RK |
1020 | if (mcspi_dma->dma_tx) { |
1021 | dma_release_channel(mcspi_dma->dma_tx); | |
1022 | mcspi_dma->dma_tx = NULL; | |
99f1a43f | 1023 | } |
ccdc7bf9 SO |
1024 | } |
1025 | } | |
1026 | ||
5fda88f5 | 1027 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
ccdc7bf9 | 1028 | { |
ccdc7bf9 SO |
1029 | |
1030 | /* We only enable one channel at a time -- the one whose message is | |
5fda88f5 | 1031 | * -- although this controller would gladly |
ccdc7bf9 SO |
1032 | * arbitrate among multiple channels. This corresponds to "single |
1033 | * channel" master mode. As a side effect, we need to manage the | |
1034 | * chipselect with the FORCE bit ... CS != channel enable. | |
1035 | */ | |
ccdc7bf9 | 1036 | |
5fda88f5 S |
1037 | struct spi_device *spi; |
1038 | struct spi_transfer *t = NULL; | |
5cbc7ca9 | 1039 | struct spi_master *master; |
ddc5cdf1 | 1040 | struct omap2_mcspi_dma *mcspi_dma; |
5fda88f5 S |
1041 | int cs_active = 0; |
1042 | struct omap2_mcspi_cs *cs; | |
1043 | struct omap2_mcspi_device_config *cd; | |
1044 | int par_override = 0; | |
1045 | int status = 0; | |
1046 | u32 chconf; | |
ccdc7bf9 | 1047 | |
5fda88f5 | 1048 | spi = m->spi; |
5cbc7ca9 | 1049 | master = spi->master; |
ddc5cdf1 | 1050 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
5fda88f5 S |
1051 | cs = spi->controller_state; |
1052 | cd = spi->controller_data; | |
ccdc7bf9 | 1053 | |
d33f473d | 1054 | omap2_mcspi_set_enable(spi, 0); |
5fda88f5 S |
1055 | list_for_each_entry(t, &m->transfers, transfer_list) { |
1056 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { | |
1057 | status = -EINVAL; | |
1058 | break; | |
1059 | } | |
1060 | if (par_override || t->speed_hz || t->bits_per_word) { | |
1061 | par_override = 1; | |
1062 | status = omap2_mcspi_setup_transfer(spi, t); | |
1063 | if (status < 0) | |
1064 | break; | |
1065 | if (!t->speed_hz && !t->bits_per_word) | |
1066 | par_override = 0; | |
1067 | } | |
5cbc7ca9 MB |
1068 | if (cd && cd->cs_per_word) { |
1069 | chconf = mcspi->ctx.modulctrl; | |
1070 | chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1071 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1072 | mcspi->ctx.modulctrl = | |
1073 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1074 | } | |
1075 | ||
4743a0f8 | 1076 | |
5fda88f5 S |
1077 | if (!cs_active) { |
1078 | omap2_mcspi_force_cs(spi, 1); | |
1079 | cs_active = 1; | |
1080 | } | |
4743a0f8 | 1081 | |
5fda88f5 S |
1082 | chconf = mcspi_cached_chconf0(spi); |
1083 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; | |
1084 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; | |
ccdc7bf9 | 1085 | |
5fda88f5 S |
1086 | if (t->tx_buf == NULL) |
1087 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; | |
1088 | else if (t->rx_buf == NULL) | |
1089 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; | |
ccdc7bf9 | 1090 | |
5fda88f5 S |
1091 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
1092 | /* Turbo mode is for more than one word */ | |
1093 | if (t->len > ((cs->word_len + 7) >> 3)) | |
1094 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; | |
1095 | } | |
ccdc7bf9 | 1096 | |
5fda88f5 | 1097 | mcspi_write_chconf0(spi, chconf); |
ccdc7bf9 | 1098 | |
5fda88f5 S |
1099 | if (t->len) { |
1100 | unsigned count; | |
1101 | ||
d33f473d IS |
1102 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1103 | (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) | |
1104 | omap2_mcspi_set_fifo(spi, t, 1); | |
1105 | ||
1106 | omap2_mcspi_set_enable(spi, 1); | |
1107 | ||
5fda88f5 S |
1108 | /* RX_ONLY mode needs dummy data in TX reg */ |
1109 | if (t->tx_buf == NULL) | |
1110 | __raw_writel(0, cs->base | |
1111 | + OMAP2_MCSPI_TX0); | |
ccdc7bf9 | 1112 | |
ddc5cdf1 TL |
1113 | if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && |
1114 | (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) | |
5fda88f5 S |
1115 | count = omap2_mcspi_txrx_dma(spi, t); |
1116 | else | |
1117 | count = omap2_mcspi_txrx_pio(spi, t); | |
1118 | m->actual_length += count; | |
ccdc7bf9 | 1119 | |
5fda88f5 S |
1120 | if (count != t->len) { |
1121 | status = -EIO; | |
1122 | break; | |
ccdc7bf9 SO |
1123 | } |
1124 | } | |
1125 | ||
5fda88f5 S |
1126 | if (t->delay_usecs) |
1127 | udelay(t->delay_usecs); | |
ccdc7bf9 | 1128 | |
5fda88f5 S |
1129 | /* ignore the "leave it on after last xfer" hint */ |
1130 | if (t->cs_change) { | |
ccdc7bf9 | 1131 | omap2_mcspi_force_cs(spi, 0); |
5fda88f5 S |
1132 | cs_active = 0; |
1133 | } | |
d33f473d IS |
1134 | |
1135 | omap2_mcspi_set_enable(spi, 0); | |
1136 | ||
1137 | if (mcspi->fifo_depth > 0) | |
1138 | omap2_mcspi_set_fifo(spi, t, 0); | |
5fda88f5 S |
1139 | } |
1140 | /* Restore defaults if they were overriden */ | |
1141 | if (par_override) { | |
1142 | par_override = 0; | |
1143 | status = omap2_mcspi_setup_transfer(spi, NULL); | |
1144 | } | |
ccdc7bf9 | 1145 | |
5fda88f5 S |
1146 | if (cs_active) |
1147 | omap2_mcspi_force_cs(spi, 0); | |
ccdc7bf9 | 1148 | |
5cbc7ca9 MB |
1149 | if (cd && cd->cs_per_word) { |
1150 | chconf = mcspi->ctx.modulctrl; | |
1151 | chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; | |
1152 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf); | |
1153 | mcspi->ctx.modulctrl = | |
1154 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); | |
1155 | } | |
1156 | ||
5fda88f5 | 1157 | omap2_mcspi_set_enable(spi, 0); |
ccdc7bf9 | 1158 | |
d33f473d IS |
1159 | if (mcspi->fifo_depth > 0 && t) |
1160 | omap2_mcspi_set_fifo(spi, t, 0); | |
1f1a4384 | 1161 | |
d33f473d | 1162 | m->status = status; |
ccdc7bf9 SO |
1163 | } |
1164 | ||
5fda88f5 | 1165 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
18dd6199 | 1166 | struct spi_message *m) |
ccdc7bf9 | 1167 | { |
ddc5cdf1 | 1168 | struct spi_device *spi; |
ccdc7bf9 | 1169 | struct omap2_mcspi *mcspi; |
ddc5cdf1 | 1170 | struct omap2_mcspi_dma *mcspi_dma; |
ccdc7bf9 SO |
1171 | struct spi_transfer *t; |
1172 | ||
ddc5cdf1 | 1173 | spi = m->spi; |
5fda88f5 | 1174 | mcspi = spi_master_get_devdata(master); |
ddc5cdf1 | 1175 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
ccdc7bf9 SO |
1176 | m->actual_length = 0; |
1177 | m->status = 0; | |
1178 | ||
1179 | /* reject invalid messages and transfers */ | |
5fda88f5 | 1180 | if (list_empty(&m->transfers)) |
ccdc7bf9 SO |
1181 | return -EINVAL; |
1182 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
1183 | const void *tx_buf = t->tx_buf; | |
1184 | void *rx_buf = t->rx_buf; | |
1185 | unsigned len = t->len; | |
1186 | ||
1187 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ | |
24778be2 | 1188 | || (len && !(rx_buf || tx_buf))) { |
5fda88f5 | 1189 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
ccdc7bf9 SO |
1190 | t->speed_hz, |
1191 | len, | |
1192 | tx_buf ? "tx" : "", | |
1193 | rx_buf ? "rx" : "", | |
1194 | t->bits_per_word); | |
1195 | return -EINVAL; | |
1196 | } | |
57d9c10d | 1197 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
5fda88f5 | 1198 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", |
18dd6199 MB |
1199 | t->speed_hz, |
1200 | OMAP2_MCSPI_MAX_FREQ >> 15); | |
ccdc7bf9 SO |
1201 | return -EINVAL; |
1202 | } | |
1203 | ||
1204 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) | |
1205 | continue; | |
1206 | ||
ddc5cdf1 | 1207 | if (mcspi_dma->dma_tx && tx_buf != NULL) { |
5fda88f5 | 1208 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
ccdc7bf9 | 1209 | len, DMA_TO_DEVICE); |
5fda88f5 S |
1210 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
1211 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1212 | 'T', len); |
1213 | return -EINVAL; | |
1214 | } | |
1215 | } | |
ddc5cdf1 | 1216 | if (mcspi_dma->dma_rx && rx_buf != NULL) { |
5fda88f5 | 1217 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
ccdc7bf9 | 1218 | DMA_FROM_DEVICE); |
5fda88f5 S |
1219 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
1220 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", | |
ccdc7bf9 SO |
1221 | 'R', len); |
1222 | if (tx_buf != NULL) | |
5fda88f5 | 1223 | dma_unmap_single(mcspi->dev, t->tx_dma, |
ccdc7bf9 SO |
1224 | len, DMA_TO_DEVICE); |
1225 | return -EINVAL; | |
1226 | } | |
1227 | } | |
1228 | } | |
1229 | ||
5fda88f5 S |
1230 | omap2_mcspi_work(mcspi, m); |
1231 | spi_finalize_current_message(master); | |
ccdc7bf9 SO |
1232 | return 0; |
1233 | } | |
1234 | ||
fd4a319b | 1235 | static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
ccdc7bf9 SO |
1236 | { |
1237 | struct spi_master *master = mcspi->master; | |
1bd897f8 | 1238 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1bd897f8 | 1239 | int ret = 0; |
ccdc7bf9 | 1240 | |
034d3dc9 | 1241 | ret = pm_runtime_get_sync(mcspi->dev); |
1f1a4384 G |
1242 | if (ret < 0) |
1243 | return ret; | |
ddb22195 | 1244 | |
39f8052d | 1245 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
18dd6199 | 1246 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
39f8052d | 1247 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
ccdc7bf9 SO |
1248 | |
1249 | omap2_mcspi_set_master_mode(master); | |
034d3dc9 S |
1250 | pm_runtime_mark_last_busy(mcspi->dev); |
1251 | pm_runtime_put_autosuspend(mcspi->dev); | |
ccdc7bf9 SO |
1252 | return 0; |
1253 | } | |
1254 | ||
1f1a4384 G |
1255 | static int omap_mcspi_runtime_resume(struct device *dev) |
1256 | { | |
1257 | struct omap2_mcspi *mcspi; | |
1258 | struct spi_master *master; | |
1259 | ||
1260 | master = dev_get_drvdata(dev); | |
1261 | mcspi = spi_master_get_devdata(master); | |
1262 | omap2_mcspi_restore_ctx(mcspi); | |
1263 | ||
1264 | return 0; | |
1265 | } | |
1266 | ||
d5a80031 BC |
1267 | static struct omap2_mcspi_platform_config omap2_pdata = { |
1268 | .regs_offset = 0, | |
1269 | }; | |
1270 | ||
1271 | static struct omap2_mcspi_platform_config omap4_pdata = { | |
1272 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, | |
1273 | }; | |
1274 | ||
1275 | static const struct of_device_id omap_mcspi_of_match[] = { | |
1276 | { | |
1277 | .compatible = "ti,omap2-mcspi", | |
1278 | .data = &omap2_pdata, | |
1279 | }, | |
1280 | { | |
1281 | .compatible = "ti,omap4-mcspi", | |
1282 | .data = &omap4_pdata, | |
1283 | }, | |
1284 | { }, | |
1285 | }; | |
1286 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); | |
ccc7baed | 1287 | |
fd4a319b | 1288 | static int omap2_mcspi_probe(struct platform_device *pdev) |
ccdc7bf9 SO |
1289 | { |
1290 | struct spi_master *master; | |
83a01e72 | 1291 | const struct omap2_mcspi_platform_config *pdata; |
ccdc7bf9 SO |
1292 | struct omap2_mcspi *mcspi; |
1293 | struct resource *r; | |
1294 | int status = 0, i; | |
d5a80031 BC |
1295 | u32 regs_offset = 0; |
1296 | static int bus_num = 1; | |
1297 | struct device_node *node = pdev->dev.of_node; | |
1298 | const struct of_device_id *match; | |
ccdc7bf9 SO |
1299 | |
1300 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); | |
1301 | if (master == NULL) { | |
1302 | dev_dbg(&pdev->dev, "master allocation failed\n"); | |
1303 | return -ENOMEM; | |
1304 | } | |
1305 | ||
e7db06b5 DB |
1306 | /* the spi->mode bits understood by this driver: */ |
1307 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
24778be2 | 1308 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
ccdc7bf9 | 1309 | master->setup = omap2_mcspi_setup; |
f0278a1a | 1310 | master->auto_runtime_pm = true; |
5fda88f5 | 1311 | master->transfer_one_message = omap2_mcspi_transfer_one_message; |
ccdc7bf9 | 1312 | master->cleanup = omap2_mcspi_cleanup; |
d5a80031 BC |
1313 | master->dev.of_node = node; |
1314 | ||
24b5a82c | 1315 | platform_set_drvdata(pdev, master); |
0384e90b DM |
1316 | |
1317 | mcspi = spi_master_get_devdata(master); | |
1318 | mcspi->master = master; | |
1319 | ||
d5a80031 BC |
1320 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
1321 | if (match) { | |
1322 | u32 num_cs = 1; /* default number of chipselect */ | |
1323 | pdata = match->data; | |
1324 | ||
1325 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); | |
1326 | master->num_chipselect = num_cs; | |
1327 | master->bus_num = bus_num++; | |
2cd45179 DM |
1328 | if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) |
1329 | mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; | |
d5a80031 | 1330 | } else { |
8074cf06 | 1331 | pdata = dev_get_platdata(&pdev->dev); |
d5a80031 BC |
1332 | master->num_chipselect = pdata->num_cs; |
1333 | if (pdev->id != -1) | |
1334 | master->bus_num = pdev->id; | |
0384e90b | 1335 | mcspi->pin_dir = pdata->pin_dir; |
d5a80031 BC |
1336 | } |
1337 | regs_offset = pdata->regs_offset; | |
ccdc7bf9 | 1338 | |
ccdc7bf9 SO |
1339 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1340 | if (r == NULL) { | |
1341 | status = -ENODEV; | |
39f1b565 | 1342 | goto free_master; |
ccdc7bf9 | 1343 | } |
1458d160 | 1344 | |
d5a80031 BC |
1345 | r->start += regs_offset; |
1346 | r->end += regs_offset; | |
1458d160 | 1347 | mcspi->phys = r->start; |
ccdc7bf9 | 1348 | |
b0ee5605 TR |
1349 | mcspi->base = devm_ioremap_resource(&pdev->dev, r); |
1350 | if (IS_ERR(mcspi->base)) { | |
1351 | status = PTR_ERR(mcspi->base); | |
1a77b127 | 1352 | goto free_master; |
55c381e4 | 1353 | } |
ccdc7bf9 | 1354 | |
1f1a4384 | 1355 | mcspi->dev = &pdev->dev; |
ccdc7bf9 | 1356 | |
1bd897f8 | 1357 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
ccdc7bf9 | 1358 | |
ccdc7bf9 SO |
1359 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
1360 | sizeof(struct omap2_mcspi_dma), | |
1361 | GFP_KERNEL); | |
1362 | ||
1363 | if (mcspi->dma_channels == NULL) | |
1a77b127 | 1364 | goto free_master; |
ccdc7bf9 | 1365 | |
1a5d8190 | 1366 | for (i = 0; i < master->num_chipselect; i++) { |
74f3aaad MP |
1367 | char *dma_rx_ch_name = mcspi->dma_channels[i].dma_rx_ch_name; |
1368 | char *dma_tx_ch_name = mcspi->dma_channels[i].dma_tx_ch_name; | |
1a5d8190 C |
1369 | struct resource *dma_res; |
1370 | ||
74f3aaad MP |
1371 | sprintf(dma_rx_ch_name, "rx%d", i); |
1372 | if (!pdev->dev.of_node) { | |
1373 | dma_res = | |
1374 | platform_get_resource_byname(pdev, | |
1375 | IORESOURCE_DMA, | |
1376 | dma_rx_ch_name); | |
1377 | if (!dma_res) { | |
1378 | dev_dbg(&pdev->dev, | |
1379 | "cannot get DMA RX channel\n"); | |
1380 | status = -ENODEV; | |
1381 | break; | |
1382 | } | |
1a5d8190 | 1383 | |
74f3aaad MP |
1384 | mcspi->dma_channels[i].dma_rx_sync_dev = |
1385 | dma_res->start; | |
1a5d8190 | 1386 | } |
74f3aaad MP |
1387 | sprintf(dma_tx_ch_name, "tx%d", i); |
1388 | if (!pdev->dev.of_node) { | |
1389 | dma_res = | |
1390 | platform_get_resource_byname(pdev, | |
1391 | IORESOURCE_DMA, | |
1392 | dma_tx_ch_name); | |
1393 | if (!dma_res) { | |
1394 | dev_dbg(&pdev->dev, | |
1395 | "cannot get DMA TX channel\n"); | |
1396 | status = -ENODEV; | |
1397 | break; | |
1398 | } | |
1a5d8190 | 1399 | |
74f3aaad MP |
1400 | mcspi->dma_channels[i].dma_tx_sync_dev = |
1401 | dma_res->start; | |
1402 | } | |
ccdc7bf9 SO |
1403 | } |
1404 | ||
39f1b565 S |
1405 | if (status < 0) |
1406 | goto dma_chnl_free; | |
1407 | ||
27b5284c S |
1408 | pm_runtime_use_autosuspend(&pdev->dev); |
1409 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); | |
1f1a4384 G |
1410 | pm_runtime_enable(&pdev->dev); |
1411 | ||
142e07be WY |
1412 | status = omap2_mcspi_master_setup(mcspi); |
1413 | if (status < 0) | |
39f1b565 | 1414 | goto disable_pm; |
ccdc7bf9 | 1415 | |
b95e02b7 | 1416 | status = devm_spi_register_master(&pdev->dev, master); |
ccdc7bf9 | 1417 | if (status < 0) |
37a2d84a | 1418 | goto disable_pm; |
ccdc7bf9 SO |
1419 | |
1420 | return status; | |
1421 | ||
39f1b565 | 1422 | disable_pm: |
751c925c | 1423 | pm_runtime_disable(&pdev->dev); |
39f1b565 | 1424 | dma_chnl_free: |
1f1a4384 | 1425 | kfree(mcspi->dma_channels); |
39f1b565 | 1426 | free_master: |
37a2d84a | 1427 | spi_master_put(master); |
ccdc7bf9 SO |
1428 | return status; |
1429 | } | |
1430 | ||
fd4a319b | 1431 | static int omap2_mcspi_remove(struct platform_device *pdev) |
ccdc7bf9 SO |
1432 | { |
1433 | struct spi_master *master; | |
1434 | struct omap2_mcspi *mcspi; | |
1435 | struct omap2_mcspi_dma *dma_channels; | |
ccdc7bf9 | 1436 | |
24b5a82c | 1437 | master = platform_get_drvdata(pdev); |
ccdc7bf9 SO |
1438 | mcspi = spi_master_get_devdata(master); |
1439 | dma_channels = mcspi->dma_channels; | |
1440 | ||
a93a2029 | 1441 | pm_runtime_put_sync(mcspi->dev); |
751c925c | 1442 | pm_runtime_disable(&pdev->dev); |
ccdc7bf9 | 1443 | |
ccdc7bf9 SO |
1444 | kfree(dma_channels); |
1445 | ||
1446 | return 0; | |
1447 | } | |
1448 | ||
7e38c3c4 KS |
1449 | /* work with hotplug and coldplug */ |
1450 | MODULE_ALIAS("platform:omap2_mcspi"); | |
1451 | ||
42ce7fd6 GC |
1452 | #ifdef CONFIG_SUSPEND |
1453 | /* | |
1454 | * When SPI wake up from off-mode, CS is in activate state. If it was in | |
1455 | * unactive state when driver was suspend, then force it to unactive state at | |
1456 | * wake up. | |
1457 | */ | |
1458 | static int omap2_mcspi_resume(struct device *dev) | |
1459 | { | |
1460 | struct spi_master *master = dev_get_drvdata(dev); | |
1461 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); | |
1bd897f8 BC |
1462 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
1463 | struct omap2_mcspi_cs *cs; | |
42ce7fd6 | 1464 | |
034d3dc9 | 1465 | pm_runtime_get_sync(mcspi->dev); |
1bd897f8 | 1466 | list_for_each_entry(cs, &ctx->cs, node) { |
42ce7fd6 | 1467 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
42ce7fd6 GC |
1468 | /* |
1469 | * We need to toggle CS state for OMAP take this | |
1470 | * change in account. | |
1471 | */ | |
af4e944d | 1472 | cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; |
42ce7fd6 | 1473 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
af4e944d | 1474 | cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; |
42ce7fd6 GC |
1475 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
1476 | } | |
1477 | } | |
034d3dc9 S |
1478 | pm_runtime_mark_last_busy(mcspi->dev); |
1479 | pm_runtime_put_autosuspend(mcspi->dev); | |
42ce7fd6 GC |
1480 | return 0; |
1481 | } | |
1482 | #else | |
1483 | #define omap2_mcspi_resume NULL | |
1484 | #endif | |
1485 | ||
1486 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { | |
1487 | .resume = omap2_mcspi_resume, | |
1f1a4384 | 1488 | .runtime_resume = omap_mcspi_runtime_resume, |
42ce7fd6 GC |
1489 | }; |
1490 | ||
ccdc7bf9 SO |
1491 | static struct platform_driver omap2_mcspi_driver = { |
1492 | .driver = { | |
1493 | .name = "omap2_mcspi", | |
1494 | .owner = THIS_MODULE, | |
d5a80031 BC |
1495 | .pm = &omap2_mcspi_pm_ops, |
1496 | .of_match_table = omap_mcspi_of_match, | |
ccdc7bf9 | 1497 | }, |
7d6b6d83 | 1498 | .probe = omap2_mcspi_probe, |
fd4a319b | 1499 | .remove = omap2_mcspi_remove, |
ccdc7bf9 SO |
1500 | }; |
1501 | ||
9fdca9df | 1502 | module_platform_driver(omap2_mcspi_driver); |
ccdc7bf9 | 1503 | MODULE_LICENSE("GPL"); |