Commit | Line | Data |
---|---|---|
a568231f LL |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Author: Leilk Liu <leilk.liu@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/ioport.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/of.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/platform_data/spi-mt65xx.h> | |
24 | #include <linux/pm_runtime.h> | |
25 | #include <linux/spi/spi.h> | |
26 | ||
27 | #define SPI_CFG0_REG 0x0000 | |
28 | #define SPI_CFG1_REG 0x0004 | |
29 | #define SPI_TX_SRC_REG 0x0008 | |
30 | #define SPI_RX_DST_REG 0x000c | |
31 | #define SPI_TX_DATA_REG 0x0010 | |
32 | #define SPI_RX_DATA_REG 0x0014 | |
33 | #define SPI_CMD_REG 0x0018 | |
34 | #define SPI_STATUS0_REG 0x001c | |
35 | #define SPI_PAD_SEL_REG 0x0024 | |
36 | ||
37 | #define SPI_CFG0_SCK_HIGH_OFFSET 0 | |
38 | #define SPI_CFG0_SCK_LOW_OFFSET 8 | |
39 | #define SPI_CFG0_CS_HOLD_OFFSET 16 | |
40 | #define SPI_CFG0_CS_SETUP_OFFSET 24 | |
41 | ||
42 | #define SPI_CFG1_CS_IDLE_OFFSET 0 | |
43 | #define SPI_CFG1_PACKET_LOOP_OFFSET 8 | |
44 | #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 | |
45 | #define SPI_CFG1_GET_TICK_DLY_OFFSET 30 | |
46 | ||
47 | #define SPI_CFG1_CS_IDLE_MASK 0xff | |
48 | #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 | |
49 | #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 | |
50 | ||
51 | #define SPI_CMD_ACT_OFFSET 0 | |
52 | #define SPI_CMD_RESUME_OFFSET 1 | |
53 | #define SPI_CMD_CPHA_OFFSET 8 | |
54 | #define SPI_CMD_CPOL_OFFSET 9 | |
55 | #define SPI_CMD_TXMSBF_OFFSET 12 | |
56 | #define SPI_CMD_RXMSBF_OFFSET 13 | |
57 | #define SPI_CMD_RX_ENDIAN_OFFSET 14 | |
58 | #define SPI_CMD_TX_ENDIAN_OFFSET 15 | |
59 | ||
60 | #define SPI_CMD_RST BIT(2) | |
61 | #define SPI_CMD_PAUSE_EN BIT(4) | |
62 | #define SPI_CMD_DEASSERT BIT(5) | |
63 | #define SPI_CMD_CPHA BIT(8) | |
64 | #define SPI_CMD_CPOL BIT(9) | |
65 | #define SPI_CMD_RX_DMA BIT(10) | |
66 | #define SPI_CMD_TX_DMA BIT(11) | |
67 | #define SPI_CMD_TXMSBF BIT(12) | |
68 | #define SPI_CMD_RXMSBF BIT(13) | |
69 | #define SPI_CMD_RX_ENDIAN BIT(14) | |
70 | #define SPI_CMD_TX_ENDIAN BIT(15) | |
71 | #define SPI_CMD_FINISH_IE BIT(16) | |
72 | #define SPI_CMD_PAUSE_IE BIT(17) | |
73 | ||
74 | #define MTK_SPI_QUIRK_PAD_SELECT 1 | |
75 | /* Must explicitly send dummy Tx bytes to do Rx only transfer */ | |
76 | #define MTK_SPI_QUIRK_MUST_TX 1 | |
77 | ||
78 | #define MT8173_SPI_MAX_PAD_SEL 3 | |
79 | ||
80 | #define MTK_SPI_IDLE 0 | |
81 | #define MTK_SPI_PAUSED 1 | |
82 | ||
83 | #define MTK_SPI_MAX_FIFO_SIZE 32 | |
84 | #define MTK_SPI_PACKET_SIZE 1024 | |
85 | ||
86 | struct mtk_spi_compatible { | |
87 | u32 need_pad_sel; | |
88 | u32 must_tx; | |
89 | }; | |
90 | ||
91 | struct mtk_spi { | |
92 | void __iomem *base; | |
93 | u32 state; | |
94 | u32 pad_sel; | |
95 | struct clk *spi_clk, *parent_clk; | |
96 | struct spi_transfer *cur_transfer; | |
97 | u32 xfer_len; | |
98 | struct scatterlist *tx_sgl, *rx_sgl; | |
99 | u32 tx_sgl_len, rx_sgl_len; | |
100 | const struct mtk_spi_compatible *dev_comp; | |
101 | }; | |
102 | ||
103 | static const struct mtk_spi_compatible mt6589_compat = { | |
104 | .need_pad_sel = 0, | |
105 | .must_tx = 0, | |
106 | }; | |
107 | ||
108 | static const struct mtk_spi_compatible mt8135_compat = { | |
109 | .need_pad_sel = 0, | |
110 | .must_tx = 0, | |
111 | }; | |
112 | ||
113 | static const struct mtk_spi_compatible mt8173_compat = { | |
114 | .need_pad_sel = MTK_SPI_QUIRK_PAD_SELECT, | |
115 | .must_tx = MTK_SPI_QUIRK_MUST_TX, | |
116 | }; | |
117 | ||
118 | /* | |
119 | * A piece of default chip info unless the platform | |
120 | * supplies it. | |
121 | */ | |
122 | static const struct mtk_chip_config mtk_default_chip_info = { | |
123 | .rx_mlsb = 1, | |
124 | .tx_mlsb = 1, | |
a568231f LL |
125 | }; |
126 | ||
127 | static const struct of_device_id mtk_spi_of_match[] = { | |
128 | { .compatible = "mediatek,mt6589-spi", .data = (void *)&mt6589_compat }, | |
129 | { .compatible = "mediatek,mt8135-spi", .data = (void *)&mt8135_compat }, | |
130 | { .compatible = "mediatek,mt8173-spi", .data = (void *)&mt8173_compat }, | |
131 | {} | |
132 | }; | |
133 | MODULE_DEVICE_TABLE(of, mtk_spi_of_match); | |
134 | ||
135 | static void mtk_spi_reset(struct mtk_spi *mdata) | |
136 | { | |
137 | u32 reg_val; | |
138 | ||
139 | /* set the software reset bit in SPI_CMD_REG. */ | |
140 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
141 | reg_val |= SPI_CMD_RST; | |
142 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
143 | ||
144 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
145 | reg_val &= ~SPI_CMD_RST; | |
146 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
147 | } | |
148 | ||
149 | static void mtk_spi_config(struct mtk_spi *mdata, | |
150 | struct mtk_chip_config *chip_config) | |
151 | { | |
152 | u32 reg_val; | |
153 | ||
154 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
155 | ||
156 | /* set the mlsbx and mlsbtx */ | |
157 | reg_val &= ~(SPI_CMD_TXMSBF | SPI_CMD_RXMSBF); | |
158 | reg_val |= (chip_config->tx_mlsb << SPI_CMD_TXMSBF_OFFSET); | |
159 | reg_val |= (chip_config->rx_mlsb << SPI_CMD_RXMSBF_OFFSET); | |
160 | ||
161 | /* set the tx/rx endian */ | |
44f636da LL |
162 | #ifdef __LITTLE_ENDIAN |
163 | reg_val &= ~SPI_CMD_TX_ENDIAN; | |
164 | reg_val &= ~SPI_CMD_RX_ENDIAN; | |
165 | #else | |
166 | reg_val |= SPI_CMD_TX_ENDIAN; | |
167 | reg_val |= SPI_CMD_RX_ENDIAN; | |
168 | #endif | |
a568231f LL |
169 | |
170 | /* set finish and pause interrupt always enable */ | |
171 | reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_EN; | |
172 | ||
173 | /* disable dma mode */ | |
174 | reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); | |
175 | ||
176 | /* disable deassert mode */ | |
177 | reg_val &= ~SPI_CMD_DEASSERT; | |
178 | ||
179 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
180 | ||
181 | /* pad select */ | |
182 | if (mdata->dev_comp->need_pad_sel) | |
183 | writel(mdata->pad_sel, mdata->base + SPI_PAD_SEL_REG); | |
184 | } | |
185 | ||
186 | static int mtk_spi_prepare_hardware(struct spi_master *master) | |
187 | { | |
188 | struct spi_transfer *trans; | |
189 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
190 | struct spi_message *msg = master->cur_msg; | |
a568231f LL |
191 | |
192 | trans = list_first_entry(&msg->transfers, struct spi_transfer, | |
193 | transfer_list); | |
194 | if (trans->cs_change == 0) { | |
195 | mdata->state = MTK_SPI_IDLE; | |
196 | mtk_spi_reset(mdata); | |
197 | } | |
198 | ||
a568231f LL |
199 | return 0; |
200 | } | |
201 | ||
202 | static int mtk_spi_prepare_message(struct spi_master *master, | |
203 | struct spi_message *msg) | |
204 | { | |
205 | u32 reg_val; | |
206 | u8 cpha, cpol; | |
207 | struct mtk_chip_config *chip_config; | |
208 | struct spi_device *spi = msg->spi; | |
209 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
210 | ||
211 | cpha = spi->mode & SPI_CPHA ? 1 : 0; | |
212 | cpol = spi->mode & SPI_CPOL ? 1 : 0; | |
213 | ||
214 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
215 | reg_val &= ~(SPI_CMD_CPHA | SPI_CMD_CPOL); | |
216 | reg_val |= (cpha << SPI_CMD_CPHA_OFFSET); | |
217 | reg_val |= (cpol << SPI_CMD_CPOL_OFFSET); | |
218 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
219 | ||
220 | chip_config = spi->controller_data; | |
221 | if (!chip_config) { | |
222 | chip_config = (void *)&mtk_default_chip_info; | |
223 | spi->controller_data = chip_config; | |
224 | } | |
225 | mtk_spi_config(mdata, chip_config); | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
230 | static void mtk_spi_set_cs(struct spi_device *spi, bool enable) | |
231 | { | |
232 | u32 reg_val; | |
233 | struct mtk_spi *mdata = spi_master_get_devdata(spi->master); | |
234 | ||
235 | reg_val = readl(mdata->base + SPI_CMD_REG); | |
236 | if (!enable) | |
237 | reg_val |= SPI_CMD_PAUSE_EN; | |
238 | else | |
239 | reg_val &= ~SPI_CMD_PAUSE_EN; | |
240 | writel(reg_val, mdata->base + SPI_CMD_REG); | |
241 | } | |
242 | ||
243 | static void mtk_spi_prepare_transfer(struct spi_master *master, | |
244 | struct spi_transfer *xfer) | |
245 | { | |
246 | u32 spi_clk_hz, div, high_time, low_time, holdtime, | |
247 | setuptime, cs_idletime, reg_val = 0; | |
248 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
249 | ||
250 | spi_clk_hz = clk_get_rate(mdata->spi_clk); | |
251 | if (xfer->speed_hz < spi_clk_hz / 2) | |
252 | div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz); | |
253 | else | |
254 | div = 1; | |
255 | ||
256 | high_time = (div + 1) / 2; | |
257 | low_time = (div + 1) / 2; | |
258 | holdtime = (div + 1) / 2 * 2; | |
259 | setuptime = (div + 1) / 2 * 2; | |
260 | cs_idletime = (div + 1) / 2 * 2; | |
261 | ||
262 | reg_val |= (((high_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); | |
263 | reg_val |= (((low_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); | |
264 | reg_val |= (((holdtime - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); | |
265 | reg_val |= (((setuptime - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); | |
266 | writel(reg_val, mdata->base + SPI_CFG0_REG); | |
267 | ||
268 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
269 | reg_val &= ~SPI_CFG1_CS_IDLE_MASK; | |
270 | reg_val |= (((cs_idletime - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); | |
271 | writel(reg_val, mdata->base + SPI_CFG1_REG); | |
272 | } | |
273 | ||
274 | static void mtk_spi_setup_packet(struct spi_master *master) | |
275 | { | |
276 | u32 packet_size, packet_loop, reg_val; | |
277 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
278 | ||
279 | packet_size = min_t(unsigned, mdata->xfer_len, MTK_SPI_PACKET_SIZE); | |
280 | packet_loop = mdata->xfer_len / packet_size; | |
281 | ||
282 | reg_val = readl(mdata->base + SPI_CFG1_REG); | |
283 | reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK + SPI_CFG1_PACKET_LOOP_MASK); | |
284 | reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; | |
285 | reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; | |
286 | writel(reg_val, mdata->base + SPI_CFG1_REG); | |
287 | } | |
288 | ||
289 | static void mtk_spi_enable_transfer(struct spi_master *master) | |
290 | { | |
291 | int cmd; | |
292 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
293 | ||
294 | cmd = readl(mdata->base + SPI_CMD_REG); | |
295 | if (mdata->state == MTK_SPI_IDLE) | |
296 | cmd |= 1 << SPI_CMD_ACT_OFFSET; | |
297 | else | |
298 | cmd |= 1 << SPI_CMD_RESUME_OFFSET; | |
299 | writel(cmd, mdata->base + SPI_CMD_REG); | |
300 | } | |
301 | ||
302 | static int mtk_spi_get_mult_delta(int xfer_len) | |
303 | { | |
304 | int mult_delta; | |
305 | ||
306 | if (xfer_len > MTK_SPI_PACKET_SIZE) | |
307 | mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; | |
308 | else | |
309 | mult_delta = 0; | |
310 | ||
311 | return mult_delta; | |
312 | } | |
313 | ||
314 | static void mtk_spi_update_mdata_len(struct spi_master *master) | |
315 | { | |
316 | int mult_delta; | |
317 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
318 | ||
319 | if (mdata->tx_sgl_len && mdata->rx_sgl_len) { | |
320 | if (mdata->tx_sgl_len > mdata->rx_sgl_len) { | |
321 | mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); | |
322 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; | |
323 | mdata->rx_sgl_len = mult_delta; | |
324 | mdata->tx_sgl_len -= mdata->xfer_len; | |
325 | } else { | |
326 | mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); | |
327 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; | |
328 | mdata->tx_sgl_len = mult_delta; | |
329 | mdata->rx_sgl_len -= mdata->xfer_len; | |
330 | } | |
331 | } else if (mdata->tx_sgl_len) { | |
332 | mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); | |
333 | mdata->xfer_len = mdata->tx_sgl_len - mult_delta; | |
334 | mdata->tx_sgl_len = mult_delta; | |
335 | } else if (mdata->rx_sgl_len) { | |
336 | mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); | |
337 | mdata->xfer_len = mdata->rx_sgl_len - mult_delta; | |
338 | mdata->rx_sgl_len = mult_delta; | |
339 | } | |
340 | } | |
341 | ||
342 | static void mtk_spi_setup_dma_addr(struct spi_master *master, | |
343 | struct spi_transfer *xfer) | |
344 | { | |
345 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
346 | ||
347 | if (mdata->tx_sgl) | |
39ba928f | 348 | writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG); |
a568231f | 349 | if (mdata->rx_sgl) |
39ba928f | 350 | writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG); |
a568231f LL |
351 | } |
352 | ||
353 | static int mtk_spi_fifo_transfer(struct spi_master *master, | |
354 | struct spi_device *spi, | |
355 | struct spi_transfer *xfer) | |
356 | { | |
44f636da | 357 | int cnt; |
a568231f LL |
358 | struct mtk_spi *mdata = spi_master_get_devdata(master); |
359 | ||
360 | mdata->cur_transfer = xfer; | |
361 | mdata->xfer_len = xfer->len; | |
362 | mtk_spi_prepare_transfer(master, xfer); | |
363 | mtk_spi_setup_packet(master); | |
364 | ||
365 | if (xfer->len % 4) | |
366 | cnt = xfer->len / 4 + 1; | |
367 | else | |
368 | cnt = xfer->len / 4; | |
44f636da | 369 | iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); |
a568231f LL |
370 | |
371 | mtk_spi_enable_transfer(master); | |
372 | ||
373 | return 1; | |
374 | } | |
375 | ||
376 | static int mtk_spi_dma_transfer(struct spi_master *master, | |
377 | struct spi_device *spi, | |
378 | struct spi_transfer *xfer) | |
379 | { | |
380 | int cmd; | |
381 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
382 | ||
383 | mdata->tx_sgl = NULL; | |
384 | mdata->rx_sgl = NULL; | |
385 | mdata->tx_sgl_len = 0; | |
386 | mdata->rx_sgl_len = 0; | |
387 | mdata->cur_transfer = xfer; | |
388 | ||
389 | mtk_spi_prepare_transfer(master, xfer); | |
390 | ||
391 | cmd = readl(mdata->base + SPI_CMD_REG); | |
392 | if (xfer->tx_buf) | |
393 | cmd |= SPI_CMD_TX_DMA; | |
394 | if (xfer->rx_buf) | |
395 | cmd |= SPI_CMD_RX_DMA; | |
396 | writel(cmd, mdata->base + SPI_CMD_REG); | |
397 | ||
398 | if (xfer->tx_buf) | |
399 | mdata->tx_sgl = xfer->tx_sg.sgl; | |
400 | if (xfer->rx_buf) | |
401 | mdata->rx_sgl = xfer->rx_sg.sgl; | |
402 | ||
403 | if (mdata->tx_sgl) { | |
404 | xfer->tx_dma = sg_dma_address(mdata->tx_sgl); | |
405 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); | |
406 | } | |
407 | if (mdata->rx_sgl) { | |
408 | xfer->rx_dma = sg_dma_address(mdata->rx_sgl); | |
409 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); | |
410 | } | |
411 | ||
412 | mtk_spi_update_mdata_len(master); | |
413 | mtk_spi_setup_packet(master); | |
414 | mtk_spi_setup_dma_addr(master, xfer); | |
415 | mtk_spi_enable_transfer(master); | |
416 | ||
417 | return 1; | |
418 | } | |
419 | ||
420 | static int mtk_spi_transfer_one(struct spi_master *master, | |
421 | struct spi_device *spi, | |
422 | struct spi_transfer *xfer) | |
423 | { | |
424 | if (master->can_dma(master, spi, xfer)) | |
425 | return mtk_spi_dma_transfer(master, spi, xfer); | |
426 | else | |
427 | return mtk_spi_fifo_transfer(master, spi, xfer); | |
428 | } | |
429 | ||
430 | static bool mtk_spi_can_dma(struct spi_master *master, | |
431 | struct spi_device *spi, | |
432 | struct spi_transfer *xfer) | |
433 | { | |
434 | return xfer->len > MTK_SPI_MAX_FIFO_SIZE; | |
435 | } | |
436 | ||
437 | static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) | |
438 | { | |
44f636da | 439 | u32 cmd, reg_val, cnt; |
a568231f LL |
440 | struct spi_master *master = dev_id; |
441 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
442 | struct spi_transfer *trans = mdata->cur_transfer; | |
443 | ||
444 | reg_val = readl(mdata->base + SPI_STATUS0_REG); | |
445 | if (reg_val & 0x2) | |
446 | mdata->state = MTK_SPI_PAUSED; | |
447 | else | |
448 | mdata->state = MTK_SPI_IDLE; | |
449 | ||
450 | if (!master->can_dma(master, master->cur_msg->spi, trans)) { | |
a568231f | 451 | if (trans->rx_buf) { |
44f636da LL |
452 | if (mdata->xfer_len % 4) |
453 | cnt = mdata->xfer_len / 4 + 1; | |
454 | else | |
455 | cnt = mdata->xfer_len / 4; | |
456 | ioread32_rep(mdata->base + SPI_RX_DATA_REG, | |
457 | trans->rx_buf, cnt); | |
a568231f LL |
458 | } |
459 | spi_finalize_current_transfer(master); | |
460 | return IRQ_HANDLED; | |
461 | } | |
462 | ||
463 | if (mdata->tx_sgl) | |
464 | trans->tx_dma += mdata->xfer_len; | |
465 | if (mdata->rx_sgl) | |
466 | trans->rx_dma += mdata->xfer_len; | |
467 | ||
468 | if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { | |
469 | mdata->tx_sgl = sg_next(mdata->tx_sgl); | |
470 | if (mdata->tx_sgl) { | |
471 | trans->tx_dma = sg_dma_address(mdata->tx_sgl); | |
472 | mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); | |
473 | } | |
474 | } | |
475 | if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { | |
476 | mdata->rx_sgl = sg_next(mdata->rx_sgl); | |
477 | if (mdata->rx_sgl) { | |
478 | trans->rx_dma = sg_dma_address(mdata->rx_sgl); | |
479 | mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); | |
480 | } | |
481 | } | |
482 | ||
483 | if (!mdata->tx_sgl && !mdata->rx_sgl) { | |
484 | /* spi disable dma */ | |
485 | cmd = readl(mdata->base + SPI_CMD_REG); | |
486 | cmd &= ~SPI_CMD_TX_DMA; | |
487 | cmd &= ~SPI_CMD_RX_DMA; | |
488 | writel(cmd, mdata->base + SPI_CMD_REG); | |
489 | ||
490 | spi_finalize_current_transfer(master); | |
491 | return IRQ_HANDLED; | |
492 | } | |
493 | ||
494 | mtk_spi_update_mdata_len(master); | |
495 | mtk_spi_setup_packet(master); | |
496 | mtk_spi_setup_dma_addr(master, trans); | |
497 | mtk_spi_enable_transfer(master); | |
498 | ||
499 | return IRQ_HANDLED; | |
500 | } | |
501 | ||
502 | static int mtk_spi_probe(struct platform_device *pdev) | |
503 | { | |
504 | struct spi_master *master; | |
505 | struct mtk_spi *mdata; | |
506 | const struct of_device_id *of_id; | |
507 | struct resource *res; | |
508 | int irq, ret; | |
509 | ||
510 | master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); | |
511 | if (!master) { | |
512 | dev_err(&pdev->dev, "failed to alloc spi master\n"); | |
513 | return -ENOMEM; | |
514 | } | |
515 | ||
516 | master->auto_runtime_pm = true; | |
517 | master->dev.of_node = pdev->dev.of_node; | |
518 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
519 | ||
520 | master->set_cs = mtk_spi_set_cs; | |
521 | master->prepare_transfer_hardware = mtk_spi_prepare_hardware; | |
a568231f LL |
522 | master->prepare_message = mtk_spi_prepare_message; |
523 | master->transfer_one = mtk_spi_transfer_one; | |
524 | master->can_dma = mtk_spi_can_dma; | |
525 | ||
526 | of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); | |
527 | if (!of_id) { | |
528 | dev_err(&pdev->dev, "failed to probe of_node\n"); | |
529 | ret = -EINVAL; | |
530 | goto err_put_master; | |
531 | } | |
532 | ||
533 | mdata = spi_master_get_devdata(master); | |
534 | mdata->dev_comp = of_id->data; | |
535 | if (mdata->dev_comp->must_tx) | |
536 | master->flags = SPI_MASTER_MUST_TX; | |
537 | ||
538 | if (mdata->dev_comp->need_pad_sel) { | |
539 | ret = of_property_read_u32(pdev->dev.of_node, | |
540 | "mediatek,pad-select", | |
541 | &mdata->pad_sel); | |
542 | if (ret) { | |
543 | dev_err(&pdev->dev, "failed to read pad select: %d\n", | |
544 | ret); | |
545 | goto err_put_master; | |
546 | } | |
547 | ||
548 | if (mdata->pad_sel > MT8173_SPI_MAX_PAD_SEL) { | |
549 | dev_err(&pdev->dev, "wrong pad-select: %u\n", | |
550 | mdata->pad_sel); | |
551 | ret = -EINVAL; | |
552 | goto err_put_master; | |
553 | } | |
554 | } | |
555 | ||
556 | platform_set_drvdata(pdev, master); | |
557 | ||
558 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
559 | if (!res) { | |
560 | ret = -ENODEV; | |
561 | dev_err(&pdev->dev, "failed to determine base address\n"); | |
562 | goto err_put_master; | |
563 | } | |
564 | ||
565 | mdata->base = devm_ioremap_resource(&pdev->dev, res); | |
566 | if (IS_ERR(mdata->base)) { | |
567 | ret = PTR_ERR(mdata->base); | |
568 | goto err_put_master; | |
569 | } | |
570 | ||
571 | irq = platform_get_irq(pdev, 0); | |
572 | if (irq < 0) { | |
573 | dev_err(&pdev->dev, "failed to get irq (%d)\n", irq); | |
574 | ret = irq; | |
575 | goto err_put_master; | |
576 | } | |
577 | ||
578 | if (!pdev->dev.dma_mask) | |
579 | pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; | |
580 | ||
581 | ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, | |
582 | IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); | |
583 | if (ret) { | |
584 | dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); | |
585 | goto err_put_master; | |
586 | } | |
587 | ||
588 | mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); | |
589 | if (IS_ERR(mdata->spi_clk)) { | |
590 | ret = PTR_ERR(mdata->spi_clk); | |
591 | dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); | |
592 | goto err_put_master; | |
593 | } | |
594 | ||
595 | mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); | |
596 | if (IS_ERR(mdata->parent_clk)) { | |
597 | ret = PTR_ERR(mdata->parent_clk); | |
598 | dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); | |
599 | goto err_put_master; | |
600 | } | |
601 | ||
602 | ret = clk_prepare_enable(mdata->spi_clk); | |
603 | if (ret < 0) { | |
604 | dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); | |
605 | goto err_put_master; | |
606 | } | |
607 | ||
608 | ret = clk_set_parent(mdata->spi_clk, mdata->parent_clk); | |
609 | if (ret < 0) { | |
610 | dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); | |
611 | goto err_disable_clk; | |
612 | } | |
613 | ||
614 | clk_disable_unprepare(mdata->spi_clk); | |
615 | ||
616 | pm_runtime_enable(&pdev->dev); | |
617 | ||
618 | ret = devm_spi_register_master(&pdev->dev, master); | |
619 | if (ret) { | |
620 | dev_err(&pdev->dev, "failed to register master (%d)\n", ret); | |
621 | goto err_put_master; | |
622 | } | |
623 | ||
624 | return 0; | |
625 | ||
626 | err_disable_clk: | |
627 | clk_disable_unprepare(mdata->spi_clk); | |
628 | err_put_master: | |
629 | spi_master_put(master); | |
630 | ||
631 | return ret; | |
632 | } | |
633 | ||
634 | static int mtk_spi_remove(struct platform_device *pdev) | |
635 | { | |
636 | struct spi_master *master = platform_get_drvdata(pdev); | |
637 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
638 | ||
639 | pm_runtime_disable(&pdev->dev); | |
640 | ||
641 | mtk_spi_reset(mdata); | |
642 | clk_disable_unprepare(mdata->spi_clk); | |
643 | spi_master_put(master); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | #ifdef CONFIG_PM_SLEEP | |
649 | static int mtk_spi_suspend(struct device *dev) | |
650 | { | |
651 | int ret; | |
652 | struct spi_master *master = dev_get_drvdata(dev); | |
653 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
654 | ||
655 | ret = spi_master_suspend(master); | |
656 | if (ret) | |
657 | return ret; | |
658 | ||
659 | if (!pm_runtime_suspended(dev)) | |
660 | clk_disable_unprepare(mdata->spi_clk); | |
661 | ||
662 | return ret; | |
663 | } | |
664 | ||
665 | static int mtk_spi_resume(struct device *dev) | |
666 | { | |
667 | int ret; | |
668 | struct spi_master *master = dev_get_drvdata(dev); | |
669 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
670 | ||
671 | if (!pm_runtime_suspended(dev)) { | |
672 | ret = clk_prepare_enable(mdata->spi_clk); | |
673 | if (ret < 0) | |
674 | return ret; | |
675 | } | |
676 | ||
677 | ret = spi_master_resume(master); | |
678 | if (ret < 0) | |
679 | clk_disable_unprepare(mdata->spi_clk); | |
680 | ||
681 | return ret; | |
682 | } | |
683 | #endif /* CONFIG_PM_SLEEP */ | |
684 | ||
685 | #ifdef CONFIG_PM | |
686 | static int mtk_spi_runtime_suspend(struct device *dev) | |
687 | { | |
688 | struct spi_master *master = dev_get_drvdata(dev); | |
689 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
690 | ||
691 | clk_disable_unprepare(mdata->spi_clk); | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
696 | static int mtk_spi_runtime_resume(struct device *dev) | |
697 | { | |
698 | struct spi_master *master = dev_get_drvdata(dev); | |
699 | struct mtk_spi *mdata = spi_master_get_devdata(master); | |
700 | ||
701 | return clk_prepare_enable(mdata->spi_clk); | |
702 | } | |
703 | #endif /* CONFIG_PM */ | |
704 | ||
705 | static const struct dev_pm_ops mtk_spi_pm = { | |
706 | SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) | |
707 | SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, | |
708 | mtk_spi_runtime_resume, NULL) | |
709 | }; | |
710 | ||
4299aaaa | 711 | static struct platform_driver mtk_spi_driver = { |
a568231f LL |
712 | .driver = { |
713 | .name = "mtk-spi", | |
714 | .pm = &mtk_spi_pm, | |
715 | .of_match_table = mtk_spi_of_match, | |
716 | }, | |
717 | .probe = mtk_spi_probe, | |
718 | .remove = mtk_spi_remove, | |
719 | }; | |
720 | ||
721 | module_platform_driver(mtk_spi_driver); | |
722 | ||
723 | MODULE_DESCRIPTION("MTK SPI Controller driver"); | |
724 | MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); | |
725 | MODULE_LICENSE("GPL v2"); | |
e4001885 | 726 | MODULE_ALIAS("platform:mtk-spi"); |