Commit | Line | Data |
---|---|---|
ccf06998 | 1 | /* |
b36ece83 | 2 | * Freescale SPI controller driver. |
ccf06998 KG |
3 | * |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
b36ece83 | 7 | * Copyright 2010 Freescale Semiconductor, Inc. |
ccf06998 | 8 | * |
4c1fba44 AV |
9 | * CPM SPI and QE buffer descriptors mode support: |
10 | * Copyright (c) 2009 MontaVista Software, Inc. | |
11 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
12 | * | |
ccf06998 KG |
13 | * This program is free software; you can redistribute it and/or modify it |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | #include <linux/module.h> | |
ccf06998 KG |
19 | #include <linux/types.h> |
20 | #include <linux/kernel.h> | |
ccf06998 KG |
21 | #include <linux/interrupt.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/irq.h> | |
ccf06998 KG |
24 | #include <linux/spi/spi.h> |
25 | #include <linux/spi/spi_bitbang.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/fsl_devices.h> | |
4c1fba44 AV |
28 | #include <linux/dma-mapping.h> |
29 | #include <linux/mm.h> | |
30 | #include <linux/mutex.h> | |
35b4b3c0 AV |
31 | #include <linux/of.h> |
32 | #include <linux/of_platform.h> | |
e8beacbb AL |
33 | #include <linux/of_address.h> |
34 | #include <linux/of_irq.h> | |
35b4b3c0 AV |
35 | #include <linux/gpio.h> |
36 | #include <linux/of_gpio.h> | |
ccf06998 | 37 | |
ca632f55 | 38 | #include "spi-fsl-lib.h" |
e8beacbb AL |
39 | #include "spi-fsl-cpm.h" |
40 | #include "spi-fsl-spi.h" | |
ccf06998 | 41 | |
b36ece83 | 42 | static void fsl_spi_change_mode(struct spi_device *spi) |
a35c1710 AV |
43 | { |
44 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
45 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
b36ece83 MH |
46 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
47 | __be32 __iomem *mode = ®_base->mode; | |
a35c1710 AV |
48 | unsigned long flags; |
49 | ||
50 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
51 | return; | |
52 | ||
53 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
54 | local_irq_save(flags); | |
55 | ||
56 | /* Turn off SPI unit prior changing mode */ | |
57 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
a35c1710 | 58 | |
4c1fba44 AV |
59 | /* When in CPM mode, we need to reinit tx and rx. */ |
60 | if (mspi->flags & SPI_CPM_MODE) { | |
e8beacbb | 61 | fsl_spi_cpm_reinit_txrx(mspi); |
4c1fba44 | 62 | } |
f9218c2a | 63 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); |
a35c1710 AV |
64 | local_irq_restore(flags); |
65 | } | |
66 | ||
b36ece83 | 67 | static void fsl_spi_chipselect(struct spi_device *spi, int value) |
ccf06998 | 68 | { |
575c5807 | 69 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
5039a869 | 70 | struct fsl_spi_platform_data *pdata; |
364fdbc0 | 71 | bool pol = spi->mode & SPI_CS_HIGH; |
575c5807 | 72 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 73 | |
5039a869 KE |
74 | pdata = spi->dev.parent->parent->platform_data; |
75 | ||
ccf06998 | 76 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
77 | if (pdata->cs_control) |
78 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
79 | } |
80 | ||
81 | if (value == BITBANG_CS_ACTIVE) { | |
575c5807 AV |
82 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
83 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
84 | mpc8xxx_spi->get_rx = cs->get_rx; | |
85 | mpc8xxx_spi->get_tx = cs->get_tx; | |
c9bfcb31 | 86 | |
b36ece83 | 87 | fsl_spi_change_mode(spi); |
a35c1710 | 88 | |
364fdbc0 AV |
89 | if (pdata->cs_control) |
90 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
91 | } |
92 | } | |
93 | ||
b48c4e3c AL |
94 | static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift, |
95 | int bits_per_word, int msb_first) | |
96 | { | |
97 | *rx_shift = 0; | |
98 | *tx_shift = 0; | |
99 | if (msb_first) { | |
100 | if (bits_per_word <= 8) { | |
101 | *rx_shift = 16; | |
102 | *tx_shift = 24; | |
103 | } else if (bits_per_word <= 16) { | |
104 | *rx_shift = 16; | |
105 | *tx_shift = 16; | |
106 | } | |
107 | } else { | |
108 | if (bits_per_word <= 8) | |
109 | *rx_shift = 8; | |
110 | } | |
111 | } | |
112 | ||
b36ece83 MH |
113 | static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, |
114 | struct spi_device *spi, | |
115 | struct mpc8xxx_spi *mpc8xxx_spi, | |
116 | int bits_per_word) | |
ccf06998 | 117 | { |
c9bfcb31 JT |
118 | cs->rx_shift = 0; |
119 | cs->tx_shift = 0; | |
ccf06998 | 120 | if (bits_per_word <= 8) { |
575c5807 AV |
121 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
122 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
ccf06998 | 123 | } else if (bits_per_word <= 16) { |
575c5807 AV |
124 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
125 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
ccf06998 | 126 | } else if (bits_per_word <= 32) { |
575c5807 AV |
127 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
128 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
ccf06998 KG |
129 | } else |
130 | return -EINVAL; | |
131 | ||
b48c4e3c AL |
132 | if (mpc8xxx_spi->set_shifts) |
133 | mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift, | |
134 | bits_per_word, | |
135 | !(spi->mode & SPI_LSB_FIRST)); | |
136 | ||
575c5807 AV |
137 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
138 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
139 | mpc8xxx_spi->get_rx = cs->get_rx; | |
140 | mpc8xxx_spi->get_tx = cs->get_tx; | |
ccf06998 | 141 | |
0398fb70 JT |
142 | return bits_per_word; |
143 | } | |
144 | ||
b36ece83 MH |
145 | static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, |
146 | struct spi_device *spi, | |
147 | int bits_per_word) | |
0398fb70 JT |
148 | { |
149 | /* QE uses Little Endian for words > 8 | |
150 | * so transform all words > 8 into 8 bits | |
151 | * Unfortnatly that doesn't work for LSB so | |
152 | * reject these for now */ | |
153 | /* Note: 32 bits word, LSB works iff | |
154 | * tfcr/rfcr is set to CPMFCR_GBL */ | |
155 | if (spi->mode & SPI_LSB_FIRST && | |
156 | bits_per_word > 8) | |
157 | return -EINVAL; | |
158 | if (bits_per_word > 8) | |
159 | return 8; /* pretend its 8 bits */ | |
160 | return bits_per_word; | |
161 | } | |
162 | ||
b36ece83 MH |
163 | static int fsl_spi_setup_transfer(struct spi_device *spi, |
164 | struct spi_transfer *t) | |
0398fb70 JT |
165 | { |
166 | struct mpc8xxx_spi *mpc8xxx_spi; | |
b36ece83 | 167 | int bits_per_word = 0; |
0398fb70 | 168 | u8 pm; |
b36ece83 | 169 | u32 hz = 0; |
0398fb70 JT |
170 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
171 | ||
172 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
173 | ||
174 | if (t) { | |
175 | bits_per_word = t->bits_per_word; | |
176 | hz = t->speed_hz; | |
0398fb70 JT |
177 | } |
178 | ||
179 | /* spi_transfer level calls that work per-word */ | |
180 | if (!bits_per_word) | |
181 | bits_per_word = spi->bits_per_word; | |
182 | ||
183 | /* Make sure its a bit width we support [4..16, 32] */ | |
184 | if ((bits_per_word < 4) | |
185 | || ((bits_per_word > 16) && (bits_per_word != 32))) | |
186 | return -EINVAL; | |
187 | ||
188 | if (!hz) | |
189 | hz = spi->max_speed_hz; | |
190 | ||
191 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) | |
192 | bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, | |
193 | mpc8xxx_spi, | |
194 | bits_per_word); | |
195 | else if (mpc8xxx_spi->flags & SPI_QE) | |
196 | bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, | |
197 | bits_per_word); | |
198 | ||
199 | if (bits_per_word < 0) | |
200 | return bits_per_word; | |
201 | ||
ccf06998 KG |
202 | if (bits_per_word == 32) |
203 | bits_per_word = 0; | |
204 | else | |
205 | bits_per_word = bits_per_word - 1; | |
206 | ||
32421daa | 207 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
208 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
209 | | SPMODE_PM(0xF)); | |
210 | ||
211 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
212 | ||
575c5807 | 213 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 214 | cs->hw_mode |= SPMODE_DIV16; |
4f4517c4 | 215 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
fd8a11e1 AV |
216 | |
217 | WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " | |
218 | "Will use %d Hz instead.\n", dev_name(&spi->dev), | |
575c5807 | 219 | hz, mpc8xxx_spi->spibrg / 1024); |
fd8a11e1 | 220 | if (pm > 16) |
53604dbe | 221 | pm = 16; |
b36ece83 | 222 | } else { |
4f4517c4 | 223 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
b36ece83 | 224 | } |
a61f5345 CG |
225 | if (pm) |
226 | pm--; | |
227 | ||
228 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 | 229 | |
b36ece83 | 230 | fsl_spi_change_mode(spi); |
c9bfcb31 JT |
231 | return 0; |
232 | } | |
ccf06998 | 233 | |
b36ece83 | 234 | static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
235 | struct spi_transfer *t, unsigned int len) |
236 | { | |
237 | u32 word; | |
b36ece83 | 238 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
239 | |
240 | mspi->count = len; | |
241 | ||
242 | /* enable rx ints */ | |
b36ece83 | 243 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); |
4c1fba44 AV |
244 | |
245 | /* transmit word */ | |
246 | word = mspi->get_tx(mspi); | |
b36ece83 | 247 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
4c1fba44 AV |
248 | |
249 | return 0; | |
250 | } | |
251 | ||
b36ece83 | 252 | static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, |
4c1fba44 AV |
253 | bool is_dma_mapped) |
254 | { | |
255 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
b36ece83 | 256 | struct fsl_spi_reg *reg_base; |
4c1fba44 AV |
257 | unsigned int len = t->len; |
258 | u8 bits_per_word; | |
259 | int ret; | |
c9bfcb31 | 260 | |
b36ece83 | 261 | reg_base = mpc8xxx_spi->reg_base; |
c9bfcb31 JT |
262 | bits_per_word = spi->bits_per_word; |
263 | if (t->bits_per_word) | |
264 | bits_per_word = t->bits_per_word; | |
4c1fba44 | 265 | |
aa77d96b PK |
266 | if (bits_per_word > 8) { |
267 | /* invalid length? */ | |
268 | if (len & 1) | |
269 | return -EINVAL; | |
c9bfcb31 | 270 | len /= 2; |
aa77d96b PK |
271 | } |
272 | if (bits_per_word > 16) { | |
273 | /* invalid length? */ | |
274 | if (len & 1) | |
275 | return -EINVAL; | |
c9bfcb31 | 276 | len /= 2; |
aa77d96b | 277 | } |
aa77d96b | 278 | |
4c1fba44 AV |
279 | mpc8xxx_spi->tx = t->tx_buf; |
280 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 | 281 | |
4c1fba44 | 282 | INIT_COMPLETION(mpc8xxx_spi->done); |
c9bfcb31 | 283 | |
4c1fba44 | 284 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 285 | ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); |
4c1fba44 | 286 | else |
b36ece83 | 287 | ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); |
4c1fba44 AV |
288 | if (ret) |
289 | return ret; | |
c9bfcb31 | 290 | |
575c5807 | 291 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
292 | |
293 | /* disable rx ints */ | |
b36ece83 | 294 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
c9bfcb31 | 295 | |
4c1fba44 | 296 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 297 | fsl_spi_cpm_bufs_complete(mpc8xxx_spi); |
4c1fba44 | 298 | |
575c5807 | 299 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
300 | } |
301 | ||
b36ece83 | 302 | static void fsl_spi_do_one_msg(struct spi_message *m) |
c9bfcb31 | 303 | { |
b9b9af11 AV |
304 | struct spi_device *spi = m->spi; |
305 | struct spi_transfer *t; | |
306 | unsigned int cs_change; | |
307 | const int nsecs = 50; | |
308 | int status; | |
309 | ||
310 | cs_change = 1; | |
311 | status = 0; | |
312 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
313 | if (t->bits_per_word || t->speed_hz) { | |
314 | /* Don't allow changes if CS is active */ | |
315 | status = -EINVAL; | |
316 | ||
317 | if (cs_change) | |
b36ece83 | 318 | status = fsl_spi_setup_transfer(spi, t); |
b9b9af11 | 319 | if (status < 0) |
c9bfcb31 | 320 | break; |
b9b9af11 | 321 | } |
c9bfcb31 | 322 | |
b9b9af11 | 323 | if (cs_change) { |
b36ece83 | 324 | fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
b9b9af11 AV |
325 | ndelay(nsecs); |
326 | } | |
327 | cs_change = t->cs_change; | |
328 | if (t->len) | |
b36ece83 | 329 | status = fsl_spi_bufs(spi, t, m->is_dma_mapped); |
b9b9af11 AV |
330 | if (status) { |
331 | status = -EMSGSIZE; | |
332 | break; | |
c9bfcb31 | 333 | } |
b9b9af11 | 334 | m->actual_length += t->len; |
c9bfcb31 | 335 | |
b9b9af11 AV |
336 | if (t->delay_usecs) |
337 | udelay(t->delay_usecs); | |
c9bfcb31 | 338 | |
b9b9af11 | 339 | if (cs_change) { |
c9bfcb31 | 340 | ndelay(nsecs); |
b36ece83 | 341 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 | 342 | ndelay(nsecs); |
c9bfcb31 | 343 | } |
b9b9af11 AV |
344 | } |
345 | ||
346 | m->status = status; | |
347 | m->complete(m->context); | |
348 | ||
349 | if (status || !cs_change) { | |
350 | ndelay(nsecs); | |
b36ece83 | 351 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 AV |
352 | } |
353 | ||
b36ece83 | 354 | fsl_spi_setup_transfer(spi, NULL); |
ccf06998 KG |
355 | } |
356 | ||
b36ece83 | 357 | static int fsl_spi_setup(struct spi_device *spi) |
ccf06998 | 358 | { |
575c5807 | 359 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 360 | struct fsl_spi_reg *reg_base; |
ccf06998 | 361 | int retval; |
c9bfcb31 | 362 | u32 hw_mode; |
575c5807 | 363 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 KG |
364 | |
365 | if (!spi->max_speed_hz) | |
366 | return -EINVAL; | |
367 | ||
c9bfcb31 JT |
368 | if (!cs) { |
369 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
370 | if (!cs) | |
371 | return -ENOMEM; | |
372 | spi->controller_state = cs; | |
373 | } | |
575c5807 | 374 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 | 375 | |
b36ece83 MH |
376 | reg_base = mpc8xxx_spi->reg_base; |
377 | ||
88393161 | 378 | hw_mode = cs->hw_mode; /* Save original settings */ |
b36ece83 | 379 | cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); |
c9bfcb31 JT |
380 | /* mask out bits we are going to set */ |
381 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
382 | | SPMODE_REV | SPMODE_LOOP); | |
383 | ||
384 | if (spi->mode & SPI_CPHA) | |
385 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
386 | if (spi->mode & SPI_CPOL) | |
387 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
388 | if (!(spi->mode & SPI_LSB_FIRST)) | |
389 | cs->hw_mode |= SPMODE_REV; | |
390 | if (spi->mode & SPI_LOOP) | |
391 | cs->hw_mode |= SPMODE_LOOP; | |
392 | ||
b36ece83 | 393 | retval = fsl_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
394 | if (retval < 0) { |
395 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 396 | return retval; |
c9bfcb31 | 397 | } |
f482cd0f AL |
398 | |
399 | /* Initialize chipselect - might be active for SPI_CS_HIGH mode */ | |
400 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); | |
401 | ||
ccf06998 KG |
402 | return 0; |
403 | } | |
404 | ||
b36ece83 | 405 | static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
4c1fba44 | 406 | { |
b36ece83 MH |
407 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
408 | ||
4c1fba44 AV |
409 | /* We need handle RX first */ |
410 | if (events & SPIE_NE) { | |
b36ece83 | 411 | u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); |
4c1fba44 AV |
412 | |
413 | if (mspi->rx) | |
414 | mspi->get_rx(rx_data, mspi); | |
ccf06998 KG |
415 | } |
416 | ||
4c1fba44 | 417 | if ((events & SPIE_NF) == 0) |
ccf06998 | 418 | /* spin until TX is done */ |
4c1fba44 | 419 | while (((events = |
b36ece83 | 420 | mpc8xxx_spi_read_reg(®_base->event)) & |
ccf06998 | 421 | SPIE_NF) == 0) |
9effb959 | 422 | cpu_relax(); |
ccf06998 | 423 | |
4c1fba44 | 424 | /* Clear the events */ |
b36ece83 | 425 | mpc8xxx_spi_write_reg(®_base->event, events); |
4c1fba44 AV |
426 | |
427 | mspi->count -= 1; | |
428 | if (mspi->count) { | |
429 | u32 word = mspi->get_tx(mspi); | |
430 | ||
b36ece83 | 431 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
ccf06998 | 432 | } else { |
4c1fba44 | 433 | complete(&mspi->done); |
ccf06998 | 434 | } |
4c1fba44 | 435 | } |
ccf06998 | 436 | |
b36ece83 | 437 | static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) |
4c1fba44 AV |
438 | { |
439 | struct mpc8xxx_spi *mspi = context_data; | |
440 | irqreturn_t ret = IRQ_NONE; | |
441 | u32 events; | |
b36ece83 | 442 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
443 | |
444 | /* Get interrupt events(tx/rx) */ | |
b36ece83 | 445 | events = mpc8xxx_spi_read_reg(®_base->event); |
4c1fba44 AV |
446 | if (events) |
447 | ret = IRQ_HANDLED; | |
448 | ||
449 | dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); | |
450 | ||
451 | if (mspi->flags & SPI_CPM_MODE) | |
b36ece83 | 452 | fsl_spi_cpm_irq(mspi, events); |
4c1fba44 | 453 | else |
b36ece83 | 454 | fsl_spi_cpu_irq(mspi, events); |
ccf06998 KG |
455 | |
456 | return ret; | |
457 | } | |
4c1fba44 | 458 | |
b36ece83 | 459 | static void fsl_spi_remove(struct mpc8xxx_spi *mspi) |
87ec0e98 | 460 | { |
b36ece83 MH |
461 | iounmap(mspi->reg_base); |
462 | fsl_spi_cpm_free(mspi); | |
87ec0e98 AV |
463 | } |
464 | ||
fd4a319b | 465 | static struct spi_master * fsl_spi_probe(struct device *dev, |
b36ece83 | 466 | struct resource *mem, unsigned int irq) |
ccf06998 | 467 | { |
35b4b3c0 | 468 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
ccf06998 | 469 | struct spi_master *master; |
575c5807 | 470 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 471 | struct fsl_spi_reg *reg_base; |
ccf06998 KG |
472 | u32 regval; |
473 | int ret = 0; | |
474 | ||
575c5807 | 475 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
ccf06998 KG |
476 | if (master == NULL) { |
477 | ret = -ENOMEM; | |
478 | goto err; | |
479 | } | |
480 | ||
35b4b3c0 | 481 | dev_set_drvdata(dev, master); |
ccf06998 | 482 | |
b36ece83 MH |
483 | ret = mpc8xxx_spi_probe(dev, mem, irq); |
484 | if (ret) | |
485 | goto err_probe; | |
e7db06b5 | 486 | |
b36ece83 | 487 | master->setup = fsl_spi_setup; |
575c5807 AV |
488 | |
489 | mpc8xxx_spi = spi_master_get_devdata(master); | |
b36ece83 MH |
490 | mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg; |
491 | mpc8xxx_spi->spi_remove = fsl_spi_remove; | |
492 | ||
575c5807 | 493 | |
b36ece83 | 494 | ret = fsl_spi_cpm_init(mpc8xxx_spi); |
4c1fba44 AV |
495 | if (ret) |
496 | goto err_cpm_init; | |
497 | ||
b48c4e3c AL |
498 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
499 | mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts; | |
500 | ||
501 | if (mpc8xxx_spi->set_shifts) | |
502 | /* 8 bits per word and MSB first */ | |
503 | mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift, | |
504 | &mpc8xxx_spi->tx_shift, 8, 1); | |
f29ba280 | 505 | |
b36ece83 MH |
506 | mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); |
507 | if (mpc8xxx_spi->reg_base == NULL) { | |
ccf06998 | 508 | ret = -ENOMEM; |
4c1fba44 | 509 | goto err_ioremap; |
ccf06998 KG |
510 | } |
511 | ||
ccf06998 | 512 | /* Register for SPI Interrupt */ |
b36ece83 MH |
513 | ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq, |
514 | 0, "fsl_spi", mpc8xxx_spi); | |
ccf06998 KG |
515 | |
516 | if (ret != 0) | |
b36ece83 | 517 | goto free_irq; |
ccf06998 | 518 | |
b36ece83 | 519 | reg_base = mpc8xxx_spi->reg_base; |
ccf06998 KG |
520 | |
521 | /* SPI controller initializations */ | |
b36ece83 MH |
522 | mpc8xxx_spi_write_reg(®_base->mode, 0); |
523 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
524 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
525 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
ccf06998 KG |
526 | |
527 | /* Enable SPI interface */ | |
528 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
87ec0e98 | 529 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
f29ba280 JT |
530 | regval |= SPMODE_OP; |
531 | ||
b36ece83 | 532 | mpc8xxx_spi_write_reg(®_base->mode, regval); |
c9bfcb31 JT |
533 | |
534 | ret = spi_register_master(master); | |
535 | if (ret < 0) | |
536 | goto unreg_master; | |
ccf06998 | 537 | |
b36ece83 | 538 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, |
87ec0e98 | 539 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); |
ccf06998 | 540 | |
35b4b3c0 | 541 | return master; |
ccf06998 | 542 | |
c9bfcb31 | 543 | unreg_master: |
575c5807 | 544 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); |
b36ece83 MH |
545 | free_irq: |
546 | iounmap(mpc8xxx_spi->reg_base); | |
4c1fba44 | 547 | err_ioremap: |
b36ece83 | 548 | fsl_spi_cpm_free(mpc8xxx_spi); |
4c1fba44 | 549 | err_cpm_init: |
b36ece83 | 550 | err_probe: |
ccf06998 | 551 | spi_master_put(master); |
ccf06998 | 552 | err: |
35b4b3c0 | 553 | return ERR_PTR(ret); |
ccf06998 KG |
554 | } |
555 | ||
b36ece83 | 556 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) |
35b4b3c0 | 557 | { |
067aa481 | 558 | struct device *dev = spi->dev.parent->parent; |
575c5807 | 559 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); |
35b4b3c0 AV |
560 | u16 cs = spi->chip_select; |
561 | int gpio = pinfo->gpios[cs]; | |
562 | bool alow = pinfo->alow_flags[cs]; | |
563 | ||
564 | gpio_set_value(gpio, on ^ alow); | |
565 | } | |
566 | ||
b36ece83 | 567 | static int of_fsl_spi_get_chipselects(struct device *dev) |
35b4b3c0 | 568 | { |
61c7a080 | 569 | struct device_node *np = dev->of_node; |
35b4b3c0 | 570 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
575c5807 | 571 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
e80beb27 | 572 | int ngpios; |
35b4b3c0 AV |
573 | int i = 0; |
574 | int ret; | |
575 | ||
576 | ngpios = of_gpio_count(np); | |
e80beb27 | 577 | if (ngpios <= 0) { |
35b4b3c0 AV |
578 | /* |
579 | * SPI w/o chip-select line. One SPI device is still permitted | |
580 | * though. | |
581 | */ | |
582 | pdata->max_chipselect = 1; | |
583 | return 0; | |
584 | } | |
585 | ||
02141546 | 586 | pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); |
35b4b3c0 AV |
587 | if (!pinfo->gpios) |
588 | return -ENOMEM; | |
02141546 | 589 | memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); |
35b4b3c0 | 590 | |
02141546 | 591 | pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), |
35b4b3c0 AV |
592 | GFP_KERNEL); |
593 | if (!pinfo->alow_flags) { | |
594 | ret = -ENOMEM; | |
595 | goto err_alloc_flags; | |
596 | } | |
597 | ||
598 | for (; i < ngpios; i++) { | |
599 | int gpio; | |
600 | enum of_gpio_flags flags; | |
601 | ||
602 | gpio = of_get_gpio_flags(np, i, &flags); | |
603 | if (!gpio_is_valid(gpio)) { | |
604 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
783058fd | 605 | ret = gpio; |
35b4b3c0 AV |
606 | goto err_loop; |
607 | } | |
608 | ||
609 | ret = gpio_request(gpio, dev_name(dev)); | |
610 | if (ret) { | |
611 | dev_err(dev, "can't request gpio #%d: %d\n", i, ret); | |
612 | goto err_loop; | |
613 | } | |
614 | ||
615 | pinfo->gpios[i] = gpio; | |
616 | pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; | |
617 | ||
618 | ret = gpio_direction_output(pinfo->gpios[i], | |
619 | pinfo->alow_flags[i]); | |
620 | if (ret) { | |
621 | dev_err(dev, "can't set output direction for gpio " | |
622 | "#%d: %d\n", i, ret); | |
623 | goto err_loop; | |
624 | } | |
625 | } | |
626 | ||
627 | pdata->max_chipselect = ngpios; | |
b36ece83 | 628 | pdata->cs_control = fsl_spi_cs_control; |
35b4b3c0 AV |
629 | |
630 | return 0; | |
631 | ||
632 | err_loop: | |
633 | while (i >= 0) { | |
634 | if (gpio_is_valid(pinfo->gpios[i])) | |
635 | gpio_free(pinfo->gpios[i]); | |
636 | i--; | |
637 | } | |
638 | ||
639 | kfree(pinfo->alow_flags); | |
640 | pinfo->alow_flags = NULL; | |
641 | err_alloc_flags: | |
642 | kfree(pinfo->gpios); | |
643 | pinfo->gpios = NULL; | |
644 | return ret; | |
645 | } | |
646 | ||
b36ece83 | 647 | static int of_fsl_spi_free_chipselects(struct device *dev) |
35b4b3c0 AV |
648 | { |
649 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
575c5807 | 650 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
651 | int i; |
652 | ||
653 | if (!pinfo->gpios) | |
654 | return 0; | |
655 | ||
656 | for (i = 0; i < pdata->max_chipselect; i++) { | |
657 | if (gpio_is_valid(pinfo->gpios[i])) | |
658 | gpio_free(pinfo->gpios[i]); | |
659 | } | |
660 | ||
661 | kfree(pinfo->gpios); | |
662 | kfree(pinfo->alow_flags); | |
663 | return 0; | |
664 | } | |
665 | ||
fd4a319b | 666 | static int of_fsl_spi_probe(struct platform_device *ofdev) |
35b4b3c0 AV |
667 | { |
668 | struct device *dev = &ofdev->dev; | |
61c7a080 | 669 | struct device_node *np = ofdev->dev.of_node; |
35b4b3c0 AV |
670 | struct spi_master *master; |
671 | struct resource mem; | |
e8beacbb | 672 | int irq; |
35b4b3c0 AV |
673 | int ret = -ENOMEM; |
674 | ||
18d306d1 | 675 | ret = of_mpc8xxx_spi_probe(ofdev); |
b36ece83 MH |
676 | if (ret) |
677 | return ret; | |
35b4b3c0 | 678 | |
b36ece83 | 679 | ret = of_fsl_spi_get_chipselects(dev); |
35b4b3c0 AV |
680 | if (ret) |
681 | goto err; | |
682 | ||
683 | ret = of_address_to_resource(np, 0, &mem); | |
684 | if (ret) | |
685 | goto err; | |
686 | ||
e8beacbb AL |
687 | irq = irq_of_parse_and_map(np, 0); |
688 | if (!irq) { | |
35b4b3c0 AV |
689 | ret = -EINVAL; |
690 | goto err; | |
691 | } | |
692 | ||
e8beacbb | 693 | master = fsl_spi_probe(dev, &mem, irq); |
35b4b3c0 AV |
694 | if (IS_ERR(master)) { |
695 | ret = PTR_ERR(master); | |
696 | goto err; | |
697 | } | |
698 | ||
35b4b3c0 AV |
699 | return 0; |
700 | ||
701 | err: | |
b36ece83 | 702 | of_fsl_spi_free_chipselects(dev); |
35b4b3c0 AV |
703 | return ret; |
704 | } | |
705 | ||
fd4a319b | 706 | static int of_fsl_spi_remove(struct platform_device *ofdev) |
35b4b3c0 AV |
707 | { |
708 | int ret; | |
709 | ||
575c5807 | 710 | ret = mpc8xxx_spi_remove(&ofdev->dev); |
35b4b3c0 AV |
711 | if (ret) |
712 | return ret; | |
b36ece83 | 713 | of_fsl_spi_free_chipselects(&ofdev->dev); |
35b4b3c0 AV |
714 | return 0; |
715 | } | |
716 | ||
b36ece83 | 717 | static const struct of_device_id of_fsl_spi_match[] = { |
35b4b3c0 | 718 | { .compatible = "fsl,spi" }, |
b36ece83 | 719 | {} |
35b4b3c0 | 720 | }; |
b36ece83 | 721 | MODULE_DEVICE_TABLE(of, of_fsl_spi_match); |
35b4b3c0 | 722 | |
18d306d1 | 723 | static struct platform_driver of_fsl_spi_driver = { |
4018294b | 724 | .driver = { |
b36ece83 | 725 | .name = "fsl_spi", |
4018294b | 726 | .owner = THIS_MODULE, |
b36ece83 | 727 | .of_match_table = of_fsl_spi_match, |
4018294b | 728 | }, |
b36ece83 | 729 | .probe = of_fsl_spi_probe, |
fd4a319b | 730 | .remove = of_fsl_spi_remove, |
35b4b3c0 AV |
731 | }; |
732 | ||
733 | #ifdef CONFIG_MPC832x_RDB | |
734 | /* | |
b36ece83 | 735 | * XXX XXX XXX |
35b4b3c0 AV |
736 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards |
737 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
738 | * tree can work with OpenFirmware driver. But for now we support old trees | |
739 | * as well. | |
740 | */ | |
fd4a319b | 741 | static int plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
742 | { |
743 | struct resource *mem; | |
e9a172f0 | 744 | int irq; |
35b4b3c0 AV |
745 | struct spi_master *master; |
746 | ||
747 | if (!pdev->dev.platform_data) | |
748 | return -EINVAL; | |
749 | ||
750 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
751 | if (!mem) | |
752 | return -EINVAL; | |
753 | ||
754 | irq = platform_get_irq(pdev, 0); | |
e9a172f0 | 755 | if (irq <= 0) |
35b4b3c0 AV |
756 | return -EINVAL; |
757 | ||
b36ece83 | 758 | master = fsl_spi_probe(&pdev->dev, mem, irq); |
e4d43781 | 759 | return PTR_RET(master); |
35b4b3c0 AV |
760 | } |
761 | ||
fd4a319b | 762 | static int plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 763 | { |
575c5807 | 764 | return mpc8xxx_spi_remove(&pdev->dev); |
35b4b3c0 AV |
765 | } |
766 | ||
575c5807 AV |
767 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
768 | static struct platform_driver mpc8xxx_spi_driver = { | |
769 | .probe = plat_mpc8xxx_spi_probe, | |
fd4a319b | 770 | .remove = plat_mpc8xxx_spi_remove, |
ccf06998 | 771 | .driver = { |
575c5807 | 772 | .name = "mpc8xxx_spi", |
7e38c3c4 | 773 | .owner = THIS_MODULE, |
ccf06998 KG |
774 | }, |
775 | }; | |
776 | ||
35b4b3c0 AV |
777 | static bool legacy_driver_failed; |
778 | ||
779 | static void __init legacy_driver_register(void) | |
780 | { | |
575c5807 | 781 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
782 | } |
783 | ||
784 | static void __exit legacy_driver_unregister(void) | |
785 | { | |
786 | if (legacy_driver_failed) | |
787 | return; | |
575c5807 | 788 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
789 | } |
790 | #else | |
791 | static void __init legacy_driver_register(void) {} | |
792 | static void __exit legacy_driver_unregister(void) {} | |
793 | #endif /* CONFIG_MPC832x_RDB */ | |
794 | ||
b36ece83 | 795 | static int __init fsl_spi_init(void) |
ccf06998 | 796 | { |
35b4b3c0 | 797 | legacy_driver_register(); |
18d306d1 | 798 | return platform_driver_register(&of_fsl_spi_driver); |
ccf06998 | 799 | } |
b36ece83 | 800 | module_init(fsl_spi_init); |
ccf06998 | 801 | |
b36ece83 | 802 | static void __exit fsl_spi_exit(void) |
ccf06998 | 803 | { |
18d306d1 | 804 | platform_driver_unregister(&of_fsl_spi_driver); |
35b4b3c0 | 805 | legacy_driver_unregister(); |
ccf06998 | 806 | } |
b36ece83 | 807 | module_exit(fsl_spi_exit); |
ccf06998 KG |
808 | |
809 | MODULE_AUTHOR("Kumar Gala"); | |
b36ece83 | 810 | MODULE_DESCRIPTION("Simple Freescale SPI Driver"); |
ccf06998 | 811 | MODULE_LICENSE("GPL"); |