Commit | Line | Data |
---|---|---|
34b8c661 SK |
1 | /* |
2 | * Freescale/Motorola Coldfire Queued SPI driver | |
3 | * | |
4 | * Copyright 2010 Steven King <sfking@fdwdc.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/platform_device.h> | |
5e1c5335 | 27 | #include <linux/sched.h> |
34b8c661 SK |
28 | #include <linux/workqueue.h> |
29 | #include <linux/delay.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/clk.h> | |
32 | #include <linux/err.h> | |
33 | #include <linux/spi/spi.h> | |
34 | ||
35 | #include <asm/coldfire.h> | |
0b4bf782 | 36 | #include <asm/mcfsim.h> |
34b8c661 SK |
37 | #include <asm/mcfqspi.h> |
38 | ||
39 | #define DRIVER_NAME "mcfqspi" | |
40 | ||
41 | #define MCFQSPI_BUSCLK (MCF_BUSCLK / 2) | |
42 | ||
43 | #define MCFQSPI_QMR 0x00 | |
44 | #define MCFQSPI_QMR_MSTR 0x8000 | |
45 | #define MCFQSPI_QMR_CPOL 0x0200 | |
46 | #define MCFQSPI_QMR_CPHA 0x0100 | |
47 | #define MCFQSPI_QDLYR 0x04 | |
48 | #define MCFQSPI_QDLYR_SPE 0x8000 | |
49 | #define MCFQSPI_QWR 0x08 | |
50 | #define MCFQSPI_QWR_HALT 0x8000 | |
51 | #define MCFQSPI_QWR_WREN 0x4000 | |
52 | #define MCFQSPI_QWR_CSIV 0x1000 | |
53 | #define MCFQSPI_QIR 0x0C | |
54 | #define MCFQSPI_QIR_WCEFB 0x8000 | |
55 | #define MCFQSPI_QIR_ABRTB 0x4000 | |
56 | #define MCFQSPI_QIR_ABRTL 0x1000 | |
57 | #define MCFQSPI_QIR_WCEFE 0x0800 | |
58 | #define MCFQSPI_QIR_ABRTE 0x0400 | |
59 | #define MCFQSPI_QIR_SPIFE 0x0100 | |
60 | #define MCFQSPI_QIR_WCEF 0x0008 | |
61 | #define MCFQSPI_QIR_ABRT 0x0004 | |
62 | #define MCFQSPI_QIR_SPIF 0x0001 | |
63 | #define MCFQSPI_QAR 0x010 | |
64 | #define MCFQSPI_QAR_TXBUF 0x00 | |
65 | #define MCFQSPI_QAR_RXBUF 0x10 | |
66 | #define MCFQSPI_QAR_CMDBUF 0x20 | |
67 | #define MCFQSPI_QDR 0x014 | |
68 | #define MCFQSPI_QCR 0x014 | |
69 | #define MCFQSPI_QCR_CONT 0x8000 | |
70 | #define MCFQSPI_QCR_BITSE 0x4000 | |
71 | #define MCFQSPI_QCR_DT 0x2000 | |
72 | ||
73 | struct mcfqspi { | |
74 | void __iomem *iobase; | |
75 | int irq; | |
76 | struct clk *clk; | |
77 | struct mcfqspi_cs_control *cs_control; | |
78 | ||
79 | wait_queue_head_t waitq; | |
80 | ||
81 | struct work_struct work; | |
82 | struct workqueue_struct *workq; | |
83 | spinlock_t lock; | |
84 | struct list_head msgq; | |
85 | }; | |
86 | ||
87 | static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val) | |
88 | { | |
89 | writew(val, mcfqspi->iobase + MCFQSPI_QMR); | |
90 | } | |
91 | ||
92 | static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val) | |
93 | { | |
94 | writew(val, mcfqspi->iobase + MCFQSPI_QDLYR); | |
95 | } | |
96 | ||
97 | static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi) | |
98 | { | |
99 | return readw(mcfqspi->iobase + MCFQSPI_QDLYR); | |
100 | } | |
101 | ||
102 | static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val) | |
103 | { | |
104 | writew(val, mcfqspi->iobase + MCFQSPI_QWR); | |
105 | } | |
106 | ||
107 | static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val) | |
108 | { | |
109 | writew(val, mcfqspi->iobase + MCFQSPI_QIR); | |
110 | } | |
111 | ||
112 | static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val) | |
113 | { | |
114 | writew(val, mcfqspi->iobase + MCFQSPI_QAR); | |
115 | } | |
116 | ||
117 | static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val) | |
118 | { | |
119 | writew(val, mcfqspi->iobase + MCFQSPI_QDR); | |
120 | } | |
121 | ||
122 | static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi) | |
123 | { | |
124 | return readw(mcfqspi->iobase + MCFQSPI_QDR); | |
125 | } | |
126 | ||
127 | static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select, | |
128 | bool cs_high) | |
129 | { | |
130 | mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high); | |
131 | } | |
132 | ||
133 | static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select, | |
134 | bool cs_high) | |
135 | { | |
136 | mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high); | |
137 | } | |
138 | ||
139 | static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi) | |
140 | { | |
141 | return (mcfqspi->cs_control && mcfqspi->cs_control->setup) ? | |
142 | mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0; | |
143 | } | |
144 | ||
145 | static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi) | |
146 | { | |
147 | if (mcfqspi->cs_control && mcfqspi->cs_control->teardown) | |
148 | mcfqspi->cs_control->teardown(mcfqspi->cs_control); | |
149 | } | |
150 | ||
151 | static u8 mcfqspi_qmr_baud(u32 speed_hz) | |
152 | { | |
153 | return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u); | |
154 | } | |
155 | ||
156 | static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi) | |
157 | { | |
158 | return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE; | |
159 | } | |
160 | ||
161 | static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id) | |
162 | { | |
163 | struct mcfqspi *mcfqspi = dev_id; | |
164 | ||
165 | /* clear interrupt */ | |
166 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF); | |
167 | wake_up(&mcfqspi->waitq); | |
168 | ||
169 | return IRQ_HANDLED; | |
170 | } | |
171 | ||
172 | static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count, | |
173 | const u8 *txbuf, u8 *rxbuf) | |
174 | { | |
175 | unsigned i, n, offset = 0; | |
176 | ||
177 | n = min(count, 16u); | |
178 | ||
179 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF); | |
180 | for (i = 0; i < n; ++i) | |
181 | mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE); | |
182 | ||
183 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF); | |
184 | if (txbuf) | |
185 | for (i = 0; i < n; ++i) | |
186 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
187 | else | |
188 | for (i = 0; i < count; ++i) | |
189 | mcfqspi_wr_qdr(mcfqspi, 0); | |
190 | ||
191 | count -= n; | |
192 | if (count) { | |
193 | u16 qwr = 0xf08; | |
194 | mcfqspi_wr_qwr(mcfqspi, 0x700); | |
195 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
196 | ||
197 | do { | |
198 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
199 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
200 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
201 | if (rxbuf) { | |
202 | mcfqspi_wr_qar(mcfqspi, | |
203 | MCFQSPI_QAR_RXBUF + offset); | |
204 | for (i = 0; i < 8; ++i) | |
205 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
206 | } | |
207 | n = min(count, 8u); | |
208 | if (txbuf) { | |
209 | mcfqspi_wr_qar(mcfqspi, | |
210 | MCFQSPI_QAR_TXBUF + offset); | |
211 | for (i = 0; i < n; ++i) | |
212 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
213 | } | |
214 | qwr = (offset ? 0x808 : 0) + ((n - 1) << 8); | |
215 | offset ^= 8; | |
216 | count -= n; | |
217 | } while (count); | |
218 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
219 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
220 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
221 | if (rxbuf) { | |
222 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
223 | for (i = 0; i < 8; ++i) | |
224 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
225 | offset ^= 8; | |
226 | } | |
227 | } else { | |
228 | mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8); | |
229 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
230 | } | |
231 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
232 | if (rxbuf) { | |
233 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
234 | for (i = 0; i < n; ++i) | |
235 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
236 | } | |
237 | } | |
238 | ||
239 | static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count, | |
240 | const u16 *txbuf, u16 *rxbuf) | |
241 | { | |
242 | unsigned i, n, offset = 0; | |
243 | ||
244 | n = min(count, 16u); | |
245 | ||
246 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF); | |
247 | for (i = 0; i < n; ++i) | |
248 | mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE); | |
249 | ||
250 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF); | |
251 | if (txbuf) | |
252 | for (i = 0; i < n; ++i) | |
253 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
254 | else | |
255 | for (i = 0; i < count; ++i) | |
256 | mcfqspi_wr_qdr(mcfqspi, 0); | |
257 | ||
258 | count -= n; | |
259 | if (count) { | |
260 | u16 qwr = 0xf08; | |
261 | mcfqspi_wr_qwr(mcfqspi, 0x700); | |
262 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
263 | ||
264 | do { | |
265 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
266 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
267 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
268 | if (rxbuf) { | |
269 | mcfqspi_wr_qar(mcfqspi, | |
270 | MCFQSPI_QAR_RXBUF + offset); | |
271 | for (i = 0; i < 8; ++i) | |
272 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
273 | } | |
274 | n = min(count, 8u); | |
275 | if (txbuf) { | |
276 | mcfqspi_wr_qar(mcfqspi, | |
277 | MCFQSPI_QAR_TXBUF + offset); | |
278 | for (i = 0; i < n; ++i) | |
279 | mcfqspi_wr_qdr(mcfqspi, *txbuf++); | |
280 | } | |
281 | qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8); | |
282 | offset ^= 8; | |
283 | count -= n; | |
284 | } while (count); | |
285 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
286 | mcfqspi_wr_qwr(mcfqspi, qwr); | |
287 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
288 | if (rxbuf) { | |
289 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
290 | for (i = 0; i < 8; ++i) | |
291 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
292 | offset ^= 8; | |
293 | } | |
294 | } else { | |
295 | mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8); | |
296 | mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE); | |
297 | } | |
298 | wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi)); | |
299 | if (rxbuf) { | |
300 | mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset); | |
301 | for (i = 0; i < n; ++i) | |
302 | *rxbuf++ = mcfqspi_rd_qdr(mcfqspi); | |
303 | } | |
304 | } | |
305 | ||
306 | static void mcfqspi_work(struct work_struct *work) | |
307 | { | |
308 | struct mcfqspi *mcfqspi = container_of(work, struct mcfqspi, work); | |
309 | unsigned long flags; | |
310 | ||
311 | spin_lock_irqsave(&mcfqspi->lock, flags); | |
312 | while (!list_empty(&mcfqspi->msgq)) { | |
313 | struct spi_message *msg; | |
314 | struct spi_device *spi; | |
315 | struct spi_transfer *xfer; | |
316 | int status = 0; | |
317 | ||
318 | msg = container_of(mcfqspi->msgq.next, struct spi_message, | |
319 | queue); | |
320 | ||
0bc46342 | 321 | list_del_init(&msg->queue); |
34b8c661 SK |
322 | spin_unlock_irqrestore(&mcfqspi->lock, flags); |
323 | ||
324 | spi = msg->spi; | |
325 | ||
326 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
327 | bool cs_high = spi->mode & SPI_CS_HIGH; | |
328 | u16 qmr = MCFQSPI_QMR_MSTR; | |
329 | ||
330 | if (xfer->bits_per_word) | |
331 | qmr |= xfer->bits_per_word << 10; | |
332 | else | |
333 | qmr |= spi->bits_per_word << 10; | |
334 | if (spi->mode & SPI_CPHA) | |
335 | qmr |= MCFQSPI_QMR_CPHA; | |
336 | if (spi->mode & SPI_CPOL) | |
337 | qmr |= MCFQSPI_QMR_CPOL; | |
338 | if (xfer->speed_hz) | |
339 | qmr |= mcfqspi_qmr_baud(xfer->speed_hz); | |
340 | else | |
341 | qmr |= mcfqspi_qmr_baud(spi->max_speed_hz); | |
342 | mcfqspi_wr_qmr(mcfqspi, qmr); | |
343 | ||
344 | mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high); | |
345 | ||
346 | mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE); | |
347 | if ((xfer->bits_per_word ? xfer->bits_per_word : | |
348 | spi->bits_per_word) == 8) | |
349 | mcfqspi_transfer_msg8(mcfqspi, xfer->len, | |
350 | xfer->tx_buf, | |
351 | xfer->rx_buf); | |
352 | else | |
353 | mcfqspi_transfer_msg16(mcfqspi, xfer->len / 2, | |
354 | xfer->tx_buf, | |
355 | xfer->rx_buf); | |
356 | mcfqspi_wr_qir(mcfqspi, 0); | |
357 | ||
358 | if (xfer->delay_usecs) | |
359 | udelay(xfer->delay_usecs); | |
360 | if (xfer->cs_change) { | |
361 | if (!list_is_last(&xfer->transfer_list, | |
362 | &msg->transfers)) | |
363 | mcfqspi_cs_deselect(mcfqspi, | |
364 | spi->chip_select, | |
365 | cs_high); | |
366 | } else { | |
367 | if (list_is_last(&xfer->transfer_list, | |
368 | &msg->transfers)) | |
369 | mcfqspi_cs_deselect(mcfqspi, | |
370 | spi->chip_select, | |
371 | cs_high); | |
372 | } | |
373 | msg->actual_length += xfer->len; | |
374 | } | |
375 | msg->status = status; | |
376 | msg->complete(msg->context); | |
377 | ||
378 | spin_lock_irqsave(&mcfqspi->lock, flags); | |
379 | } | |
380 | spin_unlock_irqrestore(&mcfqspi->lock, flags); | |
381 | } | |
382 | ||
383 | static int mcfqspi_transfer(struct spi_device *spi, struct spi_message *msg) | |
384 | { | |
385 | struct mcfqspi *mcfqspi; | |
386 | struct spi_transfer *xfer; | |
387 | unsigned long flags; | |
388 | ||
389 | mcfqspi = spi_master_get_devdata(spi->master); | |
390 | ||
391 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
392 | if (xfer->bits_per_word && ((xfer->bits_per_word < 8) | |
393 | || (xfer->bits_per_word > 16))) { | |
394 | dev_dbg(&spi->dev, | |
395 | "%d bits per word is not supported\n", | |
396 | xfer->bits_per_word); | |
397 | goto fail; | |
398 | } | |
399 | if (xfer->speed_hz) { | |
400 | u32 real_speed = MCFQSPI_BUSCLK / | |
401 | mcfqspi_qmr_baud(xfer->speed_hz); | |
402 | if (real_speed != xfer->speed_hz) | |
403 | dev_dbg(&spi->dev, | |
404 | "using speed %d instead of %d\n", | |
405 | real_speed, xfer->speed_hz); | |
406 | } | |
407 | } | |
408 | msg->status = -EINPROGRESS; | |
409 | msg->actual_length = 0; | |
410 | ||
411 | spin_lock_irqsave(&mcfqspi->lock, flags); | |
412 | list_add_tail(&msg->queue, &mcfqspi->msgq); | |
413 | queue_work(mcfqspi->workq, &mcfqspi->work); | |
414 | spin_unlock_irqrestore(&mcfqspi->lock, flags); | |
415 | ||
416 | return 0; | |
417 | fail: | |
418 | msg->status = -EINVAL; | |
419 | return -EINVAL; | |
420 | } | |
421 | ||
422 | static int mcfqspi_setup(struct spi_device *spi) | |
423 | { | |
424 | if ((spi->bits_per_word < 8) || (spi->bits_per_word > 16)) { | |
425 | dev_dbg(&spi->dev, "%d bits per word is not supported\n", | |
426 | spi->bits_per_word); | |
427 | return -EINVAL; | |
428 | } | |
429 | if (spi->chip_select >= spi->master->num_chipselect) { | |
430 | dev_dbg(&spi->dev, "%d chip select is out of range\n", | |
431 | spi->chip_select); | |
432 | return -EINVAL; | |
433 | } | |
434 | ||
435 | mcfqspi_cs_deselect(spi_master_get_devdata(spi->master), | |
436 | spi->chip_select, spi->mode & SPI_CS_HIGH); | |
437 | ||
438 | dev_dbg(&spi->dev, | |
439 | "bits per word %d, chip select %d, speed %d KHz\n", | |
440 | spi->bits_per_word, spi->chip_select, | |
441 | (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz)) | |
442 | / 1000); | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | static int __devinit mcfqspi_probe(struct platform_device *pdev) | |
448 | { | |
449 | struct spi_master *master; | |
450 | struct mcfqspi *mcfqspi; | |
451 | struct resource *res; | |
452 | struct mcfqspi_platform_data *pdata; | |
453 | int status; | |
454 | ||
455 | master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi)); | |
456 | if (master == NULL) { | |
457 | dev_dbg(&pdev->dev, "spi_alloc_master failed\n"); | |
458 | return -ENOMEM; | |
459 | } | |
460 | ||
461 | mcfqspi = spi_master_get_devdata(master); | |
462 | ||
463 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
464 | if (!res) { | |
465 | dev_dbg(&pdev->dev, "platform_get_resource failed\n"); | |
466 | status = -ENXIO; | |
467 | goto fail0; | |
468 | } | |
469 | ||
470 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) { | |
471 | dev_dbg(&pdev->dev, "request_mem_region failed\n"); | |
472 | status = -EBUSY; | |
473 | goto fail0; | |
474 | } | |
475 | ||
476 | mcfqspi->iobase = ioremap(res->start, resource_size(res)); | |
477 | if (!mcfqspi->iobase) { | |
478 | dev_dbg(&pdev->dev, "ioremap failed\n"); | |
479 | status = -ENOMEM; | |
480 | goto fail1; | |
481 | } | |
482 | ||
483 | mcfqspi->irq = platform_get_irq(pdev, 0); | |
484 | if (mcfqspi->irq < 0) { | |
485 | dev_dbg(&pdev->dev, "platform_get_irq failed\n"); | |
486 | status = -ENXIO; | |
487 | goto fail2; | |
488 | } | |
489 | ||
38ada214 | 490 | status = request_irq(mcfqspi->irq, mcfqspi_irq_handler, 0, |
34b8c661 SK |
491 | pdev->name, mcfqspi); |
492 | if (status) { | |
493 | dev_dbg(&pdev->dev, "request_irq failed\n"); | |
494 | goto fail2; | |
495 | } | |
496 | ||
497 | mcfqspi->clk = clk_get(&pdev->dev, "qspi_clk"); | |
498 | if (IS_ERR(mcfqspi->clk)) { | |
499 | dev_dbg(&pdev->dev, "clk_get failed\n"); | |
500 | status = PTR_ERR(mcfqspi->clk); | |
501 | goto fail3; | |
502 | } | |
503 | clk_enable(mcfqspi->clk); | |
504 | ||
505 | mcfqspi->workq = create_singlethread_workqueue(dev_name(master->dev.parent)); | |
506 | if (!mcfqspi->workq) { | |
507 | dev_dbg(&pdev->dev, "create_workqueue failed\n"); | |
508 | status = -ENOMEM; | |
509 | goto fail4; | |
510 | } | |
511 | INIT_WORK(&mcfqspi->work, mcfqspi_work); | |
512 | spin_lock_init(&mcfqspi->lock); | |
513 | INIT_LIST_HEAD(&mcfqspi->msgq); | |
514 | init_waitqueue_head(&mcfqspi->waitq); | |
515 | ||
516 | pdata = pdev->dev.platform_data; | |
517 | if (!pdata) { | |
518 | dev_dbg(&pdev->dev, "platform data is missing\n"); | |
519 | goto fail5; | |
520 | } | |
521 | master->bus_num = pdata->bus_num; | |
522 | master->num_chipselect = pdata->num_chipselect; | |
523 | ||
524 | mcfqspi->cs_control = pdata->cs_control; | |
525 | status = mcfqspi_cs_setup(mcfqspi); | |
526 | if (status) { | |
527 | dev_dbg(&pdev->dev, "error initializing cs_control\n"); | |
528 | goto fail5; | |
529 | } | |
530 | ||
531 | master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; | |
532 | master->setup = mcfqspi_setup; | |
533 | master->transfer = mcfqspi_transfer; | |
534 | ||
535 | platform_set_drvdata(pdev, master); | |
536 | ||
537 | status = spi_register_master(master); | |
538 | if (status) { | |
539 | dev_dbg(&pdev->dev, "spi_register_master failed\n"); | |
540 | goto fail6; | |
541 | } | |
542 | dev_info(&pdev->dev, "Coldfire QSPI bus driver\n"); | |
543 | ||
544 | return 0; | |
545 | ||
546 | fail6: | |
547 | mcfqspi_cs_teardown(mcfqspi); | |
548 | fail5: | |
549 | destroy_workqueue(mcfqspi->workq); | |
550 | fail4: | |
551 | clk_disable(mcfqspi->clk); | |
552 | clk_put(mcfqspi->clk); | |
553 | fail3: | |
554 | free_irq(mcfqspi->irq, mcfqspi); | |
555 | fail2: | |
556 | iounmap(mcfqspi->iobase); | |
557 | fail1: | |
558 | release_mem_region(res->start, resource_size(res)); | |
559 | fail0: | |
560 | spi_master_put(master); | |
561 | ||
562 | dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n"); | |
563 | ||
564 | return status; | |
565 | } | |
566 | ||
567 | static int __devexit mcfqspi_remove(struct platform_device *pdev) | |
568 | { | |
569 | struct spi_master *master = platform_get_drvdata(pdev); | |
570 | struct mcfqspi *mcfqspi = spi_master_get_devdata(master); | |
571 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
572 | ||
573 | /* disable the hardware (set the baud rate to 0) */ | |
574 | mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR); | |
575 | ||
576 | platform_set_drvdata(pdev, NULL); | |
577 | mcfqspi_cs_teardown(mcfqspi); | |
578 | destroy_workqueue(mcfqspi->workq); | |
579 | clk_disable(mcfqspi->clk); | |
580 | clk_put(mcfqspi->clk); | |
581 | free_irq(mcfqspi->irq, mcfqspi); | |
582 | iounmap(mcfqspi->iobase); | |
583 | release_mem_region(res->start, resource_size(res)); | |
584 | spi_unregister_master(master); | |
585 | spi_master_put(master); | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | #ifdef CONFIG_PM | |
591 | ||
592 | static int mcfqspi_suspend(struct device *dev) | |
593 | { | |
594 | struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); | |
595 | ||
596 | clk_disable(mcfqspi->clk); | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | static int mcfqspi_resume(struct device *dev) | |
602 | { | |
603 | struct mcfqspi *mcfqspi = platform_get_drvdata(to_platform_device(dev)); | |
604 | ||
605 | clk_enable(mcfqspi->clk); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | static struct dev_pm_ops mcfqspi_dev_pm_ops = { | |
611 | .suspend = mcfqspi_suspend, | |
612 | .resume = mcfqspi_resume, | |
613 | }; | |
614 | ||
615 | #define MCFQSPI_DEV_PM_OPS (&mcfqspi_dev_pm_ops) | |
616 | #else | |
617 | #define MCFQSPI_DEV_PM_OPS NULL | |
618 | #endif | |
619 | ||
620 | static struct platform_driver mcfqspi_driver = { | |
621 | .driver.name = DRIVER_NAME, | |
622 | .driver.owner = THIS_MODULE, | |
623 | .driver.pm = MCFQSPI_DEV_PM_OPS, | |
940ab889 | 624 | .probe = mcfqspi_probe, |
34b8c661 SK |
625 | .remove = __devexit_p(mcfqspi_remove), |
626 | }; | |
940ab889 | 627 | module_platform_driver(mcfqspi_driver); |
34b8c661 SK |
628 | |
629 | MODULE_AUTHOR("Steven King <sfking@fdwdc.com>"); | |
630 | MODULE_DESCRIPTION("Coldfire QSPI Controller Driver"); | |
631 | MODULE_LICENSE("GPL"); | |
632 | MODULE_ALIAS("platform:" DRIVER_NAME); |