[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / spi / spi-bitbang.c

/*
 * polling/bitbanging SPI master controller driver utilities
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>


/*----------------------------------------------------------------------*/

/*
 * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
 * Use this for GPIO or shift-register level hardware APIs.
 *
 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
 * to glue code.  These bitbang setup() and cleanup() routines are always
 * used, though maybe they're called from controller-aware code.
 *
 * chipselect() and friends may use spi_device->controller_data and
 * controller registers as appropriate.
 *
 *
 * NOTE:  SPI controller pins can often be used as GPIO pins instead,
 * which means you could use a bitbang driver either to get hardware
 * working quickly, or testing for differences that aren't speed related.
 */

struct spi_bitbang_cs {
	unsigned	nsecs;	/* (clock cycle time)/2 */
	u32		(*txrx_word)(struct spi_device *spi, unsigned nsecs,
					u32 word, u8 bits);
	unsigned	(*txrx_bufs)(struct spi_device *,
					u32 (*txrx_word)(
						struct spi_device *spi,
						unsigned nsecs,
						u32 word, u8 bits),
					unsigned, struct spi_transfer *);
};

static unsigned bitbang_txrx_8(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u8		*tx = t->tx_buf;
	u8			*rx = t->rx_buf;

	while (likely(count > 0)) {
		u8		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 1;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_16(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u16		*tx = t->tx_buf;
	u16			*rx = t->rx_buf;

	while (likely(count > 1)) {
		u16		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 2;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_32(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = t->bits_per_word;
	unsigned		count = t->len;
	const u32		*tx = t->tx_buf;
	u32			*rx = t->rx_buf;

	while (likely(count > 3)) {
		u32		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 4;
	}
	return t->len - count;
}

int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	u8			bits_per_word;
	u32			hz;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;
	if (bits_per_word <= 8)
		cs->txrx_bufs = bitbang_txrx_8;
	else if (bits_per_word <= 16)
		cs->txrx_bufs = bitbang_txrx_16;
	else if (bits_per_word <= 32)
		cs->txrx_bufs = bitbang_txrx_32;
	else
		return -EINVAL;

	/* nsecs = (clock period)/2 */
	if (!hz)
		hz = spi->max_speed_hz;
	if (hz) {
		cs->nsecs = (1000000000/2) / hz;
		if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
			return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);

/**
 * spi_bitbang_setup - default setup for per-word I/O loops
 */
int spi_bitbang_setup(struct spi_device *spi)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi->master);

	if (!cs) {
		cs = kzalloc(sizeof(*cs), GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	/* per-word shift register access, in hardware or bitbanging */
	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
	if (!cs->txrx_word)
		return -EINVAL;

	if (bitbang->setup_transfer) {
		int retval = bitbang->setup_transfer(spi, NULL);
		if (retval < 0)
			return retval;
	}

	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);

	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	 * setup, unless the hardware defaults cooperate to avoid confusion
	 * between normal (active low) and inverted chipselects.
	 */

	/* deselect chip (low or high) */
	mutex_lock(&bitbang->lock);
	if (!bitbang->busy) {
		bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
		ndelay(cs->nsecs);
	}
	mutex_unlock(&bitbang->lock);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup);

/**
 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
 */
void spi_bitbang_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}
EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);

static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	unsigned		nsecs = cs->nsecs;

	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
}

/*----------------------------------------------------------------------*/

/*
 * SECOND PART ... simple transfer queue runner.
 *
 * This costs a task context per controller, running the queue by
 * performing each transfer in sequence.  Smarter hardware can queue
 * several DMA transfers at once, and process several controller queues
 * in parallel; this driver doesn't match such hardware very well.
 *
 * Drivers can provide word-at-a-time i/o primitives, or provide
 * transfer-at-a-time ones to leverage dma or fifo hardware.
 */

static int spi_bitbang_prepare_hardware(struct spi_master *spi)
{
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi);

	mutex_lock(&bitbang->lock);
	bitbang->busy = 1;
	mutex_unlock(&bitbang->lock);

	return 0;
}

static int spi_bitbang_transfer_one(struct spi_master *master,
				    struct spi_message *m)
{
	struct spi_bitbang	*bitbang;
	unsigned		nsecs;
	struct spi_transfer	*t = NULL;
	unsigned		cs_change;
	int			status;
	struct spi_device	*spi = m->spi;

	bitbang = spi_master_get_devdata(master);

	/* FIXME this is made-up ... the correct value is known to
	 * word-at-a-time bitbang code, and presumably chipselect()
	 * should enforce these requirements too?
	 */
	nsecs = 100;

	cs_change = 1;
	status = 0;

	list_for_each_entry(t, &m->transfers, transfer_list) {

		if (bitbang->setup_transfer) {
			status = bitbang->setup_transfer(spi, t);
			if (status < 0)
				break;
		}

		/* set up default clock polarity, and activate chip;
		 * this implicitly updates clock and spi modes as
		 * previously recorded for this device via setup().
		 * (and also deselects any other chip that might be
		 * selected ...)
		 */
		if (cs_change) {
			bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
			ndelay(nsecs);
		}
		cs_change = t->cs_change;
		if (!t->tx_buf && !t->rx_buf && t->len) {
			status = -EINVAL;
			break;
		}

		/* transfer data.  the lower level code handles any
		 * new dma mappings it needs. our caller always gave
		 * us dma-safe buffers.
		 */
		if (t->len) {
			/* REVISIT dma API still needs a designated
			 * DMA_ADDR_INVALID; ~0 might be better.
			 */
			if (!m->is_dma_mapped)
				t->rx_dma = t->tx_dma = 0;
			status = bitbang->txrx_bufs(spi, t);
		}
		if (status > 0)
			m->actual_length += status;
		if (status != t->len) {
			/* always report some kind of error */
			if (status >= 0)
				status = -EREMOTEIO;
			break;
		}
		status = 0;

		/* protocol tweaks before next transfer */
		if (t->delay_usecs)
			udelay(t->delay_usecs);

		if (cs_change &&
		    !list_is_last(&t->transfer_list, &m->transfers)) {
			/* sometimes a short mid-message deselect of the chip
			 * may be needed to terminate a mode or command
			 */
			ndelay(nsecs);
			bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
			ndelay(nsecs);
		}
	}

	m->status = status;

	/* normally deactivate chipselect ... unless no error and
	 * cs_change has hinted that the next message will probably
	 * be for this chip too.
	 */
	if (!(status == 0 && cs_change)) {
		ndelay(nsecs);
		bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
		ndelay(nsecs);
	}

	spi_finalize_current_message(master);

	return status;
}

static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
{
	struct spi_bitbang	*bitbang;

	bitbang = spi_master_get_devdata(spi);

	mutex_lock(&bitbang->lock);
	bitbang->busy = 0;
	mutex_unlock(&bitbang->lock);

	return 0;
}

/*----------------------------------------------------------------------*/

/**
 * spi_bitbang_start - start up a polled/bitbanging SPI master driver
 * @bitbang: driver handle
 *
 * Caller should have zero-initialized all parts of the structure, and then
 * provided callbacks for chip selection and I/O loops.  If the master has
 * a transfer method, its final step should call spi_bitbang_transfer; or,
 * that's the default if the transfer routine is not initialized.  It should
 * also set up the bus number and number of chipselects.
 *
 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
 * hardware that basically exposes a shift register) or per-spi_transfer
 * (which takes better advantage of hardware like fifos or DMA engines).
 *
 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
 * master methods.  Those methods are the defaults if the bitbang->txrx_bufs
 * routine isn't initialized.
 *
 * This routine registers the spi_master, which will process requests in a
 * dedicated task, keeping IRQs unblocked most of the time.  To stop
 * processing those requests, call spi_bitbang_stop().
 *
 * On success, this routine will take a reference to master. The caller is
 * responsible for calling spi_bitbang_stop() to decrement the reference and
 * spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
 * leak.
 */
int spi_bitbang_start(struct spi_bitbang *bitbang)
{
	struct spi_master *master = bitbang->master;
	int ret;

	if (!master || !bitbang->chipselect)
		return -EINVAL;

	mutex_init(&bitbang->lock);

	if (!master->mode_bits)
		master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;

	if (master->transfer || master->transfer_one_message)
		return -EINVAL;

	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	master->transfer_one_message = spi_bitbang_transfer_one;

	if (!bitbang->txrx_bufs) {
		bitbang->use_dma = 0;
		bitbang->txrx_bufs = spi_bitbang_bufs;
		if (!master->setup) {
			if (!bitbang->setup_transfer)
				bitbang->setup_transfer =
					 spi_bitbang_setup_transfer;
			master->setup = spi_bitbang_setup;
			master->cleanup = spi_bitbang_cleanup;
		}
	}

	/* driver may get busy before register() returns, especially
	 * if someone registered boardinfo for devices
	 */
	ret = spi_register_master(spi_master_get(master));
	if (ret)
		spi_master_put(master);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_start);

/**
 * spi_bitbang_stop - stops the task providing spi communication
 */
void spi_bitbang_stop(struct spi_bitbang *bitbang)
{
	spi_unregister_master(bitbang->master);
}
EXPORT_SYMBOL_GPL(spi_bitbang_stop);

MODULE_LICENSE("GPL");
Commit	Line	Data
9904f22a	1	/*
ca632f55	2	* polling/bitbanging SPI master controller driver utilities
9904f22a DB	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
9904f22a DB	13	*/
9904f22a DB	14
9904f22a DB	15	#include <linux/spinlock.h>
	16	#include <linux/workqueue.h>
	17	#include <linux/interrupt.h>
d7614de4	18	#include <linux/module.h>
9904f22a DB	19	#include <linux/delay.h>
	20	#include <linux/errno.h>
	21	#include <linux/platform_device.h>
5a0e3ad6	22	#include <linux/slab.h>
9904f22a DB	23
	24	#include <linux/spi/spi.h>
	25	#include <linux/spi/spi_bitbang.h>
	26
	27
	28	/----------------------------------------------------------------------/
	29
	30	/*
	31	* FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
	32	* Use this for GPIO or shift-register level hardware APIs.
	33	*
	34	* spi_bitbang_cs is in spi_device->controller_state, which is unavailable
	35	* to glue code. These bitbang setup() and cleanup() routines are always
	36	* used, though maybe they're called from controller-aware code.
	37	*
03ddcbc5	38	* chipselect() and friends may use spi_device->controller_data and
9904f22a DB	39	* controller registers as appropriate.
	40	*
	41	*
	42	* NOTE: SPI controller pins can often be used as GPIO pins instead,
	43	* which means you could use a bitbang driver either to get hardware
	44	* working quickly, or testing for differences that aren't speed related.
	45	*/
	46
	47	struct spi_bitbang_cs {
	48	unsigned nsecs; /* (clock cycle time)/2 */
	49	u32 (txrx_word)(struct spi_device spi, unsigned nsecs,
	50	u32 word, u8 bits);
	51	unsigned (txrx_bufs)(struct spi_device ,
	52	u32 (*txrx_word)(
	53	struct spi_device *spi,
	54	unsigned nsecs,
	55	u32 word, u8 bits),
	56	unsigned, struct spi_transfer *);
	57	};
	58
	59	static unsigned bitbang_txrx_8(
	60	struct spi_device *spi,
	61	u32 (txrx_word)(struct spi_device spi,
	62	unsigned nsecs,
	63	u32 word, u8 bits),
	64	unsigned ns,
	65	struct spi_transfer *t
	66	) {
766ed704	67	unsigned bits = t->bits_per_word;
9904f22a DB	68	unsigned count = t->len;
	69	const u8 *tx = t->tx_buf;
	70	u8 *rx = t->rx_buf;
	71
	72	while (likely(count > 0)) {
	73	u8 word = 0;
	74
	75	if (tx)
	76	word = *tx++;
	77	word = txrx_word(spi, ns, word, bits);
	78	if (rx)
	79	*rx++ = word;
	80	count -= 1;
	81	}
	82	return t->len - count;
	83	}
	84
	85	static unsigned bitbang_txrx_16(
	86	struct spi_device *spi,
	87	u32 (txrx_word)(struct spi_device spi,
	88	unsigned nsecs,
	89	u32 word, u8 bits),
	90	unsigned ns,
	91	struct spi_transfer *t
	92	) {
766ed704	93	unsigned bits = t->bits_per_word;
9904f22a DB	94	unsigned count = t->len;
	95	const u16 *tx = t->tx_buf;
	96	u16 *rx = t->rx_buf;
	97
	98	while (likely(count > 1)) {
	99	u16 word = 0;
	100
	101	if (tx)
	102	word = *tx++;
	103	word = txrx_word(spi, ns, word, bits);
	104	if (rx)
	105	*rx++ = word;
	106	count -= 2;
	107	}
	108	return t->len - count;
	109	}
	110
	111	static unsigned bitbang_txrx_32(
	112	struct spi_device *spi,
	113	u32 (txrx_word)(struct spi_device spi,
	114	unsigned nsecs,
	115	u32 word, u8 bits),
	116	unsigned ns,
	117	struct spi_transfer *t
	118	) {
766ed704	119	unsigned bits = t->bits_per_word;
9904f22a DB	120	unsigned count = t->len;
	121	const u32 *tx = t->tx_buf;
	122	u32 *rx = t->rx_buf;
	123
	124	while (likely(count > 3)) {
	125	u32 word = 0;
	126
	127	if (tx)
	128	word = *tx++;
	129	word = txrx_word(spi, ns, word, bits);
	130	if (rx)
	131	*rx++ = word;
	132	count -= 4;
	133	}
	134	return t->len - count;
	135	}
	136
ff9f4771	137	int spi_bitbang_setup_transfer(struct spi_device spi, struct spi_transfer t)
4cff33f9 ID	138	{
	139	struct spi_bitbang_cs *cs = spi->controller_state;
	140	u8 bits_per_word;
	141	u32 hz;
	142
	143	if (t) {
	144	bits_per_word = t->bits_per_word;
	145	hz = t->speed_hz;
	146	} else {
	147	bits_per_word = 0;
	148	hz = 0;
	149	}
	150
	151	/* spi_transfer level calls that work per-word */
	152	if (!bits_per_word)
	153	bits_per_word = spi->bits_per_word;
	154	if (bits_per_word <= 8)
	155	cs->txrx_bufs = bitbang_txrx_8;
	156	else if (bits_per_word <= 16)
	157	cs->txrx_bufs = bitbang_txrx_16;
	158	else if (bits_per_word <= 32)
	159	cs->txrx_bufs = bitbang_txrx_32;
	160	else
	161	return -EINVAL;
	162
	163	/* nsecs = (clock period)/2 */
	164	if (!hz)
	165	hz = spi->max_speed_hz;
1e316d75 DB	166	if (hz) {
	167	cs->nsecs = (1000000000/2) / hz;
	168	if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
	169	return -EINVAL;
	170	}
4cff33f9 ID	171
	172	return 0;
	173	}
ff9f4771	174	EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
4cff33f9	175
9904f22a DB	176	/**
	177	* spi_bitbang_setup - default setup for per-word I/O loops
	178	*/
	179	int spi_bitbang_setup(struct spi_device *spi)
	180	{
	181	struct spi_bitbang_cs *cs = spi->controller_state;
	182	struct spi_bitbang *bitbang;
	183
ccf77cc4 DB	184	bitbang = spi_master_get_devdata(spi->master);
ccf77cc4 DB	185
9904f22a	186	if (!cs) {
cff93c58	187	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
9904f22a DB	188	if (!cs)
	189	return -ENOMEM;
	190	spi->controller_state = cs;
	191	}
9904f22a	192
9904f22a DB	193	/* per-word shift register access, in hardware or bitbanging */
	194	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL\|SPI_CPHA)];
	195	if (!cs->txrx_word)
	196	return -EINVAL;
	197
7d0ec8b6 PN	198	if (bitbang->setup_transfer) {
	199	int retval = bitbang->setup_transfer(spi, NULL);
	200	if (retval < 0)
	201	return retval;
	202	}
9904f22a	203
7d077197	204	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
9904f22a DB	205
	206	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	207	* setup, unless the hardware defaults cooperate to avoid confusion
	208	* between normal (active low) and inverted chipselects.
	209	*/
	210
	211	/* deselect chip (low or high) */
c15f6ed3	212	mutex_lock(&bitbang->lock);
9904f22a	213	if (!bitbang->busy) {
8275c642	214	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
9904f22a DB	215	ndelay(cs->nsecs);
9904f22a DB	216	}
c15f6ed3	217	mutex_unlock(&bitbang->lock);
9904f22a DB	218
	219	return 0;
	220	}
	221	EXPORT_SYMBOL_GPL(spi_bitbang_setup);
	222
	223	/**
	224	* spi_bitbang_cleanup - default cleanup for per-word I/O loops
	225	*/
0ffa0285	226	void spi_bitbang_cleanup(struct spi_device *spi)
9904f22a DB	227	{
	228	kfree(spi->controller_state);
	229	}
	230	EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
	231
	232	static int spi_bitbang_bufs(struct spi_device spi, struct spi_transfer t)
	233	{
	234	struct spi_bitbang_cs *cs = spi->controller_state;
	235	unsigned nsecs = cs->nsecs;
	236
	237	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
	238	}
	239
	240	/----------------------------------------------------------------------/
	241
	242	/*
	243	* SECOND PART ... simple transfer queue runner.
	244	*
	245	* This costs a task context per controller, running the queue by
	246	* performing each transfer in sequence. Smarter hardware can queue
	247	* several DMA transfers at once, and process several controller queues
	248	* in parallel; this driver doesn't match such hardware very well.
	249	*
	250	* Drivers can provide word-at-a-time i/o primitives, or provide
	251	* transfer-at-a-time ones to leverage dma or fifo hardware.
	252	*/
2025172e MB	253
	254	static int spi_bitbang_prepare_hardware(struct spi_master *spi)
	255	{
cff93c58	256	struct spi_bitbang *bitbang;
2025172e MB	257
	258	bitbang = spi_master_get_devdata(spi);
	259
c15f6ed3	260	mutex_lock(&bitbang->lock);
2025172e	261	bitbang->busy = 1;
c15f6ed3	262	mutex_unlock(&bitbang->lock);
2025172e MB	263
	264	return 0;
	265	}
	266
d60990d5	267	static int spi_bitbang_transfer_one(struct spi_master *master,
91b30858	268	struct spi_message *m)
9904f22a	269	{
cff93c58	270	struct spi_bitbang *bitbang;
91b30858 MB	271	unsigned nsecs;
91b30858 MB	272	struct spi_transfer *t = NULL;
91b30858 MB	273	unsigned cs_change;
91b30858 MB	274	int status;
d60990d5	275	struct spi_device *spi = m->spi;
9904f22a	276
d60990d5	277	bitbang = spi_master_get_devdata(master);
9904f22a	278
91b30858 MB	279	/* FIXME this is made-up ... the correct value is known to
	280	* word-at-a-time bitbang code, and presumably chipselect()
	281	* should enforce these requirements too?
	282	*/
	283	nsecs = 100;
9904f22a	284
91b30858 MB	285	cs_change = 1;
91b30858 MB	286	status = 0;
9904f22a	287
cff93c58	288	list_for_each_entry(t, &m->transfers, transfer_list) {
9904f22a	289
e30d8f23 HK	290	if (bitbang->setup_transfer) {
	291	status = bitbang->setup_transfer(spi, t);
	292	if (status < 0)
	293	break;
9904f22a DB	294	}
9904f22a DB	295
91b30858 MB	296	/* set up default clock polarity, and activate chip;
	297	* this implicitly updates clock and spi modes as
	298	* previously recorded for this device via setup().
	299	* (and also deselects any other chip that might be
	300	* selected ...)
	301	*/
	302	if (cs_change) {
	303	bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
	304	ndelay(nsecs);
	305	}
	306	cs_change = t->cs_change;
	307	if (!t->tx_buf && !t->rx_buf && t->len) {
	308	status = -EINVAL;
	309	break;
	310	}
9904f22a	311
91b30858 MB	312	/* transfer data. the lower level code handles any
	313	* new dma mappings it needs. our caller always gave
	314	* us dma-safe buffers.
8275c642	315	*/
91b30858 MB	316	if (t->len) {
	317	/* REVISIT dma API still needs a designated
	318	* DMA_ADDR_INVALID; ~0 might be better.
	319	*/
	320	if (!m->is_dma_mapped)
	321	t->rx_dma = t->tx_dma = 0;
	322	status = bitbang->txrx_bufs(spi, t);
	323	}
	324	if (status > 0)
	325	m->actual_length += status;
	326	if (status != t->len) {
	327	/* always report some kind of error */
	328	if (status >= 0)
	329	status = -EREMOTEIO;
	330	break;
	331	}
	332	status = 0;
	333
	334	/* protocol tweaks before next transfer */
	335	if (t->delay_usecs)
	336	udelay(t->delay_usecs);
	337
cff93c58 JH	338	if (cs_change &&
cff93c58 JH	339	!list_is_last(&t->transfer_list, &m->transfers)) {
91b30858 MB	340	/* sometimes a short mid-message deselect of the chip
	341	* may be needed to terminate a mode or command
	342	*/
8275c642 VW	343	ndelay(nsecs);
	344	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
	345	ndelay(nsecs);
	346	}
91b30858 MB	347	}
	348
	349	m->status = status;
91b30858 MB	350
	351	/* normally deactivate chipselect ... unless no error and
	352	* cs_change has hinted that the next message will probably
	353	* be for this chip too.
	354	*/
	355	if (!(status == 0 && cs_change)) {
	356	ndelay(nsecs);
	357	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
	358	ndelay(nsecs);
	359	}
	360
d60990d5	361	spi_finalize_current_message(master);
9904f22a	362
2025172e	363	return status;
9904f22a DB	364	}
9904f22a DB	365
2025172e	366	static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
9904f22a	367	{
cff93c58	368	struct spi_bitbang *bitbang;
9904f22a	369
2025172e	370	bitbang = spi_master_get_devdata(spi);
9904f22a	371
c15f6ed3	372	mutex_lock(&bitbang->lock);
2025172e	373	bitbang->busy = 0;
c15f6ed3	374	mutex_unlock(&bitbang->lock);
9904f22a	375
2025172e	376	return 0;
9904f22a	377	}
9904f22a DB	378
	379	/----------------------------------------------------------------------/
	380
	381	/**
	382	* spi_bitbang_start - start up a polled/bitbanging SPI master driver
	383	* @bitbang: driver handle
	384	*
	385	* Caller should have zero-initialized all parts of the structure, and then
	386	* provided callbacks for chip selection and I/O loops. If the master has
	387	* a transfer method, its final step should call spi_bitbang_transfer; or,
	388	* that's the default if the transfer routine is not initialized. It should
	389	* also set up the bus number and number of chipselects.
	390	*
	391	* For i/o loops, provide callbacks either per-word (for bitbanging, or for
	392	* hardware that basically exposes a shift register) or per-spi_transfer
	393	* (which takes better advantage of hardware like fifos or DMA engines).
	394	*
7f8c7619 HPN	395	* Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
	396	* spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
	397	* master methods. Those methods are the defaults if the bitbang->txrx_bufs
	398	* routine isn't initialized.
9904f22a DB	399	*
	400	* This routine registers the spi_master, which will process requests in a
	401	* dedicated task, keeping IRQs unblocked most of the time. To stop
	402	* processing those requests, call spi_bitbang_stop().
702a4879 AL	403	*
	404	* On success, this routine will take a reference to master. The caller is
	405	* responsible for calling spi_bitbang_stop() to decrement the reference and
	406	* spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
	407	* leak.
9904f22a DB	408	*/
	409	int spi_bitbang_start(struct spi_bitbang *bitbang)
	410	{
7a5d8ca1	411	struct spi_master *master = bitbang->master;
702a4879	412	int ret;
9904f22a	413
7a5d8ca1	414	if (!master \|\| !bitbang->chipselect)
9904f22a DB	415	return -EINVAL;
9904f22a DB	416
c15f6ed3	417	mutex_init(&bitbang->lock);
9904f22a	418
7a5d8ca1 GL	419	if (!master->mode_bits)
7a5d8ca1 GL	420	master->mode_bits = SPI_CPOL \| SPI_CPHA \| bitbang->flags;
e7db06b5	421
2025172e MB	422	if (master->transfer \|\| master->transfer_one_message)
	423	return -EINVAL;
	424
	425	master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
	426	master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
	427	master->transfer_one_message = spi_bitbang_transfer_one;
	428
9904f22a DB	429	if (!bitbang->txrx_bufs) {
	430	bitbang->use_dma = 0;
	431	bitbang->txrx_bufs = spi_bitbang_bufs;
7a5d8ca1	432	if (!master->setup) {
ff9f4771 KG	433	if (!bitbang->setup_transfer)
	434	bitbang->setup_transfer =
	435	spi_bitbang_setup_transfer;
7a5d8ca1 GL	436	master->setup = spi_bitbang_setup;
7a5d8ca1 GL	437	master->cleanup = spi_bitbang_cleanup;
9904f22a	438	}
52ade736	439	}
9904f22a DB	440
	441	/* driver may get busy before register() returns, especially
	442	* if someone registered boardinfo for devices
	443	*/
702a4879 AL	444	ret = spi_register_master(spi_master_get(master));
	445	if (ret)
	446	spi_master_put(master);
	447
	448	return 0;
9904f22a DB	449	}
	450	EXPORT_SYMBOL_GPL(spi_bitbang_start);
	451
	452	/**
	453	* spi_bitbang_stop - stops the task providing spi communication
	454	*/
d9721ae1	455	void spi_bitbang_stop(struct spi_bitbang *bitbang)
9904f22a	456	{
a836f585	457	spi_unregister_master(bitbang->master);
9904f22a DB	458	}
	459	EXPORT_SYMBOL_GPL(spi_bitbang_stop);
	460
	461	MODULE_LICENSE("GPL");
	462