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spi: davinci: remove unused variable 'pdata'
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / davinci_spi.c
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358934a6
SP		 1/*
2 * Copyright (C) 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/module.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/dma-mapping.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/spi_bitbang.h>
5a0e3ad6 30#include <linux/slab.h>
358934a6
SP		 31
32#include <mach/spi.h>
33#include <mach/edma.h>
34
35#define SPI_NO_RESOURCE ((resource_size_t)-1)
36
37#define SPI_MAX_CHIPSELECT 2
38
39#define CS_DEFAULT 0xFF
40
41#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
42#define DAVINCI_DMA_DATA_TYPE_S8 0x01
43#define DAVINCI_DMA_DATA_TYPE_S16 0x02
44#define DAVINCI_DMA_DATA_TYPE_S32 0x04
45
46#define SPIFMT_PHASE_MASK BIT(16)
47#define SPIFMT_POLARITY_MASK BIT(17)
48#define SPIFMT_DISTIMER_MASK BIT(18)
49#define SPIFMT_SHIFTDIR_MASK BIT(20)
50#define SPIFMT_WAITENA_MASK BIT(21)
51#define SPIFMT_PARITYENA_MASK BIT(22)
52#define SPIFMT_ODD_PARITY_MASK BIT(23)
53#define SPIFMT_WDELAY_MASK 0x3f000000u
54#define SPIFMT_WDELAY_SHIFT 24
55#define SPIFMT_CHARLEN_MASK 0x0000001Fu
56
57/* SPIGCR1 */
58#define SPIGCR1_SPIENA_MASK 0x01000000u
59
60/* SPIPC0 */
61#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
62#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
63#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
64#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
65#define SPIPC0_EN1FUN_MASK BIT(1)
66#define SPIPC0_EN0FUN_MASK BIT(0)
67
68#define SPIINT_MASKALL 0x0101035F
69#define SPI_INTLVL_1 0x000001FFu
70#define SPI_INTLVL_0 0x00000000u
71
72/* SPIDAT1 */
73#define SPIDAT1_CSHOLD_SHIFT 28
74#define SPIDAT1_CSNR_SHIFT 16
75#define SPIGCR1_CLKMOD_MASK BIT(1)
76#define SPIGCR1_MASTER_MASK BIT(0)
77#define SPIGCR1_LOOPBACK_MASK BIT(16)
78
79/* SPIBUF */
80#define SPIBUF_TXFULL_MASK BIT(29)
81#define SPIBUF_RXEMPTY_MASK BIT(31)
82
83/* Error Masks */
84#define SPIFLG_DLEN_ERR_MASK BIT(0)
85#define SPIFLG_TIMEOUT_MASK BIT(1)
86#define SPIFLG_PARERR_MASK BIT(2)
87#define SPIFLG_DESYNC_MASK BIT(3)
88#define SPIFLG_BITERR_MASK BIT(4)
89#define SPIFLG_OVRRUN_MASK BIT(6)
90#define SPIFLG_RX_INTR_MASK BIT(8)
91#define SPIFLG_TX_INTR_MASK BIT(9)
92#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
93#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \
94 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
95 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
96 | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \
97 | SPIFLG_TX_INTR_MASK \
98 | SPIFLG_BUF_INIT_ACTIVE_MASK)
99
100#define SPIINT_DLEN_ERR_INTR BIT(0)
101#define SPIINT_TIMEOUT_INTR BIT(1)
102#define SPIINT_PARERR_INTR BIT(2)
103#define SPIINT_DESYNC_INTR BIT(3)
104#define SPIINT_BITERR_INTR BIT(4)
105#define SPIINT_OVRRUN_INTR BIT(6)
106#define SPIINT_RX_INTR BIT(8)
107#define SPIINT_TX_INTR BIT(9)
108#define SPIINT_DMA_REQ_EN BIT(16)
109#define SPIINT_ENABLE_HIGHZ BIT(24)
110
111#define SPI_T2CDELAY_SHIFT 16
112#define SPI_C2TDELAY_SHIFT 24
113
114/* SPI Controller registers */
115#define SPIGCR0 0x00
116#define SPIGCR1 0x04
117#define SPIINT 0x08
118#define SPILVL 0x0c
119#define SPIFLG 0x10
120#define SPIPC0 0x14
121#define SPIPC1 0x18
122#define SPIPC2 0x1c
123#define SPIPC3 0x20
124#define SPIPC4 0x24
125#define SPIPC5 0x28
126#define SPIPC6 0x2c
127#define SPIPC7 0x30
128#define SPIPC8 0x34
129#define SPIDAT0 0x38
130#define SPIDAT1 0x3c
131#define SPIBUF 0x40
132#define SPIEMU 0x44
133#define SPIDELAY 0x48
134#define SPIDEF 0x4c
135#define SPIFMT0 0x50
136#define SPIFMT1 0x54
137#define SPIFMT2 0x58
138#define SPIFMT3 0x5c
139#define TGINTVEC0 0x60
140#define TGINTVEC1 0x64
141
142struct davinci_spi_slave {
143 u32 cmd_to_write;
144 u32 clk_ctrl_to_write;
145 u32 bytes_per_word;
146 u8 active_cs;
147};
148
149/* We have 2 DMA channels per CS, one for RX and one for TX */
150struct davinci_spi_dma {
151 int dma_tx_channel;
152 int dma_rx_channel;
153 int dma_tx_sync_dev;
154 int dma_rx_sync_dev;
155 enum dma_event_q eventq;
156
157 struct completion dma_tx_completion;
158 struct completion dma_rx_completion;
159};
160
161/* SPI Controller driver's private data. */
162struct davinci_spi {
163 struct spi_bitbang bitbang;
164 struct clk *clk;
165
166 u8 version;
167 resource_size_t pbase;
168 void __iomem *base;
169 size_t region_size;
170 u32 irq;
171 struct completion done;
172
173 const void *tx;
174 void *rx;
175 u8 *tmp_buf;
176 int count;
177 struct davinci_spi_dma *dma_channels;
778e261e 178 struct davinci_spi_platform_data *pdata;
358934a6
SP		 179
180 void (*get_rx)(u32 rx_data, struct davinci_spi *);
181 u32 (*get_tx)(struct davinci_spi *);
182
183 struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];
184};
185
186static unsigned use_dma;
187
188static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
189{
190 u8 *rx = davinci_spi->rx;
191
192 *rx++ = (u8)data;
193 davinci_spi->rx = rx;
194}
195
196static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
197{
198 u16 *rx = davinci_spi->rx;
199
200 *rx++ = (u16)data;
201 davinci_spi->rx = rx;
202}
203
204static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
205{
206 u32 data;
207 const u8 *tx = davinci_spi->tx;
208
209 data = *tx++;
210 davinci_spi->tx = tx;
211 return data;
212}
213
214static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
215{
216 u32 data;
217 const u16 *tx = davinci_spi->tx;
218
219 data = *tx++;
220 davinci_spi->tx = tx;
221 return data;
222}
223
224static inline void set_io_bits(void __iomem *addr, u32 bits)
225{
226 u32 v = ioread32(addr);
227
228 v |= bits;
229 iowrite32(v, addr);
230}
231
232static inline void clear_io_bits(void __iomem *addr, u32 bits)
233{
234 u32 v = ioread32(addr);
235
236 v &= ~bits;
237 iowrite32(v, addr);
238}
239
240static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
241{
242 set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
243}
244
245static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
246{
247 clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
248}
249
250static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
251{
252 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
253
254 if (enable)
255 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
256 else
257 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
258}
259
260/*
261 * Interface to control the chip select signal
262 */
263static void davinci_spi_chipselect(struct spi_device *spi, int value)
264{
265 struct davinci_spi *davinci_spi;
266 struct davinci_spi_platform_data *pdata;
267 u32 data1_reg_val = 0;
268
269 davinci_spi = spi_master_get_devdata(spi->master);
270 pdata = davinci_spi->pdata;
271
272 /*
273 * Board specific chip select logic decides the polarity and cs
274 * line for the controller
275 */
276 if (value == BITBANG_CS_INACTIVE) {
277 set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
278
279 data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
280 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
281
282 while ((ioread32(davinci_spi->base + SPIBUF)
283 & SPIBUF_RXEMPTY_MASK) == 0)
284 cpu_relax();
285 }
286}
287
288/**
289 * davinci_spi_setup_transfer - This functions will determine transfer method
290 * @spi: spi device on which data transfer to be done
291 * @t: spi transfer in which transfer info is filled
292 *
293 * This function determines data transfer method (8/16/32 bit transfer).
294 * It will also set the SPI Clock Control register according to
295 * SPI slave device freq.
296 */
297static int davinci_spi_setup_transfer(struct spi_device *spi,
298 struct spi_transfer *t)
299{
300
301 struct davinci_spi *davinci_spi;
358934a6 302 u8 bits_per_word = 0;
0c2a2ae3 303 u32 hz = 0, prescale = 0, clkspeed;
358934a6
SP		 304
305 davinci_spi = spi_master_get_devdata(spi->master);
358934a6
SP		 306
307 if (t) {
308 bits_per_word = t->bits_per_word;
309 hz = t->speed_hz;
310 }
311
312 /* if bits_per_word is not set then set it default */
313 if (!bits_per_word)
314 bits_per_word = spi->bits_per_word;
315
316 /*
317 * Assign function pointer to appropriate transfer method
318 * 8bit, 16bit or 32bit transfer
319 */
320 if (bits_per_word <= 8 && bits_per_word >= 2) {
321 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
322 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
323 davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
324 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
325 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
326 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
327 davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
328 } else
329 return -EINVAL;
330
331 if (!hz)
332 hz = spi->max_speed_hz;
333
334 clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
335 spi->chip_select);
336 set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
337 spi->chip_select);
338
0c2a2ae3
TK		 339 clkspeed = clk_get_rate(davinci_spi->clk);
340 if (hz > clkspeed / 2)
341 prescale = 1 << 8;
342 if (hz < clkspeed / 256)
343 prescale = 255 << 8;
344 if (!prescale)
345 prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;
358934a6
SP		 346
347 clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
0c2a2ae3 348 set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
358934a6
SP		 349
350 return 0;
351}
352
353static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
354{
355 struct spi_device *spi = (struct spi_device *)data;
356 struct davinci_spi *davinci_spi;
357 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 358
359 davinci_spi = spi_master_get_devdata(spi->master);
360 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
358934a6
SP		 361
362 if (ch_status == DMA_COMPLETE)
363 edma_stop(davinci_spi_dma->dma_rx_channel);
364 else
365 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
366
367 complete(&davinci_spi_dma->dma_rx_completion);
368 /* We must disable the DMA RX request */
369 davinci_spi_set_dma_req(spi, 0);
370}
371
372static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
373{
374 struct spi_device *spi = (struct spi_device *)data;
375 struct davinci_spi *davinci_spi;
376 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 377
378 davinci_spi = spi_master_get_devdata(spi->master);
379 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
358934a6
SP		 380
381 if (ch_status == DMA_COMPLETE)
382 edma_stop(davinci_spi_dma->dma_tx_channel);
383 else
384 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
385
386 complete(&davinci_spi_dma->dma_tx_completion);
387 /* We must disable the DMA TX request */
388 davinci_spi_set_dma_req(spi, 0);
389}
390
391static int davinci_spi_request_dma(struct spi_device *spi)
392{
393 struct davinci_spi *davinci_spi;
394 struct davinci_spi_dma *davinci_spi_dma;
358934a6
SP		 395 struct device *sdev;
396 int r;
397
398 davinci_spi = spi_master_get_devdata(spi->master);
399 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
358934a6
SP		 400 sdev = davinci_spi->bitbang.master->dev.parent;
401
402 r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
403 davinci_spi_dma_rx_callback, spi,
404 davinci_spi_dma->eventq);
405 if (r < 0) {
406 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
407 return -EAGAIN;
408 }
409 davinci_spi_dma->dma_rx_channel = r;
410 r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
411 davinci_spi_dma_tx_callback, spi,
412 davinci_spi_dma->eventq);
413 if (r < 0) {
414 edma_free_channel(davinci_spi_dma->dma_rx_channel);
415 davinci_spi_dma->dma_rx_channel = -1;
416 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
417 return -EAGAIN;
418 }
419 davinci_spi_dma->dma_tx_channel = r;
420
421 return 0;
422}
423
424/**
425 * davinci_spi_setup - This functions will set default transfer method
426 * @spi: spi device on which data transfer to be done
427 *
428 * This functions sets the default transfer method.
429 */
358934a6
SP		 430static int davinci_spi_setup(struct spi_device *spi)
431{
432 int retval;
433 struct davinci_spi *davinci_spi;
434 struct davinci_spi_dma *davinci_spi_dma;
435 struct device *sdev;
436
437 davinci_spi = spi_master_get_devdata(spi->master);
438 sdev = davinci_spi->bitbang.master->dev.parent;
439
440 /* if bits per word length is zero then set it default 8 */
441 if (!spi->bits_per_word)
442 spi->bits_per_word = 8;
443
444 davinci_spi->slave[spi->chip_select].cmd_to_write = 0;
445
446 if (use_dma && davinci_spi->dma_channels) {
447 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
448
449 if ((davinci_spi_dma->dma_rx_channel == -1)
450 || (davinci_spi_dma->dma_tx_channel == -1)) {
451 retval = davinci_spi_request_dma(spi);
452 if (retval < 0)
453 return retval;
454 }
455 }
456
457 /*
458 * SPI in DaVinci and DA8xx operate between
459 * 600 KHz and 50 MHz
460 */
461 if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) {
462 dev_dbg(sdev, "Operating frequency is not in acceptable "
463 "range\n");
464 return -EINVAL;
465 }
466
467 /*
468 * Set up SPIFMTn register, unique to this chipselect.
469 *
470 * NOTE: we could do all of these with one write. Also, some
471 * of the "version 2" features are found in chips that don't
472 * support all of them...
473 */
474 if (spi->mode & SPI_LSB_FIRST)
475 set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
476 spi->chip_select);
477 else
478 clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
479 spi->chip_select);
480
481 if (spi->mode & SPI_CPOL)
482 set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
483 spi->chip_select);
484 else
485 clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
486 spi->chip_select);
487
488 if (!(spi->mode & SPI_CPHA))
489 set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
490 spi->chip_select);
491 else
492 clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
493 spi->chip_select);
494
495 /*
496 * Version 1 hardware supports two basic SPI modes:
497 * - Standard SPI mode uses 4 pins, with chipselect
498 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
499 * (distinct from SPI_3WIRE, with just one data wire;
500 * or similar variants without MOSI or without MISO)
501 *
502 * Version 2 hardware supports an optional handshaking signal,
503 * so it can support two more modes:
504 * - 5 pin SPI variant is standard SPI plus SPI_READY
505 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
506 */
507
508 if (davinci_spi->version == SPI_VERSION_2) {
509 clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
510 spi->chip_select);
511 set_fmt_bits(davinci_spi->base,
512 (davinci_spi->pdata->wdelay
513 << SPIFMT_WDELAY_SHIFT)
514 & SPIFMT_WDELAY_MASK,
515 spi->chip_select);
516
517 if (davinci_spi->pdata->odd_parity)
518 set_fmt_bits(davinci_spi->base,
519 SPIFMT_ODD_PARITY_MASK,
520 spi->chip_select);
521 else
522 clear_fmt_bits(davinci_spi->base,
523 SPIFMT_ODD_PARITY_MASK,
524 spi->chip_select);
525
526 if (davinci_spi->pdata->parity_enable)
527 set_fmt_bits(davinci_spi->base,
528 SPIFMT_PARITYENA_MASK,
529 spi->chip_select);
530 else
531 clear_fmt_bits(davinci_spi->base,
532 SPIFMT_PARITYENA_MASK,
533 spi->chip_select);
534
535 if (davinci_spi->pdata->wait_enable)
536 set_fmt_bits(davinci_spi->base,
537 SPIFMT_WAITENA_MASK,
538 spi->chip_select);
539 else
540 clear_fmt_bits(davinci_spi->base,
541 SPIFMT_WAITENA_MASK,
542 spi->chip_select);
543
544 if (davinci_spi->pdata->timer_disable)
545 set_fmt_bits(davinci_spi->base,
546 SPIFMT_DISTIMER_MASK,
547 spi->chip_select);
548 else
549 clear_fmt_bits(davinci_spi->base,
550 SPIFMT_DISTIMER_MASK,
551 spi->chip_select);
552 }
553
554 retval = davinci_spi_setup_transfer(spi, NULL);
555
556 return retval;
557}
558
559static void davinci_spi_cleanup(struct spi_device *spi)
560{
561 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
562 struct davinci_spi_dma *davinci_spi_dma;
563
564 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
565
566 if (use_dma && davinci_spi->dma_channels) {
567 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
568
569 if ((davinci_spi_dma->dma_rx_channel != -1)
570 && (davinci_spi_dma->dma_tx_channel != -1)) {
571 edma_free_channel(davinci_spi_dma->dma_tx_channel);
572 edma_free_channel(davinci_spi_dma->dma_rx_channel);
573 }
574 }
575}
576
577static int davinci_spi_bufs_prep(struct spi_device *spi,
578 struct davinci_spi *davinci_spi)
579{
580 int op_mode = 0;
581
582 /*
583 * REVISIT unless devices disagree about SPI_LOOP or
584 * SPI_READY (SPI_NO_CS only allows one device!), this
585 * should not need to be done before each message...
586 * optimize for both flags staying cleared.
587 */
588
589 op_mode = SPIPC0_DIFUN_MASK
590 | SPIPC0_DOFUN_MASK
591 | SPIPC0_CLKFUN_MASK;
592 if (!(spi->mode & SPI_NO_CS))
593 op_mode |= 1 << spi->chip_select;
594 if (spi->mode & SPI_READY)
595 op_mode |= SPIPC0_SPIENA_MASK;
596
597 iowrite32(op_mode, davinci_spi->base + SPIPC0);
598
599 if (spi->mode & SPI_LOOP)
600 set_io_bits(davinci_spi->base + SPIGCR1,
601 SPIGCR1_LOOPBACK_MASK);
602 else
603 clear_io_bits(davinci_spi->base + SPIGCR1,
604 SPIGCR1_LOOPBACK_MASK);
605
606 return 0;
607}
608
609static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
610 int int_status)
611{
612 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
613
614 if (int_status & SPIFLG_TIMEOUT_MASK) {
615 dev_dbg(sdev, "SPI Time-out Error\n");
616 return -ETIMEDOUT;
617 }
618 if (int_status & SPIFLG_DESYNC_MASK) {
619 dev_dbg(sdev, "SPI Desynchronization Error\n");
620 return -EIO;
621 }
622 if (int_status & SPIFLG_BITERR_MASK) {
623 dev_dbg(sdev, "SPI Bit error\n");
624 return -EIO;
625 }
626
627 if (davinci_spi->version == SPI_VERSION_2) {
628 if (int_status & SPIFLG_DLEN_ERR_MASK) {
629 dev_dbg(sdev, "SPI Data Length Error\n");
630 return -EIO;
631 }
632 if (int_status & SPIFLG_PARERR_MASK) {
633 dev_dbg(sdev, "SPI Parity Error\n");
634 return -EIO;
635 }
636 if (int_status & SPIFLG_OVRRUN_MASK) {
637 dev_dbg(sdev, "SPI Data Overrun error\n");
638 return -EIO;
639 }
640 if (int_status & SPIFLG_TX_INTR_MASK) {
641 dev_dbg(sdev, "SPI TX intr bit set\n");
642 return -EIO;
643 }
644 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
645 dev_dbg(sdev, "SPI Buffer Init Active\n");
646 return -EBUSY;
647 }
648 }
649
650 return 0;
651}
652
653/**
654 * davinci_spi_bufs - functions which will handle transfer data
655 * @spi: spi device on which data transfer to be done
656 * @t: spi transfer in which transfer info is filled
657 *
658 * This function will put data to be transferred into data register
659 * of SPI controller and then wait until the completion will be marked
660 * by the IRQ Handler.
661 */
662static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
663{
664 struct davinci_spi *davinci_spi;
665 int int_status, count, ret;
666 u8 conv, tmp;
667 u32 tx_data, data1_reg_val;
668 u32 buf_val, flg_val;
669 struct davinci_spi_platform_data *pdata;
670
671 davinci_spi = spi_master_get_devdata(spi->master);
672 pdata = davinci_spi->pdata;
673
674 davinci_spi->tx = t->tx_buf;
675 davinci_spi->rx = t->rx_buf;
676
677 /* convert len to words based on bits_per_word */
678 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
679 davinci_spi->count = t->len / conv;
680
681 INIT_COMPLETION(davinci_spi->done);
682
683 ret = davinci_spi_bufs_prep(spi, davinci_spi);
684 if (ret)
685 return ret;
686
687 /* Enable SPI */
688 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
689
690 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
691 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
692 davinci_spi->base + SPIDELAY);
693
694 count = davinci_spi->count;
695 data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
696 tmp = ~(0x1 << spi->chip_select);
697
698 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
699
700 data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
701
702 while ((ioread32(davinci_spi->base + SPIBUF)
703 & SPIBUF_RXEMPTY_MASK) == 0)
704 cpu_relax();
705
706 /* Determine the command to execute READ or WRITE */
707 if (t->tx_buf) {
708 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
709
710 while (1) {
711 tx_data = davinci_spi->get_tx(davinci_spi);
712
713 data1_reg_val &= ~(0xFFFF);
714 data1_reg_val |= (0xFFFF & tx_data);
715
716 buf_val = ioread32(davinci_spi->base + SPIBUF);
717 if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
718 iowrite32(data1_reg_val,
719 davinci_spi->base + SPIDAT1);
720
721 count--;
722 }
723 while (ioread32(davinci_spi->base + SPIBUF)
724 & SPIBUF_RXEMPTY_MASK)
725 cpu_relax();
726
727 /* getting the returned byte */
728 if (t->rx_buf) {
729 buf_val = ioread32(davinci_spi->base + SPIBUF);
730 davinci_spi->get_rx(buf_val, davinci_spi);
731 }
732 if (count <= 0)
733 break;
734 }
735 } else {
736 if (pdata->poll_mode) {
737 while (1) {
738 /* keeps the serial clock going */
739 if ((ioread32(davinci_spi->base + SPIBUF)
740 & SPIBUF_TXFULL_MASK) == 0)
741 iowrite32(data1_reg_val,
742 davinci_spi->base + SPIDAT1);
743
744 while (ioread32(davinci_spi->base + SPIBUF) &
745 SPIBUF_RXEMPTY_MASK)
746 cpu_relax();
747
748 flg_val = ioread32(davinci_spi->base + SPIFLG);
749 buf_val = ioread32(davinci_spi->base + SPIBUF);
750
751 davinci_spi->get_rx(buf_val, davinci_spi);
752
753 count--;
754 if (count <= 0)
755 break;
756 }
757 } else { /* Receive in Interrupt mode */
758 int i;
759
760 for (i = 0; i < davinci_spi->count; i++) {
761 set_io_bits(davinci_spi->base + SPIINT,
762 SPIINT_BITERR_INTR
763 | SPIINT_OVRRUN_INTR
764 | SPIINT_RX_INTR);
765
766 iowrite32(data1_reg_val,
767 davinci_spi->base + SPIDAT1);
768
769 while (ioread32(davinci_spi->base + SPIINT) &
770 SPIINT_RX_INTR)
771 cpu_relax();
772 }
773 iowrite32((data1_reg_val & 0x0ffcffff),
774 davinci_spi->base + SPIDAT1);
775 }
776 }
777
778 /*
779 * Check for bit error, desync error,parity error,timeout error and
780 * receive overflow errors
781 */
782 int_status = ioread32(davinci_spi->base + SPIFLG);
783
784 ret = davinci_spi_check_error(davinci_spi, int_status);
785 if (ret != 0)
786 return ret;
787
788 /* SPI Framework maintains the count only in bytes so convert back */
789 davinci_spi->count *= conv;
790
791 return t->len;
792}
793
794#define DAVINCI_DMA_DATA_TYPE_S8 0x01
795#define DAVINCI_DMA_DATA_TYPE_S16 0x02
796#define DAVINCI_DMA_DATA_TYPE_S32 0x04
797
798static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
799{
800 struct davinci_spi *davinci_spi;
801 int int_status = 0;
802 int count, temp_count;
803 u8 conv = 1;
804 u8 tmp;
805 u32 data1_reg_val;
806 struct davinci_spi_dma *davinci_spi_dma;
807 int word_len, data_type, ret;
808 unsigned long tx_reg, rx_reg;
809 struct davinci_spi_platform_data *pdata;
810 struct device *sdev;
811
812 davinci_spi = spi_master_get_devdata(spi->master);
813 pdata = davinci_spi->pdata;
814 sdev = davinci_spi->bitbang.master->dev.parent;
815
816 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
817
818 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
819 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
820
821 davinci_spi->tx = t->tx_buf;
822 davinci_spi->rx = t->rx_buf;
823
824 /* convert len to words based on bits_per_word */
825 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
826 davinci_spi->count = t->len / conv;
827
828 INIT_COMPLETION(davinci_spi->done);
829
830 init_completion(&davinci_spi_dma->dma_rx_completion);
831 init_completion(&davinci_spi_dma->dma_tx_completion);
832
833 word_len = conv * 8;
834
835 if (word_len <= 8)
836 data_type = DAVINCI_DMA_DATA_TYPE_S8;
837 else if (word_len <= 16)
838 data_type = DAVINCI_DMA_DATA_TYPE_S16;
839 else if (word_len <= 32)
840 data_type = DAVINCI_DMA_DATA_TYPE_S32;
841 else
842 return -EINVAL;
843
844 ret = davinci_spi_bufs_prep(spi, davinci_spi);
845 if (ret)
846 return ret;
847
848 /* Put delay val if required */
849 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
850 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
851 davinci_spi->base + SPIDELAY);
852
853 count = davinci_spi->count; /* the number of elements */
854 data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
855
856 /* CS default = 0xFF */
857 tmp = ~(0x1 << spi->chip_select);
858
859 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
860
861 data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
862
863 /* disable all interrupts for dma transfers */
864 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
865 /* Disable SPI to write configuration bits in SPIDAT */
866 clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
867 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
868 /* Enable SPI */
869 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
870
871 while ((ioread32(davinci_spi->base + SPIBUF)
872 & SPIBUF_RXEMPTY_MASK) == 0)
873 cpu_relax();
874
875
876 if (t->tx_buf) {
877 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
878 DMA_TO_DEVICE);
879 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
880 dev_dbg(sdev, "Unable to DMA map a %d bytes"
881 " TX buffer\n", count);
882 return -ENOMEM;
883 }
884 temp_count = count;
885 } else {
886 /* We need TX clocking for RX transaction */
887 t->tx_dma = dma_map_single(&spi->dev,
888 (void *)davinci_spi->tmp_buf, count + 1,
889 DMA_TO_DEVICE);
890 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
891 dev_dbg(sdev, "Unable to DMA map a %d bytes"
892 " TX tmp buffer\n", count);
893 return -ENOMEM;
894 }
895 temp_count = count + 1;
896 }
897
898 edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
899 data_type, temp_count, 1, 0, ASYNC);
900 edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
901 edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
902 edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
903 edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
904
905 if (t->rx_buf) {
906 /* initiate transaction */
907 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
908
909 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
910 DMA_FROM_DEVICE);
911 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
912 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
913 count);
914 if (t->tx_buf != NULL)
915 dma_unmap_single(NULL, t->tx_dma,
916 count, DMA_TO_DEVICE);
917 return -ENOMEM;
918 }
919 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
920 data_type, count, 1, 0, ASYNC);
921 edma_set_src(davinci_spi_dma->dma_rx_channel,
922 rx_reg, INCR, W8BIT);
923 edma_set_dest(davinci_spi_dma->dma_rx_channel,
924 t->rx_dma, INCR, W8BIT);
925 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
926 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
927 data_type, 0);
928 }
929
930 if ((t->tx_buf) || (t->rx_buf))
931 edma_start(davinci_spi_dma->dma_tx_channel);
932
933 if (t->rx_buf)
934 edma_start(davinci_spi_dma->dma_rx_channel);
935
936 if ((t->rx_buf) || (t->tx_buf))
937 davinci_spi_set_dma_req(spi, 1);
938
939 if (t->tx_buf)
940 wait_for_completion_interruptible(
941 &davinci_spi_dma->dma_tx_completion);
942
943 if (t->rx_buf)
944 wait_for_completion_interruptible(
945 &davinci_spi_dma->dma_rx_completion);
946
947 dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
948
949 if (t->rx_buf)
950 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
951
952 /*
953 * Check for bit error, desync error,parity error,timeout error and
954 * receive overflow errors
955 */
956 int_status = ioread32(davinci_spi->base + SPIFLG);
957
958 ret = davinci_spi_check_error(davinci_spi, int_status);
959 if (ret != 0)
960 return ret;
961
962 /* SPI Framework maintains the count only in bytes so convert back */
963 davinci_spi->count *= conv;
964
965 return t->len;
966}
967
968/**
969 * davinci_spi_irq - IRQ handler for DaVinci SPI
970 * @irq: IRQ number for this SPI Master
971 * @context_data: structure for SPI Master controller davinci_spi
972 */
973static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
974{
975 struct davinci_spi *davinci_spi = context_data;
976 u32 int_status, rx_data = 0;
977 irqreturn_t ret = IRQ_NONE;
978
979 int_status = ioread32(davinci_spi->base + SPIFLG);
980
981 while ((int_status & SPIFLG_RX_INTR_MASK)) {
982 if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
983 ret = IRQ_HANDLED;
984
985 rx_data = ioread32(davinci_spi->base + SPIBUF);
986 davinci_spi->get_rx(rx_data, davinci_spi);
987
988 /* Disable Receive Interrupt */
989 iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
990 davinci_spi->base + SPIINT);
991 } else
992 (void)davinci_spi_check_error(davinci_spi, int_status);
993
994 int_status = ioread32(davinci_spi->base + SPIFLG);
995 }
996
997 return ret;
998}
999
1000/**
1001 * davinci_spi_probe - probe function for SPI Master Controller
1002 * @pdev: platform_device structure which contains plateform specific data
1003 */
1004static int davinci_spi_probe(struct platform_device *pdev)
1005{
1006 struct spi_master *master;
1007 struct davinci_spi *davinci_spi;
1008 struct davinci_spi_platform_data *pdata;
1009 struct resource *r, *mem;
1010 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
1011 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
1012 resource_size_t dma_eventq = SPI_NO_RESOURCE;
1013 int i = 0, ret = 0;
1014
1015 pdata = pdev->dev.platform_data;
1016 if (pdata == NULL) {
1017 ret = -ENODEV;
1018 goto err;
1019 }
1020
1021 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
1022 if (master == NULL) {
1023 ret = -ENOMEM;
1024 goto err;
1025 }
1026
1027 dev_set_drvdata(&pdev->dev, master);
1028
1029 davinci_spi = spi_master_get_devdata(master);
1030 if (davinci_spi == NULL) {
1031 ret = -ENOENT;
1032 goto free_master;
1033 }
1034
1035 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1036 if (r == NULL) {
1037 ret = -ENOENT;
1038 goto free_master;
1039 }
1040
1041 davinci_spi->pbase = r->start;
1042 davinci_spi->region_size = resource_size(r);
1043 davinci_spi->pdata = pdata;
1044
1045 mem = request_mem_region(r->start, davinci_spi->region_size,
1046 pdev->name);
1047 if (mem == NULL) {
1048 ret = -EBUSY;
1049 goto free_master;
1050 }
1051
1052 davinci_spi->base = (struct davinci_spi_reg __iomem *)
1053 ioremap(r->start, davinci_spi->region_size);
1054 if (davinci_spi->base == NULL) {
1055 ret = -ENOMEM;
1056 goto release_region;
1057 }
1058
1059 davinci_spi->irq = platform_get_irq(pdev, 0);
1060 if (davinci_spi->irq <= 0) {
1061 ret = -EINVAL;
1062 goto unmap_io;
1063 }
1064
1065 ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
1066 dev_name(&pdev->dev), davinci_spi);
1067 if (ret)
1068 goto unmap_io;
1069
1070 /* Allocate tmp_buf for tx_buf */
1071 davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
1072 if (davinci_spi->tmp_buf == NULL) {
1073 ret = -ENOMEM;
1074 goto irq_free;
1075 }
1076
1077 davinci_spi->bitbang.master = spi_master_get(master);
1078 if (davinci_spi->bitbang.master == NULL) {
1079 ret = -ENODEV;
1080 goto free_tmp_buf;
1081 }
1082
1083 davinci_spi->clk = clk_get(&pdev->dev, NULL);
1084 if (IS_ERR(davinci_spi->clk)) {
1085 ret = -ENODEV;
1086 goto put_master;
1087 }
1088 clk_enable(davinci_spi->clk);
1089
358934a6
SP		 1090 master->bus_num = pdev->id;
1091 master->num_chipselect = pdata->num_chipselect;
1092 master->setup = davinci_spi_setup;
1093 master->cleanup = davinci_spi_cleanup;
1094
1095 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
1096 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
1097
1098 davinci_spi->version = pdata->version;
1099 use_dma = pdata->use_dma;
1100
1101 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
1102 if (davinci_spi->version == SPI_VERSION_2)
1103 davinci_spi->bitbang.flags |= SPI_READY;
1104
1105 if (use_dma) {
778e261e
BN		 1106 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1107 if (r)
1108 dma_rx_chan = r->start;
1109 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1110 if (r)
1111 dma_tx_chan = r->start;
1112 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1113 if (r)
1114 dma_eventq = r->start;
358934a6
SP		 1115 }
1116
1117 if (!use_dma ||
1118 dma_rx_chan == SPI_NO_RESOURCE ||
1119 dma_tx_chan == SPI_NO_RESOURCE ||
1120 dma_eventq == SPI_NO_RESOURCE) {
1121 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
1122 use_dma = 0;
1123 } else {
1124 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
1125 davinci_spi->dma_channels = kzalloc(master->num_chipselect
1126 * sizeof(struct davinci_spi_dma), GFP_KERNEL);
1127 if (davinci_spi->dma_channels == NULL) {
1128 ret = -ENOMEM;
1129 goto free_clk;
1130 }
1131
1132 for (i = 0; i < master->num_chipselect; i++) {
1133 davinci_spi->dma_channels[i].dma_rx_channel = -1;
1134 davinci_spi->dma_channels[i].dma_rx_sync_dev =
1135 dma_rx_chan;
1136 davinci_spi->dma_channels[i].dma_tx_channel = -1;
1137 davinci_spi->dma_channels[i].dma_tx_sync_dev =
1138 dma_tx_chan;
1139 davinci_spi->dma_channels[i].eventq = dma_eventq;
1140 }
1141 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
1142 "Using RX channel = %d , TX channel = %d and "
1143 "event queue = %d", dma_rx_chan, dma_tx_chan,
1144 dma_eventq);
1145 }
1146
1147 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
1148 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1149
1150 init_completion(&davinci_spi->done);
1151
1152 /* Reset In/OUT SPI module */
1153 iowrite32(0, davinci_spi->base + SPIGCR0);
1154 udelay(100);
1155 iowrite32(1, davinci_spi->base + SPIGCR0);
1156
1157 /* Clock internal */
1158 if (davinci_spi->pdata->clk_internal)
1159 set_io_bits(davinci_spi->base + SPIGCR1,
1160 SPIGCR1_CLKMOD_MASK);
1161 else
1162 clear_io_bits(davinci_spi->base + SPIGCR1,
1163 SPIGCR1_CLKMOD_MASK);
1164
1165 /* master mode default */
1166 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1167
1168 if (davinci_spi->pdata->intr_level)
1169 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1170 else
1171 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1172
1173 ret = spi_bitbang_start(&davinci_spi->bitbang);
1174 if (ret)
1175 goto free_clk;
1176
3b740b10 1177 dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
358934a6
SP		 1178
1179 if (!pdata->poll_mode)
1180 dev_info(&pdev->dev, "Operating in interrupt mode"
1181 " using IRQ %d\n", davinci_spi->irq);
1182
1183 return ret;
1184
1185free_clk:
1186 clk_disable(davinci_spi->clk);
1187 clk_put(davinci_spi->clk);
1188put_master:
1189 spi_master_put(master);
1190free_tmp_buf:
1191 kfree(davinci_spi->tmp_buf);
1192irq_free:
1193 free_irq(davinci_spi->irq, davinci_spi);
1194unmap_io:
1195 iounmap(davinci_spi->base);
1196release_region:
1197 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1198free_master:
1199 kfree(master);
1200err:
1201 return ret;
1202}
1203
1204/**
1205 * davinci_spi_remove - remove function for SPI Master Controller
1206 * @pdev: platform_device structure which contains plateform specific data
1207 *
1208 * This function will do the reverse action of davinci_spi_probe function
1209 * It will free the IRQ and SPI controller's memory region.
1210 * It will also call spi_bitbang_stop to destroy the work queue which was
1211 * created by spi_bitbang_start.
1212 */
1213static int __exit davinci_spi_remove(struct platform_device *pdev)
1214{
1215 struct davinci_spi *davinci_spi;
1216 struct spi_master *master;
1217
1218 master = dev_get_drvdata(&pdev->dev);
1219 davinci_spi = spi_master_get_devdata(master);
1220
1221 spi_bitbang_stop(&davinci_spi->bitbang);
1222
1223 clk_disable(davinci_spi->clk);
1224 clk_put(davinci_spi->clk);
1225 spi_master_put(master);
1226 kfree(davinci_spi->tmp_buf);
1227 free_irq(davinci_spi->irq, davinci_spi);
1228 iounmap(davinci_spi->base);
1229 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1230
1231 return 0;
1232}
1233
1234static struct platform_driver davinci_spi_driver = {
1235 .driver.name = "spi_davinci",
1236 .remove = __exit_p(davinci_spi_remove),
1237};
1238
1239static int __init davinci_spi_init(void)
1240{
1241 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1242}
1243module_init(davinci_spi_init);
1244
1245static void __exit davinci_spi_exit(void)
1246{
1247 platform_driver_unregister(&davinci_spi_driver);
1248}
1249module_exit(davinci_spi_exit);
1250
1251MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1252MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)