Commit | Line | Data |
---|---|---|
754ce4f2 HS |
1 | /* |
2 | * Driver for Atmel AT32 and AT91 SPI Controllers | |
3 | * | |
4 | * Copyright (C) 2006 Atmel Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/spi/spi.h> | |
21 | ||
22 | #include <asm/io.h> | |
23 | #include <asm/arch/board.h> | |
24 | #include <asm/arch/gpio.h> | |
bb2d1c36 | 25 | #include <asm/arch/cpu.h> |
bb2d1c36 | 26 | |
754ce4f2 HS |
27 | #include "atmel_spi.h" |
28 | ||
29 | /* | |
30 | * The core SPI transfer engine just talks to a register bank to set up | |
31 | * DMA transfers; transfer queue progress is driven by IRQs. The clock | |
32 | * framework provides the base clock, subdivided for each spi_device. | |
33 | * | |
34 | * Newer controllers, marked with "new_1" flag, have: | |
35 | * - CR.LASTXFER | |
36 | * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) | |
37 | * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) | |
38 | * - SPI_CSRx.CSAAT | |
39 | * - SPI_CSRx.SBCR allows faster clocking | |
40 | */ | |
41 | struct atmel_spi { | |
42 | spinlock_t lock; | |
43 | ||
44 | void __iomem *regs; | |
45 | int irq; | |
46 | struct clk *clk; | |
47 | struct platform_device *pdev; | |
48 | unsigned new_1:1; | |
49 | ||
50 | u8 stopping; | |
51 | struct list_head queue; | |
52 | struct spi_transfer *current_transfer; | |
53 | unsigned long remaining_bytes; | |
54 | ||
55 | void *buffer; | |
56 | dma_addr_t buffer_dma; | |
57 | }; | |
58 | ||
59 | #define BUFFER_SIZE PAGE_SIZE | |
60 | #define INVALID_DMA_ADDRESS 0xffffffff | |
61 | ||
62 | /* | |
63 | * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby | |
64 | * they assume that spi slave device state will not change on deselect, so | |
65 | * that automagic deselection is OK. Not so! Workaround uses nCSx pins | |
66 | * as GPIOs; or newer controllers have CSAAT and friends. | |
67 | * | |
68 | * Since the CSAAT functionality is a bit weird on newer controllers | |
69 | * as well, we use GPIO to control nCSx pins on all controllers. | |
70 | */ | |
71 | ||
72 | static inline void cs_activate(struct spi_device *spi) | |
73 | { | |
74 | unsigned gpio = (unsigned) spi->controller_data; | |
75 | unsigned active = spi->mode & SPI_CS_HIGH; | |
76 | ||
77 | dev_dbg(&spi->dev, "activate %u%s\n", gpio, active ? " (high)" : ""); | |
78 | gpio_set_value(gpio, active); | |
79 | } | |
80 | ||
81 | static inline void cs_deactivate(struct spi_device *spi) | |
82 | { | |
83 | unsigned gpio = (unsigned) spi->controller_data; | |
84 | unsigned active = spi->mode & SPI_CS_HIGH; | |
85 | ||
86 | dev_dbg(&spi->dev, "DEactivate %u%s\n", gpio, active ? " (low)" : ""); | |
87 | gpio_set_value(gpio, !active); | |
88 | } | |
89 | ||
90 | /* | |
91 | * Submit next transfer for DMA. | |
92 | * lock is held, spi irq is blocked | |
93 | */ | |
94 | static void atmel_spi_next_xfer(struct spi_master *master, | |
95 | struct spi_message *msg) | |
96 | { | |
97 | struct atmel_spi *as = spi_master_get_devdata(master); | |
98 | struct spi_transfer *xfer; | |
99 | u32 len; | |
100 | dma_addr_t tx_dma, rx_dma; | |
101 | ||
102 | xfer = as->current_transfer; | |
103 | if (!xfer || as->remaining_bytes == 0) { | |
104 | if (xfer) | |
105 | xfer = list_entry(xfer->transfer_list.next, | |
106 | struct spi_transfer, transfer_list); | |
107 | else | |
108 | xfer = list_entry(msg->transfers.next, | |
109 | struct spi_transfer, transfer_list); | |
110 | as->remaining_bytes = xfer->len; | |
111 | as->current_transfer = xfer; | |
112 | } | |
113 | ||
114 | len = as->remaining_bytes; | |
115 | ||
5a9a62bb HS |
116 | tx_dma = xfer->tx_dma + xfer->len - len; |
117 | rx_dma = xfer->rx_dma + xfer->len - len; | |
754ce4f2 HS |
118 | |
119 | /* use scratch buffer only when rx or tx data is unspecified */ | |
5a9a62bb | 120 | if (!xfer->rx_buf) { |
754ce4f2 HS |
121 | rx_dma = as->buffer_dma; |
122 | if (len > BUFFER_SIZE) | |
123 | len = BUFFER_SIZE; | |
124 | } | |
5a9a62bb | 125 | if (!xfer->tx_buf) { |
754ce4f2 HS |
126 | tx_dma = as->buffer_dma; |
127 | if (len > BUFFER_SIZE) | |
128 | len = BUFFER_SIZE; | |
129 | memset(as->buffer, 0, len); | |
130 | dma_sync_single_for_device(&as->pdev->dev, | |
131 | as->buffer_dma, len, DMA_TO_DEVICE); | |
132 | } | |
133 | ||
134 | spi_writel(as, RPR, rx_dma); | |
135 | spi_writel(as, TPR, tx_dma); | |
136 | ||
137 | as->remaining_bytes -= len; | |
138 | if (msg->spi->bits_per_word > 8) | |
139 | len >>= 1; | |
140 | ||
141 | /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer" | |
142 | * mechanism might help avoid the IRQ latency between transfers | |
143 | * | |
144 | * We're also waiting for ENDRX before we start the next | |
145 | * transfer because we need to handle some difficult timing | |
146 | * issues otherwise. If we wait for ENDTX in one transfer and | |
147 | * then starts waiting for ENDRX in the next, it's difficult | |
148 | * to tell the difference between the ENDRX interrupt we're | |
149 | * actually waiting for and the ENDRX interrupt of the | |
150 | * previous transfer. | |
151 | * | |
152 | * It should be doable, though. Just not now... | |
153 | */ | |
154 | spi_writel(as, TNCR, 0); | |
155 | spi_writel(as, RNCR, 0); | |
156 | spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES)); | |
157 | ||
158 | dev_dbg(&msg->spi->dev, | |
159 | " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n", | |
160 | xfer, xfer->len, xfer->tx_buf, xfer->tx_dma, | |
161 | xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR)); | |
162 | ||
163 | spi_writel(as, TCR, len); | |
164 | spi_writel(as, RCR, len); | |
165 | spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); | |
166 | } | |
167 | ||
168 | static void atmel_spi_next_message(struct spi_master *master) | |
169 | { | |
170 | struct atmel_spi *as = spi_master_get_devdata(master); | |
171 | struct spi_message *msg; | |
172 | u32 mr; | |
173 | ||
174 | BUG_ON(as->current_transfer); | |
175 | ||
176 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
177 | ||
178 | /* Select the chip */ | |
179 | mr = spi_readl(as, MR); | |
180 | mr = SPI_BFINS(PCS, ~(1 << msg->spi->chip_select), mr); | |
181 | spi_writel(as, MR, mr); | |
182 | cs_activate(msg->spi); | |
183 | ||
184 | atmel_spi_next_xfer(master, msg); | |
185 | } | |
186 | ||
8da0859a DB |
187 | /* |
188 | * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: | |
189 | * - The buffer is either valid for CPU access, else NULL | |
190 | * - If the buffer is valid, so is its DMA addresss | |
191 | * | |
192 | * This driver manages the dma addresss unless message->is_dma_mapped. | |
193 | */ | |
194 | static int | |
754ce4f2 HS |
195 | atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) |
196 | { | |
8da0859a DB |
197 | struct device *dev = &as->pdev->dev; |
198 | ||
754ce4f2 | 199 | xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; |
8da0859a DB |
200 | if (xfer->tx_buf) { |
201 | xfer->tx_dma = dma_map_single(dev, | |
754ce4f2 HS |
202 | (void *) xfer->tx_buf, xfer->len, |
203 | DMA_TO_DEVICE); | |
8da0859a DB |
204 | if (dma_mapping_error(xfer->tx_dma)) |
205 | return -ENOMEM; | |
206 | } | |
207 | if (xfer->rx_buf) { | |
208 | xfer->rx_dma = dma_map_single(dev, | |
754ce4f2 HS |
209 | xfer->rx_buf, xfer->len, |
210 | DMA_FROM_DEVICE); | |
8da0859a DB |
211 | if (dma_mapping_error(xfer->tx_dma)) { |
212 | if (xfer->tx_buf) | |
213 | dma_unmap_single(dev, | |
214 | xfer->tx_dma, xfer->len, | |
215 | DMA_TO_DEVICE); | |
216 | return -ENOMEM; | |
217 | } | |
218 | } | |
219 | return 0; | |
754ce4f2 HS |
220 | } |
221 | ||
222 | static void atmel_spi_dma_unmap_xfer(struct spi_master *master, | |
223 | struct spi_transfer *xfer) | |
224 | { | |
225 | if (xfer->tx_dma != INVALID_DMA_ADDRESS) | |
226 | dma_unmap_single(master->cdev.dev, xfer->tx_dma, | |
227 | xfer->len, DMA_TO_DEVICE); | |
228 | if (xfer->rx_dma != INVALID_DMA_ADDRESS) | |
229 | dma_unmap_single(master->cdev.dev, xfer->rx_dma, | |
230 | xfer->len, DMA_FROM_DEVICE); | |
231 | } | |
232 | ||
233 | static void | |
234 | atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as, | |
235 | struct spi_message *msg, int status) | |
236 | { | |
237 | cs_deactivate(msg->spi); | |
238 | list_del(&msg->queue); | |
239 | msg->status = status; | |
240 | ||
241 | dev_dbg(master->cdev.dev, | |
242 | "xfer complete: %u bytes transferred\n", | |
243 | msg->actual_length); | |
244 | ||
245 | spin_unlock(&as->lock); | |
246 | msg->complete(msg->context); | |
247 | spin_lock(&as->lock); | |
248 | ||
249 | as->current_transfer = NULL; | |
250 | ||
251 | /* continue if needed */ | |
252 | if (list_empty(&as->queue) || as->stopping) | |
253 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
254 | else | |
255 | atmel_spi_next_message(master); | |
256 | } | |
257 | ||
258 | static irqreturn_t | |
259 | atmel_spi_interrupt(int irq, void *dev_id) | |
260 | { | |
261 | struct spi_master *master = dev_id; | |
262 | struct atmel_spi *as = spi_master_get_devdata(master); | |
263 | struct spi_message *msg; | |
264 | struct spi_transfer *xfer; | |
265 | u32 status, pending, imr; | |
266 | int ret = IRQ_NONE; | |
267 | ||
268 | spin_lock(&as->lock); | |
269 | ||
270 | xfer = as->current_transfer; | |
271 | msg = list_entry(as->queue.next, struct spi_message, queue); | |
272 | ||
273 | imr = spi_readl(as, IMR); | |
274 | status = spi_readl(as, SR); | |
275 | pending = status & imr; | |
276 | ||
277 | if (pending & SPI_BIT(OVRES)) { | |
278 | int timeout; | |
279 | ||
280 | ret = IRQ_HANDLED; | |
281 | ||
282 | spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX) | |
283 | | SPI_BIT(OVRES))); | |
284 | ||
285 | /* | |
286 | * When we get an overrun, we disregard the current | |
287 | * transfer. Data will not be copied back from any | |
288 | * bounce buffer and msg->actual_len will not be | |
289 | * updated with the last xfer. | |
290 | * | |
291 | * We will also not process any remaning transfers in | |
292 | * the message. | |
293 | * | |
294 | * First, stop the transfer and unmap the DMA buffers. | |
295 | */ | |
296 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
297 | if (!msg->is_dma_mapped) | |
298 | atmel_spi_dma_unmap_xfer(master, xfer); | |
299 | ||
300 | /* REVISIT: udelay in irq is unfriendly */ | |
301 | if (xfer->delay_usecs) | |
302 | udelay(xfer->delay_usecs); | |
303 | ||
304 | dev_warn(master->cdev.dev, "fifo overrun (%u/%u remaining)\n", | |
305 | spi_readl(as, TCR), spi_readl(as, RCR)); | |
306 | ||
307 | /* | |
308 | * Clean up DMA registers and make sure the data | |
309 | * registers are empty. | |
310 | */ | |
311 | spi_writel(as, RNCR, 0); | |
312 | spi_writel(as, TNCR, 0); | |
313 | spi_writel(as, RCR, 0); | |
314 | spi_writel(as, TCR, 0); | |
315 | for (timeout = 1000; timeout; timeout--) | |
316 | if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) | |
317 | break; | |
318 | if (!timeout) | |
319 | dev_warn(master->cdev.dev, | |
320 | "timeout waiting for TXEMPTY"); | |
321 | while (spi_readl(as, SR) & SPI_BIT(RDRF)) | |
322 | spi_readl(as, RDR); | |
323 | ||
324 | /* Clear any overrun happening while cleaning up */ | |
325 | spi_readl(as, SR); | |
326 | ||
327 | atmel_spi_msg_done(master, as, msg, -EIO); | |
328 | } else if (pending & SPI_BIT(ENDRX)) { | |
329 | ret = IRQ_HANDLED; | |
330 | ||
331 | spi_writel(as, IDR, pending); | |
332 | ||
333 | if (as->remaining_bytes == 0) { | |
334 | msg->actual_length += xfer->len; | |
335 | ||
336 | if (!msg->is_dma_mapped) | |
337 | atmel_spi_dma_unmap_xfer(master, xfer); | |
338 | ||
339 | /* REVISIT: udelay in irq is unfriendly */ | |
340 | if (xfer->delay_usecs) | |
341 | udelay(xfer->delay_usecs); | |
342 | ||
343 | if (msg->transfers.prev == &xfer->transfer_list) { | |
344 | /* report completed message */ | |
345 | atmel_spi_msg_done(master, as, msg, 0); | |
346 | } else { | |
347 | if (xfer->cs_change) { | |
348 | cs_deactivate(msg->spi); | |
349 | udelay(1); | |
350 | cs_activate(msg->spi); | |
351 | } | |
352 | ||
353 | /* | |
354 | * Not done yet. Submit the next transfer. | |
355 | * | |
356 | * FIXME handle protocol options for xfer | |
357 | */ | |
358 | atmel_spi_next_xfer(master, msg); | |
359 | } | |
360 | } else { | |
361 | /* | |
362 | * Keep going, we still have data to send in | |
363 | * the current transfer. | |
364 | */ | |
365 | atmel_spi_next_xfer(master, msg); | |
366 | } | |
367 | } | |
368 | ||
369 | spin_unlock(&as->lock); | |
370 | ||
371 | return ret; | |
372 | } | |
373 | ||
dccd573b | 374 | /* the spi->mode bits understood by this driver: */ |
754ce4f2 HS |
375 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH) |
376 | ||
377 | static int atmel_spi_setup(struct spi_device *spi) | |
378 | { | |
379 | struct atmel_spi *as; | |
380 | u32 scbr, csr; | |
381 | unsigned int bits = spi->bits_per_word; | |
382 | unsigned long bus_hz, sck_hz; | |
383 | unsigned int npcs_pin; | |
384 | int ret; | |
385 | ||
386 | as = spi_master_get_devdata(spi->master); | |
387 | ||
388 | if (as->stopping) | |
389 | return -ESHUTDOWN; | |
390 | ||
391 | if (spi->chip_select > spi->master->num_chipselect) { | |
392 | dev_dbg(&spi->dev, | |
393 | "setup: invalid chipselect %u (%u defined)\n", | |
394 | spi->chip_select, spi->master->num_chipselect); | |
395 | return -EINVAL; | |
396 | } | |
397 | ||
398 | if (bits == 0) | |
399 | bits = 8; | |
400 | if (bits < 8 || bits > 16) { | |
401 | dev_dbg(&spi->dev, | |
402 | "setup: invalid bits_per_word %u (8 to 16)\n", | |
403 | bits); | |
404 | return -EINVAL; | |
405 | } | |
406 | ||
407 | if (spi->mode & ~MODEBITS) { | |
408 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
409 | spi->mode & ~MODEBITS); | |
410 | return -EINVAL; | |
411 | } | |
412 | ||
413 | /* speed zero convention is used by some upper layers */ | |
414 | bus_hz = clk_get_rate(as->clk); | |
415 | if (spi->max_speed_hz) { | |
416 | /* assume div32/fdiv/mbz == 0 */ | |
417 | if (!as->new_1) | |
418 | bus_hz /= 2; | |
419 | scbr = ((bus_hz + spi->max_speed_hz - 1) | |
420 | / spi->max_speed_hz); | |
421 | if (scbr >= (1 << SPI_SCBR_SIZE)) { | |
8da0859a DB |
422 | dev_dbg(&spi->dev, |
423 | "setup: %d Hz too slow, scbr %u; min %ld Hz\n", | |
424 | spi->max_speed_hz, scbr, bus_hz/255); | |
754ce4f2 HS |
425 | return -EINVAL; |
426 | } | |
427 | } else | |
428 | scbr = 0xff; | |
429 | sck_hz = bus_hz / scbr; | |
430 | ||
431 | csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8); | |
432 | if (spi->mode & SPI_CPOL) | |
433 | csr |= SPI_BIT(CPOL); | |
434 | if (!(spi->mode & SPI_CPHA)) | |
435 | csr |= SPI_BIT(NCPHA); | |
436 | ||
437 | /* TODO: DLYBS and DLYBCT */ | |
438 | csr |= SPI_BF(DLYBS, 10); | |
439 | csr |= SPI_BF(DLYBCT, 10); | |
440 | ||
441 | /* chipselect must have been muxed as GPIO (e.g. in board setup) */ | |
442 | npcs_pin = (unsigned int)spi->controller_data; | |
443 | if (!spi->controller_state) { | |
444 | ret = gpio_request(npcs_pin, "spi_npcs"); | |
445 | if (ret) | |
446 | return ret; | |
447 | spi->controller_state = (void *)npcs_pin; | |
28735a72 | 448 | gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH)); |
754ce4f2 HS |
449 | } |
450 | ||
451 | dev_dbg(&spi->dev, | |
452 | "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n", | |
453 | sck_hz, bits, spi->mode, spi->chip_select, csr); | |
454 | ||
455 | spi_writel(as, CSR0 + 4 * spi->chip_select, csr); | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg) | |
461 | { | |
462 | struct atmel_spi *as; | |
463 | struct spi_transfer *xfer; | |
464 | unsigned long flags; | |
465 | struct device *controller = spi->master->cdev.dev; | |
466 | ||
467 | as = spi_master_get_devdata(spi->master); | |
468 | ||
469 | dev_dbg(controller, "new message %p submitted for %s\n", | |
470 | msg, spi->dev.bus_id); | |
471 | ||
472 | if (unlikely(list_empty(&msg->transfers) | |
473 | || !spi->max_speed_hz)) | |
474 | return -EINVAL; | |
475 | ||
476 | if (as->stopping) | |
477 | return -ESHUTDOWN; | |
478 | ||
479 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
480 | if (!(xfer->tx_buf || xfer->rx_buf)) { | |
481 | dev_dbg(&spi->dev, "missing rx or tx buf\n"); | |
482 | return -EINVAL; | |
483 | } | |
484 | ||
485 | /* FIXME implement these protocol options!! */ | |
486 | if (xfer->bits_per_word || xfer->speed_hz) { | |
487 | dev_dbg(&spi->dev, "no protocol options yet\n"); | |
488 | return -ENOPROTOOPT; | |
489 | } | |
754ce4f2 | 490 | |
8da0859a DB |
491 | /* |
492 | * DMA map early, for performance (empties dcache ASAP) and | |
493 | * better fault reporting. This is a DMA-only driver. | |
494 | * | |
495 | * NOTE that if dma_unmap_single() ever starts to do work on | |
496 | * platforms supported by this driver, we would need to clean | |
497 | * up mappings for previously-mapped transfers. | |
498 | */ | |
499 | if (!msg->is_dma_mapped) { | |
500 | if (atmel_spi_dma_map_xfer(as, xfer) < 0) | |
501 | return -ENOMEM; | |
502 | } | |
754ce4f2 HS |
503 | } |
504 | ||
505 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
506 | dev_dbg(controller, | |
507 | " xfer %p: len %u tx %p/%08x rx %p/%08x\n", | |
508 | xfer, xfer->len, | |
509 | xfer->tx_buf, xfer->tx_dma, | |
510 | xfer->rx_buf, xfer->rx_dma); | |
511 | } | |
512 | ||
513 | msg->status = -EINPROGRESS; | |
514 | msg->actual_length = 0; | |
515 | ||
516 | spin_lock_irqsave(&as->lock, flags); | |
517 | list_add_tail(&msg->queue, &as->queue); | |
518 | if (!as->current_transfer) | |
519 | atmel_spi_next_message(spi->master); | |
520 | spin_unlock_irqrestore(&as->lock, flags); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
bb2d1c36 | 525 | static void atmel_spi_cleanup(struct spi_device *spi) |
754ce4f2 HS |
526 | { |
527 | if (spi->controller_state) | |
528 | gpio_free((unsigned int)spi->controller_data); | |
529 | } | |
530 | ||
531 | /*-------------------------------------------------------------------------*/ | |
532 | ||
533 | static int __init atmel_spi_probe(struct platform_device *pdev) | |
534 | { | |
535 | struct resource *regs; | |
536 | int irq; | |
537 | struct clk *clk; | |
538 | int ret; | |
539 | struct spi_master *master; | |
540 | struct atmel_spi *as; | |
541 | ||
542 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
543 | if (!regs) | |
544 | return -ENXIO; | |
545 | ||
546 | irq = platform_get_irq(pdev, 0); | |
547 | if (irq < 0) | |
548 | return irq; | |
549 | ||
550 | clk = clk_get(&pdev->dev, "spi_clk"); | |
551 | if (IS_ERR(clk)) | |
552 | return PTR_ERR(clk); | |
553 | ||
554 | /* setup spi core then atmel-specific driver state */ | |
555 | ret = -ENOMEM; | |
556 | master = spi_alloc_master(&pdev->dev, sizeof *as); | |
557 | if (!master) | |
558 | goto out_free; | |
559 | ||
560 | master->bus_num = pdev->id; | |
561 | master->num_chipselect = 4; | |
562 | master->setup = atmel_spi_setup; | |
563 | master->transfer = atmel_spi_transfer; | |
564 | master->cleanup = atmel_spi_cleanup; | |
565 | platform_set_drvdata(pdev, master); | |
566 | ||
567 | as = spi_master_get_devdata(master); | |
568 | ||
8da0859a DB |
569 | /* |
570 | * Scratch buffer is used for throwaway rx and tx data. | |
571 | * It's coherent to minimize dcache pollution. | |
572 | */ | |
754ce4f2 HS |
573 | as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE, |
574 | &as->buffer_dma, GFP_KERNEL); | |
575 | if (!as->buffer) | |
576 | goto out_free; | |
577 | ||
578 | spin_lock_init(&as->lock); | |
579 | INIT_LIST_HEAD(&as->queue); | |
580 | as->pdev = pdev; | |
581 | as->regs = ioremap(regs->start, (regs->end - regs->start) + 1); | |
582 | if (!as->regs) | |
583 | goto out_free_buffer; | |
584 | as->irq = irq; | |
585 | as->clk = clk; | |
754ce4f2 HS |
586 | if (!cpu_is_at91rm9200()) |
587 | as->new_1 = 1; | |
754ce4f2 HS |
588 | |
589 | ret = request_irq(irq, atmel_spi_interrupt, 0, | |
590 | pdev->dev.bus_id, master); | |
591 | if (ret) | |
592 | goto out_unmap_regs; | |
593 | ||
594 | /* Initialize the hardware */ | |
595 | clk_enable(clk); | |
596 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
597 | spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); | |
598 | spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); | |
599 | spi_writel(as, CR, SPI_BIT(SPIEN)); | |
600 | ||
601 | /* go! */ | |
602 | dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n", | |
603 | (unsigned long)regs->start, irq); | |
604 | ||
605 | ret = spi_register_master(master); | |
606 | if (ret) | |
607 | goto out_reset_hw; | |
608 | ||
609 | return 0; | |
610 | ||
611 | out_reset_hw: | |
612 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
613 | clk_disable(clk); | |
614 | free_irq(irq, master); | |
615 | out_unmap_regs: | |
616 | iounmap(as->regs); | |
617 | out_free_buffer: | |
618 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
619 | as->buffer_dma); | |
620 | out_free: | |
621 | clk_put(clk); | |
622 | spi_master_put(master); | |
623 | return ret; | |
624 | } | |
625 | ||
626 | static int __exit atmel_spi_remove(struct platform_device *pdev) | |
627 | { | |
628 | struct spi_master *master = platform_get_drvdata(pdev); | |
629 | struct atmel_spi *as = spi_master_get_devdata(master); | |
630 | struct spi_message *msg; | |
631 | ||
632 | /* reset the hardware and block queue progress */ | |
633 | spin_lock_irq(&as->lock); | |
634 | as->stopping = 1; | |
635 | spi_writel(as, CR, SPI_BIT(SWRST)); | |
636 | spi_readl(as, SR); | |
637 | spin_unlock_irq(&as->lock); | |
638 | ||
639 | /* Terminate remaining queued transfers */ | |
640 | list_for_each_entry(msg, &as->queue, queue) { | |
641 | /* REVISIT unmapping the dma is a NOP on ARM and AVR32 | |
642 | * but we shouldn't depend on that... | |
643 | */ | |
644 | msg->status = -ESHUTDOWN; | |
645 | msg->complete(msg->context); | |
646 | } | |
647 | ||
648 | dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer, | |
649 | as->buffer_dma); | |
650 | ||
651 | clk_disable(as->clk); | |
652 | clk_put(as->clk); | |
653 | free_irq(as->irq, master); | |
654 | iounmap(as->regs); | |
655 | ||
656 | spi_unregister_master(master); | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | #ifdef CONFIG_PM | |
662 | ||
663 | static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg) | |
664 | { | |
665 | struct spi_master *master = platform_get_drvdata(pdev); | |
666 | struct atmel_spi *as = spi_master_get_devdata(master); | |
667 | ||
668 | clk_disable(as->clk); | |
669 | return 0; | |
670 | } | |
671 | ||
672 | static int atmel_spi_resume(struct platform_device *pdev) | |
673 | { | |
674 | struct spi_master *master = platform_get_drvdata(pdev); | |
675 | struct atmel_spi *as = spi_master_get_devdata(master); | |
676 | ||
677 | clk_enable(as->clk); | |
678 | return 0; | |
679 | } | |
680 | ||
681 | #else | |
682 | #define atmel_spi_suspend NULL | |
683 | #define atmel_spi_resume NULL | |
684 | #endif | |
685 | ||
686 | ||
687 | static struct platform_driver atmel_spi_driver = { | |
688 | .driver = { | |
689 | .name = "atmel_spi", | |
690 | .owner = THIS_MODULE, | |
691 | }, | |
692 | .suspend = atmel_spi_suspend, | |
693 | .resume = atmel_spi_resume, | |
694 | .remove = __exit_p(atmel_spi_remove), | |
695 | }; | |
696 | ||
697 | static int __init atmel_spi_init(void) | |
698 | { | |
699 | return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe); | |
700 | } | |
701 | module_init(atmel_spi_init); | |
702 | ||
703 | static void __exit atmel_spi_exit(void) | |
704 | { | |
705 | platform_driver_unregister(&atmel_spi_driver); | |
706 | } | |
707 | module_exit(atmel_spi_exit); | |
708 | ||
709 | MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); | |
710 | MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>"); | |
711 | MODULE_LICENSE("GPL"); |