Commit | Line | Data |
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238b8721 PK |
1 | /* |
2 | * uartlite.c: Serial driver for Xilinx uartlite serial controller | |
3 | * | |
4 | * Peter Korsgaard <jacmet@sunsite.dk> | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <linux/platform_device.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/console.h> | |
14 | #include <linux/serial.h> | |
15 | #include <linux/serial_core.h> | |
16 | #include <linux/tty.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <asm/io.h> | |
20 | ||
21 | #define ULITE_MAJOR 204 | |
22 | #define ULITE_MINOR 187 | |
23 | #define ULITE_NR_UARTS 4 | |
24 | ||
25 | /* For register details see datasheet: | |
26 | http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_uartlite.pdf | |
27 | */ | |
28 | #define ULITE_RX 0x00 | |
29 | #define ULITE_TX 0x04 | |
30 | #define ULITE_STATUS 0x08 | |
31 | #define ULITE_CONTROL 0x0c | |
32 | ||
33 | #define ULITE_REGION 16 | |
34 | ||
35 | #define ULITE_STATUS_RXVALID 0x01 | |
36 | #define ULITE_STATUS_RXFULL 0x02 | |
37 | #define ULITE_STATUS_TXEMPTY 0x04 | |
38 | #define ULITE_STATUS_TXFULL 0x08 | |
39 | #define ULITE_STATUS_IE 0x10 | |
40 | #define ULITE_STATUS_OVERRUN 0x20 | |
41 | #define ULITE_STATUS_FRAME 0x40 | |
42 | #define ULITE_STATUS_PARITY 0x80 | |
43 | ||
44 | #define ULITE_CONTROL_RST_TX 0x01 | |
45 | #define ULITE_CONTROL_RST_RX 0x02 | |
46 | #define ULITE_CONTROL_IE 0x10 | |
47 | ||
48 | ||
483c79db | 49 | static struct uart_port ulite_ports[ULITE_NR_UARTS]; |
238b8721 PK |
50 | |
51 | static int ulite_receive(struct uart_port *port, int stat) | |
52 | { | |
53 | struct tty_struct *tty = port->info->tty; | |
54 | unsigned char ch = 0; | |
55 | char flag = TTY_NORMAL; | |
56 | ||
57 | if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN | |
58 | | ULITE_STATUS_FRAME)) == 0) | |
59 | return 0; | |
60 | ||
61 | /* stats */ | |
62 | if (stat & ULITE_STATUS_RXVALID) { | |
63 | port->icount.rx++; | |
a15da8ef | 64 | ch = in_be32((void*)port->membase + ULITE_RX); |
238b8721 PK |
65 | |
66 | if (stat & ULITE_STATUS_PARITY) | |
67 | port->icount.parity++; | |
68 | } | |
69 | ||
70 | if (stat & ULITE_STATUS_OVERRUN) | |
71 | port->icount.overrun++; | |
72 | ||
73 | if (stat & ULITE_STATUS_FRAME) | |
74 | port->icount.frame++; | |
75 | ||
76 | ||
77 | /* drop byte with parity error if IGNPAR specificed */ | |
78 | if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) | |
79 | stat &= ~ULITE_STATUS_RXVALID; | |
80 | ||
81 | stat &= port->read_status_mask; | |
82 | ||
83 | if (stat & ULITE_STATUS_PARITY) | |
84 | flag = TTY_PARITY; | |
85 | ||
86 | ||
87 | stat &= ~port->ignore_status_mask; | |
88 | ||
89 | if (stat & ULITE_STATUS_RXVALID) | |
90 | tty_insert_flip_char(tty, ch, flag); | |
91 | ||
92 | if (stat & ULITE_STATUS_FRAME) | |
93 | tty_insert_flip_char(tty, 0, TTY_FRAME); | |
94 | ||
95 | if (stat & ULITE_STATUS_OVERRUN) | |
96 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
97 | ||
98 | return 1; | |
99 | } | |
100 | ||
101 | static int ulite_transmit(struct uart_port *port, int stat) | |
102 | { | |
103 | struct circ_buf *xmit = &port->info->xmit; | |
104 | ||
105 | if (stat & ULITE_STATUS_TXFULL) | |
106 | return 0; | |
107 | ||
108 | if (port->x_char) { | |
a15da8ef | 109 | out_be32((void*)port->membase + ULITE_TX, port->x_char); |
238b8721 PK |
110 | port->x_char = 0; |
111 | port->icount.tx++; | |
112 | return 1; | |
113 | } | |
114 | ||
115 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) | |
116 | return 0; | |
117 | ||
a15da8ef | 118 | out_be32((void*)port->membase + ULITE_TX, xmit->buf[xmit->tail]); |
238b8721 PK |
119 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); |
120 | port->icount.tx++; | |
121 | ||
122 | /* wake up */ | |
123 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
124 | uart_write_wakeup(port); | |
125 | ||
126 | return 1; | |
127 | } | |
128 | ||
129 | static irqreturn_t ulite_isr(int irq, void *dev_id) | |
130 | { | |
131 | struct uart_port *port = (struct uart_port *)dev_id; | |
132 | int busy; | |
133 | ||
134 | do { | |
a15da8ef | 135 | int stat = in_be32((void*)port->membase + ULITE_STATUS); |
238b8721 PK |
136 | busy = ulite_receive(port, stat); |
137 | busy |= ulite_transmit(port, stat); | |
138 | } while (busy); | |
139 | ||
140 | tty_flip_buffer_push(port->info->tty); | |
141 | ||
142 | return IRQ_HANDLED; | |
143 | } | |
144 | ||
145 | static unsigned int ulite_tx_empty(struct uart_port *port) | |
146 | { | |
147 | unsigned long flags; | |
148 | unsigned int ret; | |
149 | ||
150 | spin_lock_irqsave(&port->lock, flags); | |
a15da8ef | 151 | ret = in_be32((void*)port->membase + ULITE_STATUS); |
238b8721 PK |
152 | spin_unlock_irqrestore(&port->lock, flags); |
153 | ||
154 | return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; | |
155 | } | |
156 | ||
157 | static unsigned int ulite_get_mctrl(struct uart_port *port) | |
158 | { | |
159 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
160 | } | |
161 | ||
162 | static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
163 | { | |
164 | /* N/A */ | |
165 | } | |
166 | ||
167 | static void ulite_stop_tx(struct uart_port *port) | |
168 | { | |
169 | /* N/A */ | |
170 | } | |
171 | ||
172 | static void ulite_start_tx(struct uart_port *port) | |
173 | { | |
a15da8ef | 174 | ulite_transmit(port, in_be32((void*)port->membase + ULITE_STATUS)); |
238b8721 PK |
175 | } |
176 | ||
177 | static void ulite_stop_rx(struct uart_port *port) | |
178 | { | |
179 | /* don't forward any more data (like !CREAD) */ | |
180 | port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY | |
181 | | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; | |
182 | } | |
183 | ||
184 | static void ulite_enable_ms(struct uart_port *port) | |
185 | { | |
186 | /* N/A */ | |
187 | } | |
188 | ||
189 | static void ulite_break_ctl(struct uart_port *port, int ctl) | |
190 | { | |
191 | /* N/A */ | |
192 | } | |
193 | ||
194 | static int ulite_startup(struct uart_port *port) | |
195 | { | |
196 | int ret; | |
197 | ||
198 | ret = request_irq(port->irq, ulite_isr, | |
199 | IRQF_DISABLED | IRQF_SAMPLE_RANDOM, "uartlite", port); | |
200 | if (ret) | |
201 | return ret; | |
202 | ||
a15da8ef GL |
203 | out_be32((void*)port->membase + ULITE_CONTROL, |
204 | ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); | |
205 | out_be32((void*)port->membase + ULITE_CONTROL, ULITE_CONTROL_IE); | |
238b8721 PK |
206 | |
207 | return 0; | |
208 | } | |
209 | ||
210 | static void ulite_shutdown(struct uart_port *port) | |
211 | { | |
a15da8ef GL |
212 | out_be32((void*)port->membase + ULITE_CONTROL, 0); |
213 | in_be32((void*)port->membase + ULITE_CONTROL); /* dummy */ | |
238b8721 PK |
214 | free_irq(port->irq, port); |
215 | } | |
216 | ||
606d099c AC |
217 | static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, |
218 | struct ktermios *old) | |
238b8721 PK |
219 | { |
220 | unsigned long flags; | |
221 | unsigned int baud; | |
222 | ||
223 | spin_lock_irqsave(&port->lock, flags); | |
224 | ||
225 | port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN | |
226 | | ULITE_STATUS_TXFULL; | |
227 | ||
228 | if (termios->c_iflag & INPCK) | |
229 | port->read_status_mask |= | |
230 | ULITE_STATUS_PARITY | ULITE_STATUS_FRAME; | |
231 | ||
232 | port->ignore_status_mask = 0; | |
233 | if (termios->c_iflag & IGNPAR) | |
234 | port->ignore_status_mask |= ULITE_STATUS_PARITY | |
235 | | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; | |
236 | ||
237 | /* ignore all characters if CREAD is not set */ | |
238 | if ((termios->c_cflag & CREAD) == 0) | |
239 | port->ignore_status_mask |= | |
240 | ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY | |
241 | | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; | |
242 | ||
243 | /* update timeout */ | |
244 | baud = uart_get_baud_rate(port, termios, old, 0, 460800); | |
245 | uart_update_timeout(port, termios->c_cflag, baud); | |
246 | ||
247 | spin_unlock_irqrestore(&port->lock, flags); | |
248 | } | |
249 | ||
250 | static const char *ulite_type(struct uart_port *port) | |
251 | { | |
252 | return port->type == PORT_UARTLITE ? "uartlite" : NULL; | |
253 | } | |
254 | ||
255 | static void ulite_release_port(struct uart_port *port) | |
256 | { | |
257 | release_mem_region(port->mapbase, ULITE_REGION); | |
258 | iounmap(port->membase); | |
b81831c6 | 259 | port->membase = NULL; |
238b8721 PK |
260 | } |
261 | ||
262 | static int ulite_request_port(struct uart_port *port) | |
263 | { | |
264 | if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { | |
265 | dev_err(port->dev, "Memory region busy\n"); | |
266 | return -EBUSY; | |
267 | } | |
268 | ||
269 | port->membase = ioremap(port->mapbase, ULITE_REGION); | |
270 | if (!port->membase) { | |
271 | dev_err(port->dev, "Unable to map registers\n"); | |
272 | release_mem_region(port->mapbase, ULITE_REGION); | |
273 | return -EBUSY; | |
274 | } | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
279 | static void ulite_config_port(struct uart_port *port, int flags) | |
280 | { | |
e21654a7 PK |
281 | if (!ulite_request_port(port)) |
282 | port->type = PORT_UARTLITE; | |
238b8721 PK |
283 | } |
284 | ||
285 | static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser) | |
286 | { | |
287 | /* we don't want the core code to modify any port params */ | |
288 | return -EINVAL; | |
289 | } | |
290 | ||
291 | static struct uart_ops ulite_ops = { | |
292 | .tx_empty = ulite_tx_empty, | |
293 | .set_mctrl = ulite_set_mctrl, | |
294 | .get_mctrl = ulite_get_mctrl, | |
295 | .stop_tx = ulite_stop_tx, | |
296 | .start_tx = ulite_start_tx, | |
297 | .stop_rx = ulite_stop_rx, | |
298 | .enable_ms = ulite_enable_ms, | |
299 | .break_ctl = ulite_break_ctl, | |
300 | .startup = ulite_startup, | |
301 | .shutdown = ulite_shutdown, | |
302 | .set_termios = ulite_set_termios, | |
303 | .type = ulite_type, | |
304 | .release_port = ulite_release_port, | |
305 | .request_port = ulite_request_port, | |
306 | .config_port = ulite_config_port, | |
307 | .verify_port = ulite_verify_port | |
308 | }; | |
309 | ||
310 | #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE | |
311 | static void ulite_console_wait_tx(struct uart_port *port) | |
312 | { | |
313 | int i; | |
314 | ||
315 | /* wait up to 10ms for the character(s) to be sent */ | |
316 | for (i = 0; i < 10000; i++) { | |
a15da8ef | 317 | if (in_be32((void*)port->membase + ULITE_STATUS) & ULITE_STATUS_TXEMPTY) |
238b8721 PK |
318 | break; |
319 | udelay(1); | |
320 | } | |
321 | } | |
322 | ||
323 | static void ulite_console_putchar(struct uart_port *port, int ch) | |
324 | { | |
325 | ulite_console_wait_tx(port); | |
a15da8ef | 326 | out_be32((void*)port->membase + ULITE_TX, ch); |
238b8721 PK |
327 | } |
328 | ||
329 | static void ulite_console_write(struct console *co, const char *s, | |
330 | unsigned int count) | |
331 | { | |
483c79db | 332 | struct uart_port *port = &ulite_ports[co->index]; |
238b8721 PK |
333 | unsigned long flags; |
334 | unsigned int ier; | |
335 | int locked = 1; | |
336 | ||
337 | if (oops_in_progress) { | |
338 | locked = spin_trylock_irqsave(&port->lock, flags); | |
339 | } else | |
340 | spin_lock_irqsave(&port->lock, flags); | |
341 | ||
342 | /* save and disable interrupt */ | |
a15da8ef GL |
343 | ier = in_be32((void*)port->membase + ULITE_STATUS) & ULITE_STATUS_IE; |
344 | out_be32((void*)port->membase + ULITE_CONTROL, 0); | |
238b8721 PK |
345 | |
346 | uart_console_write(port, s, count, ulite_console_putchar); | |
347 | ||
348 | ulite_console_wait_tx(port); | |
349 | ||
350 | /* restore interrupt state */ | |
351 | if (ier) | |
a15da8ef | 352 | out_be32((void*)port->membase + ULITE_CONTROL, ULITE_CONTROL_IE); |
238b8721 PK |
353 | |
354 | if (locked) | |
355 | spin_unlock_irqrestore(&port->lock, flags); | |
356 | } | |
357 | ||
358 | static int __init ulite_console_setup(struct console *co, char *options) | |
359 | { | |
360 | struct uart_port *port; | |
361 | int baud = 9600; | |
362 | int bits = 8; | |
363 | int parity = 'n'; | |
364 | int flow = 'n'; | |
365 | ||
366 | if (co->index < 0 || co->index >= ULITE_NR_UARTS) | |
367 | return -EINVAL; | |
368 | ||
483c79db | 369 | port = &ulite_ports[co->index]; |
238b8721 PK |
370 | |
371 | /* not initialized yet? */ | |
372 | if (!port->membase) | |
373 | return -ENODEV; | |
374 | ||
375 | if (options) | |
376 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
377 | ||
378 | return uart_set_options(port, co, baud, parity, bits, flow); | |
379 | } | |
380 | ||
381 | static struct uart_driver ulite_uart_driver; | |
382 | ||
383 | static struct console ulite_console = { | |
384 | .name = "ttyUL", | |
385 | .write = ulite_console_write, | |
386 | .device = uart_console_device, | |
387 | .setup = ulite_console_setup, | |
388 | .flags = CON_PRINTBUFFER, | |
389 | .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */ | |
390 | .data = &ulite_uart_driver, | |
391 | }; | |
392 | ||
393 | static int __init ulite_console_init(void) | |
394 | { | |
395 | register_console(&ulite_console); | |
396 | return 0; | |
397 | } | |
398 | ||
399 | console_initcall(ulite_console_init); | |
400 | ||
401 | #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */ | |
402 | ||
403 | static struct uart_driver ulite_uart_driver = { | |
404 | .owner = THIS_MODULE, | |
405 | .driver_name = "uartlite", | |
406 | .dev_name = "ttyUL", | |
407 | .major = ULITE_MAJOR, | |
408 | .minor = ULITE_MINOR, | |
409 | .nr = ULITE_NR_UARTS, | |
410 | #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE | |
411 | .cons = &ulite_console, | |
412 | #endif | |
413 | }; | |
414 | ||
415 | static int __devinit ulite_probe(struct platform_device *pdev) | |
416 | { | |
417 | struct resource *res, *res2; | |
418 | struct uart_port *port; | |
419 | ||
420 | if (pdev->id < 0 || pdev->id >= ULITE_NR_UARTS) | |
421 | return -EINVAL; | |
422 | ||
483c79db | 423 | if (ulite_ports[pdev->id].membase) |
238b8721 PK |
424 | return -EBUSY; |
425 | ||
426 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
427 | if (!res) | |
428 | return -ENODEV; | |
429 | ||
430 | res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
431 | if (!res2) | |
432 | return -ENODEV; | |
433 | ||
483c79db | 434 | port = &ulite_ports[pdev->id]; |
238b8721 PK |
435 | |
436 | port->fifosize = 16; | |
437 | port->regshift = 2; | |
438 | port->iotype = UPIO_MEM; | |
439 | port->iobase = 1; /* mark port in use */ | |
440 | port->mapbase = res->start; | |
b81831c6 | 441 | port->membase = NULL; |
238b8721 PK |
442 | port->ops = &ulite_ops; |
443 | port->irq = res2->start; | |
444 | port->flags = UPF_BOOT_AUTOCONF; | |
445 | port->dev = &pdev->dev; | |
446 | port->type = PORT_UNKNOWN; | |
447 | port->line = pdev->id; | |
448 | ||
449 | uart_add_one_port(&ulite_uart_driver, port); | |
450 | platform_set_drvdata(pdev, port); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | static int ulite_remove(struct platform_device *pdev) | |
456 | { | |
457 | struct uart_port *port = platform_get_drvdata(pdev); | |
458 | ||
459 | platform_set_drvdata(pdev, NULL); | |
460 | ||
461 | if (port) | |
462 | uart_remove_one_port(&ulite_uart_driver, port); | |
463 | ||
464 | /* mark port as free */ | |
b81831c6 | 465 | port->membase = NULL; |
238b8721 PK |
466 | |
467 | return 0; | |
468 | } | |
469 | ||
470 | static struct platform_driver ulite_platform_driver = { | |
471 | .probe = ulite_probe, | |
472 | .remove = ulite_remove, | |
473 | .driver = { | |
474 | .owner = THIS_MODULE, | |
475 | .name = "uartlite", | |
476 | }, | |
477 | }; | |
478 | ||
479 | int __init ulite_init(void) | |
480 | { | |
481 | int ret; | |
482 | ||
483 | ret = uart_register_driver(&ulite_uart_driver); | |
484 | if (ret) | |
485 | return ret; | |
486 | ||
487 | ret = platform_driver_register(&ulite_platform_driver); | |
488 | if (ret) | |
489 | uart_unregister_driver(&ulite_uart_driver); | |
490 | ||
491 | return ret; | |
492 | } | |
493 | ||
494 | void __exit ulite_exit(void) | |
495 | { | |
496 | platform_driver_unregister(&ulite_platform_driver); | |
497 | uart_unregister_driver(&ulite_uart_driver); | |
498 | } | |
499 | ||
500 | module_init(ulite_init); | |
501 | module_exit(ulite_exit); | |
502 | ||
503 | MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>"); | |
504 | MODULE_DESCRIPTION("Xilinx uartlite serial driver"); | |
505 | MODULE_LICENSE("GPL"); |