projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $ |
| 2 | * | |
| 3 | * linux/drivers/serial/sh-sci.h | |
| 4 | * | |
| 5 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
| 6 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
| 7 | * Copyright (C) 2000 Greg Banks | |
| 8 | * Copyright (C) 2002, 2003 Paul Mundt | |
| 9 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
| 10 | * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003). | |
| 11 | * Modified to support H8/300 Series Yoshinori Sato (Feb 2004). | |
| 12 | */ | |
| 1da177e4 | 13 | #include <linux/serial_core.h> |
| e108b2ca | 14 | #include <asm/io.h> |
| 1da177e4 LT |
15 | |
| 16 | #if defined(__H8300H__) || defined(__H8300S__) | |
| 17 | #include <asm/gpio.h> | |
| 18 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
| 19 | #include <asm/regs306x.h> | |
| 20 | #endif | |
| 21 | #if defined(CONFIG_H8S2678) | |
| 22 | #include <asm/regs267x.h> | |
| 23 | #endif | |
| 24 | #endif | |
| 25 | ||
| 1da177e4 | 26 | #if defined(CONFIG_CPU_SUBTYPE_SH7708) |
| 1da177e4 LT |
27 | # define SCSPTR 0xffffff7c /* 8 bit */ |
| 28 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 29 | # define SCI_ONLY | |
| e108b2ca PM |
30 | #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 31 | defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | |
| 32 | defined(CONFIG_CPU_SUBTYPE_SH7706) | |
| 1da177e4 LT |
33 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
| 34 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | |
| 35 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 36 | # define SCI_AND_SCIF | |
| 37 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 38 | # define SCIF0 0xA4400000 | |
| 39 | # define SCIF2 0xA4410000 | |
| b7a76e4b PM |
40 | # define SCSMR_Ir 0xA44A0000 |
| 41 | # define IRDA_SCIF SCIF0 | |
| 1da177e4 LT |
42 | # define SCPCR 0xA4000116 |
| 43 | # define SCPDR 0xA4000136 | |
| 44 | ||
| 45 | /* Set the clock source, | |
| 46 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input | |
| 47 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | |
| 48 | */ | |
| 49 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | |
| 50 | # define SCIF_ONLY | |
| 51 | #elif defined(CONFIG_SH_RTS7751R2D) | |
| 1da177e4 LT |
52 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
| 53 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 54 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 55 | # define SCIF_ONLY | |
| 56 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) | |
| 1da177e4 LT |
57 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
| 58 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | |
| 59 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 60 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | |
| 61 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | |
| 62 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | |
| 63 | # define SCI_AND_SCIF | |
| 64 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | |
| b7a76e4b PM |
65 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
| 66 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | |
| 67 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | |
| 1da177e4 LT |
68 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 69 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 70 | # define SCIF_ONLY | |
| 71 | #elif defined(CONFIG_CPU_SUBTYPE_SH7300) | |
| 1da177e4 LT |
72 | # define SCPCR 0xA4050116 /* 16 bit SCIF */ |
| 73 | # define SCPDR 0xA4050136 /* 16 bit SCIF */ | |
| 74 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 75 | # define SCIF_ONLY | |
| e108b2ca PM |
76 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) |
| 77 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ | |
| 78 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 79 | # define SCIF_ONLY | |
| 1da177e4 | 80 | #elif defined(CONFIG_CPU_SUBTYPE_SH73180) |
| 1da177e4 LT |
81 | # define SCPDR 0xA4050138 /* 16 bit SCIF */ |
| 82 | # define SCSPTR2 SCPDR | |
| 83 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 84 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 85 | # define SCIF_ONLY | |
| e108b2ca PM |
86 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
| 87 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | |
| 88 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | |
| 89 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | |
| 90 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | |
| 91 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | |
| 92 | # define SCIF_ONLY | |
| 41504c39 PM |
93 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 94 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | |
| 95 | # define SCSPTR0 SCPDR0 | |
| 96 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 97 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 98 | # define SCIF_ONLY | |
| 99 | # define PORT_PSCR 0xA405011E | |
| 1da177e4 | 100 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
| 1da177e4 LT |
101 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
| 102 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 103 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 104 | # define SCIF_ONLY | |
| 105 | #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) | |
| 1da177e4 LT |
106 | # define SCSPTR1 0xffe00020 /* 16 bit SCIF */ |
| 107 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ | |
| 108 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 109 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 110 | # define SCIF_ONLY | |
| 111 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | |
| 112 | # include <asm/hardware.h> | |
| 113 | # define SCIF_BASE_ADDR 0x01030000 | |
| 114 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | |
| 115 | # define SCIF_PTR2_OFFS 0x0000020 | |
| 116 | # define SCIF_LSR2_OFFS 0x0000024 | |
| 1da177e4 LT |
117 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
| 118 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | |
| 119 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, | |
| 120 | TE=1,RE=1,REIE=1 */ | |
| 121 | # define SCIF_ONLY | |
| 122 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
| 1da177e4 LT |
123 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| 124 | # define SCI_ONLY | |
| 125 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | |
| 126 | #elif defined(CONFIG_H8S2678) | |
| 1da177e4 LT |
127 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| 128 | # define SCI_ONLY | |
| 129 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | |
| b7a76e4b PM |
130 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
| 131 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | |
| 132 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | |
| 133 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | |
| 134 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 135 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | |
| 136 | # define SCIF_ONLY | |
| 137 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | |
| 138 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
| 139 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | |
| e108b2ca | 140 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| b7a76e4b PM |
141 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| 142 | # define SCIF_ONLY | |
| 32351a28 PM |
143 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
| 144 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | |
| 145 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | |
| 146 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ | |
| 147 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ | |
| 148 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | |
| 149 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | |
| 150 | # define SCIF_OPER 0x0001 /* Overrun error bit */ | |
| 151 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 152 | # define SCIF_ONLY | |
| 9d4436a6 YS |
153 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) |
| 154 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ | |
| 155 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | |
| 156 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | |
| 157 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | |
| 158 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 159 | # define SCIF_ONLY | |
| 160 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
| 161 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | |
| 162 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | |
| 163 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | |
| 164 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 165 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 166 | # define SCIF_ONLY | |
| 1da177e4 LT |
167 | #else |
| 168 | # error CPU subtype not defined | |
| 169 | #endif | |
| 170 | ||
| 171 | /* SCSCR */ | |
| 172 | #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ | |
| 173 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ | |
| 174 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ | |
| 175 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ | |
| 32351a28 PM |
176 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 177 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 178 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
| 179 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
| 1da177e4 LT |
180 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ |
| 181 | #else | |
| 182 | #define SCI_CTRL_FLAGS_REIE 0 | |
| 183 | #endif | |
| 184 | /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 185 | /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 186 | /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ | |
| 187 | /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ | |
| 188 | ||
| 189 | /* SCxSR SCI */ | |
| 190 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 191 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 192 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 193 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 194 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 195 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 196 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 197 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 198 | ||
| 199 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) | |
| 200 | ||
| 201 | /* SCxSR SCIF */ | |
| 202 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 203 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 204 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 205 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 206 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 207 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 208 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 209 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 210 | ||
| 211 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 212 | #define SCIF_ORER 0x0200 | |
| 213 | #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | |
| 214 | #define SCIF_RFDC_MASK 0x007f | |
| 215 | #define SCIF_TXROOM_MAX 64 | |
| 216 | #else | |
| 217 | #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) | |
| 218 | #define SCIF_RFDC_MASK 0x001f | |
| 219 | #define SCIF_TXROOM_MAX 16 | |
| 220 | #endif | |
| 221 | ||
| 222 | #if defined(SCI_ONLY) | |
| 223 | # define SCxSR_TEND(port) SCI_TEND | |
| 224 | # define SCxSR_ERRORS(port) SCI_ERRORS | |
| 225 | # define SCxSR_RDxF(port) SCI_RDRF | |
| 226 | # define SCxSR_TDxE(port) SCI_TDRE | |
| 227 | # define SCxSR_ORER(port) SCI_ORER | |
| 228 | # define SCxSR_FER(port) SCI_FER | |
| 229 | # define SCxSR_PER(port) SCI_PER | |
| 230 | # define SCxSR_BRK(port) 0x00 | |
| 231 | # define SCxSR_RDxF_CLEAR(port) 0xbc | |
| 232 | # define SCxSR_ERROR_CLEAR(port) 0xc4 | |
| 233 | # define SCxSR_TDxE_CLEAR(port) 0x78 | |
| b7a76e4b | 234 | # define SCxSR_BREAK_CLEAR(port) 0xc4 |
| 1da177e4 LT |
235 | #elif defined(SCIF_ONLY) |
| 236 | # define SCxSR_TEND(port) SCIF_TEND | |
| 237 | # define SCxSR_ERRORS(port) SCIF_ERRORS | |
| 238 | # define SCxSR_RDxF(port) SCIF_RDF | |
| 239 | # define SCxSR_TDxE(port) SCIF_TDFE | |
| 240 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 241 | # define SCxSR_ORER(port) SCIF_ORER | |
| 242 | #else | |
| 243 | # define SCxSR_ORER(port) 0x0000 | |
| 244 | #endif | |
| 245 | # define SCxSR_FER(port) SCIF_FER | |
| 246 | # define SCxSR_PER(port) SCIF_PER | |
| 247 | # define SCxSR_BRK(port) SCIF_BRK | |
| 248 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 249 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) | |
| 250 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) | |
| 251 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) | |
| 252 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3) | |
| 253 | #else | |
| 254 | /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */ | |
| 255 | # define SCxSR_RDxF_CLEAR(port) 0x00fc | |
| 256 | # define SCxSR_ERROR_CLEAR(port) 0x0073 | |
| 257 | # define SCxSR_TDxE_CLEAR(port) 0x00df | |
| b7a76e4b | 258 | # define SCxSR_BREAK_CLEAR(port) 0x00e3 |
| 1da177e4 LT |
259 | #endif |
| 260 | #else | |
| 261 | # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) | |
| 262 | # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | |
| 263 | # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | |
| 264 | # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | |
| 265 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) | |
| 266 | # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | |
| 267 | # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | |
| 268 | # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | |
| 269 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) | |
| 270 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | |
| 271 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | |
| 272 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | |
| 273 | #endif | |
| 274 | ||
| 275 | /* SCFCR */ | |
| 276 | #define SCFCR_RFRST 0x0002 | |
| 277 | #define SCFCR_TFRST 0x0004 | |
| 278 | #define SCFCR_TCRST 0x4000 | |
| 279 | #define SCFCR_MCE 0x0008 | |
| 280 | ||
| 281 | #define SCI_MAJOR 204 | |
| 282 | #define SCI_MINOR_START 8 | |
| 283 | ||
| 284 | /* Generic serial flags */ | |
| 285 | #define SCI_RX_THROTTLE 0x0000001 | |
| 286 | ||
| 287 | #define SCI_MAGIC 0xbabeface | |
| 288 | ||
| 289 | /* | |
| 290 | * Events are used to schedule things to happen at timer-interrupt | |
| 291 | * time, instead of at rs interrupt time. | |
| 292 | */ | |
| 293 | #define SCI_EVENT_WRITE_WAKEUP 0 | |
| 294 | ||
| 1da177e4 LT |
295 | #define SCI_IN(size, offset) \ |
| 296 | unsigned int addr = port->mapbase + (offset); \ | |
| b7a76e4b | 297 | if ((size) == 8) { \ |
| 1da177e4 | 298 | return ctrl_inb(addr); \ |
| b7a76e4b | 299 | } else { \ |
| 1da177e4 LT |
300 | return ctrl_inw(addr); \ |
| 301 | } | |
| 302 | #define SCI_OUT(size, offset, value) \ | |
| 303 | unsigned int addr = port->mapbase + (offset); \ | |
| b7a76e4b | 304 | if ((size) == 8) { \ |
| 1da177e4 LT |
305 | ctrl_outb(value, addr); \ |
| 306 | } else { \ | |
| 307 | ctrl_outw(value, addr); \ | |
| 308 | } | |
| 309 | ||
| 310 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | |
| 311 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
| 312 | { \ | |
| b7a76e4b | 313 | if (port->type == PORT_SCI) { \ |
| 1da177e4 LT |
314 | SCI_IN(sci_size, sci_offset) \ |
| 315 | } else { \ | |
| b7a76e4b | 316 | SCI_IN(scif_size, scif_offset); \ |
| 1da177e4 LT |
317 | } \ |
| 318 | } \ | |
| 319 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
| 320 | { \ | |
| 321 | if (port->type == PORT_SCI) { \ | |
| 322 | SCI_OUT(sci_size, sci_offset, value) \ | |
| 323 | } else { \ | |
| 324 | SCI_OUT(scif_size, scif_offset, value); \ | |
| 325 | } \ | |
| 326 | } | |
| 327 | ||
| 328 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | |
| 329 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
| 330 | { \ | |
| b7a76e4b | 331 | SCI_IN(scif_size, scif_offset); \ |
| 1da177e4 LT |
332 | } \ |
| 333 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
| 334 | { \ | |
| 335 | SCI_OUT(scif_size, scif_offset, value); \ | |
| 336 | } | |
| 337 | ||
| 338 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ | |
| 339 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ | |
| 340 | { \ | |
| b7a76e4b | 341 | SCI_IN(sci_size, sci_offset); \ |
| 1da177e4 LT |
342 | } \ |
| 343 | static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ | |
| 344 | { \ | |
| 345 | SCI_OUT(sci_size, sci_offset, value); \ | |
| 346 | } | |
| 347 | ||
| 348 | #ifdef CONFIG_CPU_SH3 | |
| e108b2ca PM |
349 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ |
| 350 | defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | |
| 351 | defined(CONFIG_CPU_SUBTYPE_SH7710) | |
| 1da177e4 LT |
352 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
| 353 | CPU_SCIF_FNS(name, scif_offset, scif_size) | |
| 354 | #else | |
| 355 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 356 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 357 | h8_sci_offset, h8_sci_size) \ | |
| 358 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) | |
| 359 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 360 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) | |
| 361 | #endif | |
| 362 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 363 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 364 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 365 | h8_sci_offset, h8_sci_size) \ | |
| 366 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | |
| 367 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) | |
| 368 | #else | |
| 369 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 370 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 371 | h8_sci_offset, h8_sci_size) \ | |
| 372 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
| 373 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 374 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 375 | #endif | |
| 376 | ||
| e108b2ca PM |
377 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ |
| 378 | defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | |
| 379 | defined(CONFIG_CPU_SUBTYPE_SH7710) | |
| 1da177e4 LT |
380 | SCIF_FNS(SCSMR, 0x00, 16) |
| 381 | SCIF_FNS(SCBRR, 0x04, 8) | |
| 382 | SCIF_FNS(SCSCR, 0x08, 16) | |
| 383 | SCIF_FNS(SCTDSR, 0x0c, 8) | |
| 384 | SCIF_FNS(SCFER, 0x10, 16) | |
| 385 | SCIF_FNS(SCxSR, 0x14, 16) | |
| 386 | SCIF_FNS(SCFCR, 0x18, 16) | |
| 387 | SCIF_FNS(SCFDR, 0x1c, 16) | |
| 388 | SCIF_FNS(SCxTDR, 0x20, 8) | |
| 389 | SCIF_FNS(SCxRDR, 0x24, 8) | |
| 390 | SCIF_FNS(SCLSR, 0x24, 16) | |
| 391 | #else | |
| 392 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ | |
| 393 | /* name off sz off sz off sz off sz off sz*/ | |
| 394 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) | |
| 395 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) | |
| 396 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) | |
| 397 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | |
| 398 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | |
| 399 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | |
| 400 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | |
| 32351a28 PM |
401 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
| 402 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
| 403 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
| 6fc21b82 | 404 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| b7a76e4b PM |
405 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
| 406 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
| 407 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
| 408 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
| 409 | #else | |
| 1da177e4 LT |
410 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| 411 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) | |
| 412 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) | |
| 413 | #endif | |
| b7a76e4b | 414 | #endif |
| 1da177e4 LT |
415 | #define sci_in(port, reg) sci_##reg##_in(port) |
| 416 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | |
| 417 | ||
| 418 | /* H8/300 series SCI pins assignment */ | |
| 419 | #if defined(__H8300H__) || defined(__H8300S__) | |
| 420 | static const struct __attribute__((packed)) { | |
| 421 | int port; /* GPIO port no */ | |
| 422 | unsigned short rx,tx; /* GPIO bit no */ | |
| 423 | } h8300_sci_pins[] = { | |
| 424 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
| 425 | { /* SCI0 */ | |
| 426 | .port = H8300_GPIO_P9, | |
| 427 | .rx = H8300_GPIO_B2, | |
| 428 | .tx = H8300_GPIO_B0, | |
| 429 | }, | |
| 430 | { /* SCI1 */ | |
| 431 | .port = H8300_GPIO_P9, | |
| 432 | .rx = H8300_GPIO_B3, | |
| 433 | .tx = H8300_GPIO_B1, | |
| 434 | }, | |
| 435 | { /* SCI2 */ | |
| 436 | .port = H8300_GPIO_PB, | |
| 437 | .rx = H8300_GPIO_B7, | |
| 438 | .tx = H8300_GPIO_B6, | |
| 439 | } | |
| 440 | #elif defined(CONFIG_H8S2678) | |
| 441 | { /* SCI0 */ | |
| 442 | .port = H8300_GPIO_P3, | |
| 443 | .rx = H8300_GPIO_B2, | |
| 444 | .tx = H8300_GPIO_B0, | |
| 445 | }, | |
| 446 | { /* SCI1 */ | |
| 447 | .port = H8300_GPIO_P3, | |
| 448 | .rx = H8300_GPIO_B3, | |
| 449 | .tx = H8300_GPIO_B1, | |
| 450 | }, | |
| 451 | { /* SCI2 */ | |
| 452 | .port = H8300_GPIO_P5, | |
| 453 | .rx = H8300_GPIO_B1, | |
| 454 | .tx = H8300_GPIO_B0, | |
| 455 | } | |
| 456 | #endif | |
| 457 | }; | |
| 458 | #endif | |
| 459 | ||
| 460 | #if defined(CONFIG_CPU_SUBTYPE_SH7708) | |
| 461 | static inline int sci_rxd_in(struct uart_port *port) | |
| 462 | { | |
| 463 | if (port->mapbase == 0xfffffe80) | |
| 464 | return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */ | |
| 465 | return 1; | |
| 466 | } | |
| e108b2ca PM |
467 | #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
| 468 | defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | |
| 469 | defined(CONFIG_CPU_SUBTYPE_SH7706) | |
| 1da177e4 LT |
470 | static inline int sci_rxd_in(struct uart_port *port) |
| 471 | { | |
| 472 | if (port->mapbase == 0xfffffe80) | |
| 473 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
| 474 | if (port->mapbase == 0xa4000150) | |
| 475 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
| 476 | if (port->mapbase == 0xa4000140) | |
| 477 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
| 478 | return 1; | |
| 479 | } | |
| 480 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 481 | static inline int sci_rxd_in(struct uart_port *port) | |
| 482 | { | |
| 483 | if (port->mapbase == SCIF0) | |
| 484 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
| 485 | if (port->mapbase == SCIF2) | |
| 486 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
| 487 | return 1; | |
| 488 | } | |
| e108b2ca PM |
489 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) |
| 490 | static inline int sci_rxd_in(struct uart_port *port) | |
| 491 | { | |
| 492 | if (port->mapbase == SCSPTR0) | |
| 493 | return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0; | |
| 494 | return 1; | |
| 495 | } | |
| 1da177e4 LT |
496 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 497 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 498 | defined(CONFIG_CPU_SUBTYPE_SH4_202) | |
| 499 | static inline int sci_rxd_in(struct uart_port *port) | |
| 500 | { | |
| 501 | #ifndef SCIF_ONLY | |
| 502 | if (port->mapbase == 0xffe00000) | |
| 503 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | |
| 504 | #endif | |
| 505 | #ifndef SCI_ONLY | |
| 506 | if (port->mapbase == 0xffe80000) | |
| 507 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
| 508 | #endif | |
| 509 | return 1; | |
| 510 | } | |
| 511 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | |
| 512 | static inline int sci_rxd_in(struct uart_port *port) | |
| 513 | { | |
| 514 | if (port->mapbase == 0xfe600000) | |
| 515 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 516 | if (port->mapbase == 0xfe610000) | |
| 517 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 518 | if (port->mapbase == 0xfe620000) | |
| 519 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 520 | return 1; |
| 1da177e4 LT |
521 | } |
| 522 | #elif defined(CONFIG_CPU_SUBTYPE_SH7300) | |
| 523 | static inline int sci_rxd_in(struct uart_port *port) | |
| 524 | { | |
| 525 | if (port->mapbase == 0xa4430000) | |
| 526 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */ | |
| 527 | return 1; | |
| 528 | } | |
| 529 | #elif defined(CONFIG_CPU_SUBTYPE_SH73180) | |
| 530 | static inline int sci_rxd_in(struct uart_port *port) | |
| 531 | { | |
| 532 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */ | |
| 533 | } | |
| e108b2ca PM |
534 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
| 535 | static inline int sci_rxd_in(struct uart_port *port) | |
| 536 | { | |
| 537 | if (port->mapbase == 0xffe00000) | |
| 538 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 539 | if (port->mapbase == 0xffe10000) | |
| 540 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 541 | if (port->mapbase == 0xffe20000) | |
| 542 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 543 | if (port->mapbase == 0xffe30000) | |
| 544 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 545 | return 1; | |
| 546 | } | |
| 41504c39 PM |
547 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 548 | static inline int sci_rxd_in(struct uart_port *port) | |
| 549 | { | |
| 550 | if (port->mapbase == 0xffe00000) | |
| 551 | return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | |
| 552 | return 1; | |
| 553 | } | |
| 1da177e4 LT |
554 | #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) |
| 555 | static inline int sci_rxd_in(struct uart_port *port) | |
| 556 | { | |
| 557 | if (port->mapbase == 0xffe00000) | |
| 558 | return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */ | |
| 559 | else | |
| 560 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
| 561 | ||
| 562 | } | |
| 563 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | |
| 564 | static inline int sci_rxd_in(struct uart_port *port) | |
| 565 | { | |
| 566 | return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ | |
| 567 | } | |
| 568 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 569 | static inline int sci_rxd_in(struct uart_port *port) | |
| 570 | { | |
| 571 | int ch = (port->mapbase - SMR0) >> 3; | |
| 572 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | |
| 573 | } | |
| b7a76e4b PM |
574 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
| 575 | static inline int sci_rxd_in(struct uart_port *port) | |
| 576 | { | |
| 577 | if (port->mapbase == 0xff923000) | |
| 578 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 579 | if (port->mapbase == 0xff924000) | |
| 580 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 581 | if (port->mapbase == 0xff925000) | |
| 582 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 583 | return 1; |
| b7a76e4b PM |
584 | } |
| 585 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | |
| 586 | static inline int sci_rxd_in(struct uart_port *port) | |
| 587 | { | |
| 588 | if (port->mapbase == 0xffe00000) | |
| 589 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 590 | if (port->mapbase == 0xffe10000) | |
| 591 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 592 | return 1; |
| b7a76e4b | 593 | } |
| 32351a28 PM |
594 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
| 595 | static inline int sci_rxd_in(struct uart_port *port) | |
| 596 | { | |
| 597 | if (port->mapbase == 0xffea0000) | |
| 598 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 599 | if (port->mapbase == 0xffeb0000) | |
| 600 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 601 | if (port->mapbase == 0xffec0000) | |
| 602 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 603 | if (port->mapbase == 0xffed0000) | |
| 604 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 605 | if (port->mapbase == 0xffee0000) | |
| 606 | return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 607 | if (port->mapbase == 0xffef0000) | |
| 608 | return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 609 | return 1; | |
| 610 | } | |
| 9d4436a6 YS |
611 | #elif defined(CONFIG_CPU_SUBTYPE_SH7206) |
| 612 | static inline int sci_rxd_in(struct uart_port *port) | |
| 613 | { | |
| 614 | if (port->mapbase == 0xfffe8000) | |
| 615 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 616 | if (port->mapbase == 0xfffe8800) | |
| 617 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 618 | if (port->mapbase == 0xfffe9000) | |
| 619 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 620 | if (port->mapbase == 0xfffe9800) | |
| 621 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 622 | return 1; |
| 9d4436a6 YS |
623 | } |
| 624 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
| 625 | static inline int sci_rxd_in(struct uart_port *port) | |
| 626 | { | |
| 627 | if (port->mapbase == 0xf8400000) | |
| 628 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 629 | if (port->mapbase == 0xf8410000) | |
| 630 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 631 | if (port->mapbase == 0xf8420000) | |
| 632 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 633 | return 1; |
| 9d4436a6 | 634 | } |
| 1da177e4 LT |
635 | #endif |
| 636 | ||
| 637 | /* | |
| 638 | * Values for the BitRate Register (SCBRR) | |
| 639 | * | |
| 640 | * The values are actually divisors for a frequency which can | |
| 641 | * be internal to the SH3 (14.7456MHz) or derived from an external | |
| 642 | * clock source. This driver assumes the internal clock is used; | |
| 643 | * to support using an external clock source, config options or | |
| 644 | * possibly command-line options would need to be added. | |
| 645 | * | |
| 646 | * Also, to support speeds below 2400 (why?) the lower 2 bits of | |
| 647 | * the SCSMR register would also need to be set to non-zero values. | |
| 648 | * | |
| 649 | * -- Greg Banks 27Feb2000 | |
| 650 | * | |
| 651 | * Answer: The SCBRR register is only eight bits, and the value in | |
| 652 | * it gets larger with lower baud rates. At around 2400 (depending on | |
| 653 | * the peripherial module clock) you run out of bits. However the | |
| 654 | * lower two bits of SCSMR allow the module clock to be divided down, | |
| 655 | * scaling the value which is needed in SCBRR. | |
| 656 | * | |
| 657 | * -- Stuart Menefy - 23 May 2000 | |
| 658 | * | |
| 659 | * I meant, why would anyone bother with bitrates below 2400. | |
| 660 | * | |
| 661 | * -- Greg Banks - 7Jul2000 | |
| 662 | * | |
| 663 | * You "speedist"! How will I use my 110bps ASR-33 teletype with paper | |
| 664 | * tape reader as a console! | |
| 665 | * | |
| 666 | * -- Mitch Davis - 15 Jul 2000 | |
| 667 | */ | |
| 668 | ||
| 32351a28 PM |
669 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \ |
| 670 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
| 671 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
| b7a76e4b | 672 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
| 1da177e4 | 673 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
| b7a76e4b PM |
674 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
| 675 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 1da177e4 | 676 | #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) |
| b7a76e4b PM |
677 | #elif defined(CONFIG_SUPERH64) |
| 678 | #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1) | |
| 679 | #else /* Generic SH */ | |
| 680 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | |
| 1da177e4 | 681 | #endif |