projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 | 1 | #include <linux/serial_core.h> |
| e108b2ca | 2 | #include <asm/io.h> |
| 1da177e4 | 3 | #include <asm/gpio.h> |
| 3ea6bc3d | 4 | |
| 1da177e4 LT |
5 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) |
| 6 | #include <asm/regs306x.h> | |
| 7 | #endif | |
| 8 | #if defined(CONFIG_H8S2678) | |
| 9 | #include <asm/regs267x.h> | |
| 10 | #endif | |
| 1da177e4 | 11 | |
| 0fbde950 MD |
12 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 13 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
| 14 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
| 15 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
| 1da177e4 LT |
16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
| 17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | |
| 18 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | |
| 1da177e4 LT |
19 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
| 20 | # define SCIF0 0xA4400000 | |
| 21 | # define SCIF2 0xA4410000 | |
| b7a76e4b PM |
22 | # define SCSMR_Ir 0xA44A0000 |
| 23 | # define IRDA_SCIF SCIF0 | |
| 1da177e4 LT |
24 | # define SCPCR 0xA4000116 |
| 25 | # define SCPDR 0xA4000136 | |
| 26 | ||
| 27 | /* Set the clock source, | |
| 28 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input | |
| 29 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | |
| 30 | */ | |
| 31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | |
| 31a49c4b YS |
32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 33 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 3ea6bc3d | 34 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| 3ea6bc3d | 35 | #define SCIF_ORER 0x0200 /* overrun error bit */ |
| 1da177e4 | 36 | #elif defined(CONFIG_SH_RTS7751R2D) |
| 1da177e4 LT |
37 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
| 38 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 39 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 05627486 PM |
40 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 41 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
| 42 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
| 43 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
| 44 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 45 | defined(CONFIG_CPU_SUBTYPE_SH7751R) | |
| 1da177e4 LT |
46 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
| 47 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | |
| 48 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 49 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | |
| 50 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | |
| 51 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | |
| 1da177e4 | 52 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
| b7a76e4b PM |
53 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
| 54 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | |
| 55 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | |
| 1da177e4 LT |
56 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 57 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 2b1bd1ac | 58 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| e108b2ca | 59 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
| 9465a54f NI |
60 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 61 | # define PACR 0xa4050100 | |
| 62 | # define PBCR 0xa4050102 | |
| 63 | # define SCSCR_INIT(port) 0x3B | |
| e108b2ca PM |
64 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
| 65 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | |
| 66 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | |
| 67 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | |
| 68 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | |
| 69 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | |
| 41504c39 | 70 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 346b7463 MD |
71 | # define PADR 0xA4050120 |
| 72 | # define PSDR 0xA405013e | |
| 73 | # define PWDR 0xA4050166 | |
| 74 | # define PSCR 0xA405011E | |
| 41504c39 PM |
75 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| 76 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 9109a30e MD |
77 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
| 78 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | |
| 79 | # define SCSPTR0 SCPDR0 | |
| 80 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 81 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 178dd0cd PM |
82 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
| 83 | # define SCSPTR0 0xa4050160 | |
| 84 | # define SCSPTR1 0xa405013e | |
| 85 | # define SCSPTR2 0xa4050160 | |
| 86 | # define SCSPTR3 0xa405013e | |
| 87 | # define SCSPTR4 0xa4050128 | |
| 88 | # define SCSPTR5 0xa4050128 | |
| 89 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 90 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 1da177e4 | 91 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
| 1da177e4 LT |
92 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
| 93 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 94 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 1da177e4 | 95 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
| 1da177e4 LT |
96 | # define SCIF_BASE_ADDR 0x01030000 |
| 97 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | |
| 98 | # define SCIF_PTR2_OFFS 0x0000020 | |
| 99 | # define SCIF_LSR2_OFFS 0x0000024 | |
| 1da177e4 LT |
100 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
| 101 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | |
| f9669187 | 102 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ |
| 1da177e4 | 103 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) |
| 1da177e4 | 104 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| 1da177e4 LT |
105 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
| 106 | #elif defined(CONFIG_H8S2678) | |
| 1da177e4 | 107 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| 1da177e4 | 108 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
| 7d740a06 YS |
109 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 110 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
| 111 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ | |
| c63847a3 | 112 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ |
| 7d740a06 | 113 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| c63847a3 | 114 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| b7a76e4b PM |
115 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
| 116 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | |
| 117 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | |
| 118 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | |
| 119 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 120 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | |
| b7a76e4b PM |
121 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
| 122 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | |
| 123 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | |
| e108b2ca | 124 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| b7a76e4b | 125 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| 32351a28 PM |
126 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
| 127 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | |
| 128 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | |
| 129 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ | |
| 130 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ | |
| 131 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | |
| 132 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | |
| 133 | # define SCIF_OPER 0x0001 /* Overrun error bit */ | |
| 134 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 6d01f510 | 135 | #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ |
| a8f67f4b PM |
136 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
| 137 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
| 9d4436a6 YS |
138 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ |
| 139 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | |
| 140 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | |
| 141 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | |
| 142 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 9d4436a6 YS |
143 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
| 144 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | |
| 145 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | |
| 146 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | |
| 147 | # define SCIF_ORER 0x0001 /* overrun error bit */ | |
| 148 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 2b1bd1ac PM |
149 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
| 150 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | |
| 151 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | |
| 152 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ | |
| 153 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | |
| 154 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | |
| 155 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | |
| 1da177e4 LT |
156 | #else |
| 157 | # error CPU subtype not defined | |
| 158 | #endif | |
| 159 | ||
| 160 | /* SCSCR */ | |
| 161 | #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ | |
| 162 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ | |
| 163 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ | |
| 164 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ | |
| 05627486 PM |
165 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 166 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | |
| 167 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
| 168 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
| 169 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 170 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | |
| c63847a3 | 171 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
| 05627486 | 172 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
| 2b1bd1ac PM |
173 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
| 174 | defined(CONFIG_CPU_SUBTYPE_SHX3) | |
| 1da177e4 LT |
175 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ |
| 176 | #else | |
| 177 | #define SCI_CTRL_FLAGS_REIE 0 | |
| 178 | #endif | |
| 179 | /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 180 | /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 181 | /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ | |
| 182 | /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ | |
| 183 | ||
| 184 | /* SCxSR SCI */ | |
| 185 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 186 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 187 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 188 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 189 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 190 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 191 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 192 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | |
| 193 | ||
| 194 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) | |
| 195 | ||
| 196 | /* SCxSR SCIF */ | |
| 197 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 198 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 199 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 200 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 201 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 202 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 203 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 204 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | |
| 205 | ||
| 3ea6bc3d | 206 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
207 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 208 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| c63847a3 NI |
209 | # define SCIF_ORER 0x0200 |
| 210 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | |
| 211 | # define SCIF_RFDC_MASK 0x007f | |
| 212 | # define SCIF_TXROOM_MAX 64 | |
| 213 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | |
| 214 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK ) | |
| 215 | # define SCIF_RFDC_MASK 0x007f | |
| 216 | # define SCIF_TXROOM_MAX 64 | |
| 217 | /* SH7763 SCIF2 support */ | |
| 218 | # define SCIF2_RFDC_MASK 0x001f | |
| 219 | # define SCIF2_TXROOM_MAX 16 | |
| 1da177e4 | 220 | #else |
| c63847a3 NI |
221 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
| 222 | # define SCIF_RFDC_MASK 0x001f | |
| 223 | # define SCIF_TXROOM_MAX 16 | |
| 1da177e4 LT |
224 | #endif |
| 225 | ||
| 15c73aaa PM |
226 | #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
| 227 | #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | |
| 228 | #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | |
| 229 | #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | |
| 230 | #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | |
| 231 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | |
| 232 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | |
| 233 | ||
| d89ddd1c | 234 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) |
| 15c73aaa | 235 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) |
| 1da177e4 | 236 | #else |
| 15c73aaa | 237 | # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000) |
| 1da177e4 | 238 | #endif |
| 15c73aaa | 239 | |
| 3ea6bc3d | 240 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
241 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 242 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 15c73aaa PM |
243 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
| 244 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) | |
| 245 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) | |
| 246 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) | |
| 1da177e4 | 247 | #else |
| 1da177e4 LT |
248 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) |
| 249 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | |
| 250 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | |
| 251 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | |
| 252 | #endif | |
| 253 | ||
| 254 | /* SCFCR */ | |
| 255 | #define SCFCR_RFRST 0x0002 | |
| 256 | #define SCFCR_TFRST 0x0004 | |
| 257 | #define SCFCR_TCRST 0x4000 | |
| 258 | #define SCFCR_MCE 0x0008 | |
| 259 | ||
| 260 | #define SCI_MAJOR 204 | |
| 261 | #define SCI_MINOR_START 8 | |
| 262 | ||
| 263 | /* Generic serial flags */ | |
| 264 | #define SCI_RX_THROTTLE 0x0000001 | |
| 265 | ||
| 266 | #define SCI_MAGIC 0xbabeface | |
| 267 | ||
| 268 | /* | |
| 269 | * Events are used to schedule things to happen at timer-interrupt | |
| 270 | * time, instead of at rs interrupt time. | |
| 271 | */ | |
| 272 | #define SCI_EVENT_WRITE_WAKEUP 0 | |
| 273 | ||
| 1da177e4 | 274 | #define SCI_IN(size, offset) \ |
| b7a76e4b | 275 | if ((size) == 8) { \ |
| 7ff731ae | 276 | return ioread8(port->membase + (offset)); \ |
| b7a76e4b | 277 | } else { \ |
| 7ff731ae | 278 | return ioread16(port->membase + (offset)); \ |
| 1da177e4 LT |
279 | } |
| 280 | #define SCI_OUT(size, offset, value) \ | |
| b7a76e4b | 281 | if ((size) == 8) { \ |
| 7ff731ae | 282 | iowrite8(value, port->membase + (offset)); \ |
| 3d2c2f3e | 283 | } else if ((size) == 16) { \ |
| 7ff731ae | 284 | iowrite16(value, port->membase + (offset)); \ |
| 1da177e4 LT |
285 | } |
| 286 | ||
| 287 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | |
| 288 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
| 289 | { \ | |
| b7a76e4b | 290 | if (port->type == PORT_SCI) { \ |
| 1da177e4 LT |
291 | SCI_IN(sci_size, sci_offset) \ |
| 292 | } else { \ | |
| b7a76e4b | 293 | SCI_IN(scif_size, scif_offset); \ |
| 1da177e4 LT |
294 | } \ |
| 295 | } \ | |
| 296 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
| 297 | { \ | |
| 298 | if (port->type == PORT_SCI) { \ | |
| 299 | SCI_OUT(sci_size, sci_offset, value) \ | |
| 300 | } else { \ | |
| 301 | SCI_OUT(scif_size, scif_offset, value); \ | |
| 302 | } \ | |
| 303 | } | |
| 304 | ||
| 305 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | |
| 306 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | |
| 307 | { \ | |
| b7a76e4b | 308 | SCI_IN(scif_size, scif_offset); \ |
| 1da177e4 LT |
309 | } \ |
| 310 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | |
| 311 | { \ | |
| 312 | SCI_OUT(scif_size, scif_offset, value); \ | |
| 313 | } | |
| 314 | ||
| 315 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ | |
| 316 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ | |
| 317 | { \ | |
| b7a76e4b | 318 | SCI_IN(sci_size, sci_offset); \ |
| 1da177e4 LT |
319 | } \ |
| 320 | static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ | |
| 321 | { \ | |
| 322 | SCI_OUT(sci_size, sci_offset, value); \ | |
| 323 | } | |
| 324 | ||
| 325 | #ifdef CONFIG_CPU_SH3 | |
| 9465a54f NI |
326 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| 327 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 328 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 329 | h8_sci_offset, h8_sci_size) \ | |
| 330 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
| 331 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 332 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 3ea6bc3d | 333 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
334 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 335 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 1da177e4 LT |
336 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
| 337 | CPU_SCIF_FNS(name, scif_offset, scif_size) | |
| 338 | #else | |
| 339 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 340 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 341 | h8_sci_offset, h8_sci_size) \ | |
| 342 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) | |
| 343 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 344 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) | |
| 345 | #endif | |
| 346 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 347 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 348 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 349 | h8_sci_offset, h8_sci_size) \ | |
| 350 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | |
| 351 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) | |
| 178dd0cd PM |
352 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
| 353 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ | |
| 354 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) | |
| 355 | #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ | |
| 356 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 1da177e4 LT |
357 | #else |
| 358 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | |
| 359 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | |
| 360 | h8_sci_offset, h8_sci_size) \ | |
| 361 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | |
| 362 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | |
| 363 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | |
| 364 | #endif | |
| 365 | ||
| 3ea6bc3d | 366 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
367 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 368 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 9465a54f | 369 | |
| 1da177e4 LT |
370 | SCIF_FNS(SCSMR, 0x00, 16) |
| 371 | SCIF_FNS(SCBRR, 0x04, 8) | |
| 372 | SCIF_FNS(SCSCR, 0x08, 16) | |
| 373 | SCIF_FNS(SCTDSR, 0x0c, 8) | |
| 374 | SCIF_FNS(SCFER, 0x10, 16) | |
| 375 | SCIF_FNS(SCxSR, 0x14, 16) | |
| 376 | SCIF_FNS(SCFCR, 0x18, 16) | |
| 377 | SCIF_FNS(SCFDR, 0x1c, 16) | |
| 378 | SCIF_FNS(SCxTDR, 0x20, 8) | |
| 379 | SCIF_FNS(SCxRDR, 0x24, 8) | |
| 380 | SCIF_FNS(SCLSR, 0x24, 16) | |
| 178dd0cd PM |
381 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
| 382 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) | |
| 383 | SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) | |
| 384 | SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) | |
| 385 | SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) | |
| 386 | SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) | |
| 387 | SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) | |
| 388 | SCIF_FNS(SCTDSR, 0x0c, 8) | |
| 389 | SCIF_FNS(SCFER, 0x10, 16) | |
| 390 | SCIF_FNS(SCFCR, 0x18, 16) | |
| 391 | SCIF_FNS(SCFDR, 0x1c, 16) | |
| 392 | SCIF_FNS(SCLSR, 0x24, 16) | |
| 1da177e4 LT |
393 | #else |
| 394 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ | |
| 395 | /* name off sz off sz off sz off sz off sz*/ | |
| 396 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) | |
| 397 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) | |
| 398 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) | |
| 399 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | |
| 400 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | |
| 401 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | |
| 402 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | |
| 32351a28 PM |
403 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
| 404 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
| 405 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
| c2697968 | 406 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| b7a76e4b PM |
407 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
| 408 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
| 409 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
| 410 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
| c2697968 | 411 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| c63847a3 NI |
412 | SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) |
| 413 | SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) | |
| c2697968 PM |
414 | SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) |
| 415 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) | |
| 416 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | |
| 417 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | |
| 418 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | |
| b7a76e4b | 419 | #else |
| 1da177e4 | 420 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| 9b4e466f MD |
421 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 422 | SCIF_FNS(SCSPTR, 0, 0, 0, 0) | |
| 423 | #else | |
| 1da177e4 | 424 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) |
| 9b4e466f | 425 | #endif |
| 1da177e4 LT |
426 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) |
| 427 | #endif | |
| b7a76e4b | 428 | #endif |
| 1da177e4 LT |
429 | #define sci_in(port, reg) sci_##reg##_in(port) |
| 430 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | |
| 431 | ||
| 432 | /* H8/300 series SCI pins assignment */ | |
| 433 | #if defined(__H8300H__) || defined(__H8300S__) | |
| 434 | static const struct __attribute__((packed)) { | |
| 435 | int port; /* GPIO port no */ | |
| 436 | unsigned short rx,tx; /* GPIO bit no */ | |
| 437 | } h8300_sci_pins[] = { | |
| 438 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | |
| 439 | { /* SCI0 */ | |
| 440 | .port = H8300_GPIO_P9, | |
| 441 | .rx = H8300_GPIO_B2, | |
| 442 | .tx = H8300_GPIO_B0, | |
| 443 | }, | |
| 444 | { /* SCI1 */ | |
| 445 | .port = H8300_GPIO_P9, | |
| 446 | .rx = H8300_GPIO_B3, | |
| 447 | .tx = H8300_GPIO_B1, | |
| 448 | }, | |
| 449 | { /* SCI2 */ | |
| 450 | .port = H8300_GPIO_PB, | |
| 451 | .rx = H8300_GPIO_B7, | |
| 452 | .tx = H8300_GPIO_B6, | |
| 453 | } | |
| 454 | #elif defined(CONFIG_H8S2678) | |
| 455 | { /* SCI0 */ | |
| 456 | .port = H8300_GPIO_P3, | |
| 457 | .rx = H8300_GPIO_B2, | |
| 458 | .tx = H8300_GPIO_B0, | |
| 459 | }, | |
| 460 | { /* SCI1 */ | |
| 461 | .port = H8300_GPIO_P3, | |
| 462 | .rx = H8300_GPIO_B3, | |
| 463 | .tx = H8300_GPIO_B1, | |
| 464 | }, | |
| 465 | { /* SCI2 */ | |
| 466 | .port = H8300_GPIO_P5, | |
| 467 | .rx = H8300_GPIO_B1, | |
| 468 | .tx = H8300_GPIO_B0, | |
| 469 | } | |
| 470 | #endif | |
| 471 | }; | |
| 472 | #endif | |
| 473 | ||
| 0fbde950 MD |
474 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
| 475 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
| 476 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | |
| 477 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
| 1da177e4 LT |
478 | static inline int sci_rxd_in(struct uart_port *port) |
| 479 | { | |
| 480 | if (port->mapbase == 0xfffffe80) | |
| 481 | return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
| 482 | if (port->mapbase == 0xa4000150) | |
| 483 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
| 484 | if (port->mapbase == 0xa4000140) | |
| 485 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
| 486 | return 1; | |
| 487 | } | |
| 488 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
| 489 | static inline int sci_rxd_in(struct uart_port *port) | |
| 490 | { | |
| 491 | if (port->mapbase == SCIF0) | |
| 492 | return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
| 493 | if (port->mapbase == SCIF2) | |
| 494 | return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
| 495 | return 1; | |
| 496 | } | |
| 9465a54f | 497 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
| e108b2ca PM |
498 | static inline int sci_rxd_in(struct uart_port *port) |
| 499 | { | |
| 9465a54f NI |
500 | return sci_in(port,SCxSR)&0x0010 ? 1 : 0; |
| 501 | } | |
| 502 | static inline void set_sh771x_scif_pfc(struct uart_port *port) | |
| 503 | { | |
| 504 | if (port->mapbase == 0xA4400000){ | |
| 505 | ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR); | |
| 506 | ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR); | |
| 507 | return; | |
| 508 | } | |
| 509 | if (port->mapbase == 0xA4410000){ | |
| 510 | ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR); | |
| 511 | return; | |
| 512 | } | |
| e108b2ca | 513 | } |
| 31a49c4b YS |
514 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 515 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| 3ea6bc3d MB |
516 | static inline int sci_rxd_in(struct uart_port *port) |
| 517 | { | |
| 518 | if (port->mapbase == 0xa4430000) | |
| 519 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | |
| 520 | else if (port->mapbase == 0xa4438000) | |
| 521 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | |
| 522 | return 1; | |
| 523 | } | |
| 05627486 PM |
524 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
| 525 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
| 526 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | |
| 527 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | |
| 528 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | |
| 961e9ff9 | 529 | defined(CONFIG_CPU_SUBTYPE_SH7091) |
| 1da177e4 LT |
530 | static inline int sci_rxd_in(struct uart_port *port) |
| 531 | { | |
| 1da177e4 LT |
532 | if (port->mapbase == 0xffe00000) |
| 533 | return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | |
| 1da177e4 LT |
534 | if (port->mapbase == 0xffe80000) |
| 535 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
| 1da177e4 LT |
536 | return 1; |
| 537 | } | |
| 961e9ff9 NI |
538 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
| 539 | static inline int sci_rxd_in(struct uart_port *port) | |
| 540 | { | |
| 541 | if (port->mapbase == 0xffe80000) | |
| 542 | return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
| 543 | return 1; | |
| 544 | } | |
| 1da177e4 LT |
545 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
| 546 | static inline int sci_rxd_in(struct uart_port *port) | |
| 547 | { | |
| 548 | if (port->mapbase == 0xfe600000) | |
| 549 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 550 | if (port->mapbase == 0xfe610000) | |
| 551 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 552 | if (port->mapbase == 0xfe620000) | |
| 553 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 554 | return 1; |
| 1da177e4 | 555 | } |
| e108b2ca PM |
556 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
| 557 | static inline int sci_rxd_in(struct uart_port *port) | |
| 558 | { | |
| 559 | if (port->mapbase == 0xffe00000) | |
| 560 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 561 | if (port->mapbase == 0xffe10000) | |
| 562 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 563 | if (port->mapbase == 0xffe20000) | |
| 564 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 565 | if (port->mapbase == 0xffe30000) | |
| 566 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 567 | return 1; | |
| 568 | } | |
| 346b7463 | 569 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
| 41504c39 PM |
570 | static inline int sci_rxd_in(struct uart_port *port) |
| 571 | { | |
| 572 | if (port->mapbase == 0xffe00000) | |
| 573 | return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | |
| 574 | return 1; | |
| 575 | } | |
| 346b7463 MD |
576 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
| 577 | static inline int sci_rxd_in(struct uart_port *port) | |
| 578 | { | |
| 579 | if (port->mapbase == 0xffe00000) | |
| 580 | return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ | |
| 581 | if (port->mapbase == 0xffe10000) | |
| 582 | return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ | |
| 583 | if (port->mapbase == 0xffe20000) | |
| 584 | return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ | |
| 585 | ||
| 586 | return 1; | |
| 587 | } | |
| 178dd0cd PM |
588 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
| 589 | static inline int sci_rxd_in(struct uart_port *port) | |
| 590 | { | |
| 591 | if (port->mapbase == 0xffe00000) | |
| 592 | return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ | |
| 593 | if (port->mapbase == 0xffe10000) | |
| 594 | return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ | |
| 595 | if (port->mapbase == 0xffe20000) | |
| 596 | return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ | |
| 597 | if (port->mapbase == 0xa4e30000) | |
| 598 | return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ | |
| 599 | if (port->mapbase == 0xa4e40000) | |
| 600 | return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ | |
| 601 | if (port->mapbase == 0xa4e50000) | |
| 602 | return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ | |
| 603 | return 1; | |
| 604 | } | |
| 1da177e4 LT |
605 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
| 606 | static inline int sci_rxd_in(struct uart_port *port) | |
| 607 | { | |
| aeffd54a | 608 | return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ |
| 1da177e4 LT |
609 | } |
| 610 | #elif defined(__H8300H__) || defined(__H8300S__) | |
| 611 | static inline int sci_rxd_in(struct uart_port *port) | |
| 612 | { | |
| 613 | int ch = (port->mapbase - SMR0) >> 3; | |
| 614 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | |
| 615 | } | |
| 7d740a06 YS |
616 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
| 617 | static inline int sci_rxd_in(struct uart_port *port) | |
| 618 | { | |
| 619 | if (port->mapbase == 0xffe00000) | |
| 620 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 621 | if (port->mapbase == 0xffe08000) | |
| 622 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| c63847a3 NI |
623 | if (port->mapbase == 0xffe10000) |
| 624 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ | |
| 625 | ||
| 7d740a06 YS |
626 | return 1; |
| 627 | } | |
| b7a76e4b PM |
628 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
| 629 | static inline int sci_rxd_in(struct uart_port *port) | |
| 630 | { | |
| 631 | if (port->mapbase == 0xff923000) | |
| 632 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 633 | if (port->mapbase == 0xff924000) | |
| 634 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 635 | if (port->mapbase == 0xff925000) | |
| 636 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 637 | return 1; |
| b7a76e4b PM |
638 | } |
| 639 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | |
| 640 | static inline int sci_rxd_in(struct uart_port *port) | |
| 641 | { | |
| 642 | if (port->mapbase == 0xffe00000) | |
| 643 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 644 | if (port->mapbase == 0xffe10000) | |
| 645 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 646 | return 1; |
| b7a76e4b | 647 | } |
| 32351a28 PM |
648 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) |
| 649 | static inline int sci_rxd_in(struct uart_port *port) | |
| 650 | { | |
| 651 | if (port->mapbase == 0xffea0000) | |
| 652 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 653 | if (port->mapbase == 0xffeb0000) | |
| 654 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 655 | if (port->mapbase == 0xffec0000) | |
| 656 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 657 | if (port->mapbase == 0xffed0000) | |
| 658 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 659 | if (port->mapbase == 0xffee0000) | |
| 660 | return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 661 | if (port->mapbase == 0xffef0000) | |
| 662 | return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 663 | return 1; | |
| 664 | } | |
| 6d01f510 | 665 | #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ |
| a8f67f4b PM |
666 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ |
| 667 | defined(CONFIG_CPU_SUBTYPE_SH7263) | |
| 9d4436a6 YS |
668 | static inline int sci_rxd_in(struct uart_port *port) |
| 669 | { | |
| 670 | if (port->mapbase == 0xfffe8000) | |
| 671 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 672 | if (port->mapbase == 0xfffe8800) | |
| 673 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 674 | if (port->mapbase == 0xfffe9000) | |
| 675 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 676 | if (port->mapbase == 0xfffe9800) | |
| 677 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 678 | return 1; |
| 9d4436a6 YS |
679 | } |
| 680 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
| 681 | static inline int sci_rxd_in(struct uart_port *port) | |
| 682 | { | |
| 683 | if (port->mapbase == 0xf8400000) | |
| 684 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 685 | if (port->mapbase == 0xf8410000) | |
| 686 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 687 | if (port->mapbase == 0xf8420000) | |
| 688 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 31388750 | 689 | return 1; |
| 9d4436a6 | 690 | } |
| 2b1bd1ac PM |
691 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
| 692 | static inline int sci_rxd_in(struct uart_port *port) | |
| 693 | { | |
| 694 | if (port->mapbase == 0xffc30000) | |
| 695 | return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 696 | if (port->mapbase == 0xffc40000) | |
| 697 | return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 698 | if (port->mapbase == 0xffc50000) | |
| 699 | return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 700 | if (port->mapbase == 0xffc60000) | |
| 701 | return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
| 1760b7d7 | 702 | return 1; |
| 2b1bd1ac | 703 | } |
| 1da177e4 LT |
704 | #endif |
| 705 | ||
| 706 | /* | |
| 707 | * Values for the BitRate Register (SCBRR) | |
| 708 | * | |
| 709 | * The values are actually divisors for a frequency which can | |
| 710 | * be internal to the SH3 (14.7456MHz) or derived from an external | |
| 711 | * clock source. This driver assumes the internal clock is used; | |
| 712 | * to support using an external clock source, config options or | |
| 713 | * possibly command-line options would need to be added. | |
| 714 | * | |
| 715 | * Also, to support speeds below 2400 (why?) the lower 2 bits of | |
| 716 | * the SCSMR register would also need to be set to non-zero values. | |
| 717 | * | |
| 718 | * -- Greg Banks 27Feb2000 | |
| 719 | * | |
| 720 | * Answer: The SCBRR register is only eight bits, and the value in | |
| 721 | * it gets larger with lower baud rates. At around 2400 (depending on | |
| 722 | * the peripherial module clock) you run out of bits. However the | |
| 723 | * lower two bits of SCSMR allow the module clock to be divided down, | |
| 724 | * scaling the value which is needed in SCBRR. | |
| 725 | * | |
| 726 | * -- Stuart Menefy - 23 May 2000 | |
| 727 | * | |
| 728 | * I meant, why would anyone bother with bitrates below 2400. | |
| 729 | * | |
| 730 | * -- Greg Banks - 7Jul2000 | |
| 731 | * | |
| 732 | * You "speedist"! How will I use my 110bps ASR-33 teletype with paper | |
| 733 | * tape reader as a console! | |
| 734 | * | |
| 735 | * -- Mitch Davis - 15 Jul 2000 | |
| 736 | */ | |
| 737 | ||
| c63847a3 | 738 | #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
| 32351a28 | 739 | defined(CONFIG_CPU_SUBTYPE_SH7785) |
| b7a76e4b | 740 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
| 3ea6bc3d | 741 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
| 31a49c4b YS |
742 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
| 743 | defined(CONFIG_CPU_SUBTYPE_SH7721) | |
| b7a76e4b | 744 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
| 178dd0cd | 745 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
| ba1d2818 NI |
746 | static inline int scbrr_calc(struct uart_port *port, int bps, int clk) |
| 747 | { | |
| 748 | if (port->type == PORT_SCIF) | |
| 749 | return (clk+16*bps)/(32*bps)-1; | |
| 750 | else | |
| 751 | return ((clk*2)+16*bps)/(16*bps)-1; | |
| 752 | } | |
| 753 | #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) | |
| b7a76e4b | 754 | #elif defined(__H8300H__) || defined(__H8300S__) |
| a2159b52 | 755 | #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) |
| b7a76e4b PM |
756 | #else /* Generic SH */ |
| 757 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | |
| 1da177e4 | 758 | #endif |