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sh: Fixup dma_cache_sync() callers.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / serial / sh-sci.h
CommitLineData
1da177e4
LT		 1/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2 *
3 * linux/drivers/serial/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 */
1da177e4 13#include <linux/serial_core.h>
e108b2ca 14#include <asm/io.h>
1da177e4
LT		 15
16#if defined(__H8300H__) || defined(__H8300S__)
17#include <asm/gpio.h>
18#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
19#include <asm/regs306x.h>
20#endif
21#if defined(CONFIG_H8S2678)
22#include <asm/regs267x.h>
23#endif
24#endif
25
1da177e4 26#if defined(CONFIG_CPU_SUBTYPE_SH7708)
1da177e4
LT		 27# define SCSPTR 0xffffff7c /* 8 bit */
28# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
29# define SCI_ONLY
e108b2ca
PM		 30#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7706)
1da177e4
LT		 33# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
34# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
35# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
36# define SCI_AND_SCIF
37#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
38# define SCIF0 0xA4400000
39# define SCIF2 0xA4410000
b7a76e4b
PM		 40# define SCSMR_Ir 0xA44A0000
41# define IRDA_SCIF SCIF0
1da177e4
LT		 42# define SCPCR 0xA4000116
43# define SCPDR 0xA4000136
44
45/* Set the clock source,
46 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
47 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
48 */
49# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
50# define SCIF_ONLY
51#elif defined(CONFIG_SH_RTS7751R2D)
1da177e4
LT		 52# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
53# define SCIF_ORER 0x0001 /* overrun error bit */
54# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
55# define SCIF_ONLY
56#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1da177e4
LT		 57# define SCSPTR1 0xffe0001c /* 8 bit SCI */
58# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
59# define SCIF_ORER 0x0001 /* overrun error bit */
60# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
61 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
62 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
63# define SCI_AND_SCIF
64#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
b7a76e4b
PM		 65# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
66# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
67# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
1da177e4
LT		 68# define SCIF_ORER 0x0001 /* overrun error bit */
69# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
70# define SCIF_ONLY
71#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1da177e4
LT		 72# define SCPCR 0xA4050116 /* 16 bit SCIF */
73# define SCPDR 0xA4050136 /* 16 bit SCIF */
74# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
75# define SCIF_ONLY
e108b2ca
PM		 76#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
77# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
78# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
79# define SCIF_ONLY
1da177e4 80#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
1da177e4
LT		 81# define SCPDR 0xA4050138 /* 16 bit SCIF */
82# define SCSPTR2 SCPDR
83# define SCIF_ORER 0x0001 /* overrun error bit */
84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
85# define SCIF_ONLY
e108b2ca
PM		 86#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
87# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
88# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
89# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
90# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
91# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
92# define SCIF_ONLY
1da177e4 93#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 94# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
95# define SCIF_ORER 0x0001 /* overrun error bit */
96# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
97# define SCIF_ONLY
98#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1da177e4
LT		 99# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
100# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
101# define SCIF_ORER 0x0001 /* overrun error bit */
102# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
103# define SCIF_ONLY
104#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
105# include <asm/hardware.h>
106# define SCIF_BASE_ADDR 0x01030000
107# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
108# define SCIF_PTR2_OFFS 0x0000020
109# define SCIF_LSR2_OFFS 0x0000024
1da177e4
LT		 110# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
111# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
112# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
113 TE=1,RE=1,REIE=1 */
114# define SCIF_ONLY
115#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1da177e4
LT		 116# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
117# define SCI_ONLY
118# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
119#elif defined(CONFIG_H8S2678)
1da177e4
LT		 120# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
121# define SCI_ONLY
122# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
b7a76e4b
PM		 123#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
124# define SCSPTR0 0xff923020 /* 16 bit SCIF */
125# define SCSPTR1 0xff924020 /* 16 bit SCIF */
126# define SCSPTR2 0xff925020 /* 16 bit SCIF */
127# define SCIF_ORER 0x0001 /* overrun error bit */
128# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
129# define SCIF_ONLY
130#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
131# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
132# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
e108b2ca 133# define SCIF_ORER 0x0001 /* Overrun error bit */
b7a76e4b
PM		 134# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
135# define SCIF_ONLY
9d4436a6
YS		 136#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
137# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
138# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
139# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
140# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
141# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
142# define SCIF_ONLY
143#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
144# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
145# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
146# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
147# define SCIF_ORER 0x0001 /* overrun error bit */
148# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
149# define SCIF_ONLY
1da177e4
LT		 150#else
151# error CPU subtype not defined
152#endif
153
154/* SCSCR */
155#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
156#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
157#define SCI_CTRL_FLAGS_TE 0x20 /* all */
158#define SCI_CTRL_FLAGS_RE 0x10 /* all */
b7a76e4b 159#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780)
1da177e4
LT		 160#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
161#else
162#define SCI_CTRL_FLAGS_REIE 0
163#endif
164/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
165/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
166/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
167/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
168
169/* SCxSR SCI */
170#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
171#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
172#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
173#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
174#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
175#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
176/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
177/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
178
179#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
180
181/* SCxSR SCIF */
182#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
183#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
184#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
185#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
186#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
187#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
188#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
189#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
190
191#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
192#define SCIF_ORER 0x0200
193#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
194#define SCIF_RFDC_MASK 0x007f
195#define SCIF_TXROOM_MAX 64
196#else
197#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
198#define SCIF_RFDC_MASK 0x001f
199#define SCIF_TXROOM_MAX 16
200#endif
201
202#if defined(SCI_ONLY)
203# define SCxSR_TEND(port) SCI_TEND
204# define SCxSR_ERRORS(port) SCI_ERRORS
205# define SCxSR_RDxF(port) SCI_RDRF
206# define SCxSR_TDxE(port) SCI_TDRE
207# define SCxSR_ORER(port) SCI_ORER
208# define SCxSR_FER(port) SCI_FER
209# define SCxSR_PER(port) SCI_PER
210# define SCxSR_BRK(port) 0x00
211# define SCxSR_RDxF_CLEAR(port) 0xbc
212# define SCxSR_ERROR_CLEAR(port) 0xc4
213# define SCxSR_TDxE_CLEAR(port) 0x78
b7a76e4b 214# define SCxSR_BREAK_CLEAR(port) 0xc4
1da177e4
LT		 215#elif defined(SCIF_ONLY)
216# define SCxSR_TEND(port) SCIF_TEND
217# define SCxSR_ERRORS(port) SCIF_ERRORS
218# define SCxSR_RDxF(port) SCIF_RDF
219# define SCxSR_TDxE(port) SCIF_TDFE
220#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
221# define SCxSR_ORER(port) SCIF_ORER
222#else
223# define SCxSR_ORER(port) 0x0000
224#endif
225# define SCxSR_FER(port) SCIF_FER
226# define SCxSR_PER(port) SCIF_PER
227# define SCxSR_BRK(port) SCIF_BRK
228#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
229# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
230# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
231# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
232# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
233#else
234/* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
235# define SCxSR_RDxF_CLEAR(port) 0x00fc
236# define SCxSR_ERROR_CLEAR(port) 0x0073
237# define SCxSR_TDxE_CLEAR(port) 0x00df
b7a76e4b 238# define SCxSR_BREAK_CLEAR(port) 0x00e3
1da177e4
LT		 239#endif
240#else
241# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
242# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
243# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
244# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
245# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
246# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
247# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
248# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
249# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
250# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
251# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
252# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
253#endif
254
255/* SCFCR */
256#define SCFCR_RFRST 0x0002
257#define SCFCR_TFRST 0x0004
258#define SCFCR_TCRST 0x4000
259#define SCFCR_MCE 0x0008
260
261#define SCI_MAJOR 204
262#define SCI_MINOR_START 8
263
264/* Generic serial flags */
265#define SCI_RX_THROTTLE 0x0000001
266
267#define SCI_MAGIC 0xbabeface
268
269/*
270 * Events are used to schedule things to happen at timer-interrupt
271 * time, instead of at rs interrupt time.
272 */
273#define SCI_EVENT_WRITE_WAKEUP 0
274
1da177e4
LT		 275#define SCI_IN(size, offset) \
276 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 277 if ((size) == 8) { \
1da177e4 278 return ctrl_inb(addr); \
b7a76e4b 279 } else { \
1da177e4
LT		 280 return ctrl_inw(addr); \
281 }
282#define SCI_OUT(size, offset, value) \
283 unsigned int addr = port->mapbase + (offset); \
b7a76e4b 284 if ((size) == 8) { \
1da177e4
LT		 285 ctrl_outb(value, addr); \
286 } else { \
287 ctrl_outw(value, addr); \
288 }
289
290#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
291 static inline unsigned int sci_##name##_in(struct uart_port *port) \
292 { \
b7a76e4b 293 if (port->type == PORT_SCI) { \
1da177e4
LT		 294 SCI_IN(sci_size, sci_offset) \
295 } else { \
b7a76e4b 296 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 297 } \
298 } \
299 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
300 { \
301 if (port->type == PORT_SCI) { \
302 SCI_OUT(sci_size, sci_offset, value) \
303 } else { \
304 SCI_OUT(scif_size, scif_offset, value); \
305 } \
306 }
307
308#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
309 static inline unsigned int sci_##name##_in(struct uart_port *port) \
310 { \
b7a76e4b 311 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 312 } \
313 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
314 { \
315 SCI_OUT(scif_size, scif_offset, value); \
316 }
317
318#define CPU_SCI_FNS(name, sci_offset, sci_size) \
319 static inline unsigned int sci_##name##_in(struct uart_port* port) \
320 { \
b7a76e4b 321 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 322 } \
323 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
324 { \
325 SCI_OUT(sci_size, sci_offset, value); \
326 }
327
328#ifdef CONFIG_CPU_SH3
e108b2ca
PM		 329#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
330 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
331 defined(CONFIG_CPU_SUBTYPE_SH7710)
1da177e4
LT		 332#define SCIF_FNS(name, scif_offset, scif_size) \
333 CPU_SCIF_FNS(name, scif_offset, scif_size)
334#else
335#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
336 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
337 h8_sci_offset, h8_sci_size) \
338 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
339#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
340 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
341#endif
342#elif defined(__H8300H__) || defined(__H8300S__)
343#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
344 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
345 h8_sci_offset, h8_sci_size) \
346 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
347#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
348#else
349#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
350 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
351 h8_sci_offset, h8_sci_size) \
352 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
353#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
354 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
355#endif
356
e108b2ca
PM		 357#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
358 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
359 defined(CONFIG_CPU_SUBTYPE_SH7710)
1da177e4
LT		 360SCIF_FNS(SCSMR, 0x00, 16)
361SCIF_FNS(SCBRR, 0x04, 8)
362SCIF_FNS(SCSCR, 0x08, 16)
363SCIF_FNS(SCTDSR, 0x0c, 8)
364SCIF_FNS(SCFER, 0x10, 16)
365SCIF_FNS(SCxSR, 0x14, 16)
366SCIF_FNS(SCFCR, 0x18, 16)
367SCIF_FNS(SCFDR, 0x1c, 16)
368SCIF_FNS(SCxTDR, 0x20, 8)
369SCIF_FNS(SCxRDR, 0x24, 8)
370SCIF_FNS(SCLSR, 0x24, 16)
371#else
372/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
373/* name off sz off sz off sz off sz off sz*/
374SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
375SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
376SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
377SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
378SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
379SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
380SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
b7a76e4b 381#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
6fc21b82 382SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
b7a76e4b
PM		 383SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
384SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
385SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
386SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
387#else
1da177e4
LT		 388SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
389SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
390SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
391#endif
b7a76e4b 392#endif
1da177e4
LT		 393#define sci_in(port, reg) sci_##reg##_in(port)
394#define sci_out(port, reg, value) sci_##reg##_out(port, value)
395
396/* H8/300 series SCI pins assignment */
397#if defined(__H8300H__) || defined(__H8300S__)
398static const struct __attribute__((packed)) {
399 int port; /* GPIO port no */
400 unsigned short rx,tx; /* GPIO bit no */
401} h8300_sci_pins[] = {
402#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
403 { /* SCI0 */
404 .port = H8300_GPIO_P9,
405 .rx = H8300_GPIO_B2,
406 .tx = H8300_GPIO_B0,
407 },
408 { /* SCI1 */
409 .port = H8300_GPIO_P9,
410 .rx = H8300_GPIO_B3,
411 .tx = H8300_GPIO_B1,
412 },
413 { /* SCI2 */
414 .port = H8300_GPIO_PB,
415 .rx = H8300_GPIO_B7,
416 .tx = H8300_GPIO_B6,
417 }
418#elif defined(CONFIG_H8S2678)
419 { /* SCI0 */
420 .port = H8300_GPIO_P3,
421 .rx = H8300_GPIO_B2,
422 .tx = H8300_GPIO_B0,
423 },
424 { /* SCI1 */
425 .port = H8300_GPIO_P3,
426 .rx = H8300_GPIO_B3,
427 .tx = H8300_GPIO_B1,
428 },
429 { /* SCI2 */
430 .port = H8300_GPIO_P5,
431 .rx = H8300_GPIO_B1,
432 .tx = H8300_GPIO_B0,
433 }
434#endif
435};
436#endif
437
438#if defined(CONFIG_CPU_SUBTYPE_SH7708)
439static inline int sci_rxd_in(struct uart_port *port)
440{
441 if (port->mapbase == 0xfffffe80)
442 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
443 return 1;
444}
e108b2ca
PM		 445#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
446 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
447 defined(CONFIG_CPU_SUBTYPE_SH7706)
1da177e4
LT		 448static inline int sci_rxd_in(struct uart_port *port)
449{
450 if (port->mapbase == 0xfffffe80)
451 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
452 if (port->mapbase == 0xa4000150)
453 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
454 if (port->mapbase == 0xa4000140)
455 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
456 return 1;
457}
458#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
459static inline int sci_rxd_in(struct uart_port *port)
460{
461 if (port->mapbase == SCIF0)
462 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
463 if (port->mapbase == SCIF2)
464 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
465 return 1;
466}
e108b2ca
PM		 467#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
468static inline int sci_rxd_in(struct uart_port *port)
469{
470 if (port->mapbase == SCSPTR0)
471 return ctrl_inw(SCSPTR0 + 0x10) & 0x01 ? 1 : 0;
472 return 1;
473}
1da177e4
LT		 474#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
475 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
476 defined(CONFIG_CPU_SUBTYPE_SH4_202)
477static inline int sci_rxd_in(struct uart_port *port)
478{
479#ifndef SCIF_ONLY
480 if (port->mapbase == 0xffe00000)
481 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
482#endif
483#ifndef SCI_ONLY
484 if (port->mapbase == 0xffe80000)
485 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
486#endif
487 return 1;
488}
489#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
490static inline int sci_rxd_in(struct uart_port *port)
491{
492 if (port->mapbase == 0xfe600000)
493 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
494 if (port->mapbase == 0xfe610000)
495 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
496 if (port->mapbase == 0xfe620000)
497 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 498 return 1;
1da177e4
LT		 499}
500#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
501static inline int sci_rxd_in(struct uart_port *port)
502{
503 if (port->mapbase == 0xa4430000)
504 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
505 return 1;
506}
507#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
508static inline int sci_rxd_in(struct uart_port *port)
509{
510 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
511}
e108b2ca
PM		 512#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
513static inline int sci_rxd_in(struct uart_port *port)
514{
515 if (port->mapbase == 0xffe00000)
516 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
517 if (port->mapbase == 0xffe10000)
518 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
519 if (port->mapbase == 0xffe20000)
520 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
521 if (port->mapbase == 0xffe30000)
522 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
523 return 1;
524}
1da177e4
LT		 525#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
526static inline int sci_rxd_in(struct uart_port *port)
527{
528 if (port->mapbase == 0xffe00000)
529 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
530 else
531 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
532
533}
534#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
535static inline int sci_rxd_in(struct uart_port *port)
536{
537 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
538}
539#elif defined(__H8300H__) || defined(__H8300S__)
540static inline int sci_rxd_in(struct uart_port *port)
541{
542 int ch = (port->mapbase - SMR0) >> 3;
543 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
544}
b7a76e4b
PM		 545#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
546static inline int sci_rxd_in(struct uart_port *port)
547{
548 if (port->mapbase == 0xff923000)
549 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
550 if (port->mapbase == 0xff924000)
551 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
552 if (port->mapbase == 0xff925000)
553 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 554 return 1;
b7a76e4b
PM		 555}
556#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
557static inline int sci_rxd_in(struct uart_port *port)
558{
559 if (port->mapbase == 0xffe00000)
560 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
561 if (port->mapbase == 0xffe10000)
562 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
31388750 563 return 1;
b7a76e4b 564}
9d4436a6
YS		 565#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
566static inline int sci_rxd_in(struct uart_port *port)
567{
568 if (port->mapbase == 0xfffe8000)
569 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
570 if (port->mapbase == 0xfffe8800)
571 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
572 if (port->mapbase == 0xfffe9000)
573 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
574 if (port->mapbase == 0xfffe9800)
575 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
31388750 576 return 1;
9d4436a6
YS		 577}
578#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
579static inline int sci_rxd_in(struct uart_port *port)
580{
581 if (port->mapbase == 0xf8400000)
582 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
583 if (port->mapbase == 0xf8410000)
584 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
585 if (port->mapbase == 0xf8420000)
586 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
31388750 587 return 1;
9d4436a6 588}
1da177e4
LT		 589#endif
590
591/*
592 * Values for the BitRate Register (SCBRR)
593 *
594 * The values are actually divisors for a frequency which can
595 * be internal to the SH3 (14.7456MHz) or derived from an external
596 * clock source. This driver assumes the internal clock is used;
597 * to support using an external clock source, config options or
598 * possibly command-line options would need to be added.
599 *
600 * Also, to support speeds below 2400 (why?) the lower 2 bits of
601 * the SCSMR register would also need to be set to non-zero values.
602 *
603 * -- Greg Banks 27Feb2000
604 *
605 * Answer: The SCBRR register is only eight bits, and the value in
606 * it gets larger with lower baud rates. At around 2400 (depending on
607 * the peripherial module clock) you run out of bits. However the
608 * lower two bits of SCSMR allow the module clock to be divided down,
609 * scaling the value which is needed in SCBRR.
610 *
611 * -- Stuart Menefy - 23 May 2000
612 *
613 * I meant, why would anyone bother with bitrates below 2400.
614 *
615 * -- Greg Banks - 7Jul2000
616 *
617 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
618 * tape reader as a console!
619 *
620 * -- Mitch Davis - 15 Jul 2000
621 */
622
b7a76e4b
PM		 623#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780)
624#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
1da177e4 625#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
b7a76e4b
PM		 626#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
627#elif defined(__H8300H__) || defined(__H8300S__)
1da177e4 628#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
b7a76e4b
PM		 629#elif defined(CONFIG_SUPERH64)
630#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
631#else /* Generic SH */
632#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
1da177e4 633#endif
kernel source for telekom puls (alcatel/mediatek)