Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/pxa.c | |
3 | * | |
4 | * Based on drivers/serial/8250.c by Russell King. | |
5 | * | |
6 | * Author: Nicolas Pitre | |
7 | * Created: Feb 20, 2003 | |
8 | * Copyright: (C) 2003 Monta Vista Software, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * Note 1: This driver is made separate from the already too overloaded | |
16 | * 8250.c because it needs some kirks of its own and that'll make it | |
17 | * easier to add DMA support. | |
18 | * | |
19 | * Note 2: I'm too sick of device allocation policies for serial ports. | |
20 | * If someone else wants to request an "official" allocation of major/minor | |
21 | * for this driver please be my guest. And don't forget that new hardware | |
22 | * to come from Intel might have more than 3 or 4 of those UARTs. Let's | |
23 | * hope for a better port registration and dynamic device allocation scheme | |
24 | * with the serial core maintainer satisfaction to appear soon. | |
25 | */ | |
26 | ||
1da177e4 LT |
27 | |
28 | #if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
29 | #define SUPPORT_SYSRQ | |
30 | #endif | |
31 | ||
32 | #include <linux/module.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/console.h> | |
36 | #include <linux/sysrq.h> | |
37 | #include <linux/serial_reg.h> | |
38 | #include <linux/circ_buf.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
d052d1be | 41 | #include <linux/platform_device.h> |
1da177e4 LT |
42 | #include <linux/tty.h> |
43 | #include <linux/tty_flip.h> | |
44 | #include <linux/serial_core.h> | |
b049bd9d | 45 | #include <linux/clk.h> |
1da177e4 LT |
46 | |
47 | #include <asm/io.h> | |
a09e64fb | 48 | #include <mach/hardware.h> |
1da177e4 | 49 | #include <asm/irq.h> |
a09e64fb | 50 | #include <mach/pxa-regs.h> |
02f65262 | 51 | #include <mach/regs-uart.h> |
1da177e4 LT |
52 | |
53 | ||
54 | struct uart_pxa_port { | |
55 | struct uart_port port; | |
56 | unsigned char ier; | |
57 | unsigned char lcr; | |
58 | unsigned char mcr; | |
59 | unsigned int lsr_break_flag; | |
b049bd9d | 60 | struct clk *clk; |
1da177e4 LT |
61 | char *name; |
62 | }; | |
63 | ||
64 | static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) | |
65 | { | |
66 | offset <<= 2; | |
67 | return readl(up->port.membase + offset); | |
68 | } | |
69 | ||
70 | static inline void serial_out(struct uart_pxa_port *up, int offset, int value) | |
71 | { | |
72 | offset <<= 2; | |
73 | writel(value, up->port.membase + offset); | |
74 | } | |
75 | ||
76 | static void serial_pxa_enable_ms(struct uart_port *port) | |
77 | { | |
78 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
79 | ||
80 | up->ier |= UART_IER_MSI; | |
81 | serial_out(up, UART_IER, up->ier); | |
82 | } | |
83 | ||
b129a8cc | 84 | static void serial_pxa_stop_tx(struct uart_port *port) |
1da177e4 LT |
85 | { |
86 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
87 | ||
88 | if (up->ier & UART_IER_THRI) { | |
89 | up->ier &= ~UART_IER_THRI; | |
90 | serial_out(up, UART_IER, up->ier); | |
91 | } | |
92 | } | |
93 | ||
94 | static void serial_pxa_stop_rx(struct uart_port *port) | |
95 | { | |
96 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
97 | ||
98 | up->ier &= ~UART_IER_RLSI; | |
99 | up->port.read_status_mask &= ~UART_LSR_DR; | |
100 | serial_out(up, UART_IER, up->ier); | |
101 | } | |
102 | ||
7d12e780 | 103 | static inline void receive_chars(struct uart_pxa_port *up, int *status) |
1da177e4 | 104 | { |
a88487c7 | 105 | struct tty_struct *tty = up->port.info->port.tty; |
1da177e4 LT |
106 | unsigned int ch, flag; |
107 | int max_count = 256; | |
108 | ||
109 | do { | |
1da177e4 LT |
110 | ch = serial_in(up, UART_RX); |
111 | flag = TTY_NORMAL; | |
112 | up->port.icount.rx++; | |
113 | ||
114 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
115 | UART_LSR_FE | UART_LSR_OE))) { | |
116 | /* | |
117 | * For statistics only | |
118 | */ | |
119 | if (*status & UART_LSR_BI) { | |
120 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
121 | up->port.icount.brk++; | |
122 | /* | |
123 | * We do the SysRQ and SAK checking | |
124 | * here because otherwise the break | |
125 | * may get masked by ignore_status_mask | |
126 | * or read_status_mask. | |
127 | */ | |
128 | if (uart_handle_break(&up->port)) | |
129 | goto ignore_char; | |
130 | } else if (*status & UART_LSR_PE) | |
131 | up->port.icount.parity++; | |
132 | else if (*status & UART_LSR_FE) | |
133 | up->port.icount.frame++; | |
134 | if (*status & UART_LSR_OE) | |
135 | up->port.icount.overrun++; | |
136 | ||
137 | /* | |
138 | * Mask off conditions which should be ignored. | |
139 | */ | |
140 | *status &= up->port.read_status_mask; | |
141 | ||
142 | #ifdef CONFIG_SERIAL_PXA_CONSOLE | |
143 | if (up->port.line == up->port.cons->index) { | |
144 | /* Recover the break flag from console xmit */ | |
145 | *status |= up->lsr_break_flag; | |
146 | up->lsr_break_flag = 0; | |
147 | } | |
148 | #endif | |
149 | if (*status & UART_LSR_BI) { | |
150 | flag = TTY_BREAK; | |
151 | } else if (*status & UART_LSR_PE) | |
152 | flag = TTY_PARITY; | |
153 | else if (*status & UART_LSR_FE) | |
154 | flag = TTY_FRAME; | |
155 | } | |
05ab3014 | 156 | |
7d12e780 | 157 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 158 | goto ignore_char; |
05ab3014 RK |
159 | |
160 | uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); | |
161 | ||
1da177e4 LT |
162 | ignore_char: |
163 | *status = serial_in(up, UART_LSR); | |
164 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
165 | tty_flip_buffer_push(tty); | |
166 | } | |
167 | ||
168 | static void transmit_chars(struct uart_pxa_port *up) | |
169 | { | |
170 | struct circ_buf *xmit = &up->port.info->xmit; | |
171 | int count; | |
172 | ||
173 | if (up->port.x_char) { | |
174 | serial_out(up, UART_TX, up->port.x_char); | |
175 | up->port.icount.tx++; | |
176 | up->port.x_char = 0; | |
177 | return; | |
178 | } | |
179 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
b129a8cc | 180 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
181 | return; |
182 | } | |
183 | ||
184 | count = up->port.fifosize / 2; | |
185 | do { | |
186 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
187 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
188 | up->port.icount.tx++; | |
189 | if (uart_circ_empty(xmit)) | |
190 | break; | |
191 | } while (--count > 0); | |
192 | ||
193 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
194 | uart_write_wakeup(&up->port); | |
195 | ||
196 | ||
197 | if (uart_circ_empty(xmit)) | |
b129a8cc | 198 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
199 | } |
200 | ||
b129a8cc | 201 | static void serial_pxa_start_tx(struct uart_port *port) |
1da177e4 LT |
202 | { |
203 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
204 | ||
205 | if (!(up->ier & UART_IER_THRI)) { | |
206 | up->ier |= UART_IER_THRI; | |
207 | serial_out(up, UART_IER, up->ier); | |
208 | } | |
209 | } | |
210 | ||
211 | static inline void check_modem_status(struct uart_pxa_port *up) | |
212 | { | |
213 | int status; | |
214 | ||
215 | status = serial_in(up, UART_MSR); | |
216 | ||
217 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
218 | return; | |
219 | ||
220 | if (status & UART_MSR_TERI) | |
221 | up->port.icount.rng++; | |
222 | if (status & UART_MSR_DDSR) | |
223 | up->port.icount.dsr++; | |
224 | if (status & UART_MSR_DDCD) | |
225 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
226 | if (status & UART_MSR_DCTS) | |
227 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
228 | ||
229 | wake_up_interruptible(&up->port.info->delta_msr_wait); | |
230 | } | |
231 | ||
232 | /* | |
233 | * This handles the interrupt from one port. | |
234 | */ | |
7d12e780 | 235 | static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id) |
1da177e4 | 236 | { |
c7bec5ab | 237 | struct uart_pxa_port *up = dev_id; |
1da177e4 LT |
238 | unsigned int iir, lsr; |
239 | ||
240 | iir = serial_in(up, UART_IIR); | |
241 | if (iir & UART_IIR_NO_INT) | |
242 | return IRQ_NONE; | |
243 | lsr = serial_in(up, UART_LSR); | |
244 | if (lsr & UART_LSR_DR) | |
7d12e780 | 245 | receive_chars(up, &lsr); |
1da177e4 LT |
246 | check_modem_status(up); |
247 | if (lsr & UART_LSR_THRE) | |
248 | transmit_chars(up); | |
249 | return IRQ_HANDLED; | |
250 | } | |
251 | ||
252 | static unsigned int serial_pxa_tx_empty(struct uart_port *port) | |
253 | { | |
254 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
255 | unsigned long flags; | |
256 | unsigned int ret; | |
257 | ||
258 | spin_lock_irqsave(&up->port.lock, flags); | |
259 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
260 | spin_unlock_irqrestore(&up->port.lock, flags); | |
261 | ||
262 | return ret; | |
263 | } | |
264 | ||
265 | static unsigned int serial_pxa_get_mctrl(struct uart_port *port) | |
266 | { | |
267 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
1da177e4 LT |
268 | unsigned char status; |
269 | unsigned int ret; | |
270 | ||
1da177e4 | 271 | status = serial_in(up, UART_MSR); |
1da177e4 LT |
272 | |
273 | ret = 0; | |
274 | if (status & UART_MSR_DCD) | |
275 | ret |= TIOCM_CAR; | |
276 | if (status & UART_MSR_RI) | |
277 | ret |= TIOCM_RNG; | |
278 | if (status & UART_MSR_DSR) | |
279 | ret |= TIOCM_DSR; | |
280 | if (status & UART_MSR_CTS) | |
281 | ret |= TIOCM_CTS; | |
282 | return ret; | |
283 | } | |
284 | ||
285 | static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
286 | { | |
287 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
288 | unsigned char mcr = 0; | |
289 | ||
290 | if (mctrl & TIOCM_RTS) | |
291 | mcr |= UART_MCR_RTS; | |
292 | if (mctrl & TIOCM_DTR) | |
293 | mcr |= UART_MCR_DTR; | |
294 | if (mctrl & TIOCM_OUT1) | |
295 | mcr |= UART_MCR_OUT1; | |
296 | if (mctrl & TIOCM_OUT2) | |
297 | mcr |= UART_MCR_OUT2; | |
298 | if (mctrl & TIOCM_LOOP) | |
299 | mcr |= UART_MCR_LOOP; | |
300 | ||
301 | mcr |= up->mcr; | |
302 | ||
303 | serial_out(up, UART_MCR, mcr); | |
304 | } | |
305 | ||
306 | static void serial_pxa_break_ctl(struct uart_port *port, int break_state) | |
307 | { | |
308 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
309 | unsigned long flags; | |
310 | ||
311 | spin_lock_irqsave(&up->port.lock, flags); | |
312 | if (break_state == -1) | |
313 | up->lcr |= UART_LCR_SBC; | |
314 | else | |
315 | up->lcr &= ~UART_LCR_SBC; | |
316 | serial_out(up, UART_LCR, up->lcr); | |
317 | spin_unlock_irqrestore(&up->port.lock, flags); | |
318 | } | |
319 | ||
320 | #if 0 | |
321 | static void serial_pxa_dma_init(struct pxa_uart *up) | |
322 | { | |
323 | up->rxdma = | |
324 | pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up); | |
325 | if (up->rxdma < 0) | |
326 | goto out; | |
327 | up->txdma = | |
328 | pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up); | |
329 | if (up->txdma < 0) | |
330 | goto err_txdma; | |
331 | up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL); | |
332 | if (!up->dmadesc) | |
333 | goto err_alloc; | |
334 | ||
335 | /* ... */ | |
336 | err_alloc: | |
337 | pxa_free_dma(up->txdma); | |
338 | err_rxdma: | |
339 | pxa_free_dma(up->rxdma); | |
340 | out: | |
341 | return; | |
342 | } | |
343 | #endif | |
344 | ||
345 | static int serial_pxa_startup(struct uart_port *port) | |
346 | { | |
347 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
348 | unsigned long flags; | |
349 | int retval; | |
350 | ||
d9e29649 MR |
351 | if (port->line == 3) /* HWUART */ |
352 | up->mcr |= UART_MCR_AFE; | |
353 | else | |
f02aa3f9 | 354 | up->mcr = 0; |
1da177e4 | 355 | |
b049bd9d RK |
356 | up->port.uartclk = clk_get_rate(up->clk); |
357 | ||
1da177e4 LT |
358 | /* |
359 | * Allocate the IRQ | |
360 | */ | |
361 | retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up); | |
362 | if (retval) | |
363 | return retval; | |
364 | ||
365 | /* | |
366 | * Clear the FIFO buffers and disable them. | |
367 | * (they will be reenabled in set_termios()) | |
368 | */ | |
369 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
370 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
371 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
372 | serial_out(up, UART_FCR, 0); | |
373 | ||
374 | /* | |
375 | * Clear the interrupt registers. | |
376 | */ | |
377 | (void) serial_in(up, UART_LSR); | |
378 | (void) serial_in(up, UART_RX); | |
379 | (void) serial_in(up, UART_IIR); | |
380 | (void) serial_in(up, UART_MSR); | |
381 | ||
382 | /* | |
383 | * Now, initialize the UART | |
384 | */ | |
385 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
386 | ||
387 | spin_lock_irqsave(&up->port.lock, flags); | |
388 | up->port.mctrl |= TIOCM_OUT2; | |
389 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
390 | spin_unlock_irqrestore(&up->port.lock, flags); | |
391 | ||
392 | /* | |
393 | * Finally, enable interrupts. Note: Modem status interrupts | |
80f7228b | 394 | * are set via set_termios(), which will be occurring imminently |
1da177e4 LT |
395 | * anyway, so we don't enable them here. |
396 | */ | |
397 | up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; | |
398 | serial_out(up, UART_IER, up->ier); | |
399 | ||
400 | /* | |
401 | * And clear the interrupt registers again for luck. | |
402 | */ | |
403 | (void) serial_in(up, UART_LSR); | |
404 | (void) serial_in(up, UART_RX); | |
405 | (void) serial_in(up, UART_IIR); | |
406 | (void) serial_in(up, UART_MSR); | |
407 | ||
408 | return 0; | |
409 | } | |
410 | ||
411 | static void serial_pxa_shutdown(struct uart_port *port) | |
412 | { | |
413 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
414 | unsigned long flags; | |
415 | ||
416 | free_irq(up->port.irq, up); | |
417 | ||
418 | /* | |
419 | * Disable interrupts from this port | |
420 | */ | |
421 | up->ier = 0; | |
422 | serial_out(up, UART_IER, 0); | |
423 | ||
424 | spin_lock_irqsave(&up->port.lock, flags); | |
425 | up->port.mctrl &= ~TIOCM_OUT2; | |
426 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
427 | spin_unlock_irqrestore(&up->port.lock, flags); | |
428 | ||
429 | /* | |
430 | * Disable break condition and FIFOs | |
431 | */ | |
432 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
433 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
434 | UART_FCR_CLEAR_RCVR | | |
435 | UART_FCR_CLEAR_XMIT); | |
436 | serial_out(up, UART_FCR, 0); | |
437 | } | |
438 | ||
439 | static void | |
606d099c AC |
440 | serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, |
441 | struct ktermios *old) | |
1da177e4 LT |
442 | { |
443 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
444 | unsigned char cval, fcr = 0; | |
445 | unsigned long flags; | |
446 | unsigned int baud, quot; | |
447 | ||
448 | switch (termios->c_cflag & CSIZE) { | |
449 | case CS5: | |
0a8b80c5 | 450 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
451 | break; |
452 | case CS6: | |
0a8b80c5 | 453 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
454 | break; |
455 | case CS7: | |
0a8b80c5 | 456 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
457 | break; |
458 | default: | |
459 | case CS8: | |
0a8b80c5 | 460 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
461 | break; |
462 | } | |
463 | ||
464 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 465 | cval |= UART_LCR_STOP; |
1da177e4 LT |
466 | if (termios->c_cflag & PARENB) |
467 | cval |= UART_LCR_PARITY; | |
468 | if (!(termios->c_cflag & PARODD)) | |
469 | cval |= UART_LCR_EPAR; | |
470 | ||
471 | /* | |
472 | * Ask the core to calculate the divisor for us. | |
473 | */ | |
474 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
475 | quot = uart_get_divisor(port, baud); | |
476 | ||
477 | if ((up->port.uartclk / quot) < (2400 * 16)) | |
478 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; | |
d9e29649 | 479 | else if ((up->port.uartclk / quot) < (230400 * 16)) |
1da177e4 | 480 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; |
d9e29649 MR |
481 | else |
482 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; | |
1da177e4 LT |
483 | |
484 | /* | |
485 | * Ok, we're now changing the port state. Do it with | |
486 | * interrupts disabled. | |
487 | */ | |
488 | spin_lock_irqsave(&up->port.lock, flags); | |
489 | ||
490 | /* | |
491 | * Ensure the port will be enabled. | |
492 | * This is required especially for serial console. | |
493 | */ | |
494 | up->ier |= IER_UUE; | |
495 | ||
496 | /* | |
497 | * Update the per-port timeout. | |
498 | */ | |
e6158b4a | 499 | uart_update_timeout(port, termios->c_cflag, baud); |
1da177e4 LT |
500 | |
501 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
502 | if (termios->c_iflag & INPCK) | |
503 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
504 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
505 | up->port.read_status_mask |= UART_LSR_BI; | |
506 | ||
507 | /* | |
508 | * Characters to ignore | |
509 | */ | |
510 | up->port.ignore_status_mask = 0; | |
511 | if (termios->c_iflag & IGNPAR) | |
512 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
513 | if (termios->c_iflag & IGNBRK) { | |
514 | up->port.ignore_status_mask |= UART_LSR_BI; | |
515 | /* | |
516 | * If we're ignoring parity and break indicators, | |
517 | * ignore overruns too (for real raw support). | |
518 | */ | |
519 | if (termios->c_iflag & IGNPAR) | |
520 | up->port.ignore_status_mask |= UART_LSR_OE; | |
521 | } | |
522 | ||
523 | /* | |
524 | * ignore all characters if CREAD is not set | |
525 | */ | |
526 | if ((termios->c_cflag & CREAD) == 0) | |
527 | up->port.ignore_status_mask |= UART_LSR_DR; | |
528 | ||
529 | /* | |
530 | * CTS flow control flag and modem status interrupts | |
531 | */ | |
532 | up->ier &= ~UART_IER_MSI; | |
533 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
534 | up->ier |= UART_IER_MSI; | |
535 | ||
536 | serial_out(up, UART_IER, up->ier); | |
537 | ||
2276f03b RJ |
538 | if (termios->c_cflag & CRTSCTS) |
539 | up->mcr |= UART_MCR_AFE; | |
540 | else | |
541 | up->mcr &= ~UART_MCR_AFE; | |
542 | ||
1da177e4 LT |
543 | serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */ |
544 | serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ | |
545 | serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ | |
546 | serial_out(up, UART_LCR, cval); /* reset DLAB */ | |
547 | up->lcr = cval; /* Save LCR */ | |
548 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
549 | serial_out(up, UART_FCR, fcr); | |
550 | spin_unlock_irqrestore(&up->port.lock, flags); | |
551 | } | |
552 | ||
553 | static void | |
554 | serial_pxa_pm(struct uart_port *port, unsigned int state, | |
555 | unsigned int oldstate) | |
556 | { | |
557 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
b049bd9d | 558 | |
1da177e4 | 559 | if (!state) |
b049bd9d RK |
560 | clk_enable(up->clk); |
561 | else | |
562 | clk_disable(up->clk); | |
1da177e4 LT |
563 | } |
564 | ||
565 | static void serial_pxa_release_port(struct uart_port *port) | |
566 | { | |
567 | } | |
568 | ||
569 | static int serial_pxa_request_port(struct uart_port *port) | |
570 | { | |
571 | return 0; | |
572 | } | |
573 | ||
574 | static void serial_pxa_config_port(struct uart_port *port, int flags) | |
575 | { | |
576 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
577 | up->port.type = PORT_PXA; | |
578 | } | |
579 | ||
580 | static int | |
581 | serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) | |
582 | { | |
583 | /* we don't want the core code to modify any port params */ | |
584 | return -EINVAL; | |
585 | } | |
586 | ||
587 | static const char * | |
588 | serial_pxa_type(struct uart_port *port) | |
589 | { | |
590 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
591 | return up->name; | |
592 | } | |
593 | ||
e259a3ae | 594 | static struct uart_pxa_port *serial_pxa_ports[4]; |
2d93486c | 595 | static struct uart_driver serial_pxa_reg; |
1da177e4 | 596 | |
fa7f1518 PZ |
597 | #ifdef CONFIG_SERIAL_PXA_CONSOLE |
598 | ||
1da177e4 LT |
599 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
600 | ||
601 | /* | |
602 | * Wait for transmitter & holding register to empty | |
603 | */ | |
604 | static inline void wait_for_xmitr(struct uart_pxa_port *up) | |
605 | { | |
606 | unsigned int status, tmout = 10000; | |
607 | ||
608 | /* Wait up to 10ms for the character(s) to be sent. */ | |
609 | do { | |
610 | status = serial_in(up, UART_LSR); | |
611 | ||
612 | if (status & UART_LSR_BI) | |
613 | up->lsr_break_flag = UART_LSR_BI; | |
614 | ||
615 | if (--tmout == 0) | |
616 | break; | |
617 | udelay(1); | |
618 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
619 | ||
620 | /* Wait up to 1s for flow control if necessary */ | |
621 | if (up->port.flags & UPF_CONS_FLOW) { | |
622 | tmout = 1000000; | |
623 | while (--tmout && | |
624 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | |
625 | udelay(1); | |
626 | } | |
627 | } | |
628 | ||
d358788f RK |
629 | static void serial_pxa_console_putchar(struct uart_port *port, int ch) |
630 | { | |
631 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
632 | ||
633 | wait_for_xmitr(up); | |
634 | serial_out(up, UART_TX, ch); | |
635 | } | |
636 | ||
1da177e4 LT |
637 | /* |
638 | * Print a string to the serial port trying not to disturb | |
639 | * any possible real use of the port... | |
640 | * | |
641 | * The console_lock must be held when we get here. | |
642 | */ | |
643 | static void | |
644 | serial_pxa_console_write(struct console *co, const char *s, unsigned int count) | |
645 | { | |
e259a3ae | 646 | struct uart_pxa_port *up = serial_pxa_ports[co->index]; |
1da177e4 | 647 | unsigned int ier; |
1da177e4 | 648 | |
b049bd9d RK |
649 | clk_enable(up->clk); |
650 | ||
1da177e4 | 651 | /* |
f02aa3f9 | 652 | * First save the IER then disable the interrupts |
1da177e4 LT |
653 | */ |
654 | ier = serial_in(up, UART_IER); | |
655 | serial_out(up, UART_IER, UART_IER_UUE); | |
656 | ||
d358788f | 657 | uart_console_write(&up->port, s, count, serial_pxa_console_putchar); |
1da177e4 LT |
658 | |
659 | /* | |
660 | * Finally, wait for transmitter to become empty | |
661 | * and restore the IER | |
662 | */ | |
663 | wait_for_xmitr(up); | |
664 | serial_out(up, UART_IER, ier); | |
b049bd9d RK |
665 | |
666 | clk_disable(up->clk); | |
1da177e4 LT |
667 | } |
668 | ||
669 | static int __init | |
670 | serial_pxa_console_setup(struct console *co, char *options) | |
671 | { | |
672 | struct uart_pxa_port *up; | |
673 | int baud = 9600; | |
674 | int bits = 8; | |
675 | int parity = 'n'; | |
676 | int flow = 'n'; | |
677 | ||
678 | if (co->index == -1 || co->index >= serial_pxa_reg.nr) | |
679 | co->index = 0; | |
e259a3ae RK |
680 | up = serial_pxa_ports[co->index]; |
681 | if (!up) | |
682 | return -ENODEV; | |
1da177e4 LT |
683 | |
684 | if (options) | |
685 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
686 | ||
687 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
688 | } | |
689 | ||
690 | static struct console serial_pxa_console = { | |
691 | .name = "ttyS", | |
692 | .write = serial_pxa_console_write, | |
693 | .device = uart_console_device, | |
694 | .setup = serial_pxa_console_setup, | |
695 | .flags = CON_PRINTBUFFER, | |
696 | .index = -1, | |
697 | .data = &serial_pxa_reg, | |
698 | }; | |
699 | ||
1da177e4 LT |
700 | #define PXA_CONSOLE &serial_pxa_console |
701 | #else | |
702 | #define PXA_CONSOLE NULL | |
703 | #endif | |
704 | ||
705 | struct uart_ops serial_pxa_pops = { | |
706 | .tx_empty = serial_pxa_tx_empty, | |
707 | .set_mctrl = serial_pxa_set_mctrl, | |
708 | .get_mctrl = serial_pxa_get_mctrl, | |
709 | .stop_tx = serial_pxa_stop_tx, | |
710 | .start_tx = serial_pxa_start_tx, | |
711 | .stop_rx = serial_pxa_stop_rx, | |
712 | .enable_ms = serial_pxa_enable_ms, | |
713 | .break_ctl = serial_pxa_break_ctl, | |
714 | .startup = serial_pxa_startup, | |
715 | .shutdown = serial_pxa_shutdown, | |
716 | .set_termios = serial_pxa_set_termios, | |
717 | .pm = serial_pxa_pm, | |
718 | .type = serial_pxa_type, | |
719 | .release_port = serial_pxa_release_port, | |
720 | .request_port = serial_pxa_request_port, | |
721 | .config_port = serial_pxa_config_port, | |
722 | .verify_port = serial_pxa_verify_port, | |
723 | }; | |
724 | ||
1da177e4 LT |
725 | static struct uart_driver serial_pxa_reg = { |
726 | .owner = THIS_MODULE, | |
727 | .driver_name = "PXA serial", | |
1da177e4 LT |
728 | .dev_name = "ttyS", |
729 | .major = TTY_MAJOR, | |
730 | .minor = 64, | |
e259a3ae | 731 | .nr = 4, |
1da177e4 LT |
732 | .cons = PXA_CONSOLE, |
733 | }; | |
734 | ||
3ae5eaec | 735 | static int serial_pxa_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 736 | { |
3ae5eaec | 737 | struct uart_pxa_port *sport = platform_get_drvdata(dev); |
1da177e4 | 738 | |
9480e307 | 739 | if (sport) |
1da177e4 LT |
740 | uart_suspend_port(&serial_pxa_reg, &sport->port); |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
3ae5eaec | 745 | static int serial_pxa_resume(struct platform_device *dev) |
1da177e4 | 746 | { |
3ae5eaec | 747 | struct uart_pxa_port *sport = platform_get_drvdata(dev); |
1da177e4 | 748 | |
9480e307 | 749 | if (sport) |
1da177e4 LT |
750 | uart_resume_port(&serial_pxa_reg, &sport->port); |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
3ae5eaec | 755 | static int serial_pxa_probe(struct platform_device *dev) |
1da177e4 | 756 | { |
e259a3ae RK |
757 | struct uart_pxa_port *sport; |
758 | struct resource *mmres, *irqres; | |
759 | int ret; | |
760 | ||
761 | mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
762 | irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0); | |
763 | if (!mmres || !irqres) | |
764 | return -ENODEV; | |
765 | ||
766 | sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL); | |
767 | if (!sport) | |
768 | return -ENOMEM; | |
769 | ||
e0d8b13a | 770 | sport->clk = clk_get(&dev->dev, NULL); |
b049bd9d RK |
771 | if (IS_ERR(sport->clk)) { |
772 | ret = PTR_ERR(sport->clk); | |
773 | goto err_free; | |
774 | } | |
775 | ||
e259a3ae RK |
776 | sport->port.type = PORT_PXA; |
777 | sport->port.iotype = UPIO_MEM; | |
778 | sport->port.mapbase = mmres->start; | |
779 | sport->port.irq = irqres->start; | |
780 | sport->port.fifosize = 64; | |
781 | sport->port.ops = &serial_pxa_pops; | |
782 | sport->port.line = dev->id; | |
783 | sport->port.dev = &dev->dev; | |
784 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | |
b049bd9d | 785 | sport->port.uartclk = clk_get_rate(sport->clk); |
e259a3ae RK |
786 | |
787 | /* | |
788 | * Is it worth keeping this? | |
789 | */ | |
790 | if (mmres->start == __PREG(FFUART)) | |
791 | sport->name = "FFUART"; | |
792 | else if (mmres->start == __PREG(BTUART)) | |
793 | sport->name = "BTUART"; | |
794 | else if (mmres->start == __PREG(STUART)) | |
795 | sport->name = "STUART"; | |
796 | else if (mmres->start == __PREG(HWUART)) | |
797 | sport->name = "HWUART"; | |
798 | else | |
799 | sport->name = "???"; | |
800 | ||
801 | sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1); | |
802 | if (!sport->port.membase) { | |
803 | ret = -ENOMEM; | |
b049bd9d | 804 | goto err_clk; |
e259a3ae RK |
805 | } |
806 | ||
807 | serial_pxa_ports[dev->id] = sport; | |
808 | ||
809 | uart_add_one_port(&serial_pxa_reg, &sport->port); | |
810 | platform_set_drvdata(dev, sport); | |
811 | ||
1da177e4 | 812 | return 0; |
e259a3ae | 813 | |
b049bd9d RK |
814 | err_clk: |
815 | clk_put(sport->clk); | |
e259a3ae RK |
816 | err_free: |
817 | kfree(sport); | |
818 | return ret; | |
1da177e4 LT |
819 | } |
820 | ||
3ae5eaec | 821 | static int serial_pxa_remove(struct platform_device *dev) |
1da177e4 | 822 | { |
3ae5eaec | 823 | struct uart_pxa_port *sport = platform_get_drvdata(dev); |
1da177e4 | 824 | |
3ae5eaec | 825 | platform_set_drvdata(dev, NULL); |
1da177e4 | 826 | |
e259a3ae | 827 | uart_remove_one_port(&serial_pxa_reg, &sport->port); |
b049bd9d | 828 | clk_put(sport->clk); |
e259a3ae | 829 | kfree(sport); |
1da177e4 LT |
830 | |
831 | return 0; | |
832 | } | |
833 | ||
3ae5eaec | 834 | static struct platform_driver serial_pxa_driver = { |
1da177e4 LT |
835 | .probe = serial_pxa_probe, |
836 | .remove = serial_pxa_remove, | |
837 | ||
838 | .suspend = serial_pxa_suspend, | |
839 | .resume = serial_pxa_resume, | |
3ae5eaec RK |
840 | .driver = { |
841 | .name = "pxa2xx-uart", | |
e169c139 | 842 | .owner = THIS_MODULE, |
3ae5eaec | 843 | }, |
1da177e4 LT |
844 | }; |
845 | ||
846 | int __init serial_pxa_init(void) | |
847 | { | |
848 | int ret; | |
849 | ||
850 | ret = uart_register_driver(&serial_pxa_reg); | |
851 | if (ret != 0) | |
852 | return ret; | |
853 | ||
3ae5eaec | 854 | ret = platform_driver_register(&serial_pxa_driver); |
1da177e4 LT |
855 | if (ret != 0) |
856 | uart_unregister_driver(&serial_pxa_reg); | |
857 | ||
858 | return ret; | |
859 | } | |
860 | ||
861 | void __exit serial_pxa_exit(void) | |
862 | { | |
3ae5eaec | 863 | platform_driver_unregister(&serial_pxa_driver); |
1da177e4 LT |
864 | uart_unregister_driver(&serial_pxa_reg); |
865 | } | |
866 | ||
867 | module_init(serial_pxa_init); | |
868 | module_exit(serial_pxa_exit); | |
869 | ||
870 | MODULE_LICENSE("GPL"); | |
e169c139 | 871 | MODULE_ALIAS("platform:pxa2xx-uart"); |