Commit | Line | Data |
---|---|---|
194de561 | 1 | /* |
1ba7a3ee | 2 | * Blackfin On-Chip Serial Driver |
194de561 | 3 | * |
d273e201 | 4 | * Copyright 2006-2008 Analog Devices Inc. |
194de561 | 5 | * |
1ba7a3ee | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
194de561 | 7 | * |
1ba7a3ee | 8 | * Licensed under the GPL-2 or later. |
194de561 BW |
9 | */ |
10 | ||
11 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/console.h> | |
19 | #include <linux/sysrq.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/tty_flip.h> | |
23 | #include <linux/serial_core.h> | |
24 | ||
52e15f0e SZ |
25 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
26 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
474f1a66 SZ |
27 | #include <linux/kgdb.h> |
28 | #include <asm/irq_regs.h> | |
29 | #endif | |
30 | ||
194de561 | 31 | #include <asm/gpio.h> |
639f6571 | 32 | #include <mach/bfin_serial_5xx.h> |
194de561 BW |
33 | |
34 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/irq.h> | |
38 | #include <asm/cacheflush.h> | |
39 | #endif | |
40 | ||
41 | /* UART name and device definitions */ | |
42 | #define BFIN_SERIAL_NAME "ttyBF" | |
43 | #define BFIN_SERIAL_MAJOR 204 | |
44 | #define BFIN_SERIAL_MINOR 64 | |
45 | ||
c9607ecc MF |
46 | static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; |
47 | static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource); | |
48 | ||
52e15f0e SZ |
49 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
50 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
51 | ||
52 | # ifndef CONFIG_SERIAL_BFIN_PIO | |
53 | # error KGDB only support UART in PIO mode. | |
54 | # endif | |
55 | ||
56 | static int kgdboc_port_line; | |
57 | static int kgdboc_break_enabled; | |
58 | #endif | |
194de561 BW |
59 | /* |
60 | * Setup for console. Argument comes from the menuconfig | |
61 | */ | |
62 | #define DMA_RX_XCOUNT 512 | |
63 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
64 | ||
0aef4564 | 65 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
f30ac0ce | 66 | #define CTS_CHECK_JIFFIES (HZ / 50) |
194de561 BW |
67 | |
68 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
69 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
70 | #else | |
194de561 | 71 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); |
194de561 BW |
72 | #endif |
73 | ||
74 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart); | |
75 | ||
80d5c474 GY |
76 | static void bfin_serial_reset_irda(struct uart_port *port); |
77 | ||
194de561 BW |
78 | /* |
79 | * interrupts are disabled on entry | |
80 | */ | |
81 | static void bfin_serial_stop_tx(struct uart_port *port) | |
82 | { | |
83 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
68a784cb | 84 | #ifdef CONFIG_SERIAL_BFIN_DMA |
0711d857 | 85 | struct circ_buf *xmit = &uart->port.info->xmit; |
68a784cb | 86 | #endif |
194de561 | 87 | |
f4d640c9 | 88 | while (!(UART_GET_LSR(uart) & TEMT)) |
0711d857 | 89 | cpu_relax(); |
f4d640c9 | 90 | |
194de561 BW |
91 | #ifdef CONFIG_SERIAL_BFIN_DMA |
92 | disable_dma(uart->tx_dma_channel); | |
0711d857 SZ |
93 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
94 | uart->port.icount.tx += uart->tx_count; | |
95 | uart->tx_count = 0; | |
96 | uart->tx_done = 1; | |
f4d640c9 RH |
97 | #else |
98 | #ifdef CONFIG_BF54x | |
f4d640c9 RH |
99 | /* Clear TFI bit */ |
100 | UART_PUT_LSR(uart, TFI); | |
194de561 | 101 | #endif |
89bf6dc5 | 102 | UART_CLEAR_IER(uart, ETBEI); |
f4d640c9 | 103 | #endif |
194de561 BW |
104 | } |
105 | ||
106 | /* | |
107 | * port is locked and interrupts are disabled | |
108 | */ | |
109 | static void bfin_serial_start_tx(struct uart_port *port) | |
110 | { | |
111 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
80d5c474 GY |
112 | struct tty_struct *tty = uart->port.info->port.tty; |
113 | ||
114 | /* | |
115 | * To avoid losting RX interrupt, we reset IR function | |
116 | * before sending data. | |
117 | */ | |
118 | if (tty->termios->c_line == N_IRDA) | |
119 | bfin_serial_reset_irda(port); | |
194de561 BW |
120 | |
121 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0711d857 SZ |
122 | if (uart->tx_done) |
123 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 | 124 | #else |
f4d640c9 | 125 | UART_SET_IER(uart, ETBEI); |
a359cca7 | 126 | bfin_serial_tx_chars(uart); |
f4d640c9 | 127 | #endif |
194de561 BW |
128 | } |
129 | ||
130 | /* | |
131 | * Interrupts are enabled | |
132 | */ | |
133 | static void bfin_serial_stop_rx(struct uart_port *port) | |
134 | { | |
135 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
52e15f0e | 136 | |
f4d640c9 | 137 | UART_CLEAR_IER(uart, ERBFI); |
194de561 BW |
138 | } |
139 | ||
140 | /* | |
141 | * Set the modem control timer to fire immediately. | |
142 | */ | |
143 | static void bfin_serial_enable_ms(struct uart_port *port) | |
144 | { | |
145 | } | |
146 | ||
474f1a66 | 147 | |
50e2e15a | 148 | #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO) |
8851c71e MF |
149 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) |
150 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
151 | #else | |
152 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
153 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
154 | #endif | |
155 | ||
194de561 | 156 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
157 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
158 | { | |
52e15f0e | 159 | struct tty_struct *tty = NULL; |
194de561 | 160 | unsigned int status, ch, flg; |
8851c71e | 161 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
194de561 | 162 | |
759eb040 | 163 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
164 | UART_CLEAR_LSR(uart); |
165 | ||
166 | ch = UART_GET_CHAR(uart); | |
194de561 BW |
167 | uart->port.icount.rx++; |
168 | ||
52e15f0e SZ |
169 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
170 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
171 | if (kgdb_connected && kgdboc_port_line == uart->port.line) | |
172 | if (ch == 0x3) {/* Ctrl + C */ | |
173 | kgdb_breakpoint(); | |
474f1a66 | 174 | return; |
474f1a66 | 175 | } |
52e15f0e SZ |
176 | |
177 | if (!uart->port.info || !uart->port.info->tty) | |
178 | return; | |
474f1a66 | 179 | #endif |
52e15f0e | 180 | tty = uart->port.info->tty; |
bbf275f0 | 181 | |
50e2e15a | 182 | if (ANOMALY_05000363) { |
8851c71e MF |
183 | /* The BF533 (and BF561) family of processors have a nice anomaly |
184 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 185 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
186 | * character comes across. Due to the nature of the flood, it is |
187 | * not possible to reliably catch bytes that are sent too quickly | |
188 | * after this break. So application code talking to the Blackfin | |
189 | * which sends a break signal must allow at least 1.5 character | |
190 | * times after the end of the break for things to stabilize. This | |
191 | * timeout was picked as it must absolutely be larger than 1 | |
192 | * character time +/- some percent. So 1.5 sounds good. All other | |
193 | * Blackfin families operate properly. Woo. | |
bbf275f0 | 194 | */ |
8851c71e MF |
195 | if (anomaly_start.tv_sec) { |
196 | struct timeval curr; | |
197 | suseconds_t usecs; | |
198 | ||
199 | if ((~ch & (~ch + 1)) & 0xff) | |
200 | goto known_good_char; | |
201 | ||
202 | do_gettimeofday(&curr); | |
203 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
204 | goto known_good_char; | |
205 | ||
206 | usecs = 0; | |
207 | if (curr.tv_sec != anomaly_start.tv_sec) | |
208 | usecs += USEC_PER_SEC; | |
209 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
210 | ||
211 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
212 | goto known_good_char; | |
213 | ||
214 | if (ch) | |
215 | anomaly_start.tv_sec = 0; | |
216 | else | |
217 | anomaly_start = curr; | |
218 | ||
219 | return; | |
220 | ||
221 | known_good_char: | |
e482a237 | 222 | status &= ~BI; |
8851c71e | 223 | anomaly_start.tv_sec = 0; |
bbf275f0 | 224 | } |
194de561 | 225 | } |
194de561 BW |
226 | |
227 | if (status & BI) { | |
50e2e15a | 228 | if (ANOMALY_05000363) |
8851c71e MF |
229 | if (bfin_revid() < 5) |
230 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
231 | uart->port.icount.brk++; |
232 | if (uart_handle_break(&uart->port)) | |
233 | goto ignore_char; | |
9808901b | 234 | status &= ~(PE | FE); |
2ac5ee47 MF |
235 | } |
236 | if (status & PE) | |
194de561 | 237 | uart->port.icount.parity++; |
2ac5ee47 | 238 | if (status & OE) |
194de561 | 239 | uart->port.icount.overrun++; |
2ac5ee47 | 240 | if (status & FE) |
194de561 | 241 | uart->port.icount.frame++; |
2ac5ee47 MF |
242 | |
243 | status &= uart->port.read_status_mask; | |
244 | ||
245 | if (status & BI) | |
246 | flg = TTY_BREAK; | |
247 | else if (status & PE) | |
248 | flg = TTY_PARITY; | |
249 | else if (status & FE) | |
250 | flg = TTY_FRAME; | |
251 | else | |
194de561 BW |
252 | flg = TTY_NORMAL; |
253 | ||
254 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
255 | goto ignore_char; | |
194de561 | 256 | |
2ac5ee47 MF |
257 | uart_insert_char(&uart->port, status, OE, ch, flg); |
258 | ||
259 | ignore_char: | |
260 | tty_flip_buffer_push(tty); | |
194de561 BW |
261 | } |
262 | ||
263 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
264 | { | |
265 | struct circ_buf *xmit = &uart->port.info->xmit; | |
266 | ||
194de561 BW |
267 | /* |
268 | * Check the modem control lines before | |
269 | * transmitting anything. | |
270 | */ | |
271 | bfin_serial_mctrl_check(uart); | |
272 | ||
273 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { | |
5ffdeea2 SZ |
274 | #ifdef CONFIG_BF54x |
275 | /* Clear TFI bit */ | |
276 | UART_PUT_LSR(uart, TFI); | |
277 | #endif | |
278 | UART_CLEAR_IER(uart, ETBEI); | |
194de561 BW |
279 | return; |
280 | } | |
281 | ||
f30ac0ce SZ |
282 | if (uart->port.x_char) { |
283 | UART_PUT_CHAR(uart, uart->port.x_char); | |
284 | uart->port.icount.tx++; | |
285 | uart->port.x_char = 0; | |
286 | } | |
287 | ||
759eb040 SZ |
288 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
289 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
290 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
291 | uart->port.icount.tx++; | |
292 | SSYNC(); | |
293 | } | |
194de561 BW |
294 | |
295 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
296 | uart_write_wakeup(&uart->port); | |
194de561 BW |
297 | } |
298 | ||
5c4e472b AL |
299 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
300 | { | |
301 | struct bfin_serial_port *uart = dev_id; | |
302 | ||
f4d640c9 | 303 | spin_lock(&uart->port.lock); |
0bcfd70e | 304 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 305 | bfin_serial_rx_chars(uart); |
f4d640c9 | 306 | spin_unlock(&uart->port.lock); |
759eb040 | 307 | |
5c4e472b AL |
308 | return IRQ_HANDLED; |
309 | } | |
310 | ||
311 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
312 | { |
313 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 314 | |
f4d640c9 | 315 | spin_lock(&uart->port.lock); |
0bcfd70e | 316 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 317 | bfin_serial_tx_chars(uart); |
f4d640c9 | 318 | spin_unlock(&uart->port.lock); |
759eb040 | 319 | |
194de561 BW |
320 | return IRQ_HANDLED; |
321 | } | |
4cb4f22b | 322 | #endif |
194de561 | 323 | |
194de561 BW |
324 | #ifdef CONFIG_SERIAL_BFIN_DMA |
325 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
326 | { | |
327 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 | 328 | |
194de561 BW |
329 | uart->tx_done = 0; |
330 | ||
f30ac0ce SZ |
331 | /* |
332 | * Check the modem control lines before | |
333 | * transmitting anything. | |
334 | */ | |
335 | bfin_serial_mctrl_check(uart); | |
336 | ||
1b73351c | 337 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
0711d857 | 338 | uart->tx_count = 0; |
1b73351c SZ |
339 | uart->tx_done = 1; |
340 | return; | |
341 | } | |
342 | ||
194de561 BW |
343 | if (uart->port.x_char) { |
344 | UART_PUT_CHAR(uart, uart->port.x_char); | |
345 | uart->port.icount.tx++; | |
346 | uart->port.x_char = 0; | |
194de561 | 347 | } |
1b73351c | 348 | |
194de561 BW |
349 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
350 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
351 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
352 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
353 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
354 | set_dma_config(uart->tx_dma_channel, | |
355 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
356 | INTR_ON_BUF, | |
357 | DIMENSION_LINEAR, | |
2047e40d MH |
358 | DATA_SIZE_8, |
359 | DMA_SYNC_RESTART)); | |
194de561 BW |
360 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
361 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
362 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
363 | enable_dma(uart->tx_dma_channel); | |
99ee7b5f | 364 | |
f4d640c9 | 365 | UART_SET_IER(uart, ETBEI); |
194de561 BW |
366 | } |
367 | ||
2ac5ee47 | 368 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 | 369 | { |
a88487c7 | 370 | struct tty_struct *tty = uart->port.info->port.tty; |
194de561 BW |
371 | int i, flg, status; |
372 | ||
373 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
374 | UART_CLEAR_LSR(uart); |
375 | ||
56f5de8f SZ |
376 | uart->port.icount.rx += |
377 | CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, | |
378 | UART_XMIT_SIZE); | |
194de561 BW |
379 | |
380 | if (status & BI) { | |
381 | uart->port.icount.brk++; | |
382 | if (uart_handle_break(&uart->port)) | |
383 | goto dma_ignore_char; | |
9808901b | 384 | status &= ~(PE | FE); |
2ac5ee47 MF |
385 | } |
386 | if (status & PE) | |
194de561 | 387 | uart->port.icount.parity++; |
2ac5ee47 | 388 | if (status & OE) |
194de561 | 389 | uart->port.icount.overrun++; |
2ac5ee47 | 390 | if (status & FE) |
194de561 | 391 | uart->port.icount.frame++; |
2ac5ee47 MF |
392 | |
393 | status &= uart->port.read_status_mask; | |
394 | ||
395 | if (status & BI) | |
396 | flg = TTY_BREAK; | |
397 | else if (status & PE) | |
398 | flg = TTY_PARITY; | |
399 | else if (status & FE) | |
400 | flg = TTY_FRAME; | |
401 | else | |
194de561 BW |
402 | flg = TTY_NORMAL; |
403 | ||
56f5de8f SZ |
404 | for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) { |
405 | if (i >= UART_XMIT_SIZE) | |
406 | i = 0; | |
407 | if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) | |
408 | uart_insert_char(&uart->port, status, OE, | |
409 | uart->rx_dma_buf.buf[i], flg); | |
194de561 | 410 | } |
2ac5ee47 MF |
411 | |
412 | dma_ignore_char: | |
194de561 BW |
413 | tty_flip_buffer_push(tty); |
414 | } | |
415 | ||
416 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
417 | { | |
68a784cb SZ |
418 | int x_pos, pos, flags; |
419 | ||
420 | spin_lock_irqsave(&uart->port.lock, flags); | |
194de561 | 421 | |
56f5de8f SZ |
422 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); |
423 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); | |
424 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
425 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT) | |
426 | uart->rx_dma_nrows = 0; | |
427 | x_pos = DMA_RX_XCOUNT - x_pos; | |
194de561 BW |
428 | if (x_pos == DMA_RX_XCOUNT) |
429 | x_pos = 0; | |
430 | ||
431 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
56f5de8f SZ |
432 | if (pos != uart->rx_dma_buf.tail) { |
433 | uart->rx_dma_buf.head = pos; | |
194de561 | 434 | bfin_serial_dma_rx_chars(uart); |
56f5de8f | 435 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; |
194de561 | 436 | } |
0aef4564 | 437 | |
68a784cb SZ |
438 | spin_unlock_irqrestore(&uart->port.lock, flags); |
439 | ||
0a278423 | 440 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); |
194de561 BW |
441 | } |
442 | ||
443 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
444 | { | |
445 | struct bfin_serial_port *uart = dev_id; | |
446 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 BW |
447 | |
448 | spin_lock(&uart->port.lock); | |
449 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
194de561 | 450 | disable_dma(uart->tx_dma_channel); |
0711d857 | 451 | clear_dma_irqstat(uart->tx_dma_channel); |
f4d640c9 | 452 | UART_CLEAR_IER(uart, ETBEI); |
0711d857 SZ |
453 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
454 | uart->port.icount.tx += uart->tx_count; | |
1b73351c | 455 | |
56f5de8f SZ |
456 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
457 | uart_write_wakeup(&uart->port); | |
458 | ||
1b73351c | 459 | bfin_serial_dma_tx_chars(uart); |
194de561 BW |
460 | } |
461 | ||
462 | spin_unlock(&uart->port.lock); | |
463 | return IRQ_HANDLED; | |
464 | } | |
465 | ||
466 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
467 | { | |
468 | struct bfin_serial_port *uart = dev_id; | |
469 | unsigned short irqstat; | |
0711d857 | 470 | |
194de561 BW |
471 | spin_lock(&uart->port.lock); |
472 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); | |
473 | clear_dma_irqstat(uart->rx_dma_channel); | |
68a784cb | 474 | bfin_serial_dma_rx_chars(uart); |
194de561 | 475 | spin_unlock(&uart->port.lock); |
0aef4564 | 476 | |
194de561 BW |
477 | return IRQ_HANDLED; |
478 | } | |
479 | #endif | |
480 | ||
481 | /* | |
482 | * Return TIOCSER_TEMT when transmitter is not busy. | |
483 | */ | |
484 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
485 | { | |
486 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
487 | unsigned short lsr; | |
488 | ||
489 | lsr = UART_GET_LSR(uart); | |
490 | if (lsr & TEMT) | |
491 | return TIOCSER_TEMT; | |
492 | else | |
493 | return 0; | |
494 | } | |
495 | ||
496 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
497 | { | |
498 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
499 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
500 | if (uart->cts_pin < 0) | |
501 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
502 | ||
1feaa51d | 503 | if (UART_GET_CTS(uart)) |
194de561 BW |
504 | return TIOCM_DSR | TIOCM_CAR; |
505 | else | |
506 | #endif | |
507 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
508 | } | |
509 | ||
510 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
511 | { | |
512 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
513 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
514 | if (uart->rts_pin < 0) | |
515 | return; | |
516 | ||
517 | if (mctrl & TIOCM_RTS) | |
1feaa51d | 518 | UART_CLEAR_RTS(uart); |
194de561 | 519 | else |
1feaa51d | 520 | UART_SET_RTS(uart); |
194de561 BW |
521 | #endif |
522 | } | |
523 | ||
524 | /* | |
525 | * Handle any change of modem status signal since we were last called. | |
526 | */ | |
527 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart) | |
528 | { | |
529 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
530 | unsigned int status; | |
194de561 | 531 | struct uart_info *info = uart->port.info; |
a88487c7 | 532 | struct tty_struct *tty = info->port.tty; |
194de561 BW |
533 | |
534 | status = bfin_serial_get_mctrl(&uart->port); | |
4cb4f22b | 535 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); |
194de561 BW |
536 | if (!(status & TIOCM_CTS)) { |
537 | tty->hw_stopped = 1; | |
f30ac0ce SZ |
538 | uart->cts_timer.data = (unsigned long)(uart); |
539 | uart->cts_timer.function = (void *)bfin_serial_mctrl_check; | |
540 | uart->cts_timer.expires = jiffies + CTS_CHECK_JIFFIES; | |
541 | add_timer(&(uart->cts_timer)); | |
194de561 BW |
542 | } else { |
543 | tty->hw_stopped = 0; | |
544 | } | |
194de561 BW |
545 | #endif |
546 | } | |
547 | ||
548 | /* | |
549 | * Interrupts are always disabled. | |
550 | */ | |
551 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) | |
552 | { | |
cf686762 MF |
553 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
554 | u16 lcr = UART_GET_LCR(uart); | |
555 | if (break_state) | |
556 | lcr |= SB; | |
557 | else | |
558 | lcr &= ~SB; | |
559 | UART_PUT_LCR(uart, lcr); | |
560 | SSYNC(); | |
194de561 BW |
561 | } |
562 | ||
563 | static int bfin_serial_startup(struct uart_port *port) | |
564 | { | |
565 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
566 | ||
567 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
568 | dma_addr_t dma_handle; | |
569 | ||
570 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
571 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
572 | return -EBUSY; | |
573 | } | |
574 | ||
575 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
576 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
577 | free_dma(uart->rx_dma_channel); | |
578 | return -EBUSY; | |
579 | } | |
580 | ||
581 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
582 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
583 | ||
584 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
585 | uart->rx_dma_buf.head = 0; | |
586 | uart->rx_dma_buf.tail = 0; | |
587 | uart->rx_dma_nrows = 0; | |
588 | ||
589 | set_dma_config(uart->rx_dma_channel, | |
590 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
591 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
592 | DATA_SIZE_8, |
593 | DMA_SYNC_RESTART)); | |
194de561 BW |
594 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
595 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
596 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
597 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
598 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
599 | enable_dma(uart->rx_dma_channel); | |
600 | ||
601 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
602 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
603 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
604 | add_timer(&(uart->rx_dma_timer)); | |
605 | #else | |
52e15f0e SZ |
606 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
607 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
608 | if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled) | |
609 | kgdboc_break_enabled = 0; | |
610 | else { | |
611 | # endif | |
a359cca7 SZ |
612 | if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
613 | "BFIN_UART_RX", uart)) { | |
194de561 BW |
614 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
615 | return -EBUSY; | |
616 | } | |
617 | ||
618 | if (request_irq | |
5c4e472b | 619 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
620 | "BFIN_UART_TX", uart)) { |
621 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
622 | free_irq(uart->port.irq, uart); | |
623 | return -EBUSY; | |
624 | } | |
ab2375f2 SZ |
625 | |
626 | # ifdef CONFIG_BF54x | |
627 | { | |
628 | unsigned uart_dma_ch_rx, uart_dma_ch_tx; | |
629 | ||
630 | switch (uart->port.irq) { | |
631 | case IRQ_UART3_RX: | |
632 | uart_dma_ch_rx = CH_UART3_RX; | |
633 | uart_dma_ch_tx = CH_UART3_TX; | |
634 | break; | |
635 | case IRQ_UART2_RX: | |
636 | uart_dma_ch_rx = CH_UART2_RX; | |
637 | uart_dma_ch_tx = CH_UART2_TX; | |
638 | break; | |
639 | default: | |
640 | uart_dma_ch_rx = uart_dma_ch_tx = 0; | |
641 | break; | |
642 | }; | |
643 | ||
644 | if (uart_dma_ch_rx && | |
645 | request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) { | |
646 | printk(KERN_NOTICE"Fail to attach UART interrupt\n"); | |
647 | free_irq(uart->port.irq, uart); | |
648 | free_irq(uart->port.irq + 1, uart); | |
649 | return -EBUSY; | |
650 | } | |
651 | if (uart_dma_ch_tx && | |
652 | request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) { | |
653 | printk(KERN_NOTICE "Fail to attach UART interrupt\n"); | |
654 | free_dma(uart_dma_ch_rx); | |
655 | free_irq(uart->port.irq, uart); | |
656 | free_irq(uart->port.irq + 1, uart); | |
657 | return -EBUSY; | |
658 | } | |
659 | } | |
660 | # endif | |
52e15f0e SZ |
661 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
662 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
663 | } | |
664 | # endif | |
194de561 | 665 | #endif |
f4d640c9 | 666 | UART_SET_IER(uart, ERBFI); |
194de561 BW |
667 | return 0; |
668 | } | |
669 | ||
670 | static void bfin_serial_shutdown(struct uart_port *port) | |
671 | { | |
672 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
673 | ||
674 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
675 | disable_dma(uart->tx_dma_channel); | |
676 | free_dma(uart->tx_dma_channel); | |
677 | disable_dma(uart->rx_dma_channel); | |
678 | free_dma(uart->rx_dma_channel); | |
679 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 680 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 681 | #else |
ab2375f2 SZ |
682 | #ifdef CONFIG_BF54x |
683 | switch (uart->port.irq) { | |
684 | case IRQ_UART3_RX: | |
685 | free_dma(CH_UART3_RX); | |
686 | free_dma(CH_UART3_TX); | |
687 | break; | |
688 | case IRQ_UART2_RX: | |
689 | free_dma(CH_UART2_RX); | |
690 | free_dma(CH_UART2_TX); | |
691 | break; | |
692 | default: | |
693 | break; | |
694 | }; | |
474f1a66 | 695 | #endif |
194de561 BW |
696 | free_irq(uart->port.irq, uart); |
697 | free_irq(uart->port.irq+1, uart); | |
698 | #endif | |
699 | } | |
700 | ||
701 | static void | |
702 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
703 | struct ktermios *old) | |
704 | { | |
705 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
706 | unsigned long flags; | |
707 | unsigned int baud, quot; | |
0c44a86d | 708 | unsigned short val, ier, lcr = 0; |
194de561 BW |
709 | |
710 | switch (termios->c_cflag & CSIZE) { | |
711 | case CS8: | |
712 | lcr = WLS(8); | |
713 | break; | |
714 | case CS7: | |
715 | lcr = WLS(7); | |
716 | break; | |
717 | case CS6: | |
718 | lcr = WLS(6); | |
719 | break; | |
720 | case CS5: | |
721 | lcr = WLS(5); | |
722 | break; | |
723 | default: | |
724 | printk(KERN_ERR "%s: word lengh not supported\n", | |
71cc2c21 | 725 | __func__); |
194de561 BW |
726 | } |
727 | ||
728 | if (termios->c_cflag & CSTOPB) | |
729 | lcr |= STB; | |
19aa6382 | 730 | if (termios->c_cflag & PARENB) |
194de561 | 731 | lcr |= PEN; |
19aa6382 MF |
732 | if (!(termios->c_cflag & PARODD)) |
733 | lcr |= EPS; | |
734 | if (termios->c_cflag & CMSPAR) | |
735 | lcr |= STP; | |
194de561 | 736 | |
2ac5ee47 MF |
737 | port->read_status_mask = OE; |
738 | if (termios->c_iflag & INPCK) | |
739 | port->read_status_mask |= (FE | PE); | |
740 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
741 | port->read_status_mask |= BI; | |
194de561 | 742 | |
2ac5ee47 MF |
743 | /* |
744 | * Characters to ignore | |
745 | */ | |
746 | port->ignore_status_mask = 0; | |
747 | if (termios->c_iflag & IGNPAR) | |
748 | port->ignore_status_mask |= FE | PE; | |
749 | if (termios->c_iflag & IGNBRK) { | |
750 | port->ignore_status_mask |= BI; | |
751 | /* | |
752 | * If we're ignoring parity and break indicators, | |
753 | * ignore overruns too (for real raw support). | |
754 | */ | |
755 | if (termios->c_iflag & IGNPAR) | |
756 | port->ignore_status_mask |= OE; | |
757 | } | |
194de561 BW |
758 | |
759 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
760 | quot = uart_get_divisor(port, baud); | |
761 | spin_lock_irqsave(&uart->port.lock, flags); | |
762 | ||
8851c71e MF |
763 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
764 | ||
194de561 BW |
765 | /* Disable UART */ |
766 | ier = UART_GET_IER(uart); | |
1feaa51d | 767 | UART_DISABLE_INTS(uart); |
194de561 BW |
768 | |
769 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 770 | UART_SET_DLAB(uart); |
194de561 BW |
771 | |
772 | UART_PUT_DLL(uart, quot & 0xFF); | |
194de561 BW |
773 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); |
774 | SSYNC(); | |
775 | ||
776 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 777 | UART_CLEAR_DLAB(uart); |
194de561 BW |
778 | |
779 | UART_PUT_LCR(uart, lcr); | |
780 | ||
781 | /* Enable UART */ | |
1feaa51d | 782 | UART_ENABLE_INTS(uart, ier); |
194de561 BW |
783 | |
784 | val = UART_GET_GCTL(uart); | |
785 | val |= UCEN; | |
786 | UART_PUT_GCTL(uart, val); | |
787 | ||
b3ef5aba GY |
788 | /* Port speed changed, update the per-port timeout. */ |
789 | uart_update_timeout(port, termios->c_cflag, baud); | |
790 | ||
194de561 BW |
791 | spin_unlock_irqrestore(&uart->port.lock, flags); |
792 | } | |
793 | ||
794 | static const char *bfin_serial_type(struct uart_port *port) | |
795 | { | |
796 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
797 | ||
798 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
799 | } | |
800 | ||
801 | /* | |
802 | * Release the memory region(s) being used by 'port'. | |
803 | */ | |
804 | static void bfin_serial_release_port(struct uart_port *port) | |
805 | { | |
806 | } | |
807 | ||
808 | /* | |
809 | * Request the memory region(s) being used by 'port'. | |
810 | */ | |
811 | static int bfin_serial_request_port(struct uart_port *port) | |
812 | { | |
813 | return 0; | |
814 | } | |
815 | ||
816 | /* | |
817 | * Configure/autoconfigure the port. | |
818 | */ | |
819 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
820 | { | |
821 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
822 | ||
823 | if (flags & UART_CONFIG_TYPE && | |
824 | bfin_serial_request_port(&uart->port) == 0) | |
825 | uart->port.type = PORT_BFIN; | |
826 | } | |
827 | ||
828 | /* | |
829 | * Verify the new serial_struct (for TIOCSSERIAL). | |
830 | * The only change we allow are to the flags and type, and | |
831 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
832 | */ | |
833 | static int | |
834 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
835 | { | |
836 | return 0; | |
837 | } | |
838 | ||
7d01b475 GY |
839 | /* |
840 | * Enable the IrDA function if tty->ldisc.num is N_IRDA. | |
841 | * In other cases, disable IrDA function. | |
842 | */ | |
3b8458a9 | 843 | static void bfin_serial_set_ldisc(struct uart_port *port) |
7d01b475 | 844 | { |
3b8458a9 | 845 | int line = port->line; |
7d01b475 GY |
846 | unsigned short val; |
847 | ||
a88487c7 | 848 | if (line >= port->info->port.tty->driver->num) |
7d01b475 GY |
849 | return; |
850 | ||
b1cbefe5 | 851 | switch (port->info->port.tty->termios->c_line) { |
7d01b475 GY |
852 | case N_IRDA: |
853 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
854 | val |= (IREN | RPOLC); | |
855 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
856 | break; | |
857 | default: | |
858 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
859 | val &= ~(IREN | RPOLC); | |
860 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
861 | } | |
862 | } | |
863 | ||
52e15f0e SZ |
864 | #ifdef CONFIG_CONSOLE_POLL |
865 | static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr) | |
866 | { | |
867 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
868 | ||
869 | while (!(UART_GET_LSR(uart) & THRE)) | |
870 | cpu_relax(); | |
871 | ||
872 | UART_CLEAR_DLAB(uart); | |
873 | UART_PUT_CHAR(uart, (unsigned char)chr); | |
874 | } | |
875 | ||
876 | static int bfin_serial_poll_get_char(struct uart_port *port) | |
877 | { | |
878 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
879 | unsigned char chr; | |
880 | ||
881 | while (!(UART_GET_LSR(uart) & DR)) | |
882 | cpu_relax(); | |
883 | ||
884 | UART_CLEAR_DLAB(uart); | |
885 | chr = UART_GET_CHAR(uart); | |
886 | ||
887 | return chr; | |
888 | } | |
889 | #endif | |
890 | ||
891 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ | |
892 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
893 | static void bfin_kgdboc_port_shutdown(struct uart_port *port) | |
894 | { | |
895 | if (kgdboc_break_enabled) { | |
896 | kgdboc_break_enabled = 0; | |
897 | bfin_serial_shutdown(port); | |
898 | } | |
899 | } | |
900 | ||
901 | static int bfin_kgdboc_port_startup(struct uart_port *port) | |
902 | { | |
903 | kgdboc_port_line = port->line; | |
904 | kgdboc_break_enabled = !bfin_serial_startup(port); | |
905 | return 0; | |
906 | } | |
907 | #endif | |
908 | ||
80d5c474 GY |
909 | static void bfin_serial_reset_irda(struct uart_port *port) |
910 | { | |
911 | int line = port->line; | |
912 | unsigned short val; | |
913 | ||
914 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
915 | val &= ~(IREN | RPOLC); | |
916 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
917 | SSYNC(); | |
918 | val |= (IREN | RPOLC); | |
919 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
920 | SSYNC(); | |
921 | } | |
922 | ||
194de561 BW |
923 | static struct uart_ops bfin_serial_pops = { |
924 | .tx_empty = bfin_serial_tx_empty, | |
925 | .set_mctrl = bfin_serial_set_mctrl, | |
926 | .get_mctrl = bfin_serial_get_mctrl, | |
927 | .stop_tx = bfin_serial_stop_tx, | |
928 | .start_tx = bfin_serial_start_tx, | |
929 | .stop_rx = bfin_serial_stop_rx, | |
930 | .enable_ms = bfin_serial_enable_ms, | |
931 | .break_ctl = bfin_serial_break_ctl, | |
932 | .startup = bfin_serial_startup, | |
933 | .shutdown = bfin_serial_shutdown, | |
934 | .set_termios = bfin_serial_set_termios, | |
3b8458a9 | 935 | .set_ldisc = bfin_serial_set_ldisc, |
194de561 BW |
936 | .type = bfin_serial_type, |
937 | .release_port = bfin_serial_release_port, | |
938 | .request_port = bfin_serial_request_port, | |
939 | .config_port = bfin_serial_config_port, | |
940 | .verify_port = bfin_serial_verify_port, | |
52e15f0e SZ |
941 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
942 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
943 | .kgdboc_port_startup = bfin_kgdboc_port_startup, | |
944 | .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown, | |
945 | #endif | |
946 | #ifdef CONFIG_CONSOLE_POLL | |
947 | .poll_put_char = bfin_serial_poll_put_char, | |
948 | .poll_get_char = bfin_serial_poll_get_char, | |
949 | #endif | |
194de561 BW |
950 | }; |
951 | ||
952 | static void __init bfin_serial_init_ports(void) | |
953 | { | |
954 | static int first = 1; | |
955 | int i; | |
956 | ||
957 | if (!first) | |
958 | return; | |
959 | first = 0; | |
960 | ||
c9607ecc | 961 | for (i = 0; i < nr_active_ports; i++) { |
194de561 | 962 | bfin_serial_ports[i].port.uartclk = get_sclk(); |
b3ef5aba | 963 | bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE; |
194de561 BW |
964 | bfin_serial_ports[i].port.ops = &bfin_serial_pops; |
965 | bfin_serial_ports[i].port.line = i; | |
966 | bfin_serial_ports[i].port.iotype = UPIO_MEM; | |
967 | bfin_serial_ports[i].port.membase = | |
968 | (void __iomem *)bfin_serial_resource[i].uart_base_addr; | |
969 | bfin_serial_ports[i].port.mapbase = | |
970 | bfin_serial_resource[i].uart_base_addr; | |
971 | bfin_serial_ports[i].port.irq = | |
972 | bfin_serial_resource[i].uart_irq; | |
973 | bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; | |
974 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
975 | bfin_serial_ports[i].tx_done = 1; | |
976 | bfin_serial_ports[i].tx_count = 0; | |
977 | bfin_serial_ports[i].tx_dma_channel = | |
978 | bfin_serial_resource[i].uart_tx_dma_channel; | |
979 | bfin_serial_ports[i].rx_dma_channel = | |
980 | bfin_serial_resource[i].uart_rx_dma_channel; | |
981 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | |
194de561 BW |
982 | #endif |
983 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
f30ac0ce | 984 | init_timer(&(bfin_serial_ports[i].cts_timer)); |
194de561 BW |
985 | bfin_serial_ports[i].cts_pin = |
986 | bfin_serial_resource[i].uart_cts_pin; | |
987 | bfin_serial_ports[i].rts_pin = | |
988 | bfin_serial_resource[i].uart_rts_pin; | |
989 | #endif | |
990 | bfin_serial_hw_init(&bfin_serial_ports[i]); | |
194de561 | 991 | } |
f4d640c9 | 992 | |
194de561 BW |
993 | } |
994 | ||
b6efa1ea | 995 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) |
194de561 BW |
996 | /* |
997 | * If the port was already initialised (eg, by a boot loader), | |
998 | * try to determine the current setup. | |
999 | */ | |
1000 | static void __init | |
1001 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
1002 | int *parity, int *bits) | |
1003 | { | |
1004 | unsigned short status; | |
1005 | ||
1006 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
1007 | if (status == (ERBFI | ETBEI)) { | |
1008 | /* ok, the port was enabled */ | |
45828b81 | 1009 | u16 lcr, dlh, dll; |
194de561 BW |
1010 | |
1011 | lcr = UART_GET_LCR(uart); | |
1012 | ||
1013 | *parity = 'n'; | |
1014 | if (lcr & PEN) { | |
1015 | if (lcr & EPS) | |
1016 | *parity = 'e'; | |
1017 | else | |
1018 | *parity = 'o'; | |
1019 | } | |
1020 | switch (lcr & 0x03) { | |
1021 | case 0: *bits = 5; break; | |
1022 | case 1: *bits = 6; break; | |
1023 | case 2: *bits = 7; break; | |
1024 | case 3: *bits = 8; break; | |
1025 | } | |
1026 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 1027 | UART_SET_DLAB(uart); |
194de561 BW |
1028 | |
1029 | dll = UART_GET_DLL(uart); | |
1030 | dlh = UART_GET_DLH(uart); | |
1031 | ||
1032 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 1033 | UART_CLEAR_DLAB(uart); |
194de561 BW |
1034 | |
1035 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1036 | } | |
71cc2c21 | 1037 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits); |
194de561 | 1038 | } |
0ae53640 | 1039 | |
0ae53640 | 1040 | static struct uart_driver bfin_serial_reg; |
194de561 BW |
1041 | |
1042 | static int __init | |
1043 | bfin_serial_console_setup(struct console *co, char *options) | |
1044 | { | |
1045 | struct bfin_serial_port *uart; | |
1046 | int baud = 57600; | |
1047 | int bits = 8; | |
1048 | int parity = 'n'; | |
b6efa1ea | 1049 | # ifdef CONFIG_SERIAL_BFIN_CTSRTS |
194de561 | 1050 | int flow = 'r'; |
b6efa1ea | 1051 | # else |
194de561 | 1052 | int flow = 'n'; |
0ae53640 | 1053 | # endif |
194de561 BW |
1054 | |
1055 | /* | |
1056 | * Check whether an invalid uart number has been specified, and | |
1057 | * if so, search for the first available port that does have | |
1058 | * console support. | |
1059 | */ | |
c9607ecc | 1060 | if (co->index == -1 || co->index >= nr_active_ports) |
194de561 BW |
1061 | co->index = 0; |
1062 | uart = &bfin_serial_ports[co->index]; | |
1063 | ||
1064 | if (options) | |
1065 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1066 | else | |
1067 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1068 | ||
1069 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 RG |
1070 | } |
1071 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1072 | defined (CONFIG_EARLY_PRINTK) */ | |
1073 | ||
1074 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1075 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) | |
1076 | { | |
1077 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1078 | while (!(UART_GET_LSR(uart) & THRE)) | |
1079 | barrier(); | |
1080 | UART_PUT_CHAR(uart, ch); | |
1081 | SSYNC(); | |
1082 | } | |
1083 | ||
1084 | /* | |
1085 | * Interrupts are disabled on entering | |
1086 | */ | |
1087 | static void | |
1088 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1089 | { | |
1090 | struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; | |
1091 | int flags = 0; | |
1092 | ||
1093 | spin_lock_irqsave(&uart->port.lock, flags); | |
1094 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1095 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1096 | ||
194de561 BW |
1097 | } |
1098 | ||
194de561 BW |
1099 | static struct console bfin_serial_console = { |
1100 | .name = BFIN_SERIAL_NAME, | |
1101 | .write = bfin_serial_console_write, | |
1102 | .device = uart_console_device, | |
1103 | .setup = bfin_serial_console_setup, | |
1104 | .flags = CON_PRINTBUFFER, | |
1105 | .index = -1, | |
1106 | .data = &bfin_serial_reg, | |
1107 | }; | |
1108 | ||
1109 | static int __init bfin_serial_rs_console_init(void) | |
1110 | { | |
1111 | bfin_serial_init_ports(); | |
1112 | register_console(&bfin_serial_console); | |
52e15f0e | 1113 | |
194de561 BW |
1114 | return 0; |
1115 | } | |
1116 | console_initcall(bfin_serial_rs_console_init); | |
1117 | ||
1118 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console | |
1119 | #else | |
1120 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1121 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1122 | ||
1123 | ||
1124 | #ifdef CONFIG_EARLY_PRINTK | |
1125 | static __init void early_serial_putc(struct uart_port *port, int ch) | |
1126 | { | |
1127 | unsigned timeout = 0xffff; | |
1128 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1129 | ||
1130 | while ((!(UART_GET_LSR(uart) & THRE)) && --timeout) | |
1131 | cpu_relax(); | |
1132 | UART_PUT_CHAR(uart, ch); | |
1133 | } | |
1134 | ||
1135 | static __init void early_serial_write(struct console *con, const char *s, | |
1136 | unsigned int n) | |
1137 | { | |
1138 | struct bfin_serial_port *uart = &bfin_serial_ports[con->index]; | |
1139 | unsigned int i; | |
1140 | ||
1141 | for (i = 0; i < n; i++, s++) { | |
1142 | if (*s == '\n') | |
1143 | early_serial_putc(&uart->port, '\r'); | |
1144 | early_serial_putc(&uart->port, *s); | |
1145 | } | |
1146 | } | |
1147 | ||
c1113400 | 1148 | static struct __initdata console bfin_early_serial_console = { |
0ae53640 RG |
1149 | .name = "early_BFuart", |
1150 | .write = early_serial_write, | |
1151 | .device = uart_console_device, | |
1152 | .flags = CON_PRINTBUFFER, | |
1153 | .setup = bfin_serial_console_setup, | |
1154 | .index = -1, | |
1155 | .data = &bfin_serial_reg, | |
1156 | }; | |
1157 | ||
1158 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1159 | unsigned int cflag) | |
1160 | { | |
1161 | struct bfin_serial_port *uart; | |
1162 | struct ktermios t; | |
1163 | ||
c9607ecc | 1164 | if (port == -1 || port >= nr_active_ports) |
0ae53640 RG |
1165 | port = 0; |
1166 | bfin_serial_init_ports(); | |
1167 | bfin_early_serial_console.index = port; | |
0ae53640 RG |
1168 | uart = &bfin_serial_ports[port]; |
1169 | t.c_cflag = cflag; | |
1170 | t.c_iflag = 0; | |
1171 | t.c_oflag = 0; | |
1172 | t.c_lflag = ICANON; | |
1173 | t.c_line = port; | |
1174 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1175 | return &bfin_early_serial_console; | |
1176 | } | |
1177 | ||
b6efa1ea | 1178 | #endif /* CONFIG_EARLY_PRINTK */ |
194de561 BW |
1179 | |
1180 | static struct uart_driver bfin_serial_reg = { | |
1181 | .owner = THIS_MODULE, | |
1182 | .driver_name = "bfin-uart", | |
1183 | .dev_name = BFIN_SERIAL_NAME, | |
1184 | .major = BFIN_SERIAL_MAJOR, | |
1185 | .minor = BFIN_SERIAL_MINOR, | |
2ade9729 | 1186 | .nr = BFIN_UART_NR_PORTS, |
194de561 BW |
1187 | .cons = BFIN_SERIAL_CONSOLE, |
1188 | }; | |
1189 | ||
1190 | static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1191 | { | |
ccfbc3e1 | 1192 | int i; |
194de561 | 1193 | |
c9607ecc | 1194 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1195 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1196 | continue; | |
1197 | uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1198 | } | |
194de561 BW |
1199 | |
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | static int bfin_serial_resume(struct platform_device *dev) | |
1204 | { | |
ccfbc3e1 | 1205 | int i; |
194de561 | 1206 | |
c9607ecc | 1207 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1208 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1209 | continue; | |
1210 | uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1211 | } | |
194de561 BW |
1212 | |
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | static int bfin_serial_probe(struct platform_device *dev) | |
1217 | { | |
1218 | struct resource *res = dev->resource; | |
1219 | int i; | |
1220 | ||
1221 | for (i = 0; i < dev->num_resources; i++, res++) | |
1222 | if (res->flags & IORESOURCE_MEM) | |
1223 | break; | |
1224 | ||
1225 | if (i < dev->num_resources) { | |
c9607ecc | 1226 | for (i = 0; i < nr_active_ports; i++, res++) { |
194de561 BW |
1227 | if (bfin_serial_ports[i].port.mapbase != res->start) |
1228 | continue; | |
1229 | bfin_serial_ports[i].port.dev = &dev->dev; | |
1230 | uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
194de561 BW |
1231 | } |
1232 | } | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | ||
ccfbc3e1 | 1237 | static int bfin_serial_remove(struct platform_device *dev) |
194de561 | 1238 | { |
ccfbc3e1 | 1239 | int i; |
194de561 | 1240 | |
c9607ecc | 1241 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1242 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1243 | continue; | |
1244 | uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1245 | bfin_serial_ports[i].port.dev = NULL; | |
194de561 | 1246 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
ccfbc3e1 SZ |
1247 | gpio_free(bfin_serial_ports[i].cts_pin); |
1248 | gpio_free(bfin_serial_ports[i].rts_pin); | |
194de561 | 1249 | #endif |
ccfbc3e1 | 1250 | } |
194de561 BW |
1251 | |
1252 | return 0; | |
1253 | } | |
1254 | ||
1255 | static struct platform_driver bfin_serial_driver = { | |
1256 | .probe = bfin_serial_probe, | |
1257 | .remove = bfin_serial_remove, | |
1258 | .suspend = bfin_serial_suspend, | |
1259 | .resume = bfin_serial_resume, | |
1260 | .driver = { | |
1261 | .name = "bfin-uart", | |
e169c139 | 1262 | .owner = THIS_MODULE, |
194de561 BW |
1263 | }, |
1264 | }; | |
1265 | ||
1266 | static int __init bfin_serial_init(void) | |
1267 | { | |
1268 | int ret; | |
1269 | ||
1270 | pr_info("Serial: Blackfin serial driver\n"); | |
1271 | ||
1272 | bfin_serial_init_ports(); | |
1273 | ||
1274 | ret = uart_register_driver(&bfin_serial_reg); | |
1275 | if (ret == 0) { | |
1276 | ret = platform_driver_register(&bfin_serial_driver); | |
1277 | if (ret) { | |
1278 | pr_debug("uart register failed\n"); | |
1279 | uart_unregister_driver(&bfin_serial_reg); | |
1280 | } | |
1281 | } | |
1282 | return ret; | |
1283 | } | |
1284 | ||
1285 | static void __exit bfin_serial_exit(void) | |
1286 | { | |
1287 | platform_driver_unregister(&bfin_serial_driver); | |
1288 | uart_unregister_driver(&bfin_serial_reg); | |
1289 | } | |
1290 | ||
52e15f0e | 1291 | |
194de561 BW |
1292 | module_init(bfin_serial_init); |
1293 | module_exit(bfin_serial_exit); | |
1294 | ||
1295 | MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>"); | |
1296 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); | |
1297 | MODULE_LICENSE("GPL"); | |
1298 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); | |
e169c139 | 1299 | MODULE_ALIAS("platform:bfin-uart"); |