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[ARM] omap: improve is_omap_port()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
1da177e4
LT		 15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
1da177e4
LT		 20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
1da177e4 31#include <linux/delay.h>
d052d1be 32#include <linux/platform_device.h>
1da177e4
LT		 33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_reg.h>
36#include <linux/serial_core.h>
37#include <linux/serial.h>
38#include <linux/serial_8250.h>
78512ece 39#include <linux/nmi.h>
f392ecfa 40#include <linux/mutex.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
47/*
48 * Configuration:
40663cc7 49 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 50 * is unsafe when used on edge-triggered interrupts.
51 */
408b664a 52static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 53
a61c2d78
DJ		 54static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
55
1da177e4
LT		 56/*
57 * Debugging.
58 */
59#if 0
60#define DEBUG_AUTOCONF(fmt...) printk(fmt)
61#else
62#define DEBUG_AUTOCONF(fmt...) do { } while (0)
63#endif
64
65#if 0
66#define DEBUG_INTR(fmt...) printk(fmt)
67#else
68#define DEBUG_INTR(fmt...) do { } while (0)
69#endif
70
71#define PASS_LIMIT 256
72
73/*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78#define is_real_interrupt(irq) ((irq) != 0)
79
1da177e4
LT		 80#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
81#define CONFIG_SERIAL_DETECT_IRQ 1
82#endif
1da177e4
LT		 83#ifdef CONFIG_SERIAL_8250_MANY_PORTS
84#define CONFIG_SERIAL_MANY_PORTS 1
85#endif
86
87/*
88 * HUB6 is always on. This will be removed once the header
89 * files have been cleaned.
90 */
91#define CONFIG_HUB6 1
92
a4ed1e41 93#include <asm/serial.h>
1da177e4
LT		 94/*
95 * SERIAL_PORT_DFNS tells us about built-in ports that have no
96 * standard enumeration mechanism. Platforms that can find all
97 * serial ports via mechanisms like ACPI or PCI need not supply it.
98 */
99#ifndef SERIAL_PORT_DFNS
100#define SERIAL_PORT_DFNS
101#endif
102
cb3592be 103static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 104 SERIAL_PORT_DFNS /* defined in asm/serial.h */
105};
106
026d02a2 107#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 108
109#ifdef CONFIG_SERIAL_8250_RSA
110
111#define PORT_RSA_MAX 4
112static unsigned long probe_rsa[PORT_RSA_MAX];
113static unsigned int probe_rsa_count;
114#endif /* CONFIG_SERIAL_8250_RSA */
115
116struct uart_8250_port {
117 struct uart_port port;
118 struct timer_list timer; /* "no irq" timer */
119 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 120 unsigned short capabilities; /* port capabilities */
121 unsigned short bugs; /* port bugs */
1da177e4 122 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 123 unsigned char acr;
124 unsigned char ier;
125 unsigned char lcr;
126 unsigned char mcr;
127 unsigned char mcr_mask; /* mask of user bits */
128 unsigned char mcr_force; /* mask of forced bits */
ad4c2aa6
CM		 129
130 /*
131 * Some bits in registers are cleared on a read, so they must
132 * be saved whenever the register is read but the bits will not
133 * be immediately processed.
134 */
135#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
136 unsigned char lsr_saved_flags;
137#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
138 unsigned char msr_saved_flags;
1da177e4
LT		 139
140 /*
141 * We provide a per-port pm hook.
142 */
143 void (*pm)(struct uart_port *port,
144 unsigned int state, unsigned int old);
145};
146
147struct irq_info {
148 spinlock_t lock;
149 struct list_head *head;
150};
151
152static struct irq_info irq_lists[NR_IRQS];
153
154/*
155 * Here we define the default xmit fifo size used for each type of UART.
156 */
157static const struct serial8250_config uart_config[] = {
158 [PORT_UNKNOWN] = {
159 .name = "unknown",
160 .fifo_size = 1,
161 .tx_loadsz = 1,
162 },
163 [PORT_8250] = {
164 .name = "8250",
165 .fifo_size = 1,
166 .tx_loadsz = 1,
167 },
168 [PORT_16450] = {
169 .name = "16450",
170 .fifo_size = 1,
171 .tx_loadsz = 1,
172 },
173 [PORT_16550] = {
174 .name = "16550",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_16550A] = {
179 .name = "16550A",
180 .fifo_size = 16,
181 .tx_loadsz = 16,
182 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
183 .flags = UART_CAP_FIFO,
184 },
185 [PORT_CIRRUS] = {
186 .name = "Cirrus",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 },
190 [PORT_16650] = {
191 .name = "ST16650",
192 .fifo_size = 1,
193 .tx_loadsz = 1,
194 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
195 },
196 [PORT_16650V2] = {
197 .name = "ST16650V2",
198 .fifo_size = 32,
199 .tx_loadsz = 16,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
201 UART_FCR_T_TRIG_00,
202 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
203 },
204 [PORT_16750] = {
205 .name = "TI16750",
206 .fifo_size = 64,
207 .tx_loadsz = 64,
208 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
209 UART_FCR7_64BYTE,
210 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
211 },
212 [PORT_STARTECH] = {
213 .name = "Startech",
214 .fifo_size = 1,
215 .tx_loadsz = 1,
216 },
217 [PORT_16C950] = {
218 .name = "16C950/954",
219 .fifo_size = 128,
220 .tx_loadsz = 128,
221 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
222 .flags = UART_CAP_FIFO,
223 },
224 [PORT_16654] = {
225 .name = "ST16654",
226 .fifo_size = 64,
227 .tx_loadsz = 32,
228 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
229 UART_FCR_T_TRIG_10,
230 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
231 },
232 [PORT_16850] = {
233 .name = "XR16850",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
238 },
239 [PORT_RSA] = {
240 .name = "RSA",
241 .fifo_size = 2048,
242 .tx_loadsz = 2048,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
244 .flags = UART_CAP_FIFO,
245 },
246 [PORT_NS16550A] = {
247 .name = "NS16550A",
248 .fifo_size = 16,
249 .tx_loadsz = 16,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_NATSEMI,
252 },
253 [PORT_XSCALE] = {
254 .name = "XScale",
255 .fifo_size = 32,
256 .tx_loadsz = 32,
257 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
258 .flags = UART_CAP_FIFO | UART_CAP_UUE,
259 },
bd71c182
TK		 260 [PORT_RM9000] = {
261 .name = "RM9000",
262 .fifo_size = 16,
263 .tx_loadsz = 16,
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
265 .flags = UART_CAP_FIFO,
266 },
1da177e4
LT		 267};
268
bd71c182 269#if defined (CONFIG_SERIAL_8250_AU1X00)
21c614a7
PA		 270
271/* Au1x00 UART hardware has a weird register layout */
272static const u8 au_io_in_map[] = {
273 [UART_RX] = 0,
274 [UART_IER] = 2,
275 [UART_IIR] = 3,
276 [UART_LCR] = 5,
277 [UART_MCR] = 6,
278 [UART_LSR] = 7,
279 [UART_MSR] = 8,
280};
281
282static const u8 au_io_out_map[] = {
283 [UART_TX] = 1,
284 [UART_IER] = 2,
285 [UART_FCR] = 4,
286 [UART_LCR] = 5,
287 [UART_MCR] = 6,
288};
289
290/* sane hardware needs no mapping */
291static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
292{
293 if (up->port.iotype != UPIO_AU)
294 return offset;
295 return au_io_in_map[offset];
296}
297
298static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
299{
300 if (up->port.iotype != UPIO_AU)
301 return offset;
302 return au_io_out_map[offset];
303}
304
6f803cd0 305#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 306
307static const u8
308 regmap_in[8] = {
309 [UART_RX] = 0x00,
310 [UART_IER] = 0x0c,
311 [UART_IIR] = 0x14,
312 [UART_LCR] = 0x1c,
313 [UART_MCR] = 0x20,
314 [UART_LSR] = 0x24,
315 [UART_MSR] = 0x28,
316 [UART_SCR] = 0x2c
317 },
318 regmap_out[8] = {
319 [UART_TX] = 0x04,
320 [UART_IER] = 0x0c,
321 [UART_FCR] = 0x18,
322 [UART_LCR] = 0x1c,
323 [UART_MCR] = 0x20,
324 [UART_LSR] = 0x24,
325 [UART_MSR] = 0x28,
326 [UART_SCR] = 0x2c
327 };
328
329static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
330{
331 if (up->port.iotype != UPIO_RM9000)
332 return offset;
333 return regmap_in[offset];
334}
335
336static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
337{
338 if (up->port.iotype != UPIO_RM9000)
339 return offset;
340 return regmap_out[offset];
341}
342
21c614a7
PA		 343#else
344
345/* sane hardware needs no mapping */
346#define map_8250_in_reg(up, offset) (offset)
347#define map_8250_out_reg(up, offset) (offset)
348
349#endif
350
ea8874dc 351static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 352{
3be91ec7 353 unsigned int tmp;
21c614a7 354 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 355
356 switch (up->port.iotype) {
357 case UPIO_HUB6:
358 outb(up->port.hub6 - 1 + offset, up->port.iobase);
359 return inb(up->port.iobase + 1);
360
361 case UPIO_MEM:
beab697a 362 case UPIO_DWAPB:
1da177e4
LT		 363 return readb(up->port.membase + offset);
364
bd71c182 365 case UPIO_RM9000:
1da177e4
LT		 366 case UPIO_MEM32:
367 return readl(up->port.membase + offset);
368
21c614a7
PA		 369#ifdef CONFIG_SERIAL_8250_AU1X00
370 case UPIO_AU:
371 return __raw_readl(up->port.membase + offset);
372#endif
373
3be91ec7
ZR		 374 case UPIO_TSI:
375 if (offset == UART_IIR) {
9e84b60e
AV		 376 tmp = readl(up->port.membase + (UART_IIR & ~3));
377 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
3be91ec7
ZR		 378 } else
379 return readb(up->port.membase + offset);
380
1da177e4
LT		 381 default:
382 return inb(up->port.iobase + offset);
383 }
384}
385
ea8874dc 386static void
1da177e4
LT		 387serial_out(struct uart_8250_port *up, int offset, int value)
388{
beab697a
MSJ		 389 /* Save the offset before it's remapped */
390 int save_offset = offset;
21c614a7 391 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 392
393 switch (up->port.iotype) {
394 case UPIO_HUB6:
395 outb(up->port.hub6 - 1 + offset, up->port.iobase);
396 outb(value, up->port.iobase + 1);
397 break;
398
399 case UPIO_MEM:
400 writeb(value, up->port.membase + offset);
401 break;
402
bd71c182 403 case UPIO_RM9000:
1da177e4
LT		 404 case UPIO_MEM32:
405 writel(value, up->port.membase + offset);
406 break;
407
21c614a7
PA		 408#ifdef CONFIG_SERIAL_8250_AU1X00
409 case UPIO_AU:
410 __raw_writel(value, up->port.membase + offset);
411 break;
412#endif
3be91ec7
ZR		 413 case UPIO_TSI:
414 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
415 writeb(value, up->port.membase + offset);
416 break;
21c614a7 417
beab697a
MSJ		 418 case UPIO_DWAPB:
419 /* Save the LCR value so it can be re-written when a
420 * Busy Detect interrupt occurs. */
421 if (save_offset == UART_LCR)
422 up->lcr = value;
423 writeb(value, up->port.membase + offset);
424 /* Read the IER to ensure any interrupt is cleared before
425 * returning from ISR. */
426 if (save_offset == UART_TX || save_offset == UART_IER)
427 value = serial_in(up, UART_IER);
428 break;
429
1da177e4
LT		 430 default:
431 outb(value, up->port.iobase + offset);
432 }
433}
434
40b36daa
AW		 435static void
436serial_out_sync(struct uart_8250_port *up, int offset, int value)
437{
438 switch (up->port.iotype) {
439 case UPIO_MEM:
440 case UPIO_MEM32:
441#ifdef CONFIG_SERIAL_8250_AU1X00
442 case UPIO_AU:
443#endif
beab697a 444 case UPIO_DWAPB:
40b36daa
AW		 445 serial_out(up, offset, value);
446 serial_in(up, UART_LCR); /* safe, no side-effects */
447 break;
448 default:
449 serial_out(up, offset, value);
450 }
451}
452
1da177e4
LT		 453/*
454 * We used to support using pause I/O for certain machines. We
455 * haven't supported this for a while, but just in case it's badly
456 * needed for certain old 386 machines, I've left these #define's
457 * in....
458 */
459#define serial_inp(up, offset) serial_in(up, offset)
460#define serial_outp(up, offset, value) serial_out(up, offset, value)
461
b32b19b8
JAH		 462/* Uart divisor latch read */
463static inline int _serial_dl_read(struct uart_8250_port *up)
464{
465 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
466}
467
468/* Uart divisor latch write */
469static inline void _serial_dl_write(struct uart_8250_port *up, int value)
470{
471 serial_outp(up, UART_DLL, value & 0xff);
472 serial_outp(up, UART_DLM, value >> 8 & 0xff);
473}
474
6f803cd0 475#if defined(CONFIG_SERIAL_8250_AU1X00)
b32b19b8
JAH		 476/* Au1x00 haven't got a standard divisor latch */
477static int serial_dl_read(struct uart_8250_port *up)
478{
479 if (up->port.iotype == UPIO_AU)
480 return __raw_readl(up->port.membase + 0x28);
481 else
482 return _serial_dl_read(up);
483}
484
485static void serial_dl_write(struct uart_8250_port *up, int value)
486{
487 if (up->port.iotype == UPIO_AU)
488 __raw_writel(value, up->port.membase + 0x28);
489 else
490 _serial_dl_write(up, value);
491}
6f803cd0 492#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 493static int serial_dl_read(struct uart_8250_port *up)
494{
495 return (up->port.iotype == UPIO_RM9000) ?
496 (((__raw_readl(up->port.membase + 0x10) << 8) |
497 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
498 _serial_dl_read(up);
499}
500
501static void serial_dl_write(struct uart_8250_port *up, int value)
502{
503 if (up->port.iotype == UPIO_RM9000) {
504 __raw_writel(value, up->port.membase + 0x08);
505 __raw_writel(value >> 8, up->port.membase + 0x10);
506 } else {
507 _serial_dl_write(up, value);
508 }
509}
b32b19b8
JAH		 510#else
511#define serial_dl_read(up) _serial_dl_read(up)
512#define serial_dl_write(up, value) _serial_dl_write(up, value)
513#endif
1da177e4
LT		 514
515/*
516 * For the 16C950
517 */
518static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
519{
520 serial_out(up, UART_SCR, offset);
521 serial_out(up, UART_ICR, value);
522}
523
524static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
525{
526 unsigned int value;
527
528 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
529 serial_out(up, UART_SCR, offset);
530 value = serial_in(up, UART_ICR);
531 serial_icr_write(up, UART_ACR, up->acr);
532
533 return value;
534}
535
536/*
537 * FIFO support.
538 */
539static inline void serial8250_clear_fifos(struct uart_8250_port *p)
540{
541 if (p->capabilities & UART_CAP_FIFO) {
542 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
543 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
544 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
545 serial_outp(p, UART_FCR, 0);
546 }
547}
548
549/*
550 * IER sleep support. UARTs which have EFRs need the "extended
551 * capability" bit enabled. Note that on XR16C850s, we need to
552 * reset LCR to write to IER.
553 */
554static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
555{
556 if (p->capabilities & UART_CAP_SLEEP) {
557 if (p->capabilities & UART_CAP_EFR) {
558 serial_outp(p, UART_LCR, 0xBF);
559 serial_outp(p, UART_EFR, UART_EFR_ECB);
560 serial_outp(p, UART_LCR, 0);
561 }
562 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
563 if (p->capabilities & UART_CAP_EFR) {
564 serial_outp(p, UART_LCR, 0xBF);
565 serial_outp(p, UART_EFR, 0);
566 serial_outp(p, UART_LCR, 0);
567 }
568 }
569}
570
571#ifdef CONFIG_SERIAL_8250_RSA
572/*
573 * Attempts to turn on the RSA FIFO. Returns zero on failure.
574 * We set the port uart clock rate if we succeed.
575 */
576static int __enable_rsa(struct uart_8250_port *up)
577{
578 unsigned char mode;
579 int result;
580
581 mode = serial_inp(up, UART_RSA_MSR);
582 result = mode & UART_RSA_MSR_FIFO;
583
584 if (!result) {
585 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
586 mode = serial_inp(up, UART_RSA_MSR);
587 result = mode & UART_RSA_MSR_FIFO;
588 }
589
590 if (result)
591 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
592
593 return result;
594}
595
596static void enable_rsa(struct uart_8250_port *up)
597{
598 if (up->port.type == PORT_RSA) {
599 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
600 spin_lock_irq(&up->port.lock);
601 __enable_rsa(up);
602 spin_unlock_irq(&up->port.lock);
603 }
604 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
605 serial_outp(up, UART_RSA_FRR, 0);
606 }
607}
608
609/*
610 * Attempts to turn off the RSA FIFO. Returns zero on failure.
611 * It is unknown why interrupts were disabled in here. However,
612 * the caller is expected to preserve this behaviour by grabbing
613 * the spinlock before calling this function.
614 */
615static void disable_rsa(struct uart_8250_port *up)
616{
617 unsigned char mode;
618 int result;
619
620 if (up->port.type == PORT_RSA &&
621 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
622 spin_lock_irq(&up->port.lock);
623
624 mode = serial_inp(up, UART_RSA_MSR);
625 result = !(mode & UART_RSA_MSR_FIFO);
626
627 if (!result) {
628 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
629 mode = serial_inp(up, UART_RSA_MSR);
630 result = !(mode & UART_RSA_MSR_FIFO);
631 }
632
633 if (result)
634 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
635 spin_unlock_irq(&up->port.lock);
636 }
637}
638#endif /* CONFIG_SERIAL_8250_RSA */
639
640/*
641 * This is a quickie test to see how big the FIFO is.
642 * It doesn't work at all the time, more's the pity.
643 */
644static int size_fifo(struct uart_8250_port *up)
645{
b32b19b8
JAH		 646 unsigned char old_fcr, old_mcr, old_lcr;
647 unsigned short old_dl;
1da177e4
LT		 648 int count;
649
650 old_lcr = serial_inp(up, UART_LCR);
651 serial_outp(up, UART_LCR, 0);
652 old_fcr = serial_inp(up, UART_FCR);
653 old_mcr = serial_inp(up, UART_MCR);
654 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
655 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
656 serial_outp(up, UART_MCR, UART_MCR_LOOP);
657 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 658 old_dl = serial_dl_read(up);
659 serial_dl_write(up, 0x0001);
1da177e4
LT		 660 serial_outp(up, UART_LCR, 0x03);
661 for (count = 0; count < 256; count++)
662 serial_outp(up, UART_TX, count);
663 mdelay(20);/* FIXME - schedule_timeout */
664 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
665 (count < 256); count++)
666 serial_inp(up, UART_RX);
667 serial_outp(up, UART_FCR, old_fcr);
668 serial_outp(up, UART_MCR, old_mcr);
669 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 670 serial_dl_write(up, old_dl);
1da177e4
LT		 671 serial_outp(up, UART_LCR, old_lcr);
672
673 return count;
674}
675
676/*
677 * Read UART ID using the divisor method - set DLL and DLM to zero
678 * and the revision will be in DLL and device type in DLM. We
679 * preserve the device state across this.
680 */
681static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
682{
683 unsigned char old_dll, old_dlm, old_lcr;
684 unsigned int id;
685
686 old_lcr = serial_inp(p, UART_LCR);
687 serial_outp(p, UART_LCR, UART_LCR_DLAB);
688
689 old_dll = serial_inp(p, UART_DLL);
690 old_dlm = serial_inp(p, UART_DLM);
691
692 serial_outp(p, UART_DLL, 0);
693 serial_outp(p, UART_DLM, 0);
694
695 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
696
697 serial_outp(p, UART_DLL, old_dll);
698 serial_outp(p, UART_DLM, old_dlm);
699 serial_outp(p, UART_LCR, old_lcr);
700
701 return id;
702}
703
704/*
705 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
706 * When this function is called we know it is at least a StarTech
707 * 16650 V2, but it might be one of several StarTech UARTs, or one of
708 * its clones. (We treat the broken original StarTech 16650 V1 as a
709 * 16550, and why not? Startech doesn't seem to even acknowledge its
710 * existence.)
bd71c182 711 *
1da177e4
LT		 712 * What evil have men's minds wrought...
713 */
714static void autoconfig_has_efr(struct uart_8250_port *up)
715{
716 unsigned int id1, id2, id3, rev;
717
718 /*
719 * Everything with an EFR has SLEEP
720 */
721 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
722
723 /*
724 * First we check to see if it's an Oxford Semiconductor UART.
725 *
726 * If we have to do this here because some non-National
727 * Semiconductor clone chips lock up if you try writing to the
728 * LSR register (which serial_icr_read does)
729 */
730
731 /*
732 * Check for Oxford Semiconductor 16C950.
733 *
734 * EFR [4] must be set else this test fails.
735 *
736 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
737 * claims that it's needed for 952 dual UART's (which are not
738 * recommended for new designs).
739 */
740 up->acr = 0;
741 serial_out(up, UART_LCR, 0xBF);
742 serial_out(up, UART_EFR, UART_EFR_ECB);
743 serial_out(up, UART_LCR, 0x00);
744 id1 = serial_icr_read(up, UART_ID1);
745 id2 = serial_icr_read(up, UART_ID2);
746 id3 = serial_icr_read(up, UART_ID3);
747 rev = serial_icr_read(up, UART_REV);
748
749 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
750
751 if (id1 == 0x16 && id2 == 0xC9 &&
752 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
753 up->port.type = PORT_16C950;
4ba5e35d
RK		 754
755 /*
756 * Enable work around for the Oxford Semiconductor 952 rev B
757 * chip which causes it to seriously miscalculate baud rates
758 * when DLL is 0.
759 */
760 if (id3 == 0x52 && rev == 0x01)
761 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 762 return;
763 }
bd71c182 764
1da177e4
LT		 765 /*
766 * We check for a XR16C850 by setting DLL and DLM to 0, and then
767 * reading back DLL and DLM. The chip type depends on the DLM
768 * value read back:
769 * 0x10 - XR16C850 and the DLL contains the chip revision.
770 * 0x12 - XR16C2850.
771 * 0x14 - XR16C854.
772 */
773 id1 = autoconfig_read_divisor_id(up);
774 DEBUG_AUTOCONF("850id=%04x ", id1);
775
776 id2 = id1 >> 8;
777 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 778 up->port.type = PORT_16850;
779 return;
780 }
781
782 /*
783 * It wasn't an XR16C850.
784 *
785 * We distinguish between the '654 and the '650 by counting
786 * how many bytes are in the FIFO. I'm using this for now,
787 * since that's the technique that was sent to me in the
788 * serial driver update, but I'm not convinced this works.
789 * I've had problems doing this in the past. -TYT
790 */
791 if (size_fifo(up) == 64)
792 up->port.type = PORT_16654;
793 else
794 up->port.type = PORT_16650V2;
795}
796
797/*
798 * We detected a chip without a FIFO. Only two fall into
799 * this category - the original 8250 and the 16450. The
800 * 16450 has a scratch register (accessible with LCR=0)
801 */
802static void autoconfig_8250(struct uart_8250_port *up)
803{
804 unsigned char scratch, status1, status2;
805
806 up->port.type = PORT_8250;
807
808 scratch = serial_in(up, UART_SCR);
809 serial_outp(up, UART_SCR, 0xa5);
810 status1 = serial_in(up, UART_SCR);
811 serial_outp(up, UART_SCR, 0x5a);
812 status2 = serial_in(up, UART_SCR);
813 serial_outp(up, UART_SCR, scratch);
814
815 if (status1 == 0xa5 && status2 == 0x5a)
816 up->port.type = PORT_16450;
817}
818
819static int broken_efr(struct uart_8250_port *up)
820{
821 /*
822 * Exar ST16C2550 "A2" devices incorrectly detect as
823 * having an EFR, and report an ID of 0x0201. See
824 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
825 */
826 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
827 return 1;
828
829 return 0;
830}
831
832/*
833 * We know that the chip has FIFOs. Does it have an EFR? The
834 * EFR is located in the same register position as the IIR and
835 * we know the top two bits of the IIR are currently set. The
836 * EFR should contain zero. Try to read the EFR.
837 */
838static void autoconfig_16550a(struct uart_8250_port *up)
839{
840 unsigned char status1, status2;
841 unsigned int iersave;
842
843 up->port.type = PORT_16550A;
844 up->capabilities |= UART_CAP_FIFO;
845
846 /*
847 * Check for presence of the EFR when DLAB is set.
848 * Only ST16C650V1 UARTs pass this test.
849 */
850 serial_outp(up, UART_LCR, UART_LCR_DLAB);
851 if (serial_in(up, UART_EFR) == 0) {
852 serial_outp(up, UART_EFR, 0xA8);
853 if (serial_in(up, UART_EFR) != 0) {
854 DEBUG_AUTOCONF("EFRv1 ");
855 up->port.type = PORT_16650;
856 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
857 } else {
858 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
859 }
860 serial_outp(up, UART_EFR, 0);
861 return;
862 }
863
864 /*
865 * Maybe it requires 0xbf to be written to the LCR.
866 * (other ST16C650V2 UARTs, TI16C752A, etc)
867 */
868 serial_outp(up, UART_LCR, 0xBF);
869 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
870 DEBUG_AUTOCONF("EFRv2 ");
871 autoconfig_has_efr(up);
872 return;
873 }
874
875 /*
876 * Check for a National Semiconductor SuperIO chip.
877 * Attempt to switch to bank 2, read the value of the LOOP bit
878 * from EXCR1. Switch back to bank 0, change it in MCR. Then
879 * switch back to bank 2, read it from EXCR1 again and check
880 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 881 */
882 serial_outp(up, UART_LCR, 0);
883 status1 = serial_in(up, UART_MCR);
884 serial_outp(up, UART_LCR, 0xE0);
885 status2 = serial_in(up, 0x02); /* EXCR1 */
886
887 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
888 serial_outp(up, UART_LCR, 0);
889 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
890 serial_outp(up, UART_LCR, 0xE0);
891 status2 = serial_in(up, 0x02); /* EXCR1 */
892 serial_outp(up, UART_LCR, 0);
893 serial_outp(up, UART_MCR, status1);
894
895 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 896 unsigned short quot;
897
1da177e4 898 serial_outp(up, UART_LCR, 0xE0);
857dde2e 899
b32b19b8 900 quot = serial_dl_read(up);
857dde2e
DW		 901 quot <<= 3;
902
b5b82df6 903 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 904 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
905 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
906 serial_outp(up, 0x04, status1);
bd71c182 907
b32b19b8 908 serial_dl_write(up, quot);
857dde2e 909
1da177e4 910 serial_outp(up, UART_LCR, 0);
1da177e4 911
857dde2e 912 up->port.uartclk = 921600*16;
1da177e4
LT		 913 up->port.type = PORT_NS16550A;
914 up->capabilities |= UART_NATSEMI;
915 return;
916 }
917 }
918
919 /*
920 * No EFR. Try to detect a TI16750, which only sets bit 5 of
921 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
922 * Try setting it with and without DLAB set. Cheap clones
923 * set bit 5 without DLAB set.
924 */
925 serial_outp(up, UART_LCR, 0);
926 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
927 status1 = serial_in(up, UART_IIR) >> 5;
928 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
929 serial_outp(up, UART_LCR, UART_LCR_DLAB);
930 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
931 status2 = serial_in(up, UART_IIR) >> 5;
932 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
933 serial_outp(up, UART_LCR, 0);
934
935 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
936
937 if (status1 == 6 && status2 == 7) {
938 up->port.type = PORT_16750;
939 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
940 return;
941 }
942
943 /*
944 * Try writing and reading the UART_IER_UUE bit (b6).
945 * If it works, this is probably one of the Xscale platform's
946 * internal UARTs.
947 * We're going to explicitly set the UUE bit to 0 before
948 * trying to write and read a 1 just to make sure it's not
949 * already a 1 and maybe locked there before we even start start.
950 */
951 iersave = serial_in(up, UART_IER);
952 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
953 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
954 /*
955 * OK it's in a known zero state, try writing and reading
956 * without disturbing the current state of the other bits.
957 */
958 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
959 if (serial_in(up, UART_IER) & UART_IER_UUE) {
960 /*
961 * It's an Xscale.
962 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
963 */
964 DEBUG_AUTOCONF("Xscale ");
965 up->port.type = PORT_XSCALE;
966 up->capabilities |= UART_CAP_UUE;
967 return;
968 }
969 } else {
970 /*
971 * If we got here we couldn't force the IER_UUE bit to 0.
972 * Log it and continue.
973 */
974 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
975 }
976 serial_outp(up, UART_IER, iersave);
977}
978
979/*
980 * This routine is called by rs_init() to initialize a specific serial
981 * port. It determines what type of UART chip this serial port is
982 * using: 8250, 16450, 16550, 16550A. The important question is
983 * whether or not this UART is a 16550A or not, since this will
984 * determine whether or not we can use its FIFO features or not.
985 */
986static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
987{
988 unsigned char status1, scratch, scratch2, scratch3;
989 unsigned char save_lcr, save_mcr;
990 unsigned long flags;
991
992 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
993 return;
994
995 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
996 up->port.line, up->port.iobase, up->port.membase);
997
998 /*
999 * We really do need global IRQs disabled here - we're going to
1000 * be frobbing the chips IRQ enable register to see if it exists.
1001 */
1002 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1003
1004 up->capabilities = 0;
4ba5e35d 1005 up->bugs = 0;
1da177e4
LT		 1006
1007 if (!(up->port.flags & UPF_BUGGY_UART)) {
1008 /*
1009 * Do a simple existence test first; if we fail this,
1010 * there's no point trying anything else.
bd71c182 1011 *
1da177e4
LT		 1012 * 0x80 is used as a nonsense port to prevent against
1013 * false positives due to ISA bus float. The
1014 * assumption is that 0x80 is a non-existent port;
1015 * which should be safe since include/asm/io.h also
1016 * makes this assumption.
1017 *
1018 * Note: this is safe as long as MCR bit 4 is clear
1019 * and the device is in "PC" mode.
1020 */
1021 scratch = serial_inp(up, UART_IER);
1022 serial_outp(up, UART_IER, 0);
1023#ifdef __i386__
1024 outb(0xff, 0x080);
1025#endif
48212008
TH		 1026 /*
1027 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1028 * 16C754B) allow only to modify them if an EFR bit is set.
1029 */
1030 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1031 serial_outp(up, UART_IER, 0x0F);
1032#ifdef __i386__
1033 outb(0, 0x080);
1034#endif
48212008 1035 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1036 serial_outp(up, UART_IER, scratch);
1037 if (scratch2 != 0 || scratch3 != 0x0F) {
1038 /*
1039 * We failed; there's nothing here
1040 */
1041 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1042 scratch2, scratch3);
1043 goto out;
1044 }
1045 }
1046
1047 save_mcr = serial_in(up, UART_MCR);
1048 save_lcr = serial_in(up, UART_LCR);
1049
bd71c182 1050 /*
1da177e4
LT		 1051 * Check to see if a UART is really there. Certain broken
1052 * internal modems based on the Rockwell chipset fail this
1053 * test, because they apparently don't implement the loopback
1054 * test mode. So this test is skipped on the COM 1 through
1055 * COM 4 ports. This *should* be safe, since no board
1056 * manufacturer would be stupid enough to design a board
1057 * that conflicts with COM 1-4 --- we hope!
1058 */
1059 if (!(up->port.flags & UPF_SKIP_TEST)) {
1060 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1061 status1 = serial_inp(up, UART_MSR) & 0xF0;
1062 serial_outp(up, UART_MCR, save_mcr);
1063 if (status1 != 0x90) {
1064 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1065 status1);
1066 goto out;
1067 }
1068 }
1069
1070 /*
1071 * We're pretty sure there's a port here. Lets find out what
1072 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1073 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1074 * determines what we test for next.
1075 *
1076 * We also initialise the EFR (if any) to zero for later. The
1077 * EFR occupies the same register location as the FCR and IIR.
1078 */
1079 serial_outp(up, UART_LCR, 0xBF);
1080 serial_outp(up, UART_EFR, 0);
1081 serial_outp(up, UART_LCR, 0);
1082
1083 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1084 scratch = serial_in(up, UART_IIR) >> 6;
1085
1086 DEBUG_AUTOCONF("iir=%d ", scratch);
1087
1088 switch (scratch) {
1089 case 0:
1090 autoconfig_8250(up);
1091 break;
1092 case 1:
1093 up->port.type = PORT_UNKNOWN;
1094 break;
1095 case 2:
1096 up->port.type = PORT_16550;
1097 break;
1098 case 3:
1099 autoconfig_16550a(up);
1100 break;
1101 }
1102
1103#ifdef CONFIG_SERIAL_8250_RSA
1104 /*
1105 * Only probe for RSA ports if we got the region.
1106 */
1107 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1108 int i;
1109
1110 for (i = 0 ; i < probe_rsa_count; ++i) {
1111 if (probe_rsa[i] == up->port.iobase &&
1112 __enable_rsa(up)) {
1113 up->port.type = PORT_RSA;
1114 break;
1115 }
1116 }
1117 }
1118#endif
21c614a7
PA		 1119
1120#ifdef CONFIG_SERIAL_8250_AU1X00
1121 /* if access method is AU, it is a 16550 with a quirk */
1122 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1123 up->bugs |= UART_BUG_NOMSR;
1124#endif
1125
1da177e4
LT		 1126 serial_outp(up, UART_LCR, save_lcr);
1127
1128 if (up->capabilities != uart_config[up->port.type].flags) {
1129 printk(KERN_WARNING
1130 "ttyS%d: detected caps %08x should be %08x\n",
1131 up->port.line, up->capabilities,
1132 uart_config[up->port.type].flags);
1133 }
1134
1135 up->port.fifosize = uart_config[up->port.type].fifo_size;
1136 up->capabilities = uart_config[up->port.type].flags;
1137 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1138
1139 if (up->port.type == PORT_UNKNOWN)
1140 goto out;
1141
1142 /*
1143 * Reset the UART.
1144 */
1145#ifdef CONFIG_SERIAL_8250_RSA
1146 if (up->port.type == PORT_RSA)
1147 serial_outp(up, UART_RSA_FRR, 0);
1148#endif
1149 serial_outp(up, UART_MCR, save_mcr);
1150 serial8250_clear_fifos(up);
40b36daa 1151 serial_in(up, UART_RX);
5c8c755c
LB		 1152 if (up->capabilities & UART_CAP_UUE)
1153 serial_outp(up, UART_IER, UART_IER_UUE);
1154 else
1155 serial_outp(up, UART_IER, 0);
1da177e4 1156
bd71c182 1157 out:
1da177e4 1158 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1159 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1160}
1161
1162static void autoconfig_irq(struct uart_8250_port *up)
1163{
1164 unsigned char save_mcr, save_ier;
1165 unsigned char save_ICP = 0;
1166 unsigned int ICP = 0;
1167 unsigned long irqs;
1168 int irq;
1169
1170 if (up->port.flags & UPF_FOURPORT) {
1171 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1172 save_ICP = inb_p(ICP);
1173 outb_p(0x80, ICP);
1174 (void) inb_p(ICP);
1175 }
1176
1177 /* forget possible initially masked and pending IRQ */
1178 probe_irq_off(probe_irq_on());
1179 save_mcr = serial_inp(up, UART_MCR);
1180 save_ier = serial_inp(up, UART_IER);
1181 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1182
1da177e4
LT		 1183 irqs = probe_irq_on();
1184 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1185 udelay(10);
1186 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1187 serial_outp(up, UART_MCR,
1188 UART_MCR_DTR | UART_MCR_RTS);
1189 } else {
1190 serial_outp(up, UART_MCR,
1191 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1192 }
1193 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1194 (void)serial_inp(up, UART_LSR);
1195 (void)serial_inp(up, UART_RX);
1196 (void)serial_inp(up, UART_IIR);
1197 (void)serial_inp(up, UART_MSR);
1198 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1199 udelay(20);
1da177e4
LT		 1200 irq = probe_irq_off(irqs);
1201
1202 serial_outp(up, UART_MCR, save_mcr);
1203 serial_outp(up, UART_IER, save_ier);
1204
1205 if (up->port.flags & UPF_FOURPORT)
1206 outb_p(save_ICP, ICP);
1207
1208 up->port.irq = (irq > 0) ? irq : 0;
1209}
1210
e763b90c
RK		 1211static inline void __stop_tx(struct uart_8250_port *p)
1212{
1213 if (p->ier & UART_IER_THRI) {
1214 p->ier &= ~UART_IER_THRI;
1215 serial_out(p, UART_IER, p->ier);
1216 }
1217}
1218
b129a8cc 1219static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1220{
1221 struct uart_8250_port *up = (struct uart_8250_port *)port;
1222
e763b90c 1223 __stop_tx(up);
1da177e4
LT		 1224
1225 /*
e763b90c 1226 * We really want to stop the transmitter from sending.
1da177e4 1227 */
e763b90c 1228 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1229 up->acr |= UART_ACR_TXDIS;
1230 serial_icr_write(up, UART_ACR, up->acr);
1231 }
1232}
1233
55d3b282
RK		 1234static void transmit_chars(struct uart_8250_port *up);
1235
b129a8cc 1236static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1237{
1238 struct uart_8250_port *up = (struct uart_8250_port *)port;
1239
1240 if (!(up->ier & UART_IER_THRI)) {
1241 up->ier |= UART_IER_THRI;
1242 serial_out(up, UART_IER, up->ier);
55d3b282 1243
67f7654e 1244 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1245 unsigned char lsr, iir;
1246 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1247 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182
TK		 1248 iir = serial_in(up, UART_IIR) & 0x0f;
1249 if ((up->port.type == PORT_RM9000) ?
1250 (lsr & UART_LSR_THRE &&
1251 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1252 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
55d3b282
RK		 1253 transmit_chars(up);
1254 }
1da177e4 1255 }
e763b90c 1256
1da177e4 1257 /*
e763b90c 1258 * Re-enable the transmitter if we disabled it.
1da177e4 1259 */
e763b90c 1260 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1261 up->acr &= ~UART_ACR_TXDIS;
1262 serial_icr_write(up, UART_ACR, up->acr);
1263 }
1264}
1265
1266static void serial8250_stop_rx(struct uart_port *port)
1267{
1268 struct uart_8250_port *up = (struct uart_8250_port *)port;
1269
1270 up->ier &= ~UART_IER_RLSI;
1271 up->port.read_status_mask &= ~UART_LSR_DR;
1272 serial_out(up, UART_IER, up->ier);
1273}
1274
1275static void serial8250_enable_ms(struct uart_port *port)
1276{
1277 struct uart_8250_port *up = (struct uart_8250_port *)port;
1278
21c614a7
PA		 1279 /* no MSR capabilities */
1280 if (up->bugs & UART_BUG_NOMSR)
1281 return;
1282
1da177e4
LT		 1283 up->ier |= UART_IER_MSI;
1284 serial_out(up, UART_IER, up->ier);
1285}
1286
ea8874dc 1287static void
cc79aa9d 1288receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1289{
df4f4dd4 1290 struct tty_struct *tty = up->port.info->port.tty;
1da177e4
LT		 1291 unsigned char ch, lsr = *status;
1292 int max_count = 256;
1293 char flag;
1294
1295 do {
7500b1f6
AR		 1296 if (likely(lsr & UART_LSR_DR))
1297 ch = serial_inp(up, UART_RX);
1298 else
1299 /*
1300 * Intel 82571 has a Serial Over Lan device that will
1301 * set UART_LSR_BI without setting UART_LSR_DR when
1302 * it receives a break. To avoid reading from the
1303 * receive buffer without UART_LSR_DR bit set, we
1304 * just force the read character to be 0
1305 */
1306 ch = 0;
1307
1da177e4
LT		 1308 flag = TTY_NORMAL;
1309 up->port.icount.rx++;
1310
ad4c2aa6
CM		 1311 lsr |= up->lsr_saved_flags;
1312 up->lsr_saved_flags = 0;
1da177e4 1313
ad4c2aa6 1314 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1315 /*
1316 * For statistics only
1317 */
1318 if (lsr & UART_LSR_BI) {
1319 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1320 up->port.icount.brk++;
1321 /*
1322 * We do the SysRQ and SAK checking
1323 * here because otherwise the break
1324 * may get masked by ignore_status_mask
1325 * or read_status_mask.
1326 */
1327 if (uart_handle_break(&up->port))
1328 goto ignore_char;
1329 } else if (lsr & UART_LSR_PE)
1330 up->port.icount.parity++;
1331 else if (lsr & UART_LSR_FE)
1332 up->port.icount.frame++;
1333 if (lsr & UART_LSR_OE)
1334 up->port.icount.overrun++;
1335
1336 /*
23907eb8 1337 * Mask off conditions which should be ignored.
1da177e4
LT		 1338 */
1339 lsr &= up->port.read_status_mask;
1340
1341 if (lsr & UART_LSR_BI) {
1342 DEBUG_INTR("handling break....");
1343 flag = TTY_BREAK;
1344 } else if (lsr & UART_LSR_PE)
1345 flag = TTY_PARITY;
1346 else if (lsr & UART_LSR_FE)
1347 flag = TTY_FRAME;
1348 }
7d12e780 1349 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1350 goto ignore_char;
05ab3014
RK		 1351
1352 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1353
6f803cd0 1354ignore_char:
1da177e4 1355 lsr = serial_inp(up, UART_LSR);
7500b1f6 1356 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1357 spin_unlock(&up->port.lock);
1358 tty_flip_buffer_push(tty);
1359 spin_lock(&up->port.lock);
1360 *status = lsr;
1361}
1362
ea8874dc 1363static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1364{
1365 struct circ_buf *xmit = &up->port.info->xmit;
1366 int count;
1367
1368 if (up->port.x_char) {
1369 serial_outp(up, UART_TX, up->port.x_char);
1370 up->port.icount.tx++;
1371 up->port.x_char = 0;
1372 return;
1373 }
b129a8cc
RK		 1374 if (uart_tx_stopped(&up->port)) {
1375 serial8250_stop_tx(&up->port);
1376 return;
1377 }
1378 if (uart_circ_empty(xmit)) {
e763b90c 1379 __stop_tx(up);
1da177e4
LT		 1380 return;
1381 }
1382
1383 count = up->tx_loadsz;
1384 do {
1385 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1386 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1387 up->port.icount.tx++;
1388 if (uart_circ_empty(xmit))
1389 break;
1390 } while (--count > 0);
1391
1392 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1393 uart_write_wakeup(&up->port);
1394
1395 DEBUG_INTR("THRE...");
1396
1397 if (uart_circ_empty(xmit))
e763b90c 1398 __stop_tx(up);
1da177e4
LT		 1399}
1400
2af7cd68 1401static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1402{
2af7cd68
RK		 1403 unsigned int status = serial_in(up, UART_MSR);
1404
ad4c2aa6
CM		 1405 status |= up->msr_saved_flags;
1406 up->msr_saved_flags = 0;
fdc30b3d
TI		 1407 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1408 up->port.info != NULL) {
2af7cd68
RK		 1409 if (status & UART_MSR_TERI)
1410 up->port.icount.rng++;
1411 if (status & UART_MSR_DDSR)
1412 up->port.icount.dsr++;
1413 if (status & UART_MSR_DDCD)
1414 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1415 if (status & UART_MSR_DCTS)
1416 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1417
1418 wake_up_interruptible(&up->port.info->delta_msr_wait);
1419 }
1da177e4 1420
2af7cd68 1421 return status;
1da177e4
LT		 1422}
1423
1424/*
1425 * This handles the interrupt from one port.
1426 */
1427static inline void
7d12e780 1428serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1429{
45e24601 1430 unsigned int status;
4bf3631c 1431 unsigned long flags;
45e24601 1432
4bf3631c 1433 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1434
1435 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1436
1437 DEBUG_INTR("status = %x...", status);
1438
7500b1f6 1439 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1440 receive_chars(up, &status);
1da177e4
LT		 1441 check_modem_status(up);
1442 if (status & UART_LSR_THRE)
1443 transmit_chars(up);
45e24601 1444
4bf3631c 1445 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1446}
1447
1448/*
1449 * This is the serial driver's interrupt routine.
1450 *
1451 * Arjan thinks the old way was overly complex, so it got simplified.
1452 * Alan disagrees, saying that need the complexity to handle the weird
1453 * nature of ISA shared interrupts. (This is a special exception.)
1454 *
1455 * In order to handle ISA shared interrupts properly, we need to check
1456 * that all ports have been serviced, and therefore the ISA interrupt
1457 * line has been de-asserted.
1458 *
1459 * This means we need to loop through all ports. checking that they
1460 * don't have an interrupt pending.
1461 */
7d12e780 1462static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1463{
1464 struct irq_info *i = dev_id;
1465 struct list_head *l, *end = NULL;
1466 int pass_counter = 0, handled = 0;
1467
1468 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1469
1470 spin_lock(&i->lock);
1471
1472 l = i->head;
1473 do {
1474 struct uart_8250_port *up;
1475 unsigned int iir;
1476
1477 up = list_entry(l, struct uart_8250_port, list);
1478
1479 iir = serial_in(up, UART_IIR);
1480 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1481 serial8250_handle_port(up);
1da177e4
LT		 1482
1483 handled = 1;
1484
beab697a
MSJ		 1485 end = NULL;
1486 } else if (up->port.iotype == UPIO_DWAPB &&
1487 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1488 /* The DesignWare APB UART has an Busy Detect (0x07)
1489 * interrupt meaning an LCR write attempt occured while the
1490 * UART was busy. The interrupt must be cleared by reading
1491 * the UART status register (USR) and the LCR re-written. */
1492 unsigned int status;
1493 status = *(volatile u32 *)up->port.private_data;
1494 serial_out(up, UART_LCR, up->lcr);
1495
1496 handled = 1;
1497
1da177e4
LT		 1498 end = NULL;
1499 } else if (end == NULL)
1500 end = l;
1501
1502 l = l->next;
1503
1504 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1505 /* If we hit this, we're dead. */
1506 printk(KERN_ERR "serial8250: too much work for "
1507 "irq%d\n", irq);
1508 break;
1509 }
1510 } while (l != end);
1511
1512 spin_unlock(&i->lock);
1513
1514 DEBUG_INTR("end.\n");
1515
1516 return IRQ_RETVAL(handled);
1517}
1518
1519/*
1520 * To support ISA shared interrupts, we need to have one interrupt
1521 * handler that ensures that the IRQ line has been deasserted
1522 * before returning. Failing to do this will result in the IRQ
1523 * line being stuck active, and, since ISA irqs are edge triggered,
1524 * no more IRQs will be seen.
1525 */
1526static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1527{
1528 spin_lock_irq(&i->lock);
1529
1530 if (!list_empty(i->head)) {
1531 if (i->head == &up->list)
1532 i->head = i->head->next;
1533 list_del(&up->list);
1534 } else {
1535 BUG_ON(i->head != &up->list);
1536 i->head = NULL;
1537 }
1538
1539 spin_unlock_irq(&i->lock);
1540}
1541
1542static int serial_link_irq_chain(struct uart_8250_port *up)
1543{
1544 struct irq_info *i = irq_lists + up->port.irq;
40663cc7 1545 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4
LT		 1546
1547 spin_lock_irq(&i->lock);
1548
1549 if (i->head) {
1550 list_add(&up->list, i->head);
1551 spin_unlock_irq(&i->lock);
1552
1553 ret = 0;
1554 } else {
1555 INIT_LIST_HEAD(&up->list);
1556 i->head = &up->list;
1557 spin_unlock_irq(&i->lock);
1558
1559 ret = request_irq(up->port.irq, serial8250_interrupt,
1560 irq_flags, "serial", i);
1561 if (ret < 0)
1562 serial_do_unlink(i, up);
1563 }
1564
1565 return ret;
1566}
1567
1568static void serial_unlink_irq_chain(struct uart_8250_port *up)
1569{
1570 struct irq_info *i = irq_lists + up->port.irq;
1571
1572 BUG_ON(i->head == NULL);
1573
1574 if (list_empty(i->head))
1575 free_irq(up->port.irq, i);
1576
1577 serial_do_unlink(i, up);
1578}
1579
40b36daa
AW		 1580/* Base timer interval for polling */
1581static inline int poll_timeout(int timeout)
1582{
1583 return timeout > 6 ? (timeout / 2 - 2) : 1;
1584}
1585
1da177e4
LT		 1586/*
1587 * This function is used to handle ports that do not have an
1588 * interrupt. This doesn't work very well for 16450's, but gives
1589 * barely passable results for a 16550A. (Although at the expense
1590 * of much CPU overhead).
1591 */
1592static void serial8250_timeout(unsigned long data)
1593{
1594 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1595 unsigned int iir;
1596
1597 iir = serial_in(up, UART_IIR);
45e24601 1598 if (!(iir & UART_IIR_NO_INT))
7d12e780 1599 serial8250_handle_port(up);
40b36daa
AW		 1600 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1601}
1602
1603static void serial8250_backup_timeout(unsigned long data)
1604{
1605 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1606 unsigned int iir, ier = 0, lsr;
1607 unsigned long flags;
40b36daa
AW		 1608
1609 /*
1610 * Must disable interrupts or else we risk racing with the interrupt
1611 * based handler.
1612 */
1613 if (is_real_interrupt(up->port.irq)) {
1614 ier = serial_in(up, UART_IER);
1615 serial_out(up, UART_IER, 0);
1616 }
1da177e4 1617
40b36daa
AW		 1618 iir = serial_in(up, UART_IIR);
1619
1620 /*
1621 * This should be a safe test for anyone who doesn't trust the
1622 * IIR bits on their UART, but it's specifically designed for
1623 * the "Diva" UART used on the management processor on many HP
1624 * ia64 and parisc boxes.
1625 */
ad4c2aa6
CM		 1626 spin_lock_irqsave(&up->port.lock, flags);
1627 lsr = serial_in(up, UART_LSR);
1628 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1629 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 1630 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1631 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
ad4c2aa6 1632 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1633 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1634 iir |= UART_IIR_THRI;
1635 }
1636
1637 if (!(iir & UART_IIR_NO_INT))
1638 serial8250_handle_port(up);
1639
1640 if (is_real_interrupt(up->port.irq))
1641 serial_out(up, UART_IER, ier);
1642
1643 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0
AC		 1644 mod_timer(&up->timer,
1645 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1da177e4
LT		 1646}
1647
1648static unsigned int serial8250_tx_empty(struct uart_port *port)
1649{
1650 struct uart_8250_port *up = (struct uart_8250_port *)port;
1651 unsigned long flags;
ad4c2aa6 1652 unsigned int lsr;
1da177e4
LT		 1653
1654 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1655 lsr = serial_in(up, UART_LSR);
1656 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1657 spin_unlock_irqrestore(&up->port.lock, flags);
1658
ad4c2aa6 1659 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1da177e4
LT		 1660}
1661
1662static unsigned int serial8250_get_mctrl(struct uart_port *port)
1663{
1664 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1665 unsigned int status;
1da177e4
LT		 1666 unsigned int ret;
1667
2af7cd68 1668 status = check_modem_status(up);
1da177e4
LT		 1669
1670 ret = 0;
1671 if (status & UART_MSR_DCD)
1672 ret |= TIOCM_CAR;
1673 if (status & UART_MSR_RI)
1674 ret |= TIOCM_RNG;
1675 if (status & UART_MSR_DSR)
1676 ret |= TIOCM_DSR;
1677 if (status & UART_MSR_CTS)
1678 ret |= TIOCM_CTS;
1679 return ret;
1680}
1681
1682static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1683{
1684 struct uart_8250_port *up = (struct uart_8250_port *)port;
1685 unsigned char mcr = 0;
1686
1687 if (mctrl & TIOCM_RTS)
1688 mcr |= UART_MCR_RTS;
1689 if (mctrl & TIOCM_DTR)
1690 mcr |= UART_MCR_DTR;
1691 if (mctrl & TIOCM_OUT1)
1692 mcr |= UART_MCR_OUT1;
1693 if (mctrl & TIOCM_OUT2)
1694 mcr |= UART_MCR_OUT2;
1695 if (mctrl & TIOCM_LOOP)
1696 mcr |= UART_MCR_LOOP;
1697
1698 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1699
1700 serial_out(up, UART_MCR, mcr);
1701}
1702
1703static void serial8250_break_ctl(struct uart_port *port, int break_state)
1704{
1705 struct uart_8250_port *up = (struct uart_8250_port *)port;
1706 unsigned long flags;
1707
1708 spin_lock_irqsave(&up->port.lock, flags);
1709 if (break_state == -1)
1710 up->lcr |= UART_LCR_SBC;
1711 else
1712 up->lcr &= ~UART_LCR_SBC;
1713 serial_out(up, UART_LCR, up->lcr);
1714 spin_unlock_irqrestore(&up->port.lock, flags);
1715}
1716
40b36daa
AW		 1717#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1718
1719/*
1720 * Wait for transmitter & holding register to empty
1721 */
1722static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1723{
1724 unsigned int status, tmout = 10000;
1725
1726 /* Wait up to 10ms for the character(s) to be sent. */
1727 do {
1728 status = serial_in(up, UART_LSR);
1729
ad4c2aa6 1730 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa
AW		 1731
1732 if (--tmout == 0)
1733 break;
1734 udelay(1);
1735 } while ((status & bits) != bits);
1736
1737 /* Wait up to 1s for flow control if necessary */
1738 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1739 unsigned int tmout;
1740 for (tmout = 1000000; tmout; tmout--) {
1741 unsigned int msr = serial_in(up, UART_MSR);
1742 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1743 if (msr & UART_MSR_CTS)
1744 break;
40b36daa
AW		 1745 udelay(1);
1746 touch_nmi_watchdog();
1747 }
1748 }
1749}
1750
f2d937f3
JW		 1751#ifdef CONFIG_CONSOLE_POLL
1752/*
1753 * Console polling routines for writing and reading from the uart while
1754 * in an interrupt or debug context.
1755 */
1756
1757static int serial8250_get_poll_char(struct uart_port *port)
1758{
1759 struct uart_8250_port *up = (struct uart_8250_port *)port;
1760 unsigned char lsr = serial_inp(up, UART_LSR);
1761
1762 while (!(lsr & UART_LSR_DR))
1763 lsr = serial_inp(up, UART_LSR);
1764
1765 return serial_inp(up, UART_RX);
1766}
1767
1768
1769static void serial8250_put_poll_char(struct uart_port *port,
1770 unsigned char c)
1771{
1772 unsigned int ier;
1773 struct uart_8250_port *up = (struct uart_8250_port *)port;
1774
1775 /*
1776 * First save the IER then disable the interrupts
1777 */
1778 ier = serial_in(up, UART_IER);
1779 if (up->capabilities & UART_CAP_UUE)
1780 serial_out(up, UART_IER, UART_IER_UUE);
1781 else
1782 serial_out(up, UART_IER, 0);
1783
1784 wait_for_xmitr(up, BOTH_EMPTY);
1785 /*
1786 * Send the character out.
1787 * If a LF, also do CR...
1788 */
1789 serial_out(up, UART_TX, c);
1790 if (c == 10) {
1791 wait_for_xmitr(up, BOTH_EMPTY);
1792 serial_out(up, UART_TX, 13);
1793 }
1794
1795 /*
1796 * Finally, wait for transmitter to become empty
1797 * and restore the IER
1798 */
1799 wait_for_xmitr(up, BOTH_EMPTY);
1800 serial_out(up, UART_IER, ier);
1801}
1802
1803#endif /* CONFIG_CONSOLE_POLL */
1804
1da177e4
LT		 1805static int serial8250_startup(struct uart_port *port)
1806{
1807 struct uart_8250_port *up = (struct uart_8250_port *)port;
1808 unsigned long flags;
55d3b282 1809 unsigned char lsr, iir;
1da177e4
LT		 1810 int retval;
1811
1812 up->capabilities = uart_config[up->port.type].flags;
1813 up->mcr = 0;
1814
1815 if (up->port.type == PORT_16C950) {
1816 /* Wake up and initialize UART */
1817 up->acr = 0;
1818 serial_outp(up, UART_LCR, 0xBF);
1819 serial_outp(up, UART_EFR, UART_EFR_ECB);
1820 serial_outp(up, UART_IER, 0);
1821 serial_outp(up, UART_LCR, 0);
1822 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1823 serial_outp(up, UART_LCR, 0xBF);
1824 serial_outp(up, UART_EFR, UART_EFR_ECB);
1825 serial_outp(up, UART_LCR, 0);
1826 }
1827
1828#ifdef CONFIG_SERIAL_8250_RSA
1829 /*
1830 * If this is an RSA port, see if we can kick it up to the
1831 * higher speed clock.
1832 */
1833 enable_rsa(up);
1834#endif
1835
1836 /*
1837 * Clear the FIFO buffers and disable them.
7f927fcc 1838 * (they will be reenabled in set_termios())
1da177e4
LT		 1839 */
1840 serial8250_clear_fifos(up);
1841
1842 /*
1843 * Clear the interrupt registers.
1844 */
1845 (void) serial_inp(up, UART_LSR);
1846 (void) serial_inp(up, UART_RX);
1847 (void) serial_inp(up, UART_IIR);
1848 (void) serial_inp(up, UART_MSR);
1849
1850 /*
1851 * At this point, there's no way the LSR could still be 0xff;
1852 * if it is, then bail out, because there's likely no UART
1853 * here.
1854 */
1855 if (!(up->port.flags & UPF_BUGGY_UART) &&
1856 (serial_inp(up, UART_LSR) == 0xff)) {
1857 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1858 return -ENODEV;
1859 }
1860
1861 /*
1862 * For a XR16C850, we need to set the trigger levels
1863 */
1864 if (up->port.type == PORT_16850) {
1865 unsigned char fctr;
1866
1867 serial_outp(up, UART_LCR, 0xbf);
1868
1869 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1870 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1871 serial_outp(up, UART_TRG, UART_TRG_96);
1872 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1873 serial_outp(up, UART_TRG, UART_TRG_96);
1874
1875 serial_outp(up, UART_LCR, 0);
1876 }
1877
40b36daa 1878 if (is_real_interrupt(up->port.irq)) {
01c194d9 1879 unsigned char iir1;
40b36daa
AW		 1880 /*
1881 * Test for UARTs that do not reassert THRE when the
1882 * transmitter is idle and the interrupt has already
1883 * been cleared. Real 16550s should always reassert
1884 * this interrupt whenever the transmitter is idle and
1885 * the interrupt is enabled. Delays are necessary to
1886 * allow register changes to become visible.
1887 */
c389d27b 1888 spin_lock_irqsave(&up->port.lock, flags);
768aec0b
AV		 1889 if (up->port.flags & UPF_SHARE_IRQ)
1890 disable_irq_nosync(up->port.irq);
40b36daa
AW		 1891
1892 wait_for_xmitr(up, UART_LSR_THRE);
1893 serial_out_sync(up, UART_IER, UART_IER_THRI);
1894 udelay(1); /* allow THRE to set */
01c194d9 1895 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 1896 serial_out(up, UART_IER, 0);
1897 serial_out_sync(up, UART_IER, UART_IER_THRI);
1898 udelay(1); /* allow a working UART time to re-assert THRE */
1899 iir = serial_in(up, UART_IIR);
1900 serial_out(up, UART_IER, 0);
1901
768aec0b
AV		 1902 if (up->port.flags & UPF_SHARE_IRQ)
1903 enable_irq(up->port.irq);
c389d27b 1904 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 1905
1906 /*
1907 * If the interrupt is not reasserted, setup a timer to
1908 * kick the UART on a regular basis.
1909 */
01c194d9 1910 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 1911 up->bugs |= UART_BUG_THRE;
40b36daa 1912 pr_debug("ttyS%d - using backup timer\n", port->line);
40b36daa
AW		 1913 }
1914 }
1915
363f66fe
WN		 1916 /*
1917 * The above check will only give an accurate result the first time
1918 * the port is opened so this value needs to be preserved.
1919 */
1920 if (up->bugs & UART_BUG_THRE) {
1921 up->timer.function = serial8250_backup_timeout;
1922 up->timer.data = (unsigned long)up;
1923 mod_timer(&up->timer, jiffies +
1924 poll_timeout(up->port.timeout) + HZ / 5);
1925 }
1926
1da177e4
LT		 1927 /*
1928 * If the "interrupt" for this port doesn't correspond with any
1929 * hardware interrupt, we use a timer-based system. The original
1930 * driver used to do this with IRQ0.
1931 */
1932 if (!is_real_interrupt(up->port.irq)) {
1da177e4 1933 up->timer.data = (unsigned long)up;
40b36daa 1934 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 1935 } else {
1936 retval = serial_link_irq_chain(up);
1937 if (retval)
1938 return retval;
1939 }
1940
1941 /*
1942 * Now, initialize the UART
1943 */
1944 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1945
1946 spin_lock_irqsave(&up->port.lock, flags);
1947 if (up->port.flags & UPF_FOURPORT) {
1948 if (!is_real_interrupt(up->port.irq))
1949 up->port.mctrl |= TIOCM_OUT1;
1950 } else
1951 /*
1952 * Most PC uarts need OUT2 raised to enable interrupts.
1953 */
1954 if (is_real_interrupt(up->port.irq))
1955 up->port.mctrl |= TIOCM_OUT2;
1956
1957 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1958
1959 /*
1960 * Do a quick test to see if we receive an
1961 * interrupt when we enable the TX irq.
1962 */
1963 serial_outp(up, UART_IER, UART_IER_THRI);
1964 lsr = serial_in(up, UART_LSR);
1965 iir = serial_in(up, UART_IIR);
1966 serial_outp(up, UART_IER, 0);
1967
1968 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1969 if (!(up->bugs & UART_BUG_TXEN)) {
1970 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1971 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1972 port->line);
1973 }
1974 } else {
67f7654e 1975 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1976 }
1977
1da177e4
LT		 1978 spin_unlock_irqrestore(&up->port.lock, flags);
1979
ad4c2aa6
CM		 1980 /*
1981 * Clear the interrupt registers again for luck, and clear the
1982 * saved flags to avoid getting false values from polling
1983 * routines or the previous session.
1984 */
1985 serial_inp(up, UART_LSR);
1986 serial_inp(up, UART_RX);
1987 serial_inp(up, UART_IIR);
1988 serial_inp(up, UART_MSR);
1989 up->lsr_saved_flags = 0;
1990 up->msr_saved_flags = 0;
1991
1da177e4
LT		 1992 /*
1993 * Finally, enable interrupts. Note: Modem status interrupts
1994 * are set via set_termios(), which will be occurring imminently
1995 * anyway, so we don't enable them here.
1996 */
1997 up->ier = UART_IER_RLSI | UART_IER_RDI;
1998 serial_outp(up, UART_IER, up->ier);
1999
2000 if (up->port.flags & UPF_FOURPORT) {
2001 unsigned int icp;
2002 /*
2003 * Enable interrupts on the AST Fourport board
2004 */
2005 icp = (up->port.iobase & 0xfe0) | 0x01f;
2006 outb_p(0x80, icp);
2007 (void) inb_p(icp);
2008 }
2009
1da177e4
LT		 2010 return 0;
2011}
2012
2013static void serial8250_shutdown(struct uart_port *port)
2014{
2015 struct uart_8250_port *up = (struct uart_8250_port *)port;
2016 unsigned long flags;
2017
2018 /*
2019 * Disable interrupts from this port
2020 */
2021 up->ier = 0;
2022 serial_outp(up, UART_IER, 0);
2023
2024 spin_lock_irqsave(&up->port.lock, flags);
2025 if (up->port.flags & UPF_FOURPORT) {
2026 /* reset interrupts on the AST Fourport board */
2027 inb((up->port.iobase & 0xfe0) | 0x1f);
2028 up->port.mctrl |= TIOCM_OUT1;
2029 } else
2030 up->port.mctrl &= ~TIOCM_OUT2;
2031
2032 serial8250_set_mctrl(&up->port, up->port.mctrl);
2033 spin_unlock_irqrestore(&up->port.lock, flags);
2034
2035 /*
2036 * Disable break condition and FIFOs
2037 */
2038 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2039 serial8250_clear_fifos(up);
2040
2041#ifdef CONFIG_SERIAL_8250_RSA
2042 /*
2043 * Reset the RSA board back to 115kbps compat mode.
2044 */
2045 disable_rsa(up);
2046#endif
2047
2048 /*
2049 * Read data port to reset things, and then unlink from
2050 * the IRQ chain.
2051 */
2052 (void) serial_in(up, UART_RX);
2053
40b36daa
AW		 2054 del_timer_sync(&up->timer);
2055 up->timer.function = serial8250_timeout;
2056 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2057 serial_unlink_irq_chain(up);
2058}
2059
2060static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2061{
2062 unsigned int quot;
2063
2064 /*
2065 * Handle magic divisors for baud rates above baud_base on
2066 * SMSC SuperIO chips.
2067 */
2068 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2069 baud == (port->uartclk/4))
2070 quot = 0x8001;
2071 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2072 baud == (port->uartclk/8))
2073 quot = 0x8002;
2074 else
2075 quot = uart_get_divisor(port, baud);
2076
2077 return quot;
2078}
2079
2080static void
606d099c
AC		 2081serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2082 struct ktermios *old)
1da177e4
LT		 2083{
2084 struct uart_8250_port *up = (struct uart_8250_port *)port;
2085 unsigned char cval, fcr = 0;
2086 unsigned long flags;
2087 unsigned int baud, quot;
2088
2089 switch (termios->c_cflag & CSIZE) {
2090 case CS5:
0a8b80c5 2091 cval = UART_LCR_WLEN5;
1da177e4
LT		 2092 break;
2093 case CS6:
0a8b80c5 2094 cval = UART_LCR_WLEN6;
1da177e4
LT		 2095 break;
2096 case CS7:
0a8b80c5 2097 cval = UART_LCR_WLEN7;
1da177e4
LT		 2098 break;
2099 default:
2100 case CS8:
0a8b80c5 2101 cval = UART_LCR_WLEN8;
1da177e4
LT		 2102 break;
2103 }
2104
2105 if (termios->c_cflag & CSTOPB)
0a8b80c5 2106 cval |= UART_LCR_STOP;
1da177e4
LT		 2107 if (termios->c_cflag & PARENB)
2108 cval |= UART_LCR_PARITY;
2109 if (!(termios->c_cflag & PARODD))
2110 cval |= UART_LCR_EPAR;
2111#ifdef CMSPAR
2112 if (termios->c_cflag & CMSPAR)
2113 cval |= UART_LCR_SPAR;
2114#endif
2115
2116 /*
2117 * Ask the core to calculate the divisor for us.
2118 */
bd71c182 2119 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1da177e4
LT		 2120 quot = serial8250_get_divisor(port, baud);
2121
2122 /*
4ba5e35d 2123 * Oxford Semi 952 rev B workaround
1da177e4 2124 */
4ba5e35d 2125 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2126 quot++;
1da177e4
LT		 2127
2128 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2129 if (baud < 2400)
2130 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2131 else
2132 fcr = uart_config[up->port.type].fcr;
2133 }
2134
2135 /*
2136 * MCR-based auto flow control. When AFE is enabled, RTS will be
2137 * deasserted when the receive FIFO contains more characters than
2138 * the trigger, or the MCR RTS bit is cleared. In the case where
2139 * the remote UART is not using CTS auto flow control, we must
2140 * have sufficient FIFO entries for the latency of the remote
2141 * UART to respond. IOW, at least 32 bytes of FIFO.
2142 */
2143 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2144 up->mcr &= ~UART_MCR_AFE;
2145 if (termios->c_cflag & CRTSCTS)
2146 up->mcr |= UART_MCR_AFE;
2147 }
2148
2149 /*
2150 * Ok, we're now changing the port state. Do it with
2151 * interrupts disabled.
2152 */
2153 spin_lock_irqsave(&up->port.lock, flags);
2154
2155 /*
2156 * Update the per-port timeout.
2157 */
2158 uart_update_timeout(port, termios->c_cflag, baud);
2159
2160 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2161 if (termios->c_iflag & INPCK)
2162 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2163 if (termios->c_iflag & (BRKINT | PARMRK))
2164 up->port.read_status_mask |= UART_LSR_BI;
2165
2166 /*
2167 * Characteres to ignore
2168 */
2169 up->port.ignore_status_mask = 0;
2170 if (termios->c_iflag & IGNPAR)
2171 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2172 if (termios->c_iflag & IGNBRK) {
2173 up->port.ignore_status_mask |= UART_LSR_BI;
2174 /*
2175 * If we're ignoring parity and break indicators,
2176 * ignore overruns too (for real raw support).
2177 */
2178 if (termios->c_iflag & IGNPAR)
2179 up->port.ignore_status_mask |= UART_LSR_OE;
2180 }
2181
2182 /*
2183 * ignore all characters if CREAD is not set
2184 */
2185 if ((termios->c_cflag & CREAD) == 0)
2186 up->port.ignore_status_mask |= UART_LSR_DR;
2187
2188 /*
2189 * CTS flow control flag and modem status interrupts
2190 */
2191 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2192 if (!(up->bugs & UART_BUG_NOMSR) &&
2193 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2194 up->ier |= UART_IER_MSI;
2195 if (up->capabilities & UART_CAP_UUE)
2196 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2197
2198 serial_out(up, UART_IER, up->ier);
2199
2200 if (up->capabilities & UART_CAP_EFR) {
2201 unsigned char efr = 0;
2202 /*
2203 * TI16C752/Startech hardware flow control. FIXME:
2204 * - TI16C752 requires control thresholds to be set.
2205 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2206 */
2207 if (termios->c_cflag & CRTSCTS)
2208 efr |= UART_EFR_CTS;
2209
2210 serial_outp(up, UART_LCR, 0xBF);
2211 serial_outp(up, UART_EFR, efr);
2212 }
2213
255341c6
JM		 2214#ifdef CONFIG_ARCH_OMAP15XX
2215 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2216 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2217 if (baud == 115200) {
2218 quot = 1;
2219 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2220 } else
2221 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2222 }
2223#endif
2224
1da177e4
LT		 2225 if (up->capabilities & UART_NATSEMI) {
2226 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2227 serial_outp(up, UART_LCR, 0xe0);
2228 } else {
2229 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2230 }
2231
b32b19b8 2232 serial_dl_write(up, quot);
1da177e4
LT		 2233
2234 /*
2235 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2236 * is written without DLAB set, this mode will be disabled.
2237 */
2238 if (up->port.type == PORT_16750)
2239 serial_outp(up, UART_FCR, fcr);
2240
2241 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2242 up->lcr = cval; /* Save LCR */
2243 if (up->port.type != PORT_16750) {
2244 if (fcr & UART_FCR_ENABLE_FIFO) {
2245 /* emulated UARTs (Lucent Venus 167x) need two steps */
2246 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2247 }
2248 serial_outp(up, UART_FCR, fcr); /* set fcr */
2249 }
2250 serial8250_set_mctrl(&up->port, up->port.mctrl);
2251 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2252 /* Don't rewrite B0 */
2253 if (tty_termios_baud_rate(termios))
2254 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4
LT		 2255}
2256
2257static void
2258serial8250_pm(struct uart_port *port, unsigned int state,
2259 unsigned int oldstate)
2260{
2261 struct uart_8250_port *p = (struct uart_8250_port *)port;
2262
2263 serial8250_set_sleep(p, state != 0);
2264
2265 if (p->pm)
2266 p->pm(port, state, oldstate);
2267}
2268
2269/*
2270 * Resource handling.
2271 */
2272static int serial8250_request_std_resource(struct uart_8250_port *up)
2273{
2274 unsigned int size = 8 << up->port.regshift;
2275 int ret = 0;
2276
2277 switch (up->port.iotype) {
85835f44
SS		 2278 case UPIO_AU:
2279 size = 0x100000;
2280 /* fall thru */
0b30d668
SS		 2281 case UPIO_TSI:
2282 case UPIO_MEM32:
1da177e4 2283 case UPIO_MEM:
beab697a 2284 case UPIO_DWAPB:
1da177e4
LT		 2285 if (!up->port.mapbase)
2286 break;
2287
2288 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2289 ret = -EBUSY;
2290 break;
2291 }
2292
2293 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2294 up->port.membase = ioremap_nocache(up->port.mapbase,
2295 size);
1da177e4
LT		 2296 if (!up->port.membase) {
2297 release_mem_region(up->port.mapbase, size);
2298 ret = -ENOMEM;
2299 }
2300 }
2301 break;
2302
2303 case UPIO_HUB6:
2304 case UPIO_PORT:
2305 if (!request_region(up->port.iobase, size, "serial"))
2306 ret = -EBUSY;
2307 break;
2308 }
2309 return ret;
2310}
2311
2312static void serial8250_release_std_resource(struct uart_8250_port *up)
2313{
2314 unsigned int size = 8 << up->port.regshift;
2315
2316 switch (up->port.iotype) {
85835f44
SS		 2317 case UPIO_AU:
2318 size = 0x100000;
2319 /* fall thru */
0b30d668
SS		 2320 case UPIO_TSI:
2321 case UPIO_MEM32:
1da177e4 2322 case UPIO_MEM:
beab697a 2323 case UPIO_DWAPB:
1da177e4
LT		 2324 if (!up->port.mapbase)
2325 break;
2326
2327 if (up->port.flags & UPF_IOREMAP) {
2328 iounmap(up->port.membase);
2329 up->port.membase = NULL;
2330 }
2331
2332 release_mem_region(up->port.mapbase, size);
2333 break;
2334
2335 case UPIO_HUB6:
2336 case UPIO_PORT:
2337 release_region(up->port.iobase, size);
2338 break;
2339 }
2340}
2341
2342static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2343{
2344 unsigned long start = UART_RSA_BASE << up->port.regshift;
2345 unsigned int size = 8 << up->port.regshift;
0b30d668 2346 int ret = -EINVAL;
1da177e4
LT		 2347
2348 switch (up->port.iotype) {
1da177e4
LT		 2349 case UPIO_HUB6:
2350 case UPIO_PORT:
2351 start += up->port.iobase;
0b30d668
SS		 2352 if (request_region(start, size, "serial-rsa"))
2353 ret = 0;
2354 else
1da177e4
LT		 2355 ret = -EBUSY;
2356 break;
2357 }
2358
2359 return ret;
2360}
2361
2362static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2363{
2364 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2365 unsigned int size = 8 << up->port.regshift;
2366
2367 switch (up->port.iotype) {
1da177e4
LT		 2368 case UPIO_HUB6:
2369 case UPIO_PORT:
2370 release_region(up->port.iobase + offset, size);
2371 break;
2372 }
2373}
2374
2375static void serial8250_release_port(struct uart_port *port)
2376{
2377 struct uart_8250_port *up = (struct uart_8250_port *)port;
2378
2379 serial8250_release_std_resource(up);
2380 if (up->port.type == PORT_RSA)
2381 serial8250_release_rsa_resource(up);
2382}
2383
2384static int serial8250_request_port(struct uart_port *port)
2385{
2386 struct uart_8250_port *up = (struct uart_8250_port *)port;
2387 int ret = 0;
2388
2389 ret = serial8250_request_std_resource(up);
2390 if (ret == 0 && up->port.type == PORT_RSA) {
2391 ret = serial8250_request_rsa_resource(up);
2392 if (ret < 0)
2393 serial8250_release_std_resource(up);
2394 }
2395
2396 return ret;
2397}
2398
2399static void serial8250_config_port(struct uart_port *port, int flags)
2400{
2401 struct uart_8250_port *up = (struct uart_8250_port *)port;
2402 int probeflags = PROBE_ANY;
2403 int ret;
2404
1da177e4
LT		 2405 /*
2406 * Find the region that we can probe for. This in turn
2407 * tells us whether we can probe for the type of port.
2408 */
2409 ret = serial8250_request_std_resource(up);
2410 if (ret < 0)
2411 return;
2412
2413 ret = serial8250_request_rsa_resource(up);
2414 if (ret < 0)
2415 probeflags &= ~PROBE_RSA;
2416
2417 if (flags & UART_CONFIG_TYPE)
2418 autoconfig(up, probeflags);
2419 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2420 autoconfig_irq(up);
2421
2422 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2423 serial8250_release_rsa_resource(up);
2424 if (up->port.type == PORT_UNKNOWN)
2425 serial8250_release_std_resource(up);
2426}
2427
2428static int
2429serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2430{
2431 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2432 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2433 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2434 ser->type == PORT_STARTECH)
2435 return -EINVAL;
2436 return 0;
2437}
2438
2439static const char *
2440serial8250_type(struct uart_port *port)
2441{
2442 int type = port->type;
2443
2444 if (type >= ARRAY_SIZE(uart_config))
2445 type = 0;
2446 return uart_config[type].name;
2447}
2448
2449static struct uart_ops serial8250_pops = {
2450 .tx_empty = serial8250_tx_empty,
2451 .set_mctrl = serial8250_set_mctrl,
2452 .get_mctrl = serial8250_get_mctrl,
2453 .stop_tx = serial8250_stop_tx,
2454 .start_tx = serial8250_start_tx,
2455 .stop_rx = serial8250_stop_rx,
2456 .enable_ms = serial8250_enable_ms,
2457 .break_ctl = serial8250_break_ctl,
2458 .startup = serial8250_startup,
2459 .shutdown = serial8250_shutdown,
2460 .set_termios = serial8250_set_termios,
2461 .pm = serial8250_pm,
2462 .type = serial8250_type,
2463 .release_port = serial8250_release_port,
2464 .request_port = serial8250_request_port,
2465 .config_port = serial8250_config_port,
2466 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2467#ifdef CONFIG_CONSOLE_POLL
2468 .poll_get_char = serial8250_get_poll_char,
2469 .poll_put_char = serial8250_put_poll_char,
2470#endif
1da177e4
LT		 2471};
2472
2473static struct uart_8250_port serial8250_ports[UART_NR];
2474
2475static void __init serial8250_isa_init_ports(void)
2476{
2477 struct uart_8250_port *up;
2478 static int first = 1;
2479 int i;
2480
2481 if (!first)
2482 return;
2483 first = 0;
2484
a61c2d78 2485 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2486 struct uart_8250_port *up = &serial8250_ports[i];
2487
2488 up->port.line = i;
2489 spin_lock_init(&up->port.lock);
2490
2491 init_timer(&up->timer);
2492 up->timer.function = serial8250_timeout;
2493
2494 /*
2495 * ALPHA_KLUDGE_MCR needs to be killed.
2496 */
2497 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2498 up->mcr_force = ALPHA_KLUDGE_MCR;
2499
2500 up->port.ops = &serial8250_pops;
2501 }
2502
44454bcd 2503 for (i = 0, up = serial8250_ports;
a61c2d78 2504 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2505 i++, up++) {
2506 up->port.iobase = old_serial_port[i].port;
2507 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2508 up->port.uartclk = old_serial_port[i].baud_base * 16;
2509 up->port.flags = old_serial_port[i].flags;
2510 up->port.hub6 = old_serial_port[i].hub6;
2511 up->port.membase = old_serial_port[i].iomem_base;
2512 up->port.iotype = old_serial_port[i].io_type;
2513 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2514 if (share_irqs)
2515 up->port.flags |= UPF_SHARE_IRQ;
2516 }
2517}
2518
2519static void __init
2520serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2521{
2522 int i;
2523
2524 serial8250_isa_init_ports();
2525
a61c2d78 2526 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2527 struct uart_8250_port *up = &serial8250_ports[i];
2528
2529 up->port.dev = dev;
2530 uart_add_one_port(drv, &up->port);
2531 }
2532}
2533
2534#ifdef CONFIG_SERIAL_8250_CONSOLE
2535
d358788f
RK		 2536static void serial8250_console_putchar(struct uart_port *port, int ch)
2537{
2538 struct uart_8250_port *up = (struct uart_8250_port *)port;
2539
2540 wait_for_xmitr(up, UART_LSR_THRE);
2541 serial_out(up, UART_TX, ch);
2542}
2543
1da177e4
LT		 2544/*
2545 * Print a string to the serial port trying not to disturb
2546 * any possible real use of the port...
2547 *
2548 * The console_lock must be held when we get here.
2549 */
2550static void
2551serial8250_console_write(struct console *co, const char *s, unsigned int count)
2552{
2553 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2554 unsigned long flags;
1da177e4 2555 unsigned int ier;
d8a5a8d7 2556 int locked = 1;
1da177e4 2557
78512ece
AM		 2558 touch_nmi_watchdog();
2559
68aa2c0d
AM		 2560 local_irq_save(flags);
2561 if (up->port.sysrq) {
2562 /* serial8250_handle_port() already took the lock */
2563 locked = 0;
2564 } else if (oops_in_progress) {
2565 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2566 } else
68aa2c0d 2567 spin_lock(&up->port.lock);
d8a5a8d7 2568
1da177e4 2569 /*
dc7bf130 2570 * First save the IER then disable the interrupts
1da177e4
LT		 2571 */
2572 ier = serial_in(up, UART_IER);
2573
2574 if (up->capabilities & UART_CAP_UUE)
2575 serial_out(up, UART_IER, UART_IER_UUE);
2576 else
2577 serial_out(up, UART_IER, 0);
2578
d358788f 2579 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2580
2581 /*
2582 * Finally, wait for transmitter to become empty
2583 * and restore the IER
2584 */
f91a3715 2585 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2586 serial_out(up, UART_IER, ier);
d8a5a8d7 2587
ad4c2aa6
CM		 2588 /*
2589 * The receive handling will happen properly because the
2590 * receive ready bit will still be set; it is not cleared
2591 * on read. However, modem control will not, we must
2592 * call it if we have saved something in the saved flags
2593 * while processing with interrupts off.
2594 */
2595 if (up->msr_saved_flags)
2596 check_modem_status(up);
2597
d8a5a8d7 2598 if (locked)
68aa2c0d
AM		 2599 spin_unlock(&up->port.lock);
2600 local_irq_restore(flags);
1da177e4
LT		 2601}
2602
118c0ace 2603static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2604{
2605 struct uart_port *port;
2606 int baud = 9600;
2607 int bits = 8;
2608 int parity = 'n';
2609 int flow = 'n';
2610
2611 /*
2612 * Check whether an invalid uart number has been specified, and
2613 * if so, search for the first available port that does have
2614 * console support.
2615 */
a61c2d78 2616 if (co->index >= nr_uarts)
1da177e4
LT		 2617 co->index = 0;
2618 port = &serial8250_ports[co->index].port;
2619 if (!port->iobase && !port->membase)
2620 return -ENODEV;
2621
2622 if (options)
2623 uart_parse_options(options, &baud, &parity, &bits, &flow);
2624
2625 return uart_set_options(port, co, baud, parity, bits, flow);
2626}
2627
b6b1d877 2628static int serial8250_console_early_setup(void)
18a8bd94
YL		 2629{
2630 return serial8250_find_port_for_earlycon();
2631}
2632
1da177e4
LT		 2633static struct uart_driver serial8250_reg;
2634static struct console serial8250_console = {
2635 .name = "ttyS",
2636 .write = serial8250_console_write,
2637 .device = uart_console_device,
2638 .setup = serial8250_console_setup,
18a8bd94 2639 .early_setup = serial8250_console_early_setup,
1da177e4
LT		 2640 .flags = CON_PRINTBUFFER,
2641 .index = -1,
2642 .data = &serial8250_reg,
2643};
2644
2645static int __init serial8250_console_init(void)
2646{
05d81d22
EB		 2647 if (nr_uarts > UART_NR)
2648 nr_uarts = UART_NR;
2649
1da177e4
LT		 2650 serial8250_isa_init_ports();
2651 register_console(&serial8250_console);
2652 return 0;
2653}
2654console_initcall(serial8250_console_init);
2655
18a8bd94 2656int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2657{
2658 int line;
2659 struct uart_port *port;
2660
a61c2d78 2661 for (line = 0; line < nr_uarts; line++) {
1da177e4 2662 port = &serial8250_ports[line].port;
50aec3b5 2663 if (uart_match_port(p, port))
1da177e4
LT		 2664 return line;
2665 }
2666 return -ENODEV;
2667}
2668
1da177e4
LT		 2669#define SERIAL8250_CONSOLE &serial8250_console
2670#else
2671#define SERIAL8250_CONSOLE NULL
2672#endif
2673
2674static struct uart_driver serial8250_reg = {
2675 .owner = THIS_MODULE,
2676 .driver_name = "serial",
1da177e4
LT		 2677 .dev_name = "ttyS",
2678 .major = TTY_MAJOR,
2679 .minor = 64,
2680 .nr = UART_NR,
2681 .cons = SERIAL8250_CONSOLE,
2682};
2683
d856c666
RK		 2684/*
2685 * early_serial_setup - early registration for 8250 ports
2686 *
2687 * Setup an 8250 port structure prior to console initialisation. Use
2688 * after console initialisation will cause undefined behaviour.
2689 */
1da177e4
LT		 2690int __init early_serial_setup(struct uart_port *port)
2691{
2692 if (port->line >= ARRAY_SIZE(serial8250_ports))
2693 return -ENODEV;
2694
2695 serial8250_isa_init_ports();
2696 serial8250_ports[port->line].port = *port;
2697 serial8250_ports[port->line].port.ops = &serial8250_pops;
2698 return 0;
2699}
2700
2701/**
2702 * serial8250_suspend_port - suspend one serial port
2703 * @line: serial line number
1da177e4
LT		 2704 *
2705 * Suspend one serial port.
2706 */
2707void serial8250_suspend_port(int line)
2708{
2709 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2710}
2711
2712/**
2713 * serial8250_resume_port - resume one serial port
2714 * @line: serial line number
1da177e4
LT		 2715 *
2716 * Resume one serial port.
2717 */
2718void serial8250_resume_port(int line)
2719{
b5b82df6
DW		 2720 struct uart_8250_port *up = &serial8250_ports[line];
2721
2722 if (up->capabilities & UART_NATSEMI) {
2723 unsigned char tmp;
2724
2725 /* Ensure it's still in high speed mode */
2726 serial_outp(up, UART_LCR, 0xE0);
2727
2728 tmp = serial_in(up, 0x04); /* EXCR2 */
2729 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2730 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2731 serial_outp(up, 0x04, tmp);
2732
2733 serial_outp(up, UART_LCR, 0);
2734 }
2735 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 2736}
2737
2738/*
2739 * Register a set of serial devices attached to a platform device. The
2740 * list is terminated with a zero flags entry, which means we expect
2741 * all entries to have at least UPF_BOOT_AUTOCONF set.
2742 */
3ae5eaec 2743static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2744{
3ae5eaec 2745 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2746 struct uart_port port;
ec9f47cd 2747 int ret, i;
1da177e4
LT		 2748
2749 memset(&port, 0, sizeof(struct uart_port));
2750
ec9f47cd 2751 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2752 port.iobase = p->iobase;
2753 port.membase = p->membase;
2754 port.irq = p->irq;
2755 port.uartclk = p->uartclk;
2756 port.regshift = p->regshift;
2757 port.iotype = p->iotype;
2758 port.flags = p->flags;
2759 port.mapbase = p->mapbase;
2760 port.hub6 = p->hub6;
2761 port.private_data = p->private_data;
2762 port.dev = &dev->dev;
1da177e4
LT		 2763 if (share_irqs)
2764 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2765 ret = serial8250_register_port(&port);
2766 if (ret < 0) {
3ae5eaec 2767 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 2768 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2769 p->iobase, (unsigned long long)p->mapbase,
2770 p->irq, ret);
ec9f47cd 2771 }
1da177e4
LT		 2772 }
2773 return 0;
2774}
2775
2776/*
2777 * Remove serial ports registered against a platform device.
2778 */
3ae5eaec 2779static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2780{
2781 int i;
2782
a61c2d78 2783 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2784 struct uart_8250_port *up = &serial8250_ports[i];
2785
3ae5eaec 2786 if (up->port.dev == &dev->dev)
1da177e4
LT		 2787 serial8250_unregister_port(i);
2788 }
2789 return 0;
2790}
2791
3ae5eaec 2792static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2793{
2794 int i;
2795
1da177e4
LT		 2796 for (i = 0; i < UART_NR; i++) {
2797 struct uart_8250_port *up = &serial8250_ports[i];
2798
3ae5eaec 2799 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2800 uart_suspend_port(&serial8250_reg, &up->port);
2801 }
2802
2803 return 0;
2804}
2805
3ae5eaec 2806static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2807{
2808 int i;
2809
1da177e4
LT		 2810 for (i = 0; i < UART_NR; i++) {
2811 struct uart_8250_port *up = &serial8250_ports[i];
2812
3ae5eaec 2813 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 2814 serial8250_resume_port(i);
1da177e4
LT		 2815 }
2816
2817 return 0;
2818}
2819
3ae5eaec 2820static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2821 .probe = serial8250_probe,
2822 .remove = __devexit_p(serial8250_remove),
2823 .suspend = serial8250_suspend,
2824 .resume = serial8250_resume,
3ae5eaec
RK		 2825 .driver = {
2826 .name = "serial8250",
7493a314 2827 .owner = THIS_MODULE,
3ae5eaec 2828 },
1da177e4
LT		 2829};
2830
2831/*
2832 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2833 * in the table in include/asm/serial.h
2834 */
2835static struct platform_device *serial8250_isa_devs;
2836
2837/*
2838 * serial8250_register_port and serial8250_unregister_port allows for
2839 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2840 * modems and PCI multiport cards.
2841 */
f392ecfa 2842static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2843
2844static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2845{
2846 int i;
2847
2848 /*
2849 * First, find a port entry which matches.
2850 */
a61c2d78 2851 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2852 if (uart_match_port(&serial8250_ports[i].port, port))
2853 return &serial8250_ports[i];
2854
2855 /*
2856 * We didn't find a matching entry, so look for the first
2857 * free entry. We look for one which hasn't been previously
2858 * used (indicated by zero iobase).
2859 */
a61c2d78 2860 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2861 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2862 serial8250_ports[i].port.iobase == 0)
2863 return &serial8250_ports[i];
2864
2865 /*
2866 * That also failed. Last resort is to find any entry which
2867 * doesn't have a real port associated with it.
2868 */
a61c2d78 2869 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2870 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2871 return &serial8250_ports[i];
2872
2873 return NULL;
2874}
2875
2876/**
2877 * serial8250_register_port - register a serial port
2878 * @port: serial port template
2879 *
2880 * Configure the serial port specified by the request. If the
2881 * port exists and is in use, it is hung up and unregistered
2882 * first.
2883 *
2884 * The port is then probed and if necessary the IRQ is autodetected
2885 * If this fails an error is returned.
2886 *
2887 * On success the port is ready to use and the line number is returned.
2888 */
2889int serial8250_register_port(struct uart_port *port)
2890{
2891 struct uart_8250_port *uart;
2892 int ret = -ENOSPC;
2893
2894 if (port->uartclk == 0)
2895 return -EINVAL;
2896
f392ecfa 2897 mutex_lock(&serial_mutex);
1da177e4
LT		 2898
2899 uart = serial8250_find_match_or_unused(port);
2900 if (uart) {
2901 uart_remove_one_port(&serial8250_reg, &uart->port);
2902
74a19741
WN		 2903 uart->port.iobase = port->iobase;
2904 uart->port.membase = port->membase;
2905 uart->port.irq = port->irq;
2906 uart->port.uartclk = port->uartclk;
2907 uart->port.fifosize = port->fifosize;
2908 uart->port.regshift = port->regshift;
2909 uart->port.iotype = port->iotype;
2910 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2911 uart->port.mapbase = port->mapbase;
2912 uart->port.private_data = port->private_data;
1da177e4
LT		 2913 if (port->dev)
2914 uart->port.dev = port->dev;
2915
2916 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2917 if (ret == 0)
2918 ret = uart->port.line;
2919 }
f392ecfa 2920 mutex_unlock(&serial_mutex);
1da177e4
LT		 2921
2922 return ret;
2923}
2924EXPORT_SYMBOL(serial8250_register_port);
2925
2926/**
2927 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2928 * @line: serial line number
2929 *
2930 * Remove one serial port. This may not be called from interrupt
2931 * context. We hand the port back to the our control.
2932 */
2933void serial8250_unregister_port(int line)
2934{
2935 struct uart_8250_port *uart = &serial8250_ports[line];
2936
f392ecfa 2937 mutex_lock(&serial_mutex);
1da177e4
LT		 2938 uart_remove_one_port(&serial8250_reg, &uart->port);
2939 if (serial8250_isa_devs) {
2940 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2941 uart->port.type = PORT_UNKNOWN;
2942 uart->port.dev = &serial8250_isa_devs->dev;
2943 uart_add_one_port(&serial8250_reg, &uart->port);
2944 } else {
2945 uart->port.dev = NULL;
2946 }
f392ecfa 2947 mutex_unlock(&serial_mutex);
1da177e4
LT		 2948}
2949EXPORT_SYMBOL(serial8250_unregister_port);
2950
2951static int __init serial8250_init(void)
2952{
2953 int ret, i;
2954
a61c2d78
DJ		 2955 if (nr_uarts > UART_NR)
2956 nr_uarts = UART_NR;
2957
d87a6d95 2958 printk(KERN_INFO "Serial: 8250/16550 driver"
a61c2d78 2959 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2960 share_irqs ? "en" : "dis");
2961
2962 for (i = 0; i < NR_IRQS; i++)
2963 spin_lock_init(&irq_lists[i].lock);
2964
2965 ret = uart_register_driver(&serial8250_reg);
2966 if (ret)
2967 goto out;
2968
7493a314
DT		 2969 serial8250_isa_devs = platform_device_alloc("serial8250",
2970 PLAT8250_DEV_LEGACY);
2971 if (!serial8250_isa_devs) {
2972 ret = -ENOMEM;
bc965a7f 2973 goto unreg_uart_drv;
1da177e4
LT		 2974 }
2975
7493a314
DT		 2976 ret = platform_device_add(serial8250_isa_devs);
2977 if (ret)
2978 goto put_dev;
2979
1da177e4
LT		 2980 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2981
bc965a7f
RK		 2982 ret = platform_driver_register(&serial8250_isa_driver);
2983 if (ret == 0)
2984 goto out;
1da177e4 2985
bc965a7f 2986 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2987 put_dev:
2988 platform_device_put(serial8250_isa_devs);
7493a314 2989 unreg_uart_drv:
1da177e4
LT		 2990 uart_unregister_driver(&serial8250_reg);
2991 out:
2992 return ret;
2993}
2994
2995static void __exit serial8250_exit(void)
2996{
2997 struct platform_device *isa_dev = serial8250_isa_devs;
2998
2999 /*
3000 * This tells serial8250_unregister_port() not to re-register
3001 * the ports (thereby making serial8250_isa_driver permanently
3002 * in use.)
3003 */
3004 serial8250_isa_devs = NULL;
3005
3ae5eaec 3006 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3007 platform_device_unregister(isa_dev);
3008
3009 uart_unregister_driver(&serial8250_reg);
3010}
3011
3012module_init(serial8250_init);
3013module_exit(serial8250_exit);
3014
3015EXPORT_SYMBOL(serial8250_suspend_port);
3016EXPORT_SYMBOL(serial8250_resume_port);
3017
3018MODULE_LICENSE("GPL");
d87a6d95 3019MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3020
3021module_param(share_irqs, uint, 0644);
3022MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3023 " (unsafe)");
3024
a61c2d78
DJ		 3025module_param(nr_uarts, uint, 0644);
3026MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3027
1da177e4
LT		 3028#ifdef CONFIG_SERIAL_8250_RSA
3029module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3030MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3031#endif
3032MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
kernel source for telekom puls (alcatel/mediatek)