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Blackfin Serial Driver: fix error while transferring large files
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
1da177e4
LT		 15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
1da177e4
LT		 20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
1da177e4 31#include <linux/delay.h>
d052d1be 32#include <linux/platform_device.h>
1da177e4
LT		 33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_reg.h>
36#include <linux/serial_core.h>
37#include <linux/serial.h>
38#include <linux/serial_8250.h>
78512ece 39#include <linux/nmi.h>
f392ecfa 40#include <linux/mutex.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
b70ac771
DM		 47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
1da177e4
LT		 51/*
52 * Configuration:
40663cc7 53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
8440838b
DM		 60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
1da177e4
LT		 67/*
68 * Debugging.
69 */
70#if 0
71#define DEBUG_AUTOCONF(fmt...) printk(fmt)
72#else
73#define DEBUG_AUTOCONF(fmt...) do { } while (0)
74#endif
75
76#if 0
77#define DEBUG_INTR(fmt...) printk(fmt)
78#else
79#define DEBUG_INTR(fmt...) do { } while (0)
80#endif
81
82#define PASS_LIMIT 256
83
84/*
85 * We default to IRQ0 for the "no irq" hack. Some
86 * machine types want others as well - they're free
87 * to redefine this in their header file.
88 */
89#define is_real_interrupt(irq) ((irq) != 0)
90
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92#define CONFIG_SERIAL_DETECT_IRQ 1
93#endif
1da177e4
LT		 94#ifdef CONFIG_SERIAL_8250_MANY_PORTS
95#define CONFIG_SERIAL_MANY_PORTS 1
96#endif
97
98/*
99 * HUB6 is always on. This will be removed once the header
100 * files have been cleaned.
101 */
102#define CONFIG_HUB6 1
103
a4ed1e41 104#include <asm/serial.h>
1da177e4
LT		 105/*
106 * SERIAL_PORT_DFNS tells us about built-in ports that have no
107 * standard enumeration mechanism. Platforms that can find all
108 * serial ports via mechanisms like ACPI or PCI need not supply it.
109 */
110#ifndef SERIAL_PORT_DFNS
111#define SERIAL_PORT_DFNS
112#endif
113
cb3592be 114static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 115 SERIAL_PORT_DFNS /* defined in asm/serial.h */
116};
117
026d02a2 118#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 119
120#ifdef CONFIG_SERIAL_8250_RSA
121
122#define PORT_RSA_MAX 4
123static unsigned long probe_rsa[PORT_RSA_MAX];
124static unsigned int probe_rsa_count;
125#endif /* CONFIG_SERIAL_8250_RSA */
126
127struct uart_8250_port {
128 struct uart_port port;
129 struct timer_list timer; /* "no irq" timer */
130 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 131 unsigned short capabilities; /* port capabilities */
132 unsigned short bugs; /* port bugs */
1da177e4 133 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 134 unsigned char acr;
135 unsigned char ier;
136 unsigned char lcr;
137 unsigned char mcr;
138 unsigned char mcr_mask; /* mask of user bits */
139 unsigned char mcr_force; /* mask of forced bits */
b8e7e40a 140 unsigned char cur_iotype; /* Running I/O type */
ad4c2aa6
CM		 141
142 /*
143 * Some bits in registers are cleared on a read, so they must
144 * be saved whenever the register is read but the bits will not
145 * be immediately processed.
146 */
147#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
148 unsigned char lsr_saved_flags;
149#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
150 unsigned char msr_saved_flags;
1da177e4
LT		 151
152 /*
153 * We provide a per-port pm hook.
154 */
155 void (*pm)(struct uart_port *port,
156 unsigned int state, unsigned int old);
157};
158
159struct irq_info {
25db8ad5
AC		 160 struct hlist_node node;
161 int irq;
162 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 163 struct list_head *head;
164};
165
25db8ad5
AC		 166#define NR_IRQ_HASH 32 /* Can be adjusted later */
167static struct hlist_head irq_lists[NR_IRQ_HASH];
168static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 169
170/*
171 * Here we define the default xmit fifo size used for each type of UART.
172 */
173static const struct serial8250_config uart_config[] = {
174 [PORT_UNKNOWN] = {
175 .name = "unknown",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_8250] = {
180 .name = "8250",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16450] = {
185 .name = "16450",
186 .fifo_size = 1,
187 .tx_loadsz = 1,
188 },
189 [PORT_16550] = {
190 .name = "16550",
191 .fifo_size = 1,
192 .tx_loadsz = 1,
193 },
194 [PORT_16550A] = {
195 .name = "16550A",
196 .fifo_size = 16,
197 .tx_loadsz = 16,
198 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
199 .flags = UART_CAP_FIFO,
200 },
201 [PORT_CIRRUS] = {
202 .name = "Cirrus",
203 .fifo_size = 1,
204 .tx_loadsz = 1,
205 },
206 [PORT_16650] = {
207 .name = "ST16650",
208 .fifo_size = 1,
209 .tx_loadsz = 1,
210 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
211 },
212 [PORT_16650V2] = {
213 .name = "ST16650V2",
214 .fifo_size = 32,
215 .tx_loadsz = 16,
216 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
217 UART_FCR_T_TRIG_00,
218 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
219 },
220 [PORT_16750] = {
221 .name = "TI16750",
222 .fifo_size = 64,
223 .tx_loadsz = 64,
224 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
225 UART_FCR7_64BYTE,
226 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
227 },
228 [PORT_STARTECH] = {
229 .name = "Startech",
230 .fifo_size = 1,
231 .tx_loadsz = 1,
232 },
233 [PORT_16C950] = {
234 .name = "16C950/954",
235 .fifo_size = 128,
236 .tx_loadsz = 128,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO,
239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE,
275 },
bd71c182
TK		 276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 288 .flags = UART_CAP_FIFO,
289 },
08e0992f
FF		 290 [PORT_AR7] = {
291 .name = "AR7",
292 .fifo_size = 16,
293 .tx_loadsz = 16,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
296 },
1da177e4
LT		 297};
298
bd71c182 299#if defined (CONFIG_SERIAL_8250_AU1X00)
21c614a7
PA		 300
301/* Au1x00 UART hardware has a weird register layout */
302static const u8 au_io_in_map[] = {
303 [UART_RX] = 0,
304 [UART_IER] = 2,
305 [UART_IIR] = 3,
306 [UART_LCR] = 5,
307 [UART_MCR] = 6,
308 [UART_LSR] = 7,
309 [UART_MSR] = 8,
310};
311
312static const u8 au_io_out_map[] = {
313 [UART_TX] = 1,
314 [UART_IER] = 2,
315 [UART_FCR] = 4,
316 [UART_LCR] = 5,
317 [UART_MCR] = 6,
318};
319
320/* sane hardware needs no mapping */
7d6a07d1 321static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 322{
7d6a07d1 323 if (p->iotype != UPIO_AU)
21c614a7
PA		 324 return offset;
325 return au_io_in_map[offset];
326}
327
7d6a07d1 328static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 329{
7d6a07d1 330 if (p->iotype != UPIO_AU)
21c614a7
PA		 331 return offset;
332 return au_io_out_map[offset];
333}
334
6f803cd0 335#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 336
337static const u8
338 regmap_in[8] = {
339 [UART_RX] = 0x00,
340 [UART_IER] = 0x0c,
341 [UART_IIR] = 0x14,
342 [UART_LCR] = 0x1c,
343 [UART_MCR] = 0x20,
344 [UART_LSR] = 0x24,
345 [UART_MSR] = 0x28,
346 [UART_SCR] = 0x2c
347 },
348 regmap_out[8] = {
349 [UART_TX] = 0x04,
350 [UART_IER] = 0x0c,
351 [UART_FCR] = 0x18,
352 [UART_LCR] = 0x1c,
353 [UART_MCR] = 0x20,
354 [UART_LSR] = 0x24,
355 [UART_MSR] = 0x28,
356 [UART_SCR] = 0x2c
357 };
358
7d6a07d1 359static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 360{
7d6a07d1 361 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 362 return offset;
363 return regmap_in[offset];
364}
365
7d6a07d1 366static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 367{
7d6a07d1 368 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 369 return offset;
370 return regmap_out[offset];
371}
372
21c614a7
PA		 373#else
374
375/* sane hardware needs no mapping */
376#define map_8250_in_reg(up, offset) (offset)
377#define map_8250_out_reg(up, offset) (offset)
378
379#endif
380
7d6a07d1 381static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 382{
7d6a07d1
DD		 383 offset = map_8250_in_reg(p, offset) << p->regshift;
384 outb(p->hub6 - 1 + offset, p->iobase);
385 return inb(p->iobase + 1);
386}
1da177e4 387
7d6a07d1
DD		 388static void hub6_serial_out(struct uart_port *p, int offset, int value)
389{
390 offset = map_8250_out_reg(p, offset) << p->regshift;
391 outb(p->hub6 - 1 + offset, p->iobase);
392 outb(value, p->iobase + 1);
393}
1da177e4 394
7d6a07d1
DD		 395static unsigned int mem_serial_in(struct uart_port *p, int offset)
396{
397 offset = map_8250_in_reg(p, offset) << p->regshift;
398 return readb(p->membase + offset);
399}
1da177e4 400
7d6a07d1
DD		 401static void mem_serial_out(struct uart_port *p, int offset, int value)
402{
403 offset = map_8250_out_reg(p, offset) << p->regshift;
404 writeb(value, p->membase + offset);
405}
406
407static void mem32_serial_out(struct uart_port *p, int offset, int value)
408{
409 offset = map_8250_out_reg(p, offset) << p->regshift;
410 writel(value, p->membase + offset);
411}
412
413static unsigned int mem32_serial_in(struct uart_port *p, int offset)
414{
415 offset = map_8250_in_reg(p, offset) << p->regshift;
416 return readl(p->membase + offset);
417}
1da177e4 418
21c614a7 419#ifdef CONFIG_SERIAL_8250_AU1X00
7d6a07d1
DD		 420static unsigned int au_serial_in(struct uart_port *p, int offset)
421{
422 offset = map_8250_in_reg(p, offset) << p->regshift;
423 return __raw_readl(p->membase + offset);
424}
425
426static void au_serial_out(struct uart_port *p, int offset, int value)
427{
428 offset = map_8250_out_reg(p, offset) << p->regshift;
429 __raw_writel(value, p->membase + offset);
430}
21c614a7
PA		 431#endif
432
7d6a07d1
DD		 433static unsigned int tsi_serial_in(struct uart_port *p, int offset)
434{
435 unsigned int tmp;
436 offset = map_8250_in_reg(p, offset) << p->regshift;
437 if (offset == UART_IIR) {
438 tmp = readl(p->membase + (UART_IIR & ~3));
439 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
440 } else
441 return readb(p->membase + offset);
442}
3be91ec7 443
7d6a07d1
DD		 444static void tsi_serial_out(struct uart_port *p, int offset, int value)
445{
446 offset = map_8250_out_reg(p, offset) << p->regshift;
447 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
448 writeb(value, p->membase + offset);
1da177e4
LT		 449}
450
7d6a07d1 451static void dwapb_serial_out(struct uart_port *p, int offset, int value)
1da177e4 452{
beab697a 453 int save_offset = offset;
7d6a07d1
DD		 454 offset = map_8250_out_reg(p, offset) << p->regshift;
455 /* Save the LCR value so it can be re-written when a
456 * Busy Detect interrupt occurs. */
457 if (save_offset == UART_LCR) {
458 struct uart_8250_port *up = (struct uart_8250_port *)p;
459 up->lcr = value;
460 }
461 writeb(value, p->membase + offset);
462 /* Read the IER to ensure any interrupt is cleared before
463 * returning from ISR. */
464 if (save_offset == UART_TX || save_offset == UART_IER)
465 value = p->serial_in(p, UART_IER);
466}
1da177e4 467
7d6a07d1
DD		 468static unsigned int io_serial_in(struct uart_port *p, int offset)
469{
470 offset = map_8250_in_reg(p, offset) << p->regshift;
471 return inb(p->iobase + offset);
472}
473
474static void io_serial_out(struct uart_port *p, int offset, int value)
475{
476 offset = map_8250_out_reg(p, offset) << p->regshift;
477 outb(value, p->iobase + offset);
478}
479
480static void set_io_from_upio(struct uart_port *p)
481{
b8e7e40a 482 struct uart_8250_port *up = (struct uart_8250_port *)p;
7d6a07d1 483 switch (p->iotype) {
1da177e4 484 case UPIO_HUB6:
7d6a07d1
DD		 485 p->serial_in = hub6_serial_in;
486 p->serial_out = hub6_serial_out;
1da177e4
LT		 487 break;
488
489 case UPIO_MEM:
7d6a07d1
DD		 490 p->serial_in = mem_serial_in;
491 p->serial_out = mem_serial_out;
1da177e4
LT		 492 break;
493
bd71c182 494 case UPIO_RM9000:
1da177e4 495 case UPIO_MEM32:
7d6a07d1
DD		 496 p->serial_in = mem32_serial_in;
497 p->serial_out = mem32_serial_out;
1da177e4
LT		 498 break;
499
21c614a7
PA		 500#ifdef CONFIG_SERIAL_8250_AU1X00
501 case UPIO_AU:
7d6a07d1
DD		 502 p->serial_in = au_serial_in;
503 p->serial_out = au_serial_out;
21c614a7
PA		 504 break;
505#endif
3be91ec7 506 case UPIO_TSI:
7d6a07d1
DD		 507 p->serial_in = tsi_serial_in;
508 p->serial_out = tsi_serial_out;
3be91ec7 509 break;
21c614a7 510
beab697a 511 case UPIO_DWAPB:
7d6a07d1
DD		 512 p->serial_in = mem_serial_in;
513 p->serial_out = dwapb_serial_out;
beab697a
MSJ		 514 break;
515
1da177e4 516 default:
7d6a07d1
DD		 517 p->serial_in = io_serial_in;
518 p->serial_out = io_serial_out;
519 break;
1da177e4 520 }
b8e7e40a
AC		 521 /* Remember loaded iotype */
522 up->cur_iotype = p->iotype;
1da177e4
LT		 523}
524
40b36daa
AW		 525static void
526serial_out_sync(struct uart_8250_port *up, int offset, int value)
527{
7d6a07d1
DD		 528 struct uart_port *p = &up->port;
529 switch (p->iotype) {
40b36daa
AW		 530 case UPIO_MEM:
531 case UPIO_MEM32:
532#ifdef CONFIG_SERIAL_8250_AU1X00
533 case UPIO_AU:
534#endif
beab697a 535 case UPIO_DWAPB:
7d6a07d1
DD		 536 p->serial_out(p, offset, value);
537 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 538 break;
539 default:
7d6a07d1 540 p->serial_out(p, offset, value);
40b36daa
AW		 541 }
542}
543
7d6a07d1
DD		 544#define serial_in(up, offset) \
545 (up->port.serial_in(&(up)->port, (offset)))
546#define serial_out(up, offset, value) \
547 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 548/*
549 * We used to support using pause I/O for certain machines. We
550 * haven't supported this for a while, but just in case it's badly
551 * needed for certain old 386 machines, I've left these #define's
552 * in....
553 */
554#define serial_inp(up, offset) serial_in(up, offset)
555#define serial_outp(up, offset, value) serial_out(up, offset, value)
556
b32b19b8
JAH		 557/* Uart divisor latch read */
558static inline int _serial_dl_read(struct uart_8250_port *up)
559{
560 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
561}
562
563/* Uart divisor latch write */
564static inline void _serial_dl_write(struct uart_8250_port *up, int value)
565{
566 serial_outp(up, UART_DLL, value & 0xff);
567 serial_outp(up, UART_DLM, value >> 8 & 0xff);
568}
569
6f803cd0 570#if defined(CONFIG_SERIAL_8250_AU1X00)
b32b19b8
JAH		 571/* Au1x00 haven't got a standard divisor latch */
572static int serial_dl_read(struct uart_8250_port *up)
573{
574 if (up->port.iotype == UPIO_AU)
575 return __raw_readl(up->port.membase + 0x28);
576 else
577 return _serial_dl_read(up);
578}
579
580static void serial_dl_write(struct uart_8250_port *up, int value)
581{
582 if (up->port.iotype == UPIO_AU)
583 __raw_writel(value, up->port.membase + 0x28);
584 else
585 _serial_dl_write(up, value);
586}
6f803cd0 587#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 588static int serial_dl_read(struct uart_8250_port *up)
589{
590 return (up->port.iotype == UPIO_RM9000) ?
591 (((__raw_readl(up->port.membase + 0x10) << 8) |
592 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
593 _serial_dl_read(up);
594}
595
596static void serial_dl_write(struct uart_8250_port *up, int value)
597{
598 if (up->port.iotype == UPIO_RM9000) {
599 __raw_writel(value, up->port.membase + 0x08);
600 __raw_writel(value >> 8, up->port.membase + 0x10);
601 } else {
602 _serial_dl_write(up, value);
603 }
604}
b32b19b8
JAH		 605#else
606#define serial_dl_read(up) _serial_dl_read(up)
607#define serial_dl_write(up, value) _serial_dl_write(up, value)
608#endif
1da177e4
LT		 609
610/*
611 * For the 16C950
612 */
613static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
614{
615 serial_out(up, UART_SCR, offset);
616 serial_out(up, UART_ICR, value);
617}
618
619static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
620{
621 unsigned int value;
622
623 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
624 serial_out(up, UART_SCR, offset);
625 value = serial_in(up, UART_ICR);
626 serial_icr_write(up, UART_ACR, up->acr);
627
628 return value;
629}
630
631/*
632 * FIFO support.
633 */
b5d674ab 634static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 635{
636 if (p->capabilities & UART_CAP_FIFO) {
637 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
638 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
639 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
640 serial_outp(p, UART_FCR, 0);
641 }
642}
643
644/*
645 * IER sleep support. UARTs which have EFRs need the "extended
646 * capability" bit enabled. Note that on XR16C850s, we need to
647 * reset LCR to write to IER.
648 */
b5d674ab 649static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 650{
651 if (p->capabilities & UART_CAP_SLEEP) {
652 if (p->capabilities & UART_CAP_EFR) {
653 serial_outp(p, UART_LCR, 0xBF);
654 serial_outp(p, UART_EFR, UART_EFR_ECB);
655 serial_outp(p, UART_LCR, 0);
656 }
657 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
658 if (p->capabilities & UART_CAP_EFR) {
659 serial_outp(p, UART_LCR, 0xBF);
660 serial_outp(p, UART_EFR, 0);
661 serial_outp(p, UART_LCR, 0);
662 }
663 }
664}
665
666#ifdef CONFIG_SERIAL_8250_RSA
667/*
668 * Attempts to turn on the RSA FIFO. Returns zero on failure.
669 * We set the port uart clock rate if we succeed.
670 */
671static int __enable_rsa(struct uart_8250_port *up)
672{
673 unsigned char mode;
674 int result;
675
676 mode = serial_inp(up, UART_RSA_MSR);
677 result = mode & UART_RSA_MSR_FIFO;
678
679 if (!result) {
680 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
681 mode = serial_inp(up, UART_RSA_MSR);
682 result = mode & UART_RSA_MSR_FIFO;
683 }
684
685 if (result)
686 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
687
688 return result;
689}
690
691static void enable_rsa(struct uart_8250_port *up)
692{
693 if (up->port.type == PORT_RSA) {
694 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
695 spin_lock_irq(&up->port.lock);
696 __enable_rsa(up);
697 spin_unlock_irq(&up->port.lock);
698 }
699 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
700 serial_outp(up, UART_RSA_FRR, 0);
701 }
702}
703
704/*
705 * Attempts to turn off the RSA FIFO. Returns zero on failure.
706 * It is unknown why interrupts were disabled in here. However,
707 * the caller is expected to preserve this behaviour by grabbing
708 * the spinlock before calling this function.
709 */
710static void disable_rsa(struct uart_8250_port *up)
711{
712 unsigned char mode;
713 int result;
714
715 if (up->port.type == PORT_RSA &&
716 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
717 spin_lock_irq(&up->port.lock);
718
719 mode = serial_inp(up, UART_RSA_MSR);
720 result = !(mode & UART_RSA_MSR_FIFO);
721
722 if (!result) {
723 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
724 mode = serial_inp(up, UART_RSA_MSR);
725 result = !(mode & UART_RSA_MSR_FIFO);
726 }
727
728 if (result)
729 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
730 spin_unlock_irq(&up->port.lock);
731 }
732}
733#endif /* CONFIG_SERIAL_8250_RSA */
734
735/*
736 * This is a quickie test to see how big the FIFO is.
737 * It doesn't work at all the time, more's the pity.
738 */
739static int size_fifo(struct uart_8250_port *up)
740{
b32b19b8
JAH		 741 unsigned char old_fcr, old_mcr, old_lcr;
742 unsigned short old_dl;
1da177e4
LT		 743 int count;
744
745 old_lcr = serial_inp(up, UART_LCR);
746 serial_outp(up, UART_LCR, 0);
747 old_fcr = serial_inp(up, UART_FCR);
748 old_mcr = serial_inp(up, UART_MCR);
749 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
750 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
751 serial_outp(up, UART_MCR, UART_MCR_LOOP);
752 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 753 old_dl = serial_dl_read(up);
754 serial_dl_write(up, 0x0001);
1da177e4
LT		 755 serial_outp(up, UART_LCR, 0x03);
756 for (count = 0; count < 256; count++)
757 serial_outp(up, UART_TX, count);
758 mdelay(20);/* FIXME - schedule_timeout */
759 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
760 (count < 256); count++)
761 serial_inp(up, UART_RX);
762 serial_outp(up, UART_FCR, old_fcr);
763 serial_outp(up, UART_MCR, old_mcr);
764 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 765 serial_dl_write(up, old_dl);
1da177e4
LT		 766 serial_outp(up, UART_LCR, old_lcr);
767
768 return count;
769}
770
771/*
772 * Read UART ID using the divisor method - set DLL and DLM to zero
773 * and the revision will be in DLL and device type in DLM. We
774 * preserve the device state across this.
775 */
776static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
777{
778 unsigned char old_dll, old_dlm, old_lcr;
779 unsigned int id;
780
781 old_lcr = serial_inp(p, UART_LCR);
782 serial_outp(p, UART_LCR, UART_LCR_DLAB);
783
784 old_dll = serial_inp(p, UART_DLL);
785 old_dlm = serial_inp(p, UART_DLM);
786
787 serial_outp(p, UART_DLL, 0);
788 serial_outp(p, UART_DLM, 0);
789
790 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
791
792 serial_outp(p, UART_DLL, old_dll);
793 serial_outp(p, UART_DLM, old_dlm);
794 serial_outp(p, UART_LCR, old_lcr);
795
796 return id;
797}
798
799/*
800 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
801 * When this function is called we know it is at least a StarTech
802 * 16650 V2, but it might be one of several StarTech UARTs, or one of
803 * its clones. (We treat the broken original StarTech 16650 V1 as a
804 * 16550, and why not? Startech doesn't seem to even acknowledge its
805 * existence.)
bd71c182 806 *
1da177e4
LT		 807 * What evil have men's minds wrought...
808 */
809static void autoconfig_has_efr(struct uart_8250_port *up)
810{
811 unsigned int id1, id2, id3, rev;
812
813 /*
814 * Everything with an EFR has SLEEP
815 */
816 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
817
818 /*
819 * First we check to see if it's an Oxford Semiconductor UART.
820 *
821 * If we have to do this here because some non-National
822 * Semiconductor clone chips lock up if you try writing to the
823 * LSR register (which serial_icr_read does)
824 */
825
826 /*
827 * Check for Oxford Semiconductor 16C950.
828 *
829 * EFR [4] must be set else this test fails.
830 *
831 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
832 * claims that it's needed for 952 dual UART's (which are not
833 * recommended for new designs).
834 */
835 up->acr = 0;
836 serial_out(up, UART_LCR, 0xBF);
837 serial_out(up, UART_EFR, UART_EFR_ECB);
838 serial_out(up, UART_LCR, 0x00);
839 id1 = serial_icr_read(up, UART_ID1);
840 id2 = serial_icr_read(up, UART_ID2);
841 id3 = serial_icr_read(up, UART_ID3);
842 rev = serial_icr_read(up, UART_REV);
843
844 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
845
846 if (id1 == 0x16 && id2 == 0xC9 &&
847 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
848 up->port.type = PORT_16C950;
4ba5e35d
RK		 849
850 /*
851 * Enable work around for the Oxford Semiconductor 952 rev B
852 * chip which causes it to seriously miscalculate baud rates
853 * when DLL is 0.
854 */
855 if (id3 == 0x52 && rev == 0x01)
856 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 857 return;
858 }
bd71c182 859
1da177e4
LT		 860 /*
861 * We check for a XR16C850 by setting DLL and DLM to 0, and then
862 * reading back DLL and DLM. The chip type depends on the DLM
863 * value read back:
864 * 0x10 - XR16C850 and the DLL contains the chip revision.
865 * 0x12 - XR16C2850.
866 * 0x14 - XR16C854.
867 */
868 id1 = autoconfig_read_divisor_id(up);
869 DEBUG_AUTOCONF("850id=%04x ", id1);
870
871 id2 = id1 >> 8;
872 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 873 up->port.type = PORT_16850;
874 return;
875 }
876
877 /*
878 * It wasn't an XR16C850.
879 *
880 * We distinguish between the '654 and the '650 by counting
881 * how many bytes are in the FIFO. I'm using this for now,
882 * since that's the technique that was sent to me in the
883 * serial driver update, but I'm not convinced this works.
884 * I've had problems doing this in the past. -TYT
885 */
886 if (size_fifo(up) == 64)
887 up->port.type = PORT_16654;
888 else
889 up->port.type = PORT_16650V2;
890}
891
892/*
893 * We detected a chip without a FIFO. Only two fall into
894 * this category - the original 8250 and the 16450. The
895 * 16450 has a scratch register (accessible with LCR=0)
896 */
897static void autoconfig_8250(struct uart_8250_port *up)
898{
899 unsigned char scratch, status1, status2;
900
901 up->port.type = PORT_8250;
902
903 scratch = serial_in(up, UART_SCR);
904 serial_outp(up, UART_SCR, 0xa5);
905 status1 = serial_in(up, UART_SCR);
906 serial_outp(up, UART_SCR, 0x5a);
907 status2 = serial_in(up, UART_SCR);
908 serial_outp(up, UART_SCR, scratch);
909
910 if (status1 == 0xa5 && status2 == 0x5a)
911 up->port.type = PORT_16450;
912}
913
914static int broken_efr(struct uart_8250_port *up)
915{
916 /*
917 * Exar ST16C2550 "A2" devices incorrectly detect as
918 * having an EFR, and report an ID of 0x0201. See
919 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
920 */
921 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
922 return 1;
923
924 return 0;
925}
926
927/*
928 * We know that the chip has FIFOs. Does it have an EFR? The
929 * EFR is located in the same register position as the IIR and
930 * we know the top two bits of the IIR are currently set. The
931 * EFR should contain zero. Try to read the EFR.
932 */
933static void autoconfig_16550a(struct uart_8250_port *up)
934{
935 unsigned char status1, status2;
936 unsigned int iersave;
937
938 up->port.type = PORT_16550A;
939 up->capabilities |= UART_CAP_FIFO;
940
941 /*
942 * Check for presence of the EFR when DLAB is set.
943 * Only ST16C650V1 UARTs pass this test.
944 */
945 serial_outp(up, UART_LCR, UART_LCR_DLAB);
946 if (serial_in(up, UART_EFR) == 0) {
947 serial_outp(up, UART_EFR, 0xA8);
948 if (serial_in(up, UART_EFR) != 0) {
949 DEBUG_AUTOCONF("EFRv1 ");
950 up->port.type = PORT_16650;
951 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
952 } else {
953 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
954 }
955 serial_outp(up, UART_EFR, 0);
956 return;
957 }
958
959 /*
960 * Maybe it requires 0xbf to be written to the LCR.
961 * (other ST16C650V2 UARTs, TI16C752A, etc)
962 */
963 serial_outp(up, UART_LCR, 0xBF);
964 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
965 DEBUG_AUTOCONF("EFRv2 ");
966 autoconfig_has_efr(up);
967 return;
968 }
969
970 /*
971 * Check for a National Semiconductor SuperIO chip.
972 * Attempt to switch to bank 2, read the value of the LOOP bit
973 * from EXCR1. Switch back to bank 0, change it in MCR. Then
974 * switch back to bank 2, read it from EXCR1 again and check
975 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 976 */
977 serial_outp(up, UART_LCR, 0);
978 status1 = serial_in(up, UART_MCR);
979 serial_outp(up, UART_LCR, 0xE0);
980 status2 = serial_in(up, 0x02); /* EXCR1 */
981
982 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
983 serial_outp(up, UART_LCR, 0);
984 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
985 serial_outp(up, UART_LCR, 0xE0);
986 status2 = serial_in(up, 0x02); /* EXCR1 */
987 serial_outp(up, UART_LCR, 0);
988 serial_outp(up, UART_MCR, status1);
989
990 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 991 unsigned short quot;
992
1da177e4 993 serial_outp(up, UART_LCR, 0xE0);
857dde2e 994
b32b19b8 995 quot = serial_dl_read(up);
857dde2e
DW		 996 quot <<= 3;
997
b5b82df6 998 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 999 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1000 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1001 serial_outp(up, 0x04, status1);
bd71c182 1002
b32b19b8 1003 serial_dl_write(up, quot);
857dde2e 1004
1da177e4 1005 serial_outp(up, UART_LCR, 0);
1da177e4 1006
857dde2e 1007 up->port.uartclk = 921600*16;
1da177e4
LT		 1008 up->port.type = PORT_NS16550A;
1009 up->capabilities |= UART_NATSEMI;
1010 return;
1011 }
1012 }
1013
1014 /*
1015 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1016 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1017 * Try setting it with and without DLAB set. Cheap clones
1018 * set bit 5 without DLAB set.
1019 */
1020 serial_outp(up, UART_LCR, 0);
1021 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1022 status1 = serial_in(up, UART_IIR) >> 5;
1023 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1024 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1025 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1026 status2 = serial_in(up, UART_IIR) >> 5;
1027 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1028 serial_outp(up, UART_LCR, 0);
1029
1030 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1031
1032 if (status1 == 6 && status2 == 7) {
1033 up->port.type = PORT_16750;
1034 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1035 return;
1036 }
1037
1038 /*
1039 * Try writing and reading the UART_IER_UUE bit (b6).
1040 * If it works, this is probably one of the Xscale platform's
1041 * internal UARTs.
1042 * We're going to explicitly set the UUE bit to 0 before
1043 * trying to write and read a 1 just to make sure it's not
1044 * already a 1 and maybe locked there before we even start start.
1045 */
1046 iersave = serial_in(up, UART_IER);
1047 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1048 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1049 /*
1050 * OK it's in a known zero state, try writing and reading
1051 * without disturbing the current state of the other bits.
1052 */
1053 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1054 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1055 /*
1056 * It's an Xscale.
1057 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1058 */
1059 DEBUG_AUTOCONF("Xscale ");
1060 up->port.type = PORT_XSCALE;
1061 up->capabilities |= UART_CAP_UUE;
1062 return;
1063 }
1064 } else {
1065 /*
1066 * If we got here we couldn't force the IER_UUE bit to 0.
1067 * Log it and continue.
1068 */
1069 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1070 }
1071 serial_outp(up, UART_IER, iersave);
1072}
1073
1074/*
1075 * This routine is called by rs_init() to initialize a specific serial
1076 * port. It determines what type of UART chip this serial port is
1077 * using: 8250, 16450, 16550, 16550A. The important question is
1078 * whether or not this UART is a 16550A or not, since this will
1079 * determine whether or not we can use its FIFO features or not.
1080 */
1081static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1082{
1083 unsigned char status1, scratch, scratch2, scratch3;
1084 unsigned char save_lcr, save_mcr;
1085 unsigned long flags;
1086
1087 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1088 return;
1089
1090 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
8440838b 1091 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1092
1093 /*
1094 * We really do need global IRQs disabled here - we're going to
1095 * be frobbing the chips IRQ enable register to see if it exists.
1096 */
1097 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1098
1099 up->capabilities = 0;
4ba5e35d 1100 up->bugs = 0;
1da177e4
LT		 1101
1102 if (!(up->port.flags & UPF_BUGGY_UART)) {
1103 /*
1104 * Do a simple existence test first; if we fail this,
1105 * there's no point trying anything else.
bd71c182 1106 *
1da177e4
LT		 1107 * 0x80 is used as a nonsense port to prevent against
1108 * false positives due to ISA bus float. The
1109 * assumption is that 0x80 is a non-existent port;
1110 * which should be safe since include/asm/io.h also
1111 * makes this assumption.
1112 *
1113 * Note: this is safe as long as MCR bit 4 is clear
1114 * and the device is in "PC" mode.
1115 */
1116 scratch = serial_inp(up, UART_IER);
1117 serial_outp(up, UART_IER, 0);
1118#ifdef __i386__
1119 outb(0xff, 0x080);
1120#endif
48212008
TH		 1121 /*
1122 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1123 * 16C754B) allow only to modify them if an EFR bit is set.
1124 */
1125 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1126 serial_outp(up, UART_IER, 0x0F);
1127#ifdef __i386__
1128 outb(0, 0x080);
1129#endif
48212008 1130 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1131 serial_outp(up, UART_IER, scratch);
1132 if (scratch2 != 0 || scratch3 != 0x0F) {
1133 /*
1134 * We failed; there's nothing here
1135 */
1136 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1137 scratch2, scratch3);
1138 goto out;
1139 }
1140 }
1141
1142 save_mcr = serial_in(up, UART_MCR);
1143 save_lcr = serial_in(up, UART_LCR);
1144
bd71c182 1145 /*
1da177e4
LT		 1146 * Check to see if a UART is really there. Certain broken
1147 * internal modems based on the Rockwell chipset fail this
1148 * test, because they apparently don't implement the loopback
1149 * test mode. So this test is skipped on the COM 1 through
1150 * COM 4 ports. This *should* be safe, since no board
1151 * manufacturer would be stupid enough to design a board
1152 * that conflicts with COM 1-4 --- we hope!
1153 */
1154 if (!(up->port.flags & UPF_SKIP_TEST)) {
1155 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1156 status1 = serial_inp(up, UART_MSR) & 0xF0;
1157 serial_outp(up, UART_MCR, save_mcr);
1158 if (status1 != 0x90) {
1159 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1160 status1);
1161 goto out;
1162 }
1163 }
1164
1165 /*
1166 * We're pretty sure there's a port here. Lets find out what
1167 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1168 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1169 * determines what we test for next.
1170 *
1171 * We also initialise the EFR (if any) to zero for later. The
1172 * EFR occupies the same register location as the FCR and IIR.
1173 */
1174 serial_outp(up, UART_LCR, 0xBF);
1175 serial_outp(up, UART_EFR, 0);
1176 serial_outp(up, UART_LCR, 0);
1177
1178 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1179 scratch = serial_in(up, UART_IIR) >> 6;
1180
1181 DEBUG_AUTOCONF("iir=%d ", scratch);
1182
1183 switch (scratch) {
1184 case 0:
1185 autoconfig_8250(up);
1186 break;
1187 case 1:
1188 up->port.type = PORT_UNKNOWN;
1189 break;
1190 case 2:
1191 up->port.type = PORT_16550;
1192 break;
1193 case 3:
1194 autoconfig_16550a(up);
1195 break;
1196 }
1197
1198#ifdef CONFIG_SERIAL_8250_RSA
1199 /*
1200 * Only probe for RSA ports if we got the region.
1201 */
1202 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1203 int i;
1204
1205 for (i = 0 ; i < probe_rsa_count; ++i) {
1206 if (probe_rsa[i] == up->port.iobase &&
1207 __enable_rsa(up)) {
1208 up->port.type = PORT_RSA;
1209 break;
1210 }
1211 }
1212 }
1213#endif
21c614a7
PA		 1214
1215#ifdef CONFIG_SERIAL_8250_AU1X00
1216 /* if access method is AU, it is a 16550 with a quirk */
1217 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1218 up->bugs |= UART_BUG_NOMSR;
1219#endif
1220
1da177e4
LT		 1221 serial_outp(up, UART_LCR, save_lcr);
1222
1223 if (up->capabilities != uart_config[up->port.type].flags) {
1224 printk(KERN_WARNING
1225 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1226 serial_index(&up->port), up->capabilities,
1227 uart_config[up->port.type].flags);
1da177e4
LT		 1228 }
1229
1230 up->port.fifosize = uart_config[up->port.type].fifo_size;
1231 up->capabilities = uart_config[up->port.type].flags;
1232 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1233
1234 if (up->port.type == PORT_UNKNOWN)
1235 goto out;
1236
1237 /*
1238 * Reset the UART.
1239 */
1240#ifdef CONFIG_SERIAL_8250_RSA
1241 if (up->port.type == PORT_RSA)
1242 serial_outp(up, UART_RSA_FRR, 0);
1243#endif
1244 serial_outp(up, UART_MCR, save_mcr);
1245 serial8250_clear_fifos(up);
40b36daa 1246 serial_in(up, UART_RX);
5c8c755c
LB		 1247 if (up->capabilities & UART_CAP_UUE)
1248 serial_outp(up, UART_IER, UART_IER_UUE);
1249 else
1250 serial_outp(up, UART_IER, 0);
1da177e4 1251
bd71c182 1252 out:
1da177e4 1253 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1254 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1255}
1256
1257static void autoconfig_irq(struct uart_8250_port *up)
1258{
1259 unsigned char save_mcr, save_ier;
1260 unsigned char save_ICP = 0;
1261 unsigned int ICP = 0;
1262 unsigned long irqs;
1263 int irq;
1264
1265 if (up->port.flags & UPF_FOURPORT) {
1266 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1267 save_ICP = inb_p(ICP);
1268 outb_p(0x80, ICP);
1269 (void) inb_p(ICP);
1270 }
1271
1272 /* forget possible initially masked and pending IRQ */
1273 probe_irq_off(probe_irq_on());
1274 save_mcr = serial_inp(up, UART_MCR);
1275 save_ier = serial_inp(up, UART_IER);
1276 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1277
1da177e4
LT		 1278 irqs = probe_irq_on();
1279 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1280 udelay(10);
1281 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1282 serial_outp(up, UART_MCR,
1283 UART_MCR_DTR | UART_MCR_RTS);
1284 } else {
1285 serial_outp(up, UART_MCR,
1286 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1287 }
1288 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1289 (void)serial_inp(up, UART_LSR);
1290 (void)serial_inp(up, UART_RX);
1291 (void)serial_inp(up, UART_IIR);
1292 (void)serial_inp(up, UART_MSR);
1293 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1294 udelay(20);
1da177e4
LT		 1295 irq = probe_irq_off(irqs);
1296
1297 serial_outp(up, UART_MCR, save_mcr);
1298 serial_outp(up, UART_IER, save_ier);
1299
1300 if (up->port.flags & UPF_FOURPORT)
1301 outb_p(save_ICP, ICP);
1302
1303 up->port.irq = (irq > 0) ? irq : 0;
1304}
1305
e763b90c
RK		 1306static inline void __stop_tx(struct uart_8250_port *p)
1307{
1308 if (p->ier & UART_IER_THRI) {
1309 p->ier &= ~UART_IER_THRI;
1310 serial_out(p, UART_IER, p->ier);
1311 }
1312}
1313
b129a8cc 1314static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1315{
1316 struct uart_8250_port *up = (struct uart_8250_port *)port;
1317
e763b90c 1318 __stop_tx(up);
1da177e4
LT		 1319
1320 /*
e763b90c 1321 * We really want to stop the transmitter from sending.
1da177e4 1322 */
e763b90c 1323 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1324 up->acr |= UART_ACR_TXDIS;
1325 serial_icr_write(up, UART_ACR, up->acr);
1326 }
1327}
1328
55d3b282
RK		 1329static void transmit_chars(struct uart_8250_port *up);
1330
b129a8cc 1331static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1332{
1333 struct uart_8250_port *up = (struct uart_8250_port *)port;
1334
1335 if (!(up->ier & UART_IER_THRI)) {
1336 up->ier |= UART_IER_THRI;
1337 serial_out(up, UART_IER, up->ier);
55d3b282 1338
67f7654e 1339 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1340 unsigned char lsr, iir;
1341 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1342 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182
TK		 1343 iir = serial_in(up, UART_IIR) & 0x0f;
1344 if ((up->port.type == PORT_RM9000) ?
1345 (lsr & UART_LSR_THRE &&
1346 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1347 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
55d3b282
RK		 1348 transmit_chars(up);
1349 }
1da177e4 1350 }
e763b90c 1351
1da177e4 1352 /*
e763b90c 1353 * Re-enable the transmitter if we disabled it.
1da177e4 1354 */
e763b90c 1355 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1356 up->acr &= ~UART_ACR_TXDIS;
1357 serial_icr_write(up, UART_ACR, up->acr);
1358 }
1359}
1360
1361static void serial8250_stop_rx(struct uart_port *port)
1362{
1363 struct uart_8250_port *up = (struct uart_8250_port *)port;
1364
1365 up->ier &= ~UART_IER_RLSI;
1366 up->port.read_status_mask &= ~UART_LSR_DR;
1367 serial_out(up, UART_IER, up->ier);
1368}
1369
1370static void serial8250_enable_ms(struct uart_port *port)
1371{
1372 struct uart_8250_port *up = (struct uart_8250_port *)port;
1373
21c614a7
PA		 1374 /* no MSR capabilities */
1375 if (up->bugs & UART_BUG_NOMSR)
1376 return;
1377
1da177e4
LT		 1378 up->ier |= UART_IER_MSI;
1379 serial_out(up, UART_IER, up->ier);
1380}
1381
ea8874dc 1382static void
cc79aa9d 1383receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1384{
df4f4dd4 1385 struct tty_struct *tty = up->port.info->port.tty;
1da177e4
LT		 1386 unsigned char ch, lsr = *status;
1387 int max_count = 256;
1388 char flag;
1389
1390 do {
7500b1f6
AR		 1391 if (likely(lsr & UART_LSR_DR))
1392 ch = serial_inp(up, UART_RX);
1393 else
1394 /*
1395 * Intel 82571 has a Serial Over Lan device that will
1396 * set UART_LSR_BI without setting UART_LSR_DR when
1397 * it receives a break. To avoid reading from the
1398 * receive buffer without UART_LSR_DR bit set, we
1399 * just force the read character to be 0
1400 */
1401 ch = 0;
1402
1da177e4
LT		 1403 flag = TTY_NORMAL;
1404 up->port.icount.rx++;
1405
ad4c2aa6
CM		 1406 lsr |= up->lsr_saved_flags;
1407 up->lsr_saved_flags = 0;
1da177e4 1408
ad4c2aa6 1409 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1410 /*
1411 * For statistics only
1412 */
1413 if (lsr & UART_LSR_BI) {
1414 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1415 up->port.icount.brk++;
1416 /*
1417 * We do the SysRQ and SAK checking
1418 * here because otherwise the break
1419 * may get masked by ignore_status_mask
1420 * or read_status_mask.
1421 */
1422 if (uart_handle_break(&up->port))
1423 goto ignore_char;
1424 } else if (lsr & UART_LSR_PE)
1425 up->port.icount.parity++;
1426 else if (lsr & UART_LSR_FE)
1427 up->port.icount.frame++;
1428 if (lsr & UART_LSR_OE)
1429 up->port.icount.overrun++;
1430
1431 /*
23907eb8 1432 * Mask off conditions which should be ignored.
1da177e4
LT		 1433 */
1434 lsr &= up->port.read_status_mask;
1435
1436 if (lsr & UART_LSR_BI) {
1437 DEBUG_INTR("handling break....");
1438 flag = TTY_BREAK;
1439 } else if (lsr & UART_LSR_PE)
1440 flag = TTY_PARITY;
1441 else if (lsr & UART_LSR_FE)
1442 flag = TTY_FRAME;
1443 }
7d12e780 1444 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1445 goto ignore_char;
05ab3014
RK		 1446
1447 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1448
6f803cd0 1449ignore_char:
1da177e4 1450 lsr = serial_inp(up, UART_LSR);
7500b1f6 1451 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1452 spin_unlock(&up->port.lock);
1453 tty_flip_buffer_push(tty);
1454 spin_lock(&up->port.lock);
1455 *status = lsr;
1456}
1457
ea8874dc 1458static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1459{
1460 struct circ_buf *xmit = &up->port.info->xmit;
1461 int count;
1462
1463 if (up->port.x_char) {
1464 serial_outp(up, UART_TX, up->port.x_char);
1465 up->port.icount.tx++;
1466 up->port.x_char = 0;
1467 return;
1468 }
b129a8cc
RK		 1469 if (uart_tx_stopped(&up->port)) {
1470 serial8250_stop_tx(&up->port);
1471 return;
1472 }
1473 if (uart_circ_empty(xmit)) {
e763b90c 1474 __stop_tx(up);
1da177e4
LT		 1475 return;
1476 }
1477
1478 count = up->tx_loadsz;
1479 do {
1480 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1481 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1482 up->port.icount.tx++;
1483 if (uart_circ_empty(xmit))
1484 break;
1485 } while (--count > 0);
1486
1487 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1488 uart_write_wakeup(&up->port);
1489
1490 DEBUG_INTR("THRE...");
1491
1492 if (uart_circ_empty(xmit))
e763b90c 1493 __stop_tx(up);
1da177e4
LT		 1494}
1495
2af7cd68 1496static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1497{
2af7cd68
RK		 1498 unsigned int status = serial_in(up, UART_MSR);
1499
ad4c2aa6
CM		 1500 status |= up->msr_saved_flags;
1501 up->msr_saved_flags = 0;
fdc30b3d
TI		 1502 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1503 up->port.info != NULL) {
2af7cd68
RK		 1504 if (status & UART_MSR_TERI)
1505 up->port.icount.rng++;
1506 if (status & UART_MSR_DDSR)
1507 up->port.icount.dsr++;
1508 if (status & UART_MSR_DDCD)
1509 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1510 if (status & UART_MSR_DCTS)
1511 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1512
1513 wake_up_interruptible(&up->port.info->delta_msr_wait);
1514 }
1da177e4 1515
2af7cd68 1516 return status;
1da177e4
LT		 1517}
1518
1519/*
1520 * This handles the interrupt from one port.
1521 */
b5d674ab 1522static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1523{
45e24601 1524 unsigned int status;
4bf3631c 1525 unsigned long flags;
45e24601 1526
4bf3631c 1527 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1528
1529 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1530
1531 DEBUG_INTR("status = %x...", status);
1532
7500b1f6 1533 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1534 receive_chars(up, &status);
1da177e4
LT		 1535 check_modem_status(up);
1536 if (status & UART_LSR_THRE)
1537 transmit_chars(up);
45e24601 1538
4bf3631c 1539 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1540}
1541
1542/*
1543 * This is the serial driver's interrupt routine.
1544 *
1545 * Arjan thinks the old way was overly complex, so it got simplified.
1546 * Alan disagrees, saying that need the complexity to handle the weird
1547 * nature of ISA shared interrupts. (This is a special exception.)
1548 *
1549 * In order to handle ISA shared interrupts properly, we need to check
1550 * that all ports have been serviced, and therefore the ISA interrupt
1551 * line has been de-asserted.
1552 *
1553 * This means we need to loop through all ports. checking that they
1554 * don't have an interrupt pending.
1555 */
7d12e780 1556static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1557{
1558 struct irq_info *i = dev_id;
1559 struct list_head *l, *end = NULL;
1560 int pass_counter = 0, handled = 0;
1561
1562 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1563
1564 spin_lock(&i->lock);
1565
1566 l = i->head;
1567 do {
1568 struct uart_8250_port *up;
1569 unsigned int iir;
1570
1571 up = list_entry(l, struct uart_8250_port, list);
1572
1573 iir = serial_in(up, UART_IIR);
1574 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1575 serial8250_handle_port(up);
1da177e4
LT		 1576
1577 handled = 1;
1578
beab697a
MSJ		 1579 end = NULL;
1580 } else if (up->port.iotype == UPIO_DWAPB &&
1581 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1582 /* The DesignWare APB UART has an Busy Detect (0x07)
1583 * interrupt meaning an LCR write attempt occured while the
1584 * UART was busy. The interrupt must be cleared by reading
1585 * the UART status register (USR) and the LCR re-written. */
1586 unsigned int status;
1587 status = *(volatile u32 *)up->port.private_data;
1588 serial_out(up, UART_LCR, up->lcr);
1589
1590 handled = 1;
1591
1da177e4
LT		 1592 end = NULL;
1593 } else if (end == NULL)
1594 end = l;
1595
1596 l = l->next;
1597
1598 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1599 /* If we hit this, we're dead. */
1600 printk(KERN_ERR "serial8250: too much work for "
1601 "irq%d\n", irq);
1602 break;
1603 }
1604 } while (l != end);
1605
1606 spin_unlock(&i->lock);
1607
1608 DEBUG_INTR("end.\n");
1609
1610 return IRQ_RETVAL(handled);
1611}
1612
1613/*
1614 * To support ISA shared interrupts, we need to have one interrupt
1615 * handler that ensures that the IRQ line has been deasserted
1616 * before returning. Failing to do this will result in the IRQ
1617 * line being stuck active, and, since ISA irqs are edge triggered,
1618 * no more IRQs will be seen.
1619 */
1620static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1621{
1622 spin_lock_irq(&i->lock);
1623
1624 if (!list_empty(i->head)) {
1625 if (i->head == &up->list)
1626 i->head = i->head->next;
1627 list_del(&up->list);
1628 } else {
1629 BUG_ON(i->head != &up->list);
1630 i->head = NULL;
1631 }
1da177e4 1632 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1633 /* List empty so throw away the hash node */
1634 if (i->head == NULL) {
1635 hlist_del(&i->node);
1636 kfree(i);
1637 }
1da177e4
LT		 1638}
1639
1640static int serial_link_irq_chain(struct uart_8250_port *up)
1641{
25db8ad5
AC		 1642 struct hlist_head *h;
1643 struct hlist_node *n;
1644 struct irq_info *i;
40663cc7 1645 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1646
25db8ad5
AC		 1647 mutex_lock(&hash_mutex);
1648
1649 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1650
1651 hlist_for_each(n, h) {
1652 i = hlist_entry(n, struct irq_info, node);
1653 if (i->irq == up->port.irq)
1654 break;
1655 }
1656
1657 if (n == NULL) {
1658 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1659 if (i == NULL) {
1660 mutex_unlock(&hash_mutex);
1661 return -ENOMEM;
1662 }
1663 spin_lock_init(&i->lock);
1664 i->irq = up->port.irq;
1665 hlist_add_head(&i->node, h);
1666 }
1667 mutex_unlock(&hash_mutex);
1668
1da177e4
LT		 1669 spin_lock_irq(&i->lock);
1670
1671 if (i->head) {
1672 list_add(&up->list, i->head);
1673 spin_unlock_irq(&i->lock);
1674
1675 ret = 0;
1676 } else {
1677 INIT_LIST_HEAD(&up->list);
1678 i->head = &up->list;
1679 spin_unlock_irq(&i->lock);
1680
1681 ret = request_irq(up->port.irq, serial8250_interrupt,
1682 irq_flags, "serial", i);
1683 if (ret < 0)
1684 serial_do_unlink(i, up);
1685 }
1686
1687 return ret;
1688}
1689
1690static void serial_unlink_irq_chain(struct uart_8250_port *up)
1691{
25db8ad5
AC		 1692 struct irq_info *i;
1693 struct hlist_node *n;
1694 struct hlist_head *h;
1da177e4 1695
25db8ad5
AC		 1696 mutex_lock(&hash_mutex);
1697
1698 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1699
1700 hlist_for_each(n, h) {
1701 i = hlist_entry(n, struct irq_info, node);
1702 if (i->irq == up->port.irq)
1703 break;
1704 }
1705
1706 BUG_ON(n == NULL);
1da177e4
LT		 1707 BUG_ON(i->head == NULL);
1708
1709 if (list_empty(i->head))
1710 free_irq(up->port.irq, i);
1711
1712 serial_do_unlink(i, up);
25db8ad5 1713 mutex_unlock(&hash_mutex);
1da177e4
LT		 1714}
1715
40b36daa
AW		 1716/* Base timer interval for polling */
1717static inline int poll_timeout(int timeout)
1718{
1719 return timeout > 6 ? (timeout / 2 - 2) : 1;
1720}
1721
1da177e4
LT		 1722/*
1723 * This function is used to handle ports that do not have an
1724 * interrupt. This doesn't work very well for 16450's, but gives
1725 * barely passable results for a 16550A. (Although at the expense
1726 * of much CPU overhead).
1727 */
1728static void serial8250_timeout(unsigned long data)
1729{
1730 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1731 unsigned int iir;
1732
1733 iir = serial_in(up, UART_IIR);
45e24601 1734 if (!(iir & UART_IIR_NO_INT))
7d12e780 1735 serial8250_handle_port(up);
40b36daa
AW		 1736 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1737}
1738
1739static void serial8250_backup_timeout(unsigned long data)
1740{
1741 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1742 unsigned int iir, ier = 0, lsr;
1743 unsigned long flags;
40b36daa
AW		 1744
1745 /*
1746 * Must disable interrupts or else we risk racing with the interrupt
1747 * based handler.
1748 */
1749 if (is_real_interrupt(up->port.irq)) {
1750 ier = serial_in(up, UART_IER);
1751 serial_out(up, UART_IER, 0);
1752 }
1da177e4 1753
40b36daa
AW		 1754 iir = serial_in(up, UART_IIR);
1755
1756 /*
1757 * This should be a safe test for anyone who doesn't trust the
1758 * IIR bits on their UART, but it's specifically designed for
1759 * the "Diva" UART used on the management processor on many HP
1760 * ia64 and parisc boxes.
1761 */
ad4c2aa6
CM		 1762 spin_lock_irqsave(&up->port.lock, flags);
1763 lsr = serial_in(up, UART_LSR);
1764 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1765 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 1766 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1767 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
ad4c2aa6 1768 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1769 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1770 iir |= UART_IIR_THRI;
1771 }
1772
1773 if (!(iir & UART_IIR_NO_INT))
1774 serial8250_handle_port(up);
1775
1776 if (is_real_interrupt(up->port.irq))
1777 serial_out(up, UART_IER, ier);
1778
1779 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0
AC		 1780 mod_timer(&up->timer,
1781 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1da177e4
LT		 1782}
1783
1784static unsigned int serial8250_tx_empty(struct uart_port *port)
1785{
1786 struct uart_8250_port *up = (struct uart_8250_port *)port;
1787 unsigned long flags;
ad4c2aa6 1788 unsigned int lsr;
1da177e4
LT		 1789
1790 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1791 lsr = serial_in(up, UART_LSR);
1792 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1793 spin_unlock_irqrestore(&up->port.lock, flags);
1794
ad4c2aa6 1795 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1da177e4
LT		 1796}
1797
1798static unsigned int serial8250_get_mctrl(struct uart_port *port)
1799{
1800 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1801 unsigned int status;
1da177e4
LT		 1802 unsigned int ret;
1803
2af7cd68 1804 status = check_modem_status(up);
1da177e4
LT		 1805
1806 ret = 0;
1807 if (status & UART_MSR_DCD)
1808 ret |= TIOCM_CAR;
1809 if (status & UART_MSR_RI)
1810 ret |= TIOCM_RNG;
1811 if (status & UART_MSR_DSR)
1812 ret |= TIOCM_DSR;
1813 if (status & UART_MSR_CTS)
1814 ret |= TIOCM_CTS;
1815 return ret;
1816}
1817
1818static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1819{
1820 struct uart_8250_port *up = (struct uart_8250_port *)port;
1821 unsigned char mcr = 0;
1822
1823 if (mctrl & TIOCM_RTS)
1824 mcr |= UART_MCR_RTS;
1825 if (mctrl & TIOCM_DTR)
1826 mcr |= UART_MCR_DTR;
1827 if (mctrl & TIOCM_OUT1)
1828 mcr |= UART_MCR_OUT1;
1829 if (mctrl & TIOCM_OUT2)
1830 mcr |= UART_MCR_OUT2;
1831 if (mctrl & TIOCM_LOOP)
1832 mcr |= UART_MCR_LOOP;
1833
1834 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1835
1836 serial_out(up, UART_MCR, mcr);
1837}
1838
1839static void serial8250_break_ctl(struct uart_port *port, int break_state)
1840{
1841 struct uart_8250_port *up = (struct uart_8250_port *)port;
1842 unsigned long flags;
1843
1844 spin_lock_irqsave(&up->port.lock, flags);
1845 if (break_state == -1)
1846 up->lcr |= UART_LCR_SBC;
1847 else
1848 up->lcr &= ~UART_LCR_SBC;
1849 serial_out(up, UART_LCR, up->lcr);
1850 spin_unlock_irqrestore(&up->port.lock, flags);
1851}
1852
40b36daa
AW		 1853#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1854
1855/*
1856 * Wait for transmitter & holding register to empty
1857 */
b5d674ab 1858static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1859{
1860 unsigned int status, tmout = 10000;
1861
1862 /* Wait up to 10ms for the character(s) to be sent. */
1863 do {
1864 status = serial_in(up, UART_LSR);
1865
ad4c2aa6 1866 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa
AW		 1867
1868 if (--tmout == 0)
1869 break;
1870 udelay(1);
1871 } while ((status & bits) != bits);
1872
1873 /* Wait up to 1s for flow control if necessary */
1874 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1875 unsigned int tmout;
1876 for (tmout = 1000000; tmout; tmout--) {
1877 unsigned int msr = serial_in(up, UART_MSR);
1878 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1879 if (msr & UART_MSR_CTS)
1880 break;
40b36daa
AW		 1881 udelay(1);
1882 touch_nmi_watchdog();
1883 }
1884 }
1885}
1886
f2d937f3
JW		 1887#ifdef CONFIG_CONSOLE_POLL
1888/*
1889 * Console polling routines for writing and reading from the uart while
1890 * in an interrupt or debug context.
1891 */
1892
1893static int serial8250_get_poll_char(struct uart_port *port)
1894{
1895 struct uart_8250_port *up = (struct uart_8250_port *)port;
1896 unsigned char lsr = serial_inp(up, UART_LSR);
1897
1898 while (!(lsr & UART_LSR_DR))
1899 lsr = serial_inp(up, UART_LSR);
1900
1901 return serial_inp(up, UART_RX);
1902}
1903
1904
1905static void serial8250_put_poll_char(struct uart_port *port,
1906 unsigned char c)
1907{
1908 unsigned int ier;
1909 struct uart_8250_port *up = (struct uart_8250_port *)port;
1910
1911 /*
1912 * First save the IER then disable the interrupts
1913 */
1914 ier = serial_in(up, UART_IER);
1915 if (up->capabilities & UART_CAP_UUE)
1916 serial_out(up, UART_IER, UART_IER_UUE);
1917 else
1918 serial_out(up, UART_IER, 0);
1919
1920 wait_for_xmitr(up, BOTH_EMPTY);
1921 /*
1922 * Send the character out.
1923 * If a LF, also do CR...
1924 */
1925 serial_out(up, UART_TX, c);
1926 if (c == 10) {
1927 wait_for_xmitr(up, BOTH_EMPTY);
1928 serial_out(up, UART_TX, 13);
1929 }
1930
1931 /*
1932 * Finally, wait for transmitter to become empty
1933 * and restore the IER
1934 */
1935 wait_for_xmitr(up, BOTH_EMPTY);
1936 serial_out(up, UART_IER, ier);
1937}
1938
1939#endif /* CONFIG_CONSOLE_POLL */
1940
1da177e4
LT		 1941static int serial8250_startup(struct uart_port *port)
1942{
1943 struct uart_8250_port *up = (struct uart_8250_port *)port;
1944 unsigned long flags;
55d3b282 1945 unsigned char lsr, iir;
1da177e4
LT		 1946 int retval;
1947
1948 up->capabilities = uart_config[up->port.type].flags;
1949 up->mcr = 0;
1950
b8e7e40a
AC		 1951 if (up->port.iotype != up->cur_iotype)
1952 set_io_from_upio(port);
1953
1da177e4
LT		 1954 if (up->port.type == PORT_16C950) {
1955 /* Wake up and initialize UART */
1956 up->acr = 0;
1957 serial_outp(up, UART_LCR, 0xBF);
1958 serial_outp(up, UART_EFR, UART_EFR_ECB);
1959 serial_outp(up, UART_IER, 0);
1960 serial_outp(up, UART_LCR, 0);
1961 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1962 serial_outp(up, UART_LCR, 0xBF);
1963 serial_outp(up, UART_EFR, UART_EFR_ECB);
1964 serial_outp(up, UART_LCR, 0);
1965 }
1966
1967#ifdef CONFIG_SERIAL_8250_RSA
1968 /*
1969 * If this is an RSA port, see if we can kick it up to the
1970 * higher speed clock.
1971 */
1972 enable_rsa(up);
1973#endif
1974
1975 /*
1976 * Clear the FIFO buffers and disable them.
7f927fcc 1977 * (they will be reenabled in set_termios())
1da177e4
LT		 1978 */
1979 serial8250_clear_fifos(up);
1980
1981 /*
1982 * Clear the interrupt registers.
1983 */
1984 (void) serial_inp(up, UART_LSR);
1985 (void) serial_inp(up, UART_RX);
1986 (void) serial_inp(up, UART_IIR);
1987 (void) serial_inp(up, UART_MSR);
1988
1989 /*
1990 * At this point, there's no way the LSR could still be 0xff;
1991 * if it is, then bail out, because there's likely no UART
1992 * here.
1993 */
1994 if (!(up->port.flags & UPF_BUGGY_UART) &&
1995 (serial_inp(up, UART_LSR) == 0xff)) {
8440838b
DM		 1996 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1997 serial_index(&up->port));
1da177e4
LT		 1998 return -ENODEV;
1999 }
2000
2001 /*
2002 * For a XR16C850, we need to set the trigger levels
2003 */
2004 if (up->port.type == PORT_16850) {
2005 unsigned char fctr;
2006
2007 serial_outp(up, UART_LCR, 0xbf);
2008
2009 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2010 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2011 serial_outp(up, UART_TRG, UART_TRG_96);
2012 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2013 serial_outp(up, UART_TRG, UART_TRG_96);
2014
2015 serial_outp(up, UART_LCR, 0);
2016 }
2017
40b36daa 2018 if (is_real_interrupt(up->port.irq)) {
01c194d9 2019 unsigned char iir1;
40b36daa
AW		 2020 /*
2021 * Test for UARTs that do not reassert THRE when the
2022 * transmitter is idle and the interrupt has already
2023 * been cleared. Real 16550s should always reassert
2024 * this interrupt whenever the transmitter is idle and
2025 * the interrupt is enabled. Delays are necessary to
2026 * allow register changes to become visible.
2027 */
c389d27b 2028 spin_lock_irqsave(&up->port.lock, flags);
768aec0b
AV		 2029 if (up->port.flags & UPF_SHARE_IRQ)
2030 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2031
2032 wait_for_xmitr(up, UART_LSR_THRE);
2033 serial_out_sync(up, UART_IER, UART_IER_THRI);
2034 udelay(1); /* allow THRE to set */
01c194d9 2035 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2036 serial_out(up, UART_IER, 0);
2037 serial_out_sync(up, UART_IER, UART_IER_THRI);
2038 udelay(1); /* allow a working UART time to re-assert THRE */
2039 iir = serial_in(up, UART_IIR);
2040 serial_out(up, UART_IER, 0);
2041
768aec0b
AV		 2042 if (up->port.flags & UPF_SHARE_IRQ)
2043 enable_irq(up->port.irq);
c389d27b 2044 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2045
2046 /*
2047 * If the interrupt is not reasserted, setup a timer to
2048 * kick the UART on a regular basis.
2049 */
01c194d9 2050 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2051 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2052 pr_debug("ttyS%d - using backup timer\n",
2053 serial_index(port));
40b36daa
AW		 2054 }
2055 }
2056
363f66fe
WN		 2057 /*
2058 * The above check will only give an accurate result the first time
2059 * the port is opened so this value needs to be preserved.
2060 */
2061 if (up->bugs & UART_BUG_THRE) {
2062 up->timer.function = serial8250_backup_timeout;
2063 up->timer.data = (unsigned long)up;
2064 mod_timer(&up->timer, jiffies +
2065 poll_timeout(up->port.timeout) + HZ / 5);
2066 }
2067
1da177e4
LT		 2068 /*
2069 * If the "interrupt" for this port doesn't correspond with any
2070 * hardware interrupt, we use a timer-based system. The original
2071 * driver used to do this with IRQ0.
2072 */
2073 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2074 up->timer.data = (unsigned long)up;
40b36daa 2075 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 2076 } else {
2077 retval = serial_link_irq_chain(up);
2078 if (retval)
2079 return retval;
2080 }
2081
2082 /*
2083 * Now, initialize the UART
2084 */
2085 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2086
2087 spin_lock_irqsave(&up->port.lock, flags);
2088 if (up->port.flags & UPF_FOURPORT) {
2089 if (!is_real_interrupt(up->port.irq))
2090 up->port.mctrl |= TIOCM_OUT1;
2091 } else
2092 /*
2093 * Most PC uarts need OUT2 raised to enable interrupts.
2094 */
2095 if (is_real_interrupt(up->port.irq))
2096 up->port.mctrl |= TIOCM_OUT2;
2097
2098 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2099
b6adea33
MCC		 2100 /* Serial over Lan (SoL) hack:
2101 Intel 8257x Gigabit ethernet chips have a
2102 16550 emulation, to be used for Serial Over Lan.
2103 Those chips take a longer time than a normal
2104 serial device to signalize that a transmission
2105 data was queued. Due to that, the above test generally
2106 fails. One solution would be to delay the reading of
2107 iir. However, this is not reliable, since the timeout
2108 is variable. So, let's just don't test if we receive
2109 TX irq. This way, we'll never enable UART_BUG_TXEN.
2110 */
2111 if (up->port.flags & UPF_NO_TXEN_TEST)
2112 goto dont_test_tx_en;
2113
55d3b282
RK		 2114 /*
2115 * Do a quick test to see if we receive an
2116 * interrupt when we enable the TX irq.
2117 */
2118 serial_outp(up, UART_IER, UART_IER_THRI);
2119 lsr = serial_in(up, UART_LSR);
2120 iir = serial_in(up, UART_IIR);
2121 serial_outp(up, UART_IER, 0);
2122
2123 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2124 if (!(up->bugs & UART_BUG_TXEN)) {
2125 up->bugs |= UART_BUG_TXEN;
55d3b282 2126 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2127 serial_index(port));
55d3b282
RK		 2128 }
2129 } else {
67f7654e 2130 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2131 }
2132
b6adea33 2133dont_test_tx_en:
1da177e4
LT		 2134 spin_unlock_irqrestore(&up->port.lock, flags);
2135
ad4c2aa6
CM		 2136 /*
2137 * Clear the interrupt registers again for luck, and clear the
2138 * saved flags to avoid getting false values from polling
2139 * routines or the previous session.
2140 */
2141 serial_inp(up, UART_LSR);
2142 serial_inp(up, UART_RX);
2143 serial_inp(up, UART_IIR);
2144 serial_inp(up, UART_MSR);
2145 up->lsr_saved_flags = 0;
2146 up->msr_saved_flags = 0;
2147
1da177e4
LT		 2148 /*
2149 * Finally, enable interrupts. Note: Modem status interrupts
2150 * are set via set_termios(), which will be occurring imminently
2151 * anyway, so we don't enable them here.
2152 */
2153 up->ier = UART_IER_RLSI | UART_IER_RDI;
2154 serial_outp(up, UART_IER, up->ier);
2155
2156 if (up->port.flags & UPF_FOURPORT) {
2157 unsigned int icp;
2158 /*
2159 * Enable interrupts on the AST Fourport board
2160 */
2161 icp = (up->port.iobase & 0xfe0) | 0x01f;
2162 outb_p(0x80, icp);
2163 (void) inb_p(icp);
2164 }
2165
1da177e4
LT		 2166 return 0;
2167}
2168
2169static void serial8250_shutdown(struct uart_port *port)
2170{
2171 struct uart_8250_port *up = (struct uart_8250_port *)port;
2172 unsigned long flags;
2173
2174 /*
2175 * Disable interrupts from this port
2176 */
2177 up->ier = 0;
2178 serial_outp(up, UART_IER, 0);
2179
2180 spin_lock_irqsave(&up->port.lock, flags);
2181 if (up->port.flags & UPF_FOURPORT) {
2182 /* reset interrupts on the AST Fourport board */
2183 inb((up->port.iobase & 0xfe0) | 0x1f);
2184 up->port.mctrl |= TIOCM_OUT1;
2185 } else
2186 up->port.mctrl &= ~TIOCM_OUT2;
2187
2188 serial8250_set_mctrl(&up->port, up->port.mctrl);
2189 spin_unlock_irqrestore(&up->port.lock, flags);
2190
2191 /*
2192 * Disable break condition and FIFOs
2193 */
2194 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2195 serial8250_clear_fifos(up);
2196
2197#ifdef CONFIG_SERIAL_8250_RSA
2198 /*
2199 * Reset the RSA board back to 115kbps compat mode.
2200 */
2201 disable_rsa(up);
2202#endif
2203
2204 /*
2205 * Read data port to reset things, and then unlink from
2206 * the IRQ chain.
2207 */
2208 (void) serial_in(up, UART_RX);
2209
40b36daa
AW		 2210 del_timer_sync(&up->timer);
2211 up->timer.function = serial8250_timeout;
2212 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2213 serial_unlink_irq_chain(up);
2214}
2215
2216static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2217{
2218 unsigned int quot;
2219
2220 /*
2221 * Handle magic divisors for baud rates above baud_base on
2222 * SMSC SuperIO chips.
2223 */
2224 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2225 baud == (port->uartclk/4))
2226 quot = 0x8001;
2227 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2228 baud == (port->uartclk/8))
2229 quot = 0x8002;
2230 else
2231 quot = uart_get_divisor(port, baud);
2232
2233 return quot;
2234}
2235
2236static void
606d099c
AC		 2237serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2238 struct ktermios *old)
1da177e4
LT		 2239{
2240 struct uart_8250_port *up = (struct uart_8250_port *)port;
2241 unsigned char cval, fcr = 0;
2242 unsigned long flags;
2243 unsigned int baud, quot;
2244
2245 switch (termios->c_cflag & CSIZE) {
2246 case CS5:
0a8b80c5 2247 cval = UART_LCR_WLEN5;
1da177e4
LT		 2248 break;
2249 case CS6:
0a8b80c5 2250 cval = UART_LCR_WLEN6;
1da177e4
LT		 2251 break;
2252 case CS7:
0a8b80c5 2253 cval = UART_LCR_WLEN7;
1da177e4
LT		 2254 break;
2255 default:
2256 case CS8:
0a8b80c5 2257 cval = UART_LCR_WLEN8;
1da177e4
LT		 2258 break;
2259 }
2260
2261 if (termios->c_cflag & CSTOPB)
0a8b80c5 2262 cval |= UART_LCR_STOP;
1da177e4
LT		 2263 if (termios->c_cflag & PARENB)
2264 cval |= UART_LCR_PARITY;
2265 if (!(termios->c_cflag & PARODD))
2266 cval |= UART_LCR_EPAR;
2267#ifdef CMSPAR
2268 if (termios->c_cflag & CMSPAR)
2269 cval |= UART_LCR_SPAR;
2270#endif
2271
2272 /*
2273 * Ask the core to calculate the divisor for us.
2274 */
bd71c182 2275 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1da177e4
LT		 2276 quot = serial8250_get_divisor(port, baud);
2277
2278 /*
4ba5e35d 2279 * Oxford Semi 952 rev B workaround
1da177e4 2280 */
4ba5e35d 2281 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2282 quot++;
1da177e4
LT		 2283
2284 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2285 if (baud < 2400)
2286 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2287 else
2288 fcr = uart_config[up->port.type].fcr;
2289 }
2290
2291 /*
2292 * MCR-based auto flow control. When AFE is enabled, RTS will be
2293 * deasserted when the receive FIFO contains more characters than
2294 * the trigger, or the MCR RTS bit is cleared. In the case where
2295 * the remote UART is not using CTS auto flow control, we must
2296 * have sufficient FIFO entries for the latency of the remote
2297 * UART to respond. IOW, at least 32 bytes of FIFO.
2298 */
2299 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2300 up->mcr &= ~UART_MCR_AFE;
2301 if (termios->c_cflag & CRTSCTS)
2302 up->mcr |= UART_MCR_AFE;
2303 }
2304
2305 /*
2306 * Ok, we're now changing the port state. Do it with
2307 * interrupts disabled.
2308 */
2309 spin_lock_irqsave(&up->port.lock, flags);
2310
2311 /*
2312 * Update the per-port timeout.
2313 */
2314 uart_update_timeout(port, termios->c_cflag, baud);
2315
2316 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2317 if (termios->c_iflag & INPCK)
2318 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2319 if (termios->c_iflag & (BRKINT | PARMRK))
2320 up->port.read_status_mask |= UART_LSR_BI;
2321
2322 /*
2323 * Characteres to ignore
2324 */
2325 up->port.ignore_status_mask = 0;
2326 if (termios->c_iflag & IGNPAR)
2327 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2328 if (termios->c_iflag & IGNBRK) {
2329 up->port.ignore_status_mask |= UART_LSR_BI;
2330 /*
2331 * If we're ignoring parity and break indicators,
2332 * ignore overruns too (for real raw support).
2333 */
2334 if (termios->c_iflag & IGNPAR)
2335 up->port.ignore_status_mask |= UART_LSR_OE;
2336 }
2337
2338 /*
2339 * ignore all characters if CREAD is not set
2340 */
2341 if ((termios->c_cflag & CREAD) == 0)
2342 up->port.ignore_status_mask |= UART_LSR_DR;
2343
2344 /*
2345 * CTS flow control flag and modem status interrupts
2346 */
2347 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2348 if (!(up->bugs & UART_BUG_NOMSR) &&
2349 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2350 up->ier |= UART_IER_MSI;
2351 if (up->capabilities & UART_CAP_UUE)
2352 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2353
2354 serial_out(up, UART_IER, up->ier);
2355
2356 if (up->capabilities & UART_CAP_EFR) {
2357 unsigned char efr = 0;
2358 /*
2359 * TI16C752/Startech hardware flow control. FIXME:
2360 * - TI16C752 requires control thresholds to be set.
2361 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2362 */
2363 if (termios->c_cflag & CRTSCTS)
2364 efr |= UART_EFR_CTS;
2365
2366 serial_outp(up, UART_LCR, 0xBF);
2367 serial_outp(up, UART_EFR, efr);
2368 }
2369
f2eda27d 2370#ifdef CONFIG_ARCH_OMAP
255341c6 2371 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2372 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2373 if (baud == 115200) {
2374 quot = 1;
2375 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2376 } else
2377 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2378 }
2379#endif
2380
1da177e4
LT		 2381 if (up->capabilities & UART_NATSEMI) {
2382 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2383 serial_outp(up, UART_LCR, 0xe0);
2384 } else {
2385 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2386 }
2387
b32b19b8 2388 serial_dl_write(up, quot);
1da177e4
LT		 2389
2390 /*
2391 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2392 * is written without DLAB set, this mode will be disabled.
2393 */
2394 if (up->port.type == PORT_16750)
2395 serial_outp(up, UART_FCR, fcr);
2396
2397 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2398 up->lcr = cval; /* Save LCR */
2399 if (up->port.type != PORT_16750) {
2400 if (fcr & UART_FCR_ENABLE_FIFO) {
2401 /* emulated UARTs (Lucent Venus 167x) need two steps */
2402 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2403 }
2404 serial_outp(up, UART_FCR, fcr); /* set fcr */
2405 }
2406 serial8250_set_mctrl(&up->port, up->port.mctrl);
2407 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2408 /* Don't rewrite B0 */
2409 if (tty_termios_baud_rate(termios))
2410 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4
LT		 2411}
2412
2413static void
2414serial8250_pm(struct uart_port *port, unsigned int state,
2415 unsigned int oldstate)
2416{
2417 struct uart_8250_port *p = (struct uart_8250_port *)port;
2418
2419 serial8250_set_sleep(p, state != 0);
2420
2421 if (p->pm)
2422 p->pm(port, state, oldstate);
2423}
2424
f2eda27d
RK		 2425static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2426{
2427 if (pt->port.iotype == UPIO_AU)
2428 return 0x100000;
2429#ifdef CONFIG_ARCH_OMAP
2430 if (is_omap_port(pt))
2431 return 0x16 << pt->port.regshift;
2432#endif
2433 return 8 << pt->port.regshift;
2434}
2435
1da177e4
LT		 2436/*
2437 * Resource handling.
2438 */
2439static int serial8250_request_std_resource(struct uart_8250_port *up)
2440{
f2eda27d 2441 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2442 int ret = 0;
2443
2444 switch (up->port.iotype) {
85835f44 2445 case UPIO_AU:
0b30d668
SS		 2446 case UPIO_TSI:
2447 case UPIO_MEM32:
1da177e4 2448 case UPIO_MEM:
beab697a 2449 case UPIO_DWAPB:
1da177e4
LT		 2450 if (!up->port.mapbase)
2451 break;
2452
2453 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2454 ret = -EBUSY;
2455 break;
2456 }
2457
2458 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2459 up->port.membase = ioremap_nocache(up->port.mapbase,
2460 size);
1da177e4
LT		 2461 if (!up->port.membase) {
2462 release_mem_region(up->port.mapbase, size);
2463 ret = -ENOMEM;
2464 }
2465 }
2466 break;
2467
2468 case UPIO_HUB6:
2469 case UPIO_PORT:
2470 if (!request_region(up->port.iobase, size, "serial"))
2471 ret = -EBUSY;
2472 break;
2473 }
2474 return ret;
2475}
2476
2477static void serial8250_release_std_resource(struct uart_8250_port *up)
2478{
f2eda27d 2479 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2480
2481 switch (up->port.iotype) {
85835f44 2482 case UPIO_AU:
0b30d668
SS		 2483 case UPIO_TSI:
2484 case UPIO_MEM32:
1da177e4 2485 case UPIO_MEM:
beab697a 2486 case UPIO_DWAPB:
1da177e4
LT		 2487 if (!up->port.mapbase)
2488 break;
2489
2490 if (up->port.flags & UPF_IOREMAP) {
2491 iounmap(up->port.membase);
2492 up->port.membase = NULL;
2493 }
2494
2495 release_mem_region(up->port.mapbase, size);
2496 break;
2497
2498 case UPIO_HUB6:
2499 case UPIO_PORT:
2500 release_region(up->port.iobase, size);
2501 break;
2502 }
2503}
2504
2505static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2506{
2507 unsigned long start = UART_RSA_BASE << up->port.regshift;
2508 unsigned int size = 8 << up->port.regshift;
0b30d668 2509 int ret = -EINVAL;
1da177e4
LT		 2510
2511 switch (up->port.iotype) {
1da177e4
LT		 2512 case UPIO_HUB6:
2513 case UPIO_PORT:
2514 start += up->port.iobase;
0b30d668
SS		 2515 if (request_region(start, size, "serial-rsa"))
2516 ret = 0;
2517 else
1da177e4
LT		 2518 ret = -EBUSY;
2519 break;
2520 }
2521
2522 return ret;
2523}
2524
2525static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2526{
2527 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2528 unsigned int size = 8 << up->port.regshift;
2529
2530 switch (up->port.iotype) {
1da177e4
LT		 2531 case UPIO_HUB6:
2532 case UPIO_PORT:
2533 release_region(up->port.iobase + offset, size);
2534 break;
2535 }
2536}
2537
2538static void serial8250_release_port(struct uart_port *port)
2539{
2540 struct uart_8250_port *up = (struct uart_8250_port *)port;
2541
2542 serial8250_release_std_resource(up);
2543 if (up->port.type == PORT_RSA)
2544 serial8250_release_rsa_resource(up);
2545}
2546
2547static int serial8250_request_port(struct uart_port *port)
2548{
2549 struct uart_8250_port *up = (struct uart_8250_port *)port;
2550 int ret = 0;
2551
2552 ret = serial8250_request_std_resource(up);
2553 if (ret == 0 && up->port.type == PORT_RSA) {
2554 ret = serial8250_request_rsa_resource(up);
2555 if (ret < 0)
2556 serial8250_release_std_resource(up);
2557 }
2558
2559 return ret;
2560}
2561
2562static void serial8250_config_port(struct uart_port *port, int flags)
2563{
2564 struct uart_8250_port *up = (struct uart_8250_port *)port;
2565 int probeflags = PROBE_ANY;
2566 int ret;
2567
1da177e4
LT		 2568 /*
2569 * Find the region that we can probe for. This in turn
2570 * tells us whether we can probe for the type of port.
2571 */
2572 ret = serial8250_request_std_resource(up);
2573 if (ret < 0)
2574 return;
2575
2576 ret = serial8250_request_rsa_resource(up);
2577 if (ret < 0)
2578 probeflags &= ~PROBE_RSA;
2579
b8e7e40a
AC		 2580 if (up->port.iotype != up->cur_iotype)
2581 set_io_from_upio(port);
2582
1da177e4
LT		 2583 if (flags & UART_CONFIG_TYPE)
2584 autoconfig(up, probeflags);
2585 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2586 autoconfig_irq(up);
2587
2588 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2589 serial8250_release_rsa_resource(up);
2590 if (up->port.type == PORT_UNKNOWN)
2591 serial8250_release_std_resource(up);
2592}
2593
2594static int
2595serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2596{
a62c4133 2597 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2598 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2599 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2600 ser->type == PORT_STARTECH)
2601 return -EINVAL;
2602 return 0;
2603}
2604
2605static const char *
2606serial8250_type(struct uart_port *port)
2607{
2608 int type = port->type;
2609
2610 if (type >= ARRAY_SIZE(uart_config))
2611 type = 0;
2612 return uart_config[type].name;
2613}
2614
2615static struct uart_ops serial8250_pops = {
2616 .tx_empty = serial8250_tx_empty,
2617 .set_mctrl = serial8250_set_mctrl,
2618 .get_mctrl = serial8250_get_mctrl,
2619 .stop_tx = serial8250_stop_tx,
2620 .start_tx = serial8250_start_tx,
2621 .stop_rx = serial8250_stop_rx,
2622 .enable_ms = serial8250_enable_ms,
2623 .break_ctl = serial8250_break_ctl,
2624 .startup = serial8250_startup,
2625 .shutdown = serial8250_shutdown,
2626 .set_termios = serial8250_set_termios,
2627 .pm = serial8250_pm,
2628 .type = serial8250_type,
2629 .release_port = serial8250_release_port,
2630 .request_port = serial8250_request_port,
2631 .config_port = serial8250_config_port,
2632 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2633#ifdef CONFIG_CONSOLE_POLL
2634 .poll_get_char = serial8250_get_poll_char,
2635 .poll_put_char = serial8250_put_poll_char,
2636#endif
1da177e4
LT		 2637};
2638
2639static struct uart_8250_port serial8250_ports[UART_NR];
2640
2641static void __init serial8250_isa_init_ports(void)
2642{
2643 struct uart_8250_port *up;
2644 static int first = 1;
2645 int i;
2646
2647 if (!first)
2648 return;
2649 first = 0;
2650
a61c2d78 2651 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2652 struct uart_8250_port *up = &serial8250_ports[i];
2653
2654 up->port.line = i;
2655 spin_lock_init(&up->port.lock);
2656
2657 init_timer(&up->timer);
2658 up->timer.function = serial8250_timeout;
2659
2660 /*
2661 * ALPHA_KLUDGE_MCR needs to be killed.
2662 */
2663 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2664 up->mcr_force = ALPHA_KLUDGE_MCR;
2665
2666 up->port.ops = &serial8250_pops;
2667 }
2668
44454bcd 2669 for (i = 0, up = serial8250_ports;
a61c2d78 2670 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2671 i++, up++) {
2672 up->port.iobase = old_serial_port[i].port;
2673 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2674 up->port.uartclk = old_serial_port[i].baud_base * 16;
2675 up->port.flags = old_serial_port[i].flags;
2676 up->port.hub6 = old_serial_port[i].hub6;
2677 up->port.membase = old_serial_port[i].iomem_base;
2678 up->port.iotype = old_serial_port[i].io_type;
2679 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2680 set_io_from_upio(&up->port);
1da177e4
LT		 2681 if (share_irqs)
2682 up->port.flags |= UPF_SHARE_IRQ;
2683 }
2684}
2685
2686static void __init
2687serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2688{
2689 int i;
2690
b8e7e40a
AC		 2691 for (i = 0; i < nr_uarts; i++) {
2692 struct uart_8250_port *up = &serial8250_ports[i];
2693 up->cur_iotype = 0xFF;
2694 }
2695
1da177e4
LT		 2696 serial8250_isa_init_ports();
2697
a61c2d78 2698 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2699 struct uart_8250_port *up = &serial8250_ports[i];
2700
2701 up->port.dev = dev;
2702 uart_add_one_port(drv, &up->port);
2703 }
2704}
2705
2706#ifdef CONFIG_SERIAL_8250_CONSOLE
2707
d358788f
RK		 2708static void serial8250_console_putchar(struct uart_port *port, int ch)
2709{
2710 struct uart_8250_port *up = (struct uart_8250_port *)port;
2711
2712 wait_for_xmitr(up, UART_LSR_THRE);
2713 serial_out(up, UART_TX, ch);
2714}
2715
1da177e4
LT		 2716/*
2717 * Print a string to the serial port trying not to disturb
2718 * any possible real use of the port...
2719 *
2720 * The console_lock must be held when we get here.
2721 */
2722static void
2723serial8250_console_write(struct console *co, const char *s, unsigned int count)
2724{
2725 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2726 unsigned long flags;
1da177e4 2727 unsigned int ier;
d8a5a8d7 2728 int locked = 1;
1da177e4 2729
78512ece
AM		 2730 touch_nmi_watchdog();
2731
68aa2c0d
AM		 2732 local_irq_save(flags);
2733 if (up->port.sysrq) {
2734 /* serial8250_handle_port() already took the lock */
2735 locked = 0;
2736 } else if (oops_in_progress) {
2737 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2738 } else
68aa2c0d 2739 spin_lock(&up->port.lock);
d8a5a8d7 2740
1da177e4 2741 /*
dc7bf130 2742 * First save the IER then disable the interrupts
1da177e4
LT		 2743 */
2744 ier = serial_in(up, UART_IER);
2745
2746 if (up->capabilities & UART_CAP_UUE)
2747 serial_out(up, UART_IER, UART_IER_UUE);
2748 else
2749 serial_out(up, UART_IER, 0);
2750
d358788f 2751 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2752
2753 /*
2754 * Finally, wait for transmitter to become empty
2755 * and restore the IER
2756 */
f91a3715 2757 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2758 serial_out(up, UART_IER, ier);
d8a5a8d7 2759
ad4c2aa6
CM		 2760 /*
2761 * The receive handling will happen properly because the
2762 * receive ready bit will still be set; it is not cleared
2763 * on read. However, modem control will not, we must
2764 * call it if we have saved something in the saved flags
2765 * while processing with interrupts off.
2766 */
2767 if (up->msr_saved_flags)
2768 check_modem_status(up);
2769
d8a5a8d7 2770 if (locked)
68aa2c0d
AM		 2771 spin_unlock(&up->port.lock);
2772 local_irq_restore(flags);
1da177e4
LT		 2773}
2774
118c0ace 2775static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2776{
2777 struct uart_port *port;
2778 int baud = 9600;
2779 int bits = 8;
2780 int parity = 'n';
2781 int flow = 'n';
2782
2783 /*
2784 * Check whether an invalid uart number has been specified, and
2785 * if so, search for the first available port that does have
2786 * console support.
2787 */
a61c2d78 2788 if (co->index >= nr_uarts)
1da177e4
LT		 2789 co->index = 0;
2790 port = &serial8250_ports[co->index].port;
2791 if (!port->iobase && !port->membase)
2792 return -ENODEV;
2793
2794 if (options)
2795 uart_parse_options(options, &baud, &parity, &bits, &flow);
2796
2797 return uart_set_options(port, co, baud, parity, bits, flow);
2798}
2799
b6b1d877 2800static int serial8250_console_early_setup(void)
18a8bd94
YL		 2801{
2802 return serial8250_find_port_for_earlycon();
2803}
2804
1da177e4
LT		 2805static struct console serial8250_console = {
2806 .name = "ttyS",
2807 .write = serial8250_console_write,
2808 .device = uart_console_device,
2809 .setup = serial8250_console_setup,
18a8bd94 2810 .early_setup = serial8250_console_early_setup,
1da177e4
LT		 2811 .flags = CON_PRINTBUFFER,
2812 .index = -1,
2813 .data = &serial8250_reg,
2814};
2815
2816static int __init serial8250_console_init(void)
2817{
05d81d22
EB		 2818 if (nr_uarts > UART_NR)
2819 nr_uarts = UART_NR;
2820
1da177e4
LT		 2821 serial8250_isa_init_ports();
2822 register_console(&serial8250_console);
2823 return 0;
2824}
2825console_initcall(serial8250_console_init);
2826
18a8bd94 2827int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2828{
2829 int line;
2830 struct uart_port *port;
2831
a61c2d78 2832 for (line = 0; line < nr_uarts; line++) {
1da177e4 2833 port = &serial8250_ports[line].port;
50aec3b5 2834 if (uart_match_port(p, port))
1da177e4
LT		 2835 return line;
2836 }
2837 return -ENODEV;
2838}
2839
1da177e4
LT		 2840#define SERIAL8250_CONSOLE &serial8250_console
2841#else
2842#define SERIAL8250_CONSOLE NULL
2843#endif
2844
2845static struct uart_driver serial8250_reg = {
2846 .owner = THIS_MODULE,
2847 .driver_name = "serial",
1da177e4
LT		 2848 .dev_name = "ttyS",
2849 .major = TTY_MAJOR,
2850 .minor = 64,
1da177e4
LT		 2851 .cons = SERIAL8250_CONSOLE,
2852};
2853
d856c666
RK		 2854/*
2855 * early_serial_setup - early registration for 8250 ports
2856 *
2857 * Setup an 8250 port structure prior to console initialisation. Use
2858 * after console initialisation will cause undefined behaviour.
2859 */
1da177e4
LT		 2860int __init early_serial_setup(struct uart_port *port)
2861{
b430428a
DD		 2862 struct uart_port *p;
2863
1da177e4
LT		 2864 if (port->line >= ARRAY_SIZE(serial8250_ports))
2865 return -ENODEV;
2866
2867 serial8250_isa_init_ports();
b430428a
DD		 2868 p = &serial8250_ports[port->line].port;
2869 p->iobase = port->iobase;
2870 p->membase = port->membase;
2871 p->irq = port->irq;
2872 p->uartclk = port->uartclk;
2873 p->fifosize = port->fifosize;
2874 p->regshift = port->regshift;
2875 p->iotype = port->iotype;
2876 p->flags = port->flags;
2877 p->mapbase = port->mapbase;
2878 p->private_data = port->private_data;
125c97d8
HD		 2879 p->type = port->type;
2880 p->line = port->line;
7d6a07d1
DD		 2881
2882 set_io_from_upio(p);
2883 if (port->serial_in)
2884 p->serial_in = port->serial_in;
2885 if (port->serial_out)
2886 p->serial_out = port->serial_out;
2887
1da177e4
LT		 2888 return 0;
2889}
2890
2891/**
2892 * serial8250_suspend_port - suspend one serial port
2893 * @line: serial line number
1da177e4
LT		 2894 *
2895 * Suspend one serial port.
2896 */
2897void serial8250_suspend_port(int line)
2898{
2899 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2900}
2901
2902/**
2903 * serial8250_resume_port - resume one serial port
2904 * @line: serial line number
1da177e4
LT		 2905 *
2906 * Resume one serial port.
2907 */
2908void serial8250_resume_port(int line)
2909{
b5b82df6
DW		 2910 struct uart_8250_port *up = &serial8250_ports[line];
2911
2912 if (up->capabilities & UART_NATSEMI) {
2913 unsigned char tmp;
2914
2915 /* Ensure it's still in high speed mode */
2916 serial_outp(up, UART_LCR, 0xE0);
2917
2918 tmp = serial_in(up, 0x04); /* EXCR2 */
2919 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2920 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2921 serial_outp(up, 0x04, tmp);
2922
2923 serial_outp(up, UART_LCR, 0);
2924 }
2925 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 2926}
2927
2928/*
2929 * Register a set of serial devices attached to a platform device. The
2930 * list is terminated with a zero flags entry, which means we expect
2931 * all entries to have at least UPF_BOOT_AUTOCONF set.
2932 */
3ae5eaec 2933static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2934{
3ae5eaec 2935 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2936 struct uart_port port;
ec9f47cd 2937 int ret, i;
1da177e4
LT		 2938
2939 memset(&port, 0, sizeof(struct uart_port));
2940
ec9f47cd 2941 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2942 port.iobase = p->iobase;
2943 port.membase = p->membase;
2944 port.irq = p->irq;
2945 port.uartclk = p->uartclk;
2946 port.regshift = p->regshift;
2947 port.iotype = p->iotype;
2948 port.flags = p->flags;
2949 port.mapbase = p->mapbase;
2950 port.hub6 = p->hub6;
2951 port.private_data = p->private_data;
8e23fcc8 2952 port.type = p->type;
7d6a07d1
DD		 2953 port.serial_in = p->serial_in;
2954 port.serial_out = p->serial_out;
74a19741 2955 port.dev = &dev->dev;
1da177e4
LT		 2956 if (share_irqs)
2957 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2958 ret = serial8250_register_port(&port);
2959 if (ret < 0) {
3ae5eaec 2960 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 2961 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2962 p->iobase, (unsigned long long)p->mapbase,
2963 p->irq, ret);
ec9f47cd 2964 }
1da177e4
LT		 2965 }
2966 return 0;
2967}
2968
2969/*
2970 * Remove serial ports registered against a platform device.
2971 */
3ae5eaec 2972static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2973{
2974 int i;
2975
a61c2d78 2976 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2977 struct uart_8250_port *up = &serial8250_ports[i];
2978
3ae5eaec 2979 if (up->port.dev == &dev->dev)
1da177e4
LT		 2980 serial8250_unregister_port(i);
2981 }
2982 return 0;
2983}
2984
3ae5eaec 2985static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2986{
2987 int i;
2988
1da177e4
LT		 2989 for (i = 0; i < UART_NR; i++) {
2990 struct uart_8250_port *up = &serial8250_ports[i];
2991
3ae5eaec 2992 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2993 uart_suspend_port(&serial8250_reg, &up->port);
2994 }
2995
2996 return 0;
2997}
2998
3ae5eaec 2999static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3000{
3001 int i;
3002
1da177e4
LT		 3003 for (i = 0; i < UART_NR; i++) {
3004 struct uart_8250_port *up = &serial8250_ports[i];
3005
3ae5eaec 3006 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3007 serial8250_resume_port(i);
1da177e4
LT		 3008 }
3009
3010 return 0;
3011}
3012
3ae5eaec 3013static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3014 .probe = serial8250_probe,
3015 .remove = __devexit_p(serial8250_remove),
3016 .suspend = serial8250_suspend,
3017 .resume = serial8250_resume,
3ae5eaec
RK		 3018 .driver = {
3019 .name = "serial8250",
7493a314 3020 .owner = THIS_MODULE,
3ae5eaec 3021 },
1da177e4
LT		 3022};
3023
3024/*
3025 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3026 * in the table in include/asm/serial.h
3027 */
3028static struct platform_device *serial8250_isa_devs;
3029
3030/*
3031 * serial8250_register_port and serial8250_unregister_port allows for
3032 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3033 * modems and PCI multiport cards.
3034 */
f392ecfa 3035static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3036
3037static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3038{
3039 int i;
3040
3041 /*
3042 * First, find a port entry which matches.
3043 */
a61c2d78 3044 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3045 if (uart_match_port(&serial8250_ports[i].port, port))
3046 return &serial8250_ports[i];
3047
3048 /*
3049 * We didn't find a matching entry, so look for the first
3050 * free entry. We look for one which hasn't been previously
3051 * used (indicated by zero iobase).
3052 */
a61c2d78 3053 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3054 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3055 serial8250_ports[i].port.iobase == 0)
3056 return &serial8250_ports[i];
3057
3058 /*
3059 * That also failed. Last resort is to find any entry which
3060 * doesn't have a real port associated with it.
3061 */
a61c2d78 3062 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3063 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3064 return &serial8250_ports[i];
3065
3066 return NULL;
3067}
3068
3069/**
3070 * serial8250_register_port - register a serial port
3071 * @port: serial port template
3072 *
3073 * Configure the serial port specified by the request. If the
3074 * port exists and is in use, it is hung up and unregistered
3075 * first.
3076 *
3077 * The port is then probed and if necessary the IRQ is autodetected
3078 * If this fails an error is returned.
3079 *
3080 * On success the port is ready to use and the line number is returned.
3081 */
3082int serial8250_register_port(struct uart_port *port)
3083{
3084 struct uart_8250_port *uart;
3085 int ret = -ENOSPC;
3086
3087 if (port->uartclk == 0)
3088 return -EINVAL;
3089
f392ecfa 3090 mutex_lock(&serial_mutex);
1da177e4
LT		 3091
3092 uart = serial8250_find_match_or_unused(port);
3093 if (uart) {
3094 uart_remove_one_port(&serial8250_reg, &uart->port);
3095
74a19741
WN		 3096 uart->port.iobase = port->iobase;
3097 uart->port.membase = port->membase;
3098 uart->port.irq = port->irq;
3099 uart->port.uartclk = port->uartclk;
3100 uart->port.fifosize = port->fifosize;
3101 uart->port.regshift = port->regshift;
3102 uart->port.iotype = port->iotype;
3103 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3104 uart->port.mapbase = port->mapbase;
3105 uart->port.private_data = port->private_data;
1da177e4
LT		 3106 if (port->dev)
3107 uart->port.dev = port->dev;
8e23fcc8
DD		 3108
3109 if (port->flags & UPF_FIXED_TYPE) {
3110 uart->port.type = port->type;
3111 uart->port.fifosize = uart_config[port->type].fifo_size;
3112 uart->capabilities = uart_config[port->type].flags;
3113 uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3114 }
3115
7d6a07d1
DD		 3116 set_io_from_upio(&uart->port);
3117 /* Possibly override default I/O functions. */
3118 if (port->serial_in)
3119 uart->port.serial_in = port->serial_in;
3120 if (port->serial_out)
3121 uart->port.serial_out = port->serial_out;
1da177e4
LT		 3122
3123 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3124 if (ret == 0)
3125 ret = uart->port.line;
3126 }
f392ecfa 3127 mutex_unlock(&serial_mutex);
1da177e4
LT		 3128
3129 return ret;
3130}
3131EXPORT_SYMBOL(serial8250_register_port);
3132
3133/**
3134 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3135 * @line: serial line number
3136 *
3137 * Remove one serial port. This may not be called from interrupt
3138 * context. We hand the port back to the our control.
3139 */
3140void serial8250_unregister_port(int line)
3141{
3142 struct uart_8250_port *uart = &serial8250_ports[line];
3143
f392ecfa 3144 mutex_lock(&serial_mutex);
1da177e4
LT		 3145 uart_remove_one_port(&serial8250_reg, &uart->port);
3146 if (serial8250_isa_devs) {
3147 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3148 uart->port.type = PORT_UNKNOWN;
3149 uart->port.dev = &serial8250_isa_devs->dev;
3150 uart_add_one_port(&serial8250_reg, &uart->port);
3151 } else {
3152 uart->port.dev = NULL;
3153 }
f392ecfa 3154 mutex_unlock(&serial_mutex);
1da177e4
LT		 3155}
3156EXPORT_SYMBOL(serial8250_unregister_port);
3157
3158static int __init serial8250_init(void)
3159{
25db8ad5 3160 int ret;
1da177e4 3161
a61c2d78
DJ		 3162 if (nr_uarts > UART_NR)
3163 nr_uarts = UART_NR;
3164
f1fb9bb8 3165 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3166 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3167 share_irqs ? "en" : "dis");
3168
b70ac771
DM		 3169#ifdef CONFIG_SPARC
3170 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3171#else
3172 serial8250_reg.nr = UART_NR;
1da177e4 3173 ret = uart_register_driver(&serial8250_reg);
b70ac771 3174#endif
1da177e4
LT		 3175 if (ret)
3176 goto out;
3177
7493a314
DT		 3178 serial8250_isa_devs = platform_device_alloc("serial8250",
3179 PLAT8250_DEV_LEGACY);
3180 if (!serial8250_isa_devs) {
3181 ret = -ENOMEM;
bc965a7f 3182 goto unreg_uart_drv;
1da177e4
LT		 3183 }
3184
7493a314
DT		 3185 ret = platform_device_add(serial8250_isa_devs);
3186 if (ret)
3187 goto put_dev;
3188
1da177e4
LT		 3189 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3190
bc965a7f
RK		 3191 ret = platform_driver_register(&serial8250_isa_driver);
3192 if (ret == 0)
3193 goto out;
1da177e4 3194
bc965a7f 3195 platform_device_del(serial8250_isa_devs);
25db8ad5 3196put_dev:
7493a314 3197 platform_device_put(serial8250_isa_devs);
25db8ad5 3198unreg_uart_drv:
b70ac771
DM		 3199#ifdef CONFIG_SPARC
3200 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3201#else
1da177e4 3202 uart_unregister_driver(&serial8250_reg);
b70ac771 3203#endif
25db8ad5 3204out:
1da177e4
LT		 3205 return ret;
3206}
3207
3208static void __exit serial8250_exit(void)
3209{
3210 struct platform_device *isa_dev = serial8250_isa_devs;
3211
3212 /*
3213 * This tells serial8250_unregister_port() not to re-register
3214 * the ports (thereby making serial8250_isa_driver permanently
3215 * in use.)
3216 */
3217 serial8250_isa_devs = NULL;
3218
3ae5eaec 3219 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3220 platform_device_unregister(isa_dev);
3221
b70ac771
DM		 3222#ifdef CONFIG_SPARC
3223 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3224#else
1da177e4 3225 uart_unregister_driver(&serial8250_reg);
b70ac771 3226#endif
1da177e4
LT		 3227}
3228
3229module_init(serial8250_init);
3230module_exit(serial8250_exit);
3231
3232EXPORT_SYMBOL(serial8250_suspend_port);
3233EXPORT_SYMBOL(serial8250_resume_port);
3234
3235MODULE_LICENSE("GPL");
d87a6d95 3236MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3237
3238module_param(share_irqs, uint, 0644);
3239MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3240 " (unsafe)");
3241
a61c2d78
DJ		 3242module_param(nr_uarts, uint, 0644);
3243MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3244
1da177e4
LT		 3245#ifdef CONFIG_SERIAL_8250_RSA
3246module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3247MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3248#endif
3249MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
kernel source for telekom puls (alcatel/mediatek)