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e0eca63e VH |
1 | /* |
2 | * Universal Flash Storage Host controller driver | |
3 | * | |
4 | * This code is based on drivers/scsi/ufs/ufshcd.h | |
5 | * Copyright (C) 2011-2013 Samsung India Software Operations | |
dc3c8d3a | 6 | * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
e0eca63e VH |
7 | * |
8 | * Authors: | |
9 | * Santosh Yaraganavi <santosh.sy@samsung.com> | |
10 | * Vinayak Holikatti <h.vinayak@samsung.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version 2 | |
15 | * of the License, or (at your option) any later version. | |
16 | * See the COPYING file in the top-level directory or visit | |
17 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * This program is provided "AS IS" and "WITH ALL FAULTS" and | |
25 | * without warranty of any kind. You are solely responsible for | |
26 | * determining the appropriateness of using and distributing | |
27 | * the program and assume all risks associated with your exercise | |
28 | * of rights with respect to the program, including but not limited | |
29 | * to infringement of third party rights, the risks and costs of | |
30 | * program errors, damage to or loss of data, programs or equipment, | |
31 | * and unavailability or interruption of operations. Under no | |
32 | * circumstances will the contributor of this Program be liable for | |
33 | * any damages of any kind arising from your use or distribution of | |
34 | * this program. | |
35 | */ | |
36 | ||
37 | #ifndef _UFSHCD_H | |
38 | #define _UFSHCD_H | |
39 | ||
40 | #include <linux/module.h> | |
41 | #include <linux/kernel.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/io.h> | |
45 | #include <linux/delay.h> | |
46 | #include <linux/slab.h> | |
47 | #include <linux/spinlock.h> | |
a3cd5ec5 | 48 | #include <linux/rwsem.h> |
e0eca63e VH |
49 | #include <linux/workqueue.h> |
50 | #include <linux/errno.h> | |
51 | #include <linux/types.h> | |
52 | #include <linux/wait.h> | |
53 | #include <linux/bitops.h> | |
54 | #include <linux/pm_runtime.h> | |
55 | #include <linux/clk.h> | |
6ccf44fe | 56 | #include <linux/completion.h> |
aa497613 | 57 | #include <linux/regulator/consumer.h> |
508cb48c | 58 | #include <linux/pm_qos.h> |
f37aabcf | 59 | #include "unipro.h" |
e0eca63e VH |
60 | |
61 | #include <asm/irq.h> | |
62 | #include <asm/byteorder.h> | |
63 | #include <scsi/scsi.h> | |
64 | #include <scsi/scsi_cmnd.h> | |
65 | #include <scsi/scsi_host.h> | |
66 | #include <scsi/scsi_tcq.h> | |
67 | #include <scsi/scsi_dbg.h> | |
68 | #include <scsi/scsi_eh.h> | |
071b73ac | 69 | #include <scsi/scsi_ioctl.h> |
e0eca63e VH |
70 | |
71 | #include "ufs.h" | |
72 | #include "ufshci.h" | |
a72c5add | 73 | #include "ufs_quirks.h" |
e0eca63e VH |
74 | |
75 | #define UFSHCD "ufshcd" | |
76 | #define UFSHCD_DRIVER_VERSION "0.2" | |
77 | ||
5c0c28a8 SRT |
78 | struct ufs_hba; |
79 | ||
5a0b0cb9 SRT |
80 | enum dev_cmd_type { |
81 | DEV_CMD_TYPE_NOP = 0x0, | |
68078d5c | 82 | DEV_CMD_TYPE_QUERY = 0x1, |
5a0b0cb9 SRT |
83 | }; |
84 | ||
e0eca63e VH |
85 | /** |
86 | * struct uic_command - UIC command structure | |
87 | * @command: UIC command | |
88 | * @argument1: UIC command argument 1 | |
89 | * @argument2: UIC command argument 2 | |
90 | * @argument3: UIC command argument 3 | |
91 | * @cmd_active: Indicate if UIC command is outstanding | |
92 | * @result: UIC command result | |
6ccf44fe | 93 | * @done: UIC command completion |
e0eca63e VH |
94 | */ |
95 | struct uic_command { | |
96 | u32 command; | |
97 | u32 argument1; | |
98 | u32 argument2; | |
99 | u32 argument3; | |
100 | int cmd_active; | |
101 | int result; | |
6ccf44fe | 102 | struct completion done; |
e0eca63e VH |
103 | }; |
104 | ||
57d104c1 SJ |
105 | /* Used to differentiate the power management options */ |
106 | enum ufs_pm_op { | |
107 | UFS_RUNTIME_PM, | |
108 | UFS_SYSTEM_PM, | |
109 | UFS_SHUTDOWN_PM, | |
110 | }; | |
111 | ||
112 | #define ufshcd_is_runtime_pm(op) ((op) == UFS_RUNTIME_PM) | |
113 | #define ufshcd_is_system_pm(op) ((op) == UFS_SYSTEM_PM) | |
114 | #define ufshcd_is_shutdown_pm(op) ((op) == UFS_SHUTDOWN_PM) | |
115 | ||
116 | /* Host <-> Device UniPro Link state */ | |
117 | enum uic_link_state { | |
118 | UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ | |
119 | UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ | |
120 | UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ | |
5801290e | 121 | UIC_LINK_TRANS_ACTIVE_STATE = 3, |
122 | UIC_LINK_TRANS_HIBERN8_STATE = 4, | |
57d104c1 SJ |
123 | }; |
124 | ||
125 | #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) | |
126 | #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ | |
127 | UIC_LINK_ACTIVE_STATE) | |
128 | #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ | |
129 | UIC_LINK_HIBERN8_STATE) | |
130 | #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) | |
131 | #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ | |
132 | UIC_LINK_ACTIVE_STATE) | |
133 | #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ | |
134 | UIC_LINK_HIBERN8_STATE) | |
5801290e | 135 | #define ufshcd_set_link_trans_active(hba) ((hba)->uic_link_state = \ |
136 | UIC_LINK_TRANS_ACTIVE_STATE) | |
137 | #define ufshcd_set_link_trans_hibern8(hba) ((hba)->uic_link_state = \ | |
138 | UIC_LINK_TRANS_HIBERN8_STATE) | |
57d104c1 SJ |
139 | /* |
140 | * UFS Power management levels. | |
141 | * Each level is in increasing order of power savings. | |
142 | */ | |
143 | enum ufs_pm_level { | |
144 | UFS_PM_LVL_0, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE */ | |
145 | UFS_PM_LVL_1, /* UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE */ | |
146 | UFS_PM_LVL_2, /* UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE */ | |
147 | UFS_PM_LVL_3, /* UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE */ | |
148 | UFS_PM_LVL_4, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE */ | |
149 | UFS_PM_LVL_5, /* UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE */ | |
150 | UFS_PM_LVL_MAX | |
151 | }; | |
152 | ||
153 | struct ufs_pm_lvl_states { | |
154 | enum ufs_dev_pwr_mode dev_state; | |
155 | enum uic_link_state link_state; | |
156 | }; | |
157 | ||
e0eca63e VH |
158 | /** |
159 | * struct ufshcd_lrb - local reference block | |
160 | * @utr_descriptor_ptr: UTRD address of the command | |
5a0b0cb9 | 161 | * @ucd_req_ptr: UCD address of the command |
e0eca63e VH |
162 | * @ucd_rsp_ptr: Response UPIU address for this command |
163 | * @ucd_prdt_ptr: PRDT address of the command | |
ff8e20c6 DR |
164 | * @utrd_dma_addr: UTRD dma address for debug |
165 | * @ucd_prdt_dma_addr: PRDT dma address for debug | |
166 | * @ucd_rsp_dma_addr: UPIU response dma address for debug | |
167 | * @ucd_req_dma_addr: UPIU request dma address for debug | |
e0eca63e VH |
168 | * @cmd: pointer to SCSI command |
169 | * @sense_buffer: pointer to sense buffer address of the SCSI command | |
170 | * @sense_bufflen: Length of the sense buffer | |
171 | * @scsi_status: SCSI status of the command | |
172 | * @command_type: SCSI, UFS, Query. | |
173 | * @task_tag: Task tag of the command | |
174 | * @lun: LUN of the command | |
5a0b0cb9 | 175 | * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) |
ff8e20c6 | 176 | * @issue_time_stamp: time stamp for debug purposes |
e0b299e3 | 177 | * @req_abort_skip: skip request abort task flag |
e0eca63e VH |
178 | */ |
179 | struct ufshcd_lrb { | |
180 | struct utp_transfer_req_desc *utr_descriptor_ptr; | |
5a0b0cb9 | 181 | struct utp_upiu_req *ucd_req_ptr; |
e0eca63e VH |
182 | struct utp_upiu_rsp *ucd_rsp_ptr; |
183 | struct ufshcd_sg_entry *ucd_prdt_ptr; | |
184 | ||
ff8e20c6 DR |
185 | dma_addr_t utrd_dma_addr; |
186 | dma_addr_t ucd_req_dma_addr; | |
187 | dma_addr_t ucd_rsp_dma_addr; | |
188 | dma_addr_t ucd_prdt_dma_addr; | |
189 | ||
e0eca63e VH |
190 | struct scsi_cmnd *cmd; |
191 | u8 *sense_buffer; | |
192 | unsigned int sense_bufflen; | |
193 | int scsi_status; | |
194 | ||
195 | int command_type; | |
196 | int task_tag; | |
0ce147d4 | 197 | u8 lun; /* UPIU LUN id field is only 8-bit wide */ |
5a0b0cb9 | 198 | bool intr_cmd; |
ff8e20c6 | 199 | ktime_t issue_time_stamp; |
e0b299e3 GB |
200 | |
201 | bool req_abort_skip; | |
e0eca63e VH |
202 | }; |
203 | ||
68078d5c | 204 | /** |
a230c2f6 | 205 | * struct ufs_query - holds relevant data structures for query request |
68078d5c DR |
206 | * @request: request upiu and function |
207 | * @descriptor: buffer for sending/receiving descriptor | |
208 | * @response: response upiu and response | |
209 | */ | |
210 | struct ufs_query { | |
211 | struct ufs_query_req request; | |
212 | u8 *descriptor; | |
213 | struct ufs_query_res response; | |
214 | }; | |
215 | ||
5a0b0cb9 SRT |
216 | /** |
217 | * struct ufs_dev_cmd - all assosiated fields with device management commands | |
218 | * @type: device management command type - Query, NOP OUT | |
219 | * @lock: lock to allow one command at a time | |
220 | * @complete: internal commands completion | |
221 | * @tag_wq: wait queue until free command slot is available | |
222 | */ | |
223 | struct ufs_dev_cmd { | |
224 | enum dev_cmd_type type; | |
225 | struct mutex lock; | |
226 | struct completion *complete; | |
227 | wait_queue_head_t tag_wq; | |
68078d5c | 228 | struct ufs_query query; |
5a0b0cb9 | 229 | }; |
e0eca63e | 230 | |
dd528aaa | 231 | /** |
232 | * ufs_hba_variant: host specific data | |
233 | */ | |
234 | struct ufs_hba_variant { | |
235 | const struct ufs_hba_variant_ops *ops; | |
236 | u32 quirks; | |
237 | void *vs_data; | |
238 | }; | |
a4b0e8a4 PM |
239 | struct ufs_desc_size { |
240 | int dev_desc; | |
241 | int pwr_desc; | |
242 | int geom_desc; | |
243 | int interc_desc; | |
244 | int unit_desc; | |
245 | int conf_desc; | |
246 | }; | |
247 | ||
c6e79dac SRT |
248 | /** |
249 | * struct ufs_clk_info - UFS clock related info | |
250 | * @list: list headed by hba->clk_list_head | |
251 | * @clk: clock node | |
252 | * @name: clock name | |
253 | * @max_freq: maximum frequency supported by the clock | |
4cff6d99 | 254 | * @min_freq: min frequency that can be used for clock scaling |
856b3483 | 255 | * @curr_freq: indicates the current frequency that it is set to |
c6e79dac SRT |
256 | * @enabled: variable to check against multiple enable/disable |
257 | */ | |
258 | struct ufs_clk_info { | |
259 | struct list_head list; | |
260 | struct clk *clk; | |
261 | const char *name; | |
262 | u32 max_freq; | |
4cff6d99 | 263 | u32 min_freq; |
856b3483 | 264 | u32 curr_freq; |
c6e79dac SRT |
265 | bool enabled; |
266 | }; | |
267 | ||
f06fcc71 YG |
268 | enum ufs_notify_change_status { |
269 | PRE_CHANGE, | |
270 | POST_CHANGE, | |
271 | }; | |
7eb584db DR |
272 | |
273 | struct ufs_pa_layer_attr { | |
274 | u32 gear_rx; | |
275 | u32 gear_tx; | |
276 | u32 lane_rx; | |
277 | u32 lane_tx; | |
278 | u32 pwr_rx; | |
279 | u32 pwr_tx; | |
280 | u32 hs_rate; | |
72c97747 | 281 | u32 peer_available_lane_rx; |
282 | u32 peer_available_lane_tx; | |
7eb584db DR |
283 | }; |
284 | ||
285 | struct ufs_pwr_mode_info { | |
286 | bool is_valid; | |
287 | struct ufs_pa_layer_attr info; | |
288 | }; | |
289 | ||
5c0c28a8 SRT |
290 | /** |
291 | * struct ufs_hba_variant_ops - variant specific callbacks | |
292 | * @name: variant name | |
293 | * @init: called when the driver is initialized | |
294 | * @exit: called to cleanup everything done in init | |
9949e702 | 295 | * @get_ufs_hci_version: called to get UFS HCI version |
856b3483 | 296 | * @clk_scale_notify: notifies that clks are scaled up/down |
5c0c28a8 SRT |
297 | * @setup_clocks: called before touching any of the controller registers |
298 | * @setup_regulators: called before accessing the host controller | |
299 | * @hce_enable_notify: called before and after HCE enable bit is set to allow | |
300 | * variant specific Uni-Pro initialization. | |
301 | * @link_startup_notify: called before and after Link startup is carried out | |
302 | * to allow variant specific Uni-Pro initialization. | |
7eb584db DR |
303 | * @pwr_change_notify: called before and after a power mode change |
304 | * is carried out to allow vendor spesific capabilities | |
305 | * to be set. | |
2767a662 | 306 | |
ee32c909 | 307 | * @hibern8_notify: called around hibern8 enter/exit |
2767a662 | 308 | |
57d104c1 SJ |
309 | * @suspend: called during host controller PM callback |
310 | * @resume: called during host controller PM callback | |
6e3fd44d | 311 | * @dbg_register_dump: used to dump controller debug information |
4b9ffb5a | 312 | * @phy_initialization: used to initialize phys |
5c0c28a8 SRT |
313 | */ |
314 | struct ufs_hba_variant_ops { | |
315 | const char *name; | |
316 | int (*init)(struct ufs_hba *); | |
317 | void (*exit)(struct ufs_hba *); | |
9949e702 | 318 | u32 (*get_ufs_hci_version)(struct ufs_hba *); |
f06fcc71 YG |
319 | int (*clk_scale_notify)(struct ufs_hba *, bool, |
320 | enum ufs_notify_change_status); | |
2767a662 | 321 | int (*pre_setup_clocks)(struct ufs_hba *, bool); |
322 | int (*setup_clocks)(struct ufs_hba *, bool); | |
5c0c28a8 | 323 | int (*setup_regulators)(struct ufs_hba *, bool); |
86cba8c7 | 324 | void (*host_reset)(struct ufs_hba *); |
f06fcc71 YG |
325 | int (*hce_enable_notify)(struct ufs_hba *, |
326 | enum ufs_notify_change_status); | |
327 | int (*link_startup_notify)(struct ufs_hba *, | |
328 | enum ufs_notify_change_status); | |
7eb584db | 329 | int (*pwr_change_notify)(struct ufs_hba *, |
f06fcc71 YG |
330 | enum ufs_notify_change_status status, |
331 | struct ufs_pa_layer_attr *, | |
7eb584db | 332 | struct ufs_pa_layer_attr *); |
03229397 | 333 | void (*set_nexus_t_xfer_req)(struct ufs_hba *, |
334 | int, struct scsi_cmnd *); | |
335 | void (*set_nexus_t_task_mgmt)(struct ufs_hba *, int, u8); | |
623b5fe3 | 336 | void (*hibern8_notify)(struct ufs_hba *, u8, bool); |
57d104c1 SJ |
337 | int (*suspend)(struct ufs_hba *, enum ufs_pm_op); |
338 | int (*resume)(struct ufs_hba *, enum ufs_pm_op); | |
6e3fd44d | 339 | void (*dbg_register_dump)(struct ufs_hba *hba); |
7ec8af94 | 340 | u8 (*get_unipro_result)(struct ufs_hba *hba, u32 num); |
4b9ffb5a | 341 | int (*phy_initialization)(struct ufs_hba *); |
66cae4a3 | 342 | int (*crypto_engine_cfg)(struct ufs_hba *, struct ufshcd_lrb *, |
49e3bbe3 | 343 | struct scatterlist *, int, int, int); |
66cae4a3 BK |
344 | int (*crypto_engine_clear)(struct ufs_hba *, struct ufshcd_lrb *); |
345 | int (*access_control_abort)(struct ufs_hba *); | |
346 | ||
5c0c28a8 SRT |
347 | }; |
348 | ||
1ab27c9c ST |
349 | /* clock gating state */ |
350 | enum clk_gating_state { | |
351 | CLKS_OFF, | |
352 | CLKS_ON, | |
353 | REQ_CLKS_OFF, | |
354 | REQ_CLKS_ON, | |
40e137af | 355 | __CLKS_ON, |
4b7fcf7e | 356 | CLKS_DISABLE = 0x99, |
1ab27c9c ST |
357 | }; |
358 | ||
359 | /** | |
360 | * struct ufs_clk_gating - UFS clock gating related info | |
361 | * @gate_work: worker to turn off clocks after some delay as specified in | |
362 | * delay_ms | |
363 | * @ungate_work: worker to turn on clocks that will be used in case of | |
364 | * interrupt context | |
365 | * @state: the current clocks state | |
366 | * @delay_ms: gating delay in ms | |
367 | * @is_suspended: clk gating is suspended when set to 1 which can be used | |
368 | * during suspend/resume | |
369 | * @delay_attr: sysfs attribute to control delay_attr | |
b427411a ST |
370 | * @enable_attr: sysfs attribute to enable/disable clock gating |
371 | * @is_enabled: Indicates the current status of clock gating | |
1ab27c9c ST |
372 | * @active_reqs: number of requests that are pending and should be waited for |
373 | * completion before gating clocks. | |
374 | */ | |
375 | struct ufs_clk_gating { | |
376 | struct delayed_work gate_work; | |
377 | struct work_struct ungate_work; | |
378 | enum clk_gating_state state; | |
379 | unsigned long delay_ms; | |
380 | bool is_suspended; | |
381 | struct device_attribute delay_attr; | |
b427411a ST |
382 | struct device_attribute enable_attr; |
383 | bool is_enabled; | |
1ab27c9c ST |
384 | int active_reqs; |
385 | }; | |
386 | ||
a3cd5ec5 SJ |
387 | struct ufs_saved_pwr_info { |
388 | struct ufs_pa_layer_attr info; | |
389 | bool is_valid; | |
390 | }; | |
391 | ||
401f1e44 SJ |
392 | /** |
393 | * struct ufs_clk_scaling - UFS clock scaling related data | |
394 | * @active_reqs: number of requests that are pending. If this is zero when | |
395 | * devfreq ->target() function is called then schedule "suspend_work" to | |
396 | * suspend devfreq. | |
397 | * @tot_busy_t: Total busy time in current polling window | |
398 | * @window_start_t: Start time (in jiffies) of the current polling window | |
399 | * @busy_start_t: Start time of current busy period | |
400 | * @enable_attr: sysfs attribute to enable/disable clock scaling | |
401 | * @saved_pwr_info: UFS power mode may also be changed during scaling and this | |
402 | * one keeps track of previous power mode. | |
403 | * @workq: workqueue to schedule devfreq suspend/resume work | |
404 | * @suspend_work: worker to suspend devfreq | |
405 | * @resume_work: worker to resume devfreq | |
406 | * @is_allowed: tracks if scaling is currently allowed or not | |
407 | * @is_busy_started: tracks if busy period has started or not | |
408 | * @is_suspended: tracks if devfreq is suspended or not | |
409 | */ | |
856b3483 | 410 | struct ufs_clk_scaling { |
401f1e44 SJ |
411 | int active_reqs; |
412 | unsigned long tot_busy_t; | |
856b3483 | 413 | unsigned long window_start_t; |
401f1e44 | 414 | ktime_t busy_start_t; |
fcb0c4b0 | 415 | struct device_attribute enable_attr; |
a3cd5ec5 | 416 | struct ufs_saved_pwr_info saved_pwr_info; |
401f1e44 SJ |
417 | struct workqueue_struct *workq; |
418 | struct work_struct suspend_work; | |
419 | struct work_struct resume_work; | |
420 | bool is_allowed; | |
421 | bool is_busy_started; | |
422 | bool is_suspended; | |
856b3483 ST |
423 | }; |
424 | ||
3a4bf06d YG |
425 | /** |
426 | * struct ufs_init_prefetch - contains data that is pre-fetched once during | |
427 | * initialization | |
428 | * @icc_level: icc level which was read during initialization | |
429 | */ | |
430 | struct ufs_init_prefetch { | |
431 | u32 icc_level; | |
2767a662 | 432 | }; |
9632ac5f | 433 | |
434 | /** | |
435 | * struct ufs_monitor - monitors ufs driver's behaviors | |
436 | */ | |
437 | struct ufs_monitor { | |
438 | struct device_attribute attrs; | |
439 | unsigned long flag; | |
440 | #define UFSHCD_MONITOR_LEVEL1 (1 << 0) | |
441 | #define UFSHCD_MONITOR_LEVEL2 (1 << 1) | |
442 | }; | |
2767a662 | 443 | |
444 | struct ufs_secure_log { | |
445 | unsigned long paddr; | |
446 | u32 *vaddr; | |
3a4bf06d YG |
447 | }; |
448 | ||
ff8e20c6 DR |
449 | #define UIC_ERR_REG_HIST_LENGTH 8 |
450 | /** | |
451 | * struct ufs_uic_err_reg_hist - keeps history of uic errors | |
452 | * @pos: index to indicate cyclic buffer position | |
453 | * @reg: cyclic buffer for registers value | |
454 | * @tstamp: cyclic buffer for time stamp | |
455 | */ | |
456 | struct ufs_uic_err_reg_hist { | |
457 | int pos; | |
458 | u32 reg[UIC_ERR_REG_HIST_LENGTH]; | |
459 | ktime_t tstamp[UIC_ERR_REG_HIST_LENGTH]; | |
460 | }; | |
461 | ||
462 | /** | |
463 | * struct ufs_stats - keeps usage/err statistics | |
464 | * @hibern8_exit_cnt: Counter to keep track of number of exits, | |
465 | * reset this after link-startup. | |
466 | * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. | |
467 | * Clear after the first successful command completion. | |
468 | * @pa_err: tracks pa-uic errors | |
469 | * @dl_err: tracks dl-uic errors | |
470 | * @nl_err: tracks nl-uic errors | |
471 | * @tl_err: tracks tl-uic errors | |
472 | * @dme_err: tracks dme errors | |
473 | */ | |
474 | struct ufs_stats { | |
475 | u32 hibern8_exit_cnt; | |
476 | ktime_t last_hibern8_exit_tstamp; | |
477 | struct ufs_uic_err_reg_hist pa_err; | |
478 | struct ufs_uic_err_reg_hist dl_err; | |
479 | struct ufs_uic_err_reg_hist nl_err; | |
480 | struct ufs_uic_err_reg_hist tl_err; | |
481 | struct ufs_uic_err_reg_hist dme_err; | |
482 | }; | |
483 | ||
e0eca63e VH |
484 | /** |
485 | * struct ufs_hba - per adapter private structure | |
486 | * @mmio_base: UFSHCI base register address | |
487 | * @ucdl_base_addr: UFS Command Descriptor base address | |
488 | * @utrdl_base_addr: UTP Transfer Request Descriptor base address | |
489 | * @utmrdl_base_addr: UTP Task Management Descriptor base address | |
490 | * @ucdl_dma_addr: UFS Command Descriptor DMA address | |
491 | * @utrdl_dma_addr: UTRDL DMA address | |
492 | * @utmrdl_dma_addr: UTMRDL DMA address | |
493 | * @host: Scsi_Host instance of the driver | |
494 | * @dev: device handle | |
495 | * @lrb: local reference block | |
5a0b0cb9 | 496 | * @lrb_in_use: lrb in use |
e0eca63e VH |
497 | * @outstanding_tasks: Bits representing outstanding task requests |
498 | * @outstanding_reqs: Bits representing outstanding transfer requests | |
499 | * @capabilities: UFS Controller Capabilities | |
500 | * @nutrs: Transfer Request Queue depth supported by controller | |
501 | * @nutmrs: Task Management Queue depth supported by controller | |
502 | * @ufs_version: UFS Version to which controller complies | |
5c0c28a8 SRT |
503 | * @vops: pointer to variant specific operations |
504 | * @priv: pointer to variant specific private data | |
e0eca63e VH |
505 | * @irq: Irq number of the controller |
506 | * @active_uic_cmd: handle of active UIC command | |
6ccf44fe | 507 | * @uic_cmd_mutex: mutex for uic command |
e2933132 SRT |
508 | * @tm_wq: wait queue for task management |
509 | * @tm_tag_wq: wait queue for free task management slots | |
510 | * @tm_slots_in_use: bit map of task management request slots in use | |
53b3d9c3 | 511 | * @pwr_done: completion for power mode change |
e0eca63e VH |
512 | * @tm_condition: condition variable for task management |
513 | * @ufshcd_state: UFSHCD states | |
3441da7d | 514 | * @eh_flags: Error handling flags |
2fbd009b | 515 | * @intr_mask: Interrupt Mask Bits |
66ec6d59 | 516 | * @ee_ctrl_mask: Exception event control mask |
1d337ec2 | 517 | * @is_powered: flag to check if HBA is powered |
3a4bf06d YG |
518 | * @is_init_prefetch: flag to check if data was pre-fetched in initialization |
519 | * @init_prefetch_data: data pre-fetched during initialization | |
e8e7f271 | 520 | * @eh_work: Worker to handle UFS errors that require s/w attention |
66ec6d59 | 521 | * @eeh_work: Worker to handle exception events |
e0eca63e | 522 | * @errors: HBA errors |
e8e7f271 SRT |
523 | * @uic_error: UFS interconnect layer error status |
524 | * @saved_err: sticky error mask | |
525 | * @saved_uic_err: sticky UIC error mask | |
5a0b0cb9 | 526 | * @dev_cmd: ufs device management command information |
cad2e03d | 527 | * @last_dme_cmd_tstamp: time stamp of the last completed DME command |
66ec6d59 | 528 | * @auto_bkops_enabled: to track whether bkops is enabled in device |
aa497613 | 529 | * @vreg_info: UFS device voltage regulator information |
c6e79dac | 530 | * @clk_list_head: UFS host controller clocks list node head |
7eb584db DR |
531 | * @pwr_info: holds current power mode |
532 | * @max_pwr_info: keeps the device max valid pwm | |
a4b0e8a4 | 533 | * @desc_size: descriptor sizes reported by device |
afdfff59 YG |
534 | * @urgent_bkops_lvl: keeps track of urgent bkops level for device |
535 | * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for | |
536 | * device is known or not. | |
e0eca63e VH |
537 | */ |
538 | struct ufs_hba { | |
539 | void __iomem *mmio_base; | |
540 | ||
541 | /* Virtual memory reference */ | |
542 | struct utp_transfer_cmd_desc *ucdl_base_addr; | |
543 | struct utp_transfer_req_desc *utrdl_base_addr; | |
544 | struct utp_task_req_desc *utmrdl_base_addr; | |
545 | ||
546 | /* DMA memory reference */ | |
547 | dma_addr_t ucdl_dma_addr; | |
548 | dma_addr_t utrdl_dma_addr; | |
549 | dma_addr_t utmrdl_dma_addr; | |
550 | ||
551 | struct Scsi_Host *host; | |
552 | struct device *dev; | |
2a8fa600 SJ |
553 | /* |
554 | * This field is to keep a reference to "scsi_device" corresponding to | |
555 | * "UFS device" W-LU. | |
556 | */ | |
557 | struct scsi_device *sdev_ufs_device; | |
071b73ac | 558 | struct scsi_device *sdev_rpmb; |
e0eca63e | 559 | |
57d104c1 SJ |
560 | enum ufs_dev_pwr_mode curr_dev_pwr_mode; |
561 | enum uic_link_state uic_link_state; | |
562 | /* Desired UFS power management level during runtime PM */ | |
563 | enum ufs_pm_level rpm_lvl; | |
564 | /* Desired UFS power management level during system PM */ | |
565 | enum ufs_pm_level spm_lvl; | |
09690d5a SJ |
566 | struct device_attribute rpm_lvl_attr; |
567 | struct device_attribute spm_lvl_attr; | |
57d104c1 | 568 | int pm_op_in_progress; |
2767a662 | 569 | bool async_resume; |
57d104c1 | 570 | |
e0eca63e | 571 | struct ufshcd_lrb *lrb; |
623b5fe3 | 572 | volatile unsigned long lrb_in_use; |
e0eca63e VH |
573 | |
574 | unsigned long outstanding_tasks; | |
575 | unsigned long outstanding_reqs; | |
576 | ||
577 | u32 capabilities; | |
578 | int nutrs; | |
579 | int nutmrs; | |
580 | u32 ufs_version; | |
03229397 | 581 | const struct ufs_hba_variant_ops *vops; |
5c0c28a8 | 582 | void *priv; |
e0eca63e | 583 | unsigned int irq; |
57d104c1 | 584 | bool is_irq_enabled; |
e0eca63e | 585 | |
b852190e YG |
586 | /* Interrupt aggregation support is broken */ |
587 | #define UFSHCD_QUIRK_BROKEN_INTR_AGGR UFS_BIT(0) | |
588 | ||
cad2e03d YG |
589 | /* |
590 | * delay before each dme command is required as the unipro | |
591 | * layer has shown instabilities | |
592 | */ | |
b852190e YG |
593 | #define UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS UFS_BIT(1) |
594 | ||
7ca38cf3 YG |
595 | /* |
596 | * If UFS host controller is having issue in processing LCC (Line | |
597 | * Control Command) coming from device then enable this quirk. | |
598 | * When this quirk is enabled, host controller driver should disable | |
599 | * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE | |
600 | * attribute of device to 0). | |
601 | */ | |
602 | #define UFSHCD_QUIRK_BROKEN_LCC UFS_BIT(2) | |
cad2e03d | 603 | |
c3a2f9ee YG |
604 | /* |
605 | * The attribute PA_RXHSUNTERMCAP specifies whether or not the | |
606 | * inbound Link supports unterminated line in HS mode. Setting this | |
607 | * attribute to 1 fixes moving to HS gear. | |
608 | */ | |
609 | #define UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP UFS_BIT(3) | |
610 | ||
874237f7 YG |
611 | /* |
612 | * This quirk needs to be enabled if the host contoller only allows | |
613 | * accessing the peer dme attributes in AUTO mode (FAST AUTO or | |
614 | * SLOW AUTO). | |
615 | */ | |
616 | #define UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE UFS_BIT(4) | |
617 | ||
9949e702 YG |
618 | /* |
619 | * This quirk needs to be enabled if the host contoller doesn't | |
620 | * advertise the correct version in UFS_VER register. If this quirk | |
621 | * is enabled, standard UFS host driver will call the vendor specific | |
622 | * ops (get_ufs_hci_version) to get the correct version. | |
623 | */ | |
624 | #define UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION UFS_BIT(5) | |
625 | ||
86b7a91c | 626 | #define UFSHCD_QUIRK_BROKEN_REQ_LIST_CLR UFS_BIT(6) |
75b1cc4a KK |
627 | /* |
628 | * This quirk needs to be enabled if the host contoller regards | |
629 | * resolution of the values of PRDTO and PRDTL in UTRD as byte. | |
630 | */ | |
631 | #define UFSHCD_QUIRK_PRDT_BYTE_GRAN UFS_BIT(7) | |
632 | ||
623b5fe3 | 633 | #define UFSHCD_QUIRK_USE_OF_HCE UFS_BIT(8) |
2767a662 | 634 | #define UFSHCD_QUIRK_GET_UPMCRS_DIRECT UFS_BIT(9) |
7e1cdfbd | 635 | #define UFSHCI_QUIRK_SKIP_INTR_AGGR UFS_BIT(10) |
02527a32 | 636 | #define UFSHCD_QUIRK_GET_GENERRCODE_DIRECT UFS_BIT(11) |
b78d1b6e | 637 | #define UFSHCD_QUIRK_UNRESET_INTR_AGGR UFS_BIT(12) |
2767a662 | 638 | |
cad2e03d | 639 | unsigned int quirks; /* Deviations from standard UFSHCI spec. */ |
6ccf44fe | 640 | |
c58ab7aa YG |
641 | /* Device deviations from standard UFS device spec. */ |
642 | unsigned int dev_quirks; | |
643 | ||
e2933132 SRT |
644 | wait_queue_head_t tm_wq; |
645 | wait_queue_head_t tm_tag_wq; | |
e0eca63e | 646 | unsigned long tm_condition; |
e2933132 | 647 | unsigned long tm_slots_in_use; |
e0eca63e | 648 | |
57d104c1 SJ |
649 | struct uic_command *active_uic_cmd; |
650 | struct mutex uic_cmd_mutex; | |
651 | struct completion *uic_async_done; | |
53b3d9c3 | 652 | |
e0eca63e | 653 | u32 ufshcd_state; |
3441da7d | 654 | u32 eh_flags; |
2fbd009b | 655 | u32 intr_mask; |
60916a7e | 656 | u32 transferred_sector; |
66ec6d59 | 657 | u16 ee_ctrl_mask; |
1d337ec2 | 658 | bool is_powered; |
3a4bf06d YG |
659 | bool is_init_prefetch; |
660 | struct ufs_init_prefetch init_prefetch_data; | |
e0eca63e VH |
661 | |
662 | /* Work Queues */ | |
9087ff6a | 663 | struct workqueue_struct *ufshcd_workq; |
e8e7f271 | 664 | struct work_struct eh_work; |
66ec6d59 | 665 | struct work_struct eeh_work; |
e0eca63e VH |
666 | |
667 | /* HBA Errors */ | |
668 | u32 errors; | |
e8e7f271 SRT |
669 | u32 uic_error; |
670 | u32 saved_err; | |
671 | u32 saved_uic_err; | |
e2d02234 | 672 | u32 saved_uic_phy_err_cnt; |
ff8e20c6 | 673 | struct ufs_stats ufs_stats; |
5a0b0cb9 | 674 | |
a60d7ef4 | 675 | u32 tcx_replay_timer_expired_cnt; |
676 | u32 fcx_protection_timer_expired_cnt; | |
677 | ||
5a0b0cb9 SRT |
678 | /* Device management request data */ |
679 | struct ufs_dev_cmd dev_cmd; | |
cad2e03d | 680 | ktime_t last_dme_cmd_tstamp; |
66ec6d59 | 681 | |
57d104c1 SJ |
682 | /* Keeps information of the UFS device connected to this host */ |
683 | struct ufs_dev_info dev_info; | |
66ec6d59 | 684 | bool auto_bkops_enabled; |
aa497613 | 685 | struct ufs_vreg_info vreg_info; |
c6e79dac | 686 | struct list_head clk_list_head; |
57d104c1 SJ |
687 | |
688 | bool wlun_dev_clr_ua; | |
7eb584db | 689 | |
7fabb77b GB |
690 | /* Number of requests aborts */ |
691 | int req_abort_count; | |
692 | ||
54b879b7 YG |
693 | /* Number of lanes available (1 or 2) for Rx/Tx */ |
694 | u32 lanes_per_direction; | |
7eb584db DR |
695 | struct ufs_pa_layer_attr pwr_info; |
696 | struct ufs_pwr_mode_info max_pwr_info; | |
1ab27c9c ST |
697 | |
698 | struct ufs_clk_gating clk_gating; | |
699 | /* Control to enable/disable host capabilities */ | |
700 | u32 caps; | |
701 | /* Allow dynamic clk gating */ | |
702 | #define UFSHCD_CAP_CLK_GATING (1 << 0) | |
703 | /* Allow hiberb8 with clk gating */ | |
704 | #define UFSHCD_CAP_HIBERN8_WITH_CLK_GATING (1 << 1) | |
856b3483 ST |
705 | /* Allow dynamic clk scaling */ |
706 | #define UFSHCD_CAP_CLK_SCALING (1 << 2) | |
374a246e SJ |
707 | /* Allow auto bkops to enabled during runtime suspend */ |
708 | #define UFSHCD_CAP_AUTO_BKOPS_SUSPEND (1 << 3) | |
b852190e YG |
709 | /* |
710 | * This capability allows host controller driver to use the UFS HCI's | |
711 | * interrupt aggregation capability. | |
712 | * CAUTION: Enabling this might reduce overall UFS throughput. | |
713 | */ | |
714 | #define UFSHCD_CAP_INTR_AGGR (1 << 4) | |
4e768e76 SJ |
715 | /* |
716 | * This capability allows the device auto-bkops to be always enabled | |
717 | * except during suspend (both runtime and suspend). | |
718 | * Enabling this capability means that device will always be allowed | |
719 | * to do background operation when it's active but it might degrade | |
720 | * the performance of ongoing read/write operations. | |
721 | */ | |
722 | #define UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND (1 << 5) | |
856b3483 | 723 | |
2767a662 | 724 | /* Allow only hibern8 without clk gating */ |
725 | #define UFSHCD_CAP_FAKE_CLK_GATING (1 << 6) | |
726 | ||
856b3483 ST |
727 | struct devfreq *devfreq; |
728 | struct ufs_clk_scaling clk_scaling; | |
e785060e | 729 | bool is_sys_suspended; |
afdfff59 | 730 | |
a72c5add | 731 | char unique_number[UFS_UN_MAX_DIGITS]; |
732 | ||
9632ac5f | 733 | struct ufs_monitor monitor; |
734 | ||
afdfff59 YG |
735 | enum bkops_status urgent_bkops_lvl; |
736 | bool is_urgent_bkops_lvl_checked; | |
a3cd5ec5 SJ |
737 | |
738 | struct rw_semaphore clk_scaling_lock; | |
a4b0e8a4 | 739 | struct ufs_desc_size desc_size; |
2767a662 | 740 | struct ufs_secure_log secure_log; |
e0eca63e VH |
741 | }; |
742 | ||
1ab27c9c ST |
743 | /* Returns true if clocks can be gated. Otherwise false */ |
744 | static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) | |
745 | { | |
746 | return hba->caps & UFSHCD_CAP_CLK_GATING; | |
747 | } | |
748 | static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) | |
749 | { | |
750 | return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; | |
751 | } | |
fcb0c4b0 | 752 | static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) |
856b3483 ST |
753 | { |
754 | return hba->caps & UFSHCD_CAP_CLK_SCALING; | |
755 | } | |
374a246e SJ |
756 | static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) |
757 | { | |
758 | return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; | |
759 | } | |
760 | ||
b852190e YG |
761 | static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) |
762 | { | |
4b9ffb5a JP |
763 | /* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/ |
764 | #ifndef CONFIG_SCSI_UFS_DWC | |
b852190e YG |
765 | if ((hba->caps & UFSHCD_CAP_INTR_AGGR) && |
766 | !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR)) | |
767 | return true; | |
768 | else | |
769 | return false; | |
4b9ffb5a JP |
770 | #else |
771 | return true; | |
772 | #endif | |
b852190e | 773 | } |
b78d1b6e | 774 | |
775 | static inline bool ufshcd_can_reset_intr_aggr(struct ufs_hba *hba) | |
776 | { | |
777 | return hba->quirks & UFSHCD_QUIRK_UNRESET_INTR_AGGR; | |
778 | } | |
779 | ||
5801290e | 780 | static inline bool ufshcd_can_fake_clkgating(struct ufs_hba *hba) |
781 | { | |
782 | return hba->caps & UFSHCD_CAP_FAKE_CLK_GATING; | |
783 | } | |
b852190e | 784 | |
b873a275 SJ |
785 | #define ufshcd_writel(hba, val, reg) \ |
786 | writel((val), (hba)->mmio_base + (reg)) | |
787 | #define ufshcd_readl(hba, reg) \ | |
788 | readl((hba)->mmio_base + (reg)) | |
789 | ||
e785060e DR |
790 | /** |
791 | * ufshcd_rmwl - read modify write into a register | |
792 | * @hba - per adapter instance | |
793 | * @mask - mask to apply on read value | |
794 | * @val - actual value to write | |
795 | * @reg - register address | |
796 | */ | |
797 | static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) | |
798 | { | |
799 | u32 tmp; | |
800 | ||
801 | tmp = ufshcd_readl(hba, reg); | |
802 | tmp &= ~mask; | |
803 | tmp |= (val & mask); | |
804 | ufshcd_writel(hba, tmp, reg); | |
805 | } | |
806 | ||
5c0c28a8 | 807 | int ufshcd_alloc_host(struct device *, struct ufs_hba **); |
47555a5c | 808 | void ufshcd_dealloc_host(struct ufs_hba *); |
5c0c28a8 | 809 | int ufshcd_init(struct ufs_hba * , void __iomem * , unsigned int); |
e0eca63e | 810 | void ufshcd_remove(struct ufs_hba *); |
596585a2 YG |
811 | int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, |
812 | u32 val, unsigned long interval_us, | |
813 | unsigned long timeout_ms, bool can_sleep); | |
e0eca63e | 814 | |
68078d5c DR |
815 | static inline void check_upiu_size(void) |
816 | { | |
817 | BUILD_BUG_ON(ALIGNED_UPIU_SIZE < | |
818 | GENERAL_UPIU_REQUEST_SIZE + QUERY_DESC_MAX_SIZE); | |
819 | } | |
820 | ||
1ce5898a YG |
821 | /** |
822 | * ufshcd_set_variant - set variant specific data to the hba | |
823 | * @hba - per adapter instance | |
824 | * @variant - pointer to variant specific data | |
825 | */ | |
826 | static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) | |
827 | { | |
828 | BUG_ON(!hba); | |
829 | hba->priv = variant; | |
830 | } | |
831 | ||
832 | /** | |
833 | * ufshcd_get_variant - get variant specific data from the hba | |
834 | * @hba - per adapter instance | |
835 | */ | |
836 | static inline void *ufshcd_get_variant(struct ufs_hba *hba) | |
837 | { | |
838 | BUG_ON(!hba); | |
839 | return hba->priv; | |
840 | } | |
4e768e76 SJ |
841 | static inline bool ufshcd_keep_autobkops_enabled_except_suspend( |
842 | struct ufs_hba *hba) | |
843 | { | |
844 | return hba->caps & UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND; | |
845 | } | |
1ce5898a | 846 | |
66ec6d59 SRT |
847 | extern int ufshcd_runtime_suspend(struct ufs_hba *hba); |
848 | extern int ufshcd_runtime_resume(struct ufs_hba *hba); | |
849 | extern int ufshcd_runtime_idle(struct ufs_hba *hba); | |
57d104c1 SJ |
850 | extern int ufshcd_system_suspend(struct ufs_hba *hba); |
851 | extern int ufshcd_system_resume(struct ufs_hba *hba); | |
852 | extern int ufshcd_shutdown(struct ufs_hba *hba); | |
12b4fdb4 SJ |
853 | extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, |
854 | u8 attr_set, u32 mib_val, u8 peer); | |
855 | extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, | |
856 | u32 *mib_val, u8 peer); | |
623b5fe3 | 857 | extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, |
858 | struct ufs_pa_layer_attr *desired_pwr_mode); | |
a782a88e | 859 | extern void scsi_softirq_done(struct request *rq); |
12b4fdb4 SJ |
860 | |
861 | /* UIC command interfaces for DME primitives */ | |
862 | #define DME_LOCAL 0 | |
863 | #define DME_PEER 1 | |
864 | #define ATTR_SET_NOR 0 /* NORMAL */ | |
865 | #define ATTR_SET_ST 1 /* STATIC */ | |
866 | ||
867 | static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, | |
868 | u32 mib_val) | |
869 | { | |
870 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
871 | mib_val, DME_LOCAL); | |
872 | } | |
873 | ||
874 | static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, | |
875 | u32 mib_val) | |
876 | { | |
877 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
878 | mib_val, DME_LOCAL); | |
879 | } | |
880 | ||
881 | static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, | |
882 | u32 mib_val) | |
883 | { | |
884 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, | |
885 | mib_val, DME_PEER); | |
886 | } | |
887 | ||
888 | static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, | |
889 | u32 mib_val) | |
890 | { | |
891 | return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, | |
892 | mib_val, DME_PEER); | |
893 | } | |
894 | ||
895 | static inline int ufshcd_dme_get(struct ufs_hba *hba, | |
896 | u32 attr_sel, u32 *mib_val) | |
897 | { | |
898 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); | |
899 | } | |
900 | ||
901 | static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, | |
902 | u32 attr_sel, u32 *mib_val) | |
903 | { | |
904 | return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); | |
905 | } | |
906 | ||
f37aabcf YG |
907 | static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info) |
908 | { | |
909 | return (pwr_info->pwr_rx == FAST_MODE || | |
910 | pwr_info->pwr_rx == FASTAUTO_MODE) && | |
911 | (pwr_info->pwr_tx == FAST_MODE || | |
912 | pwr_info->pwr_tx == FASTAUTO_MODE); | |
913 | } | |
914 | ||
dc3c8d3a YG |
915 | /* Expose Query-Request API */ |
916 | int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, | |
917 | enum flag_idn idn, bool *flag_res); | |
1ab27c9c ST |
918 | int ufshcd_hold(struct ufs_hba *hba, bool async); |
919 | void ufshcd_release(struct ufs_hba *hba); | |
a4b0e8a4 PM |
920 | |
921 | int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id, | |
922 | int *desc_length); | |
923 | ||
37113106 | 924 | u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba); |
0263bcd0 YG |
925 | |
926 | /* Wrapper functions for safely calling variant operations */ | |
927 | static inline const char *ufshcd_get_var_name(struct ufs_hba *hba) | |
928 | { | |
929 | if (hba->vops) | |
930 | return hba->vops->name; | |
931 | return ""; | |
932 | } | |
933 | ||
934 | static inline int ufshcd_vops_init(struct ufs_hba *hba) | |
935 | { | |
936 | if (hba->vops && hba->vops->init) | |
937 | return hba->vops->init(hba); | |
938 | ||
939 | return 0; | |
940 | } | |
941 | ||
942 | static inline void ufshcd_vops_exit(struct ufs_hba *hba) | |
943 | { | |
944 | if (hba->vops && hba->vops->exit) | |
945 | return hba->vops->exit(hba); | |
946 | } | |
947 | ||
948 | static inline u32 ufshcd_vops_get_ufs_hci_version(struct ufs_hba *hba) | |
949 | { | |
950 | if (hba->vops && hba->vops->get_ufs_hci_version) | |
951 | return hba->vops->get_ufs_hci_version(hba); | |
952 | ||
953 | return ufshcd_readl(hba, REG_UFS_VERSION); | |
954 | } | |
955 | ||
f06fcc71 YG |
956 | static inline int ufshcd_vops_clk_scale_notify(struct ufs_hba *hba, |
957 | bool up, enum ufs_notify_change_status status) | |
0263bcd0 YG |
958 | { |
959 | if (hba->vops && hba->vops->clk_scale_notify) | |
f06fcc71 YG |
960 | return hba->vops->clk_scale_notify(hba, up, status); |
961 | return 0; | |
0263bcd0 YG |
962 | } |
963 | ||
96495cde | 964 | static inline int ufshcd_vops_pre_setup_clocks(struct ufs_hba *hba, bool on) |
965 | { | |
966 | if (hba->vops && hba->vops->pre_setup_clocks) | |
967 | return hba->vops->pre_setup_clocks(hba, on); | |
968 | return 0; | |
969 | } | |
970 | ||
2767a662 | 971 | static inline int ufshcd_vops_setup_clocks(struct ufs_hba *hba, bool on) |
0263bcd0 YG |
972 | { |
973 | if (hba->vops && hba->vops->setup_clocks) | |
2767a662 | 974 | return hba->vops->setup_clocks(hba, on); |
0263bcd0 YG |
975 | return 0; |
976 | } | |
977 | ||
978 | static inline int ufshcd_vops_setup_regulators(struct ufs_hba *hba, bool status) | |
979 | { | |
980 | if (hba->vops && hba->vops->setup_regulators) | |
981 | return hba->vops->setup_regulators(hba, status); | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
986 | static inline int ufshcd_vops_hce_enable_notify(struct ufs_hba *hba, | |
987 | bool status) | |
988 | { | |
989 | if (hba->vops && hba->vops->hce_enable_notify) | |
990 | return hba->vops->hce_enable_notify(hba, status); | |
991 | ||
992 | return 0; | |
993 | } | |
994 | static inline int ufshcd_vops_link_startup_notify(struct ufs_hba *hba, | |
995 | bool status) | |
996 | { | |
997 | if (hba->vops && hba->vops->link_startup_notify) | |
998 | return hba->vops->link_startup_notify(hba, status); | |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static inline int ufshcd_vops_pwr_change_notify(struct ufs_hba *hba, | |
1004 | bool status, | |
1005 | struct ufs_pa_layer_attr *dev_max_params, | |
1006 | struct ufs_pa_layer_attr *dev_req_params) | |
1007 | { | |
1008 | if (hba->vops && hba->vops->pwr_change_notify) | |
1009 | return hba->vops->pwr_change_notify(hba, status, | |
1010 | dev_max_params, dev_req_params); | |
1011 | ||
1012 | return -ENOTSUPP; | |
1013 | } | |
1014 | ||
1015 | static inline int ufshcd_vops_suspend(struct ufs_hba *hba, enum ufs_pm_op op) | |
1016 | { | |
1017 | if (hba->vops && hba->vops->suspend) | |
1018 | return hba->vops->suspend(hba, op); | |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | static inline int ufshcd_vops_resume(struct ufs_hba *hba, enum ufs_pm_op op) | |
1024 | { | |
1025 | if (hba->vops && hba->vops->resume) | |
1026 | return hba->vops->resume(hba, op); | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | ||
6e3fd44d YG |
1031 | static inline void ufshcd_vops_dbg_register_dump(struct ufs_hba *hba) |
1032 | { | |
1033 | if (hba->vops && hba->vops->dbg_register_dump) | |
1034 | hba->vops->dbg_register_dump(hba); | |
1035 | } | |
1036 | ||
02527a32 | 1037 | static inline u8 ufshcd_vops_get_unipro(struct ufs_hba *hba, int num) |
1038 | { | |
1039 | if (hba->vops && hba->vops->get_unipro_result) | |
1040 | return hba->vops->get_unipro_result(hba, num); | |
1041 | return 0; | |
1042 | } | |
8d65d1bb | 1043 | int ufshcd_read_health_desc(struct ufs_hba *hba, u8 *buf, u32 size); |
66cae4a3 BK |
1044 | static inline int ufshcd_vops_crypto_engine_cfg(struct ufs_hba *hba, |
1045 | struct ufshcd_lrb *lrbp, | |
1046 | struct scatterlist *sg, int index, | |
49e3bbe3 | 1047 | int sector_offset, int page_index) |
66cae4a3 BK |
1048 | { |
1049 | if (hba->vops && hba->vops->crypto_engine_cfg) | |
1050 | return hba->vops->crypto_engine_cfg(hba, lrbp, sg, index, | |
49e3bbe3 | 1051 | sector_offset, page_index); |
66cae4a3 BK |
1052 | return 0; |
1053 | } | |
1054 | ||
1055 | static inline int ufshcd_vops_crypto_engine_clear(struct ufs_hba *hba, | |
1056 | struct ufshcd_lrb *lrbp) | |
1057 | { | |
1058 | if (hba->vops && hba->vops->crypto_engine_clear) | |
1059 | return hba->vops->crypto_engine_clear(hba, lrbp); | |
1060 | return 0; | |
1061 | } | |
1062 | ||
1063 | static inline int ufshcd_vops_access_control_abort(struct ufs_hba *hba) | |
1064 | { | |
1065 | if (hba->vops && hba->vops->access_control_abort) | |
1066 | return hba->vops->access_control_abort(hba); | |
1067 | return 0; | |
1068 | } | |
e0eca63e | 1069 | #endif /* End of Header */ |