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scsi: cxgb4i: Set completion bit in work request
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
7a3e97b0 47
2fbd009b
SJ		 48#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
49 UTP_TASK_REQ_COMPL |\
50 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 51/* UIC command timeout, unit: ms */
52#define UIC_CMD_TIMEOUT 500
2fbd009b 53
5a0b0cb9
SRT		 54/* NOP OUT retries waiting for NOP IN response */
55#define NOP_OUT_RETRIES 10
56/* Timeout after 30 msecs if NOP OUT hangs without response */
57#define NOP_OUT_TIMEOUT 30 /* msecs */
58
68078d5c
DR		 59/* Query request retries */
60#define QUERY_REQ_RETRIES 10
61/* Query request timeout */
62#define QUERY_REQ_TIMEOUT 30 /* msec */
e5ad406c
YG		 63/*
64 * Query request timeout for fDeviceInit flag
65 * fDeviceInit query response time for some devices is too large that default
66 * QUERY_REQ_TIMEOUT may not be enough for such devices.
67 */
68#define QUERY_FDEVICEINIT_REQ_TIMEOUT 600 /* msec */
68078d5c 69
e2933132
SRT		 70/* Task management command timeout */
71#define TM_CMD_TIMEOUT 100 /* msecs */
72
64238fbd
YG		 73/* maximum number of retries for a general UIC command */
74#define UFS_UIC_COMMAND_RETRIES 3
75
1d337ec2
SRT		 76/* maximum number of link-startup retries */
77#define DME_LINKSTARTUP_RETRIES 3
78
87d0b4a6
YG		 79/* Maximum retries for Hibern8 enter */
80#define UIC_HIBERN8_ENTER_RETRIES 3
81
1d337ec2
SRT		 82/* maximum number of reset retries before giving up */
83#define MAX_HOST_RESET_RETRIES 5
84
68078d5c
DR		 85/* Expose the flag value from utp_upiu_query.value */
86#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
87
7d568652
SJ		 88/* Interrupt aggregation default timeout, unit: 40us */
89#define INT_AGGR_DEF_TO 0x02
90
aa497613
SRT		 91#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
92 ({ \
93 int _ret; \
94 if (_on) \
95 _ret = ufshcd_enable_vreg(_dev, _vreg); \
96 else \
97 _ret = ufshcd_disable_vreg(_dev, _vreg); \
98 _ret; \
99 })
100
da461cec
SJ		 101static u32 ufs_query_desc_max_size[] = {
102 QUERY_DESC_DEVICE_MAX_SIZE,
103 QUERY_DESC_CONFIGURAION_MAX_SIZE,
104 QUERY_DESC_UNIT_MAX_SIZE,
105 QUERY_DESC_RFU_MAX_SIZE,
106 QUERY_DESC_INTERCONNECT_MAX_SIZE,
107 QUERY_DESC_STRING_MAX_SIZE,
108 QUERY_DESC_RFU_MAX_SIZE,
1ce21794 109 QUERY_DESC_GEOMETRY_MAX_SIZE,
da461cec
SJ		 110 QUERY_DESC_POWER_MAX_SIZE,
111 QUERY_DESC_RFU_MAX_SIZE,
112};
113
7a3e97b0
SY		 114enum {
115 UFSHCD_MAX_CHANNEL = 0,
116 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 117 UFSHCD_CMD_PER_LUN = 32,
118 UFSHCD_CAN_QUEUE = 32,
119};
120
121/* UFSHCD states */
122enum {
7a3e97b0
SY		 123 UFSHCD_STATE_RESET,
124 UFSHCD_STATE_ERROR,
3441da7d
SRT		 125 UFSHCD_STATE_OPERATIONAL,
126};
127
128/* UFSHCD error handling flags */
129enum {
130 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 131};
132
e8e7f271
SRT		 133/* UFSHCD UIC layer error flags */
134enum {
135 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 136 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
137 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
138 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
139 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
140 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 141};
142
7a3e97b0
SY		 143/* Interrupt configuration options */
144enum {
145 UFSHCD_INT_DISABLE,
146 UFSHCD_INT_ENABLE,
147 UFSHCD_INT_CLEAR,
148};
149
3441da7d
SRT		 150#define ufshcd_set_eh_in_progress(h) \
151 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
152#define ufshcd_eh_in_progress(h) \
153 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
154#define ufshcd_clear_eh_in_progress(h) \
155 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
156
57d104c1
SJ		 157#define ufshcd_set_ufs_dev_active(h) \
158 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
159#define ufshcd_set_ufs_dev_sleep(h) \
160 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
161#define ufshcd_set_ufs_dev_poweroff(h) \
162 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
163#define ufshcd_is_ufs_dev_active(h) \
164 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
165#define ufshcd_is_ufs_dev_sleep(h) \
166 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
167#define ufshcd_is_ufs_dev_poweroff(h) \
168 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
169
170static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
171 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
172 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
173 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
174 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
175 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
176 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
177};
178
179static inline enum ufs_dev_pwr_mode
180ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
181{
182 return ufs_pm_lvl_states[lvl].dev_state;
183}
184
185static inline enum uic_link_state
186ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
187{
188 return ufs_pm_lvl_states[lvl].link_state;
189}
190
3441da7d
SRT		 191static void ufshcd_tmc_handler(struct ufs_hba *hba);
192static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 193static int ufshcd_reset_and_restore(struct ufs_hba *hba);
194static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 195static void ufshcd_hba_exit(struct ufs_hba *hba);
196static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 197static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
198 bool skip_ref_clk);
199static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 200static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 201static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
202static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 203static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1
SJ		 204static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
205static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 206static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
207 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG		 208static int ufshcd_change_power_mode(struct ufs_hba *hba,
209 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 210static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
211{
212 return tag >= 0 && tag < hba->nutrs;
213}
57d104c1
SJ		 214
215static inline int ufshcd_enable_irq(struct ufs_hba *hba)
216{
217 int ret = 0;
218
219 if (!hba->is_irq_enabled) {
220 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
221 hba);
222 if (ret)
223 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
224 __func__, ret);
225 hba->is_irq_enabled = true;
226 }
227
228 return ret;
229}
230
231static inline void ufshcd_disable_irq(struct ufs_hba *hba)
232{
233 if (hba->is_irq_enabled) {
234 free_irq(hba->irq, hba);
235 hba->is_irq_enabled = false;
236 }
237}
3441da7d 238
b573d484
YG		 239/* replace non-printable or non-ASCII characters with spaces */
240static inline void ufshcd_remove_non_printable(char *val)
241{
242 if (!val)
243 return;
244
245 if (*val < 0x20 || *val > 0x7e)
246 *val = ' ';
247}
248
5a0b0cb9
SRT		 249/*
250 * ufshcd_wait_for_register - wait for register value to change
251 * @hba - per-adapter interface
252 * @reg - mmio register offset
253 * @mask - mask to apply to read register value
254 * @val - wait condition
255 * @interval_us - polling interval in microsecs
256 * @timeout_ms - timeout in millisecs
596585a2 257 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 258 *
259 * Returns -ETIMEDOUT on error, zero on success
260 */
596585a2
YG		 261int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
262 u32 val, unsigned long interval_us,
263 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 264{
265 int err = 0;
266 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
267
268 /* ignore bits that we don't intend to wait on */
269 val = val & mask;
270
271 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 272 if (can_sleep)
273 usleep_range(interval_us, interval_us + 50);
274 else
275 udelay(interval_us);
5a0b0cb9
SRT		 276 if (time_after(jiffies, timeout)) {
277 if ((ufshcd_readl(hba, reg) & mask) != val)
278 err = -ETIMEDOUT;
279 break;
280 }
281 }
282
283 return err;
284}
285
2fbd009b
SJ		 286/**
287 * ufshcd_get_intr_mask - Get the interrupt bit mask
288 * @hba - Pointer to adapter instance
289 *
290 * Returns interrupt bit mask per version
291 */
292static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
293{
294 if (hba->ufs_version == UFSHCI_VERSION_10)
295 return INTERRUPT_MASK_ALL_VER_10;
296 else
297 return INTERRUPT_MASK_ALL_VER_11;
298}
299
7a3e97b0
SY		 300/**
301 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
302 * @hba - Pointer to adapter instance
303 *
304 * Returns UFSHCI version supported by the controller
305 */
306static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
307{
0263bcd0
YG		 308 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
309 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 310
b873a275 311 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 312}
313
314/**
315 * ufshcd_is_device_present - Check if any device connected to
316 * the host controller
5c0c28a8 317 * @hba: pointer to adapter instance
7a3e97b0 318 *
73ec513a 319 * Returns 1 if device present, 0 if no device detected
7a3e97b0 320 */
5c0c28a8 321static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 322{
5c0c28a8
SRT		 323 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
324 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 325}
326
327/**
328 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
329 * @lrb: pointer to local command reference block
330 *
331 * This function is used to get the OCS field from UTRD
332 * Returns the OCS field in the UTRD
333 */
334static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
335{
e8c8e82a 336 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 337}
338
339/**
340 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
341 * @task_req_descp: pointer to utp_task_req_desc structure
342 *
343 * This function is used to get the OCS field from UTMRD
344 * Returns the OCS field in the UTMRD
345 */
346static inline int
347ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
348{
e8c8e82a 349 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 350}
351
352/**
353 * ufshcd_get_tm_free_slot - get a free slot for task management request
354 * @hba: per adapter instance
e2933132 355 * @free_slot: pointer to variable with available slot value
7a3e97b0 356 *
e2933132
SRT		 357 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
358 * Returns 0 if free slot is not available, else return 1 with tag value
359 * in @free_slot.
7a3e97b0 360 */
e2933132 361static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 362{
e2933132
SRT		 363 int tag;
364 bool ret = false;
365
366 if (!free_slot)
367 goto out;
368
369 do {
370 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
371 if (tag >= hba->nutmrs)
372 goto out;
373 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
374
375 *free_slot = tag;
376 ret = true;
377out:
378 return ret;
379}
380
381static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
382{
383 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 384}
385
386/**
387 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
388 * @hba: per adapter instance
389 * @pos: position of the bit to be cleared
390 */
391static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
392{
b873a275 393 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 394}
395
a48353f6
YG		 396/**
397 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
398 * @hba: per adapter instance
399 * @tag: position of the bit to be cleared
400 */
401static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
402{
403 __clear_bit(tag, &hba->outstanding_reqs);
404}
405
7a3e97b0
SY		 406/**
407 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
408 * @reg: Register value of host controller status
409 *
410 * Returns integer, 0 on Success and positive value if failed
411 */
412static inline int ufshcd_get_lists_status(u32 reg)
413{
414 /*
415 * The mask 0xFF is for the following HCS register bits
416 * Bit Description
417 * 0 Device Present
418 * 1 UTRLRDY
419 * 2 UTMRLRDY
420 * 3 UCRDY
897efe62 421 * 4-7 reserved
7a3e97b0 422 */
897efe62 423 return ((reg & 0xFF) >> 1) ^ 0x07;
7a3e97b0
SY		 424}
425
426/**
427 * ufshcd_get_uic_cmd_result - Get the UIC command result
428 * @hba: Pointer to adapter instance
429 *
430 * This function gets the result of UIC command completion
431 * Returns 0 on success, non zero value on error
432 */
433static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
434{
b873a275 435 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 436 MASK_UIC_COMMAND_RESULT;
437}
438
12b4fdb4
SJ		 439/**
440 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
441 * @hba: Pointer to adapter instance
442 *
443 * This function gets UIC command argument3
444 * Returns 0 on success, non zero value on error
445 */
446static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
447{
448 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
449}
450
7a3e97b0 451/**
5a0b0cb9 452 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 453 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 454 */
455static inline int
5a0b0cb9 456ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 457{
5a0b0cb9 458 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 459}
460
461/**
462 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
463 * @ucd_rsp_ptr: pointer to response UPIU
464 *
465 * This function gets the response status and scsi_status from response UPIU
466 * Returns the response result code.
467 */
468static inline int
469ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
470{
471 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
472}
473
1c2623c5
SJ		 474/*
475 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
476 * from response UPIU
477 * @ucd_rsp_ptr: pointer to response UPIU
478 *
479 * Return the data segment length.
480 */
481static inline unsigned int
482ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
483{
484 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
485 MASK_RSP_UPIU_DATA_SEG_LEN;
486}
487
66ec6d59
SRT		 488/**
489 * ufshcd_is_exception_event - Check if the device raised an exception event
490 * @ucd_rsp_ptr: pointer to response UPIU
491 *
492 * The function checks if the device raised an exception event indicated in
493 * the Device Information field of response UPIU.
494 *
495 * Returns true if exception is raised, false otherwise.
496 */
497static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
498{
499 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
500 MASK_RSP_EXCEPTION_EVENT ? true : false;
501}
502
7a3e97b0 503/**
7d568652 504 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 505 * @hba: per adapter instance
7a3e97b0
SY		 506 */
507static inline void
7d568652 508ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 509{
7d568652
SJ		 510 ufshcd_writel(hba, INT_AGGR_ENABLE |
511 INT_AGGR_COUNTER_AND_TIMER_RESET,
512 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
513}
514
515/**
516 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
517 * @hba: per adapter instance
518 * @cnt: Interrupt aggregation counter threshold
519 * @tmout: Interrupt aggregation timeout value
520 */
521static inline void
522ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
523{
524 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
525 INT_AGGR_COUNTER_THLD_VAL(cnt) |
526 INT_AGGR_TIMEOUT_VAL(tmout),
527 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 528}
529
b852190e
YG		 530/**
531 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
532 * @hba: per adapter instance
533 */
534static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
535{
536 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
537}
538
7a3e97b0
SY		 539/**
540 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
541 * When run-stop registers are set to 1, it indicates the
542 * host controller that it can process the requests
543 * @hba: per adapter instance
544 */
545static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
546{
b873a275
SJ		 547 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
548 REG_UTP_TASK_REQ_LIST_RUN_STOP);
549 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
550 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 551}
552
7a3e97b0
SY		 553/**
554 * ufshcd_hba_start - Start controller initialization sequence
555 * @hba: per adapter instance
556 */
557static inline void ufshcd_hba_start(struct ufs_hba *hba)
558{
b873a275 559 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 560}
561
562/**
563 * ufshcd_is_hba_active - Get controller state
564 * @hba: per adapter instance
565 *
566 * Returns zero if controller is active, 1 otherwise
567 */
568static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
569{
b873a275 570 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 571}
572
37113106
YG		 573u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
574{
575 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
576 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
577 (hba->ufs_version == UFSHCI_VERSION_11))
578 return UFS_UNIPRO_VER_1_41;
579 else
580 return UFS_UNIPRO_VER_1_6;
581}
582EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
583
584static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
585{
586 /*
587 * If both host and device support UniPro ver1.6 or later, PA layer
588 * parameters tuning happens during link startup itself.
589 *
590 * We can manually tune PA layer parameters if either host or device
591 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
592 * logic simple, we will only do manual tuning if local unipro version
593 * doesn't support ver1.6 or later.
594 */
595 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
596 return true;
597 else
598 return false;
599}
600
1ab27c9c
ST		 601static void ufshcd_ungate_work(struct work_struct *work)
602{
603 int ret;
604 unsigned long flags;
605 struct ufs_hba *hba = container_of(work, struct ufs_hba,
606 clk_gating.ungate_work);
607
608 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
609
610 spin_lock_irqsave(hba->host->host_lock, flags);
611 if (hba->clk_gating.state == CLKS_ON) {
612 spin_unlock_irqrestore(hba->host->host_lock, flags);
613 goto unblock_reqs;
614 }
615
616 spin_unlock_irqrestore(hba->host->host_lock, flags);
617 ufshcd_setup_clocks(hba, true);
618
619 /* Exit from hibern8 */
620 if (ufshcd_can_hibern8_during_gating(hba)) {
621 /* Prevent gating in this path */
622 hba->clk_gating.is_suspended = true;
623 if (ufshcd_is_link_hibern8(hba)) {
624 ret = ufshcd_uic_hibern8_exit(hba);
625 if (ret)
626 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
627 __func__, ret);
628 else
629 ufshcd_set_link_active(hba);
630 }
631 hba->clk_gating.is_suspended = false;
632 }
633unblock_reqs:
856b3483
ST		 634 if (ufshcd_is_clkscaling_enabled(hba))
635 devfreq_resume_device(hba->devfreq);
1ab27c9c
ST		 636 scsi_unblock_requests(hba->host);
637}
638
639/**
640 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
641 * Also, exit from hibern8 mode and set the link as active.
642 * @hba: per adapter instance
643 * @async: This indicates whether caller should ungate clocks asynchronously.
644 */
645int ufshcd_hold(struct ufs_hba *hba, bool async)
646{
647 int rc = 0;
648 unsigned long flags;
649
650 if (!ufshcd_is_clkgating_allowed(hba))
651 goto out;
1ab27c9c
ST		 652 spin_lock_irqsave(hba->host->host_lock, flags);
653 hba->clk_gating.active_reqs++;
654
53c12d0e
YG		 655 if (ufshcd_eh_in_progress(hba)) {
656 spin_unlock_irqrestore(hba->host->host_lock, flags);
657 return 0;
658 }
659
856b3483 660start:
1ab27c9c
ST		 661 switch (hba->clk_gating.state) {
662 case CLKS_ON:
663 break;
664 case REQ_CLKS_OFF:
665 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
666 hba->clk_gating.state = CLKS_ON;
667 break;
668 }
669 /*
670 * If we here, it means gating work is either done or
671 * currently running. Hence, fall through to cancel gating
672 * work and to enable clocks.
673 */
674 case CLKS_OFF:
675 scsi_block_requests(hba->host);
676 hba->clk_gating.state = REQ_CLKS_ON;
677 schedule_work(&hba->clk_gating.ungate_work);
678 /*
679 * fall through to check if we should wait for this
680 * work to be done or not.
681 */
682 case REQ_CLKS_ON:
683 if (async) {
684 rc = -EAGAIN;
685 hba->clk_gating.active_reqs--;
686 break;
687 }
688
689 spin_unlock_irqrestore(hba->host->host_lock, flags);
690 flush_work(&hba->clk_gating.ungate_work);
691 /* Make sure state is CLKS_ON before returning */
856b3483 692 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 693 goto start;
694 default:
695 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
696 __func__, hba->clk_gating.state);
697 break;
698 }
699 spin_unlock_irqrestore(hba->host->host_lock, flags);
700out:
701 return rc;
702}
6e3fd44d 703EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 704
705static void ufshcd_gate_work(struct work_struct *work)
706{
707 struct ufs_hba *hba = container_of(work, struct ufs_hba,
708 clk_gating.gate_work.work);
709 unsigned long flags;
710
711 spin_lock_irqsave(hba->host->host_lock, flags);
712 if (hba->clk_gating.is_suspended) {
713 hba->clk_gating.state = CLKS_ON;
714 goto rel_lock;
715 }
716
717 if (hba->clk_gating.active_reqs
718 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
719 || hba->lrb_in_use || hba->outstanding_tasks
720 || hba->active_uic_cmd || hba->uic_async_done)
721 goto rel_lock;
722
723 spin_unlock_irqrestore(hba->host->host_lock, flags);
724
725 /* put the link into hibern8 mode before turning off clocks */
726 if (ufshcd_can_hibern8_during_gating(hba)) {
727 if (ufshcd_uic_hibern8_enter(hba)) {
728 hba->clk_gating.state = CLKS_ON;
729 goto out;
730 }
731 ufshcd_set_link_hibern8(hba);
732 }
733
856b3483
ST		 734 if (ufshcd_is_clkscaling_enabled(hba)) {
735 devfreq_suspend_device(hba->devfreq);
736 hba->clk_scaling.window_start_t = 0;
737 }
738
1ab27c9c
ST		 739 if (!ufshcd_is_link_active(hba))
740 ufshcd_setup_clocks(hba, false);
741 else
742 /* If link is active, device ref_clk can't be switched off */
743 __ufshcd_setup_clocks(hba, false, true);
744
745 /*
746 * In case you are here to cancel this work the gating state
747 * would be marked as REQ_CLKS_ON. In this case keep the state
748 * as REQ_CLKS_ON which would anyway imply that clocks are off
749 * and a request to turn them on is pending. By doing this way,
750 * we keep the state machine in tact and this would ultimately
751 * prevent from doing cancel work multiple times when there are
752 * new requests arriving before the current cancel work is done.
753 */
754 spin_lock_irqsave(hba->host->host_lock, flags);
755 if (hba->clk_gating.state == REQ_CLKS_OFF)
756 hba->clk_gating.state = CLKS_OFF;
757
758rel_lock:
759 spin_unlock_irqrestore(hba->host->host_lock, flags);
760out:
761 return;
762}
763
764/* host lock must be held before calling this variant */
765static void __ufshcd_release(struct ufs_hba *hba)
766{
767 if (!ufshcd_is_clkgating_allowed(hba))
768 return;
769
770 hba->clk_gating.active_reqs--;
771
772 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
773 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
774 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 775 || hba->active_uic_cmd || hba->uic_async_done
776 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 777 return;
778
779 hba->clk_gating.state = REQ_CLKS_OFF;
780 schedule_delayed_work(&hba->clk_gating.gate_work,
781 msecs_to_jiffies(hba->clk_gating.delay_ms));
782}
783
784void ufshcd_release(struct ufs_hba *hba)
785{
786 unsigned long flags;
787
788 spin_lock_irqsave(hba->host->host_lock, flags);
789 __ufshcd_release(hba);
790 spin_unlock_irqrestore(hba->host->host_lock, flags);
791}
6e3fd44d 792EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 793
794static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
795 struct device_attribute *attr, char *buf)
796{
797 struct ufs_hba *hba = dev_get_drvdata(dev);
798
799 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
800}
801
802static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
803 struct device_attribute *attr, const char *buf, size_t count)
804{
805 struct ufs_hba *hba = dev_get_drvdata(dev);
806 unsigned long flags, value;
807
808 if (kstrtoul(buf, 0, &value))
809 return -EINVAL;
810
811 spin_lock_irqsave(hba->host->host_lock, flags);
812 hba->clk_gating.delay_ms = value;
813 spin_unlock_irqrestore(hba->host->host_lock, flags);
814 return count;
815}
816
817static void ufshcd_init_clk_gating(struct ufs_hba *hba)
818{
819 if (!ufshcd_is_clkgating_allowed(hba))
820 return;
821
822 hba->clk_gating.delay_ms = 150;
823 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
824 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
825
826 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
827 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
828 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
829 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
830 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
831 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
832 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
833}
834
835static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
836{
837 if (!ufshcd_is_clkgating_allowed(hba))
838 return;
839 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
97cd6805
AM		 840 cancel_work_sync(&hba->clk_gating.ungate_work);
841 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST		 842}
843
856b3483
ST		 844/* Must be called with host lock acquired */
845static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
846{
847 if (!ufshcd_is_clkscaling_enabled(hba))
848 return;
849
850 if (!hba->clk_scaling.is_busy_started) {
851 hba->clk_scaling.busy_start_t = ktime_get();
852 hba->clk_scaling.is_busy_started = true;
853 }
854}
855
856static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
857{
858 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
859
860 if (!ufshcd_is_clkscaling_enabled(hba))
861 return;
862
863 if (!hba->outstanding_reqs && scaling->is_busy_started) {
864 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
865 scaling->busy_start_t));
866 scaling->busy_start_t = ktime_set(0, 0);
867 scaling->is_busy_started = false;
868 }
869}
7a3e97b0
SY		 870/**
871 * ufshcd_send_command - Send SCSI or device management commands
872 * @hba: per adapter instance
873 * @task_tag: Task tag of the command
874 */
875static inline
876void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
877{
856b3483 878 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 879 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 880 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 881}
882
883/**
884 * ufshcd_copy_sense_data - Copy sense data in case of check condition
885 * @lrb - pointer to local reference block
886 */
887static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
888{
889 int len;
1c2623c5
SJ		 890 if (lrbp->sense_buffer &&
891 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
5a0b0cb9 892 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
7a3e97b0 893 memcpy(lrbp->sense_buffer,
5a0b0cb9 894 lrbp->ucd_rsp_ptr->sr.sense_data,
7a3e97b0
SY		 895 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
896 }
897}
898
68078d5c
DR		 899/**
900 * ufshcd_copy_query_response() - Copy the Query Response and the data
901 * descriptor
902 * @hba: per adapter instance
903 * @lrb - pointer to local reference block
904 */
905static
c6d4a831 906int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 907{
908 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
909
68078d5c 910 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 911
68078d5c
DR		 912 /* Get the descriptor */
913 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 914 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 915 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 916 u16 resp_len;
917 u16 buf_len;
68078d5c
DR		 918
919 /* data segment length */
c6d4a831 920 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 921 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 922 buf_len = be16_to_cpu(
923 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 924 if (likely(buf_len >= resp_len)) {
925 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
926 } else {
927 dev_warn(hba->dev,
928 "%s: Response size is bigger than buffer",
929 __func__);
930 return -EINVAL;
931 }
68078d5c 932 }
c6d4a831
DR		 933
934 return 0;
68078d5c
DR		 935}
936
7a3e97b0
SY		 937/**
938 * ufshcd_hba_capabilities - Read controller capabilities
939 * @hba: per adapter instance
940 */
941static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
942{
b873a275 943 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 944
945 /* nutrs and nutmrs are 0 based values */
946 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
947 hba->nutmrs =
948 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
949}
950
951/**
6ccf44fe
SJ		 952 * ufshcd_ready_for_uic_cmd - Check if controller is ready
953 * to accept UIC commands
7a3e97b0 954 * @hba: per adapter instance
6ccf44fe
SJ		 955 * Return true on success, else false
956 */
957static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
958{
959 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
960 return true;
961 else
962 return false;
963}
964
53b3d9c3
SJ		 965/**
966 * ufshcd_get_upmcrs - Get the power mode change request status
967 * @hba: Pointer to adapter instance
968 *
969 * This function gets the UPMCRS field of HCS register
970 * Returns value of UPMCRS field
971 */
972static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
973{
974 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
975}
976
6ccf44fe
SJ		 977/**
978 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
979 * @hba: per adapter instance
980 * @uic_cmd: UIC command
981 *
982 * Mutex must be held.
7a3e97b0
SY		 983 */
984static inline void
6ccf44fe 985ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 986{
6ccf44fe
SJ		 987 WARN_ON(hba->active_uic_cmd);
988
989 hba->active_uic_cmd = uic_cmd;
990
7a3e97b0 991 /* Write Args */
6ccf44fe
SJ		 992 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
993 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
994 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 995
996 /* Write UIC Cmd */
6ccf44fe 997 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 998 REG_UIC_COMMAND);
7a3e97b0
SY		 999}
1000
6ccf44fe
SJ		 1001/**
1002 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1003 * @hba: per adapter instance
1004 * @uic_command: UIC command
1005 *
1006 * Must be called with mutex held.
1007 * Returns 0 only if success.
1008 */
1009static int
1010ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1011{
1012 int ret;
1013 unsigned long flags;
1014
1015 if (wait_for_completion_timeout(&uic_cmd->done,
1016 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1017 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1018 else
1019 ret = -ETIMEDOUT;
1020
1021 spin_lock_irqsave(hba->host->host_lock, flags);
1022 hba->active_uic_cmd = NULL;
1023 spin_unlock_irqrestore(hba->host->host_lock, flags);
1024
1025 return ret;
1026}
1027
1028/**
1029 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1030 * @hba: per adapter instance
1031 * @uic_cmd: UIC command
d75f7fe4 1032 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 1033 *
1034 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1035 * with mutex held and host_lock locked.
6ccf44fe
SJ		 1036 * Returns 0 only if success.
1037 */
1038static int
d75f7fe4
YG		 1039__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1040 bool completion)
6ccf44fe 1041{
6ccf44fe
SJ		 1042 if (!ufshcd_ready_for_uic_cmd(hba)) {
1043 dev_err(hba->dev,
1044 "Controller not ready to accept UIC commands\n");
1045 return -EIO;
1046 }
1047
d75f7fe4
YG		 1048 if (completion)
1049 init_completion(&uic_cmd->done);
6ccf44fe 1050
6ccf44fe 1051 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1052
57d104c1 1053 return 0;
6ccf44fe
SJ		 1054}
1055
1056/**
1057 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1058 * @hba: per adapter instance
1059 * @uic_cmd: UIC command
1060 *
1061 * Returns 0 only if success.
1062 */
1063static int
1064ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1065{
1066 int ret;
57d104c1 1067 unsigned long flags;
6ccf44fe 1068
1ab27c9c 1069 ufshcd_hold(hba, false);
6ccf44fe 1070 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 1071 ufshcd_add_delay_before_dme_cmd(hba);
1072
57d104c1 1073 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1074 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 1075 spin_unlock_irqrestore(hba->host->host_lock, flags);
1076 if (!ret)
1077 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1078
6ccf44fe
SJ		 1079 mutex_unlock(&hba->uic_cmd_mutex);
1080
1ab27c9c 1081 ufshcd_release(hba);
6ccf44fe
SJ		 1082 return ret;
1083}
1084
7a3e97b0
SY		 1085/**
1086 * ufshcd_map_sg - Map scatter-gather list to prdt
1087 * @lrbp - pointer to local reference block
1088 *
1089 * Returns 0 in case of success, non-zero value in case of failure
1090 */
1091static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
1092{
1093 struct ufshcd_sg_entry *prd_table;
1094 struct scatterlist *sg;
1095 struct scsi_cmnd *cmd;
1096 int sg_segments;
1097 int i;
1098
1099 cmd = lrbp->cmd;
1100 sg_segments = scsi_dma_map(cmd);
1101 if (sg_segments < 0)
1102 return sg_segments;
1103
1104 if (sg_segments) {
1105 lrbp->utr_descriptor_ptr->prd_table_length =
1106 cpu_to_le16((u16) (sg_segments));
1107
1108 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1109
1110 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1111 prd_table[i].size =
1112 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1113 prd_table[i].base_addr =
1114 cpu_to_le32(lower_32_bits(sg->dma_address));
1115 prd_table[i].upper_addr =
1116 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 1117 prd_table[i].reserved = 0;
7a3e97b0
SY		 1118 }
1119 } else {
1120 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1121 }
1122
1123 return 0;
1124}
1125
1126/**
2fbd009b 1127 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1128 * @hba: per adapter instance
2fbd009b 1129 * @intrs: interrupt bits
7a3e97b0 1130 */
2fbd009b 1131static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1132{
2fbd009b
SJ		 1133 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1134
1135 if (hba->ufs_version == UFSHCI_VERSION_10) {
1136 u32 rw;
1137 rw = set & INTERRUPT_MASK_RW_VER_10;
1138 set = rw | ((set ^ intrs) & intrs);
1139 } else {
1140 set |= intrs;
1141 }
1142
1143 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1144}
1145
1146/**
1147 * ufshcd_disable_intr - disable interrupts
1148 * @hba: per adapter instance
1149 * @intrs: interrupt bits
1150 */
1151static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1152{
1153 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1154
1155 if (hba->ufs_version == UFSHCI_VERSION_10) {
1156 u32 rw;
1157 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1158 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1159 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1160
1161 } else {
1162 set &= ~intrs;
7a3e97b0 1163 }
2fbd009b
SJ		 1164
1165 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 1166}
1167
5a0b0cb9
SRT		 1168/**
1169 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1170 * descriptor according to request
1171 * @lrbp: pointer to local reference block
1172 * @upiu_flags: flags required in the header
1173 * @cmd_dir: requests data direction
1174 */
1175static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 1176 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 1177{
1178 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1179 u32 data_direction;
1180 u32 dword_0;
1181
1182 if (cmd_dir == DMA_FROM_DEVICE) {
1183 data_direction = UTP_DEVICE_TO_HOST;
1184 *upiu_flags = UPIU_CMD_FLAGS_READ;
1185 } else if (cmd_dir == DMA_TO_DEVICE) {
1186 data_direction = UTP_HOST_TO_DEVICE;
1187 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1188 } else {
1189 data_direction = UTP_NO_DATA_TRANSFER;
1190 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1191 }
1192
1193 dword_0 = data_direction | (lrbp->command_type
1194 << UPIU_COMMAND_TYPE_OFFSET);
1195 if (lrbp->intr_cmd)
1196 dword_0 |= UTP_REQ_DESC_INT_CMD;
1197
1198 /* Transfer request descriptor header fields */
1199 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 1200 /* dword_1 is reserved, hence it is set to 0 */
1201 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 1202 /*
1203 * assigning invalid value for command status. Controller
1204 * updates OCS on command completion, with the command
1205 * status
1206 */
1207 req_desc->header.dword_2 =
1208 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 1209 /* dword_3 is reserved, hence it is set to 0 */
1210 req_desc->header.dword_3 = 0;
51047266
YG		 1211
1212 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 1213}
1214
1215/**
1216 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1217 * for scsi commands
1218 * @lrbp - local reference block pointer
1219 * @upiu_flags - flags
1220 */
1221static
1222void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1223{
1224 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 1225 unsigned short cdb_len;
5a0b0cb9
SRT		 1226
1227 /* command descriptor fields */
1228 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1229 UPIU_TRANSACTION_COMMAND, upiu_flags,
1230 lrbp->lun, lrbp->task_tag);
1231 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1232 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1233
1234 /* Total EHS length and Data segment length will be zero */
1235 ucd_req_ptr->header.dword_2 = 0;
1236
1237 ucd_req_ptr->sc.exp_data_transfer_len =
1238 cpu_to_be32(lrbp->cmd->sdb.length);
1239
52ac95fe
YG		 1240 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
1241 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
1242 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
1243
1244 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1245}
1246
68078d5c
DR		 1247/**
1248 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1249 * for query requsts
1250 * @hba: UFS hba
1251 * @lrbp: local reference block pointer
1252 * @upiu_flags: flags
1253 */
1254static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1255 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1256{
1257 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1258 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1259 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 1260 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1261
1262 /* Query request header */
1263 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1264 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1265 lrbp->lun, lrbp->task_tag);
1266 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1267 0, query->request.query_func, 0, 0);
1268
1269 /* Data segment length */
1270 ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
1271 0, 0, len >> 8, (u8)len);
1272
1273 /* Copy the Query Request buffer as is */
1274 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1275 QUERY_OSF_SIZE);
68078d5c
DR		 1276
1277 /* Copy the Descriptor */
c6d4a831
DR		 1278 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1279 memcpy(descp, query->descriptor, len);
1280
51047266 1281 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 1282}
1283
5a0b0cb9
SRT		 1284static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1285{
1286 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1287
1288 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1289
1290 /* command descriptor fields */
1291 ucd_req_ptr->header.dword_0 =
1292 UPIU_HEADER_DWORD(
1293 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 1294 /* clear rest of the fields of basic header */
1295 ucd_req_ptr->header.dword_1 = 0;
1296 ucd_req_ptr->header.dword_2 = 0;
1297
1298 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 1299}
1300
7a3e97b0 1301/**
300bb13f
JP		 1302 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
1303 * for Device Management Purposes
5a0b0cb9 1304 * @hba - per adapter instance
7a3e97b0
SY		 1305 * @lrb - pointer to local reference block
1306 */
300bb13f 1307static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1308{
7a3e97b0 1309 u32 upiu_flags;
5a0b0cb9 1310 int ret = 0;
7a3e97b0 1311
300bb13f
JP		 1312 if (hba->ufs_version == UFSHCI_VERSION_20)
1313 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1314 else
1315 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1316
1317 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
1318 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1319 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
1320 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
1321 ufshcd_prepare_utp_nop_upiu(lrbp);
1322 else
1323 ret = -EINVAL;
1324
1325 return ret;
1326}
1327
1328/**
1329 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
1330 * for SCSI Purposes
1331 * @hba - per adapter instance
1332 * @lrb - pointer to local reference block
1333 */
1334static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1335{
1336 u32 upiu_flags;
1337 int ret = 0;
1338
1339 if (hba->ufs_version == UFSHCI_VERSION_20)
1340 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
1341 else
1342 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1343
1344 if (likely(lrbp->cmd)) {
1345 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1346 lrbp->cmd->sc_data_direction);
1347 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
1348 } else {
1349 ret = -EINVAL;
1350 }
5a0b0cb9
SRT		 1351
1352 return ret;
7a3e97b0
SY		 1353}
1354
0ce147d4
SJ		 1355/*
1356 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1357 * @scsi_lun: scsi LUN id
1358 *
1359 * Returns UPIU LUN id
1360 */
1361static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1362{
1363 if (scsi_is_wlun(scsi_lun))
1364 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1365 | UFS_UPIU_WLUN_ID;
1366 else
1367 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1368}
1369
2a8fa600
SJ		 1370/**
1371 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1372 * @scsi_lun: UPIU W-LUN id
1373 *
1374 * Returns SCSI W-LUN id
1375 */
1376static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1377{
1378 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1379}
1380
7a3e97b0
SY		 1381/**
1382 * ufshcd_queuecommand - main entry point for SCSI requests
1383 * @cmd: command from SCSI Midlayer
1384 * @done: call back function
1385 *
1386 * Returns 0 for success, non-zero in case of failure
1387 */
1388static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1389{
1390 struct ufshcd_lrb *lrbp;
1391 struct ufs_hba *hba;
1392 unsigned long flags;
1393 int tag;
1394 int err = 0;
1395
1396 hba = shost_priv(host);
1397
1398 tag = cmd->request->tag;
14497328
YG		 1399 if (!ufshcd_valid_tag(hba, tag)) {
1400 dev_err(hba->dev,
1401 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
1402 __func__, tag, cmd, cmd->request);
1403 BUG();
1404 }
7a3e97b0 1405
3441da7d
SRT		 1406 spin_lock_irqsave(hba->host->host_lock, flags);
1407 switch (hba->ufshcd_state) {
1408 case UFSHCD_STATE_OPERATIONAL:
1409 break;
1410 case UFSHCD_STATE_RESET:
7a3e97b0 1411 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 1412 goto out_unlock;
1413 case UFSHCD_STATE_ERROR:
1414 set_host_byte(cmd, DID_ERROR);
1415 cmd->scsi_done(cmd);
1416 goto out_unlock;
1417 default:
1418 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1419 __func__, hba->ufshcd_state);
1420 set_host_byte(cmd, DID_BAD_TARGET);
1421 cmd->scsi_done(cmd);
1422 goto out_unlock;
7a3e97b0 1423 }
53c12d0e
YG		 1424
1425 /* if error handling is in progress, don't issue commands */
1426 if (ufshcd_eh_in_progress(hba)) {
1427 set_host_byte(cmd, DID_ERROR);
1428 cmd->scsi_done(cmd);
1429 goto out_unlock;
1430 }
3441da7d 1431 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1432
5a0b0cb9
SRT		 1433 /* acquire the tag to make sure device cmds don't use it */
1434 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1435 /*
1436 * Dev manage command in progress, requeue the command.
1437 * Requeuing the command helps in cases where the request *may*
1438 * find different tag instead of waiting for dev manage command
1439 * completion.
1440 */
1441 err = SCSI_MLQUEUE_HOST_BUSY;
1442 goto out;
1443 }
1444
1ab27c9c
ST		 1445 err = ufshcd_hold(hba, true);
1446 if (err) {
1447 err = SCSI_MLQUEUE_HOST_BUSY;
1448 clear_bit_unlock(tag, &hba->lrb_in_use);
1449 goto out;
1450 }
1451 WARN_ON(hba->clk_gating.state != CLKS_ON);
1452
7a3e97b0
SY		 1453 lrbp = &hba->lrb[tag];
1454
5a0b0cb9 1455 WARN_ON(lrbp->cmd);
7a3e97b0
SY		 1456 lrbp->cmd = cmd;
1457 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
1458 lrbp->sense_buffer = cmd->sense_buffer;
1459 lrbp->task_tag = tag;
0ce147d4 1460 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 1461 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
7a3e97b0 1462
300bb13f
JP		 1463 ufshcd_comp_scsi_upiu(hba, lrbp);
1464
7a3e97b0 1465 err = ufshcd_map_sg(lrbp);
5a0b0cb9
SRT		 1466 if (err) {
1467 lrbp->cmd = NULL;
1468 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1469 goto out;
5a0b0cb9 1470 }
7a3e97b0
SY		 1471
1472 /* issue command to the controller */
1473 spin_lock_irqsave(hba->host->host_lock, flags);
1474 ufshcd_send_command(hba, tag);
3441da7d 1475out_unlock:
7a3e97b0
SY		 1476 spin_unlock_irqrestore(hba->host->host_lock, flags);
1477out:
1478 return err;
1479}
1480
5a0b0cb9
SRT		 1481static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1482 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1483{
1484 lrbp->cmd = NULL;
1485 lrbp->sense_bufflen = 0;
1486 lrbp->sense_buffer = NULL;
1487 lrbp->task_tag = tag;
1488 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 1489 lrbp->intr_cmd = true; /* No interrupt aggregation */
1490 hba->dev_cmd.type = cmd_type;
1491
300bb13f 1492 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 1493}
1494
1495static int
1496ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1497{
1498 int err = 0;
1499 unsigned long flags;
1500 u32 mask = 1 << tag;
1501
1502 /* clear outstanding transaction before retry */
1503 spin_lock_irqsave(hba->host->host_lock, flags);
1504 ufshcd_utrl_clear(hba, tag);
1505 spin_unlock_irqrestore(hba->host->host_lock, flags);
1506
1507 /*
1508 * wait for for h/w to clear corresponding bit in door-bell.
1509 * max. wait is 1 sec.
1510 */
1511 err = ufshcd_wait_for_register(hba,
1512 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 1513 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 1514
1515 return err;
1516}
1517
c6d4a831
DR		 1518static int
1519ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1520{
1521 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1522
1523 /* Get the UPIU response */
1524 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1525 UPIU_RSP_CODE_OFFSET;
1526 return query_res->response;
1527}
1528
5a0b0cb9
SRT		 1529/**
1530 * ufshcd_dev_cmd_completion() - handles device management command responses
1531 * @hba: per adapter instance
1532 * @lrbp: pointer to local reference block
1533 */
1534static int
1535ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1536{
1537 int resp;
1538 int err = 0;
1539
1540 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1541
1542 switch (resp) {
1543 case UPIU_TRANSACTION_NOP_IN:
1544 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1545 err = -EINVAL;
1546 dev_err(hba->dev, "%s: unexpected response %x\n",
1547 __func__, resp);
1548 }
1549 break;
68078d5c 1550 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1551 err = ufshcd_check_query_response(hba, lrbp);
1552 if (!err)
1553 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1554 break;
5a0b0cb9
SRT		 1555 case UPIU_TRANSACTION_REJECT_UPIU:
1556 /* TODO: handle Reject UPIU Response */
1557 err = -EPERM;
1558 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1559 __func__);
1560 break;
1561 default:
1562 err = -EINVAL;
1563 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1564 __func__, resp);
1565 break;
1566 }
1567
1568 return err;
1569}
1570
1571static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1572 struct ufshcd_lrb *lrbp, int max_timeout)
1573{
1574 int err = 0;
1575 unsigned long time_left;
1576 unsigned long flags;
1577
1578 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1579 msecs_to_jiffies(max_timeout));
1580
1581 spin_lock_irqsave(hba->host->host_lock, flags);
1582 hba->dev_cmd.complete = NULL;
1583 if (likely(time_left)) {
1584 err = ufshcd_get_tr_ocs(lrbp);
1585 if (!err)
1586 err = ufshcd_dev_cmd_completion(hba, lrbp);
1587 }
1588 spin_unlock_irqrestore(hba->host->host_lock, flags);
1589
1590 if (!time_left) {
1591 err = -ETIMEDOUT;
a48353f6
YG		 1592 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
1593 __func__, lrbp->task_tag);
5a0b0cb9 1594 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 1595 /* successfully cleared the command, retry if needed */
5a0b0cb9 1596 err = -EAGAIN;
a48353f6
YG		 1597 /*
1598 * in case of an error, after clearing the doorbell,
1599 * we also need to clear the outstanding_request
1600 * field in hba
1601 */
1602 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 1603 }
1604
1605 return err;
1606}
1607
1608/**
1609 * ufshcd_get_dev_cmd_tag - Get device management command tag
1610 * @hba: per-adapter instance
1611 * @tag: pointer to variable with available slot value
1612 *
1613 * Get a free slot and lock it until device management command
1614 * completes.
1615 *
1616 * Returns false if free slot is unavailable for locking, else
1617 * return true with tag value in @tag.
1618 */
1619static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1620{
1621 int tag;
1622 bool ret = false;
1623 unsigned long tmp;
1624
1625 if (!tag_out)
1626 goto out;
1627
1628 do {
1629 tmp = ~hba->lrb_in_use;
1630 tag = find_last_bit(&tmp, hba->nutrs);
1631 if (tag >= hba->nutrs)
1632 goto out;
1633 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1634
1635 *tag_out = tag;
1636 ret = true;
1637out:
1638 return ret;
1639}
1640
1641static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1642{
1643 clear_bit_unlock(tag, &hba->lrb_in_use);
1644}
1645
1646/**
1647 * ufshcd_exec_dev_cmd - API for sending device management requests
1648 * @hba - UFS hba
1649 * @cmd_type - specifies the type (NOP, Query...)
1650 * @timeout - time in seconds
1651 *
68078d5c
DR		 1652 * NOTE: Since there is only one available tag for device management commands,
1653 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1654 */
1655static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1656 enum dev_cmd_type cmd_type, int timeout)
1657{
1658 struct ufshcd_lrb *lrbp;
1659 int err;
1660 int tag;
1661 struct completion wait;
1662 unsigned long flags;
1663
1664 /*
1665 * Get free slot, sleep if slots are unavailable.
1666 * Even though we use wait_event() which sleeps indefinitely,
1667 * the maximum wait time is bounded by SCSI request timeout.
1668 */
1669 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1670
1671 init_completion(&wait);
1672 lrbp = &hba->lrb[tag];
1673 WARN_ON(lrbp->cmd);
1674 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1675 if (unlikely(err))
1676 goto out_put_tag;
1677
1678 hba->dev_cmd.complete = &wait;
1679
e3dfdc53
YG		 1680 /* Make sure descriptors are ready before ringing the doorbell */
1681 wmb();
5a0b0cb9
SRT		 1682 spin_lock_irqsave(hba->host->host_lock, flags);
1683 ufshcd_send_command(hba, tag);
1684 spin_unlock_irqrestore(hba->host->host_lock, flags);
1685
1686 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1687
1688out_put_tag:
1689 ufshcd_put_dev_cmd_tag(hba, tag);
1690 wake_up(&hba->dev_cmd.tag_wq);
1691 return err;
1692}
1693
d44a5f98
DR		 1694/**
1695 * ufshcd_init_query() - init the query response and request parameters
1696 * @hba: per-adapter instance
1697 * @request: address of the request pointer to be initialized
1698 * @response: address of the response pointer to be initialized
1699 * @opcode: operation to perform
1700 * @idn: flag idn to access
1701 * @index: LU number to access
1702 * @selector: query/flag/descriptor further identification
1703 */
1704static inline void ufshcd_init_query(struct ufs_hba *hba,
1705 struct ufs_query_req **request, struct ufs_query_res **response,
1706 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1707{
1708 *request = &hba->dev_cmd.query.request;
1709 *response = &hba->dev_cmd.query.response;
1710 memset(*request, 0, sizeof(struct ufs_query_req));
1711 memset(*response, 0, sizeof(struct ufs_query_res));
1712 (*request)->upiu_req.opcode = opcode;
1713 (*request)->upiu_req.idn = idn;
1714 (*request)->upiu_req.index = index;
1715 (*request)->upiu_req.selector = selector;
1716}
1717
dc3c8d3a
YG		 1718static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1719 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
1720{
1721 int ret;
1722 int retries;
1723
1724 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1725 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
1726 if (ret)
1727 dev_dbg(hba->dev,
1728 "%s: failed with error %d, retries %d\n",
1729 __func__, ret, retries);
1730 else
1731 break;
1732 }
1733
1734 if (ret)
1735 dev_err(hba->dev,
1736 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1737 __func__, opcode, idn, ret, retries);
1738 return ret;
1739}
1740
68078d5c
DR		 1741/**
1742 * ufshcd_query_flag() - API function for sending flag query requests
1743 * hba: per-adapter instance
1744 * query_opcode: flag query to perform
1745 * idn: flag idn to access
1746 * flag_res: the flag value after the query request completes
1747 *
1748 * Returns 0 for success, non-zero in case of failure
1749 */
dc3c8d3a 1750int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 1751 enum flag_idn idn, bool *flag_res)
1752{
d44a5f98
DR		 1753 struct ufs_query_req *request = NULL;
1754 struct ufs_query_res *response = NULL;
1755 int err, index = 0, selector = 0;
e5ad406c 1756 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 1757
1758 BUG_ON(!hba);
1759
1ab27c9c 1760 ufshcd_hold(hba, false);
68078d5c 1761 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1762 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1763 selector);
68078d5c
DR		 1764
1765 switch (opcode) {
1766 case UPIU_QUERY_OPCODE_SET_FLAG:
1767 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1768 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1769 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1770 break;
1771 case UPIU_QUERY_OPCODE_READ_FLAG:
1772 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1773 if (!flag_res) {
1774 /* No dummy reads */
1775 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1776 __func__);
1777 err = -EINVAL;
1778 goto out_unlock;
1779 }
1780 break;
1781 default:
1782 dev_err(hba->dev,
1783 "%s: Expected query flag opcode but got = %d\n",
1784 __func__, opcode);
1785 err = -EINVAL;
1786 goto out_unlock;
1787 }
68078d5c 1788
e5ad406c
YG		 1789 if (idn == QUERY_FLAG_IDN_FDEVICEINIT)
1790 timeout = QUERY_FDEVICEINIT_REQ_TIMEOUT;
1791
1792 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 1793
1794 if (err) {
1795 dev_err(hba->dev,
1796 "%s: Sending flag query for idn %d failed, err = %d\n",
1797 __func__, idn, err);
1798 goto out_unlock;
1799 }
1800
1801 if (flag_res)
e8c8e82a 1802 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1803 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1804
1805out_unlock:
1806 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 1807 ufshcd_release(hba);
68078d5c
DR		 1808 return err;
1809}
1810
66ec6d59
SRT		 1811/**
1812 * ufshcd_query_attr - API function for sending attribute requests
1813 * hba: per-adapter instance
1814 * opcode: attribute opcode
1815 * idn: attribute idn to access
1816 * index: index field
1817 * selector: selector field
1818 * attr_val: the attribute value after the query request completes
1819 *
1820 * Returns 0 for success, non-zero in case of failure
1821*/
bdbe5d2f 1822static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1823 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1824{
d44a5f98
DR		 1825 struct ufs_query_req *request = NULL;
1826 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 1827 int err;
1828
1829 BUG_ON(!hba);
1830
1ab27c9c 1831 ufshcd_hold(hba, false);
66ec6d59
SRT		 1832 if (!attr_val) {
1833 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1834 __func__, opcode);
1835 err = -EINVAL;
1836 goto out;
1837 }
1838
1839 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1840 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1841 selector);
66ec6d59
SRT		 1842
1843 switch (opcode) {
1844 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1845 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1846 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1847 break;
1848 case UPIU_QUERY_OPCODE_READ_ATTR:
1849 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1850 break;
1851 default:
1852 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1853 __func__, opcode);
1854 err = -EINVAL;
1855 goto out_unlock;
1856 }
1857
d44a5f98 1858 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 1859
1860 if (err) {
1861 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1862 __func__, opcode, idn, err);
1863 goto out_unlock;
1864 }
1865
e8c8e82a 1866 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1867
1868out_unlock:
1869 mutex_unlock(&hba->dev_cmd.lock);
1870out:
1ab27c9c 1871 ufshcd_release(hba);
66ec6d59
SRT		 1872 return err;
1873}
1874
5e86ae44
YG		 1875/**
1876 * ufshcd_query_attr_retry() - API function for sending query
1877 * attribute with retries
1878 * @hba: per-adapter instance
1879 * @opcode: attribute opcode
1880 * @idn: attribute idn to access
1881 * @index: index field
1882 * @selector: selector field
1883 * @attr_val: the attribute value after the query request
1884 * completes
1885 *
1886 * Returns 0 for success, non-zero in case of failure
1887*/
1888static int ufshcd_query_attr_retry(struct ufs_hba *hba,
1889 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
1890 u32 *attr_val)
1891{
1892 int ret = 0;
1893 u32 retries;
1894
1895 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1896 ret = ufshcd_query_attr(hba, opcode, idn, index,
1897 selector, attr_val);
1898 if (ret)
1899 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
1900 __func__, ret, retries);
1901 else
1902 break;
1903 }
1904
1905 if (ret)
1906 dev_err(hba->dev,
1907 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
1908 __func__, idn, ret, QUERY_REQ_RETRIES);
1909 return ret;
1910}
1911
a70e91b8 1912static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 1913 enum query_opcode opcode, enum desc_idn idn, u8 index,
1914 u8 selector, u8 *desc_buf, int *buf_len)
1915{
1916 struct ufs_query_req *request = NULL;
1917 struct ufs_query_res *response = NULL;
1918 int err;
1919
1920 BUG_ON(!hba);
1921
1ab27c9c 1922 ufshcd_hold(hba, false);
d44a5f98
DR		 1923 if (!desc_buf) {
1924 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1925 __func__, opcode);
1926 err = -EINVAL;
1927 goto out;
1928 }
1929
1930 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1931 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1932 __func__, *buf_len);
1933 err = -EINVAL;
1934 goto out;
1935 }
1936
1937 mutex_lock(&hba->dev_cmd.lock);
1938 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1939 selector);
1940 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1941 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 1942
1943 switch (opcode) {
1944 case UPIU_QUERY_OPCODE_WRITE_DESC:
1945 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1946 break;
1947 case UPIU_QUERY_OPCODE_READ_DESC:
1948 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1949 break;
1950 default:
1951 dev_err(hba->dev,
1952 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1953 __func__, opcode);
1954 err = -EINVAL;
1955 goto out_unlock;
1956 }
1957
1958 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1959
1960 if (err) {
1961 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1962 __func__, opcode, idn, err);
1963 goto out_unlock;
1964 }
1965
1966 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 1967 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 1968
1969out_unlock:
1970 mutex_unlock(&hba->dev_cmd.lock);
1971out:
1ab27c9c 1972 ufshcd_release(hba);
d44a5f98
DR		 1973 return err;
1974}
1975
a70e91b8
YG		 1976/**
1977 * ufshcd_query_descriptor_retry - API function for sending descriptor
1978 * requests
1979 * hba: per-adapter instance
1980 * opcode: attribute opcode
1981 * idn: attribute idn to access
1982 * index: index field
1983 * selector: selector field
1984 * desc_buf: the buffer that contains the descriptor
1985 * buf_len: length parameter passed to the device
1986 *
1987 * Returns 0 for success, non-zero in case of failure.
1988 * The buf_len parameter will contain, on return, the length parameter
1989 * received on the response.
1990 */
1991int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
1992 enum query_opcode opcode, enum desc_idn idn, u8 index,
1993 u8 selector, u8 *desc_buf, int *buf_len)
1994{
1995 int err;
1996 int retries;
1997
1998 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1999 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2000 selector, desc_buf, buf_len);
2001 if (!err || err == -EINVAL)
2002 break;
2003 }
2004
2005 return err;
2006}
2007EXPORT_SYMBOL(ufshcd_query_descriptor_retry);
2008
da461cec
SJ		 2009/**
2010 * ufshcd_read_desc_param - read the specified descriptor parameter
2011 * @hba: Pointer to adapter instance
2012 * @desc_id: descriptor idn value
2013 * @desc_index: descriptor index
2014 * @param_offset: offset of the parameter to read
2015 * @param_read_buf: pointer to buffer where parameter would be read
2016 * @param_size: sizeof(param_read_buf)
2017 *
2018 * Return 0 in case of success, non-zero otherwise
2019 */
2020static int ufshcd_read_desc_param(struct ufs_hba *hba,
2021 enum desc_idn desc_id,
2022 int desc_index,
2023 u32 param_offset,
2024 u8 *param_read_buf,
2025 u32 param_size)
2026{
2027 int ret;
2028 u8 *desc_buf;
2029 u32 buff_len;
2030 bool is_kmalloc = true;
2031
2032 /* safety checks */
2033 if (desc_id >= QUERY_DESC_IDN_MAX)
2034 return -EINVAL;
2035
2036 buff_len = ufs_query_desc_max_size[desc_id];
2037 if ((param_offset + param_size) > buff_len)
2038 return -EINVAL;
2039
2040 if (!param_offset && (param_size == buff_len)) {
2041 /* memory space already available to hold full descriptor */
2042 desc_buf = param_read_buf;
2043 is_kmalloc = false;
2044 } else {
2045 /* allocate memory to hold full descriptor */
2046 desc_buf = kmalloc(buff_len, GFP_KERNEL);
2047 if (!desc_buf)
2048 return -ENOMEM;
2049 }
2050
a70e91b8
YG		 2051 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2052 desc_id, desc_index, 0, desc_buf,
2053 &buff_len);
da461cec
SJ		 2054
2055 if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
2056 (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
2057 ufs_query_desc_max_size[desc_id])
2058 || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
2059 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
2060 __func__, desc_id, param_offset, buff_len, ret);
2061 if (!ret)
2062 ret = -EINVAL;
2063
2064 goto out;
2065 }
2066
2067 if (is_kmalloc)
2068 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
2069out:
2070 if (is_kmalloc)
2071 kfree(desc_buf);
2072 return ret;
2073}
2074
2075static inline int ufshcd_read_desc(struct ufs_hba *hba,
2076 enum desc_idn desc_id,
2077 int desc_index,
2078 u8 *buf,
2079 u32 size)
2080{
2081 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
2082}
2083
2084static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
2085 u8 *buf,
2086 u32 size)
2087{
2088 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
2089}
2090
b573d484
YG		 2091int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
2092{
2093 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
2094}
2095EXPORT_SYMBOL(ufshcd_read_device_desc);
2096
2097/**
2098 * ufshcd_read_string_desc - read string descriptor
2099 * @hba: pointer to adapter instance
2100 * @desc_index: descriptor index
2101 * @buf: pointer to buffer where descriptor would be read
2102 * @size: size of buf
2103 * @ascii: if true convert from unicode to ascii characters
2104 *
2105 * Return 0 in case of success, non-zero otherwise
2106 */
2107int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index, u8 *buf,
2108 u32 size, bool ascii)
2109{
2110 int err = 0;
2111
2112 err = ufshcd_read_desc(hba,
2113 QUERY_DESC_IDN_STRING, desc_index, buf, size);
2114
2115 if (err) {
2116 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
2117 __func__, QUERY_REQ_RETRIES, err);
2118 goto out;
2119 }
2120
2121 if (ascii) {
2122 int desc_len;
2123 int ascii_len;
2124 int i;
2125 char *buff_ascii;
2126
2127 desc_len = buf[0];
2128 /* remove header and divide by 2 to move from UTF16 to UTF8 */
2129 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
2130 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
2131 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
2132 __func__);
2133 err = -ENOMEM;
2134 goto out;
2135 }
2136
2137 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
2138 if (!buff_ascii) {
2139 err = -ENOMEM;
fcbefc3b 2140 goto out;
b573d484
YG		 2141 }
2142
2143 /*
2144 * the descriptor contains string in UTF16 format
2145 * we need to convert to utf-8 so it can be displayed
2146 */
2147 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
2148 desc_len - QUERY_DESC_HDR_SIZE,
2149 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
2150
2151 /* replace non-printable or non-ASCII characters with spaces */
2152 for (i = 0; i < ascii_len; i++)
2153 ufshcd_remove_non_printable(&buff_ascii[i]);
2154
2155 memset(buf + QUERY_DESC_HDR_SIZE, 0,
2156 size - QUERY_DESC_HDR_SIZE);
2157 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
2158 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 2159 kfree(buff_ascii);
2160 }
2161out:
2162 return err;
2163}
2164EXPORT_SYMBOL(ufshcd_read_string_desc);
2165
da461cec
SJ		 2166/**
2167 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
2168 * @hba: Pointer to adapter instance
2169 * @lun: lun id
2170 * @param_offset: offset of the parameter to read
2171 * @param_read_buf: pointer to buffer where parameter would be read
2172 * @param_size: sizeof(param_read_buf)
2173 *
2174 * Return 0 in case of success, non-zero otherwise
2175 */
2176static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
2177 int lun,
2178 enum unit_desc_param param_offset,
2179 u8 *param_read_buf,
2180 u32 param_size)
2181{
2182 /*
2183 * Unit descriptors are only available for general purpose LUs (LUN id
2184 * from 0 to 7) and RPMB Well known LU.
2185 */
0ce147d4 2186 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 2187 return -EOPNOTSUPP;
2188
2189 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
2190 param_offset, param_read_buf, param_size);
2191}
2192
7a3e97b0
SY		 2193/**
2194 * ufshcd_memory_alloc - allocate memory for host memory space data structures
2195 * @hba: per adapter instance
2196 *
2197 * 1. Allocate DMA memory for Command Descriptor array
2198 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
2199 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
2200 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
2201 * (UTMRDL)
2202 * 4. Allocate memory for local reference block(lrb).
2203 *
2204 * Returns 0 for success, non-zero in case of failure
2205 */
2206static int ufshcd_memory_alloc(struct ufs_hba *hba)
2207{
2208 size_t utmrdl_size, utrdl_size, ucdl_size;
2209
2210 /* Allocate memory for UTP command descriptors */
2211 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 2212 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
2213 ucdl_size,
2214 &hba->ucdl_dma_addr,
2215 GFP_KERNEL);
7a3e97b0
SY		 2216
2217 /*
2218 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
2219 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
2220 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
2221 * be aligned to 128 bytes as well
2222 */
2223 if (!hba->ucdl_base_addr ||
2224 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2225 dev_err(hba->dev,
7a3e97b0
SY		 2226 "Command Descriptor Memory allocation failed\n");
2227 goto out;
2228 }
2229
2230 /*
2231 * Allocate memory for UTP Transfer descriptors
2232 * UFSHCI requires 1024 byte alignment of UTRD
2233 */
2234 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 2235 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
2236 utrdl_size,
2237 &hba->utrdl_dma_addr,
2238 GFP_KERNEL);
7a3e97b0
SY		 2239 if (!hba->utrdl_base_addr ||
2240 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2241 dev_err(hba->dev,
7a3e97b0
SY		 2242 "Transfer Descriptor Memory allocation failed\n");
2243 goto out;
2244 }
2245
2246 /*
2247 * Allocate memory for UTP Task Management descriptors
2248 * UFSHCI requires 1024 byte alignment of UTMRD
2249 */
2250 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 2251 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
2252 utmrdl_size,
2253 &hba->utmrdl_dma_addr,
2254 GFP_KERNEL);
7a3e97b0
SY		 2255 if (!hba->utmrdl_base_addr ||
2256 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 2257 dev_err(hba->dev,
7a3e97b0
SY		 2258 "Task Management Descriptor Memory allocation failed\n");
2259 goto out;
2260 }
2261
2262 /* Allocate memory for local reference block */
2953f850
SJ		 2263 hba->lrb = devm_kzalloc(hba->dev,
2264 hba->nutrs * sizeof(struct ufshcd_lrb),
2265 GFP_KERNEL);
7a3e97b0 2266 if (!hba->lrb) {
3b1d0580 2267 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 2268 goto out;
2269 }
2270 return 0;
2271out:
7a3e97b0
SY		 2272 return -ENOMEM;
2273}
2274
2275/**
2276 * ufshcd_host_memory_configure - configure local reference block with
2277 * memory offsets
2278 * @hba: per adapter instance
2279 *
2280 * Configure Host memory space
2281 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
2282 * address.
2283 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
2284 * and PRDT offset.
2285 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
2286 * into local reference block.
2287 */
2288static void ufshcd_host_memory_configure(struct ufs_hba *hba)
2289{
2290 struct utp_transfer_cmd_desc *cmd_descp;
2291 struct utp_transfer_req_desc *utrdlp;
2292 dma_addr_t cmd_desc_dma_addr;
2293 dma_addr_t cmd_desc_element_addr;
2294 u16 response_offset;
2295 u16 prdt_offset;
2296 int cmd_desc_size;
2297 int i;
2298
2299 utrdlp = hba->utrdl_base_addr;
2300 cmd_descp = hba->ucdl_base_addr;
2301
2302 response_offset =
2303 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2304 prdt_offset =
2305 offsetof(struct utp_transfer_cmd_desc, prd_table);
2306
2307 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2308 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2309
2310 for (i = 0; i < hba->nutrs; i++) {
2311 /* Configure UTRD with command descriptor base address */
2312 cmd_desc_element_addr =
2313 (cmd_desc_dma_addr + (cmd_desc_size * i));
2314 utrdlp[i].command_desc_base_addr_lo =
2315 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2316 utrdlp[i].command_desc_base_addr_hi =
2317 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2318
2319 /* Response upiu and prdt offset should be in double words */
2320 utrdlp[i].response_upiu_offset =
2321 cpu_to_le16((response_offset >> 2));
2322 utrdlp[i].prd_table_offset =
2323 cpu_to_le16((prdt_offset >> 2));
2324 utrdlp[i].response_upiu_length =
3ca316c5 2325 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0
SY		 2326
2327 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 2328 hba->lrb[i].ucd_req_ptr =
2329 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 2330 hba->lrb[i].ucd_rsp_ptr =
2331 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2332 hba->lrb[i].ucd_prdt_ptr =
2333 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2334 }
2335}
2336
2337/**
2338 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2339 * @hba: per adapter instance
2340 *
2341 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2342 * in order to initialize the Unipro link startup procedure.
2343 * Once the Unipro links are up, the device connected to the controller
2344 * is detected.
2345 *
2346 * Returns 0 on success, non-zero value on failure
2347 */
2348static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2349{
6ccf44fe
SJ		 2350 struct uic_command uic_cmd = {0};
2351 int ret;
7a3e97b0 2352
6ccf44fe 2353 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2354
6ccf44fe
SJ		 2355 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2356 if (ret)
2357 dev_err(hba->dev,
2358 "dme-link-startup: error code %d\n", ret);
2359 return ret;
7a3e97b0
SY		 2360}
2361
cad2e03d
YG		 2362static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
2363{
2364 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
2365 unsigned long min_sleep_time_us;
2366
2367 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
2368 return;
2369
2370 /*
2371 * last_dme_cmd_tstamp will be 0 only for 1st call to
2372 * this function
2373 */
2374 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
2375 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
2376 } else {
2377 unsigned long delta =
2378 (unsigned long) ktime_to_us(
2379 ktime_sub(ktime_get(),
2380 hba->last_dme_cmd_tstamp));
2381
2382 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
2383 min_sleep_time_us =
2384 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
2385 else
2386 return; /* no more delay required */
2387 }
2388
2389 /* allow sleep for extra 50us if needed */
2390 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
2391}
2392
12b4fdb4
SJ		 2393/**
2394 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2395 * @hba: per adapter instance
2396 * @attr_sel: uic command argument1
2397 * @attr_set: attribute set type as uic command argument2
2398 * @mib_val: setting value as uic command argument3
2399 * @peer: indicate whether peer or local
2400 *
2401 * Returns 0 on success, non-zero value on failure
2402 */
2403int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2404 u8 attr_set, u32 mib_val, u8 peer)
2405{
2406 struct uic_command uic_cmd = {0};
2407 static const char *const action[] = {
2408 "dme-set",
2409 "dme-peer-set"
2410 };
2411 const char *set = action[!!peer];
2412 int ret;
64238fbd 2413 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 2414
2415 uic_cmd.command = peer ?
2416 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2417 uic_cmd.argument1 = attr_sel;
2418 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2419 uic_cmd.argument3 = mib_val;
2420
64238fbd
YG		 2421 do {
2422 /* for peer attributes we retry upon failure */
2423 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2424 if (ret)
2425 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2426 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2427 } while (ret && peer && --retries);
2428
2429 if (!retries)
2430 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
2431 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
2432 retries);
12b4fdb4
SJ		 2433
2434 return ret;
2435}
2436EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2437
2438/**
2439 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2440 * @hba: per adapter instance
2441 * @attr_sel: uic command argument1
2442 * @mib_val: the value of the attribute as returned by the UIC command
2443 * @peer: indicate whether peer or local
2444 *
2445 * Returns 0 on success, non-zero value on failure
2446 */
2447int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2448 u32 *mib_val, u8 peer)
2449{
2450 struct uic_command uic_cmd = {0};
2451 static const char *const action[] = {
2452 "dme-get",
2453 "dme-peer-get"
2454 };
2455 const char *get = action[!!peer];
2456 int ret;
64238fbd 2457 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 2458 struct ufs_pa_layer_attr orig_pwr_info;
2459 struct ufs_pa_layer_attr temp_pwr_info;
2460 bool pwr_mode_change = false;
2461
2462 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
2463 orig_pwr_info = hba->pwr_info;
2464 temp_pwr_info = orig_pwr_info;
2465
2466 if (orig_pwr_info.pwr_tx == FAST_MODE ||
2467 orig_pwr_info.pwr_rx == FAST_MODE) {
2468 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
2469 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
2470 pwr_mode_change = true;
2471 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
2472 orig_pwr_info.pwr_rx == SLOW_MODE) {
2473 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
2474 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
2475 pwr_mode_change = true;
2476 }
2477 if (pwr_mode_change) {
2478 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
2479 if (ret)
2480 goto out;
2481 }
2482 }
12b4fdb4
SJ		 2483
2484 uic_cmd.command = peer ?
2485 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2486 uic_cmd.argument1 = attr_sel;
2487
64238fbd
YG		 2488 do {
2489 /* for peer attributes we retry upon failure */
2490 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2491 if (ret)
2492 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
2493 get, UIC_GET_ATTR_ID(attr_sel), ret);
2494 } while (ret && peer && --retries);
2495
2496 if (!retries)
2497 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
2498 get, UIC_GET_ATTR_ID(attr_sel), retries);
12b4fdb4 2499
64238fbd 2500 if (mib_val && !ret)
12b4fdb4 2501 *mib_val = uic_cmd.argument3;
874237f7
YG		 2502
2503 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
2504 && pwr_mode_change)
2505 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 2506out:
2507 return ret;
2508}
2509EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2510
53b3d9c3 2511/**
57d104c1
SJ		 2512 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2513 * state) and waits for it to take effect.
2514 *
53b3d9c3 2515 * @hba: per adapter instance
57d104c1
SJ		 2516 * @cmd: UIC command to execute
2517 *
2518 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2519 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2520 * and device UniPro link and hence it's final completion would be indicated by
2521 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2522 * addition to normal UIC command completion Status (UCCS). This function only
2523 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 2524 *
2525 * Returns 0 on success, non-zero value on failure
2526 */
57d104c1 2527static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2528{
57d104c1 2529 struct completion uic_async_done;
53b3d9c3
SJ		 2530 unsigned long flags;
2531 u8 status;
2532 int ret;
d75f7fe4 2533 bool reenable_intr = false;
53b3d9c3 2534
53b3d9c3 2535 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2536 init_completion(&uic_async_done);
cad2e03d 2537 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 2538
2539 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2540 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 2541 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
2542 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
2543 /*
2544 * Make sure UIC command completion interrupt is disabled before
2545 * issuing UIC command.
2546 */
2547 wmb();
2548 reenable_intr = true;
57d104c1 2549 }
d75f7fe4
YG		 2550 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
2551 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 2552 if (ret) {
2553 dev_err(hba->dev,
2554 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2555 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 2556 goto out;
2557 }
2558
57d104c1 2559 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 2560 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2561 dev_err(hba->dev,
57d104c1
SJ		 2562 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2563 cmd->command, cmd->argument3);
53b3d9c3
SJ		 2564 ret = -ETIMEDOUT;
2565 goto out;
2566 }
2567
2568 status = ufshcd_get_upmcrs(hba);
2569 if (status != PWR_LOCAL) {
2570 dev_err(hba->dev,
73615428 2571 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 2572 cmd->command, status);
53b3d9c3
SJ		 2573 ret = (status != PWR_OK) ? status : -1;
2574 }
2575out:
2576 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2577 hba->active_uic_cmd = NULL;
57d104c1 2578 hba->uic_async_done = NULL;
d75f7fe4
YG		 2579 if (reenable_intr)
2580 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 2581 spin_unlock_irqrestore(hba->host->host_lock, flags);
2582 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2583
53b3d9c3
SJ		 2584 return ret;
2585}
2586
57d104c1
SJ		 2587/**
2588 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2589 * using DME_SET primitives.
2590 * @hba: per adapter instance
2591 * @mode: powr mode value
2592 *
2593 * Returns 0 on success, non-zero value on failure
2594 */
2595static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2596{
2597 struct uic_command uic_cmd = {0};
1ab27c9c 2598 int ret;
57d104c1 2599
c3a2f9ee
YG		 2600 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
2601 ret = ufshcd_dme_set(hba,
2602 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
2603 if (ret) {
2604 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
2605 __func__, ret);
2606 goto out;
2607 }
2608 }
2609
57d104c1
SJ		 2610 uic_cmd.command = UIC_CMD_DME_SET;
2611 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2612 uic_cmd.argument3 = mode;
1ab27c9c
ST		 2613 ufshcd_hold(hba, false);
2614 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2615 ufshcd_release(hba);
57d104c1 2616
c3a2f9ee 2617out:
1ab27c9c 2618 return ret;
57d104c1
SJ		 2619}
2620
53c12d0e
YG		 2621static int ufshcd_link_recovery(struct ufs_hba *hba)
2622{
2623 int ret;
2624 unsigned long flags;
2625
2626 spin_lock_irqsave(hba->host->host_lock, flags);
2627 hba->ufshcd_state = UFSHCD_STATE_RESET;
2628 ufshcd_set_eh_in_progress(hba);
2629 spin_unlock_irqrestore(hba->host->host_lock, flags);
2630
2631 ret = ufshcd_host_reset_and_restore(hba);
2632
2633 spin_lock_irqsave(hba->host->host_lock, flags);
2634 if (ret)
2635 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2636 ufshcd_clear_eh_in_progress(hba);
2637 spin_unlock_irqrestore(hba->host->host_lock, flags);
2638
2639 if (ret)
2640 dev_err(hba->dev, "%s: link recovery failed, err %d",
2641 __func__, ret);
2642
2643 return ret;
2644}
2645
87d0b4a6 2646static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 2647{
87d0b4a6 2648 int ret;
57d104c1
SJ		 2649 struct uic_command uic_cmd = {0};
2650
2651 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6
YG		 2652 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2653
53c12d0e 2654 if (ret) {
87d0b4a6
YG		 2655 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
2656 __func__, ret);
2657
53c12d0e
YG		 2658 /*
2659 * If link recovery fails then return error so that caller
2660 * don't retry the hibern8 enter again.
2661 */
2662 if (ufshcd_link_recovery(hba))
2663 ret = -ENOLINK;
2664 }
2665
87d0b4a6
YG		 2666 return ret;
2667}
2668
2669static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2670{
2671 int ret = 0, retries;
57d104c1 2672
87d0b4a6
YG		 2673 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
2674 ret = __ufshcd_uic_hibern8_enter(hba);
2675 if (!ret || ret == -ENOLINK)
2676 goto out;
2677 }
2678out:
2679 return ret;
57d104c1
SJ		 2680}
2681
2682static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2683{
2684 struct uic_command uic_cmd = {0};
2685 int ret;
2686
2687 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2688 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2689 if (ret) {
53c12d0e
YG		 2690 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
2691 __func__, ret);
2692 ret = ufshcd_link_recovery(hba);
57d104c1
SJ		 2693 }
2694
2695 return ret;
2696}
2697
5064636c
YG		 2698 /**
2699 * ufshcd_init_pwr_info - setting the POR (power on reset)
2700 * values in hba power info
2701 * @hba: per-adapter instance
2702 */
2703static void ufshcd_init_pwr_info(struct ufs_hba *hba)
2704{
2705 hba->pwr_info.gear_rx = UFS_PWM_G1;
2706 hba->pwr_info.gear_tx = UFS_PWM_G1;
2707 hba->pwr_info.lane_rx = 1;
2708 hba->pwr_info.lane_tx = 1;
2709 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
2710 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
2711 hba->pwr_info.hs_rate = 0;
2712}
2713
d3e89bac 2714/**
7eb584db
DR		 2715 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2716 * @hba: per-adapter instance
d3e89bac 2717 */
7eb584db 2718static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 2719{
7eb584db
DR		 2720 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2721
2722 if (hba->max_pwr_info.is_valid)
2723 return 0;
2724
2725 pwr_info->pwr_tx = FASTAUTO_MODE;
2726 pwr_info->pwr_rx = FASTAUTO_MODE;
2727 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 2728
2729 /* Get the connected lane count */
7eb584db
DR		 2730 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2731 &pwr_info->lane_rx);
2732 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2733 &pwr_info->lane_tx);
2734
2735 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2736 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2737 __func__,
2738 pwr_info->lane_rx,
2739 pwr_info->lane_tx);
2740 return -EINVAL;
2741 }
d3e89bac
SJ		 2742
2743 /*
2744 * First, get the maximum gears of HS speed.
2745 * If a zero value, it means there is no HSGEAR capability.
2746 * Then, get the maximum gears of PWM speed.
2747 */
7eb584db
DR		 2748 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2749 if (!pwr_info->gear_rx) {
2750 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2751 &pwr_info->gear_rx);
2752 if (!pwr_info->gear_rx) {
2753 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2754 __func__, pwr_info->gear_rx);
2755 return -EINVAL;
2756 }
2757 pwr_info->pwr_rx = SLOWAUTO_MODE;
d3e89bac
SJ		 2758 }
2759
7eb584db
DR		 2760 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2761 &pwr_info->gear_tx);
2762 if (!pwr_info->gear_tx) {
d3e89bac 2763 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 2764 &pwr_info->gear_tx);
2765 if (!pwr_info->gear_tx) {
2766 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2767 __func__, pwr_info->gear_tx);
2768 return -EINVAL;
2769 }
2770 pwr_info->pwr_tx = SLOWAUTO_MODE;
2771 }
2772
2773 hba->max_pwr_info.is_valid = true;
2774 return 0;
2775}
2776
2777static int ufshcd_change_power_mode(struct ufs_hba *hba,
2778 struct ufs_pa_layer_attr *pwr_mode)
2779{
2780 int ret;
2781
2782 /* if already configured to the requested pwr_mode */
2783 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2784 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2785 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2786 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2787 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2788 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2789 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2790 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2791 return 0;
d3e89bac
SJ		 2792 }
2793
2794 /*
2795 * Configure attributes for power mode change with below.
2796 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2797 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2798 * - PA_HSSERIES
2799 */
7eb584db
DR		 2800 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2801 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2802 pwr_mode->lane_rx);
2803 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2804 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 2805 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 2806 else
2807 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 2808
7eb584db
DR		 2809 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2810 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2811 pwr_mode->lane_tx);
2812 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2813 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 2814 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 2815 else
2816 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 2817
7eb584db
DR		 2818 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2819 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2820 pwr_mode->pwr_rx == FAST_MODE ||
2821 pwr_mode->pwr_tx == FAST_MODE)
2822 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2823 pwr_mode->hs_rate);
d3e89bac 2824
7eb584db
DR		 2825 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2826 | pwr_mode->pwr_tx);
2827
2828 if (ret) {
d3e89bac 2829 dev_err(hba->dev,
7eb584db
DR		 2830 "%s: power mode change failed %d\n", __func__, ret);
2831 } else {
0263bcd0
YG		 2832 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
2833 pwr_mode);
7eb584db
DR		 2834
2835 memcpy(&hba->pwr_info, pwr_mode,
2836 sizeof(struct ufs_pa_layer_attr));
2837 }
2838
2839 return ret;
2840}
2841
2842/**
2843 * ufshcd_config_pwr_mode - configure a new power mode
2844 * @hba: per-adapter instance
2845 * @desired_pwr_mode: desired power configuration
2846 */
2847static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2848 struct ufs_pa_layer_attr *desired_pwr_mode)
2849{
2850 struct ufs_pa_layer_attr final_params = { 0 };
2851 int ret;
2852
0263bcd0
YG		 2853 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
2854 desired_pwr_mode, &final_params);
2855
2856 if (ret)
7eb584db
DR		 2857 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2858
2859 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 2860
2861 return ret;
2862}
2863
68078d5c
DR		 2864/**
2865 * ufshcd_complete_dev_init() - checks device readiness
2866 * hba: per-adapter instance
2867 *
2868 * Set fDeviceInit flag and poll until device toggles it.
2869 */
2870static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2871{
dc3c8d3a
YG		 2872 int i;
2873 int err;
68078d5c
DR		 2874 bool flag_res = 1;
2875
dc3c8d3a
YG		 2876 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2877 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 2878 if (err) {
2879 dev_err(hba->dev,
2880 "%s setting fDeviceInit flag failed with error %d\n",
2881 __func__, err);
2882 goto out;
2883 }
2884
dc3c8d3a
YG		 2885 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
2886 for (i = 0; i < 1000 && !err && flag_res; i++)
2887 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
2888 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2889
68078d5c
DR		 2890 if (err)
2891 dev_err(hba->dev,
2892 "%s reading fDeviceInit flag failed with error %d\n",
2893 __func__, err);
2894 else if (flag_res)
2895 dev_err(hba->dev,
2896 "%s fDeviceInit was not cleared by the device\n",
2897 __func__);
2898
2899out:
2900 return err;
2901}
2902
7a3e97b0
SY		 2903/**
2904 * ufshcd_make_hba_operational - Make UFS controller operational
2905 * @hba: per adapter instance
2906 *
2907 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 2908 * 1. Enable required interrupts
2909 * 2. Configure interrupt aggregation
897efe62 2910 * 3. Program UTRL and UTMRL base address
5c0c28a8 2911 * 4. Configure run-stop-registers
7a3e97b0
SY		 2912 *
2913 * Returns 0 on success, non-zero value on failure
2914 */
2915static int ufshcd_make_hba_operational(struct ufs_hba *hba)
2916{
2917 int err = 0;
2918 u32 reg;
2919
6ccf44fe
SJ		 2920 /* Enable required interrupts */
2921 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
2922
2923 /* Configure interrupt aggregation */
b852190e
YG		 2924 if (ufshcd_is_intr_aggr_allowed(hba))
2925 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
2926 else
2927 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 2928
2929 /* Configure UTRL and UTMRL base address registers */
2930 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
2931 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
2932 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
2933 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
2934 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
2935 REG_UTP_TASK_REQ_LIST_BASE_L);
2936 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
2937 REG_UTP_TASK_REQ_LIST_BASE_H);
2938
897efe62
YG		 2939 /*
2940 * Make sure base address and interrupt setup are updated before
2941 * enabling the run/stop registers below.
2942 */
2943 wmb();
2944
7a3e97b0
SY		 2945 /*
2946 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 2947 */
5c0c28a8 2948 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 2949 if (!(ufshcd_get_lists_status(reg))) {
2950 ufshcd_enable_run_stop_reg(hba);
2951 } else {
3b1d0580 2952 dev_err(hba->dev,
7a3e97b0
SY		 2953 "Host controller not ready to process requests");
2954 err = -EIO;
2955 goto out;
2956 }
2957
7a3e97b0
SY		 2958out:
2959 return err;
2960}
2961
596585a2
YG		 2962/**
2963 * ufshcd_hba_stop - Send controller to reset state
2964 * @hba: per adapter instance
2965 * @can_sleep: perform sleep or just spin
2966 */
2967static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
2968{
2969 int err;
2970
2971 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
2972 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
2973 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
2974 10, 1, can_sleep);
2975 if (err)
2976 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
2977}
2978
7a3e97b0
SY		 2979/**
2980 * ufshcd_hba_enable - initialize the controller
2981 * @hba: per adapter instance
2982 *
2983 * The controller resets itself and controller firmware initialization
2984 * sequence kicks off. When controller is ready it will set
2985 * the Host Controller Enable bit to 1.
2986 *
2987 * Returns 0 on success, non-zero value on failure
2988 */
2989static int ufshcd_hba_enable(struct ufs_hba *hba)
2990{
2991 int retry;
2992
2993 /*
2994 * msleep of 1 and 5 used in this function might result in msleep(20),
2995 * but it was necessary to send the UFS FPGA to reset mode during
2996 * development and testing of this driver. msleep can be changed to
2997 * mdelay and retry count can be reduced based on the controller.
2998 */
596585a2 2999 if (!ufshcd_is_hba_active(hba))
7a3e97b0 3000 /* change controller state to "reset state" */
596585a2 3001 ufshcd_hba_stop(hba, true);
7a3e97b0 3002
57d104c1
SJ		 3003 /* UniPro link is disabled at this point */
3004 ufshcd_set_link_off(hba);
3005
0263bcd0 3006 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 3007
7a3e97b0
SY		 3008 /* start controller initialization sequence */
3009 ufshcd_hba_start(hba);
3010
3011 /*
3012 * To initialize a UFS host controller HCE bit must be set to 1.
3013 * During initialization the HCE bit value changes from 1->0->1.
3014 * When the host controller completes initialization sequence
3015 * it sets the value of HCE bit to 1. The same HCE bit is read back
3016 * to check if the controller has completed initialization sequence.
3017 * So without this delay the value HCE = 1, set in the previous
3018 * instruction might be read back.
3019 * This delay can be changed based on the controller.
3020 */
3021 msleep(1);
3022
3023 /* wait for the host controller to complete initialization */
3024 retry = 10;
3025 while (ufshcd_is_hba_active(hba)) {
3026 if (retry) {
3027 retry--;
3028 } else {
3b1d0580 3029 dev_err(hba->dev,
7a3e97b0
SY		 3030 "Controller enable failed\n");
3031 return -EIO;
3032 }
3033 msleep(5);
3034 }
5c0c28a8 3035
1d337ec2 3036 /* enable UIC related interrupts */
57d104c1 3037 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 3038
0263bcd0 3039 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 3040
7a3e97b0
SY		 3041 return 0;
3042}
3043
7ca38cf3
YG		 3044static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
3045{
3046 int tx_lanes, i, err = 0;
3047
3048 if (!peer)
3049 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3050 &tx_lanes);
3051 else
3052 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3053 &tx_lanes);
3054 for (i = 0; i < tx_lanes; i++) {
3055 if (!peer)
3056 err = ufshcd_dme_set(hba,
3057 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3058 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3059 0);
3060 else
3061 err = ufshcd_dme_peer_set(hba,
3062 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
3063 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
3064 0);
3065 if (err) {
3066 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
3067 __func__, peer, i, err);
3068 break;
3069 }
3070 }
3071
3072 return err;
3073}
3074
3075static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
3076{
3077 return ufshcd_disable_tx_lcc(hba, true);
3078}
3079
7a3e97b0 3080/**
6ccf44fe 3081 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 3082 * @hba: per adapter instance
3083 *
6ccf44fe 3084 * Returns 0 for success, non-zero in case of failure
7a3e97b0 3085 */
6ccf44fe 3086static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 3087{
6ccf44fe 3088 int ret;
1d337ec2 3089 int retries = DME_LINKSTARTUP_RETRIES;
7a3e97b0 3090
1d337ec2 3091 do {
0263bcd0 3092 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 3093
1d337ec2 3094 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 3095
1d337ec2
SRT		 3096 /* check if device is detected by inter-connect layer */
3097 if (!ret && !ufshcd_is_device_present(hba)) {
3098 dev_err(hba->dev, "%s: Device not present\n", __func__);
3099 ret = -ENXIO;
3100 goto out;
3101 }
6ccf44fe 3102
1d337ec2
SRT		 3103 /*
3104 * DME link lost indication is only received when link is up,
3105 * but we can't be sure if the link is up until link startup
3106 * succeeds. So reset the local Uni-Pro and try again.
3107 */
3108 if (ret && ufshcd_hba_enable(hba))
3109 goto out;
3110 } while (ret && retries--);
3111
3112 if (ret)
3113 /* failed to get the link up... retire */
5c0c28a8 3114 goto out;
5c0c28a8 3115
7ca38cf3
YG		 3116 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
3117 ret = ufshcd_disable_device_tx_lcc(hba);
3118 if (ret)
3119 goto out;
3120 }
3121
5c0c28a8 3122 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 3123 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
3124 if (ret)
3125 goto out;
7a3e97b0 3126
5c0c28a8 3127 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 3128out:
3129 if (ret)
3130 dev_err(hba->dev, "link startup failed %d\n", ret);
3131 return ret;
7a3e97b0
SY		 3132}
3133
5a0b0cb9
SRT		 3134/**
3135 * ufshcd_verify_dev_init() - Verify device initialization
3136 * @hba: per-adapter instance
3137 *
3138 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
3139 * device Transport Protocol (UTP) layer is ready after a reset.
3140 * If the UTP layer at the device side is not initialized, it may
3141 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
3142 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
3143 */
3144static int ufshcd_verify_dev_init(struct ufs_hba *hba)
3145{
3146 int err = 0;
3147 int retries;
3148
1ab27c9c 3149 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 3150 mutex_lock(&hba->dev_cmd.lock);
3151 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
3152 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
3153 NOP_OUT_TIMEOUT);
3154
3155 if (!err || err == -ETIMEDOUT)
3156 break;
3157
3158 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
3159 }
3160 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 3161 ufshcd_release(hba);
5a0b0cb9
SRT		 3162
3163 if (err)
3164 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
3165 return err;
3166}
3167
0ce147d4
SJ		 3168/**
3169 * ufshcd_set_queue_depth - set lun queue depth
3170 * @sdev: pointer to SCSI device
3171 *
3172 * Read bLUQueueDepth value and activate scsi tagged command
3173 * queueing. For WLUN, queue depth is set to 1. For best-effort
3174 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
3175 * value that host can queue.
3176 */
3177static void ufshcd_set_queue_depth(struct scsi_device *sdev)
3178{
3179 int ret = 0;
3180 u8 lun_qdepth;
3181 struct ufs_hba *hba;
3182
3183 hba = shost_priv(sdev->host);
3184
3185 lun_qdepth = hba->nutrs;
3186 ret = ufshcd_read_unit_desc_param(hba,
3187 ufshcd_scsi_to_upiu_lun(sdev->lun),
3188 UNIT_DESC_PARAM_LU_Q_DEPTH,
3189 &lun_qdepth,
3190 sizeof(lun_qdepth));
3191
3192 /* Some WLUN doesn't support unit descriptor */
3193 if (ret == -EOPNOTSUPP)
3194 lun_qdepth = 1;
3195 else if (!lun_qdepth)
3196 /* eventually, we can figure out the real queue depth */
3197 lun_qdepth = hba->nutrs;
3198 else
3199 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
3200
3201 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
3202 __func__, lun_qdepth);
db5ed4df 3203 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 3204}
3205
57d104c1
SJ		 3206/*
3207 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
3208 * @hba: per-adapter instance
3209 * @lun: UFS device lun id
3210 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
3211 *
3212 * Returns 0 in case of success and b_lu_write_protect status would be returned
3213 * @b_lu_write_protect parameter.
3214 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
3215 * Returns -EINVAL in case of invalid parameters passed to this function.
3216 */
3217static int ufshcd_get_lu_wp(struct ufs_hba *hba,
3218 u8 lun,
3219 u8 *b_lu_write_protect)
3220{
3221 int ret;
3222
3223 if (!b_lu_write_protect)
3224 ret = -EINVAL;
3225 /*
3226 * According to UFS device spec, RPMB LU can't be write
3227 * protected so skip reading bLUWriteProtect parameter for
3228 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
3229 */
3230 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
3231 ret = -ENOTSUPP;
3232 else
3233 ret = ufshcd_read_unit_desc_param(hba,
3234 lun,
3235 UNIT_DESC_PARAM_LU_WR_PROTECT,
3236 b_lu_write_protect,
3237 sizeof(*b_lu_write_protect));
3238 return ret;
3239}
3240
3241/**
3242 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
3243 * status
3244 * @hba: per-adapter instance
3245 * @sdev: pointer to SCSI device
3246 *
3247 */
3248static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
3249 struct scsi_device *sdev)
3250{
3251 if (hba->dev_info.f_power_on_wp_en &&
3252 !hba->dev_info.is_lu_power_on_wp) {
3253 u8 b_lu_write_protect;
3254
3255 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
3256 &b_lu_write_protect) &&
3257 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
3258 hba->dev_info.is_lu_power_on_wp = true;
3259 }
3260}
3261
7a3e97b0
SY		 3262/**
3263 * ufshcd_slave_alloc - handle initial SCSI device configurations
3264 * @sdev: pointer to SCSI device
3265 *
3266 * Returns success
3267 */
3268static int ufshcd_slave_alloc(struct scsi_device *sdev)
3269{
3270 struct ufs_hba *hba;
3271
3272 hba = shost_priv(sdev->host);
7a3e97b0
SY		 3273
3274 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
3275 sdev->use_10_for_ms = 1;
7a3e97b0 3276
e8e7f271
SRT		 3277 /* allow SCSI layer to restart the device in case of errors */
3278 sdev->allow_restart = 1;
4264fd61 3279
b2a6c522
SRT		 3280 /* REPORT SUPPORTED OPERATION CODES is not supported */
3281 sdev->no_report_opcodes = 1;
3282
e8e7f271 3283
0ce147d4 3284 ufshcd_set_queue_depth(sdev);
4264fd61 3285
57d104c1
SJ		 3286 ufshcd_get_lu_power_on_wp_status(hba, sdev);
3287
7a3e97b0
SY		 3288 return 0;
3289}
3290
4264fd61
SRT		 3291/**
3292 * ufshcd_change_queue_depth - change queue depth
3293 * @sdev: pointer to SCSI device
3294 * @depth: required depth to set
4264fd61 3295 *
db5ed4df 3296 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 3297 */
db5ed4df 3298static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 3299{
3300 struct ufs_hba *hba = shost_priv(sdev->host);
3301
3302 if (depth > hba->nutrs)
3303 depth = hba->nutrs;
db5ed4df 3304 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 3305}
3306
eeda4749
AM		 3307/**
3308 * ufshcd_slave_configure - adjust SCSI device configurations
3309 * @sdev: pointer to SCSI device
3310 */
3311static int ufshcd_slave_configure(struct scsi_device *sdev)
3312{
3313 struct request_queue *q = sdev->request_queue;
3314
3315 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
3316 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
3317
3318 return 0;
3319}
3320
7a3e97b0
SY		 3321/**
3322 * ufshcd_slave_destroy - remove SCSI device configurations
3323 * @sdev: pointer to SCSI device
3324 */
3325static void ufshcd_slave_destroy(struct scsi_device *sdev)
3326{
3327 struct ufs_hba *hba;
3328
3329 hba = shost_priv(sdev->host);
0ce147d4 3330 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 3331 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
3332 unsigned long flags;
3333
3334 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 3335 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 3336 spin_unlock_irqrestore(hba->host->host_lock, flags);
3337 }
7a3e97b0
SY		 3338}
3339
3340/**
3341 * ufshcd_task_req_compl - handle task management request completion
3342 * @hba: per adapter instance
3343 * @index: index of the completed request
e2933132 3344 * @resp: task management service response
7a3e97b0 3345 *
e2933132 3346 * Returns non-zero value on error, zero on success
7a3e97b0 3347 */
e2933132 3348static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 3349{
3350 struct utp_task_req_desc *task_req_descp;
3351 struct utp_upiu_task_rsp *task_rsp_upiup;
3352 unsigned long flags;
3353 int ocs_value;
3354 int task_result;
3355
3356 spin_lock_irqsave(hba->host->host_lock, flags);
3357
3358 /* Clear completed tasks from outstanding_tasks */
3359 __clear_bit(index, &hba->outstanding_tasks);
3360
3361 task_req_descp = hba->utmrdl_base_addr;
3362 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
3363
3364 if (ocs_value == OCS_SUCCESS) {
3365 task_rsp_upiup = (struct utp_upiu_task_rsp *)
3366 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 3367 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
3368 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 3369 if (resp)
3370 *resp = (u8)task_result;
7a3e97b0 3371 } else {
e2933132
SRT		 3372 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
3373 __func__, ocs_value);
7a3e97b0
SY		 3374 }
3375 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 3376
3377 return ocs_value;
7a3e97b0
SY		 3378}
3379
7a3e97b0
SY		 3380/**
3381 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
3382 * @lrb: pointer to local reference block of completed command
3383 * @scsi_status: SCSI command status
3384 *
3385 * Returns value base on SCSI command status
3386 */
3387static inline int
3388ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
3389{
3390 int result = 0;
3391
3392 switch (scsi_status) {
7a3e97b0 3393 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 3394 ufshcd_copy_sense_data(lrbp);
3395 case SAM_STAT_GOOD:
7a3e97b0
SY		 3396 result |= DID_OK << 16 |
3397 COMMAND_COMPLETE << 8 |
1c2623c5 3398 scsi_status;
7a3e97b0
SY		 3399 break;
3400 case SAM_STAT_TASK_SET_FULL:
1c2623c5 3401 case SAM_STAT_BUSY:
7a3e97b0 3402 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 3403 ufshcd_copy_sense_data(lrbp);
3404 result |= scsi_status;
7a3e97b0
SY		 3405 break;
3406 default:
3407 result |= DID_ERROR << 16;
3408 break;
3409 } /* end of switch */
3410
3411 return result;
3412}
3413
3414/**
3415 * ufshcd_transfer_rsp_status - Get overall status of the response
3416 * @hba: per adapter instance
3417 * @lrb: pointer to local reference block of completed command
3418 *
3419 * Returns result of the command to notify SCSI midlayer
3420 */
3421static inline int
3422ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3423{
3424 int result = 0;
3425 int scsi_status;
3426 int ocs;
3427
3428 /* overall command status of utrd */
3429 ocs = ufshcd_get_tr_ocs(lrbp);
3430
3431 switch (ocs) {
3432 case OCS_SUCCESS:
5a0b0cb9 3433 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 3434
5a0b0cb9
SRT		 3435 switch (result) {
3436 case UPIU_TRANSACTION_RESPONSE:
3437 /*
3438 * get the response UPIU result to extract
3439 * the SCSI command status
3440 */
3441 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
3442
3443 /*
3444 * get the result based on SCSI status response
3445 * to notify the SCSI midlayer of the command status
3446 */
3447 scsi_status = result & MASK_SCSI_STATUS;
3448 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 3449
f05ac2e5
YG		 3450 /*
3451 * Currently we are only supporting BKOPs exception
3452 * events hence we can ignore BKOPs exception event
3453 * during power management callbacks. BKOPs exception
3454 * event is not expected to be raised in runtime suspend
3455 * callback as it allows the urgent bkops.
3456 * During system suspend, we are anyway forcefully
3457 * disabling the bkops and if urgent bkops is needed
3458 * it will be enabled on system resume. Long term
3459 * solution could be to abort the system suspend if
3460 * UFS device needs urgent BKOPs.
3461 */
3462 if (!hba->pm_op_in_progress &&
3463 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 3464 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 3465 break;
3466 case UPIU_TRANSACTION_REJECT_UPIU:
3467 /* TODO: handle Reject UPIU Response */
3468 result = DID_ERROR << 16;
3b1d0580 3469 dev_err(hba->dev,
5a0b0cb9
SRT		 3470 "Reject UPIU not fully implemented\n");
3471 break;
3472 default:
3473 result = DID_ERROR << 16;
3474 dev_err(hba->dev,
3475 "Unexpected request response code = %x\n",
3476 result);
7a3e97b0
SY		 3477 break;
3478 }
7a3e97b0
SY		 3479 break;
3480 case OCS_ABORTED:
3481 result |= DID_ABORT << 16;
3482 break;
e8e7f271
SRT		 3483 case OCS_INVALID_COMMAND_STATUS:
3484 result |= DID_REQUEUE << 16;
3485 break;
7a3e97b0
SY		 3486 case OCS_INVALID_CMD_TABLE_ATTR:
3487 case OCS_INVALID_PRDT_ATTR:
3488 case OCS_MISMATCH_DATA_BUF_SIZE:
3489 case OCS_MISMATCH_RESP_UPIU_SIZE:
3490 case OCS_PEER_COMM_FAILURE:
3491 case OCS_FATAL_ERROR:
3492 default:
3493 result |= DID_ERROR << 16;
3b1d0580 3494 dev_err(hba->dev,
7a3e97b0
SY		 3495 "OCS error from controller = %x\n", ocs);
3496 break;
3497 } /* end of switch */
3498
3499 return result;
3500}
3501
6ccf44fe
SJ		 3502/**
3503 * ufshcd_uic_cmd_compl - handle completion of uic command
3504 * @hba: per adapter instance
53b3d9c3 3505 * @intr_status: interrupt status generated by the controller
6ccf44fe 3506 */
53b3d9c3 3507static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3508{
53b3d9c3 3509 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 3510 hba->active_uic_cmd->argument2 |=
3511 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 3512 hba->active_uic_cmd->argument3 =
3513 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 3514 complete(&hba->active_uic_cmd->done);
3515 }
53b3d9c3 3516
57d104c1
SJ		 3517 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3518 complete(hba->uic_async_done);
6ccf44fe
SJ		 3519}
3520
7a3e97b0 3521/**
9a47ec7c 3522 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 3523 * @hba: per adapter instance
9a47ec7c 3524 * @completed_reqs: requests to complete
7a3e97b0 3525 */
9a47ec7c
YG		 3526static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
3527 unsigned long completed_reqs)
7a3e97b0 3528{
5a0b0cb9
SRT		 3529 struct ufshcd_lrb *lrbp;
3530 struct scsi_cmnd *cmd;
7a3e97b0
SY		 3531 int result;
3532 int index;
e9d501b1 3533
e9d501b1
DR		 3534 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3535 lrbp = &hba->lrb[index];
3536 cmd = lrbp->cmd;
3537 if (cmd) {
3538 result = ufshcd_transfer_rsp_status(hba, lrbp);
3539 scsi_dma_unmap(cmd);
3540 cmd->result = result;
3541 /* Mark completed command as NULL in LRB */
3542 lrbp->cmd = NULL;
3543 clear_bit_unlock(index, &hba->lrb_in_use);
3544 /* Do not touch lrbp after scsi done */
3545 cmd->scsi_done(cmd);
1ab27c9c 3546 __ufshcd_release(hba);
300bb13f
JP		 3547 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
3548 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
e9d501b1
DR		 3549 if (hba->dev_cmd.complete)
3550 complete(hba->dev_cmd.complete);
3551 }
3552 }
7a3e97b0
SY		 3553
3554 /* clear corresponding bits of completed commands */
3555 hba->outstanding_reqs ^= completed_reqs;
3556
856b3483
ST		 3557 ufshcd_clk_scaling_update_busy(hba);
3558
5a0b0cb9
SRT		 3559 /* we might have free'd some tags above */
3560 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 3561}
3562
9a47ec7c
YG		 3563/**
3564 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3565 * @hba: per adapter instance
3566 */
3567static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3568{
3569 unsigned long completed_reqs;
3570 u32 tr_doorbell;
3571
3572 /* Resetting interrupt aggregation counters first and reading the
3573 * DOOR_BELL afterward allows us to handle all the completed requests.
3574 * In order to prevent other interrupts starvation the DB is read once
3575 * after reset. The down side of this solution is the possibility of
3576 * false interrupt if device completes another request after resetting
3577 * aggregation and before reading the DB.
3578 */
3579 if (ufshcd_is_intr_aggr_allowed(hba))
3580 ufshcd_reset_intr_aggr(hba);
3581
3582 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3583 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3584
3585 __ufshcd_transfer_req_compl(hba, completed_reqs);
3586}
3587
66ec6d59
SRT		 3588/**
3589 * ufshcd_disable_ee - disable exception event
3590 * @hba: per-adapter instance
3591 * @mask: exception event to disable
3592 *
3593 * Disables exception event in the device so that the EVENT_ALERT
3594 * bit is not set.
3595 *
3596 * Returns zero on success, non-zero error value on failure.
3597 */
3598static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3599{
3600 int err = 0;
3601 u32 val;
3602
3603 if (!(hba->ee_ctrl_mask & mask))
3604 goto out;
3605
3606 val = hba->ee_ctrl_mask & ~mask;
3607 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3608 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 3609 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3610 if (!err)
3611 hba->ee_ctrl_mask &= ~mask;
3612out:
3613 return err;
3614}
3615
3616/**
3617 * ufshcd_enable_ee - enable exception event
3618 * @hba: per-adapter instance
3619 * @mask: exception event to enable
3620 *
3621 * Enable corresponding exception event in the device to allow
3622 * device to alert host in critical scenarios.
3623 *
3624 * Returns zero on success, non-zero error value on failure.
3625 */
3626static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3627{
3628 int err = 0;
3629 u32 val;
3630
3631 if (hba->ee_ctrl_mask & mask)
3632 goto out;
3633
3634 val = hba->ee_ctrl_mask | mask;
3635 val &= 0xFFFF; /* 2 bytes */
5e86ae44 3636 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 3637 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3638 if (!err)
3639 hba->ee_ctrl_mask |= mask;
3640out:
3641 return err;
3642}
3643
3644/**
3645 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3646 * @hba: per-adapter instance
3647 *
3648 * Allow device to manage background operations on its own. Enabling
3649 * this might lead to inconsistent latencies during normal data transfers
3650 * as the device is allowed to manage its own way of handling background
3651 * operations.
3652 *
3653 * Returns zero on success, non-zero on failure.
3654 */
3655static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3656{
3657 int err = 0;
3658
3659 if (hba->auto_bkops_enabled)
3660 goto out;
3661
dc3c8d3a 3662 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 3663 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3664 if (err) {
3665 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3666 __func__, err);
3667 goto out;
3668 }
3669
3670 hba->auto_bkops_enabled = true;
3671
3672 /* No need of URGENT_BKOPS exception from the device */
3673 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3674 if (err)
3675 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3676 __func__, err);
3677out:
3678 return err;
3679}
3680
3681/**
3682 * ufshcd_disable_auto_bkops - block device in doing background operations
3683 * @hba: per-adapter instance
3684 *
3685 * Disabling background operations improves command response latency but
3686 * has drawback of device moving into critical state where the device is
3687 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3688 * host is idle so that BKOPS are managed effectively without any negative
3689 * impacts.
3690 *
3691 * Returns zero on success, non-zero on failure.
3692 */
3693static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3694{
3695 int err = 0;
3696
3697 if (!hba->auto_bkops_enabled)
3698 goto out;
3699
3700 /*
3701 * If host assisted BKOPs is to be enabled, make sure
3702 * urgent bkops exception is allowed.
3703 */
3704 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3705 if (err) {
3706 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3707 __func__, err);
3708 goto out;
3709 }
3710
dc3c8d3a 3711 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 3712 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3713 if (err) {
3714 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3715 __func__, err);
3716 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3717 goto out;
3718 }
3719
3720 hba->auto_bkops_enabled = false;
3721out:
3722 return err;
3723}
3724
3725/**
3726 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
3727 * @hba: per adapter instance
3728 *
3729 * After a device reset the device may toggle the BKOPS_EN flag
3730 * to default value. The s/w tracking variables should be updated
3731 * as well. Do this by forcing enable of auto bkops.
3732 */
3733static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3734{
3735 hba->auto_bkops_enabled = false;
3736 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3737 ufshcd_enable_auto_bkops(hba);
3738}
3739
3740static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3741{
5e86ae44 3742 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 3743 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3744}
3745
3746/**
57d104c1 3747 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 3748 * @hba: per-adapter instance
57d104c1 3749 * @status: bkops_status value
66ec6d59 3750 *
57d104c1
SJ		 3751 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3752 * flag in the device to permit background operations if the device
3753 * bkops_status is greater than or equal to "status" argument passed to
3754 * this function, disable otherwise.
3755 *
3756 * Returns 0 for success, non-zero in case of failure.
3757 *
3758 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3759 * to know whether auto bkops is enabled or disabled after this function
3760 * returns control to it.
66ec6d59 3761 */
57d104c1
SJ		 3762static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3763 enum bkops_status status)
66ec6d59
SRT		 3764{
3765 int err;
57d104c1 3766 u32 curr_status = 0;
66ec6d59 3767
57d104c1 3768 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 3769 if (err) {
3770 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3771 __func__, err);
3772 goto out;
57d104c1
SJ		 3773 } else if (curr_status > BKOPS_STATUS_MAX) {
3774 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3775 __func__, curr_status);
3776 err = -EINVAL;
3777 goto out;
66ec6d59
SRT		 3778 }
3779
57d104c1 3780 if (curr_status >= status)
66ec6d59 3781 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 3782 else
3783 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 3784out:
3785 return err;
3786}
3787
57d104c1
SJ		 3788/**
3789 * ufshcd_urgent_bkops - handle urgent bkops exception event
3790 * @hba: per-adapter instance
3791 *
3792 * Enable fBackgroundOpsEn flag in the device to permit background
3793 * operations.
3794 *
3795 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3796 * and negative error value for any other failure.
3797 */
3798static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3799{
afdfff59 3800 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 3801}
3802
66ec6d59
SRT		 3803static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3804{
5e86ae44 3805 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 3806 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3807}
3808
afdfff59
YG		 3809static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
3810{
3811 int err;
3812 u32 curr_status = 0;
3813
3814 if (hba->is_urgent_bkops_lvl_checked)
3815 goto enable_auto_bkops;
3816
3817 err = ufshcd_get_bkops_status(hba, &curr_status);
3818 if (err) {
3819 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3820 __func__, err);
3821 goto out;
3822 }
3823
3824 /*
3825 * We are seeing that some devices are raising the urgent bkops
3826 * exception events even when BKOPS status doesn't indicate performace
3827 * impacted or critical. Handle these device by determining their urgent
3828 * bkops status at runtime.
3829 */
3830 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
3831 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
3832 __func__, curr_status);
3833 /* update the current status as the urgent bkops level */
3834 hba->urgent_bkops_lvl = curr_status;
3835 hba->is_urgent_bkops_lvl_checked = true;
3836 }
3837
3838enable_auto_bkops:
3839 err = ufshcd_enable_auto_bkops(hba);
3840out:
3841 if (err < 0)
3842 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3843 __func__, err);
3844}
3845
66ec6d59
SRT		 3846/**
3847 * ufshcd_exception_event_handler - handle exceptions raised by device
3848 * @work: pointer to work data
3849 *
3850 * Read bExceptionEventStatus attribute from the device and handle the
3851 * exception event accordingly.
3852 */
3853static void ufshcd_exception_event_handler(struct work_struct *work)
3854{
3855 struct ufs_hba *hba;
3856 int err;
3857 u32 status = 0;
3858 hba = container_of(work, struct ufs_hba, eeh_work);
3859
62694735 3860 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 3861 err = ufshcd_get_ee_status(hba, &status);
3862 if (err) {
3863 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3864 __func__, err);
3865 goto out;
3866 }
3867
3868 status &= hba->ee_ctrl_mask;
afdfff59
YG		 3869
3870 if (status & MASK_EE_URGENT_BKOPS)
3871 ufshcd_bkops_exception_event_handler(hba);
3872
66ec6d59 3873out:
62694735 3874 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 3875 return;
3876}
3877
9a47ec7c
YG		 3878/* Complete requests that have door-bell cleared */
3879static void ufshcd_complete_requests(struct ufs_hba *hba)
3880{
3881 ufshcd_transfer_req_compl(hba);
3882 ufshcd_tmc_handler(hba);
3883}
3884
583fa62d
YG		 3885/**
3886 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
3887 * to recover from the DL NAC errors or not.
3888 * @hba: per-adapter instance
3889 *
3890 * Returns true if error handling is required, false otherwise
3891 */
3892static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
3893{
3894 unsigned long flags;
3895 bool err_handling = true;
3896
3897 spin_lock_irqsave(hba->host->host_lock, flags);
3898 /*
3899 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
3900 * device fatal error and/or DL NAC & REPLAY timeout errors.
3901 */
3902 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
3903 goto out;
3904
3905 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
3906 ((hba->saved_err & UIC_ERROR) &&
3907 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
3908 goto out;
3909
3910 if ((hba->saved_err & UIC_ERROR) &&
3911 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
3912 int err;
3913 /*
3914 * wait for 50ms to see if we can get any other errors or not.
3915 */
3916 spin_unlock_irqrestore(hba->host->host_lock, flags);
3917 msleep(50);
3918 spin_lock_irqsave(hba->host->host_lock, flags);
3919
3920 /*
3921 * now check if we have got any other severe errors other than
3922 * DL NAC error?
3923 */
3924 if ((hba->saved_err & INT_FATAL_ERRORS) ||
3925 ((hba->saved_err & UIC_ERROR) &&
3926 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
3927 goto out;
3928
3929 /*
3930 * As DL NAC is the only error received so far, send out NOP
3931 * command to confirm if link is still active or not.
3932 * - If we don't get any response then do error recovery.
3933 * - If we get response then clear the DL NAC error bit.
3934 */
3935
3936 spin_unlock_irqrestore(hba->host->host_lock, flags);
3937 err = ufshcd_verify_dev_init(hba);
3938 spin_lock_irqsave(hba->host->host_lock, flags);
3939
3940 if (err)
3941 goto out;
3942
3943 /* Link seems to be alive hence ignore the DL NAC errors */
3944 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
3945 hba->saved_err &= ~UIC_ERROR;
3946 /* clear NAC error */
3947 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
3948 if (!hba->saved_uic_err) {
3949 err_handling = false;
3950 goto out;
3951 }
3952 }
3953out:
3954 spin_unlock_irqrestore(hba->host->host_lock, flags);
3955 return err_handling;
3956}
3957
7a3e97b0 3958/**
e8e7f271
SRT		 3959 * ufshcd_err_handler - handle UFS errors that require s/w attention
3960 * @work: pointer to work structure
7a3e97b0 3961 */
e8e7f271 3962static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 3963{
3964 struct ufs_hba *hba;
e8e7f271
SRT		 3965 unsigned long flags;
3966 u32 err_xfer = 0;
3967 u32 err_tm = 0;
3968 int err = 0;
3969 int tag;
9a47ec7c 3970 bool needs_reset = false;
e8e7f271
SRT		 3971
3972 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 3973
62694735 3974 pm_runtime_get_sync(hba->dev);
1ab27c9c 3975 ufshcd_hold(hba, false);
e8e7f271
SRT		 3976
3977 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 3978 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 3979 goto out;
e8e7f271
SRT		 3980
3981 hba->ufshcd_state = UFSHCD_STATE_RESET;
3982 ufshcd_set_eh_in_progress(hba);
3983
3984 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 3985 ufshcd_complete_requests(hba);
583fa62d
YG		 3986
3987 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
3988 bool ret;
3989
3990 spin_unlock_irqrestore(hba->host->host_lock, flags);
3991 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
3992 ret = ufshcd_quirk_dl_nac_errors(hba);
3993 spin_lock_irqsave(hba->host->host_lock, flags);
3994 if (!ret)
3995 goto skip_err_handling;
3996 }
9a47ec7c
YG		 3997 if ((hba->saved_err & INT_FATAL_ERRORS) ||
3998 ((hba->saved_err & UIC_ERROR) &&
3999 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
4000 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
4001 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
4002 needs_reset = true;
e8e7f271 4003
9a47ec7c
YG		 4004 /*
4005 * if host reset is required then skip clearing the pending
4006 * transfers forcefully because they will automatically get
4007 * cleared after link startup.
4008 */
4009 if (needs_reset)
4010 goto skip_pending_xfer_clear;
4011
4012 /* release lock as clear command might sleep */
4013 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4014 /* Clear pending transfer requests */
9a47ec7c
YG		 4015 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
4016 if (ufshcd_clear_cmd(hba, tag)) {
4017 err_xfer = true;
4018 goto lock_skip_pending_xfer_clear;
4019 }
4020 }
e8e7f271
SRT		 4021
4022 /* Clear pending task management requests */
9a47ec7c
YG		 4023 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
4024 if (ufshcd_clear_tm_cmd(hba, tag)) {
4025 err_tm = true;
4026 goto lock_skip_pending_xfer_clear;
4027 }
4028 }
e8e7f271 4029
9a47ec7c 4030lock_skip_pending_xfer_clear:
e8e7f271 4031 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4032
9a47ec7c
YG		 4033 /* Complete the requests that are cleared by s/w */
4034 ufshcd_complete_requests(hba);
4035
4036 if (err_xfer || err_tm)
4037 needs_reset = true;
4038
4039skip_pending_xfer_clear:
e8e7f271 4040 /* Fatal errors need reset */
9a47ec7c
YG		 4041 if (needs_reset) {
4042 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
4043
4044 /*
4045 * ufshcd_reset_and_restore() does the link reinitialization
4046 * which will need atleast one empty doorbell slot to send the
4047 * device management commands (NOP and query commands).
4048 * If there is no slot empty at this moment then free up last
4049 * slot forcefully.
4050 */
4051 if (hba->outstanding_reqs == max_doorbells)
4052 __ufshcd_transfer_req_compl(hba,
4053 (1UL << (hba->nutrs - 1)));
4054
4055 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4056 err = ufshcd_reset_and_restore(hba);
9a47ec7c 4057 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 4058 if (err) {
4059 dev_err(hba->dev, "%s: reset and restore failed\n",
4060 __func__);
4061 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4062 }
4063 /*
4064 * Inform scsi mid-layer that we did reset and allow to handle
4065 * Unit Attention properly.
4066 */
4067 scsi_report_bus_reset(hba->host, 0);
4068 hba->saved_err = 0;
4069 hba->saved_uic_err = 0;
4070 }
9a47ec7c 4071
583fa62d 4072skip_err_handling:
9a47ec7c
YG		 4073 if (!needs_reset) {
4074 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4075 if (hba->saved_err || hba->saved_uic_err)
4076 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
4077 __func__, hba->saved_err, hba->saved_uic_err);
4078 }
4079
e8e7f271
SRT		 4080 ufshcd_clear_eh_in_progress(hba);
4081
4082out:
9a47ec7c 4083 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 4084 scsi_unblock_requests(hba->host);
1ab27c9c 4085 ufshcd_release(hba);
62694735 4086 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 4087}
4088
4089/**
e8e7f271
SRT		 4090 * ufshcd_update_uic_error - check and set fatal UIC error flags.
4091 * @hba: per-adapter instance
7a3e97b0 4092 */
e8e7f271 4093static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 4094{
4095 u32 reg;
4096
e8e7f271
SRT		 4097 /* PA_INIT_ERROR is fatal and needs UIC reset */
4098 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
4099 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
4100 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 4101 else if (hba->dev_quirks &
4102 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
4103 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
4104 hba->uic_error |=
4105 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
4106 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
4107 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
4108 }
e8e7f271
SRT		 4109
4110 /* UIC NL/TL/DME errors needs software retry */
4111 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
4112 if (reg)
4113 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
4114
4115 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
4116 if (reg)
4117 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
4118
4119 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
4120 if (reg)
4121 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
4122
4123 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
4124 __func__, hba->uic_error);
4125}
4126
4127/**
4128 * ufshcd_check_errors - Check for errors that need s/w attention
4129 * @hba: per-adapter instance
4130 */
4131static void ufshcd_check_errors(struct ufs_hba *hba)
4132{
4133 bool queue_eh_work = false;
4134
7a3e97b0 4135 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 4136 queue_eh_work = true;
7a3e97b0
SY		 4137
4138 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 4139 hba->uic_error = 0;
4140 ufshcd_update_uic_error(hba);
4141 if (hba->uic_error)
4142 queue_eh_work = true;
7a3e97b0 4143 }
e8e7f271
SRT		 4144
4145 if (queue_eh_work) {
9a47ec7c
YG		 4146 /*
4147 * update the transfer error masks to sticky bits, let's do this
4148 * irrespective of current ufshcd_state.
4149 */
4150 hba->saved_err |= hba->errors;
4151 hba->saved_uic_err |= hba->uic_error;
4152
e8e7f271
SRT		 4153 /* handle fatal errors only when link is functional */
4154 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
4155 /* block commands from scsi mid-layer */
4156 scsi_block_requests(hba->host);
4157
e8e7f271
SRT		 4158 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4159 schedule_work(&hba->eh_work);
4160 }
3441da7d 4161 }
e8e7f271
SRT		 4162 /*
4163 * if (!queue_eh_work) -
4164 * Other errors are either non-fatal where host recovers
4165 * itself without s/w intervention or errors that will be
4166 * handled by the SCSI core layer.
4167 */
7a3e97b0
SY		 4168}
4169
4170/**
4171 * ufshcd_tmc_handler - handle task management function completion
4172 * @hba: per adapter instance
4173 */
4174static void ufshcd_tmc_handler(struct ufs_hba *hba)
4175{
4176 u32 tm_doorbell;
4177
b873a275 4178 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 4179 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 4180 wake_up(&hba->tm_wq);
7a3e97b0
SY		 4181}
4182
4183/**
4184 * ufshcd_sl_intr - Interrupt service routine
4185 * @hba: per adapter instance
4186 * @intr_status: contains interrupts generated by the controller
4187 */
4188static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
4189{
4190 hba->errors = UFSHCD_ERROR_MASK & intr_status;
4191 if (hba->errors)
e8e7f271 4192 ufshcd_check_errors(hba);
7a3e97b0 4193
53b3d9c3
SJ		 4194 if (intr_status & UFSHCD_UIC_MASK)
4195 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 4196
4197 if (intr_status & UTP_TASK_REQ_COMPL)
4198 ufshcd_tmc_handler(hba);
4199
4200 if (intr_status & UTP_TRANSFER_REQ_COMPL)
4201 ufshcd_transfer_req_compl(hba);
4202}
4203
4204/**
4205 * ufshcd_intr - Main interrupt service routine
4206 * @irq: irq number
4207 * @__hba: pointer to adapter instance
4208 *
4209 * Returns IRQ_HANDLED - If interrupt is valid
4210 * IRQ_NONE - If invalid interrupt
4211 */
4212static irqreturn_t ufshcd_intr(int irq, void *__hba)
4213{
d75f7fe4 4214 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 4215 irqreturn_t retval = IRQ_NONE;
4216 struct ufs_hba *hba = __hba;
4217
4218 spin_lock(hba->host->host_lock);
b873a275 4219 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4220 enabled_intr_status =
4221 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 4222
d75f7fe4 4223 if (intr_status)
261ea452 4224 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 4225
4226 if (enabled_intr_status) {
4227 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 4228 retval = IRQ_HANDLED;
4229 }
4230 spin_unlock(hba->host->host_lock);
4231 return retval;
4232}
4233
e2933132
SRT		 4234static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
4235{
4236 int err = 0;
4237 u32 mask = 1 << tag;
4238 unsigned long flags;
4239
4240 if (!test_bit(tag, &hba->outstanding_tasks))
4241 goto out;
4242
4243 spin_lock_irqsave(hba->host->host_lock, flags);
4244 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
4245 spin_unlock_irqrestore(hba->host->host_lock, flags);
4246
4247 /* poll for max. 1 sec to clear door bell register by h/w */
4248 err = ufshcd_wait_for_register(hba,
4249 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 4250 mask, 0, 1000, 1000, true);
e2933132
SRT		 4251out:
4252 return err;
4253}
4254
7a3e97b0
SY		 4255/**
4256 * ufshcd_issue_tm_cmd - issues task management commands to controller
4257 * @hba: per adapter instance
e2933132
SRT		 4258 * @lun_id: LUN ID to which TM command is sent
4259 * @task_id: task ID to which the TM command is applicable
4260 * @tm_function: task management function opcode
4261 * @tm_response: task management service response return value
7a3e97b0 4262 *
e2933132 4263 * Returns non-zero value on error, zero on success.
7a3e97b0 4264 */
e2933132
SRT		 4265static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
4266 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 4267{
4268 struct utp_task_req_desc *task_req_descp;
4269 struct utp_upiu_task_req *task_req_upiup;
4270 struct Scsi_Host *host;
4271 unsigned long flags;
e2933132 4272 int free_slot;
7a3e97b0 4273 int err;
e2933132 4274 int task_tag;
7a3e97b0
SY		 4275
4276 host = hba->host;
4277
e2933132
SRT		 4278 /*
4279 * Get free slot, sleep if slots are unavailable.
4280 * Even though we use wait_event() which sleeps indefinitely,
4281 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
4282 */
4283 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 4284 ufshcd_hold(hba, false);
7a3e97b0 4285
e2933132 4286 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 4287 task_req_descp = hba->utmrdl_base_addr;
4288 task_req_descp += free_slot;
4289
4290 /* Configure task request descriptor */
4291 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
4292 task_req_descp->header.dword_2 =
4293 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
4294
4295 /* Configure task request UPIU */
4296 task_req_upiup =
4297 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 4298 task_tag = hba->nutrs + free_slot;
7a3e97b0 4299 task_req_upiup->header.dword_0 =
5a0b0cb9 4300 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 4301 lun_id, task_tag);
7a3e97b0 4302 task_req_upiup->header.dword_1 =
5a0b0cb9 4303 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 4304 /*
4305 * The host shall provide the same value for LUN field in the basic
4306 * header and for Input Parameter.
4307 */
e2933132
SRT		 4308 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
4309 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0
SY		 4310
4311 /* send command to the controller */
4312 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 4313
4314 /* Make sure descriptors are ready before ringing the task doorbell */
4315 wmb();
4316
b873a275 4317 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0
SY		 4318
4319 spin_unlock_irqrestore(host->host_lock, flags);
4320
4321 /* wait until the task management command is completed */
e2933132
SRT		 4322 err = wait_event_timeout(hba->tm_wq,
4323 test_bit(free_slot, &hba->tm_condition),
4324 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 4325 if (!err) {
e2933132
SRT		 4326 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
4327 __func__, tm_function);
4328 if (ufshcd_clear_tm_cmd(hba, free_slot))
4329 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
4330 __func__, free_slot);
4331 err = -ETIMEDOUT;
4332 } else {
4333 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 4334 }
e2933132 4335
7a3e97b0 4336 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 4337 ufshcd_put_tm_slot(hba, free_slot);
4338 wake_up(&hba->tm_tag_wq);
4339
1ab27c9c 4340 ufshcd_release(hba);
7a3e97b0
SY		 4341 return err;
4342}
4343
4344/**
3441da7d
SRT		 4345 * ufshcd_eh_device_reset_handler - device reset handler registered to
4346 * scsi layer.
7a3e97b0
SY		 4347 * @cmd: SCSI command pointer
4348 *
4349 * Returns SUCCESS/FAILED
4350 */
3441da7d 4351static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 4352{
4353 struct Scsi_Host *host;
4354 struct ufs_hba *hba;
4355 unsigned int tag;
4356 u32 pos;
4357 int err;
e2933132
SRT		 4358 u8 resp = 0xF;
4359 struct ufshcd_lrb *lrbp;
3441da7d 4360 unsigned long flags;
7a3e97b0
SY		 4361
4362 host = cmd->device->host;
4363 hba = shost_priv(host);
4364 tag = cmd->request->tag;
4365
e2933132
SRT		 4366 lrbp = &hba->lrb[tag];
4367 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
4368 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 4369 if (!err)
4370 err = resp;
7a3e97b0 4371 goto out;
e2933132 4372 }
7a3e97b0 4373
3441da7d
SRT		 4374 /* clear the commands that were pending for corresponding LUN */
4375 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
4376 if (hba->lrb[pos].lun == lrbp->lun) {
4377 err = ufshcd_clear_cmd(hba, pos);
4378 if (err)
4379 break;
7a3e97b0 4380 }
3441da7d
SRT		 4381 }
4382 spin_lock_irqsave(host->host_lock, flags);
4383 ufshcd_transfer_req_compl(hba);
4384 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 4385out:
3441da7d
SRT		 4386 if (!err) {
4387 err = SUCCESS;
4388 } else {
4389 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4390 err = FAILED;
4391 }
7a3e97b0
SY		 4392 return err;
4393}
4394
7a3e97b0
SY		 4395/**
4396 * ufshcd_abort - abort a specific command
4397 * @cmd: SCSI command pointer
4398 *
f20810d8
SRT		 4399 * Abort the pending command in device by sending UFS_ABORT_TASK task management
4400 * command, and in host controller by clearing the door-bell register. There can
4401 * be race between controller sending the command to the device while abort is
4402 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
4403 * really issued and then try to abort it.
4404 *
7a3e97b0
SY		 4405 * Returns SUCCESS/FAILED
4406 */
4407static int ufshcd_abort(struct scsi_cmnd *cmd)
4408{
4409 struct Scsi_Host *host;
4410 struct ufs_hba *hba;
4411 unsigned long flags;
4412 unsigned int tag;
f20810d8
SRT		 4413 int err = 0;
4414 int poll_cnt;
e2933132
SRT		 4415 u8 resp = 0xF;
4416 struct ufshcd_lrb *lrbp;
e9d501b1 4417 u32 reg;
7a3e97b0
SY		 4418
4419 host = cmd->device->host;
4420 hba = shost_priv(host);
4421 tag = cmd->request->tag;
14497328
YG		 4422 if (!ufshcd_valid_tag(hba, tag)) {
4423 dev_err(hba->dev,
4424 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
4425 __func__, tag, cmd, cmd->request);
4426 BUG();
4427 }
7a3e97b0 4428
1ab27c9c 4429 ufshcd_hold(hba, false);
14497328 4430 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 4431 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 4432 if (!(test_bit(tag, &hba->outstanding_reqs))) {
4433 dev_err(hba->dev,
4434 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
4435 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 4436 goto out;
14497328 4437 }
7a3e97b0 4438
e9d501b1
DR		 4439 if (!(reg & (1 << tag))) {
4440 dev_err(hba->dev,
4441 "%s: cmd was completed, but without a notifying intr, tag = %d",
4442 __func__, tag);
4443 }
4444
f20810d8
SRT		 4445 lrbp = &hba->lrb[tag];
4446 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
4447 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4448 UFS_QUERY_TASK, &resp);
4449 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
4450 /* cmd pending in the device */
4451 break;
4452 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4453 /*
4454 * cmd not pending in the device, check if it is
4455 * in transition.
4456 */
4457 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4458 if (reg & (1 << tag)) {
4459 /* sleep for max. 200us to stabilize */
4460 usleep_range(100, 200);
4461 continue;
4462 }
4463 /* command completed already */
4464 goto out;
4465 } else {
4466 if (!err)
4467 err = resp; /* service response error */
4468 goto out;
4469 }
4470 }
4471
4472 if (!poll_cnt) {
4473 err = -EBUSY;
7a3e97b0
SY		 4474 goto out;
4475 }
7a3e97b0 4476
e2933132
SRT		 4477 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
4478 UFS_ABORT_TASK, &resp);
4479 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 4480 if (!err)
4481 err = resp; /* service response error */
7a3e97b0 4482 goto out;
e2933132 4483 }
7a3e97b0 4484
f20810d8
SRT		 4485 err = ufshcd_clear_cmd(hba, tag);
4486 if (err)
4487 goto out;
4488
7a3e97b0
SY		 4489 scsi_dma_unmap(cmd);
4490
4491 spin_lock_irqsave(host->host_lock, flags);
a48353f6 4492 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 4493 hba->lrb[tag].cmd = NULL;
4494 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 4495
4496 clear_bit_unlock(tag, &hba->lrb_in_use);
4497 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 4498
7a3e97b0 4499out:
f20810d8
SRT		 4500 if (!err) {
4501 err = SUCCESS;
4502 } else {
4503 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
4504 err = FAILED;
4505 }
4506
1ab27c9c
ST		 4507 /*
4508 * This ufshcd_release() corresponds to the original scsi cmd that got
4509 * aborted here (as we won't get any IRQ for it).
4510 */
4511 ufshcd_release(hba);
7a3e97b0
SY		 4512 return err;
4513}
4514
3441da7d
SRT		 4515/**
4516 * ufshcd_host_reset_and_restore - reset and restore host controller
4517 * @hba: per-adapter instance
4518 *
4519 * Note that host controller reset may issue DME_RESET to
4520 * local and remote (device) Uni-Pro stack and the attributes
4521 * are reset to default state.
4522 *
4523 * Returns zero on success, non-zero on failure
4524 */
4525static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
4526{
4527 int err;
3441da7d
SRT		 4528 unsigned long flags;
4529
4530 /* Reset the host controller */
4531 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 4532 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 4533 spin_unlock_irqrestore(hba->host->host_lock, flags);
4534
4535 err = ufshcd_hba_enable(hba);
4536 if (err)
4537 goto out;
4538
4539 /* Establish the link again and restore the device */
1d337ec2
SRT		 4540 err = ufshcd_probe_hba(hba);
4541
4542 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 4543 err = -EIO;
4544out:
4545 if (err)
4546 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
4547
4548 return err;
4549}
4550
4551/**
4552 * ufshcd_reset_and_restore - reset and re-initialize host/device
4553 * @hba: per-adapter instance
4554 *
4555 * Reset and recover device, host and re-establish link. This
4556 * is helpful to recover the communication in fatal error conditions.
4557 *
4558 * Returns zero on success, non-zero on failure
4559 */
4560static int ufshcd_reset_and_restore(struct ufs_hba *hba)
4561{
4562 int err = 0;
4563 unsigned long flags;
1d337ec2 4564 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 4565
1d337ec2
SRT		 4566 do {
4567 err = ufshcd_host_reset_and_restore(hba);
4568 } while (err && --retries);
3441da7d
SRT		 4569
4570 /*
4571 * After reset the door-bell might be cleared, complete
4572 * outstanding requests in s/w here.
4573 */
4574 spin_lock_irqsave(hba->host->host_lock, flags);
4575 ufshcd_transfer_req_compl(hba);
4576 ufshcd_tmc_handler(hba);
4577 spin_unlock_irqrestore(hba->host->host_lock, flags);
4578
4579 return err;
4580}
4581
4582/**
4583 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
4584 * @cmd - SCSI command pointer
4585 *
4586 * Returns SUCCESS/FAILED
4587 */
4588static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
4589{
4590 int err;
4591 unsigned long flags;
4592 struct ufs_hba *hba;
4593
4594 hba = shost_priv(cmd->device->host);
4595
1ab27c9c 4596 ufshcd_hold(hba, false);
3441da7d
SRT		 4597 /*
4598 * Check if there is any race with fatal error handling.
4599 * If so, wait for it to complete. Even though fatal error
4600 * handling does reset and restore in some cases, don't assume
4601 * anything out of it. We are just avoiding race here.
4602 */
4603 do {
4604 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 4605 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 4606 hba->ufshcd_state == UFSHCD_STATE_RESET))
4607 break;
4608 spin_unlock_irqrestore(hba->host->host_lock, flags);
4609 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 4610 flush_work(&hba->eh_work);
3441da7d
SRT		 4611 } while (1);
4612
4613 hba->ufshcd_state = UFSHCD_STATE_RESET;
4614 ufshcd_set_eh_in_progress(hba);
4615 spin_unlock_irqrestore(hba->host->host_lock, flags);
4616
4617 err = ufshcd_reset_and_restore(hba);
4618
4619 spin_lock_irqsave(hba->host->host_lock, flags);
4620 if (!err) {
4621 err = SUCCESS;
4622 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
4623 } else {
4624 err = FAILED;
4625 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4626 }
4627 ufshcd_clear_eh_in_progress(hba);
4628 spin_unlock_irqrestore(hba->host->host_lock, flags);
4629
1ab27c9c 4630 ufshcd_release(hba);
3441da7d
SRT		 4631 return err;
4632}
4633
3a4bf06d
YG		 4634/**
4635 * ufshcd_get_max_icc_level - calculate the ICC level
4636 * @sup_curr_uA: max. current supported by the regulator
4637 * @start_scan: row at the desc table to start scan from
4638 * @buff: power descriptor buffer
4639 *
4640 * Returns calculated max ICC level for specific regulator
4641 */
4642static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
4643{
4644 int i;
4645 int curr_uA;
4646 u16 data;
4647 u16 unit;
4648
4649 for (i = start_scan; i >= 0; i--) {
4650 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
4651 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
4652 ATTR_ICC_LVL_UNIT_OFFSET;
4653 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
4654 switch (unit) {
4655 case UFSHCD_NANO_AMP:
4656 curr_uA = curr_uA / 1000;
4657 break;
4658 case UFSHCD_MILI_AMP:
4659 curr_uA = curr_uA * 1000;
4660 break;
4661 case UFSHCD_AMP:
4662 curr_uA = curr_uA * 1000 * 1000;
4663 break;
4664 case UFSHCD_MICRO_AMP:
4665 default:
4666 break;
4667 }
4668 if (sup_curr_uA >= curr_uA)
4669 break;
4670 }
4671 if (i < 0) {
4672 i = 0;
4673 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
4674 }
4675
4676 return (u32)i;
4677}
4678
4679/**
4680 * ufshcd_calc_icc_level - calculate the max ICC level
4681 * In case regulators are not initialized we'll return 0
4682 * @hba: per-adapter instance
4683 * @desc_buf: power descriptor buffer to extract ICC levels from.
4684 * @len: length of desc_buff
4685 *
4686 * Returns calculated ICC level
4687 */
4688static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
4689 u8 *desc_buf, int len)
4690{
4691 u32 icc_level = 0;
4692
4693 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
4694 !hba->vreg_info.vccq2) {
4695 dev_err(hba->dev,
4696 "%s: Regulator capability was not set, actvIccLevel=%d",
4697 __func__, icc_level);
4698 goto out;
4699 }
4700
4701 if (hba->vreg_info.vcc)
4702 icc_level = ufshcd_get_max_icc_level(
4703 hba->vreg_info.vcc->max_uA,
4704 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
4705 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
4706
4707 if (hba->vreg_info.vccq)
4708 icc_level = ufshcd_get_max_icc_level(
4709 hba->vreg_info.vccq->max_uA,
4710 icc_level,
4711 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
4712
4713 if (hba->vreg_info.vccq2)
4714 icc_level = ufshcd_get_max_icc_level(
4715 hba->vreg_info.vccq2->max_uA,
4716 icc_level,
4717 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
4718out:
4719 return icc_level;
4720}
4721
4722static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4723{
4724 int ret;
4725 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4726 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4727
4728 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4729 if (ret) {
4730 dev_err(hba->dev,
4731 "%s: Failed reading power descriptor.len = %d ret = %d",
4732 __func__, buff_len, ret);
4733 return;
4734 }
4735
4736 hba->init_prefetch_data.icc_level =
4737 ufshcd_find_max_sup_active_icc_level(hba,
4738 desc_buf, buff_len);
4739 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4740 __func__, hba->init_prefetch_data.icc_level);
4741
5e86ae44
YG		 4742 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4743 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
4744 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 4745
4746 if (ret)
4747 dev_err(hba->dev,
4748 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4749 __func__, hba->init_prefetch_data.icc_level , ret);
4750
4751}
4752
2a8fa600
SJ		 4753/**
4754 * ufshcd_scsi_add_wlus - Adds required W-LUs
4755 * @hba: per-adapter instance
4756 *
4757 * UFS device specification requires the UFS devices to support 4 well known
4758 * logical units:
4759 * "REPORT_LUNS" (address: 01h)
4760 * "UFS Device" (address: 50h)
4761 * "RPMB" (address: 44h)
4762 * "BOOT" (address: 30h)
4763 * UFS device's power management needs to be controlled by "POWER CONDITION"
4764 * field of SSU (START STOP UNIT) command. But this "power condition" field
4765 * will take effect only when its sent to "UFS device" well known logical unit
4766 * hence we require the scsi_device instance to represent this logical unit in
4767 * order for the UFS host driver to send the SSU command for power management.
4768
4769 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4770 * Block) LU so user space process can control this LU. User space may also
4771 * want to have access to BOOT LU.
4772
4773 * This function adds scsi device instances for each of all well known LUs
4774 * (except "REPORT LUNS" LU).
4775 *
4776 * Returns zero on success (all required W-LUs are added successfully),
4777 * non-zero error value on failure (if failed to add any of the required W-LU).
4778 */
4779static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4780{
4781 int ret = 0;
7c48bfd0
AM		 4782 struct scsi_device *sdev_rpmb;
4783 struct scsi_device *sdev_boot;
2a8fa600
SJ		 4784
4785 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4786 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4787 if (IS_ERR(hba->sdev_ufs_device)) {
4788 ret = PTR_ERR(hba->sdev_ufs_device);
4789 hba->sdev_ufs_device = NULL;
4790 goto out;
4791 }
7c48bfd0 4792 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 4793
7c48bfd0 4794 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4795 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 4796 if (IS_ERR(sdev_boot)) {
4797 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 4798 goto remove_sdev_ufs_device;
4799 }
7c48bfd0 4800 scsi_device_put(sdev_boot);
2a8fa600 4801
7c48bfd0 4802 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 4803 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 4804 if (IS_ERR(sdev_rpmb)) {
4805 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 4806 goto remove_sdev_boot;
4807 }
7c48bfd0 4808 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 4809 goto out;
4810
4811remove_sdev_boot:
7c48bfd0 4812 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 4813remove_sdev_ufs_device:
4814 scsi_remove_device(hba->sdev_ufs_device);
4815out:
4816 return ret;
4817}
4818
c58ab7aa
YG		 4819static int ufs_get_device_info(struct ufs_hba *hba,
4820 struct ufs_device_info *card_data)
4821{
4822 int err;
4823 u8 model_index;
4824 u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
4825 u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
4826
4827 err = ufshcd_read_device_desc(hba, desc_buf,
4828 QUERY_DESC_DEVICE_MAX_SIZE);
4829 if (err) {
4830 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
4831 __func__, err);
4832 goto out;
4833 }
4834
4835 /*
4836 * getting vendor (manufacturerID) and Bank Index in big endian
4837 * format
4838 */
4839 card_data->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
4840 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
4841
4842 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
4843
4844 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
4845 QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
4846 if (err) {
4847 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
4848 __func__, err);
4849 goto out;
4850 }
4851
4852 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
4853 strlcpy(card_data->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
4854 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
4855 MAX_MODEL_LEN));
4856
4857 /* Null terminate the model string */
4858 card_data->model[MAX_MODEL_LEN] = '\0';
4859
4860out:
4861 return err;
4862}
4863
4864void ufs_advertise_fixup_device(struct ufs_hba *hba)
4865{
4866 int err;
4867 struct ufs_dev_fix *f;
4868 struct ufs_device_info card_data;
4869
4870 card_data.wmanufacturerid = 0;
4871
4872 err = ufs_get_device_info(hba, &card_data);
4873 if (err) {
4874 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
4875 __func__, err);
4876 return;
4877 }
4878
4879 for (f = ufs_fixups; f->quirk; f++) {
4880 if (((f->card.wmanufacturerid == card_data.wmanufacturerid) ||
4881 (f->card.wmanufacturerid == UFS_ANY_VENDOR)) &&
4882 (STR_PRFX_EQUAL(f->card.model, card_data.model) ||
4883 !strcmp(f->card.model, UFS_ANY_MODEL)))
4884 hba->dev_quirks |= f->quirk;
4885 }
4886}
4887
37113106
YG		 4888/**
4889 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
4890 * @hba: per-adapter instance
4891 *
4892 * PA_TActivate parameter can be tuned manually if UniPro version is less than
4893 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
4894 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
4895 * the hibern8 exit latency.
4896 *
4897 * Returns zero on success, non-zero error value on failure.
4898 */
4899static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
4900{
4901 int ret = 0;
4902 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
4903
4904 ret = ufshcd_dme_peer_get(hba,
4905 UIC_ARG_MIB_SEL(
4906 RX_MIN_ACTIVATETIME_CAPABILITY,
4907 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
4908 &peer_rx_min_activatetime);
4909 if (ret)
4910 goto out;
4911
4912 /* make sure proper unit conversion is applied */
4913 tuned_pa_tactivate =
4914 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
4915 / PA_TACTIVATE_TIME_UNIT_US);
4916 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
4917 tuned_pa_tactivate);
4918
4919out:
4920 return ret;
4921}
4922
4923/**
4924 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
4925 * @hba: per-adapter instance
4926 *
4927 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
4928 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
4929 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
4930 * This optimal value can help reduce the hibern8 exit latency.
4931 *
4932 * Returns zero on success, non-zero error value on failure.
4933 */
4934static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
4935{
4936 int ret = 0;
4937 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
4938 u32 max_hibern8_time, tuned_pa_hibern8time;
4939
4940 ret = ufshcd_dme_get(hba,
4941 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
4942 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
4943 &local_tx_hibern8_time_cap);
4944 if (ret)
4945 goto out;
4946
4947 ret = ufshcd_dme_peer_get(hba,
4948 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
4949 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
4950 &peer_rx_hibern8_time_cap);
4951 if (ret)
4952 goto out;
4953
4954 max_hibern8_time = max(local_tx_hibern8_time_cap,
4955 peer_rx_hibern8_time_cap);
4956 /* make sure proper unit conversion is applied */
4957 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
4958 / PA_HIBERN8_TIME_UNIT_US);
4959 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
4960 tuned_pa_hibern8time);
4961out:
4962 return ret;
4963}
4964
4965static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
4966{
4967 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
4968 ufshcd_tune_pa_tactivate(hba);
4969 ufshcd_tune_pa_hibern8time(hba);
4970 }
4971
4972 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
4973 /* set 1ms timeout for PA_TACTIVATE */
4974 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
4975}
4976
6ccf44fe 4977/**
1d337ec2
SRT		 4978 * ufshcd_probe_hba - probe hba to detect device and initialize
4979 * @hba: per-adapter instance
4980 *
4981 * Execute link-startup and verify device initialization
6ccf44fe 4982 */
1d337ec2 4983static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 4984{
6ccf44fe
SJ		 4985 int ret;
4986
4987 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 4988 if (ret)
4989 goto out;
4990
5064636c
YG		 4991 ufshcd_init_pwr_info(hba);
4992
afdfff59
YG		 4993 /* set the default level for urgent bkops */
4994 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
4995 hba->is_urgent_bkops_lvl_checked = false;
4996
57d104c1
SJ		 4997 /* UniPro link is active now */
4998 ufshcd_set_link_active(hba);
d3e89bac 4999
5a0b0cb9
SRT		 5000 ret = ufshcd_verify_dev_init(hba);
5001 if (ret)
5002 goto out;
68078d5c
DR		 5003
5004 ret = ufshcd_complete_dev_init(hba);
5005 if (ret)
5006 goto out;
5a0b0cb9 5007
c58ab7aa 5008 ufs_advertise_fixup_device(hba);
37113106 5009 ufshcd_tune_unipro_params(hba);
60f01870
YG		 5010
5011 ret = ufshcd_set_vccq_rail_unused(hba,
5012 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
5013 if (ret)
5014 goto out;
5015
57d104c1
SJ		 5016 /* UFS device is also active now */
5017 ufshcd_set_ufs_dev_active(hba);
66ec6d59 5018 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 5019 hba->wlun_dev_clr_ua = true;
5020
7eb584db
DR		 5021 if (ufshcd_get_max_pwr_mode(hba)) {
5022 dev_err(hba->dev,
5023 "%s: Failed getting max supported power mode\n",
5024 __func__);
5025 } else {
5026 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
5027 if (ret)
5028 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
5029 __func__, ret);
5030 }
57d104c1 5031
53c12d0e
YG		 5032 /* set the state as operational after switching to desired gear */
5033 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 5034 /*
5035 * If we are in error handling context or in power management callbacks
5036 * context, no need to scan the host
5037 */
5038 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5039 bool flag;
5040
5041 /* clear any previous UFS device information */
5042 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 5043 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
5044 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 5045 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 5046
3a4bf06d
YG		 5047 if (!hba->is_init_prefetch)
5048 ufshcd_init_icc_levels(hba);
5049
2a8fa600
SJ		 5050 /* Add required well known logical units to scsi mid layer */
5051 if (ufshcd_scsi_add_wlus(hba))
5052 goto out;
5053
3441da7d
SRT		 5054 scsi_scan_host(hba->host);
5055 pm_runtime_put_sync(hba->dev);
5056 }
3a4bf06d
YG		 5057
5058 if (!hba->is_init_prefetch)
5059 hba->is_init_prefetch = true;
5060
856b3483
ST		 5061 /* Resume devfreq after UFS device is detected */
5062 if (ufshcd_is_clkscaling_enabled(hba))
5063 devfreq_resume_device(hba->devfreq);
5064
5a0b0cb9 5065out:
1d337ec2
SRT		 5066 /*
5067 * If we failed to initialize the device or the device is not
5068 * present, turn off the power/clocks etc.
5069 */
57d104c1
SJ		 5070 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
5071 pm_runtime_put_sync(hba->dev);
1d337ec2 5072 ufshcd_hba_exit(hba);
57d104c1 5073 }
1d337ec2
SRT		 5074
5075 return ret;
5076}
5077
5078/**
5079 * ufshcd_async_scan - asynchronous execution for probing hba
5080 * @data: data pointer to pass to this function
5081 * @cookie: cookie data
5082 */
5083static void ufshcd_async_scan(void *data, async_cookie_t cookie)
5084{
5085 struct ufs_hba *hba = (struct ufs_hba *)data;
5086
5087 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 5088}
5089
f550c65b
YG		 5090static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
5091{
5092 unsigned long flags;
5093 struct Scsi_Host *host;
5094 struct ufs_hba *hba;
5095 int index;
5096 bool found = false;
5097
5098 if (!scmd || !scmd->device || !scmd->device->host)
5099 return BLK_EH_NOT_HANDLED;
5100
5101 host = scmd->device->host;
5102 hba = shost_priv(host);
5103 if (!hba)
5104 return BLK_EH_NOT_HANDLED;
5105
5106 spin_lock_irqsave(host->host_lock, flags);
5107
5108 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
5109 if (hba->lrb[index].cmd == scmd) {
5110 found = true;
5111 break;
5112 }
5113 }
5114
5115 spin_unlock_irqrestore(host->host_lock, flags);
5116
5117 /*
5118 * Bypass SCSI error handling and reset the block layer timer if this
5119 * SCSI command was not actually dispatched to UFS driver, otherwise
5120 * let SCSI layer handle the error as usual.
5121 */
5122 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
5123}
5124
7a3e97b0
SY		 5125static struct scsi_host_template ufshcd_driver_template = {
5126 .module = THIS_MODULE,
5127 .name = UFSHCD,
5128 .proc_name = UFSHCD,
5129 .queuecommand = ufshcd_queuecommand,
5130 .slave_alloc = ufshcd_slave_alloc,
eeda4749 5131 .slave_configure = ufshcd_slave_configure,
7a3e97b0 5132 .slave_destroy = ufshcd_slave_destroy,
4264fd61 5133 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 5134 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 5135 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
5136 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 5137 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 5138 .this_id = -1,
5139 .sg_tablesize = SG_ALL,
5140 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
5141 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 5142 .max_host_blocked = 1,
c40ecc12 5143 .track_queue_depth = 1,
7a3e97b0
SY		 5144};
5145
57d104c1
SJ		 5146static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
5147 int ua)
5148{
7b16a07c 5149 int ret;
57d104c1 5150
7b16a07c
BA		 5151 if (!vreg)
5152 return 0;
57d104c1 5153
7b16a07c
BA		 5154 ret = regulator_set_load(vreg->reg, ua);
5155 if (ret < 0) {
5156 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
5157 __func__, vreg->name, ua, ret);
57d104c1
SJ		 5158 }
5159
5160 return ret;
5161}
5162
5163static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
5164 struct ufs_vreg *vreg)
5165{
60f01870
YG		 5166 if (!vreg)
5167 return 0;
5168 else if (vreg->unused)
5169 return 0;
5170 else
5171 return ufshcd_config_vreg_load(hba->dev, vreg,
5172 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 5173}
5174
5175static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
5176 struct ufs_vreg *vreg)
5177{
60f01870
YG		 5178 if (!vreg)
5179 return 0;
5180 else if (vreg->unused)
5181 return 0;
5182 else
5183 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 5184}
5185
aa497613
SRT		 5186static int ufshcd_config_vreg(struct device *dev,
5187 struct ufs_vreg *vreg, bool on)
5188{
5189 int ret = 0;
5190 struct regulator *reg = vreg->reg;
5191 const char *name = vreg->name;
5192 int min_uV, uA_load;
5193
5194 BUG_ON(!vreg);
5195
5196 if (regulator_count_voltages(reg) > 0) {
5197 min_uV = on ? vreg->min_uV : 0;
5198 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
5199 if (ret) {
5200 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
5201 __func__, name, ret);
5202 goto out;
5203 }
5204
5205 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 5206 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
5207 if (ret)
aa497613 5208 goto out;
aa497613
SRT		 5209 }
5210out:
5211 return ret;
5212}
5213
5214static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
5215{
5216 int ret = 0;
5217
60f01870
YG		 5218 if (!vreg)
5219 goto out;
5220 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 5221 goto out;
5222
5223 ret = ufshcd_config_vreg(dev, vreg, true);
5224 if (!ret)
5225 ret = regulator_enable(vreg->reg);
5226
5227 if (!ret)
5228 vreg->enabled = true;
5229 else
5230 dev_err(dev, "%s: %s enable failed, err=%d\n",
5231 __func__, vreg->name, ret);
5232out:
5233 return ret;
5234}
5235
5236static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
5237{
5238 int ret = 0;
5239
60f01870
YG		 5240 if (!vreg)
5241 goto out;
5242 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 5243 goto out;
5244
5245 ret = regulator_disable(vreg->reg);
5246
5247 if (!ret) {
5248 /* ignore errors on applying disable config */
5249 ufshcd_config_vreg(dev, vreg, false);
5250 vreg->enabled = false;
5251 } else {
5252 dev_err(dev, "%s: %s disable failed, err=%d\n",
5253 __func__, vreg->name, ret);
5254 }
5255out:
5256 return ret;
5257}
5258
5259static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
5260{
5261 int ret = 0;
5262 struct device *dev = hba->dev;
5263 struct ufs_vreg_info *info = &hba->vreg_info;
5264
5265 if (!info)
5266 goto out;
5267
5268 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
5269 if (ret)
5270 goto out;
5271
5272 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
5273 if (ret)
5274 goto out;
5275
5276 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
5277 if (ret)
5278 goto out;
5279
5280out:
5281 if (ret) {
5282 ufshcd_toggle_vreg(dev, info->vccq2, false);
5283 ufshcd_toggle_vreg(dev, info->vccq, false);
5284 ufshcd_toggle_vreg(dev, info->vcc, false);
5285 }
5286 return ret;
5287}
5288
6a771a65
RS		 5289static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
5290{
5291 struct ufs_vreg_info *info = &hba->vreg_info;
5292
5293 if (info)
5294 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
5295
5296 return 0;
5297}
5298
aa497613
SRT		 5299static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
5300{
5301 int ret = 0;
5302
5303 if (!vreg)
5304 goto out;
5305
5306 vreg->reg = devm_regulator_get(dev, vreg->name);
5307 if (IS_ERR(vreg->reg)) {
5308 ret = PTR_ERR(vreg->reg);
5309 dev_err(dev, "%s: %s get failed, err=%d\n",
5310 __func__, vreg->name, ret);
5311 }
5312out:
5313 return ret;
5314}
5315
5316static int ufshcd_init_vreg(struct ufs_hba *hba)
5317{
5318 int ret = 0;
5319 struct device *dev = hba->dev;
5320 struct ufs_vreg_info *info = &hba->vreg_info;
5321
5322 if (!info)
5323 goto out;
5324
5325 ret = ufshcd_get_vreg(dev, info->vcc);
5326 if (ret)
5327 goto out;
5328
5329 ret = ufshcd_get_vreg(dev, info->vccq);
5330 if (ret)
5331 goto out;
5332
5333 ret = ufshcd_get_vreg(dev, info->vccq2);
5334out:
5335 return ret;
5336}
5337
6a771a65
RS		 5338static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
5339{
5340 struct ufs_vreg_info *info = &hba->vreg_info;
5341
5342 if (info)
5343 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
5344
5345 return 0;
5346}
5347
60f01870
YG		 5348static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
5349{
5350 int ret = 0;
5351 struct ufs_vreg_info *info = &hba->vreg_info;
5352
5353 if (!info)
5354 goto out;
5355 else if (!info->vccq)
5356 goto out;
5357
5358 if (unused) {
5359 /* shut off the rail here */
5360 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
5361 /*
5362 * Mark this rail as no longer used, so it doesn't get enabled
5363 * later by mistake
5364 */
5365 if (!ret)
5366 info->vccq->unused = true;
5367 } else {
5368 /*
5369 * rail should have been already enabled hence just make sure
5370 * that unused flag is cleared.
5371 */
5372 info->vccq->unused = false;
5373 }
5374out:
5375 return ret;
5376}
5377
57d104c1
SJ		 5378static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
5379 bool skip_ref_clk)
c6e79dac
SRT		 5380{
5381 int ret = 0;
5382 struct ufs_clk_info *clki;
5383 struct list_head *head = &hba->clk_list_head;
1ab27c9c 5384 unsigned long flags;
c6e79dac
SRT		 5385
5386 if (!head || list_empty(head))
5387 goto out;
5388
5389 list_for_each_entry(clki, head, list) {
5390 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 5391 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
5392 continue;
5393
c6e79dac
SRT		 5394 if (on && !clki->enabled) {
5395 ret = clk_prepare_enable(clki->clk);
5396 if (ret) {
5397 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
5398 __func__, clki->name, ret);
5399 goto out;
5400 }
5401 } else if (!on && clki->enabled) {
5402 clk_disable_unprepare(clki->clk);
5403 }
5404 clki->enabled = on;
5405 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
5406 clki->name, on ? "en" : "dis");
5407 }
5408 }
1ab27c9c 5409
0263bcd0 5410 ret = ufshcd_vops_setup_clocks(hba, on);
c6e79dac
SRT		 5411out:
5412 if (ret) {
5413 list_for_each_entry(clki, head, list) {
5414 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
5415 clk_disable_unprepare(clki->clk);
5416 }
eda910e4 5417 } else if (on) {
1ab27c9c
ST		 5418 spin_lock_irqsave(hba->host->host_lock, flags);
5419 hba->clk_gating.state = CLKS_ON;
5420 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac
SRT		 5421 }
5422 return ret;
5423}
5424
57d104c1
SJ		 5425static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
5426{
5427 return __ufshcd_setup_clocks(hba, on, false);
5428}
5429
c6e79dac
SRT		 5430static int ufshcd_init_clocks(struct ufs_hba *hba)
5431{
5432 int ret = 0;
5433 struct ufs_clk_info *clki;
5434 struct device *dev = hba->dev;
5435 struct list_head *head = &hba->clk_list_head;
5436
5437 if (!head || list_empty(head))
5438 goto out;
5439
5440 list_for_each_entry(clki, head, list) {
5441 if (!clki->name)
5442 continue;
5443
5444 clki->clk = devm_clk_get(dev, clki->name);
5445 if (IS_ERR(clki->clk)) {
5446 ret = PTR_ERR(clki->clk);
5447 dev_err(dev, "%s: %s clk get failed, %d\n",
5448 __func__, clki->name, ret);
5449 goto out;
5450 }
5451
5452 if (clki->max_freq) {
5453 ret = clk_set_rate(clki->clk, clki->max_freq);
5454 if (ret) {
5455 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5456 __func__, clki->name,
5457 clki->max_freq, ret);
5458 goto out;
5459 }
856b3483 5460 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 5461 }
5462 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
5463 clki->name, clk_get_rate(clki->clk));
5464 }
5465out:
5466 return ret;
5467}
5468
5c0c28a8
SRT		 5469static int ufshcd_variant_hba_init(struct ufs_hba *hba)
5470{
5471 int err = 0;
5472
5473 if (!hba->vops)
5474 goto out;
5475
0263bcd0
YG		 5476 err = ufshcd_vops_init(hba);
5477 if (err)
5478 goto out;
5c0c28a8 5479
0263bcd0
YG		 5480 err = ufshcd_vops_setup_regulators(hba, true);
5481 if (err)
5482 goto out_exit;
5c0c28a8
SRT		 5483
5484 goto out;
5485
5c0c28a8 5486out_exit:
0263bcd0 5487 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 5488out:
5489 if (err)
5490 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 5491 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 5492 return err;
5493}
5494
5495static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
5496{
5497 if (!hba->vops)
5498 return;
5499
0263bcd0 5500 ufshcd_vops_setup_clocks(hba, false);
5c0c28a8 5501
0263bcd0 5502 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 5503
0263bcd0 5504 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 5505}
5506
aa497613
SRT		 5507static int ufshcd_hba_init(struct ufs_hba *hba)
5508{
5509 int err;
5510
6a771a65
RS		 5511 /*
5512 * Handle host controller power separately from the UFS device power
5513 * rails as it will help controlling the UFS host controller power
5514 * collapse easily which is different than UFS device power collapse.
5515 * Also, enable the host controller power before we go ahead with rest
5516 * of the initialization here.
5517 */
5518 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 5519 if (err)
5520 goto out;
5521
6a771a65 5522 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 5523 if (err)
5524 goto out;
5525
6a771a65
RS		 5526 err = ufshcd_init_clocks(hba);
5527 if (err)
5528 goto out_disable_hba_vreg;
5529
5530 err = ufshcd_setup_clocks(hba, true);
5531 if (err)
5532 goto out_disable_hba_vreg;
5533
c6e79dac
SRT		 5534 err = ufshcd_init_vreg(hba);
5535 if (err)
5536 goto out_disable_clks;
5537
5538 err = ufshcd_setup_vreg(hba, true);
5539 if (err)
5540 goto out_disable_clks;
5541
aa497613
SRT		 5542 err = ufshcd_variant_hba_init(hba);
5543 if (err)
5544 goto out_disable_vreg;
5545
1d337ec2 5546 hba->is_powered = true;
aa497613
SRT		 5547 goto out;
5548
5549out_disable_vreg:
5550 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 5551out_disable_clks:
5552 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 5553out_disable_hba_vreg:
5554 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 5555out:
5556 return err;
5557}
5558
5559static void ufshcd_hba_exit(struct ufs_hba *hba)
5560{
1d337ec2
SRT		 5561 if (hba->is_powered) {
5562 ufshcd_variant_hba_exit(hba);
5563 ufshcd_setup_vreg(hba, false);
5564 ufshcd_setup_clocks(hba, false);
5565 ufshcd_setup_hba_vreg(hba, false);
5566 hba->is_powered = false;
5567 }
aa497613
SRT		 5568}
5569
57d104c1
SJ		 5570static int
5571ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
5572{
5573 unsigned char cmd[6] = {REQUEST_SENSE,
5574 0,
5575 0,
5576 0,
5577 SCSI_SENSE_BUFFERSIZE,
5578 0};
5579 char *buffer;
5580 int ret;
5581
5582 buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
5583 if (!buffer) {
5584 ret = -ENOMEM;
5585 goto out;
5586 }
5587
5588 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
5589 SCSI_SENSE_BUFFERSIZE, NULL,
5590 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
5591 if (ret)
5592 pr_err("%s: failed with err %d\n", __func__, ret);
5593
5594 kfree(buffer);
5595out:
5596 return ret;
5597}
5598
5599/**
5600 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
5601 * power mode
5602 * @hba: per adapter instance
5603 * @pwr_mode: device power mode to set
5604 *
5605 * Returns 0 if requested power mode is set successfully
5606 * Returns non-zero if failed to set the requested power mode
5607 */
5608static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
5609 enum ufs_dev_pwr_mode pwr_mode)
5610{
5611 unsigned char cmd[6] = { START_STOP };
5612 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 5613 struct scsi_device *sdp;
5614 unsigned long flags;
57d104c1
SJ		 5615 int ret;
5616
7c48bfd0
AM		 5617 spin_lock_irqsave(hba->host->host_lock, flags);
5618 sdp = hba->sdev_ufs_device;
5619 if (sdp) {
5620 ret = scsi_device_get(sdp);
5621 if (!ret && !scsi_device_online(sdp)) {
5622 ret = -ENODEV;
5623 scsi_device_put(sdp);
5624 }
5625 } else {
5626 ret = -ENODEV;
5627 }
5628 spin_unlock_irqrestore(hba->host->host_lock, flags);
5629
5630 if (ret)
5631 return ret;
57d104c1
SJ		 5632
5633 /*
5634 * If scsi commands fail, the scsi mid-layer schedules scsi error-
5635 * handling, which would wait for host to be resumed. Since we know
5636 * we are functional while we are here, skip host resume in error
5637 * handling context.
5638 */
5639 hba->host->eh_noresume = 1;
5640 if (hba->wlun_dev_clr_ua) {
5641 ret = ufshcd_send_request_sense(hba, sdp);
5642 if (ret)
5643 goto out;
5644 /* Unit attention condition is cleared now */
5645 hba->wlun_dev_clr_ua = false;
5646 }
5647
5648 cmd[4] = pwr_mode << 4;
5649
5650 /*
5651 * Current function would be generally called from the power management
5652 * callbacks hence set the REQ_PM flag so that it doesn't resume the
5653 * already suspended childs.
5654 */
5655 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
5656 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
5657 if (ret) {
5658 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 5659 "START_STOP failed for power mode: %d, result %x\n",
5660 pwr_mode, ret);
21045519
HR		 5661 if (driver_byte(ret) & DRIVER_SENSE)
5662 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 5663 }
5664
5665 if (!ret)
5666 hba->curr_dev_pwr_mode = pwr_mode;
5667out:
7c48bfd0 5668 scsi_device_put(sdp);
57d104c1
SJ		 5669 hba->host->eh_noresume = 0;
5670 return ret;
5671}
5672
5673static int ufshcd_link_state_transition(struct ufs_hba *hba,
5674 enum uic_link_state req_link_state,
5675 int check_for_bkops)
5676{
5677 int ret = 0;
5678
5679 if (req_link_state == hba->uic_link_state)
5680 return 0;
5681
5682 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
5683 ret = ufshcd_uic_hibern8_enter(hba);
5684 if (!ret)
5685 ufshcd_set_link_hibern8(hba);
5686 else
5687 goto out;
5688 }
5689 /*
5690 * If autobkops is enabled, link can't be turned off because
5691 * turning off the link would also turn off the device.
5692 */
5693 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
5694 (!check_for_bkops || (check_for_bkops &&
5695 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 5696 /*
5697 * Let's make sure that link is in low power mode, we are doing
5698 * this currently by putting the link in Hibern8. Otherway to
5699 * put the link in low power mode is to send the DME end point
5700 * to device and then send the DME reset command to local
5701 * unipro. But putting the link in hibern8 is much faster.
5702 */
5703 ret = ufshcd_uic_hibern8_enter(hba);
5704 if (ret)
5705 goto out;
57d104c1
SJ		 5706 /*
5707 * Change controller state to "reset state" which
5708 * should also put the link in off/reset state
5709 */
596585a2 5710 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 5711 /*
5712 * TODO: Check if we need any delay to make sure that
5713 * controller is reset
5714 */
5715 ufshcd_set_link_off(hba);
5716 }
5717
5718out:
5719 return ret;
5720}
5721
5722static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
5723{
b799fdf7
YG		 5724 /*
5725 * It seems some UFS devices may keep drawing more than sleep current
5726 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
5727 * To avoid this situation, add 2ms delay before putting these UFS
5728 * rails in LPM mode.
5729 */
5730 if (!ufshcd_is_link_active(hba) &&
5731 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
5732 usleep_range(2000, 2100);
5733
57d104c1
SJ		 5734 /*
5735 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
5736 * power.
5737 *
5738 * If UFS device and link is in OFF state, all power supplies (VCC,
5739 * VCCQ, VCCQ2) can be turned off if power on write protect is not
5740 * required. If UFS link is inactive (Hibern8 or OFF state) and device
5741 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
5742 *
5743 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
5744 * in low power state which would save some power.
5745 */
5746 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5747 !hba->dev_info.is_lu_power_on_wp) {
5748 ufshcd_setup_vreg(hba, false);
5749 } else if (!ufshcd_is_ufs_dev_active(hba)) {
5750 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
5751 if (!ufshcd_is_link_active(hba)) {
5752 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
5753 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
5754 }
5755 }
5756}
5757
5758static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
5759{
5760 int ret = 0;
5761
5762 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
5763 !hba->dev_info.is_lu_power_on_wp) {
5764 ret = ufshcd_setup_vreg(hba, true);
5765 } else if (!ufshcd_is_ufs_dev_active(hba)) {
5766 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
5767 if (!ret && !ufshcd_is_link_active(hba)) {
5768 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
5769 if (ret)
5770 goto vcc_disable;
5771 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
5772 if (ret)
5773 goto vccq_lpm;
5774 }
5775 }
5776 goto out;
5777
5778vccq_lpm:
5779 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
5780vcc_disable:
5781 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
5782out:
5783 return ret;
5784}
5785
5786static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
5787{
5788 if (ufshcd_is_link_off(hba))
5789 ufshcd_setup_hba_vreg(hba, false);
5790}
5791
5792static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
5793{
5794 if (ufshcd_is_link_off(hba))
5795 ufshcd_setup_hba_vreg(hba, true);
5796}
5797
7a3e97b0 5798/**
57d104c1 5799 * ufshcd_suspend - helper function for suspend operations
3b1d0580 5800 * @hba: per adapter instance
57d104c1
SJ		 5801 * @pm_op: desired low power operation type
5802 *
5803 * This function will try to put the UFS device and link into low power
5804 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
5805 * (System PM level).
5806 *
5807 * If this function is called during shutdown, it will make sure that
5808 * both UFS device and UFS link is powered off.
7a3e97b0 5809 *
57d104c1
SJ		 5810 * NOTE: UFS device & link must be active before we enter in this function.
5811 *
5812 * Returns 0 for success and non-zero for failure
7a3e97b0 5813 */
57d104c1 5814static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 5815{
57d104c1
SJ		 5816 int ret = 0;
5817 enum ufs_pm_level pm_lvl;
5818 enum ufs_dev_pwr_mode req_dev_pwr_mode;
5819 enum uic_link_state req_link_state;
5820
5821 hba->pm_op_in_progress = 1;
5822 if (!ufshcd_is_shutdown_pm(pm_op)) {
5823 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
5824 hba->rpm_lvl : hba->spm_lvl;
5825 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
5826 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
5827 } else {
5828 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
5829 req_link_state = UIC_LINK_OFF_STATE;
5830 }
5831
7a3e97b0 5832 /*
57d104c1
SJ		 5833 * If we can't transition into any of the low power modes
5834 * just gate the clocks.
7a3e97b0 5835 */
1ab27c9c
ST		 5836 ufshcd_hold(hba, false);
5837 hba->clk_gating.is_suspended = true;
5838
57d104c1
SJ		 5839 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
5840 req_link_state == UIC_LINK_ACTIVE_STATE) {
5841 goto disable_clks;
5842 }
7a3e97b0 5843
57d104c1
SJ		 5844 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
5845 (req_link_state == hba->uic_link_state))
5846 goto out;
5847
5848 /* UFS device & link must be active before we enter in this function */
5849 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
5850 ret = -EINVAL;
5851 goto out;
5852 }
5853
5854 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 5855 if (ufshcd_can_autobkops_during_suspend(hba)) {
5856 /*
5857 * The device is idle with no requests in the queue,
5858 * allow background operations if bkops status shows
5859 * that performance might be impacted.
5860 */
5861 ret = ufshcd_urgent_bkops(hba);
5862 if (ret)
5863 goto enable_gating;
5864 } else {
5865 /* make sure that auto bkops is disabled */
5866 ufshcd_disable_auto_bkops(hba);
5867 }
57d104c1
SJ		 5868 }
5869
5870 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
5871 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
5872 !ufshcd_is_runtime_pm(pm_op))) {
5873 /* ensure that bkops is disabled */
5874 ufshcd_disable_auto_bkops(hba);
5875 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
5876 if (ret)
1ab27c9c 5877 goto enable_gating;
57d104c1
SJ		 5878 }
5879
5880 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
5881 if (ret)
5882 goto set_dev_active;
5883
5884 ufshcd_vreg_set_lpm(hba);
5885
5886disable_clks:
856b3483
ST		 5887 /*
5888 * The clock scaling needs access to controller registers. Hence, Wait
5889 * for pending clock scaling work to be done before clocks are
5890 * turned off.
5891 */
5892 if (ufshcd_is_clkscaling_enabled(hba)) {
5893 devfreq_suspend_device(hba->devfreq);
5894 hba->clk_scaling.window_start_t = 0;
5895 }
57d104c1
SJ		 5896 /*
5897 * Call vendor specific suspend callback. As these callbacks may access
5898 * vendor specific host controller register space call them before the
5899 * host clocks are ON.
5900 */
0263bcd0
YG		 5901 ret = ufshcd_vops_suspend(hba, pm_op);
5902 if (ret)
5903 goto set_link_active;
57d104c1 5904
0263bcd0
YG		 5905 ret = ufshcd_vops_setup_clocks(hba, false);
5906 if (ret)
5907 goto vops_resume;
57d104c1
SJ		 5908
5909 if (!ufshcd_is_link_active(hba))
5910 ufshcd_setup_clocks(hba, false);
5911 else
5912 /* If link is active, device ref_clk can't be switched off */
5913 __ufshcd_setup_clocks(hba, false, true);
5914
1ab27c9c 5915 hba->clk_gating.state = CLKS_OFF;
57d104c1
SJ		 5916 /*
5917 * Disable the host irq as host controller as there won't be any
0263bcd0 5918 * host controller transaction expected till resume.
57d104c1
SJ		 5919 */
5920 ufshcd_disable_irq(hba);
5921 /* Put the host controller in low power mode if possible */
5922 ufshcd_hba_vreg_set_lpm(hba);
5923 goto out;
5924
5925vops_resume:
0263bcd0 5926 ufshcd_vops_resume(hba, pm_op);
57d104c1
SJ		 5927set_link_active:
5928 ufshcd_vreg_set_hpm(hba);
5929 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
5930 ufshcd_set_link_active(hba);
5931 else if (ufshcd_is_link_off(hba))
5932 ufshcd_host_reset_and_restore(hba);
5933set_dev_active:
5934 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
5935 ufshcd_disable_auto_bkops(hba);
1ab27c9c
ST		 5936enable_gating:
5937 hba->clk_gating.is_suspended = false;
5938 ufshcd_release(hba);
57d104c1
SJ		 5939out:
5940 hba->pm_op_in_progress = 0;
5941 return ret;
7a3e97b0
SY		 5942}
5943
5944/**
57d104c1 5945 * ufshcd_resume - helper function for resume operations
3b1d0580 5946 * @hba: per adapter instance
57d104c1 5947 * @pm_op: runtime PM or system PM
7a3e97b0 5948 *
57d104c1
SJ		 5949 * This function basically brings the UFS device, UniPro link and controller
5950 * to active state.
5951 *
5952 * Returns 0 for success and non-zero for failure
7a3e97b0 5953 */
57d104c1 5954static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 5955{
57d104c1
SJ		 5956 int ret;
5957 enum uic_link_state old_link_state;
5958
5959 hba->pm_op_in_progress = 1;
5960 old_link_state = hba->uic_link_state;
5961
5962 ufshcd_hba_vreg_set_hpm(hba);
5963 /* Make sure clocks are enabled before accessing controller */
5964 ret = ufshcd_setup_clocks(hba, true);
5965 if (ret)
5966 goto out;
5967
57d104c1
SJ		 5968 /* enable the host irq as host controller would be active soon */
5969 ret = ufshcd_enable_irq(hba);
5970 if (ret)
5971 goto disable_irq_and_vops_clks;
5972
5973 ret = ufshcd_vreg_set_hpm(hba);
5974 if (ret)
5975 goto disable_irq_and_vops_clks;
5976
7a3e97b0 5977 /*
57d104c1
SJ		 5978 * Call vendor specific resume callback. As these callbacks may access
5979 * vendor specific host controller register space call them when the
5980 * host clocks are ON.
7a3e97b0 5981 */
0263bcd0
YG		 5982 ret = ufshcd_vops_resume(hba, pm_op);
5983 if (ret)
5984 goto disable_vreg;
57d104c1
SJ		 5985
5986 if (ufshcd_is_link_hibern8(hba)) {
5987 ret = ufshcd_uic_hibern8_exit(hba);
5988 if (!ret)
5989 ufshcd_set_link_active(hba);
5990 else
5991 goto vendor_suspend;
5992 } else if (ufshcd_is_link_off(hba)) {
5993 ret = ufshcd_host_reset_and_restore(hba);
5994 /*
5995 * ufshcd_host_reset_and_restore() should have already
5996 * set the link state as active
5997 */
5998 if (ret || !ufshcd_is_link_active(hba))
5999 goto vendor_suspend;
6000 }
6001
6002 if (!ufshcd_is_ufs_dev_active(hba)) {
6003 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
6004 if (ret)
6005 goto set_old_link_state;
6006 }
6007
374a246e
SJ		 6008 /*
6009 * If BKOPs operations are urgently needed at this moment then
6010 * keep auto-bkops enabled or else disable it.
6011 */
6012 ufshcd_urgent_bkops(hba);
1ab27c9c
ST		 6013 hba->clk_gating.is_suspended = false;
6014
856b3483
ST		 6015 if (ufshcd_is_clkscaling_enabled(hba))
6016 devfreq_resume_device(hba->devfreq);
6017
1ab27c9c
ST		 6018 /* Schedule clock gating in case of no access to UFS device yet */
6019 ufshcd_release(hba);
57d104c1
SJ		 6020 goto out;
6021
6022set_old_link_state:
6023 ufshcd_link_state_transition(hba, old_link_state, 0);
6024vendor_suspend:
0263bcd0 6025 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 6026disable_vreg:
6027 ufshcd_vreg_set_lpm(hba);
6028disable_irq_and_vops_clks:
6029 ufshcd_disable_irq(hba);
57d104c1
SJ		 6030 ufshcd_setup_clocks(hba, false);
6031out:
6032 hba->pm_op_in_progress = 0;
6033 return ret;
6034}
6035
6036/**
6037 * ufshcd_system_suspend - system suspend routine
6038 * @hba: per adapter instance
6039 * @pm_op: runtime PM or system PM
6040 *
6041 * Check the description of ufshcd_suspend() function for more details.
6042 *
6043 * Returns 0 for success and non-zero for failure
6044 */
6045int ufshcd_system_suspend(struct ufs_hba *hba)
6046{
6047 int ret = 0;
6048
6049 if (!hba || !hba->is_powered)
233b594b 6050 return 0;
57d104c1
SJ		 6051
6052 if (pm_runtime_suspended(hba->dev)) {
6053 if (hba->rpm_lvl == hba->spm_lvl)
6054 /*
6055 * There is possibility that device may still be in
6056 * active state during the runtime suspend.
6057 */
6058 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
6059 hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
6060 goto out;
6061
6062 /*
6063 * UFS device and/or UFS link low power states during runtime
6064 * suspend seems to be different than what is expected during
6065 * system suspend. Hence runtime resume the devic & link and
6066 * let the system suspend low power states to take effect.
6067 * TODO: If resume takes longer time, we might have optimize
6068 * it in future by not resuming everything if possible.
6069 */
6070 ret = ufshcd_runtime_resume(hba);
6071 if (ret)
6072 goto out;
6073 }
6074
6075 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
6076out:
e785060e
DR		 6077 if (!ret)
6078 hba->is_sys_suspended = true;
57d104c1
SJ		 6079 return ret;
6080}
6081EXPORT_SYMBOL(ufshcd_system_suspend);
6082
6083/**
6084 * ufshcd_system_resume - system resume routine
6085 * @hba: per adapter instance
6086 *
6087 * Returns 0 for success and non-zero for failure
6088 */
7a3e97b0 6089
57d104c1
SJ		 6090int ufshcd_system_resume(struct ufs_hba *hba)
6091{
6092 if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev))
6093 /*
6094 * Let the runtime resume take care of resuming
6095 * if runtime suspended.
6096 */
6097 return 0;
6098
6099 return ufshcd_resume(hba, UFS_SYSTEM_PM);
7a3e97b0 6100}
57d104c1 6101EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 6102
57d104c1
SJ		 6103/**
6104 * ufshcd_runtime_suspend - runtime suspend routine
6105 * @hba: per adapter instance
6106 *
6107 * Check the description of ufshcd_suspend() function for more details.
6108 *
6109 * Returns 0 for success and non-zero for failure
6110 */
66ec6d59
SRT		 6111int ufshcd_runtime_suspend(struct ufs_hba *hba)
6112{
57d104c1 6113 if (!hba || !hba->is_powered)
66ec6d59
SRT		 6114 return 0;
6115
57d104c1 6116 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 6117}
6118EXPORT_SYMBOL(ufshcd_runtime_suspend);
6119
57d104c1
SJ		 6120/**
6121 * ufshcd_runtime_resume - runtime resume routine
6122 * @hba: per adapter instance
6123 *
6124 * This function basically brings the UFS device, UniPro link and controller
6125 * to active state. Following operations are done in this function:
6126 *
6127 * 1. Turn on all the controller related clocks
6128 * 2. Bring the UniPro link out of Hibernate state
6129 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
6130 * to active state.
6131 * 4. If auto-bkops is enabled on the device, disable it.
6132 *
6133 * So following would be the possible power state after this function return
6134 * successfully:
6135 * S1: UFS device in Active state with VCC rail ON
6136 * UniPro link in Active state
6137 * All the UFS/UniPro controller clocks are ON
6138 *
6139 * Returns 0 for success and non-zero for failure
6140 */
66ec6d59
SRT		 6141int ufshcd_runtime_resume(struct ufs_hba *hba)
6142{
57d104c1 6143 if (!hba || !hba->is_powered)
66ec6d59 6144 return 0;
57d104c1
SJ		 6145 else
6146 return ufshcd_resume(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 6147}
6148EXPORT_SYMBOL(ufshcd_runtime_resume);
6149
6150int ufshcd_runtime_idle(struct ufs_hba *hba)
6151{
6152 return 0;
6153}
6154EXPORT_SYMBOL(ufshcd_runtime_idle);
6155
57d104c1
SJ		 6156/**
6157 * ufshcd_shutdown - shutdown routine
6158 * @hba: per adapter instance
6159 *
6160 * This function would power off both UFS device and UFS link.
6161 *
6162 * Returns 0 always to allow force shutdown even in case of errors.
6163 */
6164int ufshcd_shutdown(struct ufs_hba *hba)
6165{
6166 int ret = 0;
6167
6168 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
6169 goto out;
6170
6171 if (pm_runtime_suspended(hba->dev)) {
6172 ret = ufshcd_runtime_resume(hba);
6173 if (ret)
6174 goto out;
6175 }
6176
6177 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
6178out:
6179 if (ret)
6180 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
6181 /* allow force shutdown even in case of errors */
6182 return 0;
6183}
6184EXPORT_SYMBOL(ufshcd_shutdown);
6185
7a3e97b0 6186/**
3b1d0580 6187 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 6188 * data structure memory
3b1d0580 6189 * @hba - per adapter instance
7a3e97b0 6190 */
3b1d0580 6191void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 6192{
cfdf9c91 6193 scsi_remove_host(hba->host);
7a3e97b0 6194 /* disable interrupts */
2fbd009b 6195 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 6196 ufshcd_hba_stop(hba, true);
7a3e97b0 6197
7a3e97b0 6198 scsi_host_put(hba->host);
5c0c28a8 6199
1ab27c9c 6200 ufshcd_exit_clk_gating(hba);
856b3483
ST		 6201 if (ufshcd_is_clkscaling_enabled(hba))
6202 devfreq_remove_device(hba->devfreq);
aa497613 6203 ufshcd_hba_exit(hba);
3b1d0580
VH		 6204}
6205EXPORT_SYMBOL_GPL(ufshcd_remove);
6206
47555a5c
YG		 6207/**
6208 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
6209 * @hba: pointer to Host Bus Adapter (HBA)
6210 */
6211void ufshcd_dealloc_host(struct ufs_hba *hba)
6212{
6213 scsi_host_put(hba->host);
6214}
6215EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
6216
ca3d7bf9
AM		 6217/**
6218 * ufshcd_set_dma_mask - Set dma mask based on the controller
6219 * addressing capability
6220 * @hba: per adapter instance
6221 *
6222 * Returns 0 for success, non-zero for failure
6223 */
6224static int ufshcd_set_dma_mask(struct ufs_hba *hba)
6225{
6226 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
6227 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
6228 return 0;
6229 }
6230 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
6231}
6232
7a3e97b0 6233/**
5c0c28a8 6234 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 6235 * @dev: pointer to device handle
6236 * @hba_handle: driver private handle
7a3e97b0
SY		 6237 * Returns 0 on success, non-zero value on failure
6238 */
5c0c28a8 6239int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 6240{
6241 struct Scsi_Host *host;
6242 struct ufs_hba *hba;
5c0c28a8 6243 int err = 0;
7a3e97b0 6244
3b1d0580
VH		 6245 if (!dev) {
6246 dev_err(dev,
6247 "Invalid memory reference for dev is NULL\n");
6248 err = -ENODEV;
7a3e97b0
SY		 6249 goto out_error;
6250 }
6251
7a3e97b0
SY		 6252 host = scsi_host_alloc(&ufshcd_driver_template,
6253 sizeof(struct ufs_hba));
6254 if (!host) {
3b1d0580 6255 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 6256 err = -ENOMEM;
3b1d0580 6257 goto out_error;
7a3e97b0
SY		 6258 }
6259 hba = shost_priv(host);
7a3e97b0 6260 hba->host = host;
3b1d0580 6261 hba->dev = dev;
5c0c28a8
SRT		 6262 *hba_handle = hba;
6263
6264out_error:
6265 return err;
6266}
6267EXPORT_SYMBOL(ufshcd_alloc_host);
6268
856b3483
ST		 6269static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
6270{
6271 int ret = 0;
6272 struct ufs_clk_info *clki;
6273 struct list_head *head = &hba->clk_list_head;
6274
6275 if (!head || list_empty(head))
6276 goto out;
6277
f06fcc71
YG		 6278 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
6279 if (ret)
6280 return ret;
6281
856b3483
ST		 6282 list_for_each_entry(clki, head, list) {
6283 if (!IS_ERR_OR_NULL(clki->clk)) {
6284 if (scale_up && clki->max_freq) {
6285 if (clki->curr_freq == clki->max_freq)
6286 continue;
6287 ret = clk_set_rate(clki->clk, clki->max_freq);
6288 if (ret) {
6289 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6290 __func__, clki->name,
6291 clki->max_freq, ret);
6292 break;
6293 }
6294 clki->curr_freq = clki->max_freq;
6295
6296 } else if (!scale_up && clki->min_freq) {
6297 if (clki->curr_freq == clki->min_freq)
6298 continue;
6299 ret = clk_set_rate(clki->clk, clki->min_freq);
6300 if (ret) {
6301 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6302 __func__, clki->name,
6303 clki->min_freq, ret);
6304 break;
6305 }
6306 clki->curr_freq = clki->min_freq;
6307 }
6308 }
6309 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
6310 clki->name, clk_get_rate(clki->clk));
6311 }
f06fcc71
YG		 6312
6313 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
6314
856b3483
ST		 6315out:
6316 return ret;
6317}
6318
6319static int ufshcd_devfreq_target(struct device *dev,
6320 unsigned long *freq, u32 flags)
6321{
6322 int err = 0;
6323 struct ufs_hba *hba = dev_get_drvdata(dev);
6324
6325 if (!ufshcd_is_clkscaling_enabled(hba))
6326 return -EINVAL;
6327
6328 if (*freq == UINT_MAX)
6329 err = ufshcd_scale_clks(hba, true);
6330 else if (*freq == 0)
6331 err = ufshcd_scale_clks(hba, false);
6332
6333 return err;
6334}
6335
6336static int ufshcd_devfreq_get_dev_status(struct device *dev,
6337 struct devfreq_dev_status *stat)
6338{
6339 struct ufs_hba *hba = dev_get_drvdata(dev);
6340 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
6341 unsigned long flags;
6342
6343 if (!ufshcd_is_clkscaling_enabled(hba))
6344 return -EINVAL;
6345
6346 memset(stat, 0, sizeof(*stat));
6347
6348 spin_lock_irqsave(hba->host->host_lock, flags);
6349 if (!scaling->window_start_t)
6350 goto start_window;
6351
6352 if (scaling->is_busy_started)
6353 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
6354 scaling->busy_start_t));
6355
6356 stat->total_time = jiffies_to_usecs((long)jiffies -
6357 (long)scaling->window_start_t);
6358 stat->busy_time = scaling->tot_busy_t;
6359start_window:
6360 scaling->window_start_t = jiffies;
6361 scaling->tot_busy_t = 0;
6362
6363 if (hba->outstanding_reqs) {
6364 scaling->busy_start_t = ktime_get();
6365 scaling->is_busy_started = true;
6366 } else {
6367 scaling->busy_start_t = ktime_set(0, 0);
6368 scaling->is_busy_started = false;
6369 }
6370 spin_unlock_irqrestore(hba->host->host_lock, flags);
6371 return 0;
6372}
6373
6374static struct devfreq_dev_profile ufs_devfreq_profile = {
6375 .polling_ms = 100,
6376 .target = ufshcd_devfreq_target,
6377 .get_dev_status = ufshcd_devfreq_get_dev_status,
6378};
6379
5c0c28a8
SRT		 6380/**
6381 * ufshcd_init - Driver initialization routine
6382 * @hba: per-adapter instance
6383 * @mmio_base: base register address
6384 * @irq: Interrupt line of device
6385 * Returns 0 on success, non-zero value on failure
6386 */
6387int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
6388{
6389 int err;
6390 struct Scsi_Host *host = hba->host;
6391 struct device *dev = hba->dev;
6392
6393 if (!mmio_base) {
6394 dev_err(hba->dev,
6395 "Invalid memory reference for mmio_base is NULL\n");
6396 err = -ENODEV;
6397 goto out_error;
6398 }
6399
3b1d0580
VH		 6400 hba->mmio_base = mmio_base;
6401 hba->irq = irq;
7a3e97b0 6402
aa497613 6403 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 6404 if (err)
6405 goto out_error;
6406
7a3e97b0
SY		 6407 /* Read capabilities registers */
6408 ufshcd_hba_capabilities(hba);
6409
6410 /* Get UFS version supported by the controller */
6411 hba->ufs_version = ufshcd_get_ufs_version(hba);
6412
2fbd009b
SJ		 6413 /* Get Interrupt bit mask per version */
6414 hba->intr_mask = ufshcd_get_intr_mask(hba);
6415
ca3d7bf9
AM		 6416 err = ufshcd_set_dma_mask(hba);
6417 if (err) {
6418 dev_err(hba->dev, "set dma mask failed\n");
6419 goto out_disable;
6420 }
6421
7a3e97b0
SY		 6422 /* Allocate memory for host memory space */
6423 err = ufshcd_memory_alloc(hba);
6424 if (err) {
3b1d0580
VH		 6425 dev_err(hba->dev, "Memory allocation failed\n");
6426 goto out_disable;
7a3e97b0
SY		 6427 }
6428
6429 /* Configure LRB */
6430 ufshcd_host_memory_configure(hba);
6431
6432 host->can_queue = hba->nutrs;
6433 host->cmd_per_lun = hba->nutrs;
6434 host->max_id = UFSHCD_MAX_ID;
0ce147d4 6435 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 6436 host->max_channel = UFSHCD_MAX_CHANNEL;
6437 host->unique_id = host->host_no;
6438 host->max_cmd_len = MAX_CDB_SIZE;
6439
7eb584db
DR		 6440 hba->max_pwr_info.is_valid = false;
6441
7a3e97b0 6442 /* Initailize wait queue for task management */
e2933132
SRT		 6443 init_waitqueue_head(&hba->tm_wq);
6444 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 6445
6446 /* Initialize work queues */
e8e7f271 6447 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 6448 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 6449
6ccf44fe
SJ		 6450 /* Initialize UIC command mutex */
6451 mutex_init(&hba->uic_cmd_mutex);
6452
5a0b0cb9
SRT		 6453 /* Initialize mutex for device management commands */
6454 mutex_init(&hba->dev_cmd.lock);
6455
6456 /* Initialize device management tag acquire wait queue */
6457 init_waitqueue_head(&hba->dev_cmd.tag_wq);
6458
1ab27c9c 6459 ufshcd_init_clk_gating(hba);
199ef13c
YG		 6460
6461 /*
6462 * In order to avoid any spurious interrupt immediately after
6463 * registering UFS controller interrupt handler, clear any pending UFS
6464 * interrupt status and disable all the UFS interrupts.
6465 */
6466 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
6467 REG_INTERRUPT_STATUS);
6468 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
6469 /*
6470 * Make sure that UFS interrupts are disabled and any pending interrupt
6471 * status is cleared before registering UFS interrupt handler.
6472 */
6473 mb();
6474
7a3e97b0 6475 /* IRQ registration */
2953f850 6476 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 6477 if (err) {
3b1d0580 6478 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 6479 goto exit_gating;
57d104c1
SJ		 6480 } else {
6481 hba->is_irq_enabled = true;
7a3e97b0
SY		 6482 }
6483
3b1d0580 6484 err = scsi_add_host(host, hba->dev);
7a3e97b0 6485 if (err) {
3b1d0580 6486 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 6487 goto exit_gating;
7a3e97b0
SY		 6488 }
6489
6ccf44fe
SJ		 6490 /* Host controller enable */
6491 err = ufshcd_hba_enable(hba);
7a3e97b0 6492 if (err) {
6ccf44fe 6493 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 6494 goto out_remove_scsi_host;
7a3e97b0 6495 }
6ccf44fe 6496
856b3483
ST		 6497 if (ufshcd_is_clkscaling_enabled(hba)) {
6498 hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
6499 "simple_ondemand", NULL);
6500 if (IS_ERR(hba->devfreq)) {
6501 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
6502 PTR_ERR(hba->devfreq));
6503 goto out_remove_scsi_host;
6504 }
6505 /* Suspend devfreq until the UFS device is detected */
6506 devfreq_suspend_device(hba->devfreq);
6507 hba->clk_scaling.window_start_t = 0;
6508 }
6509
62694735
SRT		 6510 /* Hold auto suspend until async scan completes */
6511 pm_runtime_get_sync(dev);
6512
57d104c1
SJ		 6513 /*
6514 * The device-initialize-sequence hasn't been invoked yet.
6515 * Set the device to power-off state
6516 */
6517 ufshcd_set_ufs_dev_poweroff(hba);
6518
6ccf44fe
SJ		 6519 async_schedule(ufshcd_async_scan, hba);
6520
7a3e97b0
SY		 6521 return 0;
6522
3b1d0580
VH		 6523out_remove_scsi_host:
6524 scsi_remove_host(hba->host);
1ab27c9c
ST		 6525exit_gating:
6526 ufshcd_exit_clk_gating(hba);
3b1d0580 6527out_disable:
57d104c1 6528 hba->is_irq_enabled = false;
3b1d0580 6529 scsi_host_put(host);
aa497613 6530 ufshcd_hba_exit(hba);
3b1d0580
VH		 6531out_error:
6532 return err;
6533}
6534EXPORT_SYMBOL_GPL(ufshcd_init);
6535
3b1d0580
VH		 6536MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
6537MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 6538MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 6539MODULE_LICENSE("GPL");
6540MODULE_VERSION(UFSHCD_DRIVER_VERSION);