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ufs: refactor query descriptor API support
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
5c0c28a8 6 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe
SJ		 40#include <linux/async.h>
41
e0eca63e 42#include "ufshcd.h"
53b3d9c3 43#include "unipro.h"
7a3e97b0 44
2fbd009b
SJ		 45#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
46 UTP_TASK_REQ_COMPL |\
53b3d9c3 47 UIC_POWER_MODE |\
2fbd009b 48 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 49/* UIC command timeout, unit: ms */
50#define UIC_CMD_TIMEOUT 500
2fbd009b 51
5a0b0cb9
SRT		 52/* NOP OUT retries waiting for NOP IN response */
53#define NOP_OUT_RETRIES 10
54/* Timeout after 30 msecs if NOP OUT hangs without response */
55#define NOP_OUT_TIMEOUT 30 /* msecs */
56
68078d5c
DR		 57/* Query request retries */
58#define QUERY_REQ_RETRIES 10
59/* Query request timeout */
60#define QUERY_REQ_TIMEOUT 30 /* msec */
61
e2933132
SRT		 62/* Task management command timeout */
63#define TM_CMD_TIMEOUT 100 /* msecs */
64
68078d5c
DR		 65/* Expose the flag value from utp_upiu_query.value */
66#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
67
7d568652
SJ		 68/* Interrupt aggregation default timeout, unit: 40us */
69#define INT_AGGR_DEF_TO 0x02
70
aa497613
SRT		 71#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
72 ({ \
73 int _ret; \
74 if (_on) \
75 _ret = ufshcd_enable_vreg(_dev, _vreg); \
76 else \
77 _ret = ufshcd_disable_vreg(_dev, _vreg); \
78 _ret; \
79 })
80
da461cec
SJ		 81static u32 ufs_query_desc_max_size[] = {
82 QUERY_DESC_DEVICE_MAX_SIZE,
83 QUERY_DESC_CONFIGURAION_MAX_SIZE,
84 QUERY_DESC_UNIT_MAX_SIZE,
85 QUERY_DESC_RFU_MAX_SIZE,
86 QUERY_DESC_INTERCONNECT_MAX_SIZE,
87 QUERY_DESC_STRING_MAX_SIZE,
88 QUERY_DESC_RFU_MAX_SIZE,
89 QUERY_DESC_GEOMETRY_MAZ_SIZE,
90 QUERY_DESC_POWER_MAX_SIZE,
91 QUERY_DESC_RFU_MAX_SIZE,
92};
93
7a3e97b0
SY		 94enum {
95 UFSHCD_MAX_CHANNEL = 0,
96 UFSHCD_MAX_ID = 1,
97 UFSHCD_MAX_LUNS = 8,
98 UFSHCD_CMD_PER_LUN = 32,
99 UFSHCD_CAN_QUEUE = 32,
100};
101
102/* UFSHCD states */
103enum {
7a3e97b0
SY		 104 UFSHCD_STATE_RESET,
105 UFSHCD_STATE_ERROR,
3441da7d
SRT		 106 UFSHCD_STATE_OPERATIONAL,
107};
108
109/* UFSHCD error handling flags */
110enum {
111 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 112};
113
e8e7f271
SRT		 114/* UFSHCD UIC layer error flags */
115enum {
116 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
117 UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */
118 UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */
119 UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */
120};
121
7a3e97b0
SY		 122/* Interrupt configuration options */
123enum {
124 UFSHCD_INT_DISABLE,
125 UFSHCD_INT_ENABLE,
126 UFSHCD_INT_CLEAR,
127};
128
3441da7d
SRT		 129#define ufshcd_set_eh_in_progress(h) \
130 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
131#define ufshcd_eh_in_progress(h) \
132 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
133#define ufshcd_clear_eh_in_progress(h) \
134 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
135
136static void ufshcd_tmc_handler(struct ufs_hba *hba);
137static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 138static int ufshcd_reset_and_restore(struct ufs_hba *hba);
139static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
3441da7d 140
5a0b0cb9
SRT		 141/*
142 * ufshcd_wait_for_register - wait for register value to change
143 * @hba - per-adapter interface
144 * @reg - mmio register offset
145 * @mask - mask to apply to read register value
146 * @val - wait condition
147 * @interval_us - polling interval in microsecs
148 * @timeout_ms - timeout in millisecs
149 *
150 * Returns -ETIMEDOUT on error, zero on success
151 */
152static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
153 u32 val, unsigned long interval_us, unsigned long timeout_ms)
154{
155 int err = 0;
156 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
157
158 /* ignore bits that we don't intend to wait on */
159 val = val & mask;
160
161 while ((ufshcd_readl(hba, reg) & mask) != val) {
162 /* wakeup within 50us of expiry */
163 usleep_range(interval_us, interval_us + 50);
164
165 if (time_after(jiffies, timeout)) {
166 if ((ufshcd_readl(hba, reg) & mask) != val)
167 err = -ETIMEDOUT;
168 break;
169 }
170 }
171
172 return err;
173}
174
2fbd009b
SJ		 175/**
176 * ufshcd_get_intr_mask - Get the interrupt bit mask
177 * @hba - Pointer to adapter instance
178 *
179 * Returns interrupt bit mask per version
180 */
181static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
182{
183 if (hba->ufs_version == UFSHCI_VERSION_10)
184 return INTERRUPT_MASK_ALL_VER_10;
185 else
186 return INTERRUPT_MASK_ALL_VER_11;
187}
188
7a3e97b0
SY		 189/**
190 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
191 * @hba - Pointer to adapter instance
192 *
193 * Returns UFSHCI version supported by the controller
194 */
195static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
196{
b873a275 197 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 198}
199
200/**
201 * ufshcd_is_device_present - Check if any device connected to
202 * the host controller
5c0c28a8 203 * @hba: pointer to adapter instance
7a3e97b0 204 *
73ec513a 205 * Returns 1 if device present, 0 if no device detected
7a3e97b0 206 */
5c0c28a8 207static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 208{
5c0c28a8
SRT		 209 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
210 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 211}
212
213/**
214 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
215 * @lrb: pointer to local command reference block
216 *
217 * This function is used to get the OCS field from UTRD
218 * Returns the OCS field in the UTRD
219 */
220static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
221{
e8c8e82a 222 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 223}
224
225/**
226 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
227 * @task_req_descp: pointer to utp_task_req_desc structure
228 *
229 * This function is used to get the OCS field from UTMRD
230 * Returns the OCS field in the UTMRD
231 */
232static inline int
233ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
234{
e8c8e82a 235 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 236}
237
238/**
239 * ufshcd_get_tm_free_slot - get a free slot for task management request
240 * @hba: per adapter instance
e2933132 241 * @free_slot: pointer to variable with available slot value
7a3e97b0 242 *
e2933132
SRT		 243 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
244 * Returns 0 if free slot is not available, else return 1 with tag value
245 * in @free_slot.
7a3e97b0 246 */
e2933132 247static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 248{
e2933132
SRT		 249 int tag;
250 bool ret = false;
251
252 if (!free_slot)
253 goto out;
254
255 do {
256 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
257 if (tag >= hba->nutmrs)
258 goto out;
259 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
260
261 *free_slot = tag;
262 ret = true;
263out:
264 return ret;
265}
266
267static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
268{
269 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 270}
271
272/**
273 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
274 * @hba: per adapter instance
275 * @pos: position of the bit to be cleared
276 */
277static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
278{
b873a275 279 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 280}
281
282/**
283 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
284 * @reg: Register value of host controller status
285 *
286 * Returns integer, 0 on Success and positive value if failed
287 */
288static inline int ufshcd_get_lists_status(u32 reg)
289{
290 /*
291 * The mask 0xFF is for the following HCS register bits
292 * Bit Description
293 * 0 Device Present
294 * 1 UTRLRDY
295 * 2 UTMRLRDY
296 * 3 UCRDY
297 * 4 HEI
298 * 5 DEI
299 * 6-7 reserved
300 */
301 return (((reg) & (0xFF)) >> 1) ^ (0x07);
302}
303
304/**
305 * ufshcd_get_uic_cmd_result - Get the UIC command result
306 * @hba: Pointer to adapter instance
307 *
308 * This function gets the result of UIC command completion
309 * Returns 0 on success, non zero value on error
310 */
311static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
312{
b873a275 313 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 314 MASK_UIC_COMMAND_RESULT;
315}
316
12b4fdb4
SJ		 317/**
318 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
319 * @hba: Pointer to adapter instance
320 *
321 * This function gets UIC command argument3
322 * Returns 0 on success, non zero value on error
323 */
324static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
325{
326 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
327}
328
7a3e97b0 329/**
5a0b0cb9 330 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 331 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 332 */
333static inline int
5a0b0cb9 334ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 335{
5a0b0cb9 336 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 337}
338
339/**
340 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
341 * @ucd_rsp_ptr: pointer to response UPIU
342 *
343 * This function gets the response status and scsi_status from response UPIU
344 * Returns the response result code.
345 */
346static inline int
347ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
348{
349 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
350}
351
1c2623c5
SJ		 352/*
353 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
354 * from response UPIU
355 * @ucd_rsp_ptr: pointer to response UPIU
356 *
357 * Return the data segment length.
358 */
359static inline unsigned int
360ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
361{
362 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
363 MASK_RSP_UPIU_DATA_SEG_LEN;
364}
365
66ec6d59
SRT		 366/**
367 * ufshcd_is_exception_event - Check if the device raised an exception event
368 * @ucd_rsp_ptr: pointer to response UPIU
369 *
370 * The function checks if the device raised an exception event indicated in
371 * the Device Information field of response UPIU.
372 *
373 * Returns true if exception is raised, false otherwise.
374 */
375static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
376{
377 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
378 MASK_RSP_EXCEPTION_EVENT ? true : false;
379}
380
7a3e97b0 381/**
7d568652 382 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 383 * @hba: per adapter instance
7a3e97b0
SY		 384 */
385static inline void
7d568652 386ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 387{
7d568652
SJ		 388 ufshcd_writel(hba, INT_AGGR_ENABLE |
389 INT_AGGR_COUNTER_AND_TIMER_RESET,
390 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
391}
392
393/**
394 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
395 * @hba: per adapter instance
396 * @cnt: Interrupt aggregation counter threshold
397 * @tmout: Interrupt aggregation timeout value
398 */
399static inline void
400ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
401{
402 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
403 INT_AGGR_COUNTER_THLD_VAL(cnt) |
404 INT_AGGR_TIMEOUT_VAL(tmout),
405 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 406}
407
408/**
409 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
410 * When run-stop registers are set to 1, it indicates the
411 * host controller that it can process the requests
412 * @hba: per adapter instance
413 */
414static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
415{
b873a275
SJ		 416 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
417 REG_UTP_TASK_REQ_LIST_RUN_STOP);
418 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
419 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 420}
421
7a3e97b0
SY		 422/**
423 * ufshcd_hba_start - Start controller initialization sequence
424 * @hba: per adapter instance
425 */
426static inline void ufshcd_hba_start(struct ufs_hba *hba)
427{
b873a275 428 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 429}
430
431/**
432 * ufshcd_is_hba_active - Get controller state
433 * @hba: per adapter instance
434 *
435 * Returns zero if controller is active, 1 otherwise
436 */
437static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
438{
b873a275 439 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 440}
441
442/**
443 * ufshcd_send_command - Send SCSI or device management commands
444 * @hba: per adapter instance
445 * @task_tag: Task tag of the command
446 */
447static inline
448void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
449{
450 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 451 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 452}
453
454/**
455 * ufshcd_copy_sense_data - Copy sense data in case of check condition
456 * @lrb - pointer to local reference block
457 */
458static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
459{
460 int len;
1c2623c5
SJ		 461 if (lrbp->sense_buffer &&
462 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
5a0b0cb9 463 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
7a3e97b0 464 memcpy(lrbp->sense_buffer,
5a0b0cb9 465 lrbp->ucd_rsp_ptr->sr.sense_data,
7a3e97b0
SY		 466 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
467 }
468}
469
68078d5c
DR		 470/**
471 * ufshcd_copy_query_response() - Copy the Query Response and the data
472 * descriptor
473 * @hba: per adapter instance
474 * @lrb - pointer to local reference block
475 */
476static
c6d4a831 477int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 478{
479 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
480
68078d5c 481 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 482
68078d5c
DR		 483 /* Get the descriptor */
484 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 485 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 486 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 487 u16 resp_len;
488 u16 buf_len;
68078d5c
DR		 489
490 /* data segment length */
c6d4a831 491 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 492 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 493 buf_len = be16_to_cpu(
494 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 495 if (likely(buf_len >= resp_len)) {
496 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
497 } else {
498 dev_warn(hba->dev,
499 "%s: Response size is bigger than buffer",
500 __func__);
501 return -EINVAL;
502 }
68078d5c 503 }
c6d4a831
DR		 504
505 return 0;
68078d5c
DR		 506}
507
7a3e97b0
SY		 508/**
509 * ufshcd_hba_capabilities - Read controller capabilities
510 * @hba: per adapter instance
511 */
512static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
513{
b873a275 514 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 515
516 /* nutrs and nutmrs are 0 based values */
517 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
518 hba->nutmrs =
519 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
520}
521
522/**
6ccf44fe
SJ		 523 * ufshcd_ready_for_uic_cmd - Check if controller is ready
524 * to accept UIC commands
7a3e97b0 525 * @hba: per adapter instance
6ccf44fe
SJ		 526 * Return true on success, else false
527 */
528static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
529{
530 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
531 return true;
532 else
533 return false;
534}
535
53b3d9c3
SJ		 536/**
537 * ufshcd_get_upmcrs - Get the power mode change request status
538 * @hba: Pointer to adapter instance
539 *
540 * This function gets the UPMCRS field of HCS register
541 * Returns value of UPMCRS field
542 */
543static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
544{
545 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
546}
547
6ccf44fe
SJ		 548/**
549 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
550 * @hba: per adapter instance
551 * @uic_cmd: UIC command
552 *
553 * Mutex must be held.
7a3e97b0
SY		 554 */
555static inline void
6ccf44fe 556ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 557{
6ccf44fe
SJ		 558 WARN_ON(hba->active_uic_cmd);
559
560 hba->active_uic_cmd = uic_cmd;
561
7a3e97b0 562 /* Write Args */
6ccf44fe
SJ		 563 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
564 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
565 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 566
567 /* Write UIC Cmd */
6ccf44fe 568 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 569 REG_UIC_COMMAND);
7a3e97b0
SY		 570}
571
6ccf44fe
SJ		 572/**
573 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
574 * @hba: per adapter instance
575 * @uic_command: UIC command
576 *
577 * Must be called with mutex held.
578 * Returns 0 only if success.
579 */
580static int
581ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
582{
583 int ret;
584 unsigned long flags;
585
586 if (wait_for_completion_timeout(&uic_cmd->done,
587 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
588 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
589 else
590 ret = -ETIMEDOUT;
591
592 spin_lock_irqsave(hba->host->host_lock, flags);
593 hba->active_uic_cmd = NULL;
594 spin_unlock_irqrestore(hba->host->host_lock, flags);
595
596 return ret;
597}
598
599/**
600 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
601 * @hba: per adapter instance
602 * @uic_cmd: UIC command
603 *
604 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
605 * with mutex held.
606 * Returns 0 only if success.
607 */
608static int
609__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
610{
611 int ret;
612 unsigned long flags;
613
614 if (!ufshcd_ready_for_uic_cmd(hba)) {
615 dev_err(hba->dev,
616 "Controller not ready to accept UIC commands\n");
617 return -EIO;
618 }
619
620 init_completion(&uic_cmd->done);
621
622 spin_lock_irqsave(hba->host->host_lock, flags);
623 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
624 spin_unlock_irqrestore(hba->host->host_lock, flags);
625
626 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
627
628 return ret;
629}
630
631/**
632 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
633 * @hba: per adapter instance
634 * @uic_cmd: UIC command
635 *
636 * Returns 0 only if success.
637 */
638static int
639ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
640{
641 int ret;
642
643 mutex_lock(&hba->uic_cmd_mutex);
644 ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
645 mutex_unlock(&hba->uic_cmd_mutex);
646
647 return ret;
648}
649
7a3e97b0
SY		 650/**
651 * ufshcd_map_sg - Map scatter-gather list to prdt
652 * @lrbp - pointer to local reference block
653 *
654 * Returns 0 in case of success, non-zero value in case of failure
655 */
656static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
657{
658 struct ufshcd_sg_entry *prd_table;
659 struct scatterlist *sg;
660 struct scsi_cmnd *cmd;
661 int sg_segments;
662 int i;
663
664 cmd = lrbp->cmd;
665 sg_segments = scsi_dma_map(cmd);
666 if (sg_segments < 0)
667 return sg_segments;
668
669 if (sg_segments) {
670 lrbp->utr_descriptor_ptr->prd_table_length =
671 cpu_to_le16((u16) (sg_segments));
672
673 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
674
675 scsi_for_each_sg(cmd, sg, sg_segments, i) {
676 prd_table[i].size =
677 cpu_to_le32(((u32) sg_dma_len(sg))-1);
678 prd_table[i].base_addr =
679 cpu_to_le32(lower_32_bits(sg->dma_address));
680 prd_table[i].upper_addr =
681 cpu_to_le32(upper_32_bits(sg->dma_address));
682 }
683 } else {
684 lrbp->utr_descriptor_ptr->prd_table_length = 0;
685 }
686
687 return 0;
688}
689
690/**
2fbd009b 691 * ufshcd_enable_intr - enable interrupts
7a3e97b0 692 * @hba: per adapter instance
2fbd009b 693 * @intrs: interrupt bits
7a3e97b0 694 */
2fbd009b 695static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 696{
2fbd009b
SJ		 697 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
698
699 if (hba->ufs_version == UFSHCI_VERSION_10) {
700 u32 rw;
701 rw = set & INTERRUPT_MASK_RW_VER_10;
702 set = rw | ((set ^ intrs) & intrs);
703 } else {
704 set |= intrs;
705 }
706
707 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
708}
709
710/**
711 * ufshcd_disable_intr - disable interrupts
712 * @hba: per adapter instance
713 * @intrs: interrupt bits
714 */
715static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
716{
717 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
718
719 if (hba->ufs_version == UFSHCI_VERSION_10) {
720 u32 rw;
721 rw = (set & INTERRUPT_MASK_RW_VER_10) &
722 ~(intrs & INTERRUPT_MASK_RW_VER_10);
723 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
724
725 } else {
726 set &= ~intrs;
7a3e97b0 727 }
2fbd009b
SJ		 728
729 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 730}
731
5a0b0cb9
SRT		 732/**
733 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
734 * descriptor according to request
735 * @lrbp: pointer to local reference block
736 * @upiu_flags: flags required in the header
737 * @cmd_dir: requests data direction
738 */
739static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
740 u32 *upiu_flags, enum dma_data_direction cmd_dir)
741{
742 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
743 u32 data_direction;
744 u32 dword_0;
745
746 if (cmd_dir == DMA_FROM_DEVICE) {
747 data_direction = UTP_DEVICE_TO_HOST;
748 *upiu_flags = UPIU_CMD_FLAGS_READ;
749 } else if (cmd_dir == DMA_TO_DEVICE) {
750 data_direction = UTP_HOST_TO_DEVICE;
751 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
752 } else {
753 data_direction = UTP_NO_DATA_TRANSFER;
754 *upiu_flags = UPIU_CMD_FLAGS_NONE;
755 }
756
757 dword_0 = data_direction | (lrbp->command_type
758 << UPIU_COMMAND_TYPE_OFFSET);
759 if (lrbp->intr_cmd)
760 dword_0 |= UTP_REQ_DESC_INT_CMD;
761
762 /* Transfer request descriptor header fields */
763 req_desc->header.dword_0 = cpu_to_le32(dword_0);
764
765 /*
766 * assigning invalid value for command status. Controller
767 * updates OCS on command completion, with the command
768 * status
769 */
770 req_desc->header.dword_2 =
771 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
772}
773
774/**
775 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
776 * for scsi commands
777 * @lrbp - local reference block pointer
778 * @upiu_flags - flags
779 */
780static
781void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
782{
783 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
784
785 /* command descriptor fields */
786 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
787 UPIU_TRANSACTION_COMMAND, upiu_flags,
788 lrbp->lun, lrbp->task_tag);
789 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
790 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
791
792 /* Total EHS length and Data segment length will be zero */
793 ucd_req_ptr->header.dword_2 = 0;
794
795 ucd_req_ptr->sc.exp_data_transfer_len =
796 cpu_to_be32(lrbp->cmd->sdb.length);
797
798 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd,
799 (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE)));
800}
801
68078d5c
DR		 802/**
803 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
804 * for query requsts
805 * @hba: UFS hba
806 * @lrbp: local reference block pointer
807 * @upiu_flags: flags
808 */
809static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
810 struct ufshcd_lrb *lrbp, u32 upiu_flags)
811{
812 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
813 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 814 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 815 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
816
817 /* Query request header */
818 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
819 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
820 lrbp->lun, lrbp->task_tag);
821 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
822 0, query->request.query_func, 0, 0);
823
824 /* Data segment length */
825 ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
826 0, 0, len >> 8, (u8)len);
827
828 /* Copy the Query Request buffer as is */
829 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
830 QUERY_OSF_SIZE);
68078d5c
DR		 831
832 /* Copy the Descriptor */
c6d4a831
DR		 833 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
834 memcpy(descp, query->descriptor, len);
835
68078d5c
DR		 836}
837
5a0b0cb9
SRT		 838static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
839{
840 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
841
842 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
843
844 /* command descriptor fields */
845 ucd_req_ptr->header.dword_0 =
846 UPIU_HEADER_DWORD(
847 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
848}
849
7a3e97b0
SY		 850/**
851 * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
5a0b0cb9 852 * @hba - per adapter instance
7a3e97b0
SY		 853 * @lrb - pointer to local reference block
854 */
5a0b0cb9 855static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 856{
7a3e97b0 857 u32 upiu_flags;
5a0b0cb9 858 int ret = 0;
7a3e97b0
SY		 859
860 switch (lrbp->command_type) {
861 case UTP_CMD_TYPE_SCSI:
5a0b0cb9
SRT		 862 if (likely(lrbp->cmd)) {
863 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
864 lrbp->cmd->sc_data_direction);
865 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
7a3e97b0 866 } else {
5a0b0cb9 867 ret = -EINVAL;
7a3e97b0 868 }
7a3e97b0
SY		 869 break;
870 case UTP_CMD_TYPE_DEV_MANAGE:
5a0b0cb9 871 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
68078d5c
DR		 872 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
873 ufshcd_prepare_utp_query_req_upiu(
874 hba, lrbp, upiu_flags);
875 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
5a0b0cb9
SRT		 876 ufshcd_prepare_utp_nop_upiu(lrbp);
877 else
878 ret = -EINVAL;
7a3e97b0
SY		 879 break;
880 case UTP_CMD_TYPE_UFS:
881 /* For UFS native command implementation */
5a0b0cb9
SRT		 882 ret = -ENOTSUPP;
883 dev_err(hba->dev, "%s: UFS native command are not supported\n",
884 __func__);
885 break;
886 default:
887 ret = -ENOTSUPP;
888 dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
889 __func__, lrbp->command_type);
7a3e97b0
SY		 890 break;
891 } /* end of switch */
5a0b0cb9
SRT		 892
893 return ret;
7a3e97b0
SY		 894}
895
896/**
897 * ufshcd_queuecommand - main entry point for SCSI requests
898 * @cmd: command from SCSI Midlayer
899 * @done: call back function
900 *
901 * Returns 0 for success, non-zero in case of failure
902 */
903static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
904{
905 struct ufshcd_lrb *lrbp;
906 struct ufs_hba *hba;
907 unsigned long flags;
908 int tag;
909 int err = 0;
910
911 hba = shost_priv(host);
912
913 tag = cmd->request->tag;
914
3441da7d
SRT		 915 spin_lock_irqsave(hba->host->host_lock, flags);
916 switch (hba->ufshcd_state) {
917 case UFSHCD_STATE_OPERATIONAL:
918 break;
919 case UFSHCD_STATE_RESET:
7a3e97b0 920 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 921 goto out_unlock;
922 case UFSHCD_STATE_ERROR:
923 set_host_byte(cmd, DID_ERROR);
924 cmd->scsi_done(cmd);
925 goto out_unlock;
926 default:
927 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
928 __func__, hba->ufshcd_state);
929 set_host_byte(cmd, DID_BAD_TARGET);
930 cmd->scsi_done(cmd);
931 goto out_unlock;
7a3e97b0 932 }
3441da7d 933 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 934
5a0b0cb9
SRT		 935 /* acquire the tag to make sure device cmds don't use it */
936 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
937 /*
938 * Dev manage command in progress, requeue the command.
939 * Requeuing the command helps in cases where the request *may*
940 * find different tag instead of waiting for dev manage command
941 * completion.
942 */
943 err = SCSI_MLQUEUE_HOST_BUSY;
944 goto out;
945 }
946
7a3e97b0
SY		 947 lrbp = &hba->lrb[tag];
948
5a0b0cb9 949 WARN_ON(lrbp->cmd);
7a3e97b0
SY		 950 lrbp->cmd = cmd;
951 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
952 lrbp->sense_buffer = cmd->sense_buffer;
953 lrbp->task_tag = tag;
954 lrbp->lun = cmd->device->lun;
5a0b0cb9 955 lrbp->intr_cmd = false;
7a3e97b0
SY		 956 lrbp->command_type = UTP_CMD_TYPE_SCSI;
957
958 /* form UPIU before issuing the command */
5a0b0cb9 959 ufshcd_compose_upiu(hba, lrbp);
7a3e97b0 960 err = ufshcd_map_sg(lrbp);
5a0b0cb9
SRT		 961 if (err) {
962 lrbp->cmd = NULL;
963 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 964 goto out;
5a0b0cb9 965 }
7a3e97b0
SY		 966
967 /* issue command to the controller */
968 spin_lock_irqsave(hba->host->host_lock, flags);
969 ufshcd_send_command(hba, tag);
3441da7d 970out_unlock:
7a3e97b0
SY		 971 spin_unlock_irqrestore(hba->host->host_lock, flags);
972out:
973 return err;
974}
975
5a0b0cb9
SRT		 976static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
977 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
978{
979 lrbp->cmd = NULL;
980 lrbp->sense_bufflen = 0;
981 lrbp->sense_buffer = NULL;
982 lrbp->task_tag = tag;
983 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
984 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
985 lrbp->intr_cmd = true; /* No interrupt aggregation */
986 hba->dev_cmd.type = cmd_type;
987
988 return ufshcd_compose_upiu(hba, lrbp);
989}
990
991static int
992ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
993{
994 int err = 0;
995 unsigned long flags;
996 u32 mask = 1 << tag;
997
998 /* clear outstanding transaction before retry */
999 spin_lock_irqsave(hba->host->host_lock, flags);
1000 ufshcd_utrl_clear(hba, tag);
1001 spin_unlock_irqrestore(hba->host->host_lock, flags);
1002
1003 /*
1004 * wait for for h/w to clear corresponding bit in door-bell.
1005 * max. wait is 1 sec.
1006 */
1007 err = ufshcd_wait_for_register(hba,
1008 REG_UTP_TRANSFER_REQ_DOOR_BELL,
1009 mask, ~mask, 1000, 1000);
1010
1011 return err;
1012}
1013
c6d4a831
DR		 1014static int
1015ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1016{
1017 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1018
1019 /* Get the UPIU response */
1020 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1021 UPIU_RSP_CODE_OFFSET;
1022 return query_res->response;
1023}
1024
5a0b0cb9
SRT		 1025/**
1026 * ufshcd_dev_cmd_completion() - handles device management command responses
1027 * @hba: per adapter instance
1028 * @lrbp: pointer to local reference block
1029 */
1030static int
1031ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1032{
1033 int resp;
1034 int err = 0;
1035
1036 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1037
1038 switch (resp) {
1039 case UPIU_TRANSACTION_NOP_IN:
1040 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1041 err = -EINVAL;
1042 dev_err(hba->dev, "%s: unexpected response %x\n",
1043 __func__, resp);
1044 }
1045 break;
68078d5c 1046 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1047 err = ufshcd_check_query_response(hba, lrbp);
1048 if (!err)
1049 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1050 break;
5a0b0cb9
SRT		 1051 case UPIU_TRANSACTION_REJECT_UPIU:
1052 /* TODO: handle Reject UPIU Response */
1053 err = -EPERM;
1054 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1055 __func__);
1056 break;
1057 default:
1058 err = -EINVAL;
1059 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1060 __func__, resp);
1061 break;
1062 }
1063
1064 return err;
1065}
1066
1067static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1068 struct ufshcd_lrb *lrbp, int max_timeout)
1069{
1070 int err = 0;
1071 unsigned long time_left;
1072 unsigned long flags;
1073
1074 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1075 msecs_to_jiffies(max_timeout));
1076
1077 spin_lock_irqsave(hba->host->host_lock, flags);
1078 hba->dev_cmd.complete = NULL;
1079 if (likely(time_left)) {
1080 err = ufshcd_get_tr_ocs(lrbp);
1081 if (!err)
1082 err = ufshcd_dev_cmd_completion(hba, lrbp);
1083 }
1084 spin_unlock_irqrestore(hba->host->host_lock, flags);
1085
1086 if (!time_left) {
1087 err = -ETIMEDOUT;
1088 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
1089 /* sucessfully cleared the command, retry if needed */
1090 err = -EAGAIN;
1091 }
1092
1093 return err;
1094}
1095
1096/**
1097 * ufshcd_get_dev_cmd_tag - Get device management command tag
1098 * @hba: per-adapter instance
1099 * @tag: pointer to variable with available slot value
1100 *
1101 * Get a free slot and lock it until device management command
1102 * completes.
1103 *
1104 * Returns false if free slot is unavailable for locking, else
1105 * return true with tag value in @tag.
1106 */
1107static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1108{
1109 int tag;
1110 bool ret = false;
1111 unsigned long tmp;
1112
1113 if (!tag_out)
1114 goto out;
1115
1116 do {
1117 tmp = ~hba->lrb_in_use;
1118 tag = find_last_bit(&tmp, hba->nutrs);
1119 if (tag >= hba->nutrs)
1120 goto out;
1121 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1122
1123 *tag_out = tag;
1124 ret = true;
1125out:
1126 return ret;
1127}
1128
1129static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1130{
1131 clear_bit_unlock(tag, &hba->lrb_in_use);
1132}
1133
1134/**
1135 * ufshcd_exec_dev_cmd - API for sending device management requests
1136 * @hba - UFS hba
1137 * @cmd_type - specifies the type (NOP, Query...)
1138 * @timeout - time in seconds
1139 *
68078d5c
DR		 1140 * NOTE: Since there is only one available tag for device management commands,
1141 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1142 */
1143static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1144 enum dev_cmd_type cmd_type, int timeout)
1145{
1146 struct ufshcd_lrb *lrbp;
1147 int err;
1148 int tag;
1149 struct completion wait;
1150 unsigned long flags;
1151
1152 /*
1153 * Get free slot, sleep if slots are unavailable.
1154 * Even though we use wait_event() which sleeps indefinitely,
1155 * the maximum wait time is bounded by SCSI request timeout.
1156 */
1157 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1158
1159 init_completion(&wait);
1160 lrbp = &hba->lrb[tag];
1161 WARN_ON(lrbp->cmd);
1162 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1163 if (unlikely(err))
1164 goto out_put_tag;
1165
1166 hba->dev_cmd.complete = &wait;
1167
1168 spin_lock_irqsave(hba->host->host_lock, flags);
1169 ufshcd_send_command(hba, tag);
1170 spin_unlock_irqrestore(hba->host->host_lock, flags);
1171
1172 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1173
1174out_put_tag:
1175 ufshcd_put_dev_cmd_tag(hba, tag);
1176 wake_up(&hba->dev_cmd.tag_wq);
1177 return err;
1178}
1179
d44a5f98
DR		 1180/**
1181 * ufshcd_init_query() - init the query response and request parameters
1182 * @hba: per-adapter instance
1183 * @request: address of the request pointer to be initialized
1184 * @response: address of the response pointer to be initialized
1185 * @opcode: operation to perform
1186 * @idn: flag idn to access
1187 * @index: LU number to access
1188 * @selector: query/flag/descriptor further identification
1189 */
1190static inline void ufshcd_init_query(struct ufs_hba *hba,
1191 struct ufs_query_req **request, struct ufs_query_res **response,
1192 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1193{
1194 *request = &hba->dev_cmd.query.request;
1195 *response = &hba->dev_cmd.query.response;
1196 memset(*request, 0, sizeof(struct ufs_query_req));
1197 memset(*response, 0, sizeof(struct ufs_query_res));
1198 (*request)->upiu_req.opcode = opcode;
1199 (*request)->upiu_req.idn = idn;
1200 (*request)->upiu_req.index = index;
1201 (*request)->upiu_req.selector = selector;
1202}
1203
68078d5c
DR		 1204/**
1205 * ufshcd_query_flag() - API function for sending flag query requests
1206 * hba: per-adapter instance
1207 * query_opcode: flag query to perform
1208 * idn: flag idn to access
1209 * flag_res: the flag value after the query request completes
1210 *
1211 * Returns 0 for success, non-zero in case of failure
1212 */
1213static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1214 enum flag_idn idn, bool *flag_res)
1215{
d44a5f98
DR		 1216 struct ufs_query_req *request = NULL;
1217 struct ufs_query_res *response = NULL;
1218 int err, index = 0, selector = 0;
68078d5c
DR		 1219
1220 BUG_ON(!hba);
1221
1222 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1223 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1224 selector);
68078d5c
DR		 1225
1226 switch (opcode) {
1227 case UPIU_QUERY_OPCODE_SET_FLAG:
1228 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1229 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1230 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1231 break;
1232 case UPIU_QUERY_OPCODE_READ_FLAG:
1233 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1234 if (!flag_res) {
1235 /* No dummy reads */
1236 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1237 __func__);
1238 err = -EINVAL;
1239 goto out_unlock;
1240 }
1241 break;
1242 default:
1243 dev_err(hba->dev,
1244 "%s: Expected query flag opcode but got = %d\n",
1245 __func__, opcode);
1246 err = -EINVAL;
1247 goto out_unlock;
1248 }
68078d5c 1249
d44a5f98 1250 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
68078d5c
DR		 1251
1252 if (err) {
1253 dev_err(hba->dev,
1254 "%s: Sending flag query for idn %d failed, err = %d\n",
1255 __func__, idn, err);
1256 goto out_unlock;
1257 }
1258
1259 if (flag_res)
e8c8e82a 1260 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1261 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1262
1263out_unlock:
1264 mutex_unlock(&hba->dev_cmd.lock);
1265 return err;
1266}
1267
66ec6d59
SRT		 1268/**
1269 * ufshcd_query_attr - API function for sending attribute requests
1270 * hba: per-adapter instance
1271 * opcode: attribute opcode
1272 * idn: attribute idn to access
1273 * index: index field
1274 * selector: selector field
1275 * attr_val: the attribute value after the query request completes
1276 *
1277 * Returns 0 for success, non-zero in case of failure
1278*/
bdbe5d2f 1279static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1280 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1281{
d44a5f98
DR		 1282 struct ufs_query_req *request = NULL;
1283 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 1284 int err;
1285
1286 BUG_ON(!hba);
1287
1288 if (!attr_val) {
1289 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1290 __func__, opcode);
1291 err = -EINVAL;
1292 goto out;
1293 }
1294
1295 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1296 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1297 selector);
66ec6d59
SRT		 1298
1299 switch (opcode) {
1300 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1301 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1302 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1303 break;
1304 case UPIU_QUERY_OPCODE_READ_ATTR:
1305 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1306 break;
1307 default:
1308 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1309 __func__, opcode);
1310 err = -EINVAL;
1311 goto out_unlock;
1312 }
1313
d44a5f98 1314 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 1315
1316 if (err) {
1317 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1318 __func__, opcode, idn, err);
1319 goto out_unlock;
1320 }
1321
e8c8e82a 1322 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1323
1324out_unlock:
1325 mutex_unlock(&hba->dev_cmd.lock);
1326out:
1327 return err;
1328}
1329
d44a5f98
DR		 1330/**
1331 * ufshcd_query_descriptor - API function for sending descriptor requests
1332 * hba: per-adapter instance
1333 * opcode: attribute opcode
1334 * idn: attribute idn to access
1335 * index: index field
1336 * selector: selector field
1337 * desc_buf: the buffer that contains the descriptor
1338 * buf_len: length parameter passed to the device
1339 *
1340 * Returns 0 for success, non-zero in case of failure.
1341 * The buf_len parameter will contain, on return, the length parameter
1342 * received on the response.
1343 */
7289f983 1344static int ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 1345 enum query_opcode opcode, enum desc_idn idn, u8 index,
1346 u8 selector, u8 *desc_buf, int *buf_len)
1347{
1348 struct ufs_query_req *request = NULL;
1349 struct ufs_query_res *response = NULL;
1350 int err;
1351
1352 BUG_ON(!hba);
1353
1354 if (!desc_buf) {
1355 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1356 __func__, opcode);
1357 err = -EINVAL;
1358 goto out;
1359 }
1360
1361 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1362 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1363 __func__, *buf_len);
1364 err = -EINVAL;
1365 goto out;
1366 }
1367
1368 mutex_lock(&hba->dev_cmd.lock);
1369 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1370 selector);
1371 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1372 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 1373
1374 switch (opcode) {
1375 case UPIU_QUERY_OPCODE_WRITE_DESC:
1376 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1377 break;
1378 case UPIU_QUERY_OPCODE_READ_DESC:
1379 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1380 break;
1381 default:
1382 dev_err(hba->dev,
1383 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1384 __func__, opcode);
1385 err = -EINVAL;
1386 goto out_unlock;
1387 }
1388
1389 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1390
1391 if (err) {
1392 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1393 __func__, opcode, idn, err);
1394 goto out_unlock;
1395 }
1396
1397 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 1398 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 1399
1400out_unlock:
1401 mutex_unlock(&hba->dev_cmd.lock);
1402out:
1403 return err;
1404}
1405
da461cec
SJ		 1406/**
1407 * ufshcd_read_desc_param - read the specified descriptor parameter
1408 * @hba: Pointer to adapter instance
1409 * @desc_id: descriptor idn value
1410 * @desc_index: descriptor index
1411 * @param_offset: offset of the parameter to read
1412 * @param_read_buf: pointer to buffer where parameter would be read
1413 * @param_size: sizeof(param_read_buf)
1414 *
1415 * Return 0 in case of success, non-zero otherwise
1416 */
1417static int ufshcd_read_desc_param(struct ufs_hba *hba,
1418 enum desc_idn desc_id,
1419 int desc_index,
1420 u32 param_offset,
1421 u8 *param_read_buf,
1422 u32 param_size)
1423{
1424 int ret;
1425 u8 *desc_buf;
1426 u32 buff_len;
1427 bool is_kmalloc = true;
1428
1429 /* safety checks */
1430 if (desc_id >= QUERY_DESC_IDN_MAX)
1431 return -EINVAL;
1432
1433 buff_len = ufs_query_desc_max_size[desc_id];
1434 if ((param_offset + param_size) > buff_len)
1435 return -EINVAL;
1436
1437 if (!param_offset && (param_size == buff_len)) {
1438 /* memory space already available to hold full descriptor */
1439 desc_buf = param_read_buf;
1440 is_kmalloc = false;
1441 } else {
1442 /* allocate memory to hold full descriptor */
1443 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1444 if (!desc_buf)
1445 return -ENOMEM;
1446 }
1447
1448 ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC,
1449 desc_id, desc_index, 0, desc_buf,
1450 &buff_len);
1451
1452 if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
1453 (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
1454 ufs_query_desc_max_size[desc_id])
1455 || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
1456 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
1457 __func__, desc_id, param_offset, buff_len, ret);
1458 if (!ret)
1459 ret = -EINVAL;
1460
1461 goto out;
1462 }
1463
1464 if (is_kmalloc)
1465 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
1466out:
1467 if (is_kmalloc)
1468 kfree(desc_buf);
1469 return ret;
1470}
1471
1472static inline int ufshcd_read_desc(struct ufs_hba *hba,
1473 enum desc_idn desc_id,
1474 int desc_index,
1475 u8 *buf,
1476 u32 size)
1477{
1478 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
1479}
1480
1481static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
1482 u8 *buf,
1483 u32 size)
1484{
1485 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
1486}
1487
1488/**
1489 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
1490 * @hba: Pointer to adapter instance
1491 * @lun: lun id
1492 * @param_offset: offset of the parameter to read
1493 * @param_read_buf: pointer to buffer where parameter would be read
1494 * @param_size: sizeof(param_read_buf)
1495 *
1496 * Return 0 in case of success, non-zero otherwise
1497 */
1498static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
1499 int lun,
1500 enum unit_desc_param param_offset,
1501 u8 *param_read_buf,
1502 u32 param_size)
1503{
1504 /*
1505 * Unit descriptors are only available for general purpose LUs (LUN id
1506 * from 0 to 7) and RPMB Well known LU.
1507 */
1508 if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
1509 return -EOPNOTSUPP;
1510
1511 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
1512 param_offset, param_read_buf, param_size);
1513}
1514
7a3e97b0
SY		 1515/**
1516 * ufshcd_memory_alloc - allocate memory for host memory space data structures
1517 * @hba: per adapter instance
1518 *
1519 * 1. Allocate DMA memory for Command Descriptor array
1520 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
1521 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
1522 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
1523 * (UTMRDL)
1524 * 4. Allocate memory for local reference block(lrb).
1525 *
1526 * Returns 0 for success, non-zero in case of failure
1527 */
1528static int ufshcd_memory_alloc(struct ufs_hba *hba)
1529{
1530 size_t utmrdl_size, utrdl_size, ucdl_size;
1531
1532 /* Allocate memory for UTP command descriptors */
1533 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 1534 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
1535 ucdl_size,
1536 &hba->ucdl_dma_addr,
1537 GFP_KERNEL);
7a3e97b0
SY		 1538
1539 /*
1540 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
1541 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
1542 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
1543 * be aligned to 128 bytes as well
1544 */
1545 if (!hba->ucdl_base_addr ||
1546 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1547 dev_err(hba->dev,
7a3e97b0
SY		 1548 "Command Descriptor Memory allocation failed\n");
1549 goto out;
1550 }
1551
1552 /*
1553 * Allocate memory for UTP Transfer descriptors
1554 * UFSHCI requires 1024 byte alignment of UTRD
1555 */
1556 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 1557 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
1558 utrdl_size,
1559 &hba->utrdl_dma_addr,
1560 GFP_KERNEL);
7a3e97b0
SY		 1561 if (!hba->utrdl_base_addr ||
1562 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1563 dev_err(hba->dev,
7a3e97b0
SY		 1564 "Transfer Descriptor Memory allocation failed\n");
1565 goto out;
1566 }
1567
1568 /*
1569 * Allocate memory for UTP Task Management descriptors
1570 * UFSHCI requires 1024 byte alignment of UTMRD
1571 */
1572 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 1573 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
1574 utmrdl_size,
1575 &hba->utmrdl_dma_addr,
1576 GFP_KERNEL);
7a3e97b0
SY		 1577 if (!hba->utmrdl_base_addr ||
1578 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1579 dev_err(hba->dev,
7a3e97b0
SY		 1580 "Task Management Descriptor Memory allocation failed\n");
1581 goto out;
1582 }
1583
1584 /* Allocate memory for local reference block */
2953f850
SJ		 1585 hba->lrb = devm_kzalloc(hba->dev,
1586 hba->nutrs * sizeof(struct ufshcd_lrb),
1587 GFP_KERNEL);
7a3e97b0 1588 if (!hba->lrb) {
3b1d0580 1589 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 1590 goto out;
1591 }
1592 return 0;
1593out:
7a3e97b0
SY		 1594 return -ENOMEM;
1595}
1596
1597/**
1598 * ufshcd_host_memory_configure - configure local reference block with
1599 * memory offsets
1600 * @hba: per adapter instance
1601 *
1602 * Configure Host memory space
1603 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
1604 * address.
1605 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
1606 * and PRDT offset.
1607 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
1608 * into local reference block.
1609 */
1610static void ufshcd_host_memory_configure(struct ufs_hba *hba)
1611{
1612 struct utp_transfer_cmd_desc *cmd_descp;
1613 struct utp_transfer_req_desc *utrdlp;
1614 dma_addr_t cmd_desc_dma_addr;
1615 dma_addr_t cmd_desc_element_addr;
1616 u16 response_offset;
1617 u16 prdt_offset;
1618 int cmd_desc_size;
1619 int i;
1620
1621 utrdlp = hba->utrdl_base_addr;
1622 cmd_descp = hba->ucdl_base_addr;
1623
1624 response_offset =
1625 offsetof(struct utp_transfer_cmd_desc, response_upiu);
1626 prdt_offset =
1627 offsetof(struct utp_transfer_cmd_desc, prd_table);
1628
1629 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
1630 cmd_desc_dma_addr = hba->ucdl_dma_addr;
1631
1632 for (i = 0; i < hba->nutrs; i++) {
1633 /* Configure UTRD with command descriptor base address */
1634 cmd_desc_element_addr =
1635 (cmd_desc_dma_addr + (cmd_desc_size * i));
1636 utrdlp[i].command_desc_base_addr_lo =
1637 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
1638 utrdlp[i].command_desc_base_addr_hi =
1639 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
1640
1641 /* Response upiu and prdt offset should be in double words */
1642 utrdlp[i].response_upiu_offset =
1643 cpu_to_le16((response_offset >> 2));
1644 utrdlp[i].prd_table_offset =
1645 cpu_to_le16((prdt_offset >> 2));
1646 utrdlp[i].response_upiu_length =
3ca316c5 1647 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0
SY		 1648
1649 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 1650 hba->lrb[i].ucd_req_ptr =
1651 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 1652 hba->lrb[i].ucd_rsp_ptr =
1653 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
1654 hba->lrb[i].ucd_prdt_ptr =
1655 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
1656 }
1657}
1658
1659/**
1660 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
1661 * @hba: per adapter instance
1662 *
1663 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
1664 * in order to initialize the Unipro link startup procedure.
1665 * Once the Unipro links are up, the device connected to the controller
1666 * is detected.
1667 *
1668 * Returns 0 on success, non-zero value on failure
1669 */
1670static int ufshcd_dme_link_startup(struct ufs_hba *hba)
1671{
6ccf44fe
SJ		 1672 struct uic_command uic_cmd = {0};
1673 int ret;
7a3e97b0 1674
6ccf44fe 1675 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 1676
6ccf44fe
SJ		 1677 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
1678 if (ret)
1679 dev_err(hba->dev,
1680 "dme-link-startup: error code %d\n", ret);
1681 return ret;
7a3e97b0
SY		 1682}
1683
12b4fdb4
SJ		 1684/**
1685 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
1686 * @hba: per adapter instance
1687 * @attr_sel: uic command argument1
1688 * @attr_set: attribute set type as uic command argument2
1689 * @mib_val: setting value as uic command argument3
1690 * @peer: indicate whether peer or local
1691 *
1692 * Returns 0 on success, non-zero value on failure
1693 */
1694int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1695 u8 attr_set, u32 mib_val, u8 peer)
1696{
1697 struct uic_command uic_cmd = {0};
1698 static const char *const action[] = {
1699 "dme-set",
1700 "dme-peer-set"
1701 };
1702 const char *set = action[!!peer];
1703 int ret;
1704
1705 uic_cmd.command = peer ?
1706 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
1707 uic_cmd.argument1 = attr_sel;
1708 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
1709 uic_cmd.argument3 = mib_val;
1710
1711 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
1712 if (ret)
1713 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
1714 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
1715
1716 return ret;
1717}
1718EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
1719
1720/**
1721 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
1722 * @hba: per adapter instance
1723 * @attr_sel: uic command argument1
1724 * @mib_val: the value of the attribute as returned by the UIC command
1725 * @peer: indicate whether peer or local
1726 *
1727 * Returns 0 on success, non-zero value on failure
1728 */
1729int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1730 u32 *mib_val, u8 peer)
1731{
1732 struct uic_command uic_cmd = {0};
1733 static const char *const action[] = {
1734 "dme-get",
1735 "dme-peer-get"
1736 };
1737 const char *get = action[!!peer];
1738 int ret;
1739
1740 uic_cmd.command = peer ?
1741 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
1742 uic_cmd.argument1 = attr_sel;
1743
1744 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
1745 if (ret) {
1746 dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n",
1747 get, UIC_GET_ATTR_ID(attr_sel), ret);
1748 goto out;
1749 }
1750
1751 if (mib_val)
1752 *mib_val = uic_cmd.argument3;
1753out:
1754 return ret;
1755}
1756EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
1757
53b3d9c3
SJ		 1758/**
1759 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
1760 * using DME_SET primitives.
1761 * @hba: per adapter instance
1762 * @mode: powr mode value
1763 *
1764 * Returns 0 on success, non-zero value on failure
1765 */
bdbe5d2f 1766static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
53b3d9c3
SJ		 1767{
1768 struct uic_command uic_cmd = {0};
1769 struct completion pwr_done;
1770 unsigned long flags;
1771 u8 status;
1772 int ret;
1773
1774 uic_cmd.command = UIC_CMD_DME_SET;
1775 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
1776 uic_cmd.argument3 = mode;
1777 init_completion(&pwr_done);
1778
1779 mutex_lock(&hba->uic_cmd_mutex);
1780
1781 spin_lock_irqsave(hba->host->host_lock, flags);
1782 hba->pwr_done = &pwr_done;
1783 spin_unlock_irqrestore(hba->host->host_lock, flags);
1784 ret = __ufshcd_send_uic_cmd(hba, &uic_cmd);
1785 if (ret) {
1786 dev_err(hba->dev,
1787 "pwr mode change with mode 0x%x uic error %d\n",
1788 mode, ret);
1789 goto out;
1790 }
1791
1792 if (!wait_for_completion_timeout(hba->pwr_done,
1793 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
1794 dev_err(hba->dev,
1795 "pwr mode change with mode 0x%x completion timeout\n",
1796 mode);
1797 ret = -ETIMEDOUT;
1798 goto out;
1799 }
1800
1801 status = ufshcd_get_upmcrs(hba);
1802 if (status != PWR_LOCAL) {
1803 dev_err(hba->dev,
1804 "pwr mode change failed, host umpcrs:0x%x\n",
1805 status);
1806 ret = (status != PWR_OK) ? status : -1;
1807 }
1808out:
1809 spin_lock_irqsave(hba->host->host_lock, flags);
1810 hba->pwr_done = NULL;
1811 spin_unlock_irqrestore(hba->host->host_lock, flags);
1812 mutex_unlock(&hba->uic_cmd_mutex);
1813 return ret;
1814}
1815
d3e89bac
SJ		 1816/**
1817 * ufshcd_config_max_pwr_mode - Set & Change power mode with
1818 * maximum capability attribute information.
1819 * @hba: per adapter instance
1820 *
1821 * Returns 0 on success, non-zero value on failure
1822 */
1823static int ufshcd_config_max_pwr_mode(struct ufs_hba *hba)
1824{
1825 enum {RX = 0, TX = 1};
1826 u32 lanes[] = {1, 1};
1827 u32 gear[] = {1, 1};
1828 u8 pwr[] = {FASTAUTO_MODE, FASTAUTO_MODE};
1829 int ret;
1830
1831 /* Get the connected lane count */
1832 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), &lanes[RX]);
1833 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), &lanes[TX]);
1834
1835 /*
1836 * First, get the maximum gears of HS speed.
1837 * If a zero value, it means there is no HSGEAR capability.
1838 * Then, get the maximum gears of PWM speed.
1839 */
1840 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &gear[RX]);
1841 if (!gear[RX]) {
1842 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), &gear[RX]);
1843 pwr[RX] = SLOWAUTO_MODE;
1844 }
1845
1846 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &gear[TX]);
1847 if (!gear[TX]) {
1848 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
1849 &gear[TX]);
1850 pwr[TX] = SLOWAUTO_MODE;
1851 }
1852
1853 /*
1854 * Configure attributes for power mode change with below.
1855 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
1856 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
1857 * - PA_HSSERIES
1858 */
1859 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), gear[RX]);
1860 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), lanes[RX]);
1861 if (pwr[RX] == FASTAUTO_MODE)
1862 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
1863
1864 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), gear[TX]);
1865 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), lanes[TX]);
1866 if (pwr[TX] == FASTAUTO_MODE)
1867 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
1868
1869 if (pwr[RX] == FASTAUTO_MODE || pwr[TX] == FASTAUTO_MODE)
1870 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), PA_HS_MODE_B);
1871
1872 ret = ufshcd_uic_change_pwr_mode(hba, pwr[RX] << 4 | pwr[TX]);
1873 if (ret)
1874 dev_err(hba->dev,
1875 "pwr_mode: power mode change failed %d\n", ret);
1876
1877 return ret;
1878}
1879
68078d5c
DR		 1880/**
1881 * ufshcd_complete_dev_init() - checks device readiness
1882 * hba: per-adapter instance
1883 *
1884 * Set fDeviceInit flag and poll until device toggles it.
1885 */
1886static int ufshcd_complete_dev_init(struct ufs_hba *hba)
1887{
1888 int i, retries, err = 0;
1889 bool flag_res = 1;
1890
1891 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1892 /* Set the fDeviceInit flag */
1893 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1894 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
1895 if (!err || err == -ETIMEDOUT)
1896 break;
1897 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
1898 }
1899 if (err) {
1900 dev_err(hba->dev,
1901 "%s setting fDeviceInit flag failed with error %d\n",
1902 __func__, err);
1903 goto out;
1904 }
1905
1906 /* poll for max. 100 iterations for fDeviceInit flag to clear */
1907 for (i = 0; i < 100 && !err && flag_res; i++) {
1908 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1909 err = ufshcd_query_flag(hba,
1910 UPIU_QUERY_OPCODE_READ_FLAG,
1911 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
1912 if (!err || err == -ETIMEDOUT)
1913 break;
1914 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__,
1915 err);
1916 }
1917 }
1918 if (err)
1919 dev_err(hba->dev,
1920 "%s reading fDeviceInit flag failed with error %d\n",
1921 __func__, err);
1922 else if (flag_res)
1923 dev_err(hba->dev,
1924 "%s fDeviceInit was not cleared by the device\n",
1925 __func__);
1926
1927out:
1928 return err;
1929}
1930
7a3e97b0
SY		 1931/**
1932 * ufshcd_make_hba_operational - Make UFS controller operational
1933 * @hba: per adapter instance
1934 *
1935 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 1936 * 1. Enable required interrupts
1937 * 2. Configure interrupt aggregation
1938 * 3. Program UTRL and UTMRL base addres
1939 * 4. Configure run-stop-registers
7a3e97b0
SY		 1940 *
1941 * Returns 0 on success, non-zero value on failure
1942 */
1943static int ufshcd_make_hba_operational(struct ufs_hba *hba)
1944{
1945 int err = 0;
1946 u32 reg;
1947
6ccf44fe
SJ		 1948 /* Enable required interrupts */
1949 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
1950
1951 /* Configure interrupt aggregation */
7d568652 1952 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
6ccf44fe
SJ		 1953
1954 /* Configure UTRL and UTMRL base address registers */
1955 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
1956 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
1957 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
1958 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
1959 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
1960 REG_UTP_TASK_REQ_LIST_BASE_L);
1961 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
1962 REG_UTP_TASK_REQ_LIST_BASE_H);
1963
7a3e97b0
SY		 1964 /*
1965 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
1966 * DEI, HEI bits must be 0
1967 */
5c0c28a8 1968 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 1969 if (!(ufshcd_get_lists_status(reg))) {
1970 ufshcd_enable_run_stop_reg(hba);
1971 } else {
3b1d0580 1972 dev_err(hba->dev,
7a3e97b0
SY		 1973 "Host controller not ready to process requests");
1974 err = -EIO;
1975 goto out;
1976 }
1977
7a3e97b0
SY		 1978out:
1979 return err;
1980}
1981
1982/**
1983 * ufshcd_hba_enable - initialize the controller
1984 * @hba: per adapter instance
1985 *
1986 * The controller resets itself and controller firmware initialization
1987 * sequence kicks off. When controller is ready it will set
1988 * the Host Controller Enable bit to 1.
1989 *
1990 * Returns 0 on success, non-zero value on failure
1991 */
1992static int ufshcd_hba_enable(struct ufs_hba *hba)
1993{
1994 int retry;
1995
1996 /*
1997 * msleep of 1 and 5 used in this function might result in msleep(20),
1998 * but it was necessary to send the UFS FPGA to reset mode during
1999 * development and testing of this driver. msleep can be changed to
2000 * mdelay and retry count can be reduced based on the controller.
2001 */
2002 if (!ufshcd_is_hba_active(hba)) {
2003
2004 /* change controller state to "reset state" */
2005 ufshcd_hba_stop(hba);
2006
2007 /*
2008 * This delay is based on the testing done with UFS host
2009 * controller FPGA. The delay can be changed based on the
2010 * host controller used.
2011 */
2012 msleep(5);
2013 }
2014
5c0c28a8
SRT		 2015 if (hba->vops && hba->vops->hce_enable_notify)
2016 hba->vops->hce_enable_notify(hba, PRE_CHANGE);
2017
7a3e97b0
SY		 2018 /* start controller initialization sequence */
2019 ufshcd_hba_start(hba);
2020
2021 /*
2022 * To initialize a UFS host controller HCE bit must be set to 1.
2023 * During initialization the HCE bit value changes from 1->0->1.
2024 * When the host controller completes initialization sequence
2025 * it sets the value of HCE bit to 1. The same HCE bit is read back
2026 * to check if the controller has completed initialization sequence.
2027 * So without this delay the value HCE = 1, set in the previous
2028 * instruction might be read back.
2029 * This delay can be changed based on the controller.
2030 */
2031 msleep(1);
2032
2033 /* wait for the host controller to complete initialization */
2034 retry = 10;
2035 while (ufshcd_is_hba_active(hba)) {
2036 if (retry) {
2037 retry--;
2038 } else {
3b1d0580 2039 dev_err(hba->dev,
7a3e97b0
SY		 2040 "Controller enable failed\n");
2041 return -EIO;
2042 }
2043 msleep(5);
2044 }
5c0c28a8
SRT		 2045
2046 if (hba->vops && hba->vops->hce_enable_notify)
2047 hba->vops->hce_enable_notify(hba, POST_CHANGE);
2048
7a3e97b0
SY		 2049 return 0;
2050}
2051
2052/**
6ccf44fe 2053 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 2054 * @hba: per adapter instance
2055 *
6ccf44fe 2056 * Returns 0 for success, non-zero in case of failure
7a3e97b0 2057 */
6ccf44fe 2058static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 2059{
6ccf44fe 2060 int ret;
7a3e97b0 2061
6ccf44fe
SJ		 2062 /* enable UIC related interrupts */
2063 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
2064
5c0c28a8
SRT		 2065 if (hba->vops && hba->vops->link_startup_notify)
2066 hba->vops->link_startup_notify(hba, PRE_CHANGE);
2067
6ccf44fe
SJ		 2068 ret = ufshcd_dme_link_startup(hba);
2069 if (ret)
2070 goto out;
2071
5c0c28a8
SRT		 2072 /* check if device is detected by inter-connect layer */
2073 if (!ufshcd_is_device_present(hba)) {
2074 dev_err(hba->dev, "%s: Device not present\n", __func__);
2075 ret = -ENXIO;
2076 goto out;
2077 }
2078
2079 /* Include any host controller configuration via UIC commands */
2080 if (hba->vops && hba->vops->link_startup_notify) {
2081 ret = hba->vops->link_startup_notify(hba, POST_CHANGE);
2082 if (ret)
2083 goto out;
2084 }
7a3e97b0 2085
5c0c28a8 2086 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 2087out:
2088 if (ret)
2089 dev_err(hba->dev, "link startup failed %d\n", ret);
2090 return ret;
7a3e97b0
SY		 2091}
2092
5a0b0cb9
SRT		 2093/**
2094 * ufshcd_verify_dev_init() - Verify device initialization
2095 * @hba: per-adapter instance
2096 *
2097 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
2098 * device Transport Protocol (UTP) layer is ready after a reset.
2099 * If the UTP layer at the device side is not initialized, it may
2100 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
2101 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
2102 */
2103static int ufshcd_verify_dev_init(struct ufs_hba *hba)
2104{
2105 int err = 0;
2106 int retries;
2107
2108 mutex_lock(&hba->dev_cmd.lock);
2109 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
2110 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
2111 NOP_OUT_TIMEOUT);
2112
2113 if (!err || err == -ETIMEDOUT)
2114 break;
2115
2116 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2117 }
2118 mutex_unlock(&hba->dev_cmd.lock);
2119
2120 if (err)
2121 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
2122 return err;
2123}
2124
7a3e97b0
SY		 2125/**
2126 * ufshcd_slave_alloc - handle initial SCSI device configurations
2127 * @sdev: pointer to SCSI device
2128 *
2129 * Returns success
2130 */
2131static int ufshcd_slave_alloc(struct scsi_device *sdev)
2132{
2133 struct ufs_hba *hba;
da461cec
SJ		 2134 u8 lun_qdepth;
2135 int ret;
7a3e97b0
SY		 2136
2137 hba = shost_priv(sdev->host);
2138 sdev->tagged_supported = 1;
2139
2140 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
2141 sdev->use_10_for_ms = 1;
2142 scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
2143
e8e7f271
SRT		 2144 /* allow SCSI layer to restart the device in case of errors */
2145 sdev->allow_restart = 1;
4264fd61 2146
b2a6c522
SRT		 2147 /* REPORT SUPPORTED OPERATION CODES is not supported */
2148 sdev->no_report_opcodes = 1;
2149
da461cec
SJ		 2150 ret = ufshcd_read_unit_desc_param(hba,
2151 sdev->lun,
2152 UNIT_DESC_PARAM_LU_Q_DEPTH,
2153 &lun_qdepth,
2154 sizeof(lun_qdepth));
2155 if (!ret || !lun_qdepth)
4264fd61 2156 /* eventually, we can figure out the real queue depth */
1b3e8956 2157 lun_qdepth = hba->nutrs;
4264fd61
SRT		 2158 else
2159 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
e8e7f271 2160
4264fd61
SRT		 2161 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
2162 __func__, lun_qdepth);
1b3e8956 2163 scsi_activate_tcq(sdev, lun_qdepth);
4264fd61 2164
7a3e97b0
SY		 2165 return 0;
2166}
2167
4264fd61
SRT		 2168/**
2169 * ufshcd_change_queue_depth - change queue depth
2170 * @sdev: pointer to SCSI device
2171 * @depth: required depth to set
2172 * @reason: reason for changing the depth
2173 *
2174 * Change queue depth according to the reason and make sure
2175 * the max. limits are not crossed.
2176 */
7289f983
SRT		 2177static int ufshcd_change_queue_depth(struct scsi_device *sdev,
2178 int depth, int reason)
4264fd61
SRT		 2179{
2180 struct ufs_hba *hba = shost_priv(sdev->host);
2181
2182 if (depth > hba->nutrs)
2183 depth = hba->nutrs;
2184
2185 switch (reason) {
2186 case SCSI_QDEPTH_DEFAULT:
2187 case SCSI_QDEPTH_RAMP_UP:
2188 if (!sdev->tagged_supported)
2189 depth = 1;
2190 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), depth);
2191 break;
2192 case SCSI_QDEPTH_QFULL:
2193 scsi_track_queue_full(sdev, depth);
2194 break;
2195 default:
2196 return -EOPNOTSUPP;
2197 }
2198
2199 return depth;
2200}
2201
eeda4749
AM		 2202/**
2203 * ufshcd_slave_configure - adjust SCSI device configurations
2204 * @sdev: pointer to SCSI device
2205 */
2206static int ufshcd_slave_configure(struct scsi_device *sdev)
2207{
2208 struct request_queue *q = sdev->request_queue;
2209
2210 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
2211 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
2212
2213 return 0;
2214}
2215
7a3e97b0
SY		 2216/**
2217 * ufshcd_slave_destroy - remove SCSI device configurations
2218 * @sdev: pointer to SCSI device
2219 */
2220static void ufshcd_slave_destroy(struct scsi_device *sdev)
2221{
2222 struct ufs_hba *hba;
2223
2224 hba = shost_priv(sdev->host);
2225 scsi_deactivate_tcq(sdev, hba->nutrs);
2226}
2227
2228/**
2229 * ufshcd_task_req_compl - handle task management request completion
2230 * @hba: per adapter instance
2231 * @index: index of the completed request
e2933132 2232 * @resp: task management service response
7a3e97b0 2233 *
e2933132 2234 * Returns non-zero value on error, zero on success
7a3e97b0 2235 */
e2933132 2236static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 2237{
2238 struct utp_task_req_desc *task_req_descp;
2239 struct utp_upiu_task_rsp *task_rsp_upiup;
2240 unsigned long flags;
2241 int ocs_value;
2242 int task_result;
2243
2244 spin_lock_irqsave(hba->host->host_lock, flags);
2245
2246 /* Clear completed tasks from outstanding_tasks */
2247 __clear_bit(index, &hba->outstanding_tasks);
2248
2249 task_req_descp = hba->utmrdl_base_addr;
2250 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
2251
2252 if (ocs_value == OCS_SUCCESS) {
2253 task_rsp_upiup = (struct utp_upiu_task_rsp *)
2254 task_req_descp[index].task_rsp_upiu;
2255 task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
2256 task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
e2933132
SRT		 2257 if (resp)
2258 *resp = (u8)task_result;
7a3e97b0 2259 } else {
e2933132
SRT		 2260 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
2261 __func__, ocs_value);
7a3e97b0
SY		 2262 }
2263 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 2264
2265 return ocs_value;
7a3e97b0
SY		 2266}
2267
7a3e97b0
SY		 2268/**
2269 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
2270 * @lrb: pointer to local reference block of completed command
2271 * @scsi_status: SCSI command status
2272 *
2273 * Returns value base on SCSI command status
2274 */
2275static inline int
2276ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
2277{
2278 int result = 0;
2279
2280 switch (scsi_status) {
7a3e97b0 2281 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 2282 ufshcd_copy_sense_data(lrbp);
2283 case SAM_STAT_GOOD:
7a3e97b0
SY		 2284 result |= DID_OK << 16 |
2285 COMMAND_COMPLETE << 8 |
1c2623c5 2286 scsi_status;
7a3e97b0
SY		 2287 break;
2288 case SAM_STAT_TASK_SET_FULL:
1c2623c5 2289 case SAM_STAT_BUSY:
7a3e97b0 2290 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 2291 ufshcd_copy_sense_data(lrbp);
2292 result |= scsi_status;
7a3e97b0
SY		 2293 break;
2294 default:
2295 result |= DID_ERROR << 16;
2296 break;
2297 } /* end of switch */
2298
2299 return result;
2300}
2301
2302/**
2303 * ufshcd_transfer_rsp_status - Get overall status of the response
2304 * @hba: per adapter instance
2305 * @lrb: pointer to local reference block of completed command
2306 *
2307 * Returns result of the command to notify SCSI midlayer
2308 */
2309static inline int
2310ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2311{
2312 int result = 0;
2313 int scsi_status;
2314 int ocs;
2315
2316 /* overall command status of utrd */
2317 ocs = ufshcd_get_tr_ocs(lrbp);
2318
2319 switch (ocs) {
2320 case OCS_SUCCESS:
5a0b0cb9 2321 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 2322
5a0b0cb9
SRT		 2323 switch (result) {
2324 case UPIU_TRANSACTION_RESPONSE:
2325 /*
2326 * get the response UPIU result to extract
2327 * the SCSI command status
2328 */
2329 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
2330
2331 /*
2332 * get the result based on SCSI status response
2333 * to notify the SCSI midlayer of the command status
2334 */
2335 scsi_status = result & MASK_SCSI_STATUS;
2336 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59
SRT		 2337
2338 if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
2339 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 2340 break;
2341 case UPIU_TRANSACTION_REJECT_UPIU:
2342 /* TODO: handle Reject UPIU Response */
2343 result = DID_ERROR << 16;
3b1d0580 2344 dev_err(hba->dev,
5a0b0cb9
SRT		 2345 "Reject UPIU not fully implemented\n");
2346 break;
2347 default:
2348 result = DID_ERROR << 16;
2349 dev_err(hba->dev,
2350 "Unexpected request response code = %x\n",
2351 result);
7a3e97b0
SY		 2352 break;
2353 }
7a3e97b0
SY		 2354 break;
2355 case OCS_ABORTED:
2356 result |= DID_ABORT << 16;
2357 break;
e8e7f271
SRT		 2358 case OCS_INVALID_COMMAND_STATUS:
2359 result |= DID_REQUEUE << 16;
2360 break;
7a3e97b0
SY		 2361 case OCS_INVALID_CMD_TABLE_ATTR:
2362 case OCS_INVALID_PRDT_ATTR:
2363 case OCS_MISMATCH_DATA_BUF_SIZE:
2364 case OCS_MISMATCH_RESP_UPIU_SIZE:
2365 case OCS_PEER_COMM_FAILURE:
2366 case OCS_FATAL_ERROR:
2367 default:
2368 result |= DID_ERROR << 16;
3b1d0580 2369 dev_err(hba->dev,
7a3e97b0
SY		 2370 "OCS error from controller = %x\n", ocs);
2371 break;
2372 } /* end of switch */
2373
2374 return result;
2375}
2376
6ccf44fe
SJ		 2377/**
2378 * ufshcd_uic_cmd_compl - handle completion of uic command
2379 * @hba: per adapter instance
53b3d9c3 2380 * @intr_status: interrupt status generated by the controller
6ccf44fe 2381 */
53b3d9c3 2382static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 2383{
53b3d9c3 2384 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 2385 hba->active_uic_cmd->argument2 |=
2386 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 2387 hba->active_uic_cmd->argument3 =
2388 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 2389 complete(&hba->active_uic_cmd->done);
2390 }
53b3d9c3
SJ		 2391
2392 if ((intr_status & UIC_POWER_MODE) && hba->pwr_done)
2393 complete(hba->pwr_done);
6ccf44fe
SJ		 2394}
2395
7a3e97b0
SY		 2396/**
2397 * ufshcd_transfer_req_compl - handle SCSI and query command completion
2398 * @hba: per adapter instance
2399 */
2400static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
2401{
5a0b0cb9
SRT		 2402 struct ufshcd_lrb *lrbp;
2403 struct scsi_cmnd *cmd;
7a3e97b0
SY		 2404 unsigned long completed_reqs;
2405 u32 tr_doorbell;
2406 int result;
2407 int index;
e9d501b1
DR		 2408
2409 /* Resetting interrupt aggregation counters first and reading the
2410 * DOOR_BELL afterward allows us to handle all the completed requests.
2411 * In order to prevent other interrupts starvation the DB is read once
2412 * after reset. The down side of this solution is the possibility of
2413 * false interrupt if device completes another request after resetting
2414 * aggregation and before reading the DB.
2415 */
2416 ufshcd_reset_intr_aggr(hba);
7a3e97b0 2417
b873a275 2418 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 2419 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
2420
e9d501b1
DR		 2421 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
2422 lrbp = &hba->lrb[index];
2423 cmd = lrbp->cmd;
2424 if (cmd) {
2425 result = ufshcd_transfer_rsp_status(hba, lrbp);
2426 scsi_dma_unmap(cmd);
2427 cmd->result = result;
2428 /* Mark completed command as NULL in LRB */
2429 lrbp->cmd = NULL;
2430 clear_bit_unlock(index, &hba->lrb_in_use);
2431 /* Do not touch lrbp after scsi done */
2432 cmd->scsi_done(cmd);
2433 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) {
2434 if (hba->dev_cmd.complete)
2435 complete(hba->dev_cmd.complete);
2436 }
2437 }
7a3e97b0
SY		 2438
2439 /* clear corresponding bits of completed commands */
2440 hba->outstanding_reqs ^= completed_reqs;
2441
5a0b0cb9
SRT		 2442 /* we might have free'd some tags above */
2443 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 2444}
2445
66ec6d59
SRT		 2446/**
2447 * ufshcd_disable_ee - disable exception event
2448 * @hba: per-adapter instance
2449 * @mask: exception event to disable
2450 *
2451 * Disables exception event in the device so that the EVENT_ALERT
2452 * bit is not set.
2453 *
2454 * Returns zero on success, non-zero error value on failure.
2455 */
2456static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
2457{
2458 int err = 0;
2459 u32 val;
2460
2461 if (!(hba->ee_ctrl_mask & mask))
2462 goto out;
2463
2464 val = hba->ee_ctrl_mask & ~mask;
2465 val &= 0xFFFF; /* 2 bytes */
2466 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
2467 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
2468 if (!err)
2469 hba->ee_ctrl_mask &= ~mask;
2470out:
2471 return err;
2472}
2473
2474/**
2475 * ufshcd_enable_ee - enable exception event
2476 * @hba: per-adapter instance
2477 * @mask: exception event to enable
2478 *
2479 * Enable corresponding exception event in the device to allow
2480 * device to alert host in critical scenarios.
2481 *
2482 * Returns zero on success, non-zero error value on failure.
2483 */
2484static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
2485{
2486 int err = 0;
2487 u32 val;
2488
2489 if (hba->ee_ctrl_mask & mask)
2490 goto out;
2491
2492 val = hba->ee_ctrl_mask | mask;
2493 val &= 0xFFFF; /* 2 bytes */
2494 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
2495 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
2496 if (!err)
2497 hba->ee_ctrl_mask |= mask;
2498out:
2499 return err;
2500}
2501
2502/**
2503 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
2504 * @hba: per-adapter instance
2505 *
2506 * Allow device to manage background operations on its own. Enabling
2507 * this might lead to inconsistent latencies during normal data transfers
2508 * as the device is allowed to manage its own way of handling background
2509 * operations.
2510 *
2511 * Returns zero on success, non-zero on failure.
2512 */
2513static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
2514{
2515 int err = 0;
2516
2517 if (hba->auto_bkops_enabled)
2518 goto out;
2519
2520 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2521 QUERY_FLAG_IDN_BKOPS_EN, NULL);
2522 if (err) {
2523 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
2524 __func__, err);
2525 goto out;
2526 }
2527
2528 hba->auto_bkops_enabled = true;
2529
2530 /* No need of URGENT_BKOPS exception from the device */
2531 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
2532 if (err)
2533 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
2534 __func__, err);
2535out:
2536 return err;
2537}
2538
2539/**
2540 * ufshcd_disable_auto_bkops - block device in doing background operations
2541 * @hba: per-adapter instance
2542 *
2543 * Disabling background operations improves command response latency but
2544 * has drawback of device moving into critical state where the device is
2545 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
2546 * host is idle so that BKOPS are managed effectively without any negative
2547 * impacts.
2548 *
2549 * Returns zero on success, non-zero on failure.
2550 */
2551static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
2552{
2553 int err = 0;
2554
2555 if (!hba->auto_bkops_enabled)
2556 goto out;
2557
2558 /*
2559 * If host assisted BKOPs is to be enabled, make sure
2560 * urgent bkops exception is allowed.
2561 */
2562 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
2563 if (err) {
2564 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
2565 __func__, err);
2566 goto out;
2567 }
2568
2569 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
2570 QUERY_FLAG_IDN_BKOPS_EN, NULL);
2571 if (err) {
2572 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
2573 __func__, err);
2574 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
2575 goto out;
2576 }
2577
2578 hba->auto_bkops_enabled = false;
2579out:
2580 return err;
2581}
2582
2583/**
2584 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
2585 * @hba: per adapter instance
2586 *
2587 * After a device reset the device may toggle the BKOPS_EN flag
2588 * to default value. The s/w tracking variables should be updated
2589 * as well. Do this by forcing enable of auto bkops.
2590 */
2591static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
2592{
2593 hba->auto_bkops_enabled = false;
2594 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
2595 ufshcd_enable_auto_bkops(hba);
2596}
2597
2598static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
2599{
2600 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
2601 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
2602}
2603
2604/**
2605 * ufshcd_urgent_bkops - handle urgent bkops exception event
2606 * @hba: per-adapter instance
2607 *
2608 * Enable fBackgroundOpsEn flag in the device to permit background
2609 * operations.
2610 */
2611static int ufshcd_urgent_bkops(struct ufs_hba *hba)
2612{
2613 int err;
2614 u32 status = 0;
2615
2616 err = ufshcd_get_bkops_status(hba, &status);
2617 if (err) {
2618 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
2619 __func__, err);
2620 goto out;
2621 }
2622
2623 status = status & 0xF;
2624
2625 /* handle only if status indicates performance impact or critical */
2626 if (status >= BKOPS_STATUS_PERF_IMPACT)
2627 err = ufshcd_enable_auto_bkops(hba);
2628out:
2629 return err;
2630}
2631
2632static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
2633{
2634 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
2635 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
2636}
2637
2638/**
2639 * ufshcd_exception_event_handler - handle exceptions raised by device
2640 * @work: pointer to work data
2641 *
2642 * Read bExceptionEventStatus attribute from the device and handle the
2643 * exception event accordingly.
2644 */
2645static void ufshcd_exception_event_handler(struct work_struct *work)
2646{
2647 struct ufs_hba *hba;
2648 int err;
2649 u32 status = 0;
2650 hba = container_of(work, struct ufs_hba, eeh_work);
2651
62694735 2652 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 2653 err = ufshcd_get_ee_status(hba, &status);
2654 if (err) {
2655 dev_err(hba->dev, "%s: failed to get exception status %d\n",
2656 __func__, err);
2657 goto out;
2658 }
2659
2660 status &= hba->ee_ctrl_mask;
2661 if (status & MASK_EE_URGENT_BKOPS) {
2662 err = ufshcd_urgent_bkops(hba);
2663 if (err)
2664 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
2665 __func__, err);
2666 }
2667out:
62694735 2668 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 2669 return;
2670}
2671
7a3e97b0 2672/**
e8e7f271
SRT		 2673 * ufshcd_err_handler - handle UFS errors that require s/w attention
2674 * @work: pointer to work structure
7a3e97b0 2675 */
e8e7f271 2676static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 2677{
2678 struct ufs_hba *hba;
e8e7f271
SRT		 2679 unsigned long flags;
2680 u32 err_xfer = 0;
2681 u32 err_tm = 0;
2682 int err = 0;
2683 int tag;
2684
2685 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 2686
62694735 2687 pm_runtime_get_sync(hba->dev);
e8e7f271
SRT		 2688
2689 spin_lock_irqsave(hba->host->host_lock, flags);
2690 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
2691 spin_unlock_irqrestore(hba->host->host_lock, flags);
2692 goto out;
2693 }
2694
2695 hba->ufshcd_state = UFSHCD_STATE_RESET;
2696 ufshcd_set_eh_in_progress(hba);
2697
2698 /* Complete requests that have door-bell cleared by h/w */
2699 ufshcd_transfer_req_compl(hba);
2700 ufshcd_tmc_handler(hba);
2701 spin_unlock_irqrestore(hba->host->host_lock, flags);
2702
2703 /* Clear pending transfer requests */
2704 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
2705 if (ufshcd_clear_cmd(hba, tag))
2706 err_xfer |= 1 << tag;
2707
2708 /* Clear pending task management requests */
2709 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs)
2710 if (ufshcd_clear_tm_cmd(hba, tag))
2711 err_tm |= 1 << tag;
2712
2713 /* Complete the requests that are cleared by s/w */
2714 spin_lock_irqsave(hba->host->host_lock, flags);
2715 ufshcd_transfer_req_compl(hba);
2716 ufshcd_tmc_handler(hba);
2717 spin_unlock_irqrestore(hba->host->host_lock, flags);
2718
2719 /* Fatal errors need reset */
2720 if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) ||
2721 ((hba->saved_err & UIC_ERROR) &&
2722 (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) {
2723 err = ufshcd_reset_and_restore(hba);
2724 if (err) {
2725 dev_err(hba->dev, "%s: reset and restore failed\n",
2726 __func__);
2727 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2728 }
2729 /*
2730 * Inform scsi mid-layer that we did reset and allow to handle
2731 * Unit Attention properly.
2732 */
2733 scsi_report_bus_reset(hba->host, 0);
2734 hba->saved_err = 0;
2735 hba->saved_uic_err = 0;
2736 }
2737 ufshcd_clear_eh_in_progress(hba);
2738
2739out:
2740 scsi_unblock_requests(hba->host);
62694735 2741 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 2742}
2743
2744/**
e8e7f271
SRT		 2745 * ufshcd_update_uic_error - check and set fatal UIC error flags.
2746 * @hba: per-adapter instance
7a3e97b0 2747 */
e8e7f271 2748static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 2749{
2750 u32 reg;
2751
e8e7f271
SRT		 2752 /* PA_INIT_ERROR is fatal and needs UIC reset */
2753 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
2754 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
2755 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
2756
2757 /* UIC NL/TL/DME errors needs software retry */
2758 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
2759 if (reg)
2760 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
2761
2762 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
2763 if (reg)
2764 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
2765
2766 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
2767 if (reg)
2768 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
2769
2770 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
2771 __func__, hba->uic_error);
2772}
2773
2774/**
2775 * ufshcd_check_errors - Check for errors that need s/w attention
2776 * @hba: per-adapter instance
2777 */
2778static void ufshcd_check_errors(struct ufs_hba *hba)
2779{
2780 bool queue_eh_work = false;
2781
7a3e97b0 2782 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 2783 queue_eh_work = true;
7a3e97b0
SY		 2784
2785 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 2786 hba->uic_error = 0;
2787 ufshcd_update_uic_error(hba);
2788 if (hba->uic_error)
2789 queue_eh_work = true;
7a3e97b0 2790 }
e8e7f271
SRT		 2791
2792 if (queue_eh_work) {
2793 /* handle fatal errors only when link is functional */
2794 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
2795 /* block commands from scsi mid-layer */
2796 scsi_block_requests(hba->host);
2797
2798 /* transfer error masks to sticky bits */
2799 hba->saved_err |= hba->errors;
2800 hba->saved_uic_err |= hba->uic_error;
2801
2802 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2803 schedule_work(&hba->eh_work);
2804 }
3441da7d 2805 }
e8e7f271
SRT		 2806 /*
2807 * if (!queue_eh_work) -
2808 * Other errors are either non-fatal where host recovers
2809 * itself without s/w intervention or errors that will be
2810 * handled by the SCSI core layer.
2811 */
7a3e97b0
SY		 2812}
2813
2814/**
2815 * ufshcd_tmc_handler - handle task management function completion
2816 * @hba: per adapter instance
2817 */
2818static void ufshcd_tmc_handler(struct ufs_hba *hba)
2819{
2820 u32 tm_doorbell;
2821
b873a275 2822 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 2823 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 2824 wake_up(&hba->tm_wq);
7a3e97b0
SY		 2825}
2826
2827/**
2828 * ufshcd_sl_intr - Interrupt service routine
2829 * @hba: per adapter instance
2830 * @intr_status: contains interrupts generated by the controller
2831 */
2832static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
2833{
2834 hba->errors = UFSHCD_ERROR_MASK & intr_status;
2835 if (hba->errors)
e8e7f271 2836 ufshcd_check_errors(hba);
7a3e97b0 2837
53b3d9c3
SJ		 2838 if (intr_status & UFSHCD_UIC_MASK)
2839 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 2840
2841 if (intr_status & UTP_TASK_REQ_COMPL)
2842 ufshcd_tmc_handler(hba);
2843
2844 if (intr_status & UTP_TRANSFER_REQ_COMPL)
2845 ufshcd_transfer_req_compl(hba);
2846}
2847
2848/**
2849 * ufshcd_intr - Main interrupt service routine
2850 * @irq: irq number
2851 * @__hba: pointer to adapter instance
2852 *
2853 * Returns IRQ_HANDLED - If interrupt is valid
2854 * IRQ_NONE - If invalid interrupt
2855 */
2856static irqreturn_t ufshcd_intr(int irq, void *__hba)
2857{
2858 u32 intr_status;
2859 irqreturn_t retval = IRQ_NONE;
2860 struct ufs_hba *hba = __hba;
2861
2862 spin_lock(hba->host->host_lock);
b873a275 2863 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0
SY		 2864
2865 if (intr_status) {
261ea452 2866 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
7a3e97b0 2867 ufshcd_sl_intr(hba, intr_status);
7a3e97b0
SY		 2868 retval = IRQ_HANDLED;
2869 }
2870 spin_unlock(hba->host->host_lock);
2871 return retval;
2872}
2873
e2933132
SRT		 2874static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
2875{
2876 int err = 0;
2877 u32 mask = 1 << tag;
2878 unsigned long flags;
2879
2880 if (!test_bit(tag, &hba->outstanding_tasks))
2881 goto out;
2882
2883 spin_lock_irqsave(hba->host->host_lock, flags);
2884 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
2885 spin_unlock_irqrestore(hba->host->host_lock, flags);
2886
2887 /* poll for max. 1 sec to clear door bell register by h/w */
2888 err = ufshcd_wait_for_register(hba,
2889 REG_UTP_TASK_REQ_DOOR_BELL,
2890 mask, 0, 1000, 1000);
2891out:
2892 return err;
2893}
2894
7a3e97b0
SY		 2895/**
2896 * ufshcd_issue_tm_cmd - issues task management commands to controller
2897 * @hba: per adapter instance
e2933132
SRT		 2898 * @lun_id: LUN ID to which TM command is sent
2899 * @task_id: task ID to which the TM command is applicable
2900 * @tm_function: task management function opcode
2901 * @tm_response: task management service response return value
7a3e97b0 2902 *
e2933132 2903 * Returns non-zero value on error, zero on success.
7a3e97b0 2904 */
e2933132
SRT		 2905static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
2906 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 2907{
2908 struct utp_task_req_desc *task_req_descp;
2909 struct utp_upiu_task_req *task_req_upiup;
2910 struct Scsi_Host *host;
2911 unsigned long flags;
e2933132 2912 int free_slot;
7a3e97b0 2913 int err;
e2933132 2914 int task_tag;
7a3e97b0
SY		 2915
2916 host = hba->host;
2917
e2933132
SRT		 2918 /*
2919 * Get free slot, sleep if slots are unavailable.
2920 * Even though we use wait_event() which sleeps indefinitely,
2921 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
2922 */
2923 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
7a3e97b0 2924
e2933132 2925 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 2926 task_req_descp = hba->utmrdl_base_addr;
2927 task_req_descp += free_slot;
2928
2929 /* Configure task request descriptor */
2930 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
2931 task_req_descp->header.dword_2 =
2932 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2933
2934 /* Configure task request UPIU */
2935 task_req_upiup =
2936 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 2937 task_tag = hba->nutrs + free_slot;
7a3e97b0 2938 task_req_upiup->header.dword_0 =
5a0b0cb9 2939 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 2940 lun_id, task_tag);
7a3e97b0 2941 task_req_upiup->header.dword_1 =
5a0b0cb9 2942 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
7a3e97b0 2943
e2933132
SRT		 2944 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
2945 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0
SY		 2946
2947 /* send command to the controller */
2948 __set_bit(free_slot, &hba->outstanding_tasks);
b873a275 2949 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0
SY		 2950
2951 spin_unlock_irqrestore(host->host_lock, flags);
2952
2953 /* wait until the task management command is completed */
e2933132
SRT		 2954 err = wait_event_timeout(hba->tm_wq,
2955 test_bit(free_slot, &hba->tm_condition),
2956 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 2957 if (!err) {
e2933132
SRT		 2958 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
2959 __func__, tm_function);
2960 if (ufshcd_clear_tm_cmd(hba, free_slot))
2961 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
2962 __func__, free_slot);
2963 err = -ETIMEDOUT;
2964 } else {
2965 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 2966 }
e2933132 2967
7a3e97b0 2968 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 2969 ufshcd_put_tm_slot(hba, free_slot);
2970 wake_up(&hba->tm_tag_wq);
2971
7a3e97b0
SY		 2972 return err;
2973}
2974
2975/**
3441da7d
SRT		 2976 * ufshcd_eh_device_reset_handler - device reset handler registered to
2977 * scsi layer.
7a3e97b0
SY		 2978 * @cmd: SCSI command pointer
2979 *
2980 * Returns SUCCESS/FAILED
2981 */
3441da7d 2982static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 2983{
2984 struct Scsi_Host *host;
2985 struct ufs_hba *hba;
2986 unsigned int tag;
2987 u32 pos;
2988 int err;
e2933132
SRT		 2989 u8 resp = 0xF;
2990 struct ufshcd_lrb *lrbp;
3441da7d 2991 unsigned long flags;
7a3e97b0
SY		 2992
2993 host = cmd->device->host;
2994 hba = shost_priv(host);
2995 tag = cmd->request->tag;
2996
e2933132
SRT		 2997 lrbp = &hba->lrb[tag];
2998 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
2999 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 3000 if (!err)
3001 err = resp;
7a3e97b0 3002 goto out;
e2933132 3003 }
7a3e97b0 3004
3441da7d
SRT		 3005 /* clear the commands that were pending for corresponding LUN */
3006 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
3007 if (hba->lrb[pos].lun == lrbp->lun) {
3008 err = ufshcd_clear_cmd(hba, pos);
3009 if (err)
3010 break;
7a3e97b0 3011 }
3441da7d
SRT		 3012 }
3013 spin_lock_irqsave(host->host_lock, flags);
3014 ufshcd_transfer_req_compl(hba);
3015 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 3016out:
3441da7d
SRT		 3017 if (!err) {
3018 err = SUCCESS;
3019 } else {
3020 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3021 err = FAILED;
3022 }
7a3e97b0
SY		 3023 return err;
3024}
3025
7a3e97b0
SY		 3026/**
3027 * ufshcd_abort - abort a specific command
3028 * @cmd: SCSI command pointer
3029 *
f20810d8
SRT		 3030 * Abort the pending command in device by sending UFS_ABORT_TASK task management
3031 * command, and in host controller by clearing the door-bell register. There can
3032 * be race between controller sending the command to the device while abort is
3033 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
3034 * really issued and then try to abort it.
3035 *
7a3e97b0
SY		 3036 * Returns SUCCESS/FAILED
3037 */
3038static int ufshcd_abort(struct scsi_cmnd *cmd)
3039{
3040 struct Scsi_Host *host;
3041 struct ufs_hba *hba;
3042 unsigned long flags;
3043 unsigned int tag;
f20810d8
SRT		 3044 int err = 0;
3045 int poll_cnt;
e2933132
SRT		 3046 u8 resp = 0xF;
3047 struct ufshcd_lrb *lrbp;
e9d501b1 3048 u32 reg;
7a3e97b0
SY		 3049
3050 host = cmd->device->host;
3051 hba = shost_priv(host);
3052 tag = cmd->request->tag;
3053
f20810d8
SRT		 3054 /* If command is already aborted/completed, return SUCCESS */
3055 if (!(test_bit(tag, &hba->outstanding_reqs)))
3056 goto out;
7a3e97b0 3057
e9d501b1
DR		 3058 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3059 if (!(reg & (1 << tag))) {
3060 dev_err(hba->dev,
3061 "%s: cmd was completed, but without a notifying intr, tag = %d",
3062 __func__, tag);
3063 }
3064
f20810d8
SRT		 3065 lrbp = &hba->lrb[tag];
3066 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
3067 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3068 UFS_QUERY_TASK, &resp);
3069 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
3070 /* cmd pending in the device */
3071 break;
3072 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3073 /*
3074 * cmd not pending in the device, check if it is
3075 * in transition.
3076 */
3077 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3078 if (reg & (1 << tag)) {
3079 /* sleep for max. 200us to stabilize */
3080 usleep_range(100, 200);
3081 continue;
3082 }
3083 /* command completed already */
3084 goto out;
3085 } else {
3086 if (!err)
3087 err = resp; /* service response error */
3088 goto out;
3089 }
3090 }
3091
3092 if (!poll_cnt) {
3093 err = -EBUSY;
7a3e97b0
SY		 3094 goto out;
3095 }
7a3e97b0 3096
e2933132
SRT		 3097 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3098 UFS_ABORT_TASK, &resp);
3099 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3100 if (!err)
3101 err = resp; /* service response error */
7a3e97b0 3102 goto out;
e2933132 3103 }
7a3e97b0 3104
f20810d8
SRT		 3105 err = ufshcd_clear_cmd(hba, tag);
3106 if (err)
3107 goto out;
3108
7a3e97b0
SY		 3109 scsi_dma_unmap(cmd);
3110
3111 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 3112 __clear_bit(tag, &hba->outstanding_reqs);
3113 hba->lrb[tag].cmd = NULL;
3114 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 3115
3116 clear_bit_unlock(tag, &hba->lrb_in_use);
3117 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0 3118out:
f20810d8
SRT		 3119 if (!err) {
3120 err = SUCCESS;
3121 } else {
3122 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3123 err = FAILED;
3124 }
3125
7a3e97b0
SY		 3126 return err;
3127}
3128
3441da7d
SRT		 3129/**
3130 * ufshcd_host_reset_and_restore - reset and restore host controller
3131 * @hba: per-adapter instance
3132 *
3133 * Note that host controller reset may issue DME_RESET to
3134 * local and remote (device) Uni-Pro stack and the attributes
3135 * are reset to default state.
3136 *
3137 * Returns zero on success, non-zero on failure
3138 */
3139static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
3140{
3141 int err;
3142 async_cookie_t cookie;
3143 unsigned long flags;
3144
3145 /* Reset the host controller */
3146 spin_lock_irqsave(hba->host->host_lock, flags);
3147 ufshcd_hba_stop(hba);
3148 spin_unlock_irqrestore(hba->host->host_lock, flags);
3149
3150 err = ufshcd_hba_enable(hba);
3151 if (err)
3152 goto out;
3153
3154 /* Establish the link again and restore the device */
3155 cookie = async_schedule(ufshcd_async_scan, hba);
3156 /* wait for async scan to be completed */
3157 async_synchronize_cookie(++cookie);
3158 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
3159 err = -EIO;
3160out:
3161 if (err)
3162 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
3163
3164 return err;
3165}
3166
3167/**
3168 * ufshcd_reset_and_restore - reset and re-initialize host/device
3169 * @hba: per-adapter instance
3170 *
3171 * Reset and recover device, host and re-establish link. This
3172 * is helpful to recover the communication in fatal error conditions.
3173 *
3174 * Returns zero on success, non-zero on failure
3175 */
3176static int ufshcd_reset_and_restore(struct ufs_hba *hba)
3177{
3178 int err = 0;
3179 unsigned long flags;
3180
3181 err = ufshcd_host_reset_and_restore(hba);
3182
3183 /*
3184 * After reset the door-bell might be cleared, complete
3185 * outstanding requests in s/w here.
3186 */
3187 spin_lock_irqsave(hba->host->host_lock, flags);
3188 ufshcd_transfer_req_compl(hba);
3189 ufshcd_tmc_handler(hba);
3190 spin_unlock_irqrestore(hba->host->host_lock, flags);
3191
3192 return err;
3193}
3194
3195/**
3196 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
3197 * @cmd - SCSI command pointer
3198 *
3199 * Returns SUCCESS/FAILED
3200 */
3201static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
3202{
3203 int err;
3204 unsigned long flags;
3205 struct ufs_hba *hba;
3206
3207 hba = shost_priv(cmd->device->host);
3208
3209 /*
3210 * Check if there is any race with fatal error handling.
3211 * If so, wait for it to complete. Even though fatal error
3212 * handling does reset and restore in some cases, don't assume
3213 * anything out of it. We are just avoiding race here.
3214 */
3215 do {
3216 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 3217 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 3218 hba->ufshcd_state == UFSHCD_STATE_RESET))
3219 break;
3220 spin_unlock_irqrestore(hba->host->host_lock, flags);
3221 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 3222 flush_work(&hba->eh_work);
3441da7d
SRT		 3223 } while (1);
3224
3225 hba->ufshcd_state = UFSHCD_STATE_RESET;
3226 ufshcd_set_eh_in_progress(hba);
3227 spin_unlock_irqrestore(hba->host->host_lock, flags);
3228
3229 err = ufshcd_reset_and_restore(hba);
3230
3231 spin_lock_irqsave(hba->host->host_lock, flags);
3232 if (!err) {
3233 err = SUCCESS;
3234 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
3235 } else {
3236 err = FAILED;
3237 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3238 }
3239 ufshcd_clear_eh_in_progress(hba);
3240 spin_unlock_irqrestore(hba->host->host_lock, flags);
3241
3242 return err;
3243}
3244
6ccf44fe
SJ		 3245/**
3246 * ufshcd_async_scan - asynchronous execution for link startup
3247 * @data: data pointer to pass to this function
3248 * @cookie: cookie data
3249 */
3250static void ufshcd_async_scan(void *data, async_cookie_t cookie)
3251{
3252 struct ufs_hba *hba = (struct ufs_hba *)data;
3253 int ret;
3254
3255 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 3256 if (ret)
3257 goto out;
3258
d3e89bac
SJ		 3259 ufshcd_config_max_pwr_mode(hba);
3260
5a0b0cb9
SRT		 3261 ret = ufshcd_verify_dev_init(hba);
3262 if (ret)
3263 goto out;
68078d5c
DR		 3264
3265 ret = ufshcd_complete_dev_init(hba);
3266 if (ret)
3267 goto out;
5a0b0cb9 3268
66ec6d59 3269 ufshcd_force_reset_auto_bkops(hba);
3441da7d
SRT		 3270 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
3271
3272 /* If we are in error handling context no need to scan the host */
3273 if (!ufshcd_eh_in_progress(hba)) {
3274 scsi_scan_host(hba->host);
3275 pm_runtime_put_sync(hba->dev);
3276 }
5a0b0cb9
SRT		 3277out:
3278 return;
6ccf44fe
SJ		 3279}
3280
7a3e97b0
SY		 3281static struct scsi_host_template ufshcd_driver_template = {
3282 .module = THIS_MODULE,
3283 .name = UFSHCD,
3284 .proc_name = UFSHCD,
3285 .queuecommand = ufshcd_queuecommand,
3286 .slave_alloc = ufshcd_slave_alloc,
eeda4749 3287 .slave_configure = ufshcd_slave_configure,
7a3e97b0 3288 .slave_destroy = ufshcd_slave_destroy,
4264fd61 3289 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 3290 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 3291 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
3292 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 3293 .this_id = -1,
3294 .sg_tablesize = SG_ALL,
3295 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
3296 .can_queue = UFSHCD_CAN_QUEUE,
3297};
3298
aa497613
SRT		 3299static int ufshcd_config_vreg(struct device *dev,
3300 struct ufs_vreg *vreg, bool on)
3301{
3302 int ret = 0;
3303 struct regulator *reg = vreg->reg;
3304 const char *name = vreg->name;
3305 int min_uV, uA_load;
3306
3307 BUG_ON(!vreg);
3308
3309 if (regulator_count_voltages(reg) > 0) {
3310 min_uV = on ? vreg->min_uV : 0;
3311 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
3312 if (ret) {
3313 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
3314 __func__, name, ret);
3315 goto out;
3316 }
3317
3318 uA_load = on ? vreg->max_uA : 0;
3319 ret = regulator_set_optimum_mode(reg, uA_load);
3320 if (ret >= 0) {
3321 /*
3322 * regulator_set_optimum_mode() returns new regulator
3323 * mode upon success.
3324 */
3325 ret = 0;
3326 } else {
3327 dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
3328 __func__, name, uA_load, ret);
3329 goto out;
3330 }
3331 }
3332out:
3333 return ret;
3334}
3335
3336static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
3337{
3338 int ret = 0;
3339
3340 if (!vreg || vreg->enabled)
3341 goto out;
3342
3343 ret = ufshcd_config_vreg(dev, vreg, true);
3344 if (!ret)
3345 ret = regulator_enable(vreg->reg);
3346
3347 if (!ret)
3348 vreg->enabled = true;
3349 else
3350 dev_err(dev, "%s: %s enable failed, err=%d\n",
3351 __func__, vreg->name, ret);
3352out:
3353 return ret;
3354}
3355
3356static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
3357{
3358 int ret = 0;
3359
3360 if (!vreg || !vreg->enabled)
3361 goto out;
3362
3363 ret = regulator_disable(vreg->reg);
3364
3365 if (!ret) {
3366 /* ignore errors on applying disable config */
3367 ufshcd_config_vreg(dev, vreg, false);
3368 vreg->enabled = false;
3369 } else {
3370 dev_err(dev, "%s: %s disable failed, err=%d\n",
3371 __func__, vreg->name, ret);
3372 }
3373out:
3374 return ret;
3375}
3376
3377static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
3378{
3379 int ret = 0;
3380 struct device *dev = hba->dev;
3381 struct ufs_vreg_info *info = &hba->vreg_info;
3382
3383 if (!info)
3384 goto out;
3385
3386 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
3387 if (ret)
3388 goto out;
3389
3390 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
3391 if (ret)
3392 goto out;
3393
3394 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
3395 if (ret)
3396 goto out;
3397
3398out:
3399 if (ret) {
3400 ufshcd_toggle_vreg(dev, info->vccq2, false);
3401 ufshcd_toggle_vreg(dev, info->vccq, false);
3402 ufshcd_toggle_vreg(dev, info->vcc, false);
3403 }
3404 return ret;
3405}
3406
6a771a65
RS		 3407static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
3408{
3409 struct ufs_vreg_info *info = &hba->vreg_info;
3410
3411 if (info)
3412 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
3413
3414 return 0;
3415}
3416
aa497613
SRT		 3417static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
3418{
3419 int ret = 0;
3420
3421 if (!vreg)
3422 goto out;
3423
3424 vreg->reg = devm_regulator_get(dev, vreg->name);
3425 if (IS_ERR(vreg->reg)) {
3426 ret = PTR_ERR(vreg->reg);
3427 dev_err(dev, "%s: %s get failed, err=%d\n",
3428 __func__, vreg->name, ret);
3429 }
3430out:
3431 return ret;
3432}
3433
3434static int ufshcd_init_vreg(struct ufs_hba *hba)
3435{
3436 int ret = 0;
3437 struct device *dev = hba->dev;
3438 struct ufs_vreg_info *info = &hba->vreg_info;
3439
3440 if (!info)
3441 goto out;
3442
3443 ret = ufshcd_get_vreg(dev, info->vcc);
3444 if (ret)
3445 goto out;
3446
3447 ret = ufshcd_get_vreg(dev, info->vccq);
3448 if (ret)
3449 goto out;
3450
3451 ret = ufshcd_get_vreg(dev, info->vccq2);
3452out:
3453 return ret;
3454}
3455
6a771a65
RS		 3456static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
3457{
3458 struct ufs_vreg_info *info = &hba->vreg_info;
3459
3460 if (info)
3461 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
3462
3463 return 0;
3464}
3465
c6e79dac
SRT		 3466static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
3467{
3468 int ret = 0;
3469 struct ufs_clk_info *clki;
3470 struct list_head *head = &hba->clk_list_head;
3471
3472 if (!head || list_empty(head))
3473 goto out;
3474
3475 list_for_each_entry(clki, head, list) {
3476 if (!IS_ERR_OR_NULL(clki->clk)) {
3477 if (on && !clki->enabled) {
3478 ret = clk_prepare_enable(clki->clk);
3479 if (ret) {
3480 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
3481 __func__, clki->name, ret);
3482 goto out;
3483 }
3484 } else if (!on && clki->enabled) {
3485 clk_disable_unprepare(clki->clk);
3486 }
3487 clki->enabled = on;
3488 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
3489 clki->name, on ? "en" : "dis");
3490 }
3491 }
3492out:
3493 if (ret) {
3494 list_for_each_entry(clki, head, list) {
3495 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
3496 clk_disable_unprepare(clki->clk);
3497 }
3498 }
3499 return ret;
3500}
3501
3502static int ufshcd_init_clocks(struct ufs_hba *hba)
3503{
3504 int ret = 0;
3505 struct ufs_clk_info *clki;
3506 struct device *dev = hba->dev;
3507 struct list_head *head = &hba->clk_list_head;
3508
3509 if (!head || list_empty(head))
3510 goto out;
3511
3512 list_for_each_entry(clki, head, list) {
3513 if (!clki->name)
3514 continue;
3515
3516 clki->clk = devm_clk_get(dev, clki->name);
3517 if (IS_ERR(clki->clk)) {
3518 ret = PTR_ERR(clki->clk);
3519 dev_err(dev, "%s: %s clk get failed, %d\n",
3520 __func__, clki->name, ret);
3521 goto out;
3522 }
3523
3524 if (clki->max_freq) {
3525 ret = clk_set_rate(clki->clk, clki->max_freq);
3526 if (ret) {
3527 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
3528 __func__, clki->name,
3529 clki->max_freq, ret);
3530 goto out;
3531 }
3532 }
3533 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
3534 clki->name, clk_get_rate(clki->clk));
3535 }
3536out:
3537 return ret;
3538}
3539
5c0c28a8
SRT		 3540static int ufshcd_variant_hba_init(struct ufs_hba *hba)
3541{
3542 int err = 0;
3543
3544 if (!hba->vops)
3545 goto out;
3546
3547 if (hba->vops->init) {
3548 err = hba->vops->init(hba);
3549 if (err)
3550 goto out;
3551 }
3552
3553 if (hba->vops->setup_clocks) {
3554 err = hba->vops->setup_clocks(hba, true);
3555 if (err)
3556 goto out_exit;
3557 }
3558
3559 if (hba->vops->setup_regulators) {
3560 err = hba->vops->setup_regulators(hba, true);
3561 if (err)
3562 goto out_clks;
3563 }
3564
3565 goto out;
3566
3567out_clks:
3568 if (hba->vops->setup_clocks)
3569 hba->vops->setup_clocks(hba, false);
3570out_exit:
3571 if (hba->vops->exit)
3572 hba->vops->exit(hba);
3573out:
3574 if (err)
3575 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
3576 __func__, hba->vops ? hba->vops->name : "", err);
3577 return err;
3578}
3579
3580static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
3581{
3582 if (!hba->vops)
3583 return;
3584
3585 if (hba->vops->setup_clocks)
3586 hba->vops->setup_clocks(hba, false);
3587
3588 if (hba->vops->setup_regulators)
3589 hba->vops->setup_regulators(hba, false);
3590
3591 if (hba->vops->exit)
3592 hba->vops->exit(hba);
3593}
3594
aa497613
SRT		 3595static int ufshcd_hba_init(struct ufs_hba *hba)
3596{
3597 int err;
3598
6a771a65
RS		 3599 /*
3600 * Handle host controller power separately from the UFS device power
3601 * rails as it will help controlling the UFS host controller power
3602 * collapse easily which is different than UFS device power collapse.
3603 * Also, enable the host controller power before we go ahead with rest
3604 * of the initialization here.
3605 */
3606 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 3607 if (err)
3608 goto out;
3609
6a771a65 3610 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 3611 if (err)
3612 goto out;
3613
6a771a65
RS		 3614 err = ufshcd_init_clocks(hba);
3615 if (err)
3616 goto out_disable_hba_vreg;
3617
3618 err = ufshcd_setup_clocks(hba, true);
3619 if (err)
3620 goto out_disable_hba_vreg;
3621
c6e79dac
SRT		 3622 err = ufshcd_init_vreg(hba);
3623 if (err)
3624 goto out_disable_clks;
3625
3626 err = ufshcd_setup_vreg(hba, true);
3627 if (err)
3628 goto out_disable_clks;
3629
aa497613
SRT		 3630 err = ufshcd_variant_hba_init(hba);
3631 if (err)
3632 goto out_disable_vreg;
3633
3634 goto out;
3635
3636out_disable_vreg:
3637 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 3638out_disable_clks:
3639 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 3640out_disable_hba_vreg:
3641 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 3642out:
3643 return err;
3644}
3645
3646static void ufshcd_hba_exit(struct ufs_hba *hba)
3647{
3648 ufshcd_variant_hba_exit(hba);
3649 ufshcd_setup_vreg(hba, false);
c6e79dac 3650 ufshcd_setup_clocks(hba, false);
6a771a65 3651 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 3652}
3653
7a3e97b0
SY		 3654/**
3655 * ufshcd_suspend - suspend power management function
3b1d0580 3656 * @hba: per adapter instance
7a3e97b0
SY		 3657 * @state: power state
3658 *
3659 * Returns -ENOSYS
3660 */
3b1d0580 3661int ufshcd_suspend(struct ufs_hba *hba, pm_message_t state)
7a3e97b0
SY		 3662{
3663 /*
3664 * TODO:
3665 * 1. Block SCSI requests from SCSI midlayer
3666 * 2. Change the internal driver state to non operational
3667 * 3. Set UTRLRSR and UTMRLRSR bits to zero
3668 * 4. Wait until outstanding commands are completed
3669 * 5. Set HCE to zero to send the UFS host controller to reset state
3670 */
3671
3672 return -ENOSYS;
3673}
3b1d0580 3674EXPORT_SYMBOL_GPL(ufshcd_suspend);
7a3e97b0
SY		 3675
3676/**
3677 * ufshcd_resume - resume power management function
3b1d0580 3678 * @hba: per adapter instance
7a3e97b0
SY		 3679 *
3680 * Returns -ENOSYS
3681 */
3b1d0580 3682int ufshcd_resume(struct ufs_hba *hba)
7a3e97b0
SY		 3683{
3684 /*
3685 * TODO:
3686 * 1. Set HCE to 1, to start the UFS host controller
3687 * initialization process
3688 * 2. Set UTRLRSR and UTMRLRSR bits to 1
3689 * 3. Change the internal driver state to operational
3690 * 4. Unblock SCSI requests from SCSI midlayer
3691 */
3692
3693 return -ENOSYS;
3694}
3b1d0580
VH		 3695EXPORT_SYMBOL_GPL(ufshcd_resume);
3696
66ec6d59
SRT		 3697int ufshcd_runtime_suspend(struct ufs_hba *hba)
3698{
3699 if (!hba)
3700 return 0;
3701
3702 /*
3703 * The device is idle with no requests in the queue,
3704 * allow background operations.
3705 */
3706 return ufshcd_enable_auto_bkops(hba);
3707}
3708EXPORT_SYMBOL(ufshcd_runtime_suspend);
3709
3710int ufshcd_runtime_resume(struct ufs_hba *hba)
3711{
3712 if (!hba)
3713 return 0;
3714
3715 return ufshcd_disable_auto_bkops(hba);
3716}
3717EXPORT_SYMBOL(ufshcd_runtime_resume);
3718
3719int ufshcd_runtime_idle(struct ufs_hba *hba)
3720{
3721 return 0;
3722}
3723EXPORT_SYMBOL(ufshcd_runtime_idle);
3724
7a3e97b0 3725/**
3b1d0580 3726 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 3727 * data structure memory
3b1d0580 3728 * @hba - per adapter instance
7a3e97b0 3729 */
3b1d0580 3730void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 3731{
cfdf9c91 3732 scsi_remove_host(hba->host);
7a3e97b0 3733 /* disable interrupts */
2fbd009b 3734 ufshcd_disable_intr(hba, hba->intr_mask);
7a3e97b0 3735 ufshcd_hba_stop(hba);
7a3e97b0 3736
7a3e97b0 3737 scsi_host_put(hba->host);
5c0c28a8 3738
aa497613 3739 ufshcd_hba_exit(hba);
3b1d0580
VH		 3740}
3741EXPORT_SYMBOL_GPL(ufshcd_remove);
3742
ca3d7bf9
AM		 3743/**
3744 * ufshcd_set_dma_mask - Set dma mask based on the controller
3745 * addressing capability
3746 * @hba: per adapter instance
3747 *
3748 * Returns 0 for success, non-zero for failure
3749 */
3750static int ufshcd_set_dma_mask(struct ufs_hba *hba)
3751{
3752 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
3753 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
3754 return 0;
3755 }
3756 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
3757}
3758
7a3e97b0 3759/**
5c0c28a8 3760 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 3761 * @dev: pointer to device handle
3762 * @hba_handle: driver private handle
7a3e97b0
SY		 3763 * Returns 0 on success, non-zero value on failure
3764 */
5c0c28a8 3765int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 3766{
3767 struct Scsi_Host *host;
3768 struct ufs_hba *hba;
5c0c28a8 3769 int err = 0;
7a3e97b0 3770
3b1d0580
VH		 3771 if (!dev) {
3772 dev_err(dev,
3773 "Invalid memory reference for dev is NULL\n");
3774 err = -ENODEV;
7a3e97b0
SY		 3775 goto out_error;
3776 }
3777
7a3e97b0
SY		 3778 host = scsi_host_alloc(&ufshcd_driver_template,
3779 sizeof(struct ufs_hba));
3780 if (!host) {
3b1d0580 3781 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 3782 err = -ENOMEM;
3b1d0580 3783 goto out_error;
7a3e97b0
SY		 3784 }
3785 hba = shost_priv(host);
7a3e97b0 3786 hba->host = host;
3b1d0580 3787 hba->dev = dev;
5c0c28a8
SRT		 3788 *hba_handle = hba;
3789
3790out_error:
3791 return err;
3792}
3793EXPORT_SYMBOL(ufshcd_alloc_host);
3794
3795/**
3796 * ufshcd_init - Driver initialization routine
3797 * @hba: per-adapter instance
3798 * @mmio_base: base register address
3799 * @irq: Interrupt line of device
3800 * Returns 0 on success, non-zero value on failure
3801 */
3802int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
3803{
3804 int err;
3805 struct Scsi_Host *host = hba->host;
3806 struct device *dev = hba->dev;
3807
3808 if (!mmio_base) {
3809 dev_err(hba->dev,
3810 "Invalid memory reference for mmio_base is NULL\n");
3811 err = -ENODEV;
3812 goto out_error;
3813 }
3814
3b1d0580
VH		 3815 hba->mmio_base = mmio_base;
3816 hba->irq = irq;
7a3e97b0 3817
aa497613 3818 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 3819 if (err)
3820 goto out_error;
3821
7a3e97b0
SY		 3822 /* Read capabilities registers */
3823 ufshcd_hba_capabilities(hba);
3824
3825 /* Get UFS version supported by the controller */
3826 hba->ufs_version = ufshcd_get_ufs_version(hba);
3827
2fbd009b
SJ		 3828 /* Get Interrupt bit mask per version */
3829 hba->intr_mask = ufshcd_get_intr_mask(hba);
3830
ca3d7bf9
AM		 3831 err = ufshcd_set_dma_mask(hba);
3832 if (err) {
3833 dev_err(hba->dev, "set dma mask failed\n");
3834 goto out_disable;
3835 }
3836
7a3e97b0
SY		 3837 /* Allocate memory for host memory space */
3838 err = ufshcd_memory_alloc(hba);
3839 if (err) {
3b1d0580
VH		 3840 dev_err(hba->dev, "Memory allocation failed\n");
3841 goto out_disable;
7a3e97b0
SY		 3842 }
3843
3844 /* Configure LRB */
3845 ufshcd_host_memory_configure(hba);
3846
3847 host->can_queue = hba->nutrs;
3848 host->cmd_per_lun = hba->nutrs;
3849 host->max_id = UFSHCD_MAX_ID;
3850 host->max_lun = UFSHCD_MAX_LUNS;
3851 host->max_channel = UFSHCD_MAX_CHANNEL;
3852 host->unique_id = host->host_no;
3853 host->max_cmd_len = MAX_CDB_SIZE;
3854
3855 /* Initailize wait queue for task management */
e2933132
SRT		 3856 init_waitqueue_head(&hba->tm_wq);
3857 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 3858
3859 /* Initialize work queues */
e8e7f271 3860 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 3861 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 3862
6ccf44fe
SJ		 3863 /* Initialize UIC command mutex */
3864 mutex_init(&hba->uic_cmd_mutex);
3865
5a0b0cb9
SRT		 3866 /* Initialize mutex for device management commands */
3867 mutex_init(&hba->dev_cmd.lock);
3868
3869 /* Initialize device management tag acquire wait queue */
3870 init_waitqueue_head(&hba->dev_cmd.tag_wq);
3871
7a3e97b0 3872 /* IRQ registration */
2953f850 3873 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 3874 if (err) {
3b1d0580 3875 dev_err(hba->dev, "request irq failed\n");
2953f850 3876 goto out_disable;
7a3e97b0
SY		 3877 }
3878
3879 /* Enable SCSI tag mapping */
3880 err = scsi_init_shared_tag_map(host, host->can_queue);
3881 if (err) {
3b1d0580 3882 dev_err(hba->dev, "init shared queue failed\n");
2953f850 3883 goto out_disable;
7a3e97b0
SY		 3884 }
3885
3b1d0580 3886 err = scsi_add_host(host, hba->dev);
7a3e97b0 3887 if (err) {
3b1d0580 3888 dev_err(hba->dev, "scsi_add_host failed\n");
2953f850 3889 goto out_disable;
7a3e97b0
SY		 3890 }
3891
6ccf44fe
SJ		 3892 /* Host controller enable */
3893 err = ufshcd_hba_enable(hba);
7a3e97b0 3894 if (err) {
6ccf44fe 3895 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 3896 goto out_remove_scsi_host;
7a3e97b0 3897 }
6ccf44fe 3898
62694735
SRT		 3899 /* Hold auto suspend until async scan completes */
3900 pm_runtime_get_sync(dev);
3901
6ccf44fe
SJ		 3902 async_schedule(ufshcd_async_scan, hba);
3903
7a3e97b0
SY		 3904 return 0;
3905
3b1d0580
VH		 3906out_remove_scsi_host:
3907 scsi_remove_host(hba->host);
3b1d0580
VH		 3908out_disable:
3909 scsi_host_put(host);
aa497613 3910 ufshcd_hba_exit(hba);
3b1d0580
VH		 3911out_error:
3912 return err;
3913}
3914EXPORT_SYMBOL_GPL(ufshcd_init);
3915
3b1d0580
VH		 3916MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
3917MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 3918MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 3919MODULE_LICENSE("GPL");
3920MODULE_VERSION(UFSHCD_DRIVER_VERSION);