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scsi: hisi_sas: add missing break in switch statement
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
7a3e97b0 47
7ff5ab47
SJ		 48#define CREATE_TRACE_POINTS
49#include <trace/events/ufs.h>
50
dcea0bfb
GB		 51#define UFSHCD_REQ_SENSE_SIZE 18
52
2fbd009b
SJ		 53#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
54 UTP_TASK_REQ_COMPL |\
55 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 56/* UIC command timeout, unit: ms */
57#define UIC_CMD_TIMEOUT 500
2fbd009b 58
5a0b0cb9
SRT		 59/* NOP OUT retries waiting for NOP IN response */
60#define NOP_OUT_RETRIES 10
61/* Timeout after 30 msecs if NOP OUT hangs without response */
62#define NOP_OUT_TIMEOUT 30 /* msecs */
63
68078d5c 64/* Query request retries */
10fe5888 65#define QUERY_REQ_RETRIES 3
68078d5c 66/* Query request timeout */
10fe5888 67#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 68
e2933132
SRT		 69/* Task management command timeout */
70#define TM_CMD_TIMEOUT 100 /* msecs */
71
64238fbd
YG		 72/* maximum number of retries for a general UIC command */
73#define UFS_UIC_COMMAND_RETRIES 3
74
1d337ec2
SRT		 75/* maximum number of link-startup retries */
76#define DME_LINKSTARTUP_RETRIES 3
77
87d0b4a6
YG		 78/* Maximum retries for Hibern8 enter */
79#define UIC_HIBERN8_ENTER_RETRIES 3
80
1d337ec2
SRT		 81/* maximum number of reset retries before giving up */
82#define MAX_HOST_RESET_RETRIES 5
83
68078d5c
DR		 84/* Expose the flag value from utp_upiu_query.value */
85#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
86
7d568652
SJ		 87/* Interrupt aggregation default timeout, unit: 40us */
88#define INT_AGGR_DEF_TO 0x02
89
aa497613
SRT		 90#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
91 ({ \
92 int _ret; \
93 if (_on) \
94 _ret = ufshcd_enable_vreg(_dev, _vreg); \
95 else \
96 _ret = ufshcd_disable_vreg(_dev, _vreg); \
97 _ret; \
98 })
99
66cc820f
DR		 100#define ufshcd_hex_dump(prefix_str, buf, len) \
101print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, len, false)
102
da461cec
SJ		 103static u32 ufs_query_desc_max_size[] = {
104 QUERY_DESC_DEVICE_MAX_SIZE,
105 QUERY_DESC_CONFIGURAION_MAX_SIZE,
106 QUERY_DESC_UNIT_MAX_SIZE,
107 QUERY_DESC_RFU_MAX_SIZE,
108 QUERY_DESC_INTERCONNECT_MAX_SIZE,
109 QUERY_DESC_STRING_MAX_SIZE,
110 QUERY_DESC_RFU_MAX_SIZE,
1ce21794 111 QUERY_DESC_GEOMETRY_MAX_SIZE,
da461cec
SJ		 112 QUERY_DESC_POWER_MAX_SIZE,
113 QUERY_DESC_RFU_MAX_SIZE,
114};
115
7a3e97b0
SY		 116enum {
117 UFSHCD_MAX_CHANNEL = 0,
118 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 119 UFSHCD_CMD_PER_LUN = 32,
120 UFSHCD_CAN_QUEUE = 32,
121};
122
123/* UFSHCD states */
124enum {
7a3e97b0
SY		 125 UFSHCD_STATE_RESET,
126 UFSHCD_STATE_ERROR,
3441da7d 127 UFSHCD_STATE_OPERATIONAL,
141f8165 128 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 129};
130
131/* UFSHCD error handling flags */
132enum {
133 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 134};
135
e8e7f271
SRT		 136/* UFSHCD UIC layer error flags */
137enum {
138 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 139 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
140 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
141 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
142 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
143 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
e8e7f271
SRT		 144};
145
7a3e97b0
SY		 146/* Interrupt configuration options */
147enum {
148 UFSHCD_INT_DISABLE,
149 UFSHCD_INT_ENABLE,
150 UFSHCD_INT_CLEAR,
151};
152
3441da7d
SRT		 153#define ufshcd_set_eh_in_progress(h) \
154 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
155#define ufshcd_eh_in_progress(h) \
156 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
157#define ufshcd_clear_eh_in_progress(h) \
158 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
159
57d104c1
SJ		 160#define ufshcd_set_ufs_dev_active(h) \
161 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
162#define ufshcd_set_ufs_dev_sleep(h) \
163 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
164#define ufshcd_set_ufs_dev_poweroff(h) \
165 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
166#define ufshcd_is_ufs_dev_active(h) \
167 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
168#define ufshcd_is_ufs_dev_sleep(h) \
169 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
170#define ufshcd_is_ufs_dev_poweroff(h) \
171 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
172
173static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
174 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
175 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
176 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
177 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
178 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
179 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
180};
181
182static inline enum ufs_dev_pwr_mode
183ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
184{
185 return ufs_pm_lvl_states[lvl].dev_state;
186}
187
188static inline enum uic_link_state
189ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
190{
191 return ufs_pm_lvl_states[lvl].link_state;
192}
193
0c8f7586
SJ		 194static inline enum ufs_pm_level
195ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
196 enum uic_link_state link_state)
197{
198 enum ufs_pm_level lvl;
199
200 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
201 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
202 (ufs_pm_lvl_states[lvl].link_state == link_state))
203 return lvl;
204 }
205
206 /* if no match found, return the level 0 */
207 return UFS_PM_LVL_0;
208}
209
56d4a186
SJ		 210static struct ufs_dev_fix ufs_fixups[] = {
211 /* UFS cards deviations table */
212 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
213 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
214 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
215 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
216 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
217 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
218 UFS_DEVICE_NO_FASTAUTO),
219 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
220 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
221 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
222 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
223 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
224 UFS_DEVICE_QUIRK_PA_TACTIVATE),
225 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
226 UFS_DEVICE_QUIRK_PA_TACTIVATE),
227 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
228 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
229 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
230
231 END_FIX
232};
233
3441da7d
SRT		 234static void ufshcd_tmc_handler(struct ufs_hba *hba);
235static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 236static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 237static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 238static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 239static void ufshcd_hba_exit(struct ufs_hba *hba);
240static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 241static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
242 bool skip_ref_clk);
243static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 244static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 245static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
246static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
cad2e03d 247static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 248static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 249static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
250static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 251static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 252static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 253static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 254static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
255 struct ufs_pa_layer_attr *desired_pwr_mode);
874237f7
YG		 256static int ufshcd_change_power_mode(struct ufs_hba *hba,
257 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 258static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
259{
260 return tag >= 0 && tag < hba->nutrs;
261}
57d104c1
SJ		 262
263static inline int ufshcd_enable_irq(struct ufs_hba *hba)
264{
265 int ret = 0;
266
267 if (!hba->is_irq_enabled) {
268 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
269 hba);
270 if (ret)
271 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
272 __func__, ret);
273 hba->is_irq_enabled = true;
274 }
275
276 return ret;
277}
278
279static inline void ufshcd_disable_irq(struct ufs_hba *hba)
280{
281 if (hba->is_irq_enabled) {
282 free_irq(hba->irq, hba);
283 hba->is_irq_enabled = false;
284 }
285}
3441da7d 286
b573d484
YG		 287/* replace non-printable or non-ASCII characters with spaces */
288static inline void ufshcd_remove_non_printable(char *val)
289{
290 if (!val)
291 return;
292
293 if (*val < 0x20 || *val > 0x7e)
294 *val = ' ';
295}
296
1a07f2d9
LS		 297static void ufshcd_add_command_trace(struct ufs_hba *hba,
298 unsigned int tag, const char *str)
299{
300 sector_t lba = -1;
301 u8 opcode = 0;
302 u32 intr, doorbell;
303 struct ufshcd_lrb *lrbp;
304 int transfer_len = -1;
305
306 if (!trace_ufshcd_command_enabled())
307 return;
308
309 lrbp = &hba->lrb[tag];
310
311 if (lrbp->cmd) { /* data phase exists */
312 opcode = (u8)(*lrbp->cmd->cmnd);
313 if ((opcode == READ_10) || (opcode == WRITE_10)) {
314 /*
315 * Currently we only fully trace read(10) and write(10)
316 * commands
317 */
318 if (lrbp->cmd->request && lrbp->cmd->request->bio)
319 lba =
320 lrbp->cmd->request->bio->bi_iter.bi_sector;
321 transfer_len = be32_to_cpu(
322 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
323 }
324 }
325
326 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
327 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
328 trace_ufshcd_command(dev_name(hba->dev), str, tag,
329 doorbell, transfer_len, intr, lba, opcode);
330}
331
ff8e20c6
DR		 332static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
333{
334 struct ufs_clk_info *clki;
335 struct list_head *head = &hba->clk_list_head;
336
337 if (!head || list_empty(head))
338 return;
339
340 list_for_each_entry(clki, head, list) {
341 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
342 clki->max_freq)
343 dev_err(hba->dev, "clk: %s, rate: %u\n",
344 clki->name, clki->curr_freq);
345 }
346}
347
348static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
349 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
350{
351 int i;
352
353 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
354 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
355
356 if (err_hist->reg[p] == 0)
357 continue;
358 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
359 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
360 }
361}
362
66cc820f
DR		 363static void ufshcd_print_host_regs(struct ufs_hba *hba)
364{
365 /*
366 * hex_dump reads its data without the readl macro. This might
367 * cause inconsistency issues on some platform, as the printed
368 * values may be from cache and not the most recent value.
369 * To know whether you are looking at an un-cached version verify
370 * that IORESOURCE_MEM flag is on when xxx_get_resource() is invoked
371 * during platform/pci probe function.
372 */
373 ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE);
374 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
375 hba->ufs_version, hba->capabilities);
376 dev_err(hba->dev,
377 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
378 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 379 dev_err(hba->dev,
380 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
381 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
382 hba->ufs_stats.hibern8_exit_cnt);
383
384 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
385 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
386 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
387 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
388 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
389
390 ufshcd_print_clk_freqs(hba);
391
392 if (hba->vops && hba->vops->dbg_register_dump)
393 hba->vops->dbg_register_dump(hba);
66cc820f
DR		 394}
395
396static
397void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
398{
399 struct ufshcd_lrb *lrbp;
7fabb77b 400 int prdt_length;
66cc820f
DR		 401 int tag;
402
403 for_each_set_bit(tag, &bitmap, hba->nutrs) {
404 lrbp = &hba->lrb[tag];
405
ff8e20c6
DR		 406 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
407 tag, ktime_to_us(lrbp->issue_time_stamp));
408 dev_err(hba->dev,
409 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
410 tag, (u64)lrbp->utrd_dma_addr);
411
66cc820f
DR		 412 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
413 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 414 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
415 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 416 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
417 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 418 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
419 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 420 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
421 sizeof(struct utp_upiu_rsp));
66cc820f 422
7fabb77b
GB		 423 prdt_length = le16_to_cpu(
424 lrbp->utr_descriptor_ptr->prd_table_length);
425 dev_err(hba->dev,
426 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
427 tag, prdt_length,
428 (u64)lrbp->ucd_prdt_dma_addr);
429
430 if (pr_prdt)
66cc820f 431 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 432 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 433 }
434}
435
436static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
437{
438 struct utp_task_req_desc *tmrdp;
439 int tag;
440
441 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
442 tmrdp = &hba->utmrdl_base_addr[tag];
443 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
444 ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
445 sizeof(struct request_desc_header));
446 dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
447 tag);
448 ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
449 sizeof(struct utp_upiu_req));
450 dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
451 tag);
452 ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
453 sizeof(struct utp_task_req_desc));
454 }
455}
456
6ba65588
GB		 457static void ufshcd_print_host_state(struct ufs_hba *hba)
458{
459 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
460 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
461 hba->lrb_in_use, hba->outstanding_tasks, hba->outstanding_reqs);
462 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
463 hba->saved_err, hba->saved_uic_err);
464 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
465 hba->curr_dev_pwr_mode, hba->uic_link_state);
466 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
467 hba->pm_op_in_progress, hba->is_sys_suspended);
468 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
469 hba->auto_bkops_enabled, hba->host->host_self_blocked);
470 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
471 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
472 hba->eh_flags, hba->req_abort_count);
473 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
474 hba->capabilities, hba->caps);
475 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
476 hba->dev_quirks);
477}
478
ff8e20c6
DR		 479/**
480 * ufshcd_print_pwr_info - print power params as saved in hba
481 * power info
482 * @hba: per-adapter instance
483 */
484static void ufshcd_print_pwr_info(struct ufs_hba *hba)
485{
486 static const char * const names[] = {
487 "INVALID MODE",
488 "FAST MODE",
489 "SLOW_MODE",
490 "INVALID MODE",
491 "FASTAUTO_MODE",
492 "SLOWAUTO_MODE",
493 "INVALID MODE",
494 };
495
496 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
497 __func__,
498 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
499 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
500 names[hba->pwr_info.pwr_rx],
501 names[hba->pwr_info.pwr_tx],
502 hba->pwr_info.hs_rate);
503}
504
5a0b0cb9
SRT		 505/*
506 * ufshcd_wait_for_register - wait for register value to change
507 * @hba - per-adapter interface
508 * @reg - mmio register offset
509 * @mask - mask to apply to read register value
510 * @val - wait condition
511 * @interval_us - polling interval in microsecs
512 * @timeout_ms - timeout in millisecs
596585a2 513 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 514 *
515 * Returns -ETIMEDOUT on error, zero on success
516 */
596585a2
YG		 517int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
518 u32 val, unsigned long interval_us,
519 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 520{
521 int err = 0;
522 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
523
524 /* ignore bits that we don't intend to wait on */
525 val = val & mask;
526
527 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 528 if (can_sleep)
529 usleep_range(interval_us, interval_us + 50);
530 else
531 udelay(interval_us);
5a0b0cb9
SRT		 532 if (time_after(jiffies, timeout)) {
533 if ((ufshcd_readl(hba, reg) & mask) != val)
534 err = -ETIMEDOUT;
535 break;
536 }
537 }
538
539 return err;
540}
541
2fbd009b
SJ		 542/**
543 * ufshcd_get_intr_mask - Get the interrupt bit mask
544 * @hba - Pointer to adapter instance
545 *
546 * Returns interrupt bit mask per version
547 */
548static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
549{
c01848c6
YG		 550 u32 intr_mask = 0;
551
552 switch (hba->ufs_version) {
553 case UFSHCI_VERSION_10:
554 intr_mask = INTERRUPT_MASK_ALL_VER_10;
555 break;
c01848c6
YG		 556 case UFSHCI_VERSION_11:
557 case UFSHCI_VERSION_20:
558 intr_mask = INTERRUPT_MASK_ALL_VER_11;
559 break;
c01848c6
YG		 560 case UFSHCI_VERSION_21:
561 default:
562 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 563 break;
c01848c6
YG		 564 }
565
566 return intr_mask;
2fbd009b
SJ		 567}
568
7a3e97b0
SY		 569/**
570 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
571 * @hba - Pointer to adapter instance
572 *
573 * Returns UFSHCI version supported by the controller
574 */
575static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
576{
0263bcd0
YG		 577 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
578 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 579
b873a275 580 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 581}
582
583/**
584 * ufshcd_is_device_present - Check if any device connected to
585 * the host controller
5c0c28a8 586 * @hba: pointer to adapter instance
7a3e97b0 587 *
73ec513a 588 * Returns 1 if device present, 0 if no device detected
7a3e97b0 589 */
5c0c28a8 590static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 591{
5c0c28a8
SRT		 592 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
593 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 594}
595
596/**
597 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
598 * @lrb: pointer to local command reference block
599 *
600 * This function is used to get the OCS field from UTRD
601 * Returns the OCS field in the UTRD
602 */
603static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
604{
e8c8e82a 605 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 606}
607
608/**
609 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
610 * @task_req_descp: pointer to utp_task_req_desc structure
611 *
612 * This function is used to get the OCS field from UTMRD
613 * Returns the OCS field in the UTMRD
614 */
615static inline int
616ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
617{
e8c8e82a 618 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 619}
620
621/**
622 * ufshcd_get_tm_free_slot - get a free slot for task management request
623 * @hba: per adapter instance
e2933132 624 * @free_slot: pointer to variable with available slot value
7a3e97b0 625 *
e2933132
SRT		 626 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
627 * Returns 0 if free slot is not available, else return 1 with tag value
628 * in @free_slot.
7a3e97b0 629 */
e2933132 630static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 631{
e2933132
SRT		 632 int tag;
633 bool ret = false;
634
635 if (!free_slot)
636 goto out;
637
638 do {
639 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
640 if (tag >= hba->nutmrs)
641 goto out;
642 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
643
644 *free_slot = tag;
645 ret = true;
646out:
647 return ret;
648}
649
650static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
651{
652 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 653}
654
655/**
656 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
657 * @hba: per adapter instance
658 * @pos: position of the bit to be cleared
659 */
660static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
661{
b873a275 662 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 663}
664
a48353f6
YG		 665/**
666 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
667 * @hba: per adapter instance
668 * @tag: position of the bit to be cleared
669 */
670static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
671{
672 __clear_bit(tag, &hba->outstanding_reqs);
673}
674
7a3e97b0
SY		 675/**
676 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
677 * @reg: Register value of host controller status
678 *
679 * Returns integer, 0 on Success and positive value if failed
680 */
681static inline int ufshcd_get_lists_status(u32 reg)
682{
683 /*
684 * The mask 0xFF is for the following HCS register bits
685 * Bit Description
686 * 0 Device Present
687 * 1 UTRLRDY
688 * 2 UTMRLRDY
689 * 3 UCRDY
897efe62 690 * 4-7 reserved
7a3e97b0 691 */
897efe62 692 return ((reg & 0xFF) >> 1) ^ 0x07;
7a3e97b0
SY		 693}
694
695/**
696 * ufshcd_get_uic_cmd_result - Get the UIC command result
697 * @hba: Pointer to adapter instance
698 *
699 * This function gets the result of UIC command completion
700 * Returns 0 on success, non zero value on error
701 */
702static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
703{
b873a275 704 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 705 MASK_UIC_COMMAND_RESULT;
706}
707
12b4fdb4
SJ		 708/**
709 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
710 * @hba: Pointer to adapter instance
711 *
712 * This function gets UIC command argument3
713 * Returns 0 on success, non zero value on error
714 */
715static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
716{
717 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
718}
719
7a3e97b0 720/**
5a0b0cb9 721 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 722 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 723 */
724static inline int
5a0b0cb9 725ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 726{
5a0b0cb9 727 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 728}
729
730/**
731 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
732 * @ucd_rsp_ptr: pointer to response UPIU
733 *
734 * This function gets the response status and scsi_status from response UPIU
735 * Returns the response result code.
736 */
737static inline int
738ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
739{
740 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
741}
742
1c2623c5
SJ		 743/*
744 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
745 * from response UPIU
746 * @ucd_rsp_ptr: pointer to response UPIU
747 *
748 * Return the data segment length.
749 */
750static inline unsigned int
751ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
752{
753 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
754 MASK_RSP_UPIU_DATA_SEG_LEN;
755}
756
66ec6d59
SRT		 757/**
758 * ufshcd_is_exception_event - Check if the device raised an exception event
759 * @ucd_rsp_ptr: pointer to response UPIU
760 *
761 * The function checks if the device raised an exception event indicated in
762 * the Device Information field of response UPIU.
763 *
764 * Returns true if exception is raised, false otherwise.
765 */
766static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
767{
768 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
769 MASK_RSP_EXCEPTION_EVENT ? true : false;
770}
771
7a3e97b0 772/**
7d568652 773 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 774 * @hba: per adapter instance
7a3e97b0
SY		 775 */
776static inline void
7d568652 777ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 778{
7d568652
SJ		 779 ufshcd_writel(hba, INT_AGGR_ENABLE |
780 INT_AGGR_COUNTER_AND_TIMER_RESET,
781 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
782}
783
784/**
785 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
786 * @hba: per adapter instance
787 * @cnt: Interrupt aggregation counter threshold
788 * @tmout: Interrupt aggregation timeout value
789 */
790static inline void
791ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
792{
793 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
794 INT_AGGR_COUNTER_THLD_VAL(cnt) |
795 INT_AGGR_TIMEOUT_VAL(tmout),
796 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 797}
798
b852190e
YG		 799/**
800 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
801 * @hba: per adapter instance
802 */
803static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
804{
805 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
806}
807
7a3e97b0
SY		 808/**
809 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
810 * When run-stop registers are set to 1, it indicates the
811 * host controller that it can process the requests
812 * @hba: per adapter instance
813 */
814static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
815{
b873a275
SJ		 816 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
817 REG_UTP_TASK_REQ_LIST_RUN_STOP);
818 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
819 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 820}
821
7a3e97b0
SY		 822/**
823 * ufshcd_hba_start - Start controller initialization sequence
824 * @hba: per adapter instance
825 */
826static inline void ufshcd_hba_start(struct ufs_hba *hba)
827{
b873a275 828 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 829}
830
831/**
832 * ufshcd_is_hba_active - Get controller state
833 * @hba: per adapter instance
834 *
835 * Returns zero if controller is active, 1 otherwise
836 */
837static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
838{
b873a275 839 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 840}
841
09690d5a
SJ		 842static const char *ufschd_uic_link_state_to_string(
843 enum uic_link_state state)
844{
845 switch (state) {
846 case UIC_LINK_OFF_STATE: return "OFF";
847 case UIC_LINK_ACTIVE_STATE: return "ACTIVE";
848 case UIC_LINK_HIBERN8_STATE: return "HIBERN8";
849 default: return "UNKNOWN";
850 }
851}
852
853static const char *ufschd_ufs_dev_pwr_mode_to_string(
854 enum ufs_dev_pwr_mode state)
855{
856 switch (state) {
857 case UFS_ACTIVE_PWR_MODE: return "ACTIVE";
858 case UFS_SLEEP_PWR_MODE: return "SLEEP";
859 case UFS_POWERDOWN_PWR_MODE: return "POWERDOWN";
860 default: return "UNKNOWN";
861 }
862}
863
37113106
YG		 864u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
865{
866 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
867 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
868 (hba->ufs_version == UFSHCI_VERSION_11))
869 return UFS_UNIPRO_VER_1_41;
870 else
871 return UFS_UNIPRO_VER_1_6;
872}
873EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
874
875static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
876{
877 /*
878 * If both host and device support UniPro ver1.6 or later, PA layer
879 * parameters tuning happens during link startup itself.
880 *
881 * We can manually tune PA layer parameters if either host or device
882 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
883 * logic simple, we will only do manual tuning if local unipro version
884 * doesn't support ver1.6 or later.
885 */
886 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
887 return true;
888 else
889 return false;
890}
891
a3cd5ec5
SJ		 892static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
893{
894 int ret = 0;
895 struct ufs_clk_info *clki;
896 struct list_head *head = &hba->clk_list_head;
897 ktime_t start = ktime_get();
898 bool clk_state_changed = false;
899
900 if (!head || list_empty(head))
901 goto out;
902
903 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
904 if (ret)
905 return ret;
906
907 list_for_each_entry(clki, head, list) {
908 if (!IS_ERR_OR_NULL(clki->clk)) {
909 if (scale_up && clki->max_freq) {
910 if (clki->curr_freq == clki->max_freq)
911 continue;
912
913 clk_state_changed = true;
914 ret = clk_set_rate(clki->clk, clki->max_freq);
915 if (ret) {
916 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
917 __func__, clki->name,
918 clki->max_freq, ret);
919 break;
920 }
921 trace_ufshcd_clk_scaling(dev_name(hba->dev),
922 "scaled up", clki->name,
923 clki->curr_freq,
924 clki->max_freq);
925
926 clki->curr_freq = clki->max_freq;
927
928 } else if (!scale_up && clki->min_freq) {
929 if (clki->curr_freq == clki->min_freq)
930 continue;
931
932 clk_state_changed = true;
933 ret = clk_set_rate(clki->clk, clki->min_freq);
934 if (ret) {
935 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
936 __func__, clki->name,
937 clki->min_freq, ret);
938 break;
939 }
940 trace_ufshcd_clk_scaling(dev_name(hba->dev),
941 "scaled down", clki->name,
942 clki->curr_freq,
943 clki->min_freq);
944 clki->curr_freq = clki->min_freq;
945 }
946 }
947 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
948 clki->name, clk_get_rate(clki->clk));
949 }
950
951 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
952
953out:
954 if (clk_state_changed)
955 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
956 (scale_up ? "up" : "down"),
957 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
958 return ret;
959}
960
961/**
962 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
963 * @hba: per adapter instance
964 * @scale_up: True if scaling up and false if scaling down
965 *
966 * Returns true if scaling is required, false otherwise.
967 */
968static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
969 bool scale_up)
970{
971 struct ufs_clk_info *clki;
972 struct list_head *head = &hba->clk_list_head;
973
974 if (!head || list_empty(head))
975 return false;
976
977 list_for_each_entry(clki, head, list) {
978 if (!IS_ERR_OR_NULL(clki->clk)) {
979 if (scale_up && clki->max_freq) {
980 if (clki->curr_freq == clki->max_freq)
981 continue;
982 return true;
983 } else if (!scale_up && clki->min_freq) {
984 if (clki->curr_freq == clki->min_freq)
985 continue;
986 return true;
987 }
988 }
989 }
990
991 return false;
992}
993
994static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
995 u64 wait_timeout_us)
996{
997 unsigned long flags;
998 int ret = 0;
999 u32 tm_doorbell;
1000 u32 tr_doorbell;
1001 bool timeout = false, do_last_check = false;
1002 ktime_t start;
1003
1004 ufshcd_hold(hba, false);
1005 spin_lock_irqsave(hba->host->host_lock, flags);
1006 /*
1007 * Wait for all the outstanding tasks/transfer requests.
1008 * Verify by checking the doorbell registers are clear.
1009 */
1010 start = ktime_get();
1011 do {
1012 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1013 ret = -EBUSY;
1014 goto out;
1015 }
1016
1017 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1018 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1019 if (!tm_doorbell && !tr_doorbell) {
1020 timeout = false;
1021 break;
1022 } else if (do_last_check) {
1023 break;
1024 }
1025
1026 spin_unlock_irqrestore(hba->host->host_lock, flags);
1027 schedule();
1028 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1029 wait_timeout_us) {
1030 timeout = true;
1031 /*
1032 * We might have scheduled out for long time so make
1033 * sure to check if doorbells are cleared by this time
1034 * or not.
1035 */
1036 do_last_check = true;
1037 }
1038 spin_lock_irqsave(hba->host->host_lock, flags);
1039 } while (tm_doorbell || tr_doorbell);
1040
1041 if (timeout) {
1042 dev_err(hba->dev,
1043 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1044 __func__, tm_doorbell, tr_doorbell);
1045 ret = -EBUSY;
1046 }
1047out:
1048 spin_unlock_irqrestore(hba->host->host_lock, flags);
1049 ufshcd_release(hba);
1050 return ret;
1051}
1052
1053/**
1054 * ufshcd_scale_gear - scale up/down UFS gear
1055 * @hba: per adapter instance
1056 * @scale_up: True for scaling up gear and false for scaling down
1057 *
1058 * Returns 0 for success,
1059 * Returns -EBUSY if scaling can't happen at this time
1060 * Returns non-zero for any other errors
1061 */
1062static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1063{
1064 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1065 int ret = 0;
1066 struct ufs_pa_layer_attr new_pwr_info;
1067
1068 if (scale_up) {
1069 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1070 sizeof(struct ufs_pa_layer_attr));
1071 } else {
1072 memcpy(&new_pwr_info, &hba->pwr_info,
1073 sizeof(struct ufs_pa_layer_attr));
1074
1075 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1076 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1077 /* save the current power mode */
1078 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1079 &hba->pwr_info,
1080 sizeof(struct ufs_pa_layer_attr));
1081
1082 /* scale down gear */
1083 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1084 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1085 }
1086 }
1087
1088 /* check if the power mode needs to be changed or not? */
1089 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1090
1091 if (ret)
1092 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1093 __func__, ret,
1094 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1095 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1096
1097 return ret;
1098}
1099
1100static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1101{
1102 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1103 int ret = 0;
1104 /*
1105 * make sure that there are no outstanding requests when
1106 * clock scaling is in progress
1107 */
1108 scsi_block_requests(hba->host);
1109 down_write(&hba->clk_scaling_lock);
1110 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1111 ret = -EBUSY;
1112 up_write(&hba->clk_scaling_lock);
1113 scsi_unblock_requests(hba->host);
1114 }
1115
1116 return ret;
1117}
1118
1119static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1120{
1121 up_write(&hba->clk_scaling_lock);
1122 scsi_unblock_requests(hba->host);
1123}
1124
1125/**
1126 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1127 * @hba: per adapter instance
1128 * @scale_up: True for scaling up and false for scalin down
1129 *
1130 * Returns 0 for success,
1131 * Returns -EBUSY if scaling can't happen at this time
1132 * Returns non-zero for any other errors
1133 */
1134static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1135{
1136 int ret = 0;
1137
401f1e44
SJ		 1138 /* let's not get into low power until clock scaling is completed */
1139 ufshcd_hold(hba, false);
1140
a3cd5ec5
SJ		 1141 ret = ufshcd_clock_scaling_prepare(hba);
1142 if (ret)
1143 return ret;
1144
1145 /* scale down the gear before scaling down clocks */
1146 if (!scale_up) {
1147 ret = ufshcd_scale_gear(hba, false);
1148 if (ret)
1149 goto out;
1150 }
1151
1152 ret = ufshcd_scale_clks(hba, scale_up);
1153 if (ret) {
1154 if (!scale_up)
1155 ufshcd_scale_gear(hba, true);
1156 goto out;
1157 }
1158
1159 /* scale up the gear after scaling up clocks */
1160 if (scale_up) {
1161 ret = ufshcd_scale_gear(hba, true);
1162 if (ret) {
1163 ufshcd_scale_clks(hba, false);
1164 goto out;
1165 }
1166 }
1167
1168 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1169
1170out:
1171 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1172 ufshcd_release(hba);
a3cd5ec5
SJ		 1173 return ret;
1174}
1175
401f1e44
SJ		 1176static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1177{
1178 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1179 clk_scaling.suspend_work);
1180 unsigned long irq_flags;
1181
1182 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1183 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1184 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1185 return;
1186 }
1187 hba->clk_scaling.is_suspended = true;
1188 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1189
1190 __ufshcd_suspend_clkscaling(hba);
1191}
1192
1193static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1194{
1195 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1196 clk_scaling.resume_work);
1197 unsigned long irq_flags;
1198
1199 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1200 if (!hba->clk_scaling.is_suspended) {
1201 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1202 return;
1203 }
1204 hba->clk_scaling.is_suspended = false;
1205 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1206
1207 devfreq_resume_device(hba->devfreq);
1208}
1209
a3cd5ec5
SJ		 1210static int ufshcd_devfreq_target(struct device *dev,
1211 unsigned long *freq, u32 flags)
1212{
1213 int ret = 0;
1214 struct ufs_hba *hba = dev_get_drvdata(dev);
1215 ktime_t start;
401f1e44 1216 bool scale_up, sched_clk_scaling_suspend_work = false;
a3cd5ec5
SJ		 1217 unsigned long irq_flags;
1218
1219 if (!ufshcd_is_clkscaling_supported(hba))
1220 return -EINVAL;
1221
1222 if ((*freq > 0) && (*freq < UINT_MAX)) {
1223 dev_err(hba->dev, "%s: invalid freq = %lu\n", __func__, *freq);
1224 return -EINVAL;
1225 }
1226
a3cd5ec5
SJ		 1227 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1228 if (ufshcd_eh_in_progress(hba)) {
1229 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1230 return 0;
1231 }
1232
401f1e44
SJ		 1233 if (!hba->clk_scaling.active_reqs)
1234 sched_clk_scaling_suspend_work = true;
1235
1236 scale_up = (*freq == UINT_MAX) ? true : false;
1237 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1238 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1239 ret = 0;
1240 goto out; /* no state change required */
a3cd5ec5
SJ		 1241 }
1242 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1243
1244 start = ktime_get();
a3cd5ec5
SJ		 1245 ret = ufshcd_devfreq_scale(hba, scale_up);
1246
a3cd5ec5
SJ		 1247 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1248 (scale_up ? "up" : "down"),
1249 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1250
401f1e44
SJ		 1251out:
1252 if (sched_clk_scaling_suspend_work)
1253 queue_work(hba->clk_scaling.workq,
1254 &hba->clk_scaling.suspend_work);
1255
a3cd5ec5
SJ		 1256 return ret;
1257}
1258
1259
1260static int ufshcd_devfreq_get_dev_status(struct device *dev,
1261 struct devfreq_dev_status *stat)
1262{
1263 struct ufs_hba *hba = dev_get_drvdata(dev);
1264 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1265 unsigned long flags;
1266
1267 if (!ufshcd_is_clkscaling_supported(hba))
1268 return -EINVAL;
1269
1270 memset(stat, 0, sizeof(*stat));
1271
1272 spin_lock_irqsave(hba->host->host_lock, flags);
1273 if (!scaling->window_start_t)
1274 goto start_window;
1275
1276 if (scaling->is_busy_started)
1277 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1278 scaling->busy_start_t));
1279
1280 stat->total_time = jiffies_to_usecs((long)jiffies -
1281 (long)scaling->window_start_t);
1282 stat->busy_time = scaling->tot_busy_t;
1283start_window:
1284 scaling->window_start_t = jiffies;
1285 scaling->tot_busy_t = 0;
1286
1287 if (hba->outstanding_reqs) {
1288 scaling->busy_start_t = ktime_get();
1289 scaling->is_busy_started = true;
1290 } else {
1291 scaling->busy_start_t = 0;
1292 scaling->is_busy_started = false;
1293 }
1294 spin_unlock_irqrestore(hba->host->host_lock, flags);
1295 return 0;
1296}
1297
1298static struct devfreq_dev_profile ufs_devfreq_profile = {
1299 .polling_ms = 100,
1300 .target = ufshcd_devfreq_target,
1301 .get_dev_status = ufshcd_devfreq_get_dev_status,
1302};
1303
401f1e44
SJ		 1304static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1305{
1306 unsigned long flags;
1307
1308 devfreq_suspend_device(hba->devfreq);
1309 spin_lock_irqsave(hba->host->host_lock, flags);
1310 hba->clk_scaling.window_start_t = 0;
1311 spin_unlock_irqrestore(hba->host->host_lock, flags);
1312}
a3cd5ec5 1313
a508253d
GB		 1314static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1315{
401f1e44
SJ		 1316 unsigned long flags;
1317 bool suspend = false;
1318
fcb0c4b0
ST		 1319 if (!ufshcd_is_clkscaling_supported(hba))
1320 return;
1321
401f1e44
SJ		 1322 spin_lock_irqsave(hba->host->host_lock, flags);
1323 if (!hba->clk_scaling.is_suspended) {
1324 suspend = true;
1325 hba->clk_scaling.is_suspended = true;
1326 }
1327 spin_unlock_irqrestore(hba->host->host_lock, flags);
1328
1329 if (suspend)
1330 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1331}
1332
1333static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1334{
401f1e44
SJ		 1335 unsigned long flags;
1336 bool resume = false;
1337
1338 if (!ufshcd_is_clkscaling_supported(hba))
1339 return;
1340
1341 spin_lock_irqsave(hba->host->host_lock, flags);
1342 if (hba->clk_scaling.is_suspended) {
1343 resume = true;
1344 hba->clk_scaling.is_suspended = false;
1345 }
1346 spin_unlock_irqrestore(hba->host->host_lock, flags);
1347
1348 if (resume)
1349 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1350}
1351
1352static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1353 struct device_attribute *attr, char *buf)
1354{
1355 struct ufs_hba *hba = dev_get_drvdata(dev);
1356
1357 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1358}
1359
1360static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1361 struct device_attribute *attr, const char *buf, size_t count)
1362{
1363 struct ufs_hba *hba = dev_get_drvdata(dev);
1364 u32 value;
1365 int err;
1366
1367 if (kstrtou32(buf, 0, &value))
1368 return -EINVAL;
1369
1370 value = !!value;
1371 if (value == hba->clk_scaling.is_allowed)
1372 goto out;
1373
1374 pm_runtime_get_sync(hba->dev);
1375 ufshcd_hold(hba, false);
1376
401f1e44
SJ		 1377 cancel_work_sync(&hba->clk_scaling.suspend_work);
1378 cancel_work_sync(&hba->clk_scaling.resume_work);
1379
1380 hba->clk_scaling.is_allowed = value;
1381
fcb0c4b0
ST		 1382 if (value) {
1383 ufshcd_resume_clkscaling(hba);
1384 } else {
1385 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1386 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1387 if (err)
1388 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1389 __func__, err);
1390 }
fcb0c4b0
ST		 1391
1392 ufshcd_release(hba);
1393 pm_runtime_put_sync(hba->dev);
1394out:
1395 return count;
a508253d
GB		 1396}
1397
a3cd5ec5
SJ		 1398static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1399{
1400 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1401 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1402 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1403 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1404 hba->clk_scaling.enable_attr.attr.mode = 0644;
1405 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1406 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1407}
1408
1ab27c9c
ST		 1409static void ufshcd_ungate_work(struct work_struct *work)
1410{
1411 int ret;
1412 unsigned long flags;
1413 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1414 clk_gating.ungate_work);
1415
1416 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1417
1418 spin_lock_irqsave(hba->host->host_lock, flags);
1419 if (hba->clk_gating.state == CLKS_ON) {
1420 spin_unlock_irqrestore(hba->host->host_lock, flags);
1421 goto unblock_reqs;
1422 }
1423
1424 spin_unlock_irqrestore(hba->host->host_lock, flags);
1425 ufshcd_setup_clocks(hba, true);
1426
1427 /* Exit from hibern8 */
1428 if (ufshcd_can_hibern8_during_gating(hba)) {
1429 /* Prevent gating in this path */
1430 hba->clk_gating.is_suspended = true;
1431 if (ufshcd_is_link_hibern8(hba)) {
1432 ret = ufshcd_uic_hibern8_exit(hba);
1433 if (ret)
1434 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1435 __func__, ret);
1436 else
1437 ufshcd_set_link_active(hba);
1438 }
1439 hba->clk_gating.is_suspended = false;
1440 }
1441unblock_reqs:
1442 scsi_unblock_requests(hba->host);
1443}
1444
1445/**
1446 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1447 * Also, exit from hibern8 mode and set the link as active.
1448 * @hba: per adapter instance
1449 * @async: This indicates whether caller should ungate clocks asynchronously.
1450 */
1451int ufshcd_hold(struct ufs_hba *hba, bool async)
1452{
1453 int rc = 0;
1454 unsigned long flags;
1455
1456 if (!ufshcd_is_clkgating_allowed(hba))
1457 goto out;
1ab27c9c
ST		 1458 spin_lock_irqsave(hba->host->host_lock, flags);
1459 hba->clk_gating.active_reqs++;
1460
53c12d0e
YG		 1461 if (ufshcd_eh_in_progress(hba)) {
1462 spin_unlock_irqrestore(hba->host->host_lock, flags);
1463 return 0;
1464 }
1465
856b3483 1466start:
1ab27c9c
ST		 1467 switch (hba->clk_gating.state) {
1468 case CLKS_ON:
f2a785ac
VG		 1469 /*
1470 * Wait for the ungate work to complete if in progress.
1471 * Though the clocks may be in ON state, the link could
1472 * still be in hibner8 state if hibern8 is allowed
1473 * during clock gating.
1474 * Make sure we exit hibern8 state also in addition to
1475 * clocks being ON.
1476 */
1477 if (ufshcd_can_hibern8_during_gating(hba) &&
1478 ufshcd_is_link_hibern8(hba)) {
1479 spin_unlock_irqrestore(hba->host->host_lock, flags);
1480 flush_work(&hba->clk_gating.ungate_work);
1481 spin_lock_irqsave(hba->host->host_lock, flags);
1482 goto start;
1483 }
1ab27c9c
ST		 1484 break;
1485 case REQ_CLKS_OFF:
1486 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1487 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1488 trace_ufshcd_clk_gating(dev_name(hba->dev),
1489 hba->clk_gating.state);
1ab27c9c
ST		 1490 break;
1491 }
1492 /*
1493 * If we here, it means gating work is either done or
1494 * currently running. Hence, fall through to cancel gating
1495 * work and to enable clocks.
1496 */
1497 case CLKS_OFF:
1498 scsi_block_requests(hba->host);
1499 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47
SJ		 1500 trace_ufshcd_clk_gating(dev_name(hba->dev),
1501 hba->clk_gating.state);
1ab27c9c
ST		 1502 schedule_work(&hba->clk_gating.ungate_work);
1503 /*
1504 * fall through to check if we should wait for this
1505 * work to be done or not.
1506 */
1507 case REQ_CLKS_ON:
1508 if (async) {
1509 rc = -EAGAIN;
1510 hba->clk_gating.active_reqs--;
1511 break;
1512 }
1513
1514 spin_unlock_irqrestore(hba->host->host_lock, flags);
1515 flush_work(&hba->clk_gating.ungate_work);
1516 /* Make sure state is CLKS_ON before returning */
856b3483 1517 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1518 goto start;
1519 default:
1520 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1521 __func__, hba->clk_gating.state);
1522 break;
1523 }
1524 spin_unlock_irqrestore(hba->host->host_lock, flags);
1525out:
1526 return rc;
1527}
6e3fd44d 1528EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1529
1530static void ufshcd_gate_work(struct work_struct *work)
1531{
1532 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1533 clk_gating.gate_work.work);
1534 unsigned long flags;
1535
1536 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1537 /*
1538 * In case you are here to cancel this work the gating state
1539 * would be marked as REQ_CLKS_ON. In this case save time by
1540 * skipping the gating work and exit after changing the clock
1541 * state to CLKS_ON.
1542 */
1543 if (hba->clk_gating.is_suspended ||
1544 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 1545 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1546 trace_ufshcd_clk_gating(dev_name(hba->dev),
1547 hba->clk_gating.state);
1ab27c9c
ST		 1548 goto rel_lock;
1549 }
1550
1551 if (hba->clk_gating.active_reqs
1552 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1553 || hba->lrb_in_use || hba->outstanding_tasks
1554 || hba->active_uic_cmd || hba->uic_async_done)
1555 goto rel_lock;
1556
1557 spin_unlock_irqrestore(hba->host->host_lock, flags);
1558
1559 /* put the link into hibern8 mode before turning off clocks */
1560 if (ufshcd_can_hibern8_during_gating(hba)) {
1561 if (ufshcd_uic_hibern8_enter(hba)) {
1562 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1563 trace_ufshcd_clk_gating(dev_name(hba->dev),
1564 hba->clk_gating.state);
1ab27c9c
ST		 1565 goto out;
1566 }
1567 ufshcd_set_link_hibern8(hba);
1568 }
1569
1570 if (!ufshcd_is_link_active(hba))
1571 ufshcd_setup_clocks(hba, false);
1572 else
1573 /* If link is active, device ref_clk can't be switched off */
1574 __ufshcd_setup_clocks(hba, false, true);
1575
1576 /*
1577 * In case you are here to cancel this work the gating state
1578 * would be marked as REQ_CLKS_ON. In this case keep the state
1579 * as REQ_CLKS_ON which would anyway imply that clocks are off
1580 * and a request to turn them on is pending. By doing this way,
1581 * we keep the state machine in tact and this would ultimately
1582 * prevent from doing cancel work multiple times when there are
1583 * new requests arriving before the current cancel work is done.
1584 */
1585 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1586 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1587 hba->clk_gating.state = CLKS_OFF;
7ff5ab47
SJ		 1588 trace_ufshcd_clk_gating(dev_name(hba->dev),
1589 hba->clk_gating.state);
1590 }
1ab27c9c
ST		 1591rel_lock:
1592 spin_unlock_irqrestore(hba->host->host_lock, flags);
1593out:
1594 return;
1595}
1596
1597/* host lock must be held before calling this variant */
1598static void __ufshcd_release(struct ufs_hba *hba)
1599{
1600 if (!ufshcd_is_clkgating_allowed(hba))
1601 return;
1602
1603 hba->clk_gating.active_reqs--;
1604
1605 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1606 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1607 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e
YG		 1608 || hba->active_uic_cmd || hba->uic_async_done
1609 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1610 return;
1611
1612 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1613 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1ab27c9c
ST		 1614 schedule_delayed_work(&hba->clk_gating.gate_work,
1615 msecs_to_jiffies(hba->clk_gating.delay_ms));
1616}
1617
1618void ufshcd_release(struct ufs_hba *hba)
1619{
1620 unsigned long flags;
1621
1622 spin_lock_irqsave(hba->host->host_lock, flags);
1623 __ufshcd_release(hba);
1624 spin_unlock_irqrestore(hba->host->host_lock, flags);
1625}
6e3fd44d 1626EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1627
1628static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1629 struct device_attribute *attr, char *buf)
1630{
1631 struct ufs_hba *hba = dev_get_drvdata(dev);
1632
1633 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1634}
1635
1636static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1637 struct device_attribute *attr, const char *buf, size_t count)
1638{
1639 struct ufs_hba *hba = dev_get_drvdata(dev);
1640 unsigned long flags, value;
1641
1642 if (kstrtoul(buf, 0, &value))
1643 return -EINVAL;
1644
1645 spin_lock_irqsave(hba->host->host_lock, flags);
1646 hba->clk_gating.delay_ms = value;
1647 spin_unlock_irqrestore(hba->host->host_lock, flags);
1648 return count;
1649}
1650
b427411a
ST		 1651static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1652 struct device_attribute *attr, char *buf)
1653{
1654 struct ufs_hba *hba = dev_get_drvdata(dev);
1655
1656 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1657}
1658
1659static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1660 struct device_attribute *attr, const char *buf, size_t count)
1661{
1662 struct ufs_hba *hba = dev_get_drvdata(dev);
1663 unsigned long flags;
1664 u32 value;
1665
1666 if (kstrtou32(buf, 0, &value))
1667 return -EINVAL;
1668
1669 value = !!value;
1670 if (value == hba->clk_gating.is_enabled)
1671 goto out;
1672
1673 if (value) {
1674 ufshcd_release(hba);
1675 } else {
1676 spin_lock_irqsave(hba->host->host_lock, flags);
1677 hba->clk_gating.active_reqs++;
1678 spin_unlock_irqrestore(hba->host->host_lock, flags);
1679 }
1680
1681 hba->clk_gating.is_enabled = value;
1682out:
1683 return count;
1684}
1685
1ab27c9c
ST		 1686static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1687{
1688 if (!ufshcd_is_clkgating_allowed(hba))
1689 return;
1690
1691 hba->clk_gating.delay_ms = 150;
1692 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1693 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1694
b427411a
ST		 1695 hba->clk_gating.is_enabled = true;
1696
1ab27c9c
ST		 1697 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1698 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1699 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1700 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1701 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1702 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1703 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1704
1705 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1706 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1707 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1708 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1709 hba->clk_gating.enable_attr.attr.mode = 0644;
1710 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1711 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1ab27c9c
ST		 1712}
1713
1714static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1715{
1716 if (!ufshcd_is_clkgating_allowed(hba))
1717 return;
1718 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1719 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
97cd6805
AM		 1720 cancel_work_sync(&hba->clk_gating.ungate_work);
1721 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1ab27c9c
ST		 1722}
1723
856b3483
ST		 1724/* Must be called with host lock acquired */
1725static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1726{
401f1e44
SJ		 1727 bool queue_resume_work = false;
1728
fcb0c4b0 1729 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1730 return;
1731
401f1e44
SJ		 1732 if (!hba->clk_scaling.active_reqs++)
1733 queue_resume_work = true;
1734
1735 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1736 return;
1737
1738 if (queue_resume_work)
1739 queue_work(hba->clk_scaling.workq,
1740 &hba->clk_scaling.resume_work);
1741
1742 if (!hba->clk_scaling.window_start_t) {
1743 hba->clk_scaling.window_start_t = jiffies;
1744 hba->clk_scaling.tot_busy_t = 0;
1745 hba->clk_scaling.is_busy_started = false;
1746 }
1747
856b3483
ST		 1748 if (!hba->clk_scaling.is_busy_started) {
1749 hba->clk_scaling.busy_start_t = ktime_get();
1750 hba->clk_scaling.is_busy_started = true;
1751 }
1752}
1753
1754static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1755{
1756 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1757
fcb0c4b0 1758 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1759 return;
1760
1761 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1762 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1763 scaling->busy_start_t));
8b0e1953 1764 scaling->busy_start_t = 0;
856b3483
ST		 1765 scaling->is_busy_started = false;
1766 }
1767}
7a3e97b0
SY		 1768/**
1769 * ufshcd_send_command - Send SCSI or device management commands
1770 * @hba: per adapter instance
1771 * @task_tag: Task tag of the command
1772 */
1773static inline
1774void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1775{
ff8e20c6 1776 hba->lrb[task_tag].issue_time_stamp = ktime_get();
856b3483 1777 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1778 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1779 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1780 /* Make sure that doorbell is committed immediately */
1781 wmb();
1a07f2d9 1782 ufshcd_add_command_trace(hba, task_tag, "send");
7a3e97b0
SY		 1783}
1784
1785/**
1786 * ufshcd_copy_sense_data - Copy sense data in case of check condition
1787 * @lrb - pointer to local reference block
1788 */
1789static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1790{
1791 int len;
1c2623c5
SJ		 1792 if (lrbp->sense_buffer &&
1793 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1794 int len_to_copy;
1795
5a0b0cb9 1796 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 1797 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1798
7a3e97b0 1799 memcpy(lrbp->sense_buffer,
5a0b0cb9 1800 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1801 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 1802 }
1803}
1804
68078d5c
DR		 1805/**
1806 * ufshcd_copy_query_response() - Copy the Query Response and the data
1807 * descriptor
1808 * @hba: per adapter instance
1809 * @lrb - pointer to local reference block
1810 */
1811static
c6d4a831 1812int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1813{
1814 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1815
68078d5c 1816 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1817
68078d5c
DR		 1818 /* Get the descriptor */
1819 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1820 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1821 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1822 u16 resp_len;
1823 u16 buf_len;
68078d5c
DR		 1824
1825 /* data segment length */
c6d4a831 1826 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1827 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1828 buf_len = be16_to_cpu(
1829 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1830 if (likely(buf_len >= resp_len)) {
1831 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1832 } else {
1833 dev_warn(hba->dev,
1834 "%s: Response size is bigger than buffer",
1835 __func__);
1836 return -EINVAL;
1837 }
68078d5c 1838 }
c6d4a831
DR		 1839
1840 return 0;
68078d5c
DR		 1841}
1842
7a3e97b0
SY		 1843/**
1844 * ufshcd_hba_capabilities - Read controller capabilities
1845 * @hba: per adapter instance
1846 */
1847static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1848{
b873a275 1849 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1850
1851 /* nutrs and nutmrs are 0 based values */
1852 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1853 hba->nutmrs =
1854 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1855}
1856
1857/**
6ccf44fe
SJ		 1858 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1859 * to accept UIC commands
7a3e97b0 1860 * @hba: per adapter instance
6ccf44fe
SJ		 1861 * Return true on success, else false
1862 */
1863static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1864{
1865 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1866 return true;
1867 else
1868 return false;
1869}
1870
53b3d9c3
SJ		 1871/**
1872 * ufshcd_get_upmcrs - Get the power mode change request status
1873 * @hba: Pointer to adapter instance
1874 *
1875 * This function gets the UPMCRS field of HCS register
1876 * Returns value of UPMCRS field
1877 */
1878static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1879{
1880 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1881}
1882
6ccf44fe
SJ		 1883/**
1884 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1885 * @hba: per adapter instance
1886 * @uic_cmd: UIC command
1887 *
1888 * Mutex must be held.
7a3e97b0
SY		 1889 */
1890static inline void
6ccf44fe 1891ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1892{
6ccf44fe
SJ		 1893 WARN_ON(hba->active_uic_cmd);
1894
1895 hba->active_uic_cmd = uic_cmd;
1896
7a3e97b0 1897 /* Write Args */
6ccf44fe
SJ		 1898 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1899 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1900 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1901
1902 /* Write UIC Cmd */
6ccf44fe 1903 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1904 REG_UIC_COMMAND);
7a3e97b0
SY		 1905}
1906
6ccf44fe
SJ		 1907/**
1908 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1909 * @hba: per adapter instance
1910 * @uic_command: UIC command
1911 *
1912 * Must be called with mutex held.
1913 * Returns 0 only if success.
1914 */
1915static int
1916ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1917{
1918 int ret;
1919 unsigned long flags;
1920
1921 if (wait_for_completion_timeout(&uic_cmd->done,
1922 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1923 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1924 else
1925 ret = -ETIMEDOUT;
1926
1927 spin_lock_irqsave(hba->host->host_lock, flags);
1928 hba->active_uic_cmd = NULL;
1929 spin_unlock_irqrestore(hba->host->host_lock, flags);
1930
1931 return ret;
1932}
1933
1934/**
1935 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1936 * @hba: per adapter instance
1937 * @uic_cmd: UIC command
d75f7fe4 1938 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 1939 *
1940 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1941 * with mutex held and host_lock locked.
6ccf44fe
SJ		 1942 * Returns 0 only if success.
1943 */
1944static int
d75f7fe4
YG		 1945__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1946 bool completion)
6ccf44fe 1947{
6ccf44fe
SJ		 1948 if (!ufshcd_ready_for_uic_cmd(hba)) {
1949 dev_err(hba->dev,
1950 "Controller not ready to accept UIC commands\n");
1951 return -EIO;
1952 }
1953
d75f7fe4
YG		 1954 if (completion)
1955 init_completion(&uic_cmd->done);
6ccf44fe 1956
6ccf44fe 1957 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 1958
57d104c1 1959 return 0;
6ccf44fe
SJ		 1960}
1961
1962/**
1963 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1964 * @hba: per adapter instance
1965 * @uic_cmd: UIC command
1966 *
1967 * Returns 0 only if success.
1968 */
1969static int
1970ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1971{
1972 int ret;
57d104c1 1973 unsigned long flags;
6ccf44fe 1974
1ab27c9c 1975 ufshcd_hold(hba, false);
6ccf44fe 1976 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 1977 ufshcd_add_delay_before_dme_cmd(hba);
1978
57d104c1 1979 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 1980 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 1981 spin_unlock_irqrestore(hba->host->host_lock, flags);
1982 if (!ret)
1983 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
1984
6ccf44fe
SJ		 1985 mutex_unlock(&hba->uic_cmd_mutex);
1986
1ab27c9c 1987 ufshcd_release(hba);
6ccf44fe
SJ		 1988 return ret;
1989}
1990
7a3e97b0
SY		 1991/**
1992 * ufshcd_map_sg - Map scatter-gather list to prdt
1993 * @lrbp - pointer to local reference block
1994 *
1995 * Returns 0 in case of success, non-zero value in case of failure
1996 */
75b1cc4a 1997static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 1998{
1999 struct ufshcd_sg_entry *prd_table;
2000 struct scatterlist *sg;
2001 struct scsi_cmnd *cmd;
2002 int sg_segments;
2003 int i;
2004
2005 cmd = lrbp->cmd;
2006 sg_segments = scsi_dma_map(cmd);
2007 if (sg_segments < 0)
2008 return sg_segments;
2009
2010 if (sg_segments) {
75b1cc4a
KK		 2011 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2012 lrbp->utr_descriptor_ptr->prd_table_length =
2013 cpu_to_le16((u16)(sg_segments *
2014 sizeof(struct ufshcd_sg_entry)));
2015 else
2016 lrbp->utr_descriptor_ptr->prd_table_length =
2017 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2018
2019 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2020
2021 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2022 prd_table[i].size =
2023 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2024 prd_table[i].base_addr =
2025 cpu_to_le32(lower_32_bits(sg->dma_address));
2026 prd_table[i].upper_addr =
2027 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2028 prd_table[i].reserved = 0;
7a3e97b0
SY		 2029 }
2030 } else {
2031 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2032 }
2033
2034 return 0;
2035}
2036
2037/**
2fbd009b 2038 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2039 * @hba: per adapter instance
2fbd009b 2040 * @intrs: interrupt bits
7a3e97b0 2041 */
2fbd009b 2042static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2043{
2fbd009b
SJ		 2044 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2045
2046 if (hba->ufs_version == UFSHCI_VERSION_10) {
2047 u32 rw;
2048 rw = set & INTERRUPT_MASK_RW_VER_10;
2049 set = rw | ((set ^ intrs) & intrs);
2050 } else {
2051 set |= intrs;
2052 }
2053
2054 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2055}
2056
2057/**
2058 * ufshcd_disable_intr - disable interrupts
2059 * @hba: per adapter instance
2060 * @intrs: interrupt bits
2061 */
2062static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2063{
2064 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2065
2066 if (hba->ufs_version == UFSHCI_VERSION_10) {
2067 u32 rw;
2068 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2069 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2070 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2071
2072 } else {
2073 set &= ~intrs;
7a3e97b0 2074 }
2fbd009b
SJ		 2075
2076 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2077}
2078
5a0b0cb9
SRT		 2079/**
2080 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2081 * descriptor according to request
2082 * @lrbp: pointer to local reference block
2083 * @upiu_flags: flags required in the header
2084 * @cmd_dir: requests data direction
2085 */
2086static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2087 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2088{
2089 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2090 u32 data_direction;
2091 u32 dword_0;
2092
2093 if (cmd_dir == DMA_FROM_DEVICE) {
2094 data_direction = UTP_DEVICE_TO_HOST;
2095 *upiu_flags = UPIU_CMD_FLAGS_READ;
2096 } else if (cmd_dir == DMA_TO_DEVICE) {
2097 data_direction = UTP_HOST_TO_DEVICE;
2098 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2099 } else {
2100 data_direction = UTP_NO_DATA_TRANSFER;
2101 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2102 }
2103
2104 dword_0 = data_direction | (lrbp->command_type
2105 << UPIU_COMMAND_TYPE_OFFSET);
2106 if (lrbp->intr_cmd)
2107 dword_0 |= UTP_REQ_DESC_INT_CMD;
2108
2109 /* Transfer request descriptor header fields */
2110 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2111 /* dword_1 is reserved, hence it is set to 0 */
2112 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2113 /*
2114 * assigning invalid value for command status. Controller
2115 * updates OCS on command completion, with the command
2116 * status
2117 */
2118 req_desc->header.dword_2 =
2119 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2120 /* dword_3 is reserved, hence it is set to 0 */
2121 req_desc->header.dword_3 = 0;
51047266
YG		 2122
2123 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2124}
2125
2126/**
2127 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2128 * for scsi commands
2129 * @lrbp - local reference block pointer
2130 * @upiu_flags - flags
2131 */
2132static
2133void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2134{
2135 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2136 unsigned short cdb_len;
5a0b0cb9
SRT		 2137
2138 /* command descriptor fields */
2139 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2140 UPIU_TRANSACTION_COMMAND, upiu_flags,
2141 lrbp->lun, lrbp->task_tag);
2142 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2143 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2144
2145 /* Total EHS length and Data segment length will be zero */
2146 ucd_req_ptr->header.dword_2 = 0;
2147
2148 ucd_req_ptr->sc.exp_data_transfer_len =
2149 cpu_to_be32(lrbp->cmd->sdb.length);
2150
52ac95fe
YG		 2151 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
2152 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
2153 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2154
2155 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2156}
2157
68078d5c
DR		 2158/**
2159 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2160 * for query requsts
2161 * @hba: UFS hba
2162 * @lrbp: local reference block pointer
2163 * @upiu_flags: flags
2164 */
2165static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2166 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2167{
2168 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2169 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2170 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2171 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
2172
2173 /* Query request header */
2174 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2175 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2176 lrbp->lun, lrbp->task_tag);
2177 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2178 0, query->request.query_func, 0, 0);
2179
6861285c
ZL		 2180 /* Data segment length only need for WRITE_DESC */
2181 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2182 ucd_req_ptr->header.dword_2 =
2183 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2184 else
2185 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2186
2187 /* Copy the Query Request buffer as is */
2188 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2189 QUERY_OSF_SIZE);
68078d5c
DR		 2190
2191 /* Copy the Descriptor */
c6d4a831
DR		 2192 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2193 memcpy(descp, query->descriptor, len);
2194
51047266 2195 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2196}
2197
5a0b0cb9
SRT		 2198static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2199{
2200 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2201
2202 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2203
2204 /* command descriptor fields */
2205 ucd_req_ptr->header.dword_0 =
2206 UPIU_HEADER_DWORD(
2207 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2208 /* clear rest of the fields of basic header */
2209 ucd_req_ptr->header.dword_1 = 0;
2210 ucd_req_ptr->header.dword_2 = 0;
2211
2212 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2213}
2214
7a3e97b0 2215/**
300bb13f
JP		 2216 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2217 * for Device Management Purposes
5a0b0cb9 2218 * @hba - per adapter instance
7a3e97b0
SY		 2219 * @lrb - pointer to local reference block
2220 */
300bb13f 2221static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2222{
7a3e97b0 2223 u32 upiu_flags;
5a0b0cb9 2224 int ret = 0;
7a3e97b0 2225
300bb13f
JP		 2226 if (hba->ufs_version == UFSHCI_VERSION_20)
2227 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2228 else
2229 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2230
2231 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2232 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2233 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2234 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2235 ufshcd_prepare_utp_nop_upiu(lrbp);
2236 else
2237 ret = -EINVAL;
2238
2239 return ret;
2240}
2241
2242/**
2243 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2244 * for SCSI Purposes
2245 * @hba - per adapter instance
2246 * @lrb - pointer to local reference block
2247 */
2248static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2249{
2250 u32 upiu_flags;
2251 int ret = 0;
2252
2253 if (hba->ufs_version == UFSHCI_VERSION_20)
2254 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2255 else
2256 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2257
2258 if (likely(lrbp->cmd)) {
2259 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2260 lrbp->cmd->sc_data_direction);
2261 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2262 } else {
2263 ret = -EINVAL;
2264 }
5a0b0cb9
SRT		 2265
2266 return ret;
7a3e97b0
SY		 2267}
2268
0ce147d4
SJ		 2269/*
2270 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
2271 * @scsi_lun: scsi LUN id
2272 *
2273 * Returns UPIU LUN id
2274 */
2275static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
2276{
2277 if (scsi_is_wlun(scsi_lun))
2278 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
2279 | UFS_UPIU_WLUN_ID;
2280 else
2281 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
2282}
2283
2a8fa600
SJ		 2284/**
2285 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2286 * @scsi_lun: UPIU W-LUN id
2287 *
2288 * Returns SCSI W-LUN id
2289 */
2290static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2291{
2292 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2293}
2294
7a3e97b0
SY		 2295/**
2296 * ufshcd_queuecommand - main entry point for SCSI requests
2297 * @cmd: command from SCSI Midlayer
2298 * @done: call back function
2299 *
2300 * Returns 0 for success, non-zero in case of failure
2301 */
2302static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2303{
2304 struct ufshcd_lrb *lrbp;
2305 struct ufs_hba *hba;
2306 unsigned long flags;
2307 int tag;
2308 int err = 0;
2309
2310 hba = shost_priv(host);
2311
2312 tag = cmd->request->tag;
14497328
YG		 2313 if (!ufshcd_valid_tag(hba, tag)) {
2314 dev_err(hba->dev,
2315 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2316 __func__, tag, cmd, cmd->request);
2317 BUG();
2318 }
7a3e97b0 2319
a3cd5ec5
SJ		 2320 if (!down_read_trylock(&hba->clk_scaling_lock))
2321 return SCSI_MLQUEUE_HOST_BUSY;
2322
3441da7d
SRT		 2323 spin_lock_irqsave(hba->host->host_lock, flags);
2324 switch (hba->ufshcd_state) {
2325 case UFSHCD_STATE_OPERATIONAL:
2326 break;
141f8165 2327 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2328 case UFSHCD_STATE_RESET:
7a3e97b0 2329 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2330 goto out_unlock;
2331 case UFSHCD_STATE_ERROR:
2332 set_host_byte(cmd, DID_ERROR);
2333 cmd->scsi_done(cmd);
2334 goto out_unlock;
2335 default:
2336 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2337 __func__, hba->ufshcd_state);
2338 set_host_byte(cmd, DID_BAD_TARGET);
2339 cmd->scsi_done(cmd);
2340 goto out_unlock;
7a3e97b0 2341 }
53c12d0e
YG		 2342
2343 /* if error handling is in progress, don't issue commands */
2344 if (ufshcd_eh_in_progress(hba)) {
2345 set_host_byte(cmd, DID_ERROR);
2346 cmd->scsi_done(cmd);
2347 goto out_unlock;
2348 }
3441da7d 2349 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2350
7fabb77b
GB		 2351 hba->req_abort_count = 0;
2352
5a0b0cb9
SRT		 2353 /* acquire the tag to make sure device cmds don't use it */
2354 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2355 /*
2356 * Dev manage command in progress, requeue the command.
2357 * Requeuing the command helps in cases where the request *may*
2358 * find different tag instead of waiting for dev manage command
2359 * completion.
2360 */
2361 err = SCSI_MLQUEUE_HOST_BUSY;
2362 goto out;
2363 }
2364
1ab27c9c
ST		 2365 err = ufshcd_hold(hba, true);
2366 if (err) {
2367 err = SCSI_MLQUEUE_HOST_BUSY;
2368 clear_bit_unlock(tag, &hba->lrb_in_use);
2369 goto out;
2370 }
2371 WARN_ON(hba->clk_gating.state != CLKS_ON);
2372
7a3e97b0
SY		 2373 lrbp = &hba->lrb[tag];
2374
5a0b0cb9 2375 WARN_ON(lrbp->cmd);
7a3e97b0 2376 lrbp->cmd = cmd;
dcea0bfb 2377 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 2378 lrbp->sense_buffer = cmd->sense_buffer;
2379 lrbp->task_tag = tag;
0ce147d4 2380 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2381 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2382 lrbp->req_abort_skip = false;
7a3e97b0 2383
300bb13f
JP		 2384 ufshcd_comp_scsi_upiu(hba, lrbp);
2385
75b1cc4a 2386 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2387 if (err) {
2388 lrbp->cmd = NULL;
2389 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 2390 goto out;
5a0b0cb9 2391 }
ad1a1b9c
GB		 2392 /* Make sure descriptors are ready before ringing the doorbell */
2393 wmb();
7a3e97b0
SY		 2394
2395 /* issue command to the controller */
2396 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2397 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
7a3e97b0 2398 ufshcd_send_command(hba, tag);
3441da7d 2399out_unlock:
7a3e97b0
SY		 2400 spin_unlock_irqrestore(hba->host->host_lock, flags);
2401out:
a3cd5ec5 2402 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2403 return err;
2404}
2405
5a0b0cb9
SRT		 2406static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2407 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2408{
2409 lrbp->cmd = NULL;
2410 lrbp->sense_bufflen = 0;
2411 lrbp->sense_buffer = NULL;
2412 lrbp->task_tag = tag;
2413 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2414 lrbp->intr_cmd = true; /* No interrupt aggregation */
2415 hba->dev_cmd.type = cmd_type;
2416
300bb13f 2417 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2418}
2419
2420static int
2421ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2422{
2423 int err = 0;
2424 unsigned long flags;
2425 u32 mask = 1 << tag;
2426
2427 /* clear outstanding transaction before retry */
2428 spin_lock_irqsave(hba->host->host_lock, flags);
2429 ufshcd_utrl_clear(hba, tag);
2430 spin_unlock_irqrestore(hba->host->host_lock, flags);
2431
2432 /*
2433 * wait for for h/w to clear corresponding bit in door-bell.
2434 * max. wait is 1 sec.
2435 */
2436 err = ufshcd_wait_for_register(hba,
2437 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2438 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2439
2440 return err;
2441}
2442
c6d4a831
DR		 2443static int
2444ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2445{
2446 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2447
2448 /* Get the UPIU response */
2449 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2450 UPIU_RSP_CODE_OFFSET;
2451 return query_res->response;
2452}
2453
5a0b0cb9
SRT		 2454/**
2455 * ufshcd_dev_cmd_completion() - handles device management command responses
2456 * @hba: per adapter instance
2457 * @lrbp: pointer to local reference block
2458 */
2459static int
2460ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2461{
2462 int resp;
2463 int err = 0;
2464
ff8e20c6 2465 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2466 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2467
2468 switch (resp) {
2469 case UPIU_TRANSACTION_NOP_IN:
2470 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2471 err = -EINVAL;
2472 dev_err(hba->dev, "%s: unexpected response %x\n",
2473 __func__, resp);
2474 }
2475 break;
68078d5c 2476 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2477 err = ufshcd_check_query_response(hba, lrbp);
2478 if (!err)
2479 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2480 break;
5a0b0cb9
SRT		 2481 case UPIU_TRANSACTION_REJECT_UPIU:
2482 /* TODO: handle Reject UPIU Response */
2483 err = -EPERM;
2484 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2485 __func__);
2486 break;
2487 default:
2488 err = -EINVAL;
2489 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2490 __func__, resp);
2491 break;
2492 }
2493
2494 return err;
2495}
2496
2497static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2498 struct ufshcd_lrb *lrbp, int max_timeout)
2499{
2500 int err = 0;
2501 unsigned long time_left;
2502 unsigned long flags;
2503
2504 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2505 msecs_to_jiffies(max_timeout));
2506
ad1a1b9c
GB		 2507 /* Make sure descriptors are ready before ringing the doorbell */
2508 wmb();
5a0b0cb9
SRT		 2509 spin_lock_irqsave(hba->host->host_lock, flags);
2510 hba->dev_cmd.complete = NULL;
2511 if (likely(time_left)) {
2512 err = ufshcd_get_tr_ocs(lrbp);
2513 if (!err)
2514 err = ufshcd_dev_cmd_completion(hba, lrbp);
2515 }
2516 spin_unlock_irqrestore(hba->host->host_lock, flags);
2517
2518 if (!time_left) {
2519 err = -ETIMEDOUT;
a48353f6
YG		 2520 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2521 __func__, lrbp->task_tag);
5a0b0cb9 2522 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2523 /* successfully cleared the command, retry if needed */
5a0b0cb9 2524 err = -EAGAIN;
a48353f6
YG		 2525 /*
2526 * in case of an error, after clearing the doorbell,
2527 * we also need to clear the outstanding_request
2528 * field in hba
2529 */
2530 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2531 }
2532
2533 return err;
2534}
2535
2536/**
2537 * ufshcd_get_dev_cmd_tag - Get device management command tag
2538 * @hba: per-adapter instance
2539 * @tag: pointer to variable with available slot value
2540 *
2541 * Get a free slot and lock it until device management command
2542 * completes.
2543 *
2544 * Returns false if free slot is unavailable for locking, else
2545 * return true with tag value in @tag.
2546 */
2547static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2548{
2549 int tag;
2550 bool ret = false;
2551 unsigned long tmp;
2552
2553 if (!tag_out)
2554 goto out;
2555
2556 do {
2557 tmp = ~hba->lrb_in_use;
2558 tag = find_last_bit(&tmp, hba->nutrs);
2559 if (tag >= hba->nutrs)
2560 goto out;
2561 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2562
2563 *tag_out = tag;
2564 ret = true;
2565out:
2566 return ret;
2567}
2568
2569static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2570{
2571 clear_bit_unlock(tag, &hba->lrb_in_use);
2572}
2573
2574/**
2575 * ufshcd_exec_dev_cmd - API for sending device management requests
2576 * @hba - UFS hba
2577 * @cmd_type - specifies the type (NOP, Query...)
2578 * @timeout - time in seconds
2579 *
68078d5c
DR		 2580 * NOTE: Since there is only one available tag for device management commands,
2581 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2582 */
2583static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2584 enum dev_cmd_type cmd_type, int timeout)
2585{
2586 struct ufshcd_lrb *lrbp;
2587 int err;
2588 int tag;
2589 struct completion wait;
2590 unsigned long flags;
2591
a3cd5ec5
SJ		 2592 down_read(&hba->clk_scaling_lock);
2593
5a0b0cb9
SRT		 2594 /*
2595 * Get free slot, sleep if slots are unavailable.
2596 * Even though we use wait_event() which sleeps indefinitely,
2597 * the maximum wait time is bounded by SCSI request timeout.
2598 */
2599 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2600
2601 init_completion(&wait);
2602 lrbp = &hba->lrb[tag];
2603 WARN_ON(lrbp->cmd);
2604 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2605 if (unlikely(err))
2606 goto out_put_tag;
2607
2608 hba->dev_cmd.complete = &wait;
2609
e3dfdc53
YG		 2610 /* Make sure descriptors are ready before ringing the doorbell */
2611 wmb();
5a0b0cb9 2612 spin_lock_irqsave(hba->host->host_lock, flags);
0e675efa 2613 ufshcd_vops_setup_xfer_req(hba, tag, (lrbp->cmd ? true : false));
5a0b0cb9
SRT		 2614 ufshcd_send_command(hba, tag);
2615 spin_unlock_irqrestore(hba->host->host_lock, flags);
2616
2617 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2618
2619out_put_tag:
2620 ufshcd_put_dev_cmd_tag(hba, tag);
2621 wake_up(&hba->dev_cmd.tag_wq);
a3cd5ec5 2622 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2623 return err;
2624}
2625
d44a5f98
DR		 2626/**
2627 * ufshcd_init_query() - init the query response and request parameters
2628 * @hba: per-adapter instance
2629 * @request: address of the request pointer to be initialized
2630 * @response: address of the response pointer to be initialized
2631 * @opcode: operation to perform
2632 * @idn: flag idn to access
2633 * @index: LU number to access
2634 * @selector: query/flag/descriptor further identification
2635 */
2636static inline void ufshcd_init_query(struct ufs_hba *hba,
2637 struct ufs_query_req **request, struct ufs_query_res **response,
2638 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2639{
2640 *request = &hba->dev_cmd.query.request;
2641 *response = &hba->dev_cmd.query.response;
2642 memset(*request, 0, sizeof(struct ufs_query_req));
2643 memset(*response, 0, sizeof(struct ufs_query_res));
2644 (*request)->upiu_req.opcode = opcode;
2645 (*request)->upiu_req.idn = idn;
2646 (*request)->upiu_req.index = index;
2647 (*request)->upiu_req.selector = selector;
2648}
2649
dc3c8d3a
YG		 2650static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2651 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2652{
2653 int ret;
2654 int retries;
2655
2656 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2657 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2658 if (ret)
2659 dev_dbg(hba->dev,
2660 "%s: failed with error %d, retries %d\n",
2661 __func__, ret, retries);
2662 else
2663 break;
2664 }
2665
2666 if (ret)
2667 dev_err(hba->dev,
2668 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2669 __func__, opcode, idn, ret, retries);
2670 return ret;
2671}
2672
68078d5c
DR		 2673/**
2674 * ufshcd_query_flag() - API function for sending flag query requests
2675 * hba: per-adapter instance
2676 * query_opcode: flag query to perform
2677 * idn: flag idn to access
2678 * flag_res: the flag value after the query request completes
2679 *
2680 * Returns 0 for success, non-zero in case of failure
2681 */
dc3c8d3a 2682int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2683 enum flag_idn idn, bool *flag_res)
2684{
d44a5f98
DR		 2685 struct ufs_query_req *request = NULL;
2686 struct ufs_query_res *response = NULL;
2687 int err, index = 0, selector = 0;
e5ad406c 2688 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2689
2690 BUG_ON(!hba);
2691
1ab27c9c 2692 ufshcd_hold(hba, false);
68078d5c 2693 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2694 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2695 selector);
68078d5c
DR		 2696
2697 switch (opcode) {
2698 case UPIU_QUERY_OPCODE_SET_FLAG:
2699 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2700 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2701 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2702 break;
2703 case UPIU_QUERY_OPCODE_READ_FLAG:
2704 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2705 if (!flag_res) {
2706 /* No dummy reads */
2707 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2708 __func__);
2709 err = -EINVAL;
2710 goto out_unlock;
2711 }
2712 break;
2713 default:
2714 dev_err(hba->dev,
2715 "%s: Expected query flag opcode but got = %d\n",
2716 __func__, opcode);
2717 err = -EINVAL;
2718 goto out_unlock;
2719 }
68078d5c 2720
e5ad406c 2721 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2722
2723 if (err) {
2724 dev_err(hba->dev,
2725 "%s: Sending flag query for idn %d failed, err = %d\n",
2726 __func__, idn, err);
2727 goto out_unlock;
2728 }
2729
2730 if (flag_res)
e8c8e82a 2731 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2732 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2733
2734out_unlock:
2735 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2736 ufshcd_release(hba);
68078d5c
DR		 2737 return err;
2738}
2739
66ec6d59
SRT		 2740/**
2741 * ufshcd_query_attr - API function for sending attribute requests
2742 * hba: per-adapter instance
2743 * opcode: attribute opcode
2744 * idn: attribute idn to access
2745 * index: index field
2746 * selector: selector field
2747 * attr_val: the attribute value after the query request completes
2748 *
2749 * Returns 0 for success, non-zero in case of failure
2750*/
bdbe5d2f 2751static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 2752 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2753{
d44a5f98
DR		 2754 struct ufs_query_req *request = NULL;
2755 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2756 int err;
2757
2758 BUG_ON(!hba);
2759
1ab27c9c 2760 ufshcd_hold(hba, false);
66ec6d59
SRT		 2761 if (!attr_val) {
2762 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2763 __func__, opcode);
2764 err = -EINVAL;
2765 goto out;
2766 }
2767
2768 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2769 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2770 selector);
66ec6d59
SRT		 2771
2772 switch (opcode) {
2773 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2774 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2775 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2776 break;
2777 case UPIU_QUERY_OPCODE_READ_ATTR:
2778 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2779 break;
2780 default:
2781 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2782 __func__, opcode);
2783 err = -EINVAL;
2784 goto out_unlock;
2785 }
2786
d44a5f98 2787 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2788
2789 if (err) {
4b761b58
YG		 2790 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2791 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2792 goto out_unlock;
2793 }
2794
e8c8e82a 2795 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2796
2797out_unlock:
2798 mutex_unlock(&hba->dev_cmd.lock);
2799out:
1ab27c9c 2800 ufshcd_release(hba);
66ec6d59
SRT		 2801 return err;
2802}
2803
5e86ae44
YG		 2804/**
2805 * ufshcd_query_attr_retry() - API function for sending query
2806 * attribute with retries
2807 * @hba: per-adapter instance
2808 * @opcode: attribute opcode
2809 * @idn: attribute idn to access
2810 * @index: index field
2811 * @selector: selector field
2812 * @attr_val: the attribute value after the query request
2813 * completes
2814 *
2815 * Returns 0 for success, non-zero in case of failure
2816*/
2817static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2818 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2819 u32 *attr_val)
2820{
2821 int ret = 0;
2822 u32 retries;
2823
2824 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2825 ret = ufshcd_query_attr(hba, opcode, idn, index,
2826 selector, attr_val);
2827 if (ret)
2828 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2829 __func__, ret, retries);
2830 else
2831 break;
2832 }
2833
2834 if (ret)
2835 dev_err(hba->dev,
2836 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2837 __func__, idn, ret, QUERY_REQ_RETRIES);
2838 return ret;
2839}
2840
a70e91b8 2841static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2842 enum query_opcode opcode, enum desc_idn idn, u8 index,
2843 u8 selector, u8 *desc_buf, int *buf_len)
2844{
2845 struct ufs_query_req *request = NULL;
2846 struct ufs_query_res *response = NULL;
2847 int err;
2848
2849 BUG_ON(!hba);
2850
1ab27c9c 2851 ufshcd_hold(hba, false);
d44a5f98
DR		 2852 if (!desc_buf) {
2853 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2854 __func__, opcode);
2855 err = -EINVAL;
2856 goto out;
2857 }
2858
2859 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
2860 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2861 __func__, *buf_len);
2862 err = -EINVAL;
2863 goto out;
2864 }
2865
2866 mutex_lock(&hba->dev_cmd.lock);
2867 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2868 selector);
2869 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2870 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2871
2872 switch (opcode) {
2873 case UPIU_QUERY_OPCODE_WRITE_DESC:
2874 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2875 break;
2876 case UPIU_QUERY_OPCODE_READ_DESC:
2877 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2878 break;
2879 default:
2880 dev_err(hba->dev,
2881 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2882 __func__, opcode);
2883 err = -EINVAL;
2884 goto out_unlock;
2885 }
2886
2887 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2888
2889 if (err) {
4b761b58
YG		 2890 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2891 __func__, opcode, idn, index, err);
d44a5f98
DR		 2892 goto out_unlock;
2893 }
2894
2895 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2896 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2897
2898out_unlock:
2899 mutex_unlock(&hba->dev_cmd.lock);
2900out:
1ab27c9c 2901 ufshcd_release(hba);
d44a5f98
DR		 2902 return err;
2903}
2904
a70e91b8
YG		 2905/**
2906 * ufshcd_query_descriptor_retry - API function for sending descriptor
2907 * requests
2908 * hba: per-adapter instance
2909 * opcode: attribute opcode
2910 * idn: attribute idn to access
2911 * index: index field
2912 * selector: selector field
2913 * desc_buf: the buffer that contains the descriptor
2914 * buf_len: length parameter passed to the device
2915 *
2916 * Returns 0 for success, non-zero in case of failure.
2917 * The buf_len parameter will contain, on return, the length parameter
2918 * received on the response.
2919 */
26cf9155
TW		 2920static int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2921 enum query_opcode opcode,
2922 enum desc_idn idn, u8 index,
2923 u8 selector,
2924 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 2925{
2926 int err;
2927 int retries;
2928
2929 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2930 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2931 selector, desc_buf, buf_len);
2932 if (!err || err == -EINVAL)
2933 break;
2934 }
2935
2936 return err;
2937}
a70e91b8 2938
da461cec
SJ		 2939/**
2940 * ufshcd_read_desc_param - read the specified descriptor parameter
2941 * @hba: Pointer to adapter instance
2942 * @desc_id: descriptor idn value
2943 * @desc_index: descriptor index
2944 * @param_offset: offset of the parameter to read
2945 * @param_read_buf: pointer to buffer where parameter would be read
2946 * @param_size: sizeof(param_read_buf)
2947 *
2948 * Return 0 in case of success, non-zero otherwise
2949 */
2950static int ufshcd_read_desc_param(struct ufs_hba *hba,
2951 enum desc_idn desc_id,
2952 int desc_index,
2953 u32 param_offset,
2954 u8 *param_read_buf,
2955 u32 param_size)
2956{
2957 int ret;
2958 u8 *desc_buf;
2959 u32 buff_len;
2960 bool is_kmalloc = true;
2961
2962 /* safety checks */
2963 if (desc_id >= QUERY_DESC_IDN_MAX)
2964 return -EINVAL;
2965
2966 buff_len = ufs_query_desc_max_size[desc_id];
2967 if ((param_offset + param_size) > buff_len)
2968 return -EINVAL;
2969
2970 if (!param_offset && (param_size == buff_len)) {
2971 /* memory space already available to hold full descriptor */
2972 desc_buf = param_read_buf;
2973 is_kmalloc = false;
2974 } else {
2975 /* allocate memory to hold full descriptor */
2976 desc_buf = kmalloc(buff_len, GFP_KERNEL);
2977 if (!desc_buf)
2978 return -ENOMEM;
2979 }
2980
a70e91b8
YG		 2981 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
2982 desc_id, desc_index, 0, desc_buf,
2983 &buff_len);
da461cec 2984
bde44bb6
SJ		 2985 if (ret) {
2986 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
2987 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 2988
2989 goto out;
2990 }
2991
bde44bb6
SJ		 2992 /* Sanity check */
2993 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
2994 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
2995 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
2996 ret = -EINVAL;
2997 goto out;
2998 }
2999
3000 /*
3001 * While reading variable size descriptors (like string descriptor),
3002 * some UFS devices may report the "LENGTH" (field in "Transaction
3003 * Specific fields" of Query Response UPIU) same as what was requested
3004 * in Query Request UPIU instead of reporting the actual size of the
3005 * variable size descriptor.
3006 * Although it's safe to ignore the "LENGTH" field for variable size
3007 * descriptors as we can always derive the length of the descriptor from
3008 * the descriptor header fields. Hence this change impose the length
3009 * match check only for fixed size descriptors (for which we always
3010 * request the correct size as part of Query Request UPIU).
3011 */
3012 if ((desc_id != QUERY_DESC_IDN_STRING) &&
3013 (buff_len != desc_buf[QUERY_DESC_LENGTH_OFFSET])) {
3014 dev_err(hba->dev, "%s: desc_buf length mismatch: buff_len %d, buff_len(desc_header) %d",
3015 __func__, buff_len, desc_buf[QUERY_DESC_LENGTH_OFFSET]);
3016 ret = -EINVAL;
3017 goto out;
3018 }
3019
da461cec
SJ		 3020 if (is_kmalloc)
3021 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3022out:
3023 if (is_kmalloc)
3024 kfree(desc_buf);
3025 return ret;
3026}
3027
3028static inline int ufshcd_read_desc(struct ufs_hba *hba,
3029 enum desc_idn desc_id,
3030 int desc_index,
3031 u8 *buf,
3032 u32 size)
3033{
3034 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3035}
3036
3037static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3038 u8 *buf,
3039 u32 size)
3040{
61e07359
DR		 3041 int err = 0;
3042 int retries;
3043
3044 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3045 /* Read descriptor*/
3046 err = ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
3047 if (!err)
3048 break;
3049 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
3050 }
3051
3052 return err;
da461cec
SJ		 3053}
3054
8209b6d5 3055static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG		 3056{
3057 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3058}
b573d484
YG		 3059
3060/**
3061 * ufshcd_read_string_desc - read string descriptor
3062 * @hba: pointer to adapter instance
3063 * @desc_index: descriptor index
3064 * @buf: pointer to buffer where descriptor would be read
3065 * @size: size of buf
3066 * @ascii: if true convert from unicode to ascii characters
3067 *
3068 * Return 0 in case of success, non-zero otherwise
3069 */
8209b6d5
TW		 3070#define ASCII_STD true
3071static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3072 u8 *buf, u32 size, bool ascii)
b573d484
YG		 3073{
3074 int err = 0;
3075
3076 err = ufshcd_read_desc(hba,
3077 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3078
3079 if (err) {
3080 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3081 __func__, QUERY_REQ_RETRIES, err);
3082 goto out;
3083 }
3084
3085 if (ascii) {
3086 int desc_len;
3087 int ascii_len;
3088 int i;
3089 char *buff_ascii;
3090
3091 desc_len = buf[0];
3092 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3093 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3094 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3095 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3096 __func__);
3097 err = -ENOMEM;
3098 goto out;
3099 }
3100
3101 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3102 if (!buff_ascii) {
3103 err = -ENOMEM;
fcbefc3b 3104 goto out;
b573d484
YG		 3105 }
3106
3107 /*
3108 * the descriptor contains string in UTF16 format
3109 * we need to convert to utf-8 so it can be displayed
3110 */
3111 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3112 desc_len - QUERY_DESC_HDR_SIZE,
3113 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3114
3115 /* replace non-printable or non-ASCII characters with spaces */
3116 for (i = 0; i < ascii_len; i++)
3117 ufshcd_remove_non_printable(&buff_ascii[i]);
3118
3119 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3120 size - QUERY_DESC_HDR_SIZE);
3121 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3122 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 3123 kfree(buff_ascii);
3124 }
3125out:
3126 return err;
3127}
b573d484 3128
da461cec
SJ		 3129/**
3130 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3131 * @hba: Pointer to adapter instance
3132 * @lun: lun id
3133 * @param_offset: offset of the parameter to read
3134 * @param_read_buf: pointer to buffer where parameter would be read
3135 * @param_size: sizeof(param_read_buf)
3136 *
3137 * Return 0 in case of success, non-zero otherwise
3138 */
3139static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3140 int lun,
3141 enum unit_desc_param param_offset,
3142 u8 *param_read_buf,
3143 u32 param_size)
3144{
3145 /*
3146 * Unit descriptors are only available for general purpose LUs (LUN id
3147 * from 0 to 7) and RPMB Well known LU.
3148 */
0ce147d4 3149 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 3150 return -EOPNOTSUPP;
3151
3152 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3153 param_offset, param_read_buf, param_size);
3154}
3155
7a3e97b0
SY		 3156/**
3157 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3158 * @hba: per adapter instance
3159 *
3160 * 1. Allocate DMA memory for Command Descriptor array
3161 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3162 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3163 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3164 * (UTMRDL)
3165 * 4. Allocate memory for local reference block(lrb).
3166 *
3167 * Returns 0 for success, non-zero in case of failure
3168 */
3169static int ufshcd_memory_alloc(struct ufs_hba *hba)
3170{
3171 size_t utmrdl_size, utrdl_size, ucdl_size;
3172
3173 /* Allocate memory for UTP command descriptors */
3174 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3175 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3176 ucdl_size,
3177 &hba->ucdl_dma_addr,
3178 GFP_KERNEL);
7a3e97b0
SY		 3179
3180 /*
3181 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3182 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3183 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3184 * be aligned to 128 bytes as well
3185 */
3186 if (!hba->ucdl_base_addr ||
3187 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3188 dev_err(hba->dev,
7a3e97b0
SY		 3189 "Command Descriptor Memory allocation failed\n");
3190 goto out;
3191 }
3192
3193 /*
3194 * Allocate memory for UTP Transfer descriptors
3195 * UFSHCI requires 1024 byte alignment of UTRD
3196 */
3197 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3198 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3199 utrdl_size,
3200 &hba->utrdl_dma_addr,
3201 GFP_KERNEL);
7a3e97b0
SY		 3202 if (!hba->utrdl_base_addr ||
3203 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3204 dev_err(hba->dev,
7a3e97b0
SY		 3205 "Transfer Descriptor Memory allocation failed\n");
3206 goto out;
3207 }
3208
3209 /*
3210 * Allocate memory for UTP Task Management descriptors
3211 * UFSHCI requires 1024 byte alignment of UTMRD
3212 */
3213 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3214 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3215 utmrdl_size,
3216 &hba->utmrdl_dma_addr,
3217 GFP_KERNEL);
7a3e97b0
SY		 3218 if (!hba->utmrdl_base_addr ||
3219 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3220 dev_err(hba->dev,
7a3e97b0
SY		 3221 "Task Management Descriptor Memory allocation failed\n");
3222 goto out;
3223 }
3224
3225 /* Allocate memory for local reference block */
2953f850
SJ		 3226 hba->lrb = devm_kzalloc(hba->dev,
3227 hba->nutrs * sizeof(struct ufshcd_lrb),
3228 GFP_KERNEL);
7a3e97b0 3229 if (!hba->lrb) {
3b1d0580 3230 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3231 goto out;
3232 }
3233 return 0;
3234out:
7a3e97b0
SY		 3235 return -ENOMEM;
3236}
3237
3238/**
3239 * ufshcd_host_memory_configure - configure local reference block with
3240 * memory offsets
3241 * @hba: per adapter instance
3242 *
3243 * Configure Host memory space
3244 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3245 * address.
3246 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3247 * and PRDT offset.
3248 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3249 * into local reference block.
3250 */
3251static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3252{
3253 struct utp_transfer_cmd_desc *cmd_descp;
3254 struct utp_transfer_req_desc *utrdlp;
3255 dma_addr_t cmd_desc_dma_addr;
3256 dma_addr_t cmd_desc_element_addr;
3257 u16 response_offset;
3258 u16 prdt_offset;
3259 int cmd_desc_size;
3260 int i;
3261
3262 utrdlp = hba->utrdl_base_addr;
3263 cmd_descp = hba->ucdl_base_addr;
3264
3265 response_offset =
3266 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3267 prdt_offset =
3268 offsetof(struct utp_transfer_cmd_desc, prd_table);
3269
3270 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3271 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3272
3273 for (i = 0; i < hba->nutrs; i++) {
3274 /* Configure UTRD with command descriptor base address */
3275 cmd_desc_element_addr =
3276 (cmd_desc_dma_addr + (cmd_desc_size * i));
3277 utrdlp[i].command_desc_base_addr_lo =
3278 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3279 utrdlp[i].command_desc_base_addr_hi =
3280 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3281
3282 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 3283 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3284 utrdlp[i].response_upiu_offset =
3285 cpu_to_le16(response_offset);
3286 utrdlp[i].prd_table_offset =
3287 cpu_to_le16(prdt_offset);
3288 utrdlp[i].response_upiu_length =
3289 cpu_to_le16(ALIGNED_UPIU_SIZE);
3290 } else {
3291 utrdlp[i].response_upiu_offset =
7a3e97b0 3292 cpu_to_le16((response_offset >> 2));
75b1cc4a 3293 utrdlp[i].prd_table_offset =
7a3e97b0 3294 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3295 utrdlp[i].response_upiu_length =
3ca316c5 3296 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3297 }
7a3e97b0
SY		 3298
3299 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR		 3300 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3301 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT		 3302 hba->lrb[i].ucd_req_ptr =
3303 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3304 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY		 3305 hba->lrb[i].ucd_rsp_ptr =
3306 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR		 3307 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3308 response_offset;
7a3e97b0
SY		 3309 hba->lrb[i].ucd_prdt_ptr =
3310 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR		 3311 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3312 prdt_offset;
7a3e97b0
SY		 3313 }
3314}
3315
3316/**
3317 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3318 * @hba: per adapter instance
3319 *
3320 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3321 * in order to initialize the Unipro link startup procedure.
3322 * Once the Unipro links are up, the device connected to the controller
3323 * is detected.
3324 *
3325 * Returns 0 on success, non-zero value on failure
3326 */
3327static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3328{
6ccf44fe
SJ		 3329 struct uic_command uic_cmd = {0};
3330 int ret;
7a3e97b0 3331
6ccf44fe 3332 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3333
6ccf44fe
SJ		 3334 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3335 if (ret)
ff8e20c6 3336 dev_dbg(hba->dev,
6ccf44fe
SJ		 3337 "dme-link-startup: error code %d\n", ret);
3338 return ret;
7a3e97b0
SY		 3339}
3340
cad2e03d
YG		 3341static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3342{
3343 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3344 unsigned long min_sleep_time_us;
3345
3346 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3347 return;
3348
3349 /*
3350 * last_dme_cmd_tstamp will be 0 only for 1st call to
3351 * this function
3352 */
3353 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3354 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3355 } else {
3356 unsigned long delta =
3357 (unsigned long) ktime_to_us(
3358 ktime_sub(ktime_get(),
3359 hba->last_dme_cmd_tstamp));
3360
3361 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3362 min_sleep_time_us =
3363 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3364 else
3365 return; /* no more delay required */
3366 }
3367
3368 /* allow sleep for extra 50us if needed */
3369 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3370}
3371
12b4fdb4
SJ		 3372/**
3373 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3374 * @hba: per adapter instance
3375 * @attr_sel: uic command argument1
3376 * @attr_set: attribute set type as uic command argument2
3377 * @mib_val: setting value as uic command argument3
3378 * @peer: indicate whether peer or local
3379 *
3380 * Returns 0 on success, non-zero value on failure
3381 */
3382int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3383 u8 attr_set, u32 mib_val, u8 peer)
3384{
3385 struct uic_command uic_cmd = {0};
3386 static const char *const action[] = {
3387 "dme-set",
3388 "dme-peer-set"
3389 };
3390 const char *set = action[!!peer];
3391 int ret;
64238fbd 3392 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3393
3394 uic_cmd.command = peer ?
3395 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3396 uic_cmd.argument1 = attr_sel;
3397 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3398 uic_cmd.argument3 = mib_val;
3399
64238fbd
YG		 3400 do {
3401 /* for peer attributes we retry upon failure */
3402 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3403 if (ret)
3404 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3405 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3406 } while (ret && peer && --retries);
3407
f37e9f8c 3408 if (ret)
64238fbd 3409 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3410 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3411 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3412
3413 return ret;
3414}
3415EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3416
3417/**
3418 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3419 * @hba: per adapter instance
3420 * @attr_sel: uic command argument1
3421 * @mib_val: the value of the attribute as returned by the UIC command
3422 * @peer: indicate whether peer or local
3423 *
3424 * Returns 0 on success, non-zero value on failure
3425 */
3426int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3427 u32 *mib_val, u8 peer)
3428{
3429 struct uic_command uic_cmd = {0};
3430 static const char *const action[] = {
3431 "dme-get",
3432 "dme-peer-get"
3433 };
3434 const char *get = action[!!peer];
3435 int ret;
64238fbd 3436 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3437 struct ufs_pa_layer_attr orig_pwr_info;
3438 struct ufs_pa_layer_attr temp_pwr_info;
3439 bool pwr_mode_change = false;
3440
3441 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3442 orig_pwr_info = hba->pwr_info;
3443 temp_pwr_info = orig_pwr_info;
3444
3445 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3446 orig_pwr_info.pwr_rx == FAST_MODE) {
3447 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3448 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3449 pwr_mode_change = true;
3450 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3451 orig_pwr_info.pwr_rx == SLOW_MODE) {
3452 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3453 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3454 pwr_mode_change = true;
3455 }
3456 if (pwr_mode_change) {
3457 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3458 if (ret)
3459 goto out;
3460 }
3461 }
12b4fdb4
SJ		 3462
3463 uic_cmd.command = peer ?
3464 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3465 uic_cmd.argument1 = attr_sel;
3466
64238fbd
YG		 3467 do {
3468 /* for peer attributes we retry upon failure */
3469 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3470 if (ret)
3471 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3472 get, UIC_GET_ATTR_ID(attr_sel), ret);
3473 } while (ret && peer && --retries);
3474
f37e9f8c 3475 if (ret)
64238fbd 3476 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3477 get, UIC_GET_ATTR_ID(attr_sel),
3478 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3479
64238fbd 3480 if (mib_val && !ret)
12b4fdb4 3481 *mib_val = uic_cmd.argument3;
874237f7
YG		 3482
3483 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3484 && pwr_mode_change)
3485 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3486out:
3487 return ret;
3488}
3489EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3490
53b3d9c3 3491/**
57d104c1
SJ		 3492 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3493 * state) and waits for it to take effect.
3494 *
53b3d9c3 3495 * @hba: per adapter instance
57d104c1
SJ		 3496 * @cmd: UIC command to execute
3497 *
3498 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3499 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3500 * and device UniPro link and hence it's final completion would be indicated by
3501 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3502 * addition to normal UIC command completion Status (UCCS). This function only
3503 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3504 *
3505 * Returns 0 on success, non-zero value on failure
3506 */
57d104c1 3507static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3508{
57d104c1 3509 struct completion uic_async_done;
53b3d9c3
SJ		 3510 unsigned long flags;
3511 u8 status;
3512 int ret;
d75f7fe4 3513 bool reenable_intr = false;
53b3d9c3 3514
53b3d9c3 3515 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3516 init_completion(&uic_async_done);
cad2e03d 3517 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3518
3519 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3520 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3521 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3522 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3523 /*
3524 * Make sure UIC command completion interrupt is disabled before
3525 * issuing UIC command.
3526 */
3527 wmb();
3528 reenable_intr = true;
57d104c1 3529 }
d75f7fe4
YG		 3530 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3531 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3532 if (ret) {
3533 dev_err(hba->dev,
3534 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3535 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3536 goto out;
3537 }
3538
57d104c1 3539 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3540 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3541 dev_err(hba->dev,
57d104c1
SJ		 3542 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3543 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3544 ret = -ETIMEDOUT;
3545 goto out;
3546 }
3547
3548 status = ufshcd_get_upmcrs(hba);
3549 if (status != PWR_LOCAL) {
3550 dev_err(hba->dev,
73615428 3551 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 3552 cmd->command, status);
53b3d9c3
SJ		 3553 ret = (status != PWR_OK) ? status : -1;
3554 }
3555out:
7942f7b5
VG		 3556 if (ret) {
3557 ufshcd_print_host_state(hba);
3558 ufshcd_print_pwr_info(hba);
3559 ufshcd_print_host_regs(hba);
3560 }
3561
53b3d9c3 3562 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3563 hba->active_uic_cmd = NULL;
57d104c1 3564 hba->uic_async_done = NULL;
d75f7fe4
YG		 3565 if (reenable_intr)
3566 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3567 spin_unlock_irqrestore(hba->host->host_lock, flags);
3568 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3569
53b3d9c3
SJ		 3570 return ret;
3571}
3572
57d104c1
SJ		 3573/**
3574 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3575 * using DME_SET primitives.
3576 * @hba: per adapter instance
3577 * @mode: powr mode value
3578 *
3579 * Returns 0 on success, non-zero value on failure
3580 */
3581static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3582{
3583 struct uic_command uic_cmd = {0};
1ab27c9c 3584 int ret;
57d104c1 3585
c3a2f9ee
YG		 3586 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3587 ret = ufshcd_dme_set(hba,
3588 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3589 if (ret) {
3590 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3591 __func__, ret);
3592 goto out;
3593 }
3594 }
3595
57d104c1
SJ		 3596 uic_cmd.command = UIC_CMD_DME_SET;
3597 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3598 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3599 ufshcd_hold(hba, false);
3600 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3601 ufshcd_release(hba);
57d104c1 3602
c3a2f9ee 3603out:
1ab27c9c 3604 return ret;
57d104c1
SJ		 3605}
3606
53c12d0e
YG		 3607static int ufshcd_link_recovery(struct ufs_hba *hba)
3608{
3609 int ret;
3610 unsigned long flags;
3611
3612 spin_lock_irqsave(hba->host->host_lock, flags);
3613 hba->ufshcd_state = UFSHCD_STATE_RESET;
3614 ufshcd_set_eh_in_progress(hba);
3615 spin_unlock_irqrestore(hba->host->host_lock, flags);
3616
3617 ret = ufshcd_host_reset_and_restore(hba);
3618
3619 spin_lock_irqsave(hba->host->host_lock, flags);
3620 if (ret)
3621 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3622 ufshcd_clear_eh_in_progress(hba);
3623 spin_unlock_irqrestore(hba->host->host_lock, flags);
3624
3625 if (ret)
3626 dev_err(hba->dev, "%s: link recovery failed, err %d",
3627 __func__, ret);
3628
3629 return ret;
3630}
3631
87d0b4a6 3632static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3633{
87d0b4a6 3634 int ret;
57d104c1 3635 struct uic_command uic_cmd = {0};
911a0771 3636 ktime_t start = ktime_get();
57d104c1 3637
ee32c909
KK		 3638 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3639
57d104c1 3640 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3641 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3642 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3643 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3644
53c12d0e 3645 if (ret) {
87d0b4a6
YG		 3646 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3647 __func__, ret);
3648
53c12d0e
YG		 3649 /*
3650 * If link recovery fails then return error so that caller
3651 * don't retry the hibern8 enter again.
3652 */
3653 if (ufshcd_link_recovery(hba))
3654 ret = -ENOLINK;
ee32c909
KK		 3655 } else
3656 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3657 POST_CHANGE);
53c12d0e 3658
87d0b4a6
YG		 3659 return ret;
3660}
3661
3662static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3663{
3664 int ret = 0, retries;
57d104c1 3665
87d0b4a6
YG		 3666 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3667 ret = __ufshcd_uic_hibern8_enter(hba);
3668 if (!ret || ret == -ENOLINK)
3669 goto out;
3670 }
3671out:
3672 return ret;
57d104c1
SJ		 3673}
3674
3675static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3676{
3677 struct uic_command uic_cmd = {0};
3678 int ret;
911a0771 3679 ktime_t start = ktime_get();
57d104c1 3680
ee32c909
KK		 3681 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3682
57d104c1
SJ		 3683 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3684 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3685 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3686 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3687
57d104c1 3688 if (ret) {
53c12d0e
YG		 3689 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3690 __func__, ret);
3691 ret = ufshcd_link_recovery(hba);
ff8e20c6 3692 } else {
ee32c909
KK		 3693 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3694 POST_CHANGE);
ff8e20c6
DR		 3695 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3696 hba->ufs_stats.hibern8_exit_cnt++;
3697 }
57d104c1
SJ		 3698
3699 return ret;
3700}
3701
5064636c
YG		 3702 /**
3703 * ufshcd_init_pwr_info - setting the POR (power on reset)
3704 * values in hba power info
3705 * @hba: per-adapter instance
3706 */
3707static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3708{
3709 hba->pwr_info.gear_rx = UFS_PWM_G1;
3710 hba->pwr_info.gear_tx = UFS_PWM_G1;
3711 hba->pwr_info.lane_rx = 1;
3712 hba->pwr_info.lane_tx = 1;
3713 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3714 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3715 hba->pwr_info.hs_rate = 0;
3716}
3717
d3e89bac 3718/**
7eb584db
DR		 3719 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3720 * @hba: per-adapter instance
d3e89bac 3721 */
7eb584db 3722static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3723{
7eb584db
DR		 3724 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3725
3726 if (hba->max_pwr_info.is_valid)
3727 return 0;
3728
2349b533
SJ		 3729 pwr_info->pwr_tx = FAST_MODE;
3730 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3731 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3732
3733 /* Get the connected lane count */
7eb584db
DR		 3734 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3735 &pwr_info->lane_rx);
3736 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3737 &pwr_info->lane_tx);
3738
3739 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3740 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3741 __func__,
3742 pwr_info->lane_rx,
3743 pwr_info->lane_tx);
3744 return -EINVAL;
3745 }
d3e89bac
SJ		 3746
3747 /*
3748 * First, get the maximum gears of HS speed.
3749 * If a zero value, it means there is no HSGEAR capability.
3750 * Then, get the maximum gears of PWM speed.
3751 */
7eb584db
DR		 3752 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3753 if (!pwr_info->gear_rx) {
3754 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3755 &pwr_info->gear_rx);
3756 if (!pwr_info->gear_rx) {
3757 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3758 __func__, pwr_info->gear_rx);
3759 return -EINVAL;
3760 }
2349b533 3761 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3762 }
3763
7eb584db
DR		 3764 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3765 &pwr_info->gear_tx);
3766 if (!pwr_info->gear_tx) {
d3e89bac 3767 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3768 &pwr_info->gear_tx);
3769 if (!pwr_info->gear_tx) {
3770 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3771 __func__, pwr_info->gear_tx);
3772 return -EINVAL;
3773 }
2349b533 3774 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3775 }
3776
3777 hba->max_pwr_info.is_valid = true;
3778 return 0;
3779}
3780
3781static int ufshcd_change_power_mode(struct ufs_hba *hba,
3782 struct ufs_pa_layer_attr *pwr_mode)
3783{
3784 int ret;
3785
3786 /* if already configured to the requested pwr_mode */
3787 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
3788 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
3789 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
3790 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
3791 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
3792 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
3793 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
3794 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
3795 return 0;
d3e89bac
SJ		 3796 }
3797
3798 /*
3799 * Configure attributes for power mode change with below.
3800 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
3801 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
3802 * - PA_HSSERIES
3803 */
7eb584db
DR		 3804 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
3805 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
3806 pwr_mode->lane_rx);
3807 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3808 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 3809 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 3810 else
3811 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 3812
7eb584db
DR		 3813 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
3814 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
3815 pwr_mode->lane_tx);
3816 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
3817 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 3818 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 3819 else
3820 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 3821
7eb584db
DR		 3822 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
3823 pwr_mode->pwr_tx == FASTAUTO_MODE ||
3824 pwr_mode->pwr_rx == FAST_MODE ||
3825 pwr_mode->pwr_tx == FAST_MODE)
3826 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
3827 pwr_mode->hs_rate);
d3e89bac 3828
7eb584db
DR		 3829 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
3830 | pwr_mode->pwr_tx);
3831
3832 if (ret) {
d3e89bac 3833 dev_err(hba->dev,
7eb584db
DR		 3834 "%s: power mode change failed %d\n", __func__, ret);
3835 } else {
0263bcd0
YG		 3836 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
3837 pwr_mode);
7eb584db
DR		 3838
3839 memcpy(&hba->pwr_info, pwr_mode,
3840 sizeof(struct ufs_pa_layer_attr));
3841 }
3842
3843 return ret;
3844}
3845
3846/**
3847 * ufshcd_config_pwr_mode - configure a new power mode
3848 * @hba: per-adapter instance
3849 * @desired_pwr_mode: desired power configuration
3850 */
3851static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
3852 struct ufs_pa_layer_attr *desired_pwr_mode)
3853{
3854 struct ufs_pa_layer_attr final_params = { 0 };
3855 int ret;
3856
0263bcd0
YG		 3857 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
3858 desired_pwr_mode, &final_params);
3859
3860 if (ret)
7eb584db
DR		 3861 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
3862
3863 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5
SJ		 3864 if (!ret)
3865 ufshcd_print_pwr_info(hba);
d3e89bac
SJ		 3866
3867 return ret;
3868}
3869
68078d5c
DR		 3870/**
3871 * ufshcd_complete_dev_init() - checks device readiness
3872 * hba: per-adapter instance
3873 *
3874 * Set fDeviceInit flag and poll until device toggles it.
3875 */
3876static int ufshcd_complete_dev_init(struct ufs_hba *hba)
3877{
dc3c8d3a
YG		 3878 int i;
3879 int err;
68078d5c
DR		 3880 bool flag_res = 1;
3881
dc3c8d3a
YG		 3882 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3883 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 3884 if (err) {
3885 dev_err(hba->dev,
3886 "%s setting fDeviceInit flag failed with error %d\n",
3887 __func__, err);
3888 goto out;
3889 }
3890
dc3c8d3a
YG		 3891 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
3892 for (i = 0; i < 1000 && !err && flag_res; i++)
3893 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
3894 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
3895
68078d5c
DR		 3896 if (err)
3897 dev_err(hba->dev,
3898 "%s reading fDeviceInit flag failed with error %d\n",
3899 __func__, err);
3900 else if (flag_res)
3901 dev_err(hba->dev,
3902 "%s fDeviceInit was not cleared by the device\n",
3903 __func__);
3904
3905out:
3906 return err;
3907}
3908
7a3e97b0
SY		 3909/**
3910 * ufshcd_make_hba_operational - Make UFS controller operational
3911 * @hba: per adapter instance
3912 *
3913 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 3914 * 1. Enable required interrupts
3915 * 2. Configure interrupt aggregation
897efe62 3916 * 3. Program UTRL and UTMRL base address
5c0c28a8 3917 * 4. Configure run-stop-registers
7a3e97b0
SY		 3918 *
3919 * Returns 0 on success, non-zero value on failure
3920 */
3921static int ufshcd_make_hba_operational(struct ufs_hba *hba)
3922{
3923 int err = 0;
3924 u32 reg;
3925
6ccf44fe
SJ		 3926 /* Enable required interrupts */
3927 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
3928
3929 /* Configure interrupt aggregation */
b852190e
YG		 3930 if (ufshcd_is_intr_aggr_allowed(hba))
3931 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
3932 else
3933 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 3934
3935 /* Configure UTRL and UTMRL base address registers */
3936 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
3937 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
3938 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
3939 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
3940 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
3941 REG_UTP_TASK_REQ_LIST_BASE_L);
3942 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
3943 REG_UTP_TASK_REQ_LIST_BASE_H);
3944
897efe62
YG		 3945 /*
3946 * Make sure base address and interrupt setup are updated before
3947 * enabling the run/stop registers below.
3948 */
3949 wmb();
3950
7a3e97b0
SY		 3951 /*
3952 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 3953 */
5c0c28a8 3954 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 3955 if (!(ufshcd_get_lists_status(reg))) {
3956 ufshcd_enable_run_stop_reg(hba);
3957 } else {
3b1d0580 3958 dev_err(hba->dev,
7a3e97b0
SY		 3959 "Host controller not ready to process requests");
3960 err = -EIO;
3961 goto out;
3962 }
3963
7a3e97b0
SY		 3964out:
3965 return err;
3966}
3967
596585a2
YG		 3968/**
3969 * ufshcd_hba_stop - Send controller to reset state
3970 * @hba: per adapter instance
3971 * @can_sleep: perform sleep or just spin
3972 */
3973static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
3974{
3975 int err;
3976
3977 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
3978 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
3979 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
3980 10, 1, can_sleep);
3981 if (err)
3982 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
3983}
3984
7a3e97b0
SY		 3985/**
3986 * ufshcd_hba_enable - initialize the controller
3987 * @hba: per adapter instance
3988 *
3989 * The controller resets itself and controller firmware initialization
3990 * sequence kicks off. When controller is ready it will set
3991 * the Host Controller Enable bit to 1.
3992 *
3993 * Returns 0 on success, non-zero value on failure
3994 */
3995static int ufshcd_hba_enable(struct ufs_hba *hba)
3996{
3997 int retry;
3998
3999 /*
4000 * msleep of 1 and 5 used in this function might result in msleep(20),
4001 * but it was necessary to send the UFS FPGA to reset mode during
4002 * development and testing of this driver. msleep can be changed to
4003 * mdelay and retry count can be reduced based on the controller.
4004 */
596585a2 4005 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4006 /* change controller state to "reset state" */
596585a2 4007 ufshcd_hba_stop(hba, true);
7a3e97b0 4008
57d104c1
SJ		 4009 /* UniPro link is disabled at this point */
4010 ufshcd_set_link_off(hba);
4011
0263bcd0 4012 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4013
7a3e97b0
SY		 4014 /* start controller initialization sequence */
4015 ufshcd_hba_start(hba);
4016
4017 /*
4018 * To initialize a UFS host controller HCE bit must be set to 1.
4019 * During initialization the HCE bit value changes from 1->0->1.
4020 * When the host controller completes initialization sequence
4021 * it sets the value of HCE bit to 1. The same HCE bit is read back
4022 * to check if the controller has completed initialization sequence.
4023 * So without this delay the value HCE = 1, set in the previous
4024 * instruction might be read back.
4025 * This delay can be changed based on the controller.
4026 */
4027 msleep(1);
4028
4029 /* wait for the host controller to complete initialization */
4030 retry = 10;
4031 while (ufshcd_is_hba_active(hba)) {
4032 if (retry) {
4033 retry--;
4034 } else {
3b1d0580 4035 dev_err(hba->dev,
7a3e97b0
SY		 4036 "Controller enable failed\n");
4037 return -EIO;
4038 }
4039 msleep(5);
4040 }
5c0c28a8 4041
1d337ec2 4042 /* enable UIC related interrupts */
57d104c1 4043 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4044
0263bcd0 4045 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4046
7a3e97b0
SY		 4047 return 0;
4048}
4049
7ca38cf3
YG		 4050static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4051{
4052 int tx_lanes, i, err = 0;
4053
4054 if (!peer)
4055 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4056 &tx_lanes);
4057 else
4058 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4059 &tx_lanes);
4060 for (i = 0; i < tx_lanes; i++) {
4061 if (!peer)
4062 err = ufshcd_dme_set(hba,
4063 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4064 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4065 0);
4066 else
4067 err = ufshcd_dme_peer_set(hba,
4068 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4069 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4070 0);
4071 if (err) {
4072 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4073 __func__, peer, i, err);
4074 break;
4075 }
4076 }
4077
4078 return err;
4079}
4080
4081static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4082{
4083 return ufshcd_disable_tx_lcc(hba, true);
4084}
4085
7a3e97b0 4086/**
6ccf44fe 4087 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4088 * @hba: per adapter instance
4089 *
6ccf44fe 4090 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4091 */
6ccf44fe 4092static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4093{
6ccf44fe 4094 int ret;
1d337ec2 4095 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4096 bool link_startup_again = false;
7a3e97b0 4097
7caf489b
SJ		 4098 /*
4099 * If UFS device isn't active then we will have to issue link startup
4100 * 2 times to make sure the device state move to active.
4101 */
4102 if (!ufshcd_is_ufs_dev_active(hba))
4103 link_startup_again = true;
7a3e97b0 4104
7caf489b 4105link_startup:
1d337ec2 4106 do {
0263bcd0 4107 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4108
1d337ec2 4109 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4110
1d337ec2
SRT		 4111 /* check if device is detected by inter-connect layer */
4112 if (!ret && !ufshcd_is_device_present(hba)) {
4113 dev_err(hba->dev, "%s: Device not present\n", __func__);
4114 ret = -ENXIO;
4115 goto out;
4116 }
6ccf44fe 4117
1d337ec2
SRT		 4118 /*
4119 * DME link lost indication is only received when link is up,
4120 * but we can't be sure if the link is up until link startup
4121 * succeeds. So reset the local Uni-Pro and try again.
4122 */
4123 if (ret && ufshcd_hba_enable(hba))
4124 goto out;
4125 } while (ret && retries--);
4126
4127 if (ret)
4128 /* failed to get the link up... retire */
5c0c28a8 4129 goto out;
5c0c28a8 4130
7caf489b
SJ		 4131 if (link_startup_again) {
4132 link_startup_again = false;
4133 retries = DME_LINKSTARTUP_RETRIES;
4134 goto link_startup;
4135 }
4136
d2aebb9b
SJ		 4137 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4138 ufshcd_init_pwr_info(hba);
4139 ufshcd_print_pwr_info(hba);
4140
7ca38cf3
YG		 4141 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4142 ret = ufshcd_disable_device_tx_lcc(hba);
4143 if (ret)
4144 goto out;
4145 }
4146
5c0c28a8 4147 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4148 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4149 if (ret)
4150 goto out;
7a3e97b0 4151
5c0c28a8 4152 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4153out:
7942f7b5 4154 if (ret) {
6ccf44fe 4155 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4156 ufshcd_print_host_state(hba);
4157 ufshcd_print_pwr_info(hba);
4158 ufshcd_print_host_regs(hba);
4159 }
6ccf44fe 4160 return ret;
7a3e97b0
SY		 4161}
4162
5a0b0cb9
SRT		 4163/**
4164 * ufshcd_verify_dev_init() - Verify device initialization
4165 * @hba: per-adapter instance
4166 *
4167 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4168 * device Transport Protocol (UTP) layer is ready after a reset.
4169 * If the UTP layer at the device side is not initialized, it may
4170 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4171 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4172 */
4173static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4174{
4175 int err = 0;
4176 int retries;
4177
1ab27c9c 4178 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4179 mutex_lock(&hba->dev_cmd.lock);
4180 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4181 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4182 NOP_OUT_TIMEOUT);
4183
4184 if (!err || err == -ETIMEDOUT)
4185 break;
4186
4187 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4188 }
4189 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4190 ufshcd_release(hba);
5a0b0cb9
SRT		 4191
4192 if (err)
4193 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4194 return err;
4195}
4196
0ce147d4
SJ		 4197/**
4198 * ufshcd_set_queue_depth - set lun queue depth
4199 * @sdev: pointer to SCSI device
4200 *
4201 * Read bLUQueueDepth value and activate scsi tagged command
4202 * queueing. For WLUN, queue depth is set to 1. For best-effort
4203 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4204 * value that host can queue.
4205 */
4206static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4207{
4208 int ret = 0;
4209 u8 lun_qdepth;
61e07359 4210 int retries;
0ce147d4
SJ		 4211 struct ufs_hba *hba;
4212
4213 hba = shost_priv(sdev->host);
4214
4215 lun_qdepth = hba->nutrs;
61e07359
DR		 4216 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
4217 /* Read descriptor*/
4218 ret = ufshcd_read_unit_desc_param(hba,
4219 ufshcd_scsi_to_upiu_lun(sdev->lun),
4220 UNIT_DESC_PARAM_LU_Q_DEPTH,
4221 &lun_qdepth,
4222 sizeof(lun_qdepth));
4223 if (!ret || ret == -ENOTSUPP)
4224 break;
4225
4226 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, ret);
4227 }
0ce147d4
SJ		 4228
4229 /* Some WLUN doesn't support unit descriptor */
4230 if (ret == -EOPNOTSUPP)
4231 lun_qdepth = 1;
4232 else if (!lun_qdepth)
4233 /* eventually, we can figure out the real queue depth */
4234 lun_qdepth = hba->nutrs;
4235 else
4236 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4237
4238 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4239 __func__, lun_qdepth);
db5ed4df 4240 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4241}
4242
57d104c1
SJ		 4243/*
4244 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4245 * @hba: per-adapter instance
4246 * @lun: UFS device lun id
4247 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4248 *
4249 * Returns 0 in case of success and b_lu_write_protect status would be returned
4250 * @b_lu_write_protect parameter.
4251 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4252 * Returns -EINVAL in case of invalid parameters passed to this function.
4253 */
4254static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4255 u8 lun,
4256 u8 *b_lu_write_protect)
4257{
4258 int ret;
4259
4260 if (!b_lu_write_protect)
4261 ret = -EINVAL;
4262 /*
4263 * According to UFS device spec, RPMB LU can't be write
4264 * protected so skip reading bLUWriteProtect parameter for
4265 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4266 */
4267 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4268 ret = -ENOTSUPP;
4269 else
4270 ret = ufshcd_read_unit_desc_param(hba,
4271 lun,
4272 UNIT_DESC_PARAM_LU_WR_PROTECT,
4273 b_lu_write_protect,
4274 sizeof(*b_lu_write_protect));
4275 return ret;
4276}
4277
4278/**
4279 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4280 * status
4281 * @hba: per-adapter instance
4282 * @sdev: pointer to SCSI device
4283 *
4284 */
4285static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4286 struct scsi_device *sdev)
4287{
4288 if (hba->dev_info.f_power_on_wp_en &&
4289 !hba->dev_info.is_lu_power_on_wp) {
4290 u8 b_lu_write_protect;
4291
4292 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4293 &b_lu_write_protect) &&
4294 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4295 hba->dev_info.is_lu_power_on_wp = true;
4296 }
4297}
4298
7a3e97b0
SY		 4299/**
4300 * ufshcd_slave_alloc - handle initial SCSI device configurations
4301 * @sdev: pointer to SCSI device
4302 *
4303 * Returns success
4304 */
4305static int ufshcd_slave_alloc(struct scsi_device *sdev)
4306{
4307 struct ufs_hba *hba;
4308
4309 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4310
4311 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4312 sdev->use_10_for_ms = 1;
7a3e97b0 4313
e8e7f271
SRT		 4314 /* allow SCSI layer to restart the device in case of errors */
4315 sdev->allow_restart = 1;
4264fd61 4316
b2a6c522
SRT		 4317 /* REPORT SUPPORTED OPERATION CODES is not supported */
4318 sdev->no_report_opcodes = 1;
4319
e8e7f271 4320
0ce147d4 4321 ufshcd_set_queue_depth(sdev);
4264fd61 4322
57d104c1
SJ		 4323 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4324
7a3e97b0
SY		 4325 return 0;
4326}
4327
4264fd61
SRT		 4328/**
4329 * ufshcd_change_queue_depth - change queue depth
4330 * @sdev: pointer to SCSI device
4331 * @depth: required depth to set
4264fd61 4332 *
db5ed4df 4333 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4334 */
db5ed4df 4335static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4336{
4337 struct ufs_hba *hba = shost_priv(sdev->host);
4338
4339 if (depth > hba->nutrs)
4340 depth = hba->nutrs;
db5ed4df 4341 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4342}
4343
eeda4749
AM		 4344/**
4345 * ufshcd_slave_configure - adjust SCSI device configurations
4346 * @sdev: pointer to SCSI device
4347 */
4348static int ufshcd_slave_configure(struct scsi_device *sdev)
4349{
4350 struct request_queue *q = sdev->request_queue;
4351
4352 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4353 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
4354
4355 return 0;
4356}
4357
7a3e97b0
SY		 4358/**
4359 * ufshcd_slave_destroy - remove SCSI device configurations
4360 * @sdev: pointer to SCSI device
4361 */
4362static void ufshcd_slave_destroy(struct scsi_device *sdev)
4363{
4364 struct ufs_hba *hba;
4365
4366 hba = shost_priv(sdev->host);
0ce147d4 4367 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4368 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4369 unsigned long flags;
4370
4371 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4372 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4373 spin_unlock_irqrestore(hba->host->host_lock, flags);
4374 }
7a3e97b0
SY		 4375}
4376
4377/**
4378 * ufshcd_task_req_compl - handle task management request completion
4379 * @hba: per adapter instance
4380 * @index: index of the completed request
e2933132 4381 * @resp: task management service response
7a3e97b0 4382 *
e2933132 4383 * Returns non-zero value on error, zero on success
7a3e97b0 4384 */
e2933132 4385static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 4386{
4387 struct utp_task_req_desc *task_req_descp;
4388 struct utp_upiu_task_rsp *task_rsp_upiup;
4389 unsigned long flags;
4390 int ocs_value;
4391 int task_result;
4392
4393 spin_lock_irqsave(hba->host->host_lock, flags);
4394
4395 /* Clear completed tasks from outstanding_tasks */
4396 __clear_bit(index, &hba->outstanding_tasks);
4397
4398 task_req_descp = hba->utmrdl_base_addr;
4399 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
4400
4401 if (ocs_value == OCS_SUCCESS) {
4402 task_rsp_upiup = (struct utp_upiu_task_rsp *)
4403 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 4404 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
4405 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 4406 if (resp)
4407 *resp = (u8)task_result;
7a3e97b0 4408 } else {
e2933132
SRT		 4409 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
4410 __func__, ocs_value);
7a3e97b0
SY		 4411 }
4412 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 4413
4414 return ocs_value;
7a3e97b0
SY		 4415}
4416
7a3e97b0
SY		 4417/**
4418 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
4419 * @lrb: pointer to local reference block of completed command
4420 * @scsi_status: SCSI command status
4421 *
4422 * Returns value base on SCSI command status
4423 */
4424static inline int
4425ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4426{
4427 int result = 0;
4428
4429 switch (scsi_status) {
7a3e97b0 4430 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 4431 ufshcd_copy_sense_data(lrbp);
4432 case SAM_STAT_GOOD:
7a3e97b0
SY		 4433 result |= DID_OK << 16 |
4434 COMMAND_COMPLETE << 8 |
1c2623c5 4435 scsi_status;
7a3e97b0
SY		 4436 break;
4437 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4438 case SAM_STAT_BUSY:
7a3e97b0 4439 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4440 ufshcd_copy_sense_data(lrbp);
4441 result |= scsi_status;
7a3e97b0
SY		 4442 break;
4443 default:
4444 result |= DID_ERROR << 16;
4445 break;
4446 } /* end of switch */
4447
4448 return result;
4449}
4450
4451/**
4452 * ufshcd_transfer_rsp_status - Get overall status of the response
4453 * @hba: per adapter instance
4454 * @lrb: pointer to local reference block of completed command
4455 *
4456 * Returns result of the command to notify SCSI midlayer
4457 */
4458static inline int
4459ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4460{
4461 int result = 0;
4462 int scsi_status;
4463 int ocs;
4464
4465 /* overall command status of utrd */
4466 ocs = ufshcd_get_tr_ocs(lrbp);
4467
4468 switch (ocs) {
4469 case OCS_SUCCESS:
5a0b0cb9 4470 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4471 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4472 switch (result) {
4473 case UPIU_TRANSACTION_RESPONSE:
4474 /*
4475 * get the response UPIU result to extract
4476 * the SCSI command status
4477 */
4478 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4479
4480 /*
4481 * get the result based on SCSI status response
4482 * to notify the SCSI midlayer of the command status
4483 */
4484 scsi_status = result & MASK_SCSI_STATUS;
4485 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4486
f05ac2e5
YG		 4487 /*
4488 * Currently we are only supporting BKOPs exception
4489 * events hence we can ignore BKOPs exception event
4490 * during power management callbacks. BKOPs exception
4491 * event is not expected to be raised in runtime suspend
4492 * callback as it allows the urgent bkops.
4493 * During system suspend, we are anyway forcefully
4494 * disabling the bkops and if urgent bkops is needed
4495 * it will be enabled on system resume. Long term
4496 * solution could be to abort the system suspend if
4497 * UFS device needs urgent BKOPs.
4498 */
4499 if (!hba->pm_op_in_progress &&
4500 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
66ec6d59 4501 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 4502 break;
4503 case UPIU_TRANSACTION_REJECT_UPIU:
4504 /* TODO: handle Reject UPIU Response */
4505 result = DID_ERROR << 16;
3b1d0580 4506 dev_err(hba->dev,
5a0b0cb9
SRT		 4507 "Reject UPIU not fully implemented\n");
4508 break;
4509 default:
4510 result = DID_ERROR << 16;
4511 dev_err(hba->dev,
4512 "Unexpected request response code = %x\n",
4513 result);
7a3e97b0
SY		 4514 break;
4515 }
7a3e97b0
SY		 4516 break;
4517 case OCS_ABORTED:
4518 result |= DID_ABORT << 16;
4519 break;
e8e7f271
SRT		 4520 case OCS_INVALID_COMMAND_STATUS:
4521 result |= DID_REQUEUE << 16;
4522 break;
7a3e97b0
SY		 4523 case OCS_INVALID_CMD_TABLE_ATTR:
4524 case OCS_INVALID_PRDT_ATTR:
4525 case OCS_MISMATCH_DATA_BUF_SIZE:
4526 case OCS_MISMATCH_RESP_UPIU_SIZE:
4527 case OCS_PEER_COMM_FAILURE:
4528 case OCS_FATAL_ERROR:
4529 default:
4530 result |= DID_ERROR << 16;
3b1d0580 4531 dev_err(hba->dev,
ff8e20c6
DR		 4532 "OCS error from controller = %x for tag %d\n",
4533 ocs, lrbp->task_tag);
4534 ufshcd_print_host_regs(hba);
6ba65588 4535 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4536 break;
4537 } /* end of switch */
4538
66cc820f
DR		 4539 if (host_byte(result) != DID_OK)
4540 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4541 return result;
4542}
4543
6ccf44fe
SJ		 4544/**
4545 * ufshcd_uic_cmd_compl - handle completion of uic command
4546 * @hba: per adapter instance
53b3d9c3 4547 * @intr_status: interrupt status generated by the controller
6ccf44fe 4548 */
53b3d9c3 4549static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4550{
53b3d9c3 4551 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4552 hba->active_uic_cmd->argument2 |=
4553 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4554 hba->active_uic_cmd->argument3 =
4555 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 4556 complete(&hba->active_uic_cmd->done);
4557 }
53b3d9c3 4558
57d104c1
SJ		 4559 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4560 complete(hba->uic_async_done);
6ccf44fe
SJ		 4561}
4562
7a3e97b0 4563/**
9a47ec7c 4564 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4565 * @hba: per adapter instance
9a47ec7c 4566 * @completed_reqs: requests to complete
7a3e97b0 4567 */
9a47ec7c
YG		 4568static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
4569 unsigned long completed_reqs)
7a3e97b0 4570{
5a0b0cb9
SRT		 4571 struct ufshcd_lrb *lrbp;
4572 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4573 int result;
4574 int index;
e9d501b1 4575
e9d501b1
DR		 4576 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4577 lrbp = &hba->lrb[index];
4578 cmd = lrbp->cmd;
4579 if (cmd) {
1a07f2d9 4580 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4581 result = ufshcd_transfer_rsp_status(hba, lrbp);
4582 scsi_dma_unmap(cmd);
4583 cmd->result = result;
4584 /* Mark completed command as NULL in LRB */
4585 lrbp->cmd = NULL;
4586 clear_bit_unlock(index, &hba->lrb_in_use);
4587 /* Do not touch lrbp after scsi done */
4588 cmd->scsi_done(cmd);
1ab27c9c 4589 __ufshcd_release(hba);
300bb13f
JP		 4590 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4591 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 4592 if (hba->dev_cmd.complete) {
4593 ufshcd_add_command_trace(hba, index,
4594 "dev_complete");
e9d501b1 4595 complete(hba->dev_cmd.complete);
1a07f2d9 4596 }
e9d501b1 4597 }
401f1e44
SJ		 4598 if (ufshcd_is_clkscaling_supported(hba))
4599 hba->clk_scaling.active_reqs--;
4600 if (ufshcd_is_clkscaling_supported(hba))
4601 hba->clk_scaling.active_reqs--;
e9d501b1 4602 }
7a3e97b0
SY		 4603
4604 /* clear corresponding bits of completed commands */
4605 hba->outstanding_reqs ^= completed_reqs;
4606
856b3483
ST		 4607 ufshcd_clk_scaling_update_busy(hba);
4608
5a0b0cb9
SRT		 4609 /* we might have free'd some tags above */
4610 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 4611}
4612
9a47ec7c
YG		 4613/**
4614 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4615 * @hba: per adapter instance
4616 */
4617static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4618{
4619 unsigned long completed_reqs;
4620 u32 tr_doorbell;
4621
4622 /* Resetting interrupt aggregation counters first and reading the
4623 * DOOR_BELL afterward allows us to handle all the completed requests.
4624 * In order to prevent other interrupts starvation the DB is read once
4625 * after reset. The down side of this solution is the possibility of
4626 * false interrupt if device completes another request after resetting
4627 * aggregation and before reading the DB.
4628 */
4629 if (ufshcd_is_intr_aggr_allowed(hba))
4630 ufshcd_reset_intr_aggr(hba);
4631
4632 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4633 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4634
4635 __ufshcd_transfer_req_compl(hba, completed_reqs);
4636}
4637
66ec6d59
SRT		 4638/**
4639 * ufshcd_disable_ee - disable exception event
4640 * @hba: per-adapter instance
4641 * @mask: exception event to disable
4642 *
4643 * Disables exception event in the device so that the EVENT_ALERT
4644 * bit is not set.
4645 *
4646 * Returns zero on success, non-zero error value on failure.
4647 */
4648static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4649{
4650 int err = 0;
4651 u32 val;
4652
4653 if (!(hba->ee_ctrl_mask & mask))
4654 goto out;
4655
4656 val = hba->ee_ctrl_mask & ~mask;
4657 val &= 0xFFFF; /* 2 bytes */
5e86ae44 4658 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4659 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4660 if (!err)
4661 hba->ee_ctrl_mask &= ~mask;
4662out:
4663 return err;
4664}
4665
4666/**
4667 * ufshcd_enable_ee - enable exception event
4668 * @hba: per-adapter instance
4669 * @mask: exception event to enable
4670 *
4671 * Enable corresponding exception event in the device to allow
4672 * device to alert host in critical scenarios.
4673 *
4674 * Returns zero on success, non-zero error value on failure.
4675 */
4676static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4677{
4678 int err = 0;
4679 u32 val;
4680
4681 if (hba->ee_ctrl_mask & mask)
4682 goto out;
4683
4684 val = hba->ee_ctrl_mask | mask;
4685 val &= 0xFFFF; /* 2 bytes */
5e86ae44 4686 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4687 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4688 if (!err)
4689 hba->ee_ctrl_mask |= mask;
4690out:
4691 return err;
4692}
4693
4694/**
4695 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4696 * @hba: per-adapter instance
4697 *
4698 * Allow device to manage background operations on its own. Enabling
4699 * this might lead to inconsistent latencies during normal data transfers
4700 * as the device is allowed to manage its own way of handling background
4701 * operations.
4702 *
4703 * Returns zero on success, non-zero on failure.
4704 */
4705static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4706{
4707 int err = 0;
4708
4709 if (hba->auto_bkops_enabled)
4710 goto out;
4711
dc3c8d3a 4712 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4713 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4714 if (err) {
4715 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4716 __func__, err);
4717 goto out;
4718 }
4719
4720 hba->auto_bkops_enabled = true;
7ff5ab47 4721 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4722
4723 /* No need of URGENT_BKOPS exception from the device */
4724 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4725 if (err)
4726 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4727 __func__, err);
4728out:
4729 return err;
4730}
4731
4732/**
4733 * ufshcd_disable_auto_bkops - block device in doing background operations
4734 * @hba: per-adapter instance
4735 *
4736 * Disabling background operations improves command response latency but
4737 * has drawback of device moving into critical state where the device is
4738 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4739 * host is idle so that BKOPS are managed effectively without any negative
4740 * impacts.
4741 *
4742 * Returns zero on success, non-zero on failure.
4743 */
4744static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
4745{
4746 int err = 0;
4747
4748 if (!hba->auto_bkops_enabled)
4749 goto out;
4750
4751 /*
4752 * If host assisted BKOPs is to be enabled, make sure
4753 * urgent bkops exception is allowed.
4754 */
4755 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
4756 if (err) {
4757 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
4758 __func__, err);
4759 goto out;
4760 }
4761
dc3c8d3a 4762 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 4763 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4764 if (err) {
4765 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
4766 __func__, err);
4767 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4768 goto out;
4769 }
4770
4771 hba->auto_bkops_enabled = false;
7ff5ab47 4772 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT		 4773out:
4774 return err;
4775}
4776
4777/**
4e768e76 4778 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 4779 * @hba: per adapter instance
4780 *
4781 * After a device reset the device may toggle the BKOPS_EN flag
4782 * to default value. The s/w tracking variables should be updated
4e768e76
SJ		 4783 * as well. This function would change the auto-bkops state based on
4784 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 4785 */
4e768e76 4786static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 4787{
4e768e76
SJ		 4788 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
4789 hba->auto_bkops_enabled = false;
4790 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
4791 ufshcd_enable_auto_bkops(hba);
4792 } else {
4793 hba->auto_bkops_enabled = true;
4794 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
4795 ufshcd_disable_auto_bkops(hba);
4796 }
66ec6d59
SRT		 4797}
4798
4799static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
4800{
5e86ae44 4801 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4802 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
4803}
4804
4805/**
57d104c1 4806 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 4807 * @hba: per-adapter instance
57d104c1 4808 * @status: bkops_status value
66ec6d59 4809 *
57d104c1
SJ		 4810 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
4811 * flag in the device to permit background operations if the device
4812 * bkops_status is greater than or equal to "status" argument passed to
4813 * this function, disable otherwise.
4814 *
4815 * Returns 0 for success, non-zero in case of failure.
4816 *
4817 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
4818 * to know whether auto bkops is enabled or disabled after this function
4819 * returns control to it.
66ec6d59 4820 */
57d104c1
SJ		 4821static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
4822 enum bkops_status status)
66ec6d59
SRT		 4823{
4824 int err;
57d104c1 4825 u32 curr_status = 0;
66ec6d59 4826
57d104c1 4827 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 4828 if (err) {
4829 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4830 __func__, err);
4831 goto out;
57d104c1
SJ		 4832 } else if (curr_status > BKOPS_STATUS_MAX) {
4833 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
4834 __func__, curr_status);
4835 err = -EINVAL;
4836 goto out;
66ec6d59
SRT		 4837 }
4838
57d104c1 4839 if (curr_status >= status)
66ec6d59 4840 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 4841 else
4842 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 4843out:
4844 return err;
4845}
4846
57d104c1
SJ		 4847/**
4848 * ufshcd_urgent_bkops - handle urgent bkops exception event
4849 * @hba: per-adapter instance
4850 *
4851 * Enable fBackgroundOpsEn flag in the device to permit background
4852 * operations.
4853 *
4854 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
4855 * and negative error value for any other failure.
4856 */
4857static int ufshcd_urgent_bkops(struct ufs_hba *hba)
4858{
afdfff59 4859 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 4860}
4861
66ec6d59
SRT		 4862static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
4863{
5e86ae44 4864 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 4865 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
4866}
4867
afdfff59
YG		 4868static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
4869{
4870 int err;
4871 u32 curr_status = 0;
4872
4873 if (hba->is_urgent_bkops_lvl_checked)
4874 goto enable_auto_bkops;
4875
4876 err = ufshcd_get_bkops_status(hba, &curr_status);
4877 if (err) {
4878 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
4879 __func__, err);
4880 goto out;
4881 }
4882
4883 /*
4884 * We are seeing that some devices are raising the urgent bkops
4885 * exception events even when BKOPS status doesn't indicate performace
4886 * impacted or critical. Handle these device by determining their urgent
4887 * bkops status at runtime.
4888 */
4889 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
4890 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
4891 __func__, curr_status);
4892 /* update the current status as the urgent bkops level */
4893 hba->urgent_bkops_lvl = curr_status;
4894 hba->is_urgent_bkops_lvl_checked = true;
4895 }
4896
4897enable_auto_bkops:
4898 err = ufshcd_enable_auto_bkops(hba);
4899out:
4900 if (err < 0)
4901 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
4902 __func__, err);
4903}
4904
66ec6d59
SRT		 4905/**
4906 * ufshcd_exception_event_handler - handle exceptions raised by device
4907 * @work: pointer to work data
4908 *
4909 * Read bExceptionEventStatus attribute from the device and handle the
4910 * exception event accordingly.
4911 */
4912static void ufshcd_exception_event_handler(struct work_struct *work)
4913{
4914 struct ufs_hba *hba;
4915 int err;
4916 u32 status = 0;
4917 hba = container_of(work, struct ufs_hba, eeh_work);
4918
62694735 4919 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 4920 err = ufshcd_get_ee_status(hba, &status);
4921 if (err) {
4922 dev_err(hba->dev, "%s: failed to get exception status %d\n",
4923 __func__, err);
4924 goto out;
4925 }
4926
4927 status &= hba->ee_ctrl_mask;
afdfff59
YG		 4928
4929 if (status & MASK_EE_URGENT_BKOPS)
4930 ufshcd_bkops_exception_event_handler(hba);
4931
66ec6d59 4932out:
62694735 4933 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 4934 return;
4935}
4936
9a47ec7c
YG		 4937/* Complete requests that have door-bell cleared */
4938static void ufshcd_complete_requests(struct ufs_hba *hba)
4939{
4940 ufshcd_transfer_req_compl(hba);
4941 ufshcd_tmc_handler(hba);
4942}
4943
583fa62d
YG		 4944/**
4945 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
4946 * to recover from the DL NAC errors or not.
4947 * @hba: per-adapter instance
4948 *
4949 * Returns true if error handling is required, false otherwise
4950 */
4951static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
4952{
4953 unsigned long flags;
4954 bool err_handling = true;
4955
4956 spin_lock_irqsave(hba->host->host_lock, flags);
4957 /*
4958 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
4959 * device fatal error and/or DL NAC & REPLAY timeout errors.
4960 */
4961 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
4962 goto out;
4963
4964 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
4965 ((hba->saved_err & UIC_ERROR) &&
4966 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
4967 goto out;
4968
4969 if ((hba->saved_err & UIC_ERROR) &&
4970 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
4971 int err;
4972 /*
4973 * wait for 50ms to see if we can get any other errors or not.
4974 */
4975 spin_unlock_irqrestore(hba->host->host_lock, flags);
4976 msleep(50);
4977 spin_lock_irqsave(hba->host->host_lock, flags);
4978
4979 /*
4980 * now check if we have got any other severe errors other than
4981 * DL NAC error?
4982 */
4983 if ((hba->saved_err & INT_FATAL_ERRORS) ||
4984 ((hba->saved_err & UIC_ERROR) &&
4985 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
4986 goto out;
4987
4988 /*
4989 * As DL NAC is the only error received so far, send out NOP
4990 * command to confirm if link is still active or not.
4991 * - If we don't get any response then do error recovery.
4992 * - If we get response then clear the DL NAC error bit.
4993 */
4994
4995 spin_unlock_irqrestore(hba->host->host_lock, flags);
4996 err = ufshcd_verify_dev_init(hba);
4997 spin_lock_irqsave(hba->host->host_lock, flags);
4998
4999 if (err)
5000 goto out;
5001
5002 /* Link seems to be alive hence ignore the DL NAC errors */
5003 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5004 hba->saved_err &= ~UIC_ERROR;
5005 /* clear NAC error */
5006 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5007 if (!hba->saved_uic_err) {
5008 err_handling = false;
5009 goto out;
5010 }
5011 }
5012out:
5013 spin_unlock_irqrestore(hba->host->host_lock, flags);
5014 return err_handling;
5015}
5016
7a3e97b0 5017/**
e8e7f271
SRT		 5018 * ufshcd_err_handler - handle UFS errors that require s/w attention
5019 * @work: pointer to work structure
7a3e97b0 5020 */
e8e7f271 5021static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5022{
5023 struct ufs_hba *hba;
e8e7f271
SRT		 5024 unsigned long flags;
5025 u32 err_xfer = 0;
5026 u32 err_tm = 0;
5027 int err = 0;
5028 int tag;
9a47ec7c 5029 bool needs_reset = false;
e8e7f271
SRT		 5030
5031 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5032
62694735 5033 pm_runtime_get_sync(hba->dev);
1ab27c9c 5034 ufshcd_hold(hba, false);
e8e7f271
SRT		 5035
5036 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5037 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5038 goto out;
e8e7f271
SRT		 5039
5040 hba->ufshcd_state = UFSHCD_STATE_RESET;
5041 ufshcd_set_eh_in_progress(hba);
5042
5043 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5044 ufshcd_complete_requests(hba);
583fa62d
YG		 5045
5046 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5047 bool ret;
5048
5049 spin_unlock_irqrestore(hba->host->host_lock, flags);
5050 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5051 ret = ufshcd_quirk_dl_nac_errors(hba);
5052 spin_lock_irqsave(hba->host->host_lock, flags);
5053 if (!ret)
5054 goto skip_err_handling;
5055 }
9a47ec7c
YG		 5056 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5057 ((hba->saved_err & UIC_ERROR) &&
5058 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5059 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5060 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5061 needs_reset = true;
e8e7f271 5062
9a47ec7c
YG		 5063 /*
5064 * if host reset is required then skip clearing the pending
5065 * transfers forcefully because they will automatically get
5066 * cleared after link startup.
5067 */
5068 if (needs_reset)
5069 goto skip_pending_xfer_clear;
5070
5071 /* release lock as clear command might sleep */
5072 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5073 /* Clear pending transfer requests */
9a47ec7c
YG		 5074 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5075 if (ufshcd_clear_cmd(hba, tag)) {
5076 err_xfer = true;
5077 goto lock_skip_pending_xfer_clear;
5078 }
5079 }
e8e7f271
SRT		 5080
5081 /* Clear pending task management requests */
9a47ec7c
YG		 5082 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5083 if (ufshcd_clear_tm_cmd(hba, tag)) {
5084 err_tm = true;
5085 goto lock_skip_pending_xfer_clear;
5086 }
5087 }
e8e7f271 5088
9a47ec7c 5089lock_skip_pending_xfer_clear:
e8e7f271 5090 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5091
9a47ec7c
YG		 5092 /* Complete the requests that are cleared by s/w */
5093 ufshcd_complete_requests(hba);
5094
5095 if (err_xfer || err_tm)
5096 needs_reset = true;
5097
5098skip_pending_xfer_clear:
e8e7f271 5099 /* Fatal errors need reset */
9a47ec7c
YG		 5100 if (needs_reset) {
5101 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5102
5103 /*
5104 * ufshcd_reset_and_restore() does the link reinitialization
5105 * which will need atleast one empty doorbell slot to send the
5106 * device management commands (NOP and query commands).
5107 * If there is no slot empty at this moment then free up last
5108 * slot forcefully.
5109 */
5110 if (hba->outstanding_reqs == max_doorbells)
5111 __ufshcd_transfer_req_compl(hba,
5112 (1UL << (hba->nutrs - 1)));
5113
5114 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5115 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5116 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271
SRT		 5117 if (err) {
5118 dev_err(hba->dev, "%s: reset and restore failed\n",
5119 __func__);
5120 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5121 }
5122 /*
5123 * Inform scsi mid-layer that we did reset and allow to handle
5124 * Unit Attention properly.
5125 */
5126 scsi_report_bus_reset(hba->host, 0);
5127 hba->saved_err = 0;
5128 hba->saved_uic_err = 0;
5129 }
9a47ec7c 5130
583fa62d 5131skip_err_handling:
9a47ec7c
YG		 5132 if (!needs_reset) {
5133 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5134 if (hba->saved_err || hba->saved_uic_err)
5135 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5136 __func__, hba->saved_err, hba->saved_uic_err);
5137 }
5138
e8e7f271
SRT		 5139 ufshcd_clear_eh_in_progress(hba);
5140
5141out:
9a47ec7c 5142 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5143 scsi_unblock_requests(hba->host);
1ab27c9c 5144 ufshcd_release(hba);
62694735 5145 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5146}
5147
ff8e20c6
DR		 5148static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5149 u32 reg)
5150{
5151 reg_hist->reg[reg_hist->pos] = reg;
5152 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5153 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5154}
5155
7a3e97b0 5156/**
e8e7f271
SRT		 5157 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5158 * @hba: per-adapter instance
7a3e97b0 5159 */
e8e7f271 5160static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5161{
5162 u32 reg;
5163
fb7b45f0
DR		 5164 /* PHY layer lane error */
5165 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5166 /* Ignore LINERESET indication, as this is not an error */
5167 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
ff8e20c6 5168 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5169 /*
5170 * To know whether this error is fatal or not, DB timeout
5171 * must be checked but this error is handled separately.
5172 */
5173 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
ff8e20c6
DR		 5174 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5175 }
fb7b45f0 5176
e8e7f271
SRT		 5177 /* PA_INIT_ERROR is fatal and needs UIC reset */
5178 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
ff8e20c6
DR		 5179 if (reg)
5180 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5181
e8e7f271
SRT		 5182 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5183 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 5184 else if (hba->dev_quirks &
5185 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5186 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5187 hba->uic_error |=
5188 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5189 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5190 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5191 }
e8e7f271
SRT		 5192
5193 /* UIC NL/TL/DME errors needs software retry */
5194 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
ff8e20c6
DR		 5195 if (reg) {
5196 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5197 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
ff8e20c6 5198 }
e8e7f271
SRT		 5199
5200 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
ff8e20c6
DR		 5201 if (reg) {
5202 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5203 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
ff8e20c6 5204 }
e8e7f271
SRT		 5205
5206 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
ff8e20c6
DR		 5207 if (reg) {
5208 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5209 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
ff8e20c6 5210 }
e8e7f271
SRT		 5211
5212 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5213 __func__, hba->uic_error);
5214}
5215
5216/**
5217 * ufshcd_check_errors - Check for errors that need s/w attention
5218 * @hba: per-adapter instance
5219 */
5220static void ufshcd_check_errors(struct ufs_hba *hba)
5221{
5222 bool queue_eh_work = false;
5223
7a3e97b0 5224 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 5225 queue_eh_work = true;
7a3e97b0
SY		 5226
5227 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 5228 hba->uic_error = 0;
5229 ufshcd_update_uic_error(hba);
5230 if (hba->uic_error)
5231 queue_eh_work = true;
7a3e97b0 5232 }
e8e7f271
SRT		 5233
5234 if (queue_eh_work) {
9a47ec7c
YG		 5235 /*
5236 * update the transfer error masks to sticky bits, let's do this
5237 * irrespective of current ufshcd_state.
5238 */
5239 hba->saved_err |= hba->errors;
5240 hba->saved_uic_err |= hba->uic_error;
5241
e8e7f271
SRT		 5242 /* handle fatal errors only when link is functional */
5243 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5244 /* block commands from scsi mid-layer */
5245 scsi_block_requests(hba->host);
5246
141f8165 5247 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5248
5249 /* dump controller state before resetting */
5250 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5251 bool pr_prdt = !!(hba->saved_err &
5252 SYSTEM_BUS_FATAL_ERROR);
5253
5254 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5255 __func__, hba->saved_err,
5256 hba->saved_uic_err);
5257
5258 ufshcd_print_host_regs(hba);
5259 ufshcd_print_pwr_info(hba);
5260 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5261 ufshcd_print_trs(hba, hba->outstanding_reqs,
5262 pr_prdt);
5263 }
e8e7f271
SRT		 5264 schedule_work(&hba->eh_work);
5265 }
3441da7d 5266 }
e8e7f271
SRT		 5267 /*
5268 * if (!queue_eh_work) -
5269 * Other errors are either non-fatal where host recovers
5270 * itself without s/w intervention or errors that will be
5271 * handled by the SCSI core layer.
5272 */
7a3e97b0
SY		 5273}
5274
5275/**
5276 * ufshcd_tmc_handler - handle task management function completion
5277 * @hba: per adapter instance
5278 */
5279static void ufshcd_tmc_handler(struct ufs_hba *hba)
5280{
5281 u32 tm_doorbell;
5282
b873a275 5283 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 5284 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 5285 wake_up(&hba->tm_wq);
7a3e97b0
SY		 5286}
5287
5288/**
5289 * ufshcd_sl_intr - Interrupt service routine
5290 * @hba: per adapter instance
5291 * @intr_status: contains interrupts generated by the controller
5292 */
5293static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5294{
5295 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5296 if (hba->errors)
e8e7f271 5297 ufshcd_check_errors(hba);
7a3e97b0 5298
53b3d9c3
SJ		 5299 if (intr_status & UFSHCD_UIC_MASK)
5300 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5301
5302 if (intr_status & UTP_TASK_REQ_COMPL)
5303 ufshcd_tmc_handler(hba);
5304
5305 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5306 ufshcd_transfer_req_compl(hba);
5307}
5308
5309/**
5310 * ufshcd_intr - Main interrupt service routine
5311 * @irq: irq number
5312 * @__hba: pointer to adapter instance
5313 *
5314 * Returns IRQ_HANDLED - If interrupt is valid
5315 * IRQ_NONE - If invalid interrupt
5316 */
5317static irqreturn_t ufshcd_intr(int irq, void *__hba)
5318{
d75f7fe4 5319 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5320 irqreturn_t retval = IRQ_NONE;
5321 struct ufs_hba *hba = __hba;
5322
5323 spin_lock(hba->host->host_lock);
b873a275 5324 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5325 enabled_intr_status =
5326 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 5327
d75f7fe4 5328 if (intr_status)
261ea452 5329 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5330
5331 if (enabled_intr_status) {
5332 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 5333 retval = IRQ_HANDLED;
5334 }
5335 spin_unlock(hba->host->host_lock);
5336 return retval;
5337}
5338
e2933132
SRT		 5339static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5340{
5341 int err = 0;
5342 u32 mask = 1 << tag;
5343 unsigned long flags;
5344
5345 if (!test_bit(tag, &hba->outstanding_tasks))
5346 goto out;
5347
5348 spin_lock_irqsave(hba->host->host_lock, flags);
5349 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
5350 spin_unlock_irqrestore(hba->host->host_lock, flags);
5351
5352 /* poll for max. 1 sec to clear door bell register by h/w */
5353 err = ufshcd_wait_for_register(hba,
5354 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5355 mask, 0, 1000, 1000, true);
e2933132
SRT		 5356out:
5357 return err;
5358}
5359
7a3e97b0
SY		 5360/**
5361 * ufshcd_issue_tm_cmd - issues task management commands to controller
5362 * @hba: per adapter instance
e2933132
SRT		 5363 * @lun_id: LUN ID to which TM command is sent
5364 * @task_id: task ID to which the TM command is applicable
5365 * @tm_function: task management function opcode
5366 * @tm_response: task management service response return value
7a3e97b0 5367 *
e2933132 5368 * Returns non-zero value on error, zero on success.
7a3e97b0 5369 */
e2933132
SRT		 5370static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5371 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 5372{
5373 struct utp_task_req_desc *task_req_descp;
5374 struct utp_upiu_task_req *task_req_upiup;
5375 struct Scsi_Host *host;
5376 unsigned long flags;
e2933132 5377 int free_slot;
7a3e97b0 5378 int err;
e2933132 5379 int task_tag;
7a3e97b0
SY		 5380
5381 host = hba->host;
5382
e2933132
SRT		 5383 /*
5384 * Get free slot, sleep if slots are unavailable.
5385 * Even though we use wait_event() which sleeps indefinitely,
5386 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5387 */
5388 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 5389 ufshcd_hold(hba, false);
7a3e97b0 5390
e2933132 5391 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 5392 task_req_descp = hba->utmrdl_base_addr;
5393 task_req_descp += free_slot;
5394
5395 /* Configure task request descriptor */
5396 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5397 task_req_descp->header.dword_2 =
5398 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5399
5400 /* Configure task request UPIU */
5401 task_req_upiup =
5402 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 5403 task_tag = hba->nutrs + free_slot;
7a3e97b0 5404 task_req_upiup->header.dword_0 =
5a0b0cb9 5405 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 5406 lun_id, task_tag);
7a3e97b0 5407 task_req_upiup->header.dword_1 =
5a0b0cb9 5408 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 5409 /*
5410 * The host shall provide the same value for LUN field in the basic
5411 * header and for Input Parameter.
5412 */
e2933132
SRT		 5413 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
5414 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 5415
d2877be4
KK		 5416 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5417
7a3e97b0
SY		 5418 /* send command to the controller */
5419 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5420
5421 /* Make sure descriptors are ready before ringing the task doorbell */
5422 wmb();
5423
b873a275 5424 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5425 /* Make sure that doorbell is committed immediately */
5426 wmb();
7a3e97b0
SY		 5427
5428 spin_unlock_irqrestore(host->host_lock, flags);
5429
5430 /* wait until the task management command is completed */
e2933132
SRT		 5431 err = wait_event_timeout(hba->tm_wq,
5432 test_bit(free_slot, &hba->tm_condition),
5433 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5434 if (!err) {
e2933132
SRT		 5435 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5436 __func__, tm_function);
5437 if (ufshcd_clear_tm_cmd(hba, free_slot))
5438 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5439 __func__, free_slot);
5440 err = -ETIMEDOUT;
5441 } else {
5442 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 5443 }
e2933132 5444
7a3e97b0 5445 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 5446 ufshcd_put_tm_slot(hba, free_slot);
5447 wake_up(&hba->tm_tag_wq);
5448
1ab27c9c 5449 ufshcd_release(hba);
7a3e97b0
SY		 5450 return err;
5451}
5452
5453/**
3441da7d
SRT		 5454 * ufshcd_eh_device_reset_handler - device reset handler registered to
5455 * scsi layer.
7a3e97b0
SY		 5456 * @cmd: SCSI command pointer
5457 *
5458 * Returns SUCCESS/FAILED
5459 */
3441da7d 5460static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 5461{
5462 struct Scsi_Host *host;
5463 struct ufs_hba *hba;
5464 unsigned int tag;
5465 u32 pos;
5466 int err;
e2933132
SRT		 5467 u8 resp = 0xF;
5468 struct ufshcd_lrb *lrbp;
3441da7d 5469 unsigned long flags;
7a3e97b0
SY		 5470
5471 host = cmd->device->host;
5472 hba = shost_priv(host);
5473 tag = cmd->request->tag;
5474
e2933132
SRT		 5475 lrbp = &hba->lrb[tag];
5476 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5477 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 5478 if (!err)
5479 err = resp;
7a3e97b0 5480 goto out;
e2933132 5481 }
7a3e97b0 5482
3441da7d
SRT		 5483 /* clear the commands that were pending for corresponding LUN */
5484 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5485 if (hba->lrb[pos].lun == lrbp->lun) {
5486 err = ufshcd_clear_cmd(hba, pos);
5487 if (err)
5488 break;
7a3e97b0 5489 }
3441da7d
SRT		 5490 }
5491 spin_lock_irqsave(host->host_lock, flags);
5492 ufshcd_transfer_req_compl(hba);
5493 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 5494
7a3e97b0 5495out:
7fabb77b 5496 hba->req_abort_count = 0;
3441da7d
SRT		 5497 if (!err) {
5498 err = SUCCESS;
5499 } else {
5500 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5501 err = FAILED;
5502 }
7a3e97b0
SY		 5503 return err;
5504}
5505
e0b299e3
GB		 5506static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5507{
5508 struct ufshcd_lrb *lrbp;
5509 int tag;
5510
5511 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5512 lrbp = &hba->lrb[tag];
5513 lrbp->req_abort_skip = true;
5514 }
5515}
5516
7a3e97b0
SY		 5517/**
5518 * ufshcd_abort - abort a specific command
5519 * @cmd: SCSI command pointer
5520 *
f20810d8
SRT		 5521 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5522 * command, and in host controller by clearing the door-bell register. There can
5523 * be race between controller sending the command to the device while abort is
5524 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5525 * really issued and then try to abort it.
5526 *
7a3e97b0
SY		 5527 * Returns SUCCESS/FAILED
5528 */
5529static int ufshcd_abort(struct scsi_cmnd *cmd)
5530{
5531 struct Scsi_Host *host;
5532 struct ufs_hba *hba;
5533 unsigned long flags;
5534 unsigned int tag;
f20810d8
SRT		 5535 int err = 0;
5536 int poll_cnt;
e2933132
SRT		 5537 u8 resp = 0xF;
5538 struct ufshcd_lrb *lrbp;
e9d501b1 5539 u32 reg;
7a3e97b0
SY		 5540
5541 host = cmd->device->host;
5542 hba = shost_priv(host);
5543 tag = cmd->request->tag;
e7d38257 5544 lrbp = &hba->lrb[tag];
14497328
YG		 5545 if (!ufshcd_valid_tag(hba, tag)) {
5546 dev_err(hba->dev,
5547 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5548 __func__, tag, cmd, cmd->request);
5549 BUG();
5550 }
7a3e97b0 5551
e7d38257
DR		 5552 /*
5553 * Task abort to the device W-LUN is illegal. When this command
5554 * will fail, due to spec violation, scsi err handling next step
5555 * will be to send LU reset which, again, is a spec violation.
5556 * To avoid these unnecessary/illegal step we skip to the last error
5557 * handling stage: reset and restore.
5558 */
5559 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5560 return ufshcd_eh_host_reset_handler(cmd);
5561
1ab27c9c 5562 ufshcd_hold(hba, false);
14497328 5563 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 5564 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 5565 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5566 dev_err(hba->dev,
5567 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5568 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 5569 goto out;
14497328 5570 }
7a3e97b0 5571
e9d501b1
DR		 5572 if (!(reg & (1 << tag))) {
5573 dev_err(hba->dev,
5574 "%s: cmd was completed, but without a notifying intr, tag = %d",
5575 __func__, tag);
5576 }
5577
66cc820f
DR		 5578 /* Print Transfer Request of aborted task */
5579 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 5580
7fabb77b
GB		 5581 /*
5582 * Print detailed info about aborted request.
5583 * As more than one request might get aborted at the same time,
5584 * print full information only for the first aborted request in order
5585 * to reduce repeated printouts. For other aborted requests only print
5586 * basic details.
5587 */
5588 scsi_print_command(hba->lrb[tag].cmd);
5589 if (!hba->req_abort_count) {
5590 ufshcd_print_host_regs(hba);
6ba65588 5591 ufshcd_print_host_state(hba);
7fabb77b
GB		 5592 ufshcd_print_pwr_info(hba);
5593 ufshcd_print_trs(hba, 1 << tag, true);
5594 } else {
5595 ufshcd_print_trs(hba, 1 << tag, false);
5596 }
5597 hba->req_abort_count++;
e0b299e3
GB		 5598
5599 /* Skip task abort in case previous aborts failed and report failure */
5600 if (lrbp->req_abort_skip) {
5601 err = -EIO;
5602 goto out;
5603 }
5604
f20810d8
SRT		 5605 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
5606 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5607 UFS_QUERY_TASK, &resp);
5608 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
5609 /* cmd pending in the device */
ff8e20c6
DR		 5610 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
5611 __func__, tag);
f20810d8
SRT		 5612 break;
5613 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 5614 /*
5615 * cmd not pending in the device, check if it is
5616 * in transition.
5617 */
ff8e20c6
DR		 5618 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
5619 __func__, tag);
f20810d8
SRT		 5620 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5621 if (reg & (1 << tag)) {
5622 /* sleep for max. 200us to stabilize */
5623 usleep_range(100, 200);
5624 continue;
5625 }
5626 /* command completed already */
ff8e20c6
DR		 5627 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
5628 __func__, tag);
f20810d8
SRT		 5629 goto out;
5630 } else {
ff8e20c6
DR		 5631 dev_err(hba->dev,
5632 "%s: no response from device. tag = %d, err %d\n",
5633 __func__, tag, err);
f20810d8
SRT		 5634 if (!err)
5635 err = resp; /* service response error */
5636 goto out;
5637 }
5638 }
5639
5640 if (!poll_cnt) {
5641 err = -EBUSY;
7a3e97b0
SY		 5642 goto out;
5643 }
7a3e97b0 5644
e2933132
SRT		 5645 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5646 UFS_ABORT_TASK, &resp);
5647 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 5648 if (!err) {
f20810d8 5649 err = resp; /* service response error */
ff8e20c6
DR		 5650 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
5651 __func__, tag, err);
5652 }
7a3e97b0 5653 goto out;
e2933132 5654 }
7a3e97b0 5655
f20810d8 5656 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 5657 if (err) {
5658 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
5659 __func__, tag, err);
f20810d8 5660 goto out;
ff8e20c6 5661 }
f20810d8 5662
7a3e97b0
SY		 5663 scsi_dma_unmap(cmd);
5664
5665 spin_lock_irqsave(host->host_lock, flags);
a48353f6 5666 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 5667 hba->lrb[tag].cmd = NULL;
5668 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 5669
5670 clear_bit_unlock(tag, &hba->lrb_in_use);
5671 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 5672
7a3e97b0 5673out:
f20810d8
SRT		 5674 if (!err) {
5675 err = SUCCESS;
5676 } else {
5677 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 5678 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 5679 err = FAILED;
5680 }
5681
1ab27c9c
ST		 5682 /*
5683 * This ufshcd_release() corresponds to the original scsi cmd that got
5684 * aborted here (as we won't get any IRQ for it).
5685 */
5686 ufshcd_release(hba);
7a3e97b0
SY		 5687 return err;
5688}
5689
3441da7d
SRT		 5690/**
5691 * ufshcd_host_reset_and_restore - reset and restore host controller
5692 * @hba: per-adapter instance
5693 *
5694 * Note that host controller reset may issue DME_RESET to
5695 * local and remote (device) Uni-Pro stack and the attributes
5696 * are reset to default state.
5697 *
5698 * Returns zero on success, non-zero on failure
5699 */
5700static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
5701{
5702 int err;
3441da7d
SRT		 5703 unsigned long flags;
5704
5705 /* Reset the host controller */
5706 spin_lock_irqsave(hba->host->host_lock, flags);
596585a2 5707 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 5708 spin_unlock_irqrestore(hba->host->host_lock, flags);
5709
a3cd5ec5
SJ		 5710 /* scale up clocks to max frequency before full reinitialization */
5711 ufshcd_scale_clks(hba, true);
5712
3441da7d
SRT		 5713 err = ufshcd_hba_enable(hba);
5714 if (err)
5715 goto out;
5716
5717 /* Establish the link again and restore the device */
1d337ec2
SRT		 5718 err = ufshcd_probe_hba(hba);
5719
5720 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 5721 err = -EIO;
5722out:
5723 if (err)
5724 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
5725
5726 return err;
5727}
5728
5729/**
5730 * ufshcd_reset_and_restore - reset and re-initialize host/device
5731 * @hba: per-adapter instance
5732 *
5733 * Reset and recover device, host and re-establish link. This
5734 * is helpful to recover the communication in fatal error conditions.
5735 *
5736 * Returns zero on success, non-zero on failure
5737 */
5738static int ufshcd_reset_and_restore(struct ufs_hba *hba)
5739{
5740 int err = 0;
5741 unsigned long flags;
1d337ec2 5742 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 5743
1d337ec2
SRT		 5744 do {
5745 err = ufshcd_host_reset_and_restore(hba);
5746 } while (err && --retries);
3441da7d
SRT		 5747
5748 /*
5749 * After reset the door-bell might be cleared, complete
5750 * outstanding requests in s/w here.
5751 */
5752 spin_lock_irqsave(hba->host->host_lock, flags);
5753 ufshcd_transfer_req_compl(hba);
5754 ufshcd_tmc_handler(hba);
5755 spin_unlock_irqrestore(hba->host->host_lock, flags);
5756
5757 return err;
5758}
5759
5760/**
5761 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
5762 * @cmd - SCSI command pointer
5763 *
5764 * Returns SUCCESS/FAILED
5765 */
5766static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
5767{
5768 int err;
5769 unsigned long flags;
5770 struct ufs_hba *hba;
5771
5772 hba = shost_priv(cmd->device->host);
5773
1ab27c9c 5774 ufshcd_hold(hba, false);
3441da7d
SRT		 5775 /*
5776 * Check if there is any race with fatal error handling.
5777 * If so, wait for it to complete. Even though fatal error
5778 * handling does reset and restore in some cases, don't assume
5779 * anything out of it. We are just avoiding race here.
5780 */
5781 do {
5782 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5783 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 5784 hba->ufshcd_state == UFSHCD_STATE_RESET))
5785 break;
5786 spin_unlock_irqrestore(hba->host->host_lock, flags);
5787 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 5788 flush_work(&hba->eh_work);
3441da7d
SRT		 5789 } while (1);
5790
5791 hba->ufshcd_state = UFSHCD_STATE_RESET;
5792 ufshcd_set_eh_in_progress(hba);
5793 spin_unlock_irqrestore(hba->host->host_lock, flags);
5794
5795 err = ufshcd_reset_and_restore(hba);
5796
5797 spin_lock_irqsave(hba->host->host_lock, flags);
5798 if (!err) {
5799 err = SUCCESS;
5800 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5801 } else {
5802 err = FAILED;
5803 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5804 }
5805 ufshcd_clear_eh_in_progress(hba);
5806 spin_unlock_irqrestore(hba->host->host_lock, flags);
5807
1ab27c9c 5808 ufshcd_release(hba);
3441da7d
SRT		 5809 return err;
5810}
5811
3a4bf06d
YG		 5812/**
5813 * ufshcd_get_max_icc_level - calculate the ICC level
5814 * @sup_curr_uA: max. current supported by the regulator
5815 * @start_scan: row at the desc table to start scan from
5816 * @buff: power descriptor buffer
5817 *
5818 * Returns calculated max ICC level for specific regulator
5819 */
5820static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
5821{
5822 int i;
5823 int curr_uA;
5824 u16 data;
5825 u16 unit;
5826
5827 for (i = start_scan; i >= 0; i--) {
d79713f9 5828 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 5829 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
5830 ATTR_ICC_LVL_UNIT_OFFSET;
5831 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
5832 switch (unit) {
5833 case UFSHCD_NANO_AMP:
5834 curr_uA = curr_uA / 1000;
5835 break;
5836 case UFSHCD_MILI_AMP:
5837 curr_uA = curr_uA * 1000;
5838 break;
5839 case UFSHCD_AMP:
5840 curr_uA = curr_uA * 1000 * 1000;
5841 break;
5842 case UFSHCD_MICRO_AMP:
5843 default:
5844 break;
5845 }
5846 if (sup_curr_uA >= curr_uA)
5847 break;
5848 }
5849 if (i < 0) {
5850 i = 0;
5851 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
5852 }
5853
5854 return (u32)i;
5855}
5856
5857/**
5858 * ufshcd_calc_icc_level - calculate the max ICC level
5859 * In case regulators are not initialized we'll return 0
5860 * @hba: per-adapter instance
5861 * @desc_buf: power descriptor buffer to extract ICC levels from.
5862 * @len: length of desc_buff
5863 *
5864 * Returns calculated ICC level
5865 */
5866static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
5867 u8 *desc_buf, int len)
5868{
5869 u32 icc_level = 0;
5870
5871 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
5872 !hba->vreg_info.vccq2) {
5873 dev_err(hba->dev,
5874 "%s: Regulator capability was not set, actvIccLevel=%d",
5875 __func__, icc_level);
5876 goto out;
5877 }
5878
5879 if (hba->vreg_info.vcc)
5880 icc_level = ufshcd_get_max_icc_level(
5881 hba->vreg_info.vcc->max_uA,
5882 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
5883 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
5884
5885 if (hba->vreg_info.vccq)
5886 icc_level = ufshcd_get_max_icc_level(
5887 hba->vreg_info.vccq->max_uA,
5888 icc_level,
5889 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
5890
5891 if (hba->vreg_info.vccq2)
5892 icc_level = ufshcd_get_max_icc_level(
5893 hba->vreg_info.vccq2->max_uA,
5894 icc_level,
5895 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
5896out:
5897 return icc_level;
5898}
5899
61e07359
DR		 5900static int ufshcd_set_icc_levels_attr(struct ufs_hba *hba, u32 icc_level)
5901{
5902 int ret = 0;
5903 int retries;
5904
5905 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
5906 /* write attribute */
5907 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5908 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
5909 if (!ret)
5910 break;
5911
5912 dev_dbg(hba->dev, "%s: failed with error %d\n", __func__, ret);
5913 }
5914
5915 return ret;
5916}
5917
3a4bf06d
YG		 5918static void ufshcd_init_icc_levels(struct ufs_hba *hba)
5919{
5920 int ret;
5921 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
5922 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
5923
5924 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
5925 if (ret) {
5926 dev_err(hba->dev,
5927 "%s: Failed reading power descriptor.len = %d ret = %d",
5928 __func__, buff_len, ret);
5929 return;
5930 }
5931
5932 hba->init_prefetch_data.icc_level =
5933 ufshcd_find_max_sup_active_icc_level(hba,
5934 desc_buf, buff_len);
5935 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
5936 __func__, hba->init_prefetch_data.icc_level);
5937
61e07359
DR		 5938 ret = ufshcd_set_icc_levels_attr(hba,
5939 hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 5940
5941 if (ret)
5942 dev_err(hba->dev,
5943 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
5944 __func__, hba->init_prefetch_data.icc_level , ret);
5945
5946}
5947
2a8fa600
SJ		 5948/**
5949 * ufshcd_scsi_add_wlus - Adds required W-LUs
5950 * @hba: per-adapter instance
5951 *
5952 * UFS device specification requires the UFS devices to support 4 well known
5953 * logical units:
5954 * "REPORT_LUNS" (address: 01h)
5955 * "UFS Device" (address: 50h)
5956 * "RPMB" (address: 44h)
5957 * "BOOT" (address: 30h)
5958 * UFS device's power management needs to be controlled by "POWER CONDITION"
5959 * field of SSU (START STOP UNIT) command. But this "power condition" field
5960 * will take effect only when its sent to "UFS device" well known logical unit
5961 * hence we require the scsi_device instance to represent this logical unit in
5962 * order for the UFS host driver to send the SSU command for power management.
5963
5964 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
5965 * Block) LU so user space process can control this LU. User space may also
5966 * want to have access to BOOT LU.
5967
5968 * This function adds scsi device instances for each of all well known LUs
5969 * (except "REPORT LUNS" LU).
5970 *
5971 * Returns zero on success (all required W-LUs are added successfully),
5972 * non-zero error value on failure (if failed to add any of the required W-LU).
5973 */
5974static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
5975{
5976 int ret = 0;
7c48bfd0
AM		 5977 struct scsi_device *sdev_rpmb;
5978 struct scsi_device *sdev_boot;
2a8fa600
SJ		 5979
5980 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
5981 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
5982 if (IS_ERR(hba->sdev_ufs_device)) {
5983 ret = PTR_ERR(hba->sdev_ufs_device);
5984 hba->sdev_ufs_device = NULL;
5985 goto out;
5986 }
7c48bfd0 5987 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 5988
7c48bfd0 5989 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 5990 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 5991 if (IS_ERR(sdev_boot)) {
5992 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 5993 goto remove_sdev_ufs_device;
5994 }
7c48bfd0 5995 scsi_device_put(sdev_boot);
2a8fa600 5996
7c48bfd0 5997 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 5998 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 5999 if (IS_ERR(sdev_rpmb)) {
6000 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 6001 goto remove_sdev_boot;
6002 }
7c48bfd0 6003 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 6004 goto out;
6005
6006remove_sdev_boot:
7c48bfd0 6007 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 6008remove_sdev_ufs_device:
6009 scsi_remove_device(hba->sdev_ufs_device);
6010out:
6011 return ret;
6012}
6013
93fdd5ac
TW		 6014static int ufs_get_device_desc(struct ufs_hba *hba,
6015 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG		 6016{
6017 int err;
6018 u8 model_index;
6019 u8 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE + 1] = {0};
6020 u8 desc_buf[QUERY_DESC_DEVICE_MAX_SIZE];
6021
6022 err = ufshcd_read_device_desc(hba, desc_buf,
6023 QUERY_DESC_DEVICE_MAX_SIZE);
6024 if (err) {
6025 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6026 __func__, err);
6027 goto out;
6028 }
6029
6030 /*
6031 * getting vendor (manufacturerID) and Bank Index in big endian
6032 * format
6033 */
93fdd5ac 6034 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6035 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6036
6037 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6038
6039 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
6040 QUERY_DESC_STRING_MAX_SIZE, ASCII_STD);
6041 if (err) {
6042 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6043 __func__, err);
6044 goto out;
6045 }
6046
6047 str_desc_buf[QUERY_DESC_STRING_MAX_SIZE] = '\0';
93fdd5ac 6048 strlcpy(dev_desc->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
c58ab7aa
YG		 6049 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
6050 MAX_MODEL_LEN));
6051
6052 /* Null terminate the model string */
93fdd5ac 6053 dev_desc->model[MAX_MODEL_LEN] = '\0';
c58ab7aa
YG		 6054
6055out:
6056 return err;
6057}
6058
93fdd5ac
TW		 6059static void ufs_fixup_device_setup(struct ufs_hba *hba,
6060 struct ufs_dev_desc *dev_desc)
c58ab7aa 6061{
c58ab7aa 6062 struct ufs_dev_fix *f;
c58ab7aa
YG		 6063
6064 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW		 6065 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6066 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6067 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
c58ab7aa
YG		 6068 !strcmp(f->card.model, UFS_ANY_MODEL)))
6069 hba->dev_quirks |= f->quirk;
6070 }
6071}
6072
37113106
YG		 6073/**
6074 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6075 * @hba: per-adapter instance
6076 *
6077 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6078 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6079 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6080 * the hibern8 exit latency.
6081 *
6082 * Returns zero on success, non-zero error value on failure.
6083 */
6084static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6085{
6086 int ret = 0;
6087 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6088
6089 ret = ufshcd_dme_peer_get(hba,
6090 UIC_ARG_MIB_SEL(
6091 RX_MIN_ACTIVATETIME_CAPABILITY,
6092 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6093 &peer_rx_min_activatetime);
6094 if (ret)
6095 goto out;
6096
6097 /* make sure proper unit conversion is applied */
6098 tuned_pa_tactivate =
6099 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6100 / PA_TACTIVATE_TIME_UNIT_US);
6101 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6102 tuned_pa_tactivate);
6103
6104out:
6105 return ret;
6106}
6107
6108/**
6109 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6110 * @hba: per-adapter instance
6111 *
6112 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6113 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6114 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6115 * This optimal value can help reduce the hibern8 exit latency.
6116 *
6117 * Returns zero on success, non-zero error value on failure.
6118 */
6119static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6120{
6121 int ret = 0;
6122 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6123 u32 max_hibern8_time, tuned_pa_hibern8time;
6124
6125 ret = ufshcd_dme_get(hba,
6126 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6127 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6128 &local_tx_hibern8_time_cap);
6129 if (ret)
6130 goto out;
6131
6132 ret = ufshcd_dme_peer_get(hba,
6133 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6134 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6135 &peer_rx_hibern8_time_cap);
6136 if (ret)
6137 goto out;
6138
6139 max_hibern8_time = max(local_tx_hibern8_time_cap,
6140 peer_rx_hibern8_time_cap);
6141 /* make sure proper unit conversion is applied */
6142 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6143 / PA_HIBERN8_TIME_UNIT_US);
6144 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6145 tuned_pa_hibern8time);
6146out:
6147 return ret;
6148}
6149
c6a6db43
SJ		 6150/**
6151 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6152 * less than device PA_TACTIVATE time.
6153 * @hba: per-adapter instance
6154 *
6155 * Some UFS devices require host PA_TACTIVATE to be lower than device
6156 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6157 * for such devices.
6158 *
6159 * Returns zero on success, non-zero error value on failure.
6160 */
6161static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6162{
6163 int ret = 0;
6164 u32 granularity, peer_granularity;
6165 u32 pa_tactivate, peer_pa_tactivate;
6166 u32 pa_tactivate_us, peer_pa_tactivate_us;
6167 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6168
6169 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6170 &granularity);
6171 if (ret)
6172 goto out;
6173
6174 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6175 &peer_granularity);
6176 if (ret)
6177 goto out;
6178
6179 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6180 (granularity > PA_GRANULARITY_MAX_VAL)) {
6181 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6182 __func__, granularity);
6183 return -EINVAL;
6184 }
6185
6186 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6187 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6188 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6189 __func__, peer_granularity);
6190 return -EINVAL;
6191 }
6192
6193 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6194 if (ret)
6195 goto out;
6196
6197 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6198 &peer_pa_tactivate);
6199 if (ret)
6200 goto out;
6201
6202 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6203 peer_pa_tactivate_us = peer_pa_tactivate *
6204 gran_to_us_table[peer_granularity - 1];
6205
6206 if (pa_tactivate_us > peer_pa_tactivate_us) {
6207 u32 new_peer_pa_tactivate;
6208
6209 new_peer_pa_tactivate = pa_tactivate_us /
6210 gran_to_us_table[peer_granularity - 1];
6211 new_peer_pa_tactivate++;
6212 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6213 new_peer_pa_tactivate);
6214 }
6215
6216out:
6217 return ret;
6218}
6219
37113106
YG		 6220static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6221{
6222 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6223 ufshcd_tune_pa_tactivate(hba);
6224 ufshcd_tune_pa_hibern8time(hba);
6225 }
6226
6227 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6228 /* set 1ms timeout for PA_TACTIVATE */
6229 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43
SJ		 6230
6231 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6232 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 6233
6234 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 6235}
6236
ff8e20c6
DR		 6237static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6238{
6239 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6240
6241 hba->ufs_stats.hibern8_exit_cnt = 0;
6242 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6243
6244 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6245 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6246 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6247 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6248 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
7fabb77b
GB		 6249
6250 hba->req_abort_count = 0;
ff8e20c6
DR		 6251}
6252
6ccf44fe 6253/**
1d337ec2
SRT		 6254 * ufshcd_probe_hba - probe hba to detect device and initialize
6255 * @hba: per-adapter instance
6256 *
6257 * Execute link-startup and verify device initialization
6ccf44fe 6258 */
1d337ec2 6259static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6260{
93fdd5ac 6261 struct ufs_dev_desc card = {0};
6ccf44fe 6262 int ret;
7ff5ab47 6263 ktime_t start = ktime_get();
6ccf44fe
SJ		 6264
6265 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 6266 if (ret)
6267 goto out;
6268
afdfff59
YG		 6269 /* set the default level for urgent bkops */
6270 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6271 hba->is_urgent_bkops_lvl_checked = false;
6272
ff8e20c6
DR		 6273 /* Debug counters initialization */
6274 ufshcd_clear_dbg_ufs_stats(hba);
6275
57d104c1
SJ		 6276 /* UniPro link is active now */
6277 ufshcd_set_link_active(hba);
d3e89bac 6278
5a0b0cb9
SRT		 6279 ret = ufshcd_verify_dev_init(hba);
6280 if (ret)
6281 goto out;
68078d5c
DR		 6282
6283 ret = ufshcd_complete_dev_init(hba);
6284 if (ret)
6285 goto out;
5a0b0cb9 6286
93fdd5ac
TW		 6287 ret = ufs_get_device_desc(hba, &card);
6288 if (ret) {
6289 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6290 __func__, ret);
6291 goto out;
6292 }
6293
6294 ufs_fixup_device_setup(hba, &card);
37113106 6295 ufshcd_tune_unipro_params(hba);
60f01870
YG		 6296
6297 ret = ufshcd_set_vccq_rail_unused(hba,
6298 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6299 if (ret)
6300 goto out;
6301
57d104c1
SJ		 6302 /* UFS device is also active now */
6303 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6304 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 6305 hba->wlun_dev_clr_ua = true;
6306
7eb584db
DR		 6307 if (ufshcd_get_max_pwr_mode(hba)) {
6308 dev_err(hba->dev,
6309 "%s: Failed getting max supported power mode\n",
6310 __func__);
6311 } else {
6312 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 6313 if (ret) {
7eb584db
DR		 6314 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6315 __func__, ret);
8643ae66
DL		 6316 goto out;
6317 }
7eb584db 6318 }
57d104c1 6319
53c12d0e
YG		 6320 /* set the state as operational after switching to desired gear */
6321 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 6322 /*
6323 * If we are in error handling context or in power management callbacks
6324 * context, no need to scan the host
6325 */
6326 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6327 bool flag;
6328
6329 /* clear any previous UFS device information */
6330 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 6331 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6332 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 6333 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 6334
3a4bf06d
YG		 6335 if (!hba->is_init_prefetch)
6336 ufshcd_init_icc_levels(hba);
6337
2a8fa600
SJ		 6338 /* Add required well known logical units to scsi mid layer */
6339 if (ufshcd_scsi_add_wlus(hba))
6340 goto out;
6341
0701e49d
SJ		 6342 /* Initialize devfreq after UFS device is detected */
6343 if (ufshcd_is_clkscaling_supported(hba)) {
6344 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6345 &hba->pwr_info,
6346 sizeof(struct ufs_pa_layer_attr));
6347 hba->clk_scaling.saved_pwr_info.is_valid = true;
6348 if (!hba->devfreq) {
6349 hba->devfreq = devm_devfreq_add_device(hba->dev,
6350 &ufs_devfreq_profile,
6351 "simple_ondemand",
6352 NULL);
6353 if (IS_ERR(hba->devfreq)) {
6354 ret = PTR_ERR(hba->devfreq);
6355 dev_err(hba->dev, "Unable to register with devfreq %d\n",
6356 ret);
6357 goto out;
6358 }
6359 }
6360 hba->clk_scaling.is_allowed = true;
6361 }
6362
3441da7d
SRT		 6363 scsi_scan_host(hba->host);
6364 pm_runtime_put_sync(hba->dev);
6365 }
3a4bf06d
YG		 6366
6367 if (!hba->is_init_prefetch)
6368 hba->is_init_prefetch = true;
6369
5a0b0cb9 6370out:
1d337ec2
SRT		 6371 /*
6372 * If we failed to initialize the device or the device is not
6373 * present, turn off the power/clocks etc.
6374 */
57d104c1
SJ		 6375 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6376 pm_runtime_put_sync(hba->dev);
1d337ec2 6377 ufshcd_hba_exit(hba);
57d104c1 6378 }
1d337ec2 6379
7ff5ab47
SJ		 6380 trace_ufshcd_init(dev_name(hba->dev), ret,
6381 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 6382 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 6383 return ret;
6384}
6385
6386/**
6387 * ufshcd_async_scan - asynchronous execution for probing hba
6388 * @data: data pointer to pass to this function
6389 * @cookie: cookie data
6390 */
6391static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6392{
6393 struct ufs_hba *hba = (struct ufs_hba *)data;
6394
6395 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 6396}
6397
f550c65b
YG		 6398static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6399{
6400 unsigned long flags;
6401 struct Scsi_Host *host;
6402 struct ufs_hba *hba;
6403 int index;
6404 bool found = false;
6405
6406 if (!scmd || !scmd->device || !scmd->device->host)
6407 return BLK_EH_NOT_HANDLED;
6408
6409 host = scmd->device->host;
6410 hba = shost_priv(host);
6411 if (!hba)
6412 return BLK_EH_NOT_HANDLED;
6413
6414 spin_lock_irqsave(host->host_lock, flags);
6415
6416 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6417 if (hba->lrb[index].cmd == scmd) {
6418 found = true;
6419 break;
6420 }
6421 }
6422
6423 spin_unlock_irqrestore(host->host_lock, flags);
6424
6425 /*
6426 * Bypass SCSI error handling and reset the block layer timer if this
6427 * SCSI command was not actually dispatched to UFS driver, otherwise
6428 * let SCSI layer handle the error as usual.
6429 */
6430 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
6431}
6432
7a3e97b0
SY		 6433static struct scsi_host_template ufshcd_driver_template = {
6434 .module = THIS_MODULE,
6435 .name = UFSHCD,
6436 .proc_name = UFSHCD,
6437 .queuecommand = ufshcd_queuecommand,
6438 .slave_alloc = ufshcd_slave_alloc,
eeda4749 6439 .slave_configure = ufshcd_slave_configure,
7a3e97b0 6440 .slave_destroy = ufshcd_slave_destroy,
4264fd61 6441 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 6442 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 6443 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6444 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 6445 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 6446 .this_id = -1,
6447 .sg_tablesize = SG_ALL,
6448 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6449 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 6450 .max_host_blocked = 1,
c40ecc12 6451 .track_queue_depth = 1,
7a3e97b0
SY		 6452};
6453
57d104c1
SJ		 6454static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
6455 int ua)
6456{
7b16a07c 6457 int ret;
57d104c1 6458
7b16a07c
BA		 6459 if (!vreg)
6460 return 0;
57d104c1 6461
7b16a07c
BA		 6462 ret = regulator_set_load(vreg->reg, ua);
6463 if (ret < 0) {
6464 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
6465 __func__, vreg->name, ua, ret);
57d104c1
SJ		 6466 }
6467
6468 return ret;
6469}
6470
6471static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
6472 struct ufs_vreg *vreg)
6473{
60f01870
YG		 6474 if (!vreg)
6475 return 0;
6476 else if (vreg->unused)
6477 return 0;
6478 else
6479 return ufshcd_config_vreg_load(hba->dev, vreg,
6480 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 6481}
6482
6483static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
6484 struct ufs_vreg *vreg)
6485{
60f01870
YG		 6486 if (!vreg)
6487 return 0;
6488 else if (vreg->unused)
6489 return 0;
6490 else
6491 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 6492}
6493
aa497613
SRT		 6494static int ufshcd_config_vreg(struct device *dev,
6495 struct ufs_vreg *vreg, bool on)
6496{
6497 int ret = 0;
6498 struct regulator *reg = vreg->reg;
6499 const char *name = vreg->name;
6500 int min_uV, uA_load;
6501
6502 BUG_ON(!vreg);
6503
6504 if (regulator_count_voltages(reg) > 0) {
6505 min_uV = on ? vreg->min_uV : 0;
6506 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
6507 if (ret) {
6508 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
6509 __func__, name, ret);
6510 goto out;
6511 }
6512
6513 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 6514 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
6515 if (ret)
aa497613 6516 goto out;
aa497613
SRT		 6517 }
6518out:
6519 return ret;
6520}
6521
6522static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
6523{
6524 int ret = 0;
6525
60f01870
YG		 6526 if (!vreg)
6527 goto out;
6528 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 6529 goto out;
6530
6531 ret = ufshcd_config_vreg(dev, vreg, true);
6532 if (!ret)
6533 ret = regulator_enable(vreg->reg);
6534
6535 if (!ret)
6536 vreg->enabled = true;
6537 else
6538 dev_err(dev, "%s: %s enable failed, err=%d\n",
6539 __func__, vreg->name, ret);
6540out:
6541 return ret;
6542}
6543
6544static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
6545{
6546 int ret = 0;
6547
60f01870
YG		 6548 if (!vreg)
6549 goto out;
6550 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 6551 goto out;
6552
6553 ret = regulator_disable(vreg->reg);
6554
6555 if (!ret) {
6556 /* ignore errors on applying disable config */
6557 ufshcd_config_vreg(dev, vreg, false);
6558 vreg->enabled = false;
6559 } else {
6560 dev_err(dev, "%s: %s disable failed, err=%d\n",
6561 __func__, vreg->name, ret);
6562 }
6563out:
6564 return ret;
6565}
6566
6567static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
6568{
6569 int ret = 0;
6570 struct device *dev = hba->dev;
6571 struct ufs_vreg_info *info = &hba->vreg_info;
6572
6573 if (!info)
6574 goto out;
6575
6576 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
6577 if (ret)
6578 goto out;
6579
6580 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
6581 if (ret)
6582 goto out;
6583
6584 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
6585 if (ret)
6586 goto out;
6587
6588out:
6589 if (ret) {
6590 ufshcd_toggle_vreg(dev, info->vccq2, false);
6591 ufshcd_toggle_vreg(dev, info->vccq, false);
6592 ufshcd_toggle_vreg(dev, info->vcc, false);
6593 }
6594 return ret;
6595}
6596
6a771a65
RS		 6597static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
6598{
6599 struct ufs_vreg_info *info = &hba->vreg_info;
6600
6601 if (info)
6602 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6603
6604 return 0;
6605}
6606
aa497613
SRT		 6607static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
6608{
6609 int ret = 0;
6610
6611 if (!vreg)
6612 goto out;
6613
6614 vreg->reg = devm_regulator_get(dev, vreg->name);
6615 if (IS_ERR(vreg->reg)) {
6616 ret = PTR_ERR(vreg->reg);
6617 dev_err(dev, "%s: %s get failed, err=%d\n",
6618 __func__, vreg->name, ret);
6619 }
6620out:
6621 return ret;
6622}
6623
6624static int ufshcd_init_vreg(struct ufs_hba *hba)
6625{
6626 int ret = 0;
6627 struct device *dev = hba->dev;
6628 struct ufs_vreg_info *info = &hba->vreg_info;
6629
6630 if (!info)
6631 goto out;
6632
6633 ret = ufshcd_get_vreg(dev, info->vcc);
6634 if (ret)
6635 goto out;
6636
6637 ret = ufshcd_get_vreg(dev, info->vccq);
6638 if (ret)
6639 goto out;
6640
6641 ret = ufshcd_get_vreg(dev, info->vccq2);
6642out:
6643 return ret;
6644}
6645
6a771a65
RS		 6646static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
6647{
6648 struct ufs_vreg_info *info = &hba->vreg_info;
6649
6650 if (info)
6651 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
6652
6653 return 0;
6654}
6655
60f01870
YG		 6656static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
6657{
6658 int ret = 0;
6659 struct ufs_vreg_info *info = &hba->vreg_info;
6660
6661 if (!info)
6662 goto out;
6663 else if (!info->vccq)
6664 goto out;
6665
6666 if (unused) {
6667 /* shut off the rail here */
6668 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
6669 /*
6670 * Mark this rail as no longer used, so it doesn't get enabled
6671 * later by mistake
6672 */
6673 if (!ret)
6674 info->vccq->unused = true;
6675 } else {
6676 /*
6677 * rail should have been already enabled hence just make sure
6678 * that unused flag is cleared.
6679 */
6680 info->vccq->unused = false;
6681 }
6682out:
6683 return ret;
6684}
6685
57d104c1
SJ		 6686static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
6687 bool skip_ref_clk)
c6e79dac
SRT		 6688{
6689 int ret = 0;
6690 struct ufs_clk_info *clki;
6691 struct list_head *head = &hba->clk_list_head;
1ab27c9c 6692 unsigned long flags;
911a0771
SJ		 6693 ktime_t start = ktime_get();
6694 bool clk_state_changed = false;
c6e79dac
SRT		 6695
6696 if (!head || list_empty(head))
6697 goto out;
6698
1e879e8f
SJ		 6699 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
6700 if (ret)
6701 return ret;
6702
c6e79dac
SRT		 6703 list_for_each_entry(clki, head, list) {
6704 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 6705 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
6706 continue;
6707
911a0771 6708 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 6709 if (on && !clki->enabled) {
6710 ret = clk_prepare_enable(clki->clk);
6711 if (ret) {
6712 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
6713 __func__, clki->name, ret);
6714 goto out;
6715 }
6716 } else if (!on && clki->enabled) {
6717 clk_disable_unprepare(clki->clk);
6718 }
6719 clki->enabled = on;
6720 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
6721 clki->name, on ? "en" : "dis");
6722 }
6723 }
1ab27c9c 6724
1e879e8f
SJ		 6725 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
6726 if (ret)
6727 return ret;
6728
c6e79dac
SRT		 6729out:
6730 if (ret) {
6731 list_for_each_entry(clki, head, list) {
6732 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
6733 clk_disable_unprepare(clki->clk);
6734 }
7ff5ab47 6735 } else if (!ret && on) {
1ab27c9c
ST		 6736 spin_lock_irqsave(hba->host->host_lock, flags);
6737 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 6738 trace_ufshcd_clk_gating(dev_name(hba->dev),
6739 hba->clk_gating.state);
1ab27c9c 6740 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 6741 }
7ff5ab47 6742
911a0771
SJ		 6743 if (clk_state_changed)
6744 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
6745 (on ? "on" : "off"),
6746 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 6747 return ret;
6748}
6749
57d104c1
SJ		 6750static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
6751{
6752 return __ufshcd_setup_clocks(hba, on, false);
6753}
6754
c6e79dac
SRT		 6755static int ufshcd_init_clocks(struct ufs_hba *hba)
6756{
6757 int ret = 0;
6758 struct ufs_clk_info *clki;
6759 struct device *dev = hba->dev;
6760 struct list_head *head = &hba->clk_list_head;
6761
6762 if (!head || list_empty(head))
6763 goto out;
6764
6765 list_for_each_entry(clki, head, list) {
6766 if (!clki->name)
6767 continue;
6768
6769 clki->clk = devm_clk_get(dev, clki->name);
6770 if (IS_ERR(clki->clk)) {
6771 ret = PTR_ERR(clki->clk);
6772 dev_err(dev, "%s: %s clk get failed, %d\n",
6773 __func__, clki->name, ret);
6774 goto out;
6775 }
6776
6777 if (clki->max_freq) {
6778 ret = clk_set_rate(clki->clk, clki->max_freq);
6779 if (ret) {
6780 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
6781 __func__, clki->name,
6782 clki->max_freq, ret);
6783 goto out;
6784 }
856b3483 6785 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 6786 }
6787 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
6788 clki->name, clk_get_rate(clki->clk));
6789 }
6790out:
6791 return ret;
6792}
6793
5c0c28a8
SRT		 6794static int ufshcd_variant_hba_init(struct ufs_hba *hba)
6795{
6796 int err = 0;
6797
6798 if (!hba->vops)
6799 goto out;
6800
0263bcd0
YG		 6801 err = ufshcd_vops_init(hba);
6802 if (err)
6803 goto out;
5c0c28a8 6804
0263bcd0
YG		 6805 err = ufshcd_vops_setup_regulators(hba, true);
6806 if (err)
6807 goto out_exit;
5c0c28a8
SRT		 6808
6809 goto out;
6810
5c0c28a8 6811out_exit:
0263bcd0 6812 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 6813out:
6814 if (err)
6815 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 6816 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 6817 return err;
6818}
6819
6820static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
6821{
6822 if (!hba->vops)
6823 return;
6824
0263bcd0 6825 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 6826
0263bcd0 6827 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 6828}
6829
aa497613
SRT		 6830static int ufshcd_hba_init(struct ufs_hba *hba)
6831{
6832 int err;
6833
6a771a65
RS		 6834 /*
6835 * Handle host controller power separately from the UFS device power
6836 * rails as it will help controlling the UFS host controller power
6837 * collapse easily which is different than UFS device power collapse.
6838 * Also, enable the host controller power before we go ahead with rest
6839 * of the initialization here.
6840 */
6841 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 6842 if (err)
6843 goto out;
6844
6a771a65 6845 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 6846 if (err)
6847 goto out;
6848
6a771a65
RS		 6849 err = ufshcd_init_clocks(hba);
6850 if (err)
6851 goto out_disable_hba_vreg;
6852
6853 err = ufshcd_setup_clocks(hba, true);
6854 if (err)
6855 goto out_disable_hba_vreg;
6856
c6e79dac
SRT		 6857 err = ufshcd_init_vreg(hba);
6858 if (err)
6859 goto out_disable_clks;
6860
6861 err = ufshcd_setup_vreg(hba, true);
6862 if (err)
6863 goto out_disable_clks;
6864
aa497613
SRT		 6865 err = ufshcd_variant_hba_init(hba);
6866 if (err)
6867 goto out_disable_vreg;
6868
1d337ec2 6869 hba->is_powered = true;
aa497613
SRT		 6870 goto out;
6871
6872out_disable_vreg:
6873 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 6874out_disable_clks:
6875 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 6876out_disable_hba_vreg:
6877 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 6878out:
6879 return err;
6880}
6881
6882static void ufshcd_hba_exit(struct ufs_hba *hba)
6883{
1d337ec2
SRT		 6884 if (hba->is_powered) {
6885 ufshcd_variant_hba_exit(hba);
6886 ufshcd_setup_vreg(hba, false);
a508253d 6887 ufshcd_suspend_clkscaling(hba);
401f1e44 6888 if (ufshcd_is_clkscaling_supported(hba)) {
0701e49d
SJ		 6889 if (hba->devfreq)
6890 ufshcd_suspend_clkscaling(hba);
401f1e44
SJ		 6891 destroy_workqueue(hba->clk_scaling.workq);
6892 }
1d337ec2
SRT		 6893 ufshcd_setup_clocks(hba, false);
6894 ufshcd_setup_hba_vreg(hba, false);
6895 hba->is_powered = false;
6896 }
aa497613
SRT		 6897}
6898
57d104c1
SJ		 6899static int
6900ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
6901{
6902 unsigned char cmd[6] = {REQUEST_SENSE,
6903 0,
6904 0,
6905 0,
dcea0bfb 6906 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 6907 0};
6908 char *buffer;
6909 int ret;
6910
dcea0bfb 6911 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 6912 if (!buffer) {
6913 ret = -ENOMEM;
6914 goto out;
6915 }
6916
fcbfffe2
CH		 6917 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
6918 UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
6919 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 6920 if (ret)
6921 pr_err("%s: failed with err %d\n", __func__, ret);
6922
6923 kfree(buffer);
6924out:
6925 return ret;
6926}
6927
6928/**
6929 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
6930 * power mode
6931 * @hba: per adapter instance
6932 * @pwr_mode: device power mode to set
6933 *
6934 * Returns 0 if requested power mode is set successfully
6935 * Returns non-zero if failed to set the requested power mode
6936 */
6937static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
6938 enum ufs_dev_pwr_mode pwr_mode)
6939{
6940 unsigned char cmd[6] = { START_STOP };
6941 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 6942 struct scsi_device *sdp;
6943 unsigned long flags;
57d104c1
SJ		 6944 int ret;
6945
7c48bfd0
AM		 6946 spin_lock_irqsave(hba->host->host_lock, flags);
6947 sdp = hba->sdev_ufs_device;
6948 if (sdp) {
6949 ret = scsi_device_get(sdp);
6950 if (!ret && !scsi_device_online(sdp)) {
6951 ret = -ENODEV;
6952 scsi_device_put(sdp);
6953 }
6954 } else {
6955 ret = -ENODEV;
6956 }
6957 spin_unlock_irqrestore(hba->host->host_lock, flags);
6958
6959 if (ret)
6960 return ret;
57d104c1
SJ		 6961
6962 /*
6963 * If scsi commands fail, the scsi mid-layer schedules scsi error-
6964 * handling, which would wait for host to be resumed. Since we know
6965 * we are functional while we are here, skip host resume in error
6966 * handling context.
6967 */
6968 hba->host->eh_noresume = 1;
6969 if (hba->wlun_dev_clr_ua) {
6970 ret = ufshcd_send_request_sense(hba, sdp);
6971 if (ret)
6972 goto out;
6973 /* Unit attention condition is cleared now */
6974 hba->wlun_dev_clr_ua = false;
6975 }
6976
6977 cmd[4] = pwr_mode << 4;
6978
6979 /*
6980 * Current function would be generally called from the power management
e8064021 6981 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 6982 * already suspended childs.
6983 */
fcbfffe2
CH		 6984 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
6985 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 6986 if (ret) {
6987 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 6988 "START_STOP failed for power mode: %d, result %x\n",
6989 pwr_mode, ret);
21045519
HR		 6990 if (driver_byte(ret) & DRIVER_SENSE)
6991 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 6992 }
6993
6994 if (!ret)
6995 hba->curr_dev_pwr_mode = pwr_mode;
6996out:
7c48bfd0 6997 scsi_device_put(sdp);
57d104c1
SJ		 6998 hba->host->eh_noresume = 0;
6999 return ret;
7000}
7001
7002static int ufshcd_link_state_transition(struct ufs_hba *hba,
7003 enum uic_link_state req_link_state,
7004 int check_for_bkops)
7005{
7006 int ret = 0;
7007
7008 if (req_link_state == hba->uic_link_state)
7009 return 0;
7010
7011 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
7012 ret = ufshcd_uic_hibern8_enter(hba);
7013 if (!ret)
7014 ufshcd_set_link_hibern8(hba);
7015 else
7016 goto out;
7017 }
7018 /*
7019 * If autobkops is enabled, link can't be turned off because
7020 * turning off the link would also turn off the device.
7021 */
7022 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7023 (!check_for_bkops || (check_for_bkops &&
7024 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 7025 /*
7026 * Let's make sure that link is in low power mode, we are doing
7027 * this currently by putting the link in Hibern8. Otherway to
7028 * put the link in low power mode is to send the DME end point
7029 * to device and then send the DME reset command to local
7030 * unipro. But putting the link in hibern8 is much faster.
7031 */
7032 ret = ufshcd_uic_hibern8_enter(hba);
7033 if (ret)
7034 goto out;
57d104c1
SJ		 7035 /*
7036 * Change controller state to "reset state" which
7037 * should also put the link in off/reset state
7038 */
596585a2 7039 ufshcd_hba_stop(hba, true);
57d104c1
SJ		 7040 /*
7041 * TODO: Check if we need any delay to make sure that
7042 * controller is reset
7043 */
7044 ufshcd_set_link_off(hba);
7045 }
7046
7047out:
7048 return ret;
7049}
7050
7051static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7052{
b799fdf7
YG		 7053 /*
7054 * It seems some UFS devices may keep drawing more than sleep current
7055 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7056 * To avoid this situation, add 2ms delay before putting these UFS
7057 * rails in LPM mode.
7058 */
7059 if (!ufshcd_is_link_active(hba) &&
7060 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7061 usleep_range(2000, 2100);
7062
57d104c1
SJ		 7063 /*
7064 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7065 * power.
7066 *
7067 * If UFS device and link is in OFF state, all power supplies (VCC,
7068 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7069 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7070 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7071 *
7072 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7073 * in low power state which would save some power.
7074 */
7075 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7076 !hba->dev_info.is_lu_power_on_wp) {
7077 ufshcd_setup_vreg(hba, false);
7078 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7079 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7080 if (!ufshcd_is_link_active(hba)) {
7081 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7082 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7083 }
7084 }
7085}
7086
7087static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7088{
7089 int ret = 0;
7090
7091 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7092 !hba->dev_info.is_lu_power_on_wp) {
7093 ret = ufshcd_setup_vreg(hba, true);
7094 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7095 if (!ret && !ufshcd_is_link_active(hba)) {
7096 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7097 if (ret)
7098 goto vcc_disable;
7099 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7100 if (ret)
7101 goto vccq_lpm;
7102 }
69d72ac8 7103 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7104 }
7105 goto out;
7106
7107vccq_lpm:
7108 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7109vcc_disable:
7110 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7111out:
7112 return ret;
7113}
7114
7115static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7116{
7117 if (ufshcd_is_link_off(hba))
7118 ufshcd_setup_hba_vreg(hba, false);
7119}
7120
7121static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7122{
7123 if (ufshcd_is_link_off(hba))
7124 ufshcd_setup_hba_vreg(hba, true);
7125}
7126
7a3e97b0 7127/**
57d104c1 7128 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7129 * @hba: per adapter instance
57d104c1
SJ		 7130 * @pm_op: desired low power operation type
7131 *
7132 * This function will try to put the UFS device and link into low power
7133 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7134 * (System PM level).
7135 *
7136 * If this function is called during shutdown, it will make sure that
7137 * both UFS device and UFS link is powered off.
7a3e97b0 7138 *
57d104c1
SJ		 7139 * NOTE: UFS device & link must be active before we enter in this function.
7140 *
7141 * Returns 0 for success and non-zero for failure
7a3e97b0 7142 */
57d104c1 7143static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7144{
57d104c1
SJ		 7145 int ret = 0;
7146 enum ufs_pm_level pm_lvl;
7147 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7148 enum uic_link_state req_link_state;
7149
7150 hba->pm_op_in_progress = 1;
7151 if (!ufshcd_is_shutdown_pm(pm_op)) {
7152 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7153 hba->rpm_lvl : hba->spm_lvl;
7154 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7155 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7156 } else {
7157 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7158 req_link_state = UIC_LINK_OFF_STATE;
7159 }
7160
7a3e97b0 7161 /*
57d104c1
SJ		 7162 * If we can't transition into any of the low power modes
7163 * just gate the clocks.
7a3e97b0 7164 */
1ab27c9c
ST		 7165 ufshcd_hold(hba, false);
7166 hba->clk_gating.is_suspended = true;
7167
401f1e44
SJ		 7168 if (hba->clk_scaling.is_allowed) {
7169 cancel_work_sync(&hba->clk_scaling.suspend_work);
7170 cancel_work_sync(&hba->clk_scaling.resume_work);
7171 ufshcd_suspend_clkscaling(hba);
7172 }
d6fcf81a 7173
57d104c1
SJ		 7174 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7175 req_link_state == UIC_LINK_ACTIVE_STATE) {
7176 goto disable_clks;
7177 }
7a3e97b0 7178
57d104c1
SJ		 7179 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7180 (req_link_state == hba->uic_link_state))
d6fcf81a 7181 goto enable_gating;
57d104c1
SJ		 7182
7183 /* UFS device & link must be active before we enter in this function */
7184 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7185 ret = -EINVAL;
d6fcf81a 7186 goto enable_gating;
57d104c1
SJ		 7187 }
7188
7189 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 7190 if (ufshcd_can_autobkops_during_suspend(hba)) {
7191 /*
7192 * The device is idle with no requests in the queue,
7193 * allow background operations if bkops status shows
7194 * that performance might be impacted.
7195 */
7196 ret = ufshcd_urgent_bkops(hba);
7197 if (ret)
7198 goto enable_gating;
7199 } else {
7200 /* make sure that auto bkops is disabled */
7201 ufshcd_disable_auto_bkops(hba);
7202 }
57d104c1
SJ		 7203 }
7204
7205 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7206 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7207 !ufshcd_is_runtime_pm(pm_op))) {
7208 /* ensure that bkops is disabled */
7209 ufshcd_disable_auto_bkops(hba);
7210 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7211 if (ret)
1ab27c9c 7212 goto enable_gating;
57d104c1
SJ		 7213 }
7214
7215 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7216 if (ret)
7217 goto set_dev_active;
7218
7219 ufshcd_vreg_set_lpm(hba);
7220
7221disable_clks:
7222 /*
7223 * Call vendor specific suspend callback. As these callbacks may access
7224 * vendor specific host controller register space call them before the
7225 * host clocks are ON.
7226 */
0263bcd0
YG		 7227 ret = ufshcd_vops_suspend(hba, pm_op);
7228 if (ret)
7229 goto set_link_active;
57d104c1 7230
57d104c1
SJ		 7231 if (!ufshcd_is_link_active(hba))
7232 ufshcd_setup_clocks(hba, false);
7233 else
7234 /* If link is active, device ref_clk can't be switched off */
7235 __ufshcd_setup_clocks(hba, false, true);
7236
1ab27c9c 7237 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7238 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1
SJ		 7239 /*
7240 * Disable the host irq as host controller as there won't be any
0263bcd0 7241 * host controller transaction expected till resume.
57d104c1
SJ		 7242 */
7243 ufshcd_disable_irq(hba);
7244 /* Put the host controller in low power mode if possible */
7245 ufshcd_hba_vreg_set_lpm(hba);
7246 goto out;
7247
57d104c1 7248set_link_active:
401f1e44
SJ		 7249 if (hba->clk_scaling.is_allowed)
7250 ufshcd_resume_clkscaling(hba);
57d104c1
SJ		 7251 ufshcd_vreg_set_hpm(hba);
7252 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
7253 ufshcd_set_link_active(hba);
7254 else if (ufshcd_is_link_off(hba))
7255 ufshcd_host_reset_and_restore(hba);
7256set_dev_active:
7257 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7258 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7259enable_gating:
401f1e44
SJ		 7260 if (hba->clk_scaling.is_allowed)
7261 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 7262 hba->clk_gating.is_suspended = false;
7263 ufshcd_release(hba);
57d104c1
SJ		 7264out:
7265 hba->pm_op_in_progress = 0;
7266 return ret;
7a3e97b0
SY		 7267}
7268
7269/**
57d104c1 7270 * ufshcd_resume - helper function for resume operations
3b1d0580 7271 * @hba: per adapter instance
57d104c1 7272 * @pm_op: runtime PM or system PM
7a3e97b0 7273 *
57d104c1
SJ		 7274 * This function basically brings the UFS device, UniPro link and controller
7275 * to active state.
7276 *
7277 * Returns 0 for success and non-zero for failure
7a3e97b0 7278 */
57d104c1 7279static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7280{
57d104c1
SJ		 7281 int ret;
7282 enum uic_link_state old_link_state;
7283
7284 hba->pm_op_in_progress = 1;
7285 old_link_state = hba->uic_link_state;
7286
7287 ufshcd_hba_vreg_set_hpm(hba);
7288 /* Make sure clocks are enabled before accessing controller */
7289 ret = ufshcd_setup_clocks(hba, true);
7290 if (ret)
7291 goto out;
7292
57d104c1
SJ		 7293 /* enable the host irq as host controller would be active soon */
7294 ret = ufshcd_enable_irq(hba);
7295 if (ret)
7296 goto disable_irq_and_vops_clks;
7297
7298 ret = ufshcd_vreg_set_hpm(hba);
7299 if (ret)
7300 goto disable_irq_and_vops_clks;
7301
7a3e97b0 7302 /*
57d104c1
SJ		 7303 * Call vendor specific resume callback. As these callbacks may access
7304 * vendor specific host controller register space call them when the
7305 * host clocks are ON.
7a3e97b0 7306 */
0263bcd0
YG		 7307 ret = ufshcd_vops_resume(hba, pm_op);
7308 if (ret)
7309 goto disable_vreg;
57d104c1
SJ		 7310
7311 if (ufshcd_is_link_hibern8(hba)) {
7312 ret = ufshcd_uic_hibern8_exit(hba);
7313 if (!ret)
7314 ufshcd_set_link_active(hba);
7315 else
7316 goto vendor_suspend;
7317 } else if (ufshcd_is_link_off(hba)) {
7318 ret = ufshcd_host_reset_and_restore(hba);
7319 /*
7320 * ufshcd_host_reset_and_restore() should have already
7321 * set the link state as active
7322 */
7323 if (ret || !ufshcd_is_link_active(hba))
7324 goto vendor_suspend;
7325 }
7326
7327 if (!ufshcd_is_ufs_dev_active(hba)) {
7328 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7329 if (ret)
7330 goto set_old_link_state;
7331 }
7332
4e768e76
SJ		 7333 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7334 ufshcd_enable_auto_bkops(hba);
7335 else
7336 /*
7337 * If BKOPs operations are urgently needed at this moment then
7338 * keep auto-bkops enabled or else disable it.
7339 */
7340 ufshcd_urgent_bkops(hba);
7341
1ab27c9c
ST		 7342 hba->clk_gating.is_suspended = false;
7343
fcb0c4b0
ST		 7344 if (hba->clk_scaling.is_allowed)
7345 ufshcd_resume_clkscaling(hba);
856b3483 7346
1ab27c9c
ST		 7347 /* Schedule clock gating in case of no access to UFS device yet */
7348 ufshcd_release(hba);
57d104c1
SJ		 7349 goto out;
7350
7351set_old_link_state:
7352 ufshcd_link_state_transition(hba, old_link_state, 0);
7353vendor_suspend:
0263bcd0 7354 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 7355disable_vreg:
7356 ufshcd_vreg_set_lpm(hba);
7357disable_irq_and_vops_clks:
7358 ufshcd_disable_irq(hba);
401f1e44
SJ		 7359 if (hba->clk_scaling.is_allowed)
7360 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 7361 ufshcd_setup_clocks(hba, false);
7362out:
7363 hba->pm_op_in_progress = 0;
7364 return ret;
7365}
7366
7367/**
7368 * ufshcd_system_suspend - system suspend routine
7369 * @hba: per adapter instance
7370 * @pm_op: runtime PM or system PM
7371 *
7372 * Check the description of ufshcd_suspend() function for more details.
7373 *
7374 * Returns 0 for success and non-zero for failure
7375 */
7376int ufshcd_system_suspend(struct ufs_hba *hba)
7377{
7378 int ret = 0;
7ff5ab47 7379 ktime_t start = ktime_get();
57d104c1
SJ		 7380
7381 if (!hba || !hba->is_powered)
233b594b 7382 return 0;
57d104c1 7383
0b257734
SJ		 7384 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7385 hba->curr_dev_pwr_mode) &&
7386 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7387 hba->uic_link_state))
7388 goto out;
57d104c1 7389
0b257734 7390 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 7391 /*
7392 * UFS device and/or UFS link low power states during runtime
7393 * suspend seems to be different than what is expected during
7394 * system suspend. Hence runtime resume the devic & link and
7395 * let the system suspend low power states to take effect.
7396 * TODO: If resume takes longer time, we might have optimize
7397 * it in future by not resuming everything if possible.
7398 */
7399 ret = ufshcd_runtime_resume(hba);
7400 if (ret)
7401 goto out;
7402 }
7403
7404 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7405out:
7ff5ab47
SJ		 7406 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7407 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7408 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 7409 if (!ret)
7410 hba->is_sys_suspended = true;
57d104c1
SJ		 7411 return ret;
7412}
7413EXPORT_SYMBOL(ufshcd_system_suspend);
7414
7415/**
7416 * ufshcd_system_resume - system resume routine
7417 * @hba: per adapter instance
7418 *
7419 * Returns 0 for success and non-zero for failure
7420 */
7a3e97b0 7421
57d104c1
SJ		 7422int ufshcd_system_resume(struct ufs_hba *hba)
7423{
7ff5ab47
SJ		 7424 int ret = 0;
7425 ktime_t start = ktime_get();
7426
e3ce73d6
YG		 7427 if (!hba)
7428 return -EINVAL;
7429
7430 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 7431 /*
7432 * Let the runtime resume take care of resuming
7433 * if runtime suspended.
7434 */
7ff5ab47
SJ		 7435 goto out;
7436 else
7437 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7438out:
7439 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7440 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7441 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7442 return ret;
7a3e97b0 7443}
57d104c1 7444EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 7445
57d104c1
SJ		 7446/**
7447 * ufshcd_runtime_suspend - runtime suspend routine
7448 * @hba: per adapter instance
7449 *
7450 * Check the description of ufshcd_suspend() function for more details.
7451 *
7452 * Returns 0 for success and non-zero for failure
7453 */
66ec6d59
SRT		 7454int ufshcd_runtime_suspend(struct ufs_hba *hba)
7455{
7ff5ab47
SJ		 7456 int ret = 0;
7457 ktime_t start = ktime_get();
7458
e3ce73d6
YG		 7459 if (!hba)
7460 return -EINVAL;
7461
7462 if (!hba->is_powered)
7ff5ab47
SJ		 7463 goto out;
7464 else
7465 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7466out:
7467 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7468 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7469 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7470 return ret;
66ec6d59
SRT		 7471}
7472EXPORT_SYMBOL(ufshcd_runtime_suspend);
7473
57d104c1
SJ		 7474/**
7475 * ufshcd_runtime_resume - runtime resume routine
7476 * @hba: per adapter instance
7477 *
7478 * This function basically brings the UFS device, UniPro link and controller
7479 * to active state. Following operations are done in this function:
7480 *
7481 * 1. Turn on all the controller related clocks
7482 * 2. Bring the UniPro link out of Hibernate state
7483 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
7484 * to active state.
7485 * 4. If auto-bkops is enabled on the device, disable it.
7486 *
7487 * So following would be the possible power state after this function return
7488 * successfully:
7489 * S1: UFS device in Active state with VCC rail ON
7490 * UniPro link in Active state
7491 * All the UFS/UniPro controller clocks are ON
7492 *
7493 * Returns 0 for success and non-zero for failure
7494 */
66ec6d59
SRT		 7495int ufshcd_runtime_resume(struct ufs_hba *hba)
7496{
7ff5ab47
SJ		 7497 int ret = 0;
7498 ktime_t start = ktime_get();
7499
e3ce73d6
YG		 7500 if (!hba)
7501 return -EINVAL;
7502
7503 if (!hba->is_powered)
7ff5ab47
SJ		 7504 goto out;
7505 else
7506 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
7507out:
7508 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
7509 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7510 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7511 return ret;
66ec6d59
SRT		 7512}
7513EXPORT_SYMBOL(ufshcd_runtime_resume);
7514
7515int ufshcd_runtime_idle(struct ufs_hba *hba)
7516{
7517 return 0;
7518}
7519EXPORT_SYMBOL(ufshcd_runtime_idle);
7520
09690d5a
SJ		 7521static inline ssize_t ufshcd_pm_lvl_store(struct device *dev,
7522 struct device_attribute *attr,
7523 const char *buf, size_t count,
7524 bool rpm)
7525{
7526 struct ufs_hba *hba = dev_get_drvdata(dev);
7527 unsigned long flags, value;
7528
7529 if (kstrtoul(buf, 0, &value))
7530 return -EINVAL;
7531
7532 if ((value < UFS_PM_LVL_0) || (value >= UFS_PM_LVL_MAX))
7533 return -EINVAL;
7534
7535 spin_lock_irqsave(hba->host->host_lock, flags);
7536 if (rpm)
7537 hba->rpm_lvl = value;
7538 else
7539 hba->spm_lvl = value;
7540 spin_unlock_irqrestore(hba->host->host_lock, flags);
7541 return count;
7542}
7543
7544static ssize_t ufshcd_rpm_lvl_show(struct device *dev,
7545 struct device_attribute *attr, char *buf)
7546{
7547 struct ufs_hba *hba = dev_get_drvdata(dev);
7548 int curr_len;
7549 u8 lvl;
7550
7551 curr_len = snprintf(buf, PAGE_SIZE,
7552 "\nCurrent Runtime PM level [%d] => dev_state [%s] link_state [%s]\n",
7553 hba->rpm_lvl,
7554 ufschd_ufs_dev_pwr_mode_to_string(
7555 ufs_pm_lvl_states[hba->rpm_lvl].dev_state),
7556 ufschd_uic_link_state_to_string(
7557 ufs_pm_lvl_states[hba->rpm_lvl].link_state));
7558
7559 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7560 "\nAll available Runtime PM levels info:\n");
7561 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
7562 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7563 "\tRuntime PM level [%d] => dev_state [%s] link_state [%s]\n",
7564 lvl,
7565 ufschd_ufs_dev_pwr_mode_to_string(
7566 ufs_pm_lvl_states[lvl].dev_state),
7567 ufschd_uic_link_state_to_string(
7568 ufs_pm_lvl_states[lvl].link_state));
7569
7570 return curr_len;
7571}
7572
7573static ssize_t ufshcd_rpm_lvl_store(struct device *dev,
7574 struct device_attribute *attr, const char *buf, size_t count)
7575{
7576 return ufshcd_pm_lvl_store(dev, attr, buf, count, true);
7577}
7578
7579static void ufshcd_add_rpm_lvl_sysfs_nodes(struct ufs_hba *hba)
7580{
7581 hba->rpm_lvl_attr.show = ufshcd_rpm_lvl_show;
7582 hba->rpm_lvl_attr.store = ufshcd_rpm_lvl_store;
7583 sysfs_attr_init(&hba->rpm_lvl_attr.attr);
7584 hba->rpm_lvl_attr.attr.name = "rpm_lvl";
7585 hba->rpm_lvl_attr.attr.mode = 0644;
7586 if (device_create_file(hba->dev, &hba->rpm_lvl_attr))
7587 dev_err(hba->dev, "Failed to create sysfs for rpm_lvl\n");
7588}
7589
7590static ssize_t ufshcd_spm_lvl_show(struct device *dev,
7591 struct device_attribute *attr, char *buf)
7592{
7593 struct ufs_hba *hba = dev_get_drvdata(dev);
7594 int curr_len;
7595 u8 lvl;
7596
7597 curr_len = snprintf(buf, PAGE_SIZE,
7598 "\nCurrent System PM level [%d] => dev_state [%s] link_state [%s]\n",
7599 hba->spm_lvl,
7600 ufschd_ufs_dev_pwr_mode_to_string(
7601 ufs_pm_lvl_states[hba->spm_lvl].dev_state),
7602 ufschd_uic_link_state_to_string(
7603 ufs_pm_lvl_states[hba->spm_lvl].link_state));
7604
7605 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7606 "\nAll available System PM levels info:\n");
7607 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
7608 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7609 "\tSystem PM level [%d] => dev_state [%s] link_state [%s]\n",
7610 lvl,
7611 ufschd_ufs_dev_pwr_mode_to_string(
7612 ufs_pm_lvl_states[lvl].dev_state),
7613 ufschd_uic_link_state_to_string(
7614 ufs_pm_lvl_states[lvl].link_state));
7615
7616 return curr_len;
7617}
7618
7619static ssize_t ufshcd_spm_lvl_store(struct device *dev,
7620 struct device_attribute *attr, const char *buf, size_t count)
7621{
7622 return ufshcd_pm_lvl_store(dev, attr, buf, count, false);
7623}
7624
7625static void ufshcd_add_spm_lvl_sysfs_nodes(struct ufs_hba *hba)
7626{
7627 hba->spm_lvl_attr.show = ufshcd_spm_lvl_show;
7628 hba->spm_lvl_attr.store = ufshcd_spm_lvl_store;
7629 sysfs_attr_init(&hba->spm_lvl_attr.attr);
7630 hba->spm_lvl_attr.attr.name = "spm_lvl";
7631 hba->spm_lvl_attr.attr.mode = 0644;
7632 if (device_create_file(hba->dev, &hba->spm_lvl_attr))
7633 dev_err(hba->dev, "Failed to create sysfs for spm_lvl\n");
7634}
7635
7636static inline void ufshcd_add_sysfs_nodes(struct ufs_hba *hba)
7637{
7638 ufshcd_add_rpm_lvl_sysfs_nodes(hba);
7639 ufshcd_add_spm_lvl_sysfs_nodes(hba);
7640}
7641
57d104c1
SJ		 7642/**
7643 * ufshcd_shutdown - shutdown routine
7644 * @hba: per adapter instance
7645 *
7646 * This function would power off both UFS device and UFS link.
7647 *
7648 * Returns 0 always to allow force shutdown even in case of errors.
7649 */
7650int ufshcd_shutdown(struct ufs_hba *hba)
7651{
7652 int ret = 0;
7653
7654 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
7655 goto out;
7656
7657 if (pm_runtime_suspended(hba->dev)) {
7658 ret = ufshcd_runtime_resume(hba);
7659 if (ret)
7660 goto out;
7661 }
7662
7663 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
7664out:
7665 if (ret)
7666 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
7667 /* allow force shutdown even in case of errors */
7668 return 0;
7669}
7670EXPORT_SYMBOL(ufshcd_shutdown);
7671
7a3e97b0 7672/**
3b1d0580 7673 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 7674 * data structure memory
3b1d0580 7675 * @hba - per adapter instance
7a3e97b0 7676 */
3b1d0580 7677void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 7678{
cfdf9c91 7679 scsi_remove_host(hba->host);
7a3e97b0 7680 /* disable interrupts */
2fbd009b 7681 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 7682 ufshcd_hba_stop(hba, true);
7a3e97b0 7683
1ab27c9c 7684 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 7685 if (ufshcd_is_clkscaling_supported(hba))
7686 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 7687 ufshcd_hba_exit(hba);
3b1d0580
VH		 7688}
7689EXPORT_SYMBOL_GPL(ufshcd_remove);
7690
47555a5c
YG		 7691/**
7692 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
7693 * @hba: pointer to Host Bus Adapter (HBA)
7694 */
7695void ufshcd_dealloc_host(struct ufs_hba *hba)
7696{
7697 scsi_host_put(hba->host);
7698}
7699EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
7700
ca3d7bf9
AM		 7701/**
7702 * ufshcd_set_dma_mask - Set dma mask based on the controller
7703 * addressing capability
7704 * @hba: per adapter instance
7705 *
7706 * Returns 0 for success, non-zero for failure
7707 */
7708static int ufshcd_set_dma_mask(struct ufs_hba *hba)
7709{
7710 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
7711 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
7712 return 0;
7713 }
7714 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
7715}
7716
7a3e97b0 7717/**
5c0c28a8 7718 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 7719 * @dev: pointer to device handle
7720 * @hba_handle: driver private handle
7a3e97b0
SY		 7721 * Returns 0 on success, non-zero value on failure
7722 */
5c0c28a8 7723int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 7724{
7725 struct Scsi_Host *host;
7726 struct ufs_hba *hba;
5c0c28a8 7727 int err = 0;
7a3e97b0 7728
3b1d0580
VH		 7729 if (!dev) {
7730 dev_err(dev,
7731 "Invalid memory reference for dev is NULL\n");
7732 err = -ENODEV;
7a3e97b0
SY		 7733 goto out_error;
7734 }
7735
7a3e97b0
SY		 7736 host = scsi_host_alloc(&ufshcd_driver_template,
7737 sizeof(struct ufs_hba));
7738 if (!host) {
3b1d0580 7739 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 7740 err = -ENOMEM;
3b1d0580 7741 goto out_error;
7a3e97b0
SY		 7742 }
7743 hba = shost_priv(host);
7a3e97b0 7744 hba->host = host;
3b1d0580 7745 hba->dev = dev;
5c0c28a8
SRT		 7746 *hba_handle = hba;
7747
7748out_error:
7749 return err;
7750}
7751EXPORT_SYMBOL(ufshcd_alloc_host);
7752
7753/**
7754 * ufshcd_init - Driver initialization routine
7755 * @hba: per-adapter instance
7756 * @mmio_base: base register address
7757 * @irq: Interrupt line of device
7758 * Returns 0 on success, non-zero value on failure
7759 */
7760int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
7761{
7762 int err;
7763 struct Scsi_Host *host = hba->host;
7764 struct device *dev = hba->dev;
7765
7766 if (!mmio_base) {
7767 dev_err(hba->dev,
7768 "Invalid memory reference for mmio_base is NULL\n");
7769 err = -ENODEV;
7770 goto out_error;
7771 }
7772
3b1d0580
VH		 7773 hba->mmio_base = mmio_base;
7774 hba->irq = irq;
7a3e97b0 7775
aa497613 7776 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 7777 if (err)
7778 goto out_error;
7779
7a3e97b0
SY		 7780 /* Read capabilities registers */
7781 ufshcd_hba_capabilities(hba);
7782
7783 /* Get UFS version supported by the controller */
7784 hba->ufs_version = ufshcd_get_ufs_version(hba);
7785
c01848c6
YG		 7786 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
7787 (hba->ufs_version != UFSHCI_VERSION_11) &&
7788 (hba->ufs_version != UFSHCI_VERSION_20) &&
7789 (hba->ufs_version != UFSHCI_VERSION_21))
7790 dev_err(hba->dev, "invalid UFS version 0x%x\n",
7791 hba->ufs_version);
7792
2fbd009b
SJ		 7793 /* Get Interrupt bit mask per version */
7794 hba->intr_mask = ufshcd_get_intr_mask(hba);
7795
ca3d7bf9
AM		 7796 err = ufshcd_set_dma_mask(hba);
7797 if (err) {
7798 dev_err(hba->dev, "set dma mask failed\n");
7799 goto out_disable;
7800 }
7801
7a3e97b0
SY		 7802 /* Allocate memory for host memory space */
7803 err = ufshcd_memory_alloc(hba);
7804 if (err) {
3b1d0580
VH		 7805 dev_err(hba->dev, "Memory allocation failed\n");
7806 goto out_disable;
7a3e97b0
SY		 7807 }
7808
7809 /* Configure LRB */
7810 ufshcd_host_memory_configure(hba);
7811
7812 host->can_queue = hba->nutrs;
7813 host->cmd_per_lun = hba->nutrs;
7814 host->max_id = UFSHCD_MAX_ID;
0ce147d4 7815 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 7816 host->max_channel = UFSHCD_MAX_CHANNEL;
7817 host->unique_id = host->host_no;
7818 host->max_cmd_len = MAX_CDB_SIZE;
7819
7eb584db
DR		 7820 hba->max_pwr_info.is_valid = false;
7821
7a3e97b0 7822 /* Initailize wait queue for task management */
e2933132
SRT		 7823 init_waitqueue_head(&hba->tm_wq);
7824 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 7825
7826 /* Initialize work queues */
e8e7f271 7827 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 7828 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 7829
6ccf44fe
SJ		 7830 /* Initialize UIC command mutex */
7831 mutex_init(&hba->uic_cmd_mutex);
7832
5a0b0cb9
SRT		 7833 /* Initialize mutex for device management commands */
7834 mutex_init(&hba->dev_cmd.lock);
7835
a3cd5ec5
SJ		 7836 init_rwsem(&hba->clk_scaling_lock);
7837
5a0b0cb9
SRT		 7838 /* Initialize device management tag acquire wait queue */
7839 init_waitqueue_head(&hba->dev_cmd.tag_wq);
7840
1ab27c9c 7841 ufshcd_init_clk_gating(hba);
199ef13c
YG		 7842
7843 /*
7844 * In order to avoid any spurious interrupt immediately after
7845 * registering UFS controller interrupt handler, clear any pending UFS
7846 * interrupt status and disable all the UFS interrupts.
7847 */
7848 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
7849 REG_INTERRUPT_STATUS);
7850 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
7851 /*
7852 * Make sure that UFS interrupts are disabled and any pending interrupt
7853 * status is cleared before registering UFS interrupt handler.
7854 */
7855 mb();
7856
7a3e97b0 7857 /* IRQ registration */
2953f850 7858 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 7859 if (err) {
3b1d0580 7860 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 7861 goto exit_gating;
57d104c1
SJ		 7862 } else {
7863 hba->is_irq_enabled = true;
7a3e97b0
SY		 7864 }
7865
3b1d0580 7866 err = scsi_add_host(host, hba->dev);
7a3e97b0 7867 if (err) {
3b1d0580 7868 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 7869 goto exit_gating;
7a3e97b0
SY		 7870 }
7871
6ccf44fe
SJ		 7872 /* Host controller enable */
7873 err = ufshcd_hba_enable(hba);
7a3e97b0 7874 if (err) {
6ccf44fe 7875 dev_err(hba->dev, "Host controller enable failed\n");
66cc820f 7876 ufshcd_print_host_regs(hba);
6ba65588 7877 ufshcd_print_host_state(hba);
3b1d0580 7878 goto out_remove_scsi_host;
7a3e97b0 7879 }
6ccf44fe 7880
fcb0c4b0 7881 if (ufshcd_is_clkscaling_supported(hba)) {
401f1e44
SJ		 7882 char wq_name[sizeof("ufs_clkscaling_00")];
7883
401f1e44
SJ		 7884 INIT_WORK(&hba->clk_scaling.suspend_work,
7885 ufshcd_clk_scaling_suspend_work);
7886 INIT_WORK(&hba->clk_scaling.resume_work,
7887 ufshcd_clk_scaling_resume_work);
7888
7889 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clkscaling_%d",
7890 host->host_no);
7891 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
7892
fcb0c4b0 7893 ufshcd_clkscaling_init_sysfs(hba);
856b3483
ST		 7894 }
7895
0c8f7586
SJ		 7896 /*
7897 * Set the default power management level for runtime and system PM.
7898 * Default power saving mode is to keep UFS link in Hibern8 state
7899 * and UFS device in sleep state.
7900 */
7901 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7902 UFS_SLEEP_PWR_MODE,
7903 UIC_LINK_HIBERN8_STATE);
7904 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
7905 UFS_SLEEP_PWR_MODE,
7906 UIC_LINK_HIBERN8_STATE);
7907
62694735
SRT		 7908 /* Hold auto suspend until async scan completes */
7909 pm_runtime_get_sync(dev);
7910
57d104c1 7911 /*
7caf489b
SJ		 7912 * We are assuming that device wasn't put in sleep/power-down
7913 * state exclusively during the boot stage before kernel.
7914 * This assumption helps avoid doing link startup twice during
7915 * ufshcd_probe_hba().
57d104c1 7916 */
7caf489b 7917 ufshcd_set_ufs_dev_active(hba);
57d104c1 7918
6ccf44fe 7919 async_schedule(ufshcd_async_scan, hba);
09690d5a 7920 ufshcd_add_sysfs_nodes(hba);
6ccf44fe 7921
7a3e97b0
SY		 7922 return 0;
7923
3b1d0580
VH		 7924out_remove_scsi_host:
7925 scsi_remove_host(hba->host);
1ab27c9c
ST		 7926exit_gating:
7927 ufshcd_exit_clk_gating(hba);
3b1d0580 7928out_disable:
57d104c1 7929 hba->is_irq_enabled = false;
aa497613 7930 ufshcd_hba_exit(hba);
3b1d0580
VH		 7931out_error:
7932 return err;
7933}
7934EXPORT_SYMBOL_GPL(ufshcd_init);
7935
3b1d0580
VH		 7936MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
7937MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 7938MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 7939MODULE_LICENSE("GPL");
7940MODULE_VERSION(UFSHCD_DRIVER_VERSION);