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scsi: change scsi_softirq_done as external
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
b573d484 42#include <linux/nls.h>
54b879b7 43#include <linux/of.h>
e0eca63e 44#include "ufshcd.h"
c58ab7aa 45#include "ufs_quirks.h"
53b3d9c3 46#include "unipro.h"
8d65d1bb 47#include "ufs-exynos.h"
48#include "ufs_quirks.h"
7a3e97b0 49
7ff5ab47
SJ		 50#define CREATE_TRACE_POINTS
51#include <trace/events/ufs.h>
52
dcea0bfb
GB		 53#define UFSHCD_REQ_SENSE_SIZE 18
54
2fbd009b
SJ		 55#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
56 UTP_TASK_REQ_COMPL |\
57 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 58/* UIC command timeout, unit: ms */
59#define UIC_CMD_TIMEOUT 500
2fbd009b 60
5a0b0cb9
SRT		 61/* NOP OUT retries waiting for NOP IN response */
62#define NOP_OUT_RETRIES 10
63/* Timeout after 30 msecs if NOP OUT hangs without response */
64#define NOP_OUT_TIMEOUT 30 /* msecs */
65
68078d5c 66/* Query request retries */
10fe5888 67#define QUERY_REQ_RETRIES 3
68078d5c 68/* Query request timeout */
10fe5888 69#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 70
e2933132
SRT		 71/* Task management command timeout */
72#define TM_CMD_TIMEOUT 100 /* msecs */
73
64238fbd
YG		 74/* maximum number of retries for a general UIC command */
75#define UFS_UIC_COMMAND_RETRIES 3
76
1d337ec2
SRT		 77/* maximum number of link-startup retries */
78#define DME_LINKSTARTUP_RETRIES 3
79
87d0b4a6
YG		 80/* Maximum retries for Hibern8 enter */
81#define UIC_HIBERN8_ENTER_RETRIES 3
82
1d337ec2
SRT		 83/* maximum number of reset retries before giving up */
84#define MAX_HOST_RESET_RETRIES 5
85
68078d5c
DR		 86/* Expose the flag value from utp_upiu_query.value */
87#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
88
7d568652 89/* Interrupt aggregation default timeout, unit: 40us */
623b5fe3 90#define INT_AGGR_DEF_TO 0x01
91
92/* Link Hibernation delay, msecs */
93#define LINK_H8_DELAY 20
94
251f4e5f 95/* UFS link setup retries */
96#define UFS_LINK_SETUP_RETRIES 5
7d568652 97
aa497613
SRT		 98#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
99 ({ \
100 int _ret; \
101 if (_on) \
102 _ret = ufshcd_enable_vreg(_dev, _vreg); \
103 else \
104 _ret = ufshcd_disable_vreg(_dev, _vreg); \
105 _ret; \
106 })
107
66cc820f
DR		 108#define ufshcd_hex_dump(prefix_str, buf, len) \
109print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, len, false)
110
7a3e97b0
SY		 111enum {
112 UFSHCD_MAX_CHANNEL = 0,
113 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 114 UFSHCD_CMD_PER_LUN = 32,
115 UFSHCD_CAN_QUEUE = 32,
116};
117
118/* UFSHCD states */
119enum {
7a3e97b0
SY		 120 UFSHCD_STATE_RESET,
121 UFSHCD_STATE_ERROR,
3441da7d 122 UFSHCD_STATE_OPERATIONAL,
141f8165 123 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 124};
125
126/* UFSHCD error handling flags */
127enum {
128 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 129};
130
e8e7f271
SRT		 131/* UFSHCD UIC layer error flags */
132enum {
133 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 134 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
135 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
136 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
137 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
138 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
a60d7ef4 139 UFSHCD_UIC_DL_ERROR = (1 << 6), /* Data link layer error */
e8e7f271
SRT		 140};
141
3441da7d 142#define ufshcd_set_eh_in_progress(h) \
9c490d2d 143 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 144#define ufshcd_eh_in_progress(h) \
9c490d2d 145 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 146#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 147 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 148
57d104c1
SJ		 149#define ufshcd_set_ufs_dev_active(h) \
150 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
151#define ufshcd_set_ufs_dev_sleep(h) \
152 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
153#define ufshcd_set_ufs_dev_poweroff(h) \
154 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
155#define ufshcd_is_ufs_dev_active(h) \
156 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
157#define ufshcd_is_ufs_dev_sleep(h) \
158 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
159#define ufshcd_is_ufs_dev_poweroff(h) \
160 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
161
162static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
163 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
164 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
165 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
166 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
167 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
168 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
169};
170
171static inline enum ufs_dev_pwr_mode
172ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
173{
174 return ufs_pm_lvl_states[lvl].dev_state;
175}
176
177static inline enum uic_link_state
178ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
179{
180 return ufs_pm_lvl_states[lvl].link_state;
181}
182
0c8f7586
SJ		 183static inline enum ufs_pm_level
184ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
185 enum uic_link_state link_state)
186{
187 enum ufs_pm_level lvl;
188
189 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
190 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
191 (ufs_pm_lvl_states[lvl].link_state == link_state))
192 return lvl;
193 }
194
195 /* if no match found, return the level 0 */
196 return UFS_PM_LVL_0;
197}
198
56d4a186
SJ		 199static struct ufs_dev_fix ufs_fixups[] = {
200 /* UFS cards deviations table */
201 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
202 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
203 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
204 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
205 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
206 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
207 UFS_DEVICE_NO_FASTAUTO),
208 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
209 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
210 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
211 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
212 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
213 UFS_DEVICE_QUIRK_PA_TACTIVATE),
214 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
215 UFS_DEVICE_QUIRK_PA_TACTIVATE),
216 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
217 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
218 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
219
220 END_FIX
221};
222
3441da7d
SRT		 223static void ufshcd_tmc_handler(struct ufs_hba *hba);
224static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 225static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 226static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 227static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 228static void ufshcd_hba_exit(struct ufs_hba *hba);
229static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 230static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
231 bool skip_ref_clk);
232static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 233static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 234static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
235static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
0f7f11ff 236static int ufshcd_link_hibern8_ctrl(struct ufs_hba *hba, bool en);
cad2e03d 237static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 238static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 239static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
240static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 241static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 242static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 243static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 244static int ufshcd_change_power_mode(struct ufs_hba *hba,
245 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 246static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
247{
248 return tag >= 0 && tag < hba->nutrs;
249}
57d104c1
SJ		 250
251static inline int ufshcd_enable_irq(struct ufs_hba *hba)
252{
253 int ret = 0;
254
255 if (!hba->is_irq_enabled) {
256 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
257 hba);
258 if (ret)
259 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
260 __func__, ret);
261 hba->is_irq_enabled = true;
262 }
263
264 return ret;
265}
266
267static inline void ufshcd_disable_irq(struct ufs_hba *hba)
268{
269 if (hba->is_irq_enabled) {
270 free_irq(hba->irq, hba);
271 hba->is_irq_enabled = false;
272 }
273}
3441da7d 274
b573d484
YG		 275/* replace non-printable or non-ASCII characters with spaces */
276static inline void ufshcd_remove_non_printable(char *val)
277{
278 if (!val)
279 return;
280
281 if (*val < 0x20 || *val > 0x7e)
282 *val = ' ';
283}
284
1a07f2d9
LS		 285static void ufshcd_add_command_trace(struct ufs_hba *hba,
286 unsigned int tag, const char *str)
287{
288 sector_t lba = -1;
289 u8 opcode = 0;
290 u32 intr, doorbell;
291 struct ufshcd_lrb *lrbp;
292 int transfer_len = -1;
293
294 if (!trace_ufshcd_command_enabled())
295 return;
296
297 lrbp = &hba->lrb[tag];
298
299 if (lrbp->cmd) { /* data phase exists */
300 opcode = (u8)(*lrbp->cmd->cmnd);
301 if ((opcode == READ_10) || (opcode == WRITE_10)) {
302 /*
303 * Currently we only fully trace read(10) and write(10)
304 * commands
305 */
306 if (lrbp->cmd->request && lrbp->cmd->request->bio)
307 lba =
308 lrbp->cmd->request->bio->bi_iter.bi_sector;
309 transfer_len = be32_to_cpu(
310 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
311 }
312 }
313
314 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
315 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
316 trace_ufshcd_command(dev_name(hba->dev), str, tag,
317 doorbell, transfer_len, intr, lba, opcode);
318}
319
ff8e20c6
DR		 320static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
321{
322 struct ufs_clk_info *clki;
323 struct list_head *head = &hba->clk_list_head;
324
566ec9ad 325 if (list_empty(head))
ff8e20c6
DR		 326 return;
327
328 list_for_each_entry(clki, head, list) {
329 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
330 clki->max_freq)
331 dev_err(hba->dev, "clk: %s, rate: %u\n",
332 clki->name, clki->curr_freq);
333 }
334}
335
336static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
337 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
338{
339 int i;
340
341 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
342 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
343
344 if (err_hist->reg[p] == 0)
345 continue;
346 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
347 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
348 }
349}
350
66cc820f
DR		 351static void ufshcd_print_host_regs(struct ufs_hba *hba)
352{
353 /*
354 * hex_dump reads its data without the readl macro. This might
355 * cause inconsistency issues on some platform, as the printed
356 * values may be from cache and not the most recent value.
357 * To know whether you are looking at an un-cached version verify
358 * that IORESOURCE_MEM flag is on when xxx_get_resource() is invoked
359 * during platform/pci probe function.
360 */
361 ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE);
362 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
363 hba->ufs_version, hba->capabilities);
364 dev_err(hba->dev,
365 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
366 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 367 dev_err(hba->dev,
368 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
369 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
370 hba->ufs_stats.hibern8_exit_cnt);
371
372 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
373 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
374 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
375 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
376 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
377
378 ufshcd_print_clk_freqs(hba);
379
380 if (hba->vops && hba->vops->dbg_register_dump)
381 hba->vops->dbg_register_dump(hba);
66cc820f
DR		 382}
383
384static
385void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
386{
387 struct ufshcd_lrb *lrbp;
7fabb77b 388 int prdt_length;
66cc820f
DR		 389 int tag;
390
391 for_each_set_bit(tag, &bitmap, hba->nutrs) {
392 lrbp = &hba->lrb[tag];
393
ff8e20c6
DR		 394 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
395 tag, ktime_to_us(lrbp->issue_time_stamp));
396 dev_err(hba->dev,
397 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
398 tag, (u64)lrbp->utrd_dma_addr);
399
66cc820f
DR		 400 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
401 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 402 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
403 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 404 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
405 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 406 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
407 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 408 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
409 sizeof(struct utp_upiu_rsp));
66cc820f 410
7fabb77b
GB		 411 prdt_length = le16_to_cpu(
412 lrbp->utr_descriptor_ptr->prd_table_length);
413 dev_err(hba->dev,
414 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
415 tag, prdt_length,
416 (u64)lrbp->ucd_prdt_dma_addr);
417
418 if (pr_prdt)
66cc820f 419 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 420 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 421 }
422}
423
424static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
425{
426 struct utp_task_req_desc *tmrdp;
427 int tag;
428
429 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
430 tmrdp = &hba->utmrdl_base_addr[tag];
431 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
432 ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
433 sizeof(struct request_desc_header));
434 dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
435 tag);
436 ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
437 sizeof(struct utp_upiu_req));
438 dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
439 tag);
440 ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
441 sizeof(struct utp_task_req_desc));
442 }
443}
444
6ba65588
GB		 445static void ufshcd_print_host_state(struct ufs_hba *hba)
446{
447 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
448 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
e002e651 449 hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 450 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
451 hba->saved_err, hba->saved_uic_err);
452 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
453 hba->curr_dev_pwr_mode, hba->uic_link_state);
454 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
455 hba->pm_op_in_progress, hba->is_sys_suspended);
456 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
457 hba->auto_bkops_enabled, hba->host->host_self_blocked);
458 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
459 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
460 hba->eh_flags, hba->req_abort_count);
461 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
462 hba->capabilities, hba->caps);
463 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
464 hba->dev_quirks);
465}
466
ff8e20c6
DR		 467/**
468 * ufshcd_print_pwr_info - print power params as saved in hba
469 * power info
470 * @hba: per-adapter instance
471 */
472static void ufshcd_print_pwr_info(struct ufs_hba *hba)
473{
474 static const char * const names[] = {
475 "INVALID MODE",
476 "FAST MODE",
477 "SLOW_MODE",
478 "INVALID MODE",
479 "FASTAUTO_MODE",
480 "SLOWAUTO_MODE",
481 "INVALID MODE",
482 };
483
484 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
485 __func__,
486 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
487 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
488 names[hba->pwr_info.pwr_rx],
489 names[hba->pwr_info.pwr_tx],
490 hba->pwr_info.hs_rate);
491}
492
5a0b0cb9
SRT		 493/*
494 * ufshcd_wait_for_register - wait for register value to change
495 * @hba - per-adapter interface
496 * @reg - mmio register offset
497 * @mask - mask to apply to read register value
498 * @val - wait condition
499 * @interval_us - polling interval in microsecs
500 * @timeout_ms - timeout in millisecs
596585a2 501 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 502 *
503 * Returns -ETIMEDOUT on error, zero on success
504 */
596585a2
YG		 505int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
506 u32 val, unsigned long interval_us,
507 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 508{
509 int err = 0;
510 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
511
512 /* ignore bits that we don't intend to wait on */
513 val = val & mask;
514
515 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 516 if (can_sleep)
517 usleep_range(interval_us, interval_us + 50);
518 else
519 udelay(interval_us);
5a0b0cb9
SRT		 520 if (time_after(jiffies, timeout)) {
521 if ((ufshcd_readl(hba, reg) & mask) != val)
522 err = -ETIMEDOUT;
523 break;
524 }
525 }
526
527 return err;
528}
529
2fbd009b
SJ		 530/**
531 * ufshcd_get_intr_mask - Get the interrupt bit mask
532 * @hba - Pointer to adapter instance
533 *
534 * Returns interrupt bit mask per version
535 */
536static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
537{
c01848c6
YG		 538 u32 intr_mask = 0;
539
540 switch (hba->ufs_version) {
541 case UFSHCI_VERSION_10:
542 intr_mask = INTERRUPT_MASK_ALL_VER_10;
543 break;
c01848c6
YG		 544 case UFSHCI_VERSION_11:
545 case UFSHCI_VERSION_20:
546 intr_mask = INTERRUPT_MASK_ALL_VER_11;
547 break;
c01848c6
YG		 548 case UFSHCI_VERSION_21:
549 default:
550 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 551 break;
c01848c6
YG		 552 }
553
554 return intr_mask;
2fbd009b
SJ		 555}
556
7a3e97b0
SY		 557/**
558 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
559 * @hba - Pointer to adapter instance
560 *
561 * Returns UFSHCI version supported by the controller
562 */
563static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
564{
0263bcd0
YG		 565 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
566 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 567
b873a275 568 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 569}
570
571/**
572 * ufshcd_is_device_present - Check if any device connected to
573 * the host controller
5c0c28a8 574 * @hba: pointer to adapter instance
7a3e97b0 575 *
c9e6010b 576 * Returns true if device present, false if no device detected
7a3e97b0 577 */
c9e6010b 578static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 579{
5c0c28a8 580 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 581 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 582}
583
584/**
585 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
586 * @lrb: pointer to local command reference block
587 *
588 * This function is used to get the OCS field from UTRD
589 * Returns the OCS field in the UTRD
590 */
591static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
592{
e8c8e82a 593 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 594}
595
596/**
597 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
598 * @task_req_descp: pointer to utp_task_req_desc structure
599 *
600 * This function is used to get the OCS field from UTMRD
601 * Returns the OCS field in the UTMRD
602 */
603static inline int
604ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
605{
e8c8e82a 606 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 607}
608
609/**
610 * ufshcd_get_tm_free_slot - get a free slot for task management request
611 * @hba: per adapter instance
e2933132 612 * @free_slot: pointer to variable with available slot value
7a3e97b0 613 *
e2933132
SRT		 614 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
615 * Returns 0 if free slot is not available, else return 1 with tag value
616 * in @free_slot.
7a3e97b0 617 */
e2933132 618static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 619{
e2933132
SRT		 620 int tag;
621 bool ret = false;
622
623 if (!free_slot)
624 goto out;
625
626 do {
627 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
628 if (tag >= hba->nutmrs)
629 goto out;
630 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
631
632 *free_slot = tag;
633 ret = true;
634out:
635 return ret;
636}
637
638static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
639{
640 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 641}
642
643/**
644 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
645 * @hba: per adapter instance
646 * @pos: position of the bit to be cleared
647 */
648static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
649{
86b7a91c 650 u32 clear;
651
652 if (hba->quirks & UFSHCD_QUIRK_BROKEN_REQ_LIST_CLR)
653 clear = (1 << pos);
654 else
655 clear = ~(1 << pos);
656
657 ufshcd_writel(hba, clear, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
658}
659
660/**
661 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
662 * @hba: per adapter instance
663 * @pos: position of the bit to be cleared
664 */
665static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
666{
667 u32 clear;
668
669 if (hba->quirks & UFSHCD_QUIRK_BROKEN_REQ_LIST_CLR)
670 clear = (1 << pos);
671 else
672 clear = ~(1 << pos);
673
674 ufshcd_writel(hba, clear, REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 675}
676
a48353f6
YG		 677/**
678 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
679 * @hba: per adapter instance
680 * @tag: position of the bit to be cleared
681 */
682static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
683{
684 __clear_bit(tag, &hba->outstanding_reqs);
685}
686
7a3e97b0
SY		 687/**
688 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
689 * @reg: Register value of host controller status
690 *
691 * Returns integer, 0 on Success and positive value if failed
692 */
693static inline int ufshcd_get_lists_status(u32 reg)
694{
6cf16115 695 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 696}
697
698/**
699 * ufshcd_get_uic_cmd_result - Get the UIC command result
700 * @hba: Pointer to adapter instance
701 *
702 * This function gets the result of UIC command completion
703 * Returns 0 on success, non zero value on error
704 */
705static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
706{
b873a275 707 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 708 MASK_UIC_COMMAND_RESULT;
709}
710
12b4fdb4
SJ		 711/**
712 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
713 * @hba: Pointer to adapter instance
714 *
715 * This function gets UIC command argument3
716 * Returns 0 on success, non zero value on error
717 */
718static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
719{
720 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
721}
722
7a3e97b0 723/**
5a0b0cb9 724 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 725 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 726 */
727static inline int
5a0b0cb9 728ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 729{
5a0b0cb9 730 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 731}
732
733/**
734 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
735 * @ucd_rsp_ptr: pointer to response UPIU
736 *
737 * This function gets the response status and scsi_status from response UPIU
738 * Returns the response result code.
739 */
740static inline int
741ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
742{
743 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
744}
745
1c2623c5
SJ		 746/*
747 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
748 * from response UPIU
749 * @ucd_rsp_ptr: pointer to response UPIU
750 *
751 * Return the data segment length.
752 */
753static inline unsigned int
754ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
755{
756 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
757 MASK_RSP_UPIU_DATA_SEG_LEN;
758}
759
66ec6d59
SRT		 760/**
761 * ufshcd_is_exception_event - Check if the device raised an exception event
762 * @ucd_rsp_ptr: pointer to response UPIU
763 *
764 * The function checks if the device raised an exception event indicated in
765 * the Device Information field of response UPIU.
766 *
767 * Returns true if exception is raised, false otherwise.
768 */
769static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
770{
771 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
772 MASK_RSP_EXCEPTION_EVENT ? true : false;
773}
774
7a3e97b0 775/**
7d568652 776 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 777 * @hba: per adapter instance
7a3e97b0
SY		 778 */
779static inline void
7d568652 780ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 781{
7d568652
SJ		 782 ufshcd_writel(hba, INT_AGGR_ENABLE |
783 INT_AGGR_COUNTER_AND_TIMER_RESET,
784 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
785}
786
787/**
788 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
789 * @hba: per adapter instance
790 * @cnt: Interrupt aggregation counter threshold
791 * @tmout: Interrupt aggregation timeout value
792 */
793static inline void
794ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
795{
796 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
797 INT_AGGR_COUNTER_THLD_VAL(cnt) |
798 INT_AGGR_TIMEOUT_VAL(tmout),
799 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 800}
801
b852190e
YG		 802/**
803 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
804 * @hba: per adapter instance
805 */
806static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
807{
808 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
809}
810
7a3e97b0
SY		 811/**
812 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
813 * When run-stop registers are set to 1, it indicates the
814 * host controller that it can process the requests
815 * @hba: per adapter instance
816 */
817static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
818{
b873a275
SJ		 819 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
820 REG_UTP_TASK_REQ_LIST_RUN_STOP);
821 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
822 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 823}
824
7a3e97b0
SY		 825/**
826 * ufshcd_hba_start - Start controller initialization sequence
827 * @hba: per adapter instance
828 */
829static inline void ufshcd_hba_start(struct ufs_hba *hba)
830{
b873a275 831 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 832}
833
834/**
835 * ufshcd_is_hba_active - Get controller state
836 * @hba: per adapter instance
837 *
c9e6010b 838 * Returns false if controller is active, true otherwise
7a3e97b0 839 */
c9e6010b 840static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 841{
4a8eec2b
TK		 842 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
843 ? false : true;
7a3e97b0
SY		 844}
845
09690d5a
SJ		 846static const char *ufschd_uic_link_state_to_string(
847 enum uic_link_state state)
848{
849 switch (state) {
850 case UIC_LINK_OFF_STATE: return "OFF";
851 case UIC_LINK_ACTIVE_STATE: return "ACTIVE";
852 case UIC_LINK_HIBERN8_STATE: return "HIBERN8";
853 default: return "UNKNOWN";
854 }
855}
856
857static const char *ufschd_ufs_dev_pwr_mode_to_string(
858 enum ufs_dev_pwr_mode state)
859{
860 switch (state) {
861 case UFS_ACTIVE_PWR_MODE: return "ACTIVE";
862 case UFS_SLEEP_PWR_MODE: return "SLEEP";
863 case UFS_POWERDOWN_PWR_MODE: return "POWERDOWN";
864 default: return "UNKNOWN";
865 }
866}
867
37113106
YG		 868u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
869{
870 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
871 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
872 (hba->ufs_version == UFSHCI_VERSION_11))
873 return UFS_UNIPRO_VER_1_41;
874 else
875 return UFS_UNIPRO_VER_1_6;
876}
877EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
878
879static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
880{
881 /*
882 * If both host and device support UniPro ver1.6 or later, PA layer
883 * parameters tuning happens during link startup itself.
884 *
885 * We can manually tune PA layer parameters if either host or device
886 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
887 * logic simple, we will only do manual tuning if local unipro version
888 * doesn't support ver1.6 or later.
889 */
890 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
891 return true;
892 else
893 return false;
894}
895
a3cd5ec5
SJ		 896static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
897{
898 int ret = 0;
899 struct ufs_clk_info *clki;
900 struct list_head *head = &hba->clk_list_head;
901 ktime_t start = ktime_get();
902 bool clk_state_changed = false;
903
566ec9ad 904 if (list_empty(head))
a3cd5ec5
SJ		 905 goto out;
906
907 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
908 if (ret)
909 return ret;
910
911 list_for_each_entry(clki, head, list) {
912 if (!IS_ERR_OR_NULL(clki->clk)) {
913 if (scale_up && clki->max_freq) {
914 if (clki->curr_freq == clki->max_freq)
915 continue;
916
917 clk_state_changed = true;
918 ret = clk_set_rate(clki->clk, clki->max_freq);
919 if (ret) {
920 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
921 __func__, clki->name,
922 clki->max_freq, ret);
923 break;
924 }
925 trace_ufshcd_clk_scaling(dev_name(hba->dev),
926 "scaled up", clki->name,
927 clki->curr_freq,
928 clki->max_freq);
929
930 clki->curr_freq = clki->max_freq;
931
932 } else if (!scale_up && clki->min_freq) {
933 if (clki->curr_freq == clki->min_freq)
934 continue;
935
936 clk_state_changed = true;
937 ret = clk_set_rate(clki->clk, clki->min_freq);
938 if (ret) {
939 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
940 __func__, clki->name,
941 clki->min_freq, ret);
942 break;
943 }
944 trace_ufshcd_clk_scaling(dev_name(hba->dev),
945 "scaled down", clki->name,
946 clki->curr_freq,
947 clki->min_freq);
948 clki->curr_freq = clki->min_freq;
949 }
950 }
951 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
952 clki->name, clk_get_rate(clki->clk));
953 }
954
955 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
956
957out:
958 if (clk_state_changed)
959 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
960 (scale_up ? "up" : "down"),
961 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
962 return ret;
963}
964
965/**
966 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
967 * @hba: per adapter instance
968 * @scale_up: True if scaling up and false if scaling down
969 *
970 * Returns true if scaling is required, false otherwise.
971 */
972static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
973 bool scale_up)
974{
975 struct ufs_clk_info *clki;
976 struct list_head *head = &hba->clk_list_head;
977
566ec9ad 978 if (list_empty(head))
a3cd5ec5
SJ		 979 return false;
980
981 list_for_each_entry(clki, head, list) {
982 if (!IS_ERR_OR_NULL(clki->clk)) {
983 if (scale_up && clki->max_freq) {
984 if (clki->curr_freq == clki->max_freq)
985 continue;
986 return true;
987 } else if (!scale_up && clki->min_freq) {
988 if (clki->curr_freq == clki->min_freq)
989 continue;
990 return true;
991 }
992 }
993 }
994
995 return false;
996}
997
998static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
999 u64 wait_timeout_us)
1000{
1001 unsigned long flags;
1002 int ret = 0;
1003 u32 tm_doorbell;
1004 u32 tr_doorbell;
1005 bool timeout = false, do_last_check = false;
1006 ktime_t start;
1007
1008 ufshcd_hold(hba, false);
1009 spin_lock_irqsave(hba->host->host_lock, flags);
1010 /*
1011 * Wait for all the outstanding tasks/transfer requests.
1012 * Verify by checking the doorbell registers are clear.
1013 */
1014 start = ktime_get();
1015 do {
1016 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1017 ret = -EBUSY;
1018 goto out;
1019 }
1020
1021 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1022 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1023 if (!tm_doorbell && !tr_doorbell) {
1024 timeout = false;
1025 break;
1026 } else if (do_last_check) {
1027 break;
1028 }
1029
1030 spin_unlock_irqrestore(hba->host->host_lock, flags);
1031 schedule();
1032 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1033 wait_timeout_us) {
1034 timeout = true;
1035 /*
1036 * We might have scheduled out for long time so make
1037 * sure to check if doorbells are cleared by this time
1038 * or not.
1039 */
1040 do_last_check = true;
1041 }
1042 spin_lock_irqsave(hba->host->host_lock, flags);
1043 } while (tm_doorbell || tr_doorbell);
1044
1045 if (timeout) {
1046 dev_err(hba->dev,
1047 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1048 __func__, tm_doorbell, tr_doorbell);
1049 ret = -EBUSY;
1050 }
1051out:
1052 spin_unlock_irqrestore(hba->host->host_lock, flags);
1053 ufshcd_release(hba);
1054 return ret;
1055}
1056
1057/**
1058 * ufshcd_scale_gear - scale up/down UFS gear
1059 * @hba: per adapter instance
1060 * @scale_up: True for scaling up gear and false for scaling down
1061 *
1062 * Returns 0 for success,
1063 * Returns -EBUSY if scaling can't happen at this time
1064 * Returns non-zero for any other errors
1065 */
1066static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1067{
1068 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1069 int ret = 0;
1070 struct ufs_pa_layer_attr new_pwr_info;
1071
1072 if (scale_up) {
1073 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1074 sizeof(struct ufs_pa_layer_attr));
1075 } else {
1076 memcpy(&new_pwr_info, &hba->pwr_info,
1077 sizeof(struct ufs_pa_layer_attr));
1078
1079 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1080 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1081 /* save the current power mode */
1082 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1083 &hba->pwr_info,
1084 sizeof(struct ufs_pa_layer_attr));
1085
1086 /* scale down gear */
1087 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1088 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1089 }
1090 }
1091
1092 /* check if the power mode needs to be changed or not? */
1093 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1094
1095 if (ret)
1096 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1097 __func__, ret,
1098 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1099 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1100
1101 return ret;
1102}
1103
1104static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1105{
1106 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1107 int ret = 0;
1108 /*
1109 * make sure that there are no outstanding requests when
1110 * clock scaling is in progress
1111 */
1112 scsi_block_requests(hba->host);
1113 down_write(&hba->clk_scaling_lock);
1114 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1115 ret = -EBUSY;
1116 up_write(&hba->clk_scaling_lock);
1117 scsi_unblock_requests(hba->host);
1118 }
1119
1120 return ret;
1121}
1122
1123static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1124{
1125 up_write(&hba->clk_scaling_lock);
1126 scsi_unblock_requests(hba->host);
1127}
1128
1129/**
1130 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1131 * @hba: per adapter instance
1132 * @scale_up: True for scaling up and false for scalin down
1133 *
1134 * Returns 0 for success,
1135 * Returns -EBUSY if scaling can't happen at this time
1136 * Returns non-zero for any other errors
1137 */
1138static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1139{
1140 int ret = 0;
1141
401f1e44
SJ		 1142 /* let's not get into low power until clock scaling is completed */
1143 ufshcd_hold(hba, false);
1144
a3cd5ec5
SJ		 1145 ret = ufshcd_clock_scaling_prepare(hba);
1146 if (ret)
1147 return ret;
1148
1149 /* scale down the gear before scaling down clocks */
1150 if (!scale_up) {
1151 ret = ufshcd_scale_gear(hba, false);
1152 if (ret)
1153 goto out;
1154 }
1155
1156 ret = ufshcd_scale_clks(hba, scale_up);
1157 if (ret) {
1158 if (!scale_up)
1159 ufshcd_scale_gear(hba, true);
1160 goto out;
1161 }
1162
1163 /* scale up the gear after scaling up clocks */
1164 if (scale_up) {
1165 ret = ufshcd_scale_gear(hba, true);
1166 if (ret) {
1167 ufshcd_scale_clks(hba, false);
1168 goto out;
1169 }
1170 }
1171
1172 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1173
1174out:
1175 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1176 ufshcd_release(hba);
a3cd5ec5
SJ		 1177 return ret;
1178}
1179
401f1e44
SJ		 1180static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1181{
1182 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1183 clk_scaling.suspend_work);
1184 unsigned long irq_flags;
1185
1186 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1187 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1188 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1189 return;
1190 }
1191 hba->clk_scaling.is_suspended = true;
1192 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1193
1194 __ufshcd_suspend_clkscaling(hba);
1195}
1196
1197static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1198{
1199 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1200 clk_scaling.resume_work);
1201 unsigned long irq_flags;
1202
1203 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1204 if (!hba->clk_scaling.is_suspended) {
1205 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1206 return;
1207 }
1208 hba->clk_scaling.is_suspended = false;
1209 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1210
1211 devfreq_resume_device(hba->devfreq);
1212}
1213
a3cd5ec5
SJ		 1214static int ufshcd_devfreq_target(struct device *dev,
1215 unsigned long *freq, u32 flags)
1216{
1217 int ret = 0;
1218 struct ufs_hba *hba = dev_get_drvdata(dev);
1219 ktime_t start;
401f1e44 1220 bool scale_up, sched_clk_scaling_suspend_work = false;
a3cd5ec5
SJ		 1221 unsigned long irq_flags;
1222
1223 if (!ufshcd_is_clkscaling_supported(hba))
1224 return -EINVAL;
1225
1226 if ((*freq > 0) && (*freq < UINT_MAX)) {
1227 dev_err(hba->dev, "%s: invalid freq = %lu\n", __func__, *freq);
1228 return -EINVAL;
1229 }
1230
a3cd5ec5
SJ		 1231 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1232 if (ufshcd_eh_in_progress(hba)) {
1233 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1234 return 0;
1235 }
1236
401f1e44
SJ		 1237 if (!hba->clk_scaling.active_reqs)
1238 sched_clk_scaling_suspend_work = true;
1239
1240 scale_up = (*freq == UINT_MAX) ? true : false;
1241 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1242 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1243 ret = 0;
1244 goto out; /* no state change required */
a3cd5ec5
SJ		 1245 }
1246 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1247
1248 start = ktime_get();
a3cd5ec5
SJ		 1249 ret = ufshcd_devfreq_scale(hba, scale_up);
1250
a3cd5ec5
SJ		 1251 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1252 (scale_up ? "up" : "down"),
1253 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1254
401f1e44
SJ		 1255out:
1256 if (sched_clk_scaling_suspend_work)
1257 queue_work(hba->clk_scaling.workq,
1258 &hba->clk_scaling.suspend_work);
1259
a3cd5ec5
SJ		 1260 return ret;
1261}
1262
1263
1264static int ufshcd_devfreq_get_dev_status(struct device *dev,
1265 struct devfreq_dev_status *stat)
1266{
1267 struct ufs_hba *hba = dev_get_drvdata(dev);
1268 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1269 unsigned long flags;
1270
1271 if (!ufshcd_is_clkscaling_supported(hba))
1272 return -EINVAL;
1273
1274 memset(stat, 0, sizeof(*stat));
1275
1276 spin_lock_irqsave(hba->host->host_lock, flags);
1277 if (!scaling->window_start_t)
1278 goto start_window;
1279
1280 if (scaling->is_busy_started)
1281 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1282 scaling->busy_start_t));
1283
1284 stat->total_time = jiffies_to_usecs((long)jiffies -
1285 (long)scaling->window_start_t);
1286 stat->busy_time = scaling->tot_busy_t;
1287start_window:
1288 scaling->window_start_t = jiffies;
1289 scaling->tot_busy_t = 0;
1290
1291 if (hba->outstanding_reqs) {
1292 scaling->busy_start_t = ktime_get();
1293 scaling->is_busy_started = true;
1294 } else {
1295 scaling->busy_start_t = 0;
1296 scaling->is_busy_started = false;
1297 }
1298 spin_unlock_irqrestore(hba->host->host_lock, flags);
1299 return 0;
1300}
1301
1302static struct devfreq_dev_profile ufs_devfreq_profile = {
1303 .polling_ms = 100,
1304 .target = ufshcd_devfreq_target,
1305 .get_dev_status = ufshcd_devfreq_get_dev_status,
1306};
1307
401f1e44
SJ		 1308static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1309{
1310 unsigned long flags;
1311
1312 devfreq_suspend_device(hba->devfreq);
1313 spin_lock_irqsave(hba->host->host_lock, flags);
1314 hba->clk_scaling.window_start_t = 0;
1315 spin_unlock_irqrestore(hba->host->host_lock, flags);
1316}
a3cd5ec5 1317
a508253d
GB		 1318static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1319{
401f1e44
SJ		 1320 unsigned long flags;
1321 bool suspend = false;
1322
fcb0c4b0
ST		 1323 if (!ufshcd_is_clkscaling_supported(hba))
1324 return;
1325
401f1e44
SJ		 1326 spin_lock_irqsave(hba->host->host_lock, flags);
1327 if (!hba->clk_scaling.is_suspended) {
1328 suspend = true;
1329 hba->clk_scaling.is_suspended = true;
1330 }
1331 spin_unlock_irqrestore(hba->host->host_lock, flags);
1332
1333 if (suspend)
1334 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1335}
1336
1337static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1338{
401f1e44
SJ		 1339 unsigned long flags;
1340 bool resume = false;
1341
1342 if (!ufshcd_is_clkscaling_supported(hba))
1343 return;
1344
1345 spin_lock_irqsave(hba->host->host_lock, flags);
1346 if (hba->clk_scaling.is_suspended) {
1347 resume = true;
1348 hba->clk_scaling.is_suspended = false;
1349 }
1350 spin_unlock_irqrestore(hba->host->host_lock, flags);
1351
1352 if (resume)
1353 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1354}
1355
1356static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1357 struct device_attribute *attr, char *buf)
1358{
1359 struct ufs_hba *hba = dev_get_drvdata(dev);
1360
1361 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1362}
1363
1364static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1365 struct device_attribute *attr, const char *buf, size_t count)
1366{
1367 struct ufs_hba *hba = dev_get_drvdata(dev);
1368 u32 value;
1369 int err;
1370
1371 if (kstrtou32(buf, 0, &value))
1372 return -EINVAL;
1373
1374 value = !!value;
1375 if (value == hba->clk_scaling.is_allowed)
1376 goto out;
1377
1378 pm_runtime_get_sync(hba->dev);
1379 ufshcd_hold(hba, false);
1380
401f1e44
SJ		 1381 cancel_work_sync(&hba->clk_scaling.suspend_work);
1382 cancel_work_sync(&hba->clk_scaling.resume_work);
1383
1384 hba->clk_scaling.is_allowed = value;
1385
fcb0c4b0
ST		 1386 if (value) {
1387 ufshcd_resume_clkscaling(hba);
1388 } else {
1389 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1390 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1391 if (err)
1392 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1393 __func__, err);
1394 }
fcb0c4b0
ST		 1395
1396 ufshcd_release(hba);
1397 pm_runtime_put_sync(hba->dev);
1398out:
1399 return count;
a508253d
GB		 1400}
1401
a3cd5ec5
SJ		 1402static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1403{
1404 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1405 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1406 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1407 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1408 hba->clk_scaling.enable_attr.attr.mode = 0644;
1409 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1410 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1411}
1412
1ab27c9c
ST		 1413static void ufshcd_ungate_work(struct work_struct *work)
1414{
1415 int ret;
1416 unsigned long flags;
1417 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1418 clk_gating.ungate_work);
5801290e 1419 bool gating_allowed = !ufshcd_can_fake_clkgating(hba);
1ab27c9c
ST		 1420
1421 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1422
1423 spin_lock_irqsave(hba->host->host_lock, flags);
5801290e 1424 if (hba->clk_gating.state == CLKS_ON && gating_allowed) {
1ab27c9c
ST		 1425 spin_unlock_irqrestore(hba->host->host_lock, flags);
1426 goto unblock_reqs;
1427 }
1428
1429 spin_unlock_irqrestore(hba->host->host_lock, flags);
5801290e 1430 if (gating_allowed) {
1431 ufshcd_setup_clocks(hba, true);
1432 } else {
66a35665 1433 spin_lock_irqsave(hba->host->host_lock, flags);
5801290e 1434 hba->clk_gating.state = CLKS_ON;
66a35665 1435 spin_unlock_irqrestore(hba->host->host_lock, flags);
5801290e 1436 }
1ab27c9c
ST		 1437
1438 /* Exit from hibern8 */
1439 if (ufshcd_can_hibern8_during_gating(hba)) {
1440 /* Prevent gating in this path */
1441 hba->clk_gating.is_suspended = true;
1442 if (ufshcd_is_link_hibern8(hba)) {
5801290e 1443 ufshcd_set_link_trans_active(hba);
0f7f11ff 1444 ret = ufshcd_link_hibern8_ctrl(hba, false);
5801290e 1445 if (ret) {
1446 ufshcd_set_link_off(hba);
1ab27c9c
ST		 1447 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1448 __func__, ret);
5801290e 1449 } else {
1ab27c9c 1450 ufshcd_set_link_active(hba);
5801290e 1451 }
1ab27c9c
ST		 1452 }
1453 hba->clk_gating.is_suspended = false;
1454 }
1455unblock_reqs:
1456 scsi_unblock_requests(hba->host);
1457}
1458
1459/**
1460 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1461 * Also, exit from hibern8 mode and set the link as active.
1462 * @hba: per adapter instance
1463 * @async: This indicates whether caller should ungate clocks asynchronously.
1464 */
1465int ufshcd_hold(struct ufs_hba *hba, bool async)
1466{
1467 int rc = 0;
1468 unsigned long flags;
1469
1470 if (!ufshcd_is_clkgating_allowed(hba))
1471 goto out;
1ab27c9c
ST		 1472 spin_lock_irqsave(hba->host->host_lock, flags);
1473 hba->clk_gating.active_reqs++;
1474
53c12d0e
YG		 1475 if (ufshcd_eh_in_progress(hba)) {
1476 spin_unlock_irqrestore(hba->host->host_lock, flags);
1477 return 0;
1478 }
1479
856b3483 1480start:
1ab27c9c 1481 switch (hba->clk_gating.state) {
40e137af 1482 case __CLKS_ON:
1483 rc = -EAGAIN;
1484 if (async)
1485 hba->clk_gating.active_reqs--;
1ab27c9c 1486 case CLKS_ON:
f2a785ac
VG		 1487 /*
1488 * Wait for the ungate work to complete if in progress.
1489 * Though the clocks may be in ON state, the link could
1490 * still be in hibner8 state if hibern8 is allowed
1491 * during clock gating.
1492 * Make sure we exit hibern8 state also in addition to
1493 * clocks being ON.
1494 */
1495 if (ufshcd_can_hibern8_during_gating(hba) &&
1496 ufshcd_is_link_hibern8(hba)) {
1497 spin_unlock_irqrestore(hba->host->host_lock, flags);
1498 flush_work(&hba->clk_gating.ungate_work);
1499 spin_lock_irqsave(hba->host->host_lock, flags);
1500 goto start;
1501 }
1ab27c9c
ST		 1502 break;
1503 case REQ_CLKS_OFF:
1504 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1505 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1506 trace_ufshcd_clk_gating(dev_name(hba->dev),
1507 hba->clk_gating.state);
1ab27c9c
ST		 1508 break;
1509 }
1510 /*
9c490d2d 1511 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1512 * currently running. Hence, fall through to cancel gating
1513 * work and to enable clocks.
1514 */
1515 case CLKS_OFF:
1516 scsi_block_requests(hba->host);
1517 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47
SJ		 1518 trace_ufshcd_clk_gating(dev_name(hba->dev),
1519 hba->clk_gating.state);
9087ff6a 1520 queue_work(hba->ufshcd_workq, &hba->clk_gating.ungate_work);
1ab27c9c
ST		 1521 /*
1522 * fall through to check if we should wait for this
1523 * work to be done or not.
1524 */
1525 case REQ_CLKS_ON:
1526 if (async) {
1527 rc = -EAGAIN;
1528 hba->clk_gating.active_reqs--;
1529 break;
1530 }
1531
1532 spin_unlock_irqrestore(hba->host->host_lock, flags);
1533 flush_work(&hba->clk_gating.ungate_work);
1534 /* Make sure state is CLKS_ON before returning */
856b3483 1535 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1536 goto start;
1537 default:
1538 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1539 __func__, hba->clk_gating.state);
1540 break;
1541 }
1542 spin_unlock_irqrestore(hba->host->host_lock, flags);
1543out:
1544 return rc;
1545}
6e3fd44d 1546EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1547
1548static void ufshcd_gate_work(struct work_struct *work)
1549{
1550 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1551 clk_gating.gate_work.work);
5801290e 1552 bool gating_allowed = !ufshcd_can_fake_clkgating(hba);
1ab27c9c
ST		 1553 unsigned long flags;
1554
1555 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1556 /*
1557 * In case you are here to cancel this work the gating state
1558 * would be marked as REQ_CLKS_ON. In this case save time by
1559 * skipping the gating work and exit after changing the clock
1560 * state to CLKS_ON.
1561 */
1562 if (hba->clk_gating.is_suspended ||
1563 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 1564 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1565 trace_ufshcd_clk_gating(dev_name(hba->dev),
1566 hba->clk_gating.state);
1ab27c9c
ST		 1567 goto rel_lock;
1568 }
1569
1570 if (hba->clk_gating.active_reqs
1571 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1572 || hba->lrb_in_use || hba->outstanding_tasks
abebc6eb 1573 || hba->active_uic_cmd || hba->uic_async_done
1574 || scsi_host_in_recovery(hba->host))
1ab27c9c
ST		 1575 goto rel_lock;
1576
1577 spin_unlock_irqrestore(hba->host->host_lock, flags);
1578
1579 /* put the link into hibern8 mode before turning off clocks */
1580 if (ufshcd_can_hibern8_during_gating(hba)) {
5801290e 1581 ufshcd_set_link_trans_hibern8(hba);
0f7f11ff 1582 if (ufshcd_link_hibern8_ctrl(hba, true)) {
66a35665 1583 spin_lock_irqsave(hba->host->host_lock, flags);
1584 hba->clk_gating.state = __CLKS_ON;
1585 spin_unlock_irqrestore(hba->host->host_lock, flags);
1586 hba->clk_gating.is_suspended = true;
1587 ufshcd_reset_and_restore(hba);
40e137af 1588 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c 1589 hba->clk_gating.state = CLKS_ON;
40e137af 1590 spin_unlock_irqrestore(hba->host->host_lock, flags);
66a35665 1591 hba->clk_gating.is_suspended = false;
7ff5ab47
SJ		 1592 trace_ufshcd_clk_gating(dev_name(hba->dev),
1593 hba->clk_gating.state);
1ab27c9c
ST		 1594 goto out;
1595 }
1596 ufshcd_set_link_hibern8(hba);
1597 }
1598
5801290e 1599 if (gating_allowed) {
1600 if (!ufshcd_is_link_active(hba))
1601 ufshcd_setup_clocks(hba, false);
1602 else
1603 /* If link is active, device ref_clk can't be switched off */
1604 __ufshcd_setup_clocks(hba, false, true);
1605 }
1ab27c9c
ST		 1606
1607 /*
1608 * In case you are here to cancel this work the gating state
1609 * would be marked as REQ_CLKS_ON. In this case keep the state
1610 * as REQ_CLKS_ON which would anyway imply that clocks are off
1611 * and a request to turn them on is pending. By doing this way,
1612 * we keep the state machine in tact and this would ultimately
1613 * prevent from doing cancel work multiple times when there are
1614 * new requests arriving before the current cancel work is done.
1615 */
1616 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1617 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1618 hba->clk_gating.state = CLKS_OFF;
7ff5ab47
SJ		 1619 trace_ufshcd_clk_gating(dev_name(hba->dev),
1620 hba->clk_gating.state);
1621 }
1ab27c9c
ST		 1622rel_lock:
1623 spin_unlock_irqrestore(hba->host->host_lock, flags);
1624out:
1625 return;
1626}
1627
1628/* host lock must be held before calling this variant */
1629static void __ufshcd_release(struct ufs_hba *hba)
1630{
1631 if (!ufshcd_is_clkgating_allowed(hba))
1632 return;
1633
1634 hba->clk_gating.active_reqs--;
1635
1636 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1637 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1638 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e 1639 || hba->active_uic_cmd || hba->uic_async_done
abebc6eb 1640 || scsi_host_in_recovery(hba->host)
53c12d0e 1641 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1642 return;
1643
1644 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1645 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
9087ff6a 1646 queue_delayed_work(hba->ufshcd_workq, &hba->clk_gating.gate_work,
1ab27c9c
ST		 1647 msecs_to_jiffies(hba->clk_gating.delay_ms));
1648}
1649
1650void ufshcd_release(struct ufs_hba *hba)
1651{
1652 unsigned long flags;
1653
1654 spin_lock_irqsave(hba->host->host_lock, flags);
1655 __ufshcd_release(hba);
1656 spin_unlock_irqrestore(hba->host->host_lock, flags);
1657}
6e3fd44d 1658EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1659
1660static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1661 struct device_attribute *attr, char *buf)
1662{
1663 struct ufs_hba *hba = dev_get_drvdata(dev);
1664
1665 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1666}
1667
1668static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1669 struct device_attribute *attr, const char *buf, size_t count)
1670{
1671 struct ufs_hba *hba = dev_get_drvdata(dev);
1672 unsigned long flags, value;
1673
1674 if (kstrtoul(buf, 0, &value))
1675 return -EINVAL;
1676
1677 spin_lock_irqsave(hba->host->host_lock, flags);
1678 hba->clk_gating.delay_ms = value;
1679 spin_unlock_irqrestore(hba->host->host_lock, flags);
1680 return count;
1681}
1682
b427411a
ST		 1683static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1684 struct device_attribute *attr, char *buf)
1685{
1686 struct ufs_hba *hba = dev_get_drvdata(dev);
1687
1688 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1689}
1690
1691static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1692 struct device_attribute *attr, const char *buf, size_t count)
1693{
1694 struct ufs_hba *hba = dev_get_drvdata(dev);
1695 unsigned long flags;
1696 u32 value;
1697
1698 if (kstrtou32(buf, 0, &value))
1699 return -EINVAL;
1700
1701 value = !!value;
1702 if (value == hba->clk_gating.is_enabled)
1703 goto out;
1704
1705 if (value) {
1706 ufshcd_release(hba);
1707 } else {
1708 spin_lock_irqsave(hba->host->host_lock, flags);
1709 hba->clk_gating.active_reqs++;
1710 spin_unlock_irqrestore(hba->host->host_lock, flags);
1711 }
1712
1713 hba->clk_gating.is_enabled = value;
1714out:
1715 return count;
1716}
1717
9087ff6a 1718static int ufshcd_init_clk_gating(struct ufs_hba *hba)
1ab27c9c 1719{
9087ff6a 1720 int ret = 0;
1721
1ab27c9c 1722 if (!ufshcd_is_clkgating_allowed(hba))
9087ff6a 1723 goto out;
1724
1725 hba->ufshcd_workq = alloc_workqueue("ufshcd_wq", WQ_HIGHPRI, 0);
1726 if (!hba->ufshcd_workq) {
1727 ret = -ENOMEM;
1728 goto out;
1729 }
1ab27c9c 1730
0f7f11ff 1731 hba->clk_gating.delay_ms = LINK_H8_DELAY;
1ab27c9c
ST		 1732 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1733 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1734
b427411a
ST		 1735 hba->clk_gating.is_enabled = true;
1736
1ab27c9c
ST		 1737 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1738 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1739 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1740 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1741 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1742 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1743 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1744
1745 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1746 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1747 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1748 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1749 hba->clk_gating.enable_attr.attr.mode = 0644;
1750 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1751 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
9087ff6a 1752
1753out:
1754 return ret;
1ab27c9c
ST		 1755}
1756
1757static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1758{
1759 if (!ufshcd_is_clkgating_allowed(hba))
1760 return;
9087ff6a 1761 destroy_workqueue(hba->ufshcd_workq);
1ab27c9c 1762 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1763 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1ab27c9c
ST		 1764}
1765
856b3483
ST		 1766/* Must be called with host lock acquired */
1767static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1768{
401f1e44
SJ		 1769 bool queue_resume_work = false;
1770
fcb0c4b0 1771 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1772 return;
1773
401f1e44
SJ		 1774 if (!hba->clk_scaling.active_reqs++)
1775 queue_resume_work = true;
1776
1777 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1778 return;
1779
1780 if (queue_resume_work)
1781 queue_work(hba->clk_scaling.workq,
1782 &hba->clk_scaling.resume_work);
1783
1784 if (!hba->clk_scaling.window_start_t) {
1785 hba->clk_scaling.window_start_t = jiffies;
1786 hba->clk_scaling.tot_busy_t = 0;
1787 hba->clk_scaling.is_busy_started = false;
1788 }
1789
856b3483
ST		 1790 if (!hba->clk_scaling.is_busy_started) {
1791 hba->clk_scaling.busy_start_t = ktime_get();
1792 hba->clk_scaling.is_busy_started = true;
1793 }
1794}
1795
1796static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1797{
1798 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1799
fcb0c4b0 1800 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1801 return;
1802
1803 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1804 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1805 scaling->busy_start_t));
8b0e1953 1806 scaling->busy_start_t = 0;
856b3483
ST		 1807 scaling->is_busy_started = false;
1808 }
1809}
7a3e97b0
SY		 1810/**
1811 * ufshcd_send_command - Send SCSI or device management commands
1812 * @hba: per adapter instance
1813 * @task_tag: Task tag of the command
1814 */
1815static inline
1816void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1817{
ff8e20c6 1818 hba->lrb[task_tag].issue_time_stamp = ktime_get();
856b3483 1819 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 1820 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1821 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1822 /* Make sure that doorbell is committed immediately */
1823 wmb();
1a07f2d9 1824 ufshcd_add_command_trace(hba, task_tag, "send");
7a3e97b0
SY		 1825}
1826
1827/**
1828 * ufshcd_copy_sense_data - Copy sense data in case of check condition
1829 * @lrb - pointer to local reference block
1830 */
1831static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1832{
1833 int len;
1c2623c5
SJ		 1834 if (lrbp->sense_buffer &&
1835 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1836 int len_to_copy;
1837
5a0b0cb9 1838 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 1839 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1840
7a3e97b0 1841 memcpy(lrbp->sense_buffer,
5a0b0cb9 1842 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1843 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 1844 }
1845}
1846
68078d5c
DR		 1847/**
1848 * ufshcd_copy_query_response() - Copy the Query Response and the data
1849 * descriptor
1850 * @hba: per adapter instance
1851 * @lrb - pointer to local reference block
1852 */
1853static
c6d4a831 1854int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1855{
1856 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1857
68078d5c 1858 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1859
68078d5c
DR		 1860 /* Get the descriptor */
1861 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1862 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1863 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1864 u16 resp_len;
1865 u16 buf_len;
68078d5c
DR		 1866
1867 /* data segment length */
c6d4a831 1868 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1869 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1870 buf_len = be16_to_cpu(
1871 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1872 if (likely(buf_len >= resp_len)) {
1873 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1874 } else {
1875 dev_warn(hba->dev,
1876 "%s: Response size is bigger than buffer",
1877 __func__);
1878 return -EINVAL;
1879 }
68078d5c 1880 }
c6d4a831
DR		 1881
1882 return 0;
68078d5c
DR		 1883}
1884
7a3e97b0
SY		 1885/**
1886 * ufshcd_hba_capabilities - Read controller capabilities
1887 * @hba: per adapter instance
1888 */
1889static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1890{
b873a275 1891 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1892
1893 /* nutrs and nutmrs are 0 based values */
1894 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1895 hba->nutmrs =
1896 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1897}
1898
1899/**
6ccf44fe
SJ		 1900 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1901 * to accept UIC commands
7a3e97b0 1902 * @hba: per adapter instance
6ccf44fe
SJ		 1903 * Return true on success, else false
1904 */
1905static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1906{
1907 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1908 return true;
1909 else
1910 return false;
1911}
1912
53b3d9c3
SJ		 1913/**
1914 * ufshcd_get_upmcrs - Get the power mode change request status
1915 * @hba: Pointer to adapter instance
1916 *
1917 * This function gets the UPMCRS field of HCS register
1918 * Returns value of UPMCRS field
1919 */
1920static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
1921{
1922 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
1923}
1924
6ccf44fe
SJ		 1925/**
1926 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1927 * @hba: per adapter instance
1928 * @uic_cmd: UIC command
1929 *
1930 * Mutex must be held.
7a3e97b0
SY		 1931 */
1932static inline void
6ccf44fe 1933ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1934{
6ccf44fe
SJ		 1935 WARN_ON(hba->active_uic_cmd);
1936
1937 hba->active_uic_cmd = uic_cmd;
1938
7a3e97b0 1939 /* Write Args */
6ccf44fe
SJ		 1940 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
1941 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
1942 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 1943
1944 /* Write UIC Cmd */
6ccf44fe 1945 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 1946 REG_UIC_COMMAND);
7a3e97b0
SY		 1947}
1948
6ccf44fe
SJ		 1949/**
1950 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
1951 * @hba: per adapter instance
1952 * @uic_command: UIC command
1953 *
1954 * Must be called with mutex held.
1955 * Returns 0 only if success.
1956 */
1957static int
1958ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
1959{
1960 int ret;
1961 unsigned long flags;
1962
1963 if (wait_for_completion_timeout(&uic_cmd->done,
1964 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
1965 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
1966 else
1967 ret = -ETIMEDOUT;
1968
1969 spin_lock_irqsave(hba->host->host_lock, flags);
1970 hba->active_uic_cmd = NULL;
1971 spin_unlock_irqrestore(hba->host->host_lock, flags);
1972
1973 return ret;
1974}
1975
1976/**
1977 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
1978 * @hba: per adapter instance
1979 * @uic_cmd: UIC command
d75f7fe4 1980 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 1981 *
1982 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 1983 * with mutex held and host_lock locked.
6ccf44fe
SJ		 1984 * Returns 0 only if success.
1985 */
1986static int
d75f7fe4
YG		 1987__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
1988 bool completion)
6ccf44fe 1989{
6ccf44fe
SJ		 1990 if (!ufshcd_ready_for_uic_cmd(hba)) {
1991 dev_err(hba->dev,
1992 "Controller not ready to accept UIC commands\n");
1993 return -EIO;
1994 }
1995
d75f7fe4
YG		 1996 if (completion)
1997 init_completion(&uic_cmd->done);
6ccf44fe 1998
6ccf44fe 1999 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2000
57d104c1 2001 return 0;
6ccf44fe
SJ		 2002}
2003
2004/**
2005 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2006 * @hba: per adapter instance
2007 * @uic_cmd: UIC command
2008 *
2009 * Returns 0 only if success.
2010 */
2011static int
2012ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2013{
2014 int ret;
57d104c1 2015 unsigned long flags;
6ccf44fe 2016
1ab27c9c 2017 ufshcd_hold(hba, false);
6ccf44fe 2018 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2019 ufshcd_add_delay_before_dme_cmd(hba);
2020
57d104c1 2021 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2022 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2023 spin_unlock_irqrestore(hba->host->host_lock, flags);
2024 if (!ret)
2025 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2026
6ccf44fe
SJ		 2027 mutex_unlock(&hba->uic_cmd_mutex);
2028
1ab27c9c 2029 ufshcd_release(hba);
6ccf44fe
SJ		 2030 return ret;
2031}
2032
7a3e97b0
SY		 2033/**
2034 * ufshcd_map_sg - Map scatter-gather list to prdt
2035 * @lrbp - pointer to local reference block
2036 *
2037 * Returns 0 in case of success, non-zero value in case of failure
2038 */
75b1cc4a 2039static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2040{
2041 struct ufshcd_sg_entry *prd_table;
2042 struct scatterlist *sg;
2043 struct scsi_cmnd *cmd;
2044 int sg_segments;
2045 int i;
2046
2047 cmd = lrbp->cmd;
2048 sg_segments = scsi_dma_map(cmd);
2049 if (sg_segments < 0)
2050 return sg_segments;
2051
2052 if (sg_segments) {
75b1cc4a
KK		 2053 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2054 lrbp->utr_descriptor_ptr->prd_table_length =
2055 cpu_to_le16((u16)(sg_segments *
2056 sizeof(struct ufshcd_sg_entry)));
2057 else
2058 lrbp->utr_descriptor_ptr->prd_table_length =
2059 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2060
2061 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2062
2063 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2064 prd_table[i].size =
2065 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2066 prd_table[i].base_addr =
2067 cpu_to_le32(lower_32_bits(sg->dma_address));
2068 prd_table[i].upper_addr =
2069 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2070 prd_table[i].reserved = 0;
60916a7e 2071 hba->transferred_sector += prd_table[i].size;
2072
7a3e97b0
SY		 2073 }
2074 } else {
2075 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2076 }
2077
2078 return 0;
2079}
2080
2081/**
2fbd009b 2082 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2083 * @hba: per adapter instance
2fbd009b 2084 * @intrs: interrupt bits
7a3e97b0 2085 */
2fbd009b 2086static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2087{
2fbd009b
SJ		 2088 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2089
2090 if (hba->ufs_version == UFSHCI_VERSION_10) {
2091 u32 rw;
2092 rw = set & INTERRUPT_MASK_RW_VER_10;
2093 set = rw | ((set ^ intrs) & intrs);
2094 } else {
2095 set |= intrs;
2096 }
2097
2098 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2099}
2100
2101/**
2102 * ufshcd_disable_intr - disable interrupts
2103 * @hba: per adapter instance
2104 * @intrs: interrupt bits
2105 */
2106static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2107{
2108 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2109
2110 if (hba->ufs_version == UFSHCI_VERSION_10) {
2111 u32 rw;
2112 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2113 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2114 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2115
2116 } else {
2117 set &= ~intrs;
7a3e97b0 2118 }
2fbd009b
SJ		 2119
2120 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2121}
2122
5a0b0cb9
SRT		 2123/**
2124 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2125 * descriptor according to request
2126 * @lrbp: pointer to local reference block
2127 * @upiu_flags: flags required in the header
2128 * @cmd_dir: requests data direction
2129 */
2130static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2131 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2132{
2133 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2134 u32 data_direction;
2135 u32 dword_0;
2136
2137 if (cmd_dir == DMA_FROM_DEVICE) {
2138 data_direction = UTP_DEVICE_TO_HOST;
2139 *upiu_flags = UPIU_CMD_FLAGS_READ;
2140 } else if (cmd_dir == DMA_TO_DEVICE) {
2141 data_direction = UTP_HOST_TO_DEVICE;
2142 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2143 } else {
2144 data_direction = UTP_NO_DATA_TRANSFER;
2145 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2146 }
2147
2148 dword_0 = data_direction | (lrbp->command_type
2149 << UPIU_COMMAND_TYPE_OFFSET);
2150 if (lrbp->intr_cmd)
2151 dword_0 |= UTP_REQ_DESC_INT_CMD;
2152
2153 /* Transfer request descriptor header fields */
2154 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2155 /* dword_1 is reserved, hence it is set to 0 */
2156 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2157 /*
2158 * assigning invalid value for command status. Controller
2159 * updates OCS on command completion, with the command
2160 * status
2161 */
2162 req_desc->header.dword_2 =
2163 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2164 /* dword_3 is reserved, hence it is set to 0 */
2165 req_desc->header.dword_3 = 0;
51047266
YG		 2166
2167 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2168}
2169
2170/**
2171 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2172 * for scsi commands
2173 * @lrbp - local reference block pointer
2174 * @upiu_flags - flags
2175 */
2176static
2177void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2178{
2179 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2180 unsigned short cdb_len;
5a0b0cb9
SRT		 2181
2182 /* command descriptor fields */
2183 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2184 UPIU_TRANSACTION_COMMAND, upiu_flags,
2185 lrbp->lun, lrbp->task_tag);
2186 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2187 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2188
2189 /* Total EHS length and Data segment length will be zero */
2190 ucd_req_ptr->header.dword_2 = 0;
2191
2192 ucd_req_ptr->sc.exp_data_transfer_len =
2193 cpu_to_be32(lrbp->cmd->sdb.length);
2194
52ac95fe
YG		 2195 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
2196 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
2197 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2198
2199 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2200}
2201
68078d5c
DR		 2202/**
2203 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2204 * for query requsts
2205 * @hba: UFS hba
2206 * @lrbp: local reference block pointer
2207 * @upiu_flags: flags
2208 */
2209static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2210 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2211{
2212 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2213 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2214 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2215 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
2216
2217 /* Query request header */
2218 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2219 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2220 lrbp->lun, lrbp->task_tag);
2221 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2222 0, query->request.query_func, 0, 0);
2223
74cf8b55 2224 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_READ_DESC)
2225 len = 0;
2226
6861285c
ZL		 2227 /* Data segment length only need for WRITE_DESC */
2228 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2229 ucd_req_ptr->header.dword_2 =
2230 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2231 else
2232 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2233
2234 /* Copy the Query Request buffer as is */
2235 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2236 QUERY_OSF_SIZE);
68078d5c
DR		 2237
2238 /* Copy the Descriptor */
c6d4a831
DR		 2239 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2240 memcpy(descp, query->descriptor, len);
2241
51047266 2242 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2243}
2244
5a0b0cb9
SRT		 2245static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2246{
2247 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2248
2249 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2250
2251 /* command descriptor fields */
2252 ucd_req_ptr->header.dword_0 =
2253 UPIU_HEADER_DWORD(
2254 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2255 /* clear rest of the fields of basic header */
2256 ucd_req_ptr->header.dword_1 = 0;
2257 ucd_req_ptr->header.dword_2 = 0;
2258
2259 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2260}
2261
7a3e97b0 2262/**
300bb13f
JP		 2263 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2264 * for Device Management Purposes
5a0b0cb9 2265 * @hba - per adapter instance
7a3e97b0
SY		 2266 * @lrb - pointer to local reference block
2267 */
300bb13f 2268static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2269{
7a3e97b0 2270 u32 upiu_flags;
5a0b0cb9 2271 int ret = 0;
7a3e97b0 2272
300bb13f
JP		 2273 if (hba->ufs_version == UFSHCI_VERSION_20)
2274 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2275 else
2276 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2277
2278 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2279 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2280 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2281 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2282 ufshcd_prepare_utp_nop_upiu(lrbp);
2283 else
2284 ret = -EINVAL;
2285
2286 return ret;
2287}
2288
2289/**
2290 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2291 * for SCSI Purposes
2292 * @hba - per adapter instance
2293 * @lrb - pointer to local reference block
2294 */
2295static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2296{
2297 u32 upiu_flags;
2298 int ret = 0;
2299
2300 if (hba->ufs_version == UFSHCI_VERSION_20)
2301 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2302 else
2303 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2304
2305 if (likely(lrbp->cmd)) {
2306 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2307 lrbp->cmd->sc_data_direction);
2308 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2309 } else {
2310 ret = -EINVAL;
2311 }
5a0b0cb9
SRT		 2312
2313 return ret;
7a3e97b0
SY		 2314}
2315
0ce147d4
SJ		 2316/*
2317 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
2318 * @scsi_lun: scsi LUN id
2319 *
2320 * Returns UPIU LUN id
2321 */
2322static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
2323{
2324 if (scsi_is_wlun(scsi_lun))
2325 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
2326 | UFS_UPIU_WLUN_ID;
2327 else
2328 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
2329}
2330
2a8fa600
SJ		 2331/**
2332 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2333 * @scsi_lun: UPIU W-LUN id
2334 *
2335 * Returns SCSI W-LUN id
2336 */
2337static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2338{
2339 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2340}
2341
7a3e97b0
SY		 2342/**
2343 * ufshcd_queuecommand - main entry point for SCSI requests
2344 * @cmd: command from SCSI Midlayer
2345 * @done: call back function
2346 *
2347 * Returns 0 for success, non-zero in case of failure
2348 */
2349static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2350{
2351 struct ufshcd_lrb *lrbp;
2352 struct ufs_hba *hba;
2353 unsigned long flags;
2354 int tag;
2355 int err = 0;
2356
2357 hba = shost_priv(host);
2358
2359 tag = cmd->request->tag;
14497328
YG		 2360 if (!ufshcd_valid_tag(hba, tag)) {
2361 dev_err(hba->dev,
2362 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2363 __func__, tag, cmd, cmd->request);
2364 BUG();
2365 }
7a3e97b0 2366
a3cd5ec5
SJ		 2367 if (!down_read_trylock(&hba->clk_scaling_lock))
2368 return SCSI_MLQUEUE_HOST_BUSY;
2369
3441da7d
SRT		 2370 spin_lock_irqsave(hba->host->host_lock, flags);
2371 switch (hba->ufshcd_state) {
2372 case UFSHCD_STATE_OPERATIONAL:
2373 break;
141f8165 2374 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2375 case UFSHCD_STATE_RESET:
7a3e97b0 2376 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2377 goto out_unlock;
2378 case UFSHCD_STATE_ERROR:
2379 set_host_byte(cmd, DID_ERROR);
2380 cmd->scsi_done(cmd);
2381 goto out_unlock;
2382 default:
2383 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2384 __func__, hba->ufshcd_state);
2385 set_host_byte(cmd, DID_BAD_TARGET);
2386 cmd->scsi_done(cmd);
2387 goto out_unlock;
7a3e97b0 2388 }
53c12d0e
YG		 2389
2390 /* if error handling is in progress, don't issue commands */
2391 if (ufshcd_eh_in_progress(hba)) {
2392 set_host_byte(cmd, DID_ERROR);
2393 cmd->scsi_done(cmd);
2394 goto out_unlock;
2395 }
3441da7d 2396 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2397
7fabb77b
GB		 2398 hba->req_abort_count = 0;
2399
5a0b0cb9
SRT		 2400 /* acquire the tag to make sure device cmds don't use it */
2401 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2402 /*
2403 * Dev manage command in progress, requeue the command.
2404 * Requeuing the command helps in cases where the request *may*
2405 * find different tag instead of waiting for dev manage command
2406 * completion.
2407 */
2408 err = SCSI_MLQUEUE_HOST_BUSY;
2409 goto out;
2410 }
2411
1ab27c9c
ST		 2412 err = ufshcd_hold(hba, true);
2413 if (err) {
2414 err = SCSI_MLQUEUE_HOST_BUSY;
2415 clear_bit_unlock(tag, &hba->lrb_in_use);
2416 goto out;
2417 }
2418 WARN_ON(hba->clk_gating.state != CLKS_ON);
2419
7a3e97b0
SY		 2420 lrbp = &hba->lrb[tag];
2421
5a0b0cb9 2422 WARN_ON(lrbp->cmd);
7a3e97b0 2423 lrbp->cmd = cmd;
dcea0bfb 2424 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 2425 lrbp->sense_buffer = cmd->sense_buffer;
2426 lrbp->task_tag = tag;
0ce147d4 2427 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2428 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2429 lrbp->req_abort_skip = false;
7a3e97b0 2430
300bb13f
JP		 2431 ufshcd_comp_scsi_upiu(hba, lrbp);
2432
75b1cc4a 2433 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2434 if (err) {
2435 lrbp->cmd = NULL;
2436 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 2437 goto out;
5a0b0cb9 2438 }
ad1a1b9c
GB		 2439 /* Make sure descriptors are ready before ringing the doorbell */
2440 wmb();
7a3e97b0
SY		 2441
2442 /* issue command to the controller */
2443 spin_lock_irqsave(hba->host->host_lock, flags);
03229397 2444 if (hba->vops && hba->vops->set_nexus_t_xfer_req)
2445 hba->vops->set_nexus_t_xfer_req(hba, tag, lrbp->cmd);
7a3e97b0 2446 ufshcd_send_command(hba, tag);
3441da7d 2447out_unlock:
7a3e97b0
SY		 2448 spin_unlock_irqrestore(hba->host->host_lock, flags);
2449out:
a3cd5ec5 2450 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2451 return err;
2452}
2453
5a0b0cb9
SRT		 2454static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2455 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2456{
2457 lrbp->cmd = NULL;
2458 lrbp->sense_bufflen = 0;
2459 lrbp->sense_buffer = NULL;
2460 lrbp->task_tag = tag;
2461 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2462 lrbp->intr_cmd = true; /* No interrupt aggregation */
2463 hba->dev_cmd.type = cmd_type;
2464
300bb13f 2465 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2466}
2467
2468static int
2469ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2470{
2471 int err = 0;
2472 unsigned long flags;
2473 u32 mask = 1 << tag;
2474
2475 /* clear outstanding transaction before retry */
2476 spin_lock_irqsave(hba->host->host_lock, flags);
2477 ufshcd_utrl_clear(hba, tag);
2478 spin_unlock_irqrestore(hba->host->host_lock, flags);
2479
2480 /*
2481 * wait for for h/w to clear corresponding bit in door-bell.
2482 * max. wait is 1 sec.
2483 */
2484 err = ufshcd_wait_for_register(hba,
2485 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2486 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2487
2488 return err;
2489}
2490
c6d4a831
DR		 2491static int
2492ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2493{
2494 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2495
2496 /* Get the UPIU response */
2497 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2498 UPIU_RSP_CODE_OFFSET;
2499 return query_res->response;
2500}
2501
5a0b0cb9
SRT		 2502/**
2503 * ufshcd_dev_cmd_completion() - handles device management command responses
2504 * @hba: per adapter instance
2505 * @lrbp: pointer to local reference block
2506 */
2507static int
2508ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2509{
2510 int resp;
2511 int err = 0;
2512
ff8e20c6 2513 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2514 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2515
2516 switch (resp) {
2517 case UPIU_TRANSACTION_NOP_IN:
2518 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2519 err = -EINVAL;
2520 dev_err(hba->dev, "%s: unexpected response %x\n",
2521 __func__, resp);
2522 }
2523 break;
68078d5c 2524 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2525 err = ufshcd_check_query_response(hba, lrbp);
2526 if (!err)
2527 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2528 break;
5a0b0cb9
SRT		 2529 case UPIU_TRANSACTION_REJECT_UPIU:
2530 /* TODO: handle Reject UPIU Response */
2531 err = -EPERM;
2532 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2533 __func__);
2534 break;
2535 default:
2536 err = -EINVAL;
2537 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2538 __func__, resp);
2539 break;
2540 }
2541
2542 return err;
2543}
2544
2545static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2546 struct ufshcd_lrb *lrbp, int max_timeout)
2547{
2548 int err = 0;
2549 unsigned long time_left;
2550 unsigned long flags;
2551
2552 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2553 msecs_to_jiffies(max_timeout));
2554
ad1a1b9c
GB		 2555 /* Make sure descriptors are ready before ringing the doorbell */
2556 wmb();
5a0b0cb9
SRT		 2557 spin_lock_irqsave(hba->host->host_lock, flags);
2558 hba->dev_cmd.complete = NULL;
2559 if (likely(time_left)) {
2560 err = ufshcd_get_tr_ocs(lrbp);
2561 if (!err)
2562 err = ufshcd_dev_cmd_completion(hba, lrbp);
2563 }
2564 spin_unlock_irqrestore(hba->host->host_lock, flags);
2565
2566 if (!time_left) {
2567 err = -ETIMEDOUT;
a48353f6
YG		 2568 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2569 __func__, lrbp->task_tag);
5a0b0cb9 2570 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2571 /* successfully cleared the command, retry if needed */
5a0b0cb9 2572 err = -EAGAIN;
a48353f6
YG		 2573 /*
2574 * in case of an error, after clearing the doorbell,
2575 * we also need to clear the outstanding_request
2576 * field in hba
2577 */
2578 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2579 }
2580
2581 return err;
2582}
2583
2584/**
2585 * ufshcd_get_dev_cmd_tag - Get device management command tag
2586 * @hba: per-adapter instance
2587 * @tag: pointer to variable with available slot value
2588 *
2589 * Get a free slot and lock it until device management command
2590 * completes.
2591 *
2592 * Returns false if free slot is unavailable for locking, else
2593 * return true with tag value in @tag.
2594 */
2595static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2596{
2597 int tag;
2598 bool ret = false;
2599 unsigned long tmp;
2600
2601 if (!tag_out)
2602 goto out;
2603
2604 do {
2605 tmp = ~hba->lrb_in_use;
2606 tag = find_last_bit(&tmp, hba->nutrs);
2607 if (tag >= hba->nutrs)
2608 goto out;
2609 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2610
2611 *tag_out = tag;
2612 ret = true;
2613out:
2614 return ret;
2615}
2616
2617static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2618{
2619 clear_bit_unlock(tag, &hba->lrb_in_use);
2620}
2621
2622/**
2623 * ufshcd_exec_dev_cmd - API for sending device management requests
2624 * @hba - UFS hba
2625 * @cmd_type - specifies the type (NOP, Query...)
2626 * @timeout - time in seconds
2627 *
68078d5c
DR		 2628 * NOTE: Since there is only one available tag for device management commands,
2629 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2630 */
2631static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2632 enum dev_cmd_type cmd_type, int timeout)
2633{
2634 struct ufshcd_lrb *lrbp;
2635 int err;
2636 int tag;
2637 struct completion wait;
2638 unsigned long flags;
2639
0f7f11ff 2640 if (!ufshcd_is_link_active(hba)) {
c7cf4cc2 2641 flush_work(&hba->clk_gating.ungate_work);
2642 if (!ufshcd_is_link_active(hba))
0f7f11ff 2643 return -EPERM;
2644 }
a3cd5ec5
SJ		 2645 down_read(&hba->clk_scaling_lock);
2646
5a0b0cb9
SRT		 2647 /*
2648 * Get free slot, sleep if slots are unavailable.
2649 * Even though we use wait_event() which sleeps indefinitely,
2650 * the maximum wait time is bounded by SCSI request timeout.
2651 */
2652 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2653
2654 init_completion(&wait);
2655 lrbp = &hba->lrb[tag];
2656 WARN_ON(lrbp->cmd);
2657 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2658 if (unlikely(err))
2659 goto out_put_tag;
2660
2661 hba->dev_cmd.complete = &wait;
2662
e3dfdc53
YG		 2663 /* Make sure descriptors are ready before ringing the doorbell */
2664 wmb();
5a0b0cb9 2665 spin_lock_irqsave(hba->host->host_lock, flags);
03229397 2666 if (hba->vops && hba->vops->set_nexus_t_xfer_req)
2667 hba->vops->set_nexus_t_xfer_req(hba, tag, lrbp->cmd);
5a0b0cb9
SRT		 2668 ufshcd_send_command(hba, tag);
2669 spin_unlock_irqrestore(hba->host->host_lock, flags);
2670
2671 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2672
2673out_put_tag:
2674 ufshcd_put_dev_cmd_tag(hba, tag);
2675 wake_up(&hba->dev_cmd.tag_wq);
a3cd5ec5 2676 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2677 return err;
2678}
2679
d44a5f98
DR		 2680/**
2681 * ufshcd_init_query() - init the query response and request parameters
2682 * @hba: per-adapter instance
2683 * @request: address of the request pointer to be initialized
2684 * @response: address of the response pointer to be initialized
2685 * @opcode: operation to perform
2686 * @idn: flag idn to access
2687 * @index: LU number to access
2688 * @selector: query/flag/descriptor further identification
2689 */
2690static inline void ufshcd_init_query(struct ufs_hba *hba,
2691 struct ufs_query_req **request, struct ufs_query_res **response,
2692 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2693{
2694 *request = &hba->dev_cmd.query.request;
2695 *response = &hba->dev_cmd.query.response;
2696 memset(*request, 0, sizeof(struct ufs_query_req));
2697 memset(*response, 0, sizeof(struct ufs_query_res));
2698 (*request)->upiu_req.opcode = opcode;
2699 (*request)->upiu_req.idn = idn;
2700 (*request)->upiu_req.index = index;
2701 (*request)->upiu_req.selector = selector;
2702}
2703
dc3c8d3a
YG		 2704static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2705 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2706{
2707 int ret;
2708 int retries;
2709
2710 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2711 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2712 if (ret)
2713 dev_dbg(hba->dev,
2714 "%s: failed with error %d, retries %d\n",
2715 __func__, ret, retries);
2716 else
2717 break;
2718 }
2719
2720 if (ret)
2721 dev_err(hba->dev,
2722 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2723 __func__, opcode, idn, ret, retries);
2724 return ret;
2725}
2726
68078d5c
DR		 2727/**
2728 * ufshcd_query_flag() - API function for sending flag query requests
2729 * hba: per-adapter instance
2730 * query_opcode: flag query to perform
2731 * idn: flag idn to access
2732 * flag_res: the flag value after the query request completes
2733 *
2734 * Returns 0 for success, non-zero in case of failure
2735 */
dc3c8d3a 2736int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2737 enum flag_idn idn, bool *flag_res)
2738{
d44a5f98
DR		 2739 struct ufs_query_req *request = NULL;
2740 struct ufs_query_res *response = NULL;
2741 int err, index = 0, selector = 0;
e5ad406c 2742 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2743
2744 BUG_ON(!hba);
2745
1ab27c9c 2746 ufshcd_hold(hba, false);
68078d5c 2747 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2748 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2749 selector);
68078d5c
DR		 2750
2751 switch (opcode) {
2752 case UPIU_QUERY_OPCODE_SET_FLAG:
2753 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2754 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2755 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2756 break;
2757 case UPIU_QUERY_OPCODE_READ_FLAG:
2758 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2759 if (!flag_res) {
2760 /* No dummy reads */
2761 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2762 __func__);
2763 err = -EINVAL;
2764 goto out_unlock;
2765 }
2766 break;
2767 default:
2768 dev_err(hba->dev,
2769 "%s: Expected query flag opcode but got = %d\n",
2770 __func__, opcode);
2771 err = -EINVAL;
2772 goto out_unlock;
2773 }
68078d5c 2774
e5ad406c 2775 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2776
2777 if (err) {
2778 dev_err(hba->dev,
2779 "%s: Sending flag query for idn %d failed, err = %d\n",
2780 __func__, idn, err);
2781 goto out_unlock;
2782 }
2783
2784 if (flag_res)
e8c8e82a 2785 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2786 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2787
2788out_unlock:
2789 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2790 ufshcd_release(hba);
68078d5c
DR		 2791 return err;
2792}
2793
66ec6d59
SRT		 2794/**
2795 * ufshcd_query_attr - API function for sending attribute requests
2796 * hba: per-adapter instance
2797 * opcode: attribute opcode
2798 * idn: attribute idn to access
2799 * index: index field
2800 * selector: selector field
2801 * attr_val: the attribute value after the query request completes
2802 *
2803 * Returns 0 for success, non-zero in case of failure
2804*/
bdbe5d2f 2805static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 2806 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2807{
d44a5f98
DR		 2808 struct ufs_query_req *request = NULL;
2809 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2810 int err;
2811
2812 BUG_ON(!hba);
2813
1ab27c9c 2814 ufshcd_hold(hba, false);
66ec6d59
SRT		 2815 if (!attr_val) {
2816 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2817 __func__, opcode);
2818 err = -EINVAL;
2819 goto out;
2820 }
2821
2822 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2823 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2824 selector);
66ec6d59
SRT		 2825
2826 switch (opcode) {
2827 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2828 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2829 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2830 break;
2831 case UPIU_QUERY_OPCODE_READ_ATTR:
2832 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2833 break;
2834 default:
2835 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2836 __func__, opcode);
2837 err = -EINVAL;
2838 goto out_unlock;
2839 }
2840
d44a5f98 2841 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2842
2843 if (err) {
4b761b58
YG		 2844 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2845 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2846 goto out_unlock;
2847 }
2848
e8c8e82a 2849 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2850
2851out_unlock:
2852 mutex_unlock(&hba->dev_cmd.lock);
2853out:
1ab27c9c 2854 ufshcd_release(hba);
66ec6d59
SRT		 2855 return err;
2856}
2857
5e86ae44
YG		 2858/**
2859 * ufshcd_query_attr_retry() - API function for sending query
2860 * attribute with retries
2861 * @hba: per-adapter instance
2862 * @opcode: attribute opcode
2863 * @idn: attribute idn to access
2864 * @index: index field
2865 * @selector: selector field
2866 * @attr_val: the attribute value after the query request
2867 * completes
2868 *
2869 * Returns 0 for success, non-zero in case of failure
2870*/
2871static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2872 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2873 u32 *attr_val)
2874{
2875 int ret = 0;
2876 u32 retries;
2877
2878 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2879 ret = ufshcd_query_attr(hba, opcode, idn, index,
2880 selector, attr_val);
2881 if (ret)
2882 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2883 __func__, ret, retries);
2884 else
2885 break;
2886 }
2887
2888 if (ret)
2889 dev_err(hba->dev,
2890 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2891 __func__, idn, ret, QUERY_REQ_RETRIES);
2892 return ret;
2893}
2894
a70e91b8 2895static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2896 enum query_opcode opcode, enum desc_idn idn, u8 index,
2897 u8 selector, u8 *desc_buf, int *buf_len)
2898{
2899 struct ufs_query_req *request = NULL;
2900 struct ufs_query_res *response = NULL;
2901 int err;
2902
2903 BUG_ON(!hba);
2904
1ab27c9c 2905 ufshcd_hold(hba, false);
d44a5f98
DR		 2906 if (!desc_buf) {
2907 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
2908 __func__, opcode);
2909 err = -EINVAL;
2910 goto out;
2911 }
2912
a4b0e8a4 2913 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 2914 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
2915 __func__, *buf_len);
2916 err = -EINVAL;
2917 goto out;
2918 }
2919
2920 mutex_lock(&hba->dev_cmd.lock);
2921 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2922 selector);
2923 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 2924 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 2925
2926 switch (opcode) {
2927 case UPIU_QUERY_OPCODE_WRITE_DESC:
2928 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2929 break;
2930 case UPIU_QUERY_OPCODE_READ_DESC:
2931 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2932 break;
2933 default:
2934 dev_err(hba->dev,
2935 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
2936 __func__, opcode);
2937 err = -EINVAL;
2938 goto out_unlock;
2939 }
2940
2941 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
2942
2943 if (err) {
4b761b58
YG		 2944 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2945 __func__, opcode, idn, index, err);
d44a5f98
DR		 2946 goto out_unlock;
2947 }
2948
2949 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 2950 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 2951
2952out_unlock:
2953 mutex_unlock(&hba->dev_cmd.lock);
2954out:
1ab27c9c 2955 ufshcd_release(hba);
d44a5f98
DR		 2956 return err;
2957}
2958
a70e91b8
YG		 2959/**
2960 * ufshcd_query_descriptor_retry - API function for sending descriptor
2961 * requests
2962 * hba: per-adapter instance
2963 * opcode: attribute opcode
2964 * idn: attribute idn to access
2965 * index: index field
2966 * selector: selector field
2967 * desc_buf: the buffer that contains the descriptor
2968 * buf_len: length parameter passed to the device
2969 *
2970 * Returns 0 for success, non-zero in case of failure.
2971 * The buf_len parameter will contain, on return, the length parameter
2972 * received on the response.
2973 */
26cf9155
TW		 2974static int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
2975 enum query_opcode opcode,
2976 enum desc_idn idn, u8 index,
2977 u8 selector,
2978 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 2979{
2980 int err;
2981 int retries;
2982
2983 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2984 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
2985 selector, desc_buf, buf_len);
2986 if (!err || err == -EINVAL)
2987 break;
2988 }
2989
2990 return err;
2991}
a70e91b8 2992
a4b0e8a4
PM		 2993/**
2994 * ufshcd_read_desc_length - read the specified descriptor length from header
2995 * @hba: Pointer to adapter instance
2996 * @desc_id: descriptor idn value
2997 * @desc_index: descriptor index
2998 * @desc_length: pointer to variable to read the length of descriptor
2999 *
3000 * Return 0 in case of success, non-zero otherwise
3001 */
3002static int ufshcd_read_desc_length(struct ufs_hba *hba,
3003 enum desc_idn desc_id,
3004 int desc_index,
3005 int *desc_length)
3006{
3007 int ret;
3008 u8 header[QUERY_DESC_HDR_SIZE];
3009 int header_len = QUERY_DESC_HDR_SIZE;
3010
3011 if (desc_id >= QUERY_DESC_IDN_MAX)
3012 return -EINVAL;
3013
3014 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3015 desc_id, desc_index, 0, header,
3016 &header_len);
3017
3018 if (ret) {
3019 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
3020 __func__, desc_id);
3021 return ret;
3022 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3023 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3024 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3025 desc_id);
3026 ret = -EINVAL;
3027 }
3028
3029 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3030 return ret;
3031
3032}
3033
3034/**
3035 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3036 * @hba: Pointer to adapter instance
3037 * @desc_id: descriptor idn value
3038 * @desc_len: mapped desc length (out)
3039 *
3040 * Return 0 in case of success, non-zero otherwise
3041 */
3042int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3043 enum desc_idn desc_id, int *desc_len)
3044{
3045 switch (desc_id) {
3046 case QUERY_DESC_IDN_DEVICE:
3047 *desc_len = hba->desc_size.dev_desc;
3048 break;
3049 case QUERY_DESC_IDN_POWER:
3050 *desc_len = hba->desc_size.pwr_desc;
3051 break;
3052 case QUERY_DESC_IDN_GEOMETRY:
3053 *desc_len = hba->desc_size.geom_desc;
3054 break;
3055 case QUERY_DESC_IDN_CONFIGURATION:
3056 *desc_len = hba->desc_size.conf_desc;
3057 break;
3058 case QUERY_DESC_IDN_UNIT:
3059 *desc_len = hba->desc_size.unit_desc;
3060 break;
3061 case QUERY_DESC_IDN_INTERCONNECT:
3062 *desc_len = hba->desc_size.interc_desc;
3063 break;
3064 case QUERY_DESC_IDN_STRING:
3065 *desc_len = QUERY_DESC_MAX_SIZE;
3066 break;
3067 case QUERY_DESC_IDN_RFU_0:
3068 case QUERY_DESC_IDN_RFU_1:
3069 *desc_len = 0;
3070 break;
3071 default:
3072 *desc_len = 0;
3073 return -EINVAL;
3074 }
3075 return 0;
3076}
3077EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3078
da461cec
SJ		 3079/**
3080 * ufshcd_read_desc_param - read the specified descriptor parameter
3081 * @hba: Pointer to adapter instance
3082 * @desc_id: descriptor idn value
3083 * @desc_index: descriptor index
3084 * @param_offset: offset of the parameter to read
3085 * @param_read_buf: pointer to buffer where parameter would be read
3086 * @param_size: sizeof(param_read_buf)
3087 *
3088 * Return 0 in case of success, non-zero otherwise
3089 */
3090static int ufshcd_read_desc_param(struct ufs_hba *hba,
3091 enum desc_idn desc_id,
3092 int desc_index,
a4b0e8a4 3093 u8 param_offset,
da461cec 3094 u8 *param_read_buf,
a4b0e8a4 3095 u8 param_size)
da461cec
SJ		 3096{
3097 int ret;
3098 u8 *desc_buf;
a4b0e8a4 3099 int buff_len;
da461cec
SJ		 3100 bool is_kmalloc = true;
3101
a4b0e8a4
PM		 3102 /* Safety check */
3103 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3104 return -EINVAL;
3105
a4b0e8a4
PM		 3106 /* Get the max length of descriptor from structure filled up at probe
3107 * time.
3108 */
3109 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3110
a4b0e8a4
PM		 3111 /* Sanity checks */
3112 if (ret || !buff_len) {
3113 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3114 __func__);
3115 return ret;
3116 }
3117
3118 /* Check whether we need temp memory */
3119 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3120 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3121 if (!desc_buf)
3122 return -ENOMEM;
a4b0e8a4
PM		 3123 } else {
3124 desc_buf = param_read_buf;
3125 is_kmalloc = false;
da461cec
SJ		 3126 }
3127
a4b0e8a4 3128 /* Request for full descriptor */
a70e91b8 3129 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3130 desc_id, desc_index, 0,
3131 desc_buf, &buff_len);
da461cec 3132
bde44bb6
SJ		 3133 if (ret) {
3134 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3135 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3136 goto out;
3137 }
3138
bde44bb6
SJ		 3139 /* Sanity check */
3140 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3141 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3142 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3143 ret = -EINVAL;
3144 goto out;
3145 }
3146
8d65d1bb 3147 /*
3148 * While reading variable size descriptors (like string descriptor),
3149 * some UFS devices may report the "LENGTH" (field in "Transaction
3150 * Specific fields" of Query Response UPIU) same as what was requested
3151 * in Query Request UPIU instead of reporting the actual size of the
3152 * variable size descriptor.
3153 * Although it's safe to ignore the "LENGTH" field for variable size
3154 * descriptors as we can always derive the length of the descriptor from
3155 * the descriptor header fields. Hence this change impose the length
3156 * match check only for fixed size descriptors (for which we always
3157 * request the correct size as part of Query Request UPIU).
3158 */
3159 if ((desc_id != QUERY_DESC_IDN_STRING) &&
3160 (buff_len != desc_buf[QUERY_DESC_LENGTH_OFFSET])) {
3161 dev_err(hba->dev, "%s: desc_buf length mismatch: buff_len %d, buff_len(desc_header) %d",
3162 __func__, buff_len, desc_buf[QUERY_DESC_LENGTH_OFFSET]);
3163 ret = -EINVAL;
3164 goto out;
3165 }
a4b0e8a4
PM		 3166 /* Check wherher we will not copy more data, than available */
3167 if (is_kmalloc && param_size > buff_len)
3168 param_size = buff_len;
bde44bb6 3169
da461cec
SJ		 3170 if (is_kmalloc)
3171 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3172out:
3173 if (is_kmalloc)
3174 kfree(desc_buf);
3175 return ret;
3176}
3177
3178static inline int ufshcd_read_desc(struct ufs_hba *hba,
3179 enum desc_idn desc_id,
3180 int desc_index,
3181 u8 *buf,
3182 u32 size)
3183{
3184 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3185}
3186
3187static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3188 u8 *buf,
3189 u32 size)
3190{
dbd34a61 3191 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
da461cec
SJ		 3192}
3193
8209b6d5 3194static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG		 3195{
3196 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3197}
b573d484
YG		 3198
3199/**
3200 * ufshcd_read_string_desc - read string descriptor
3201 * @hba: pointer to adapter instance
3202 * @desc_index: descriptor index
3203 * @buf: pointer to buffer where descriptor would be read
3204 * @size: size of buf
3205 * @ascii: if true convert from unicode to ascii characters
3206 *
3207 * Return 0 in case of success, non-zero otherwise
3208 */
8209b6d5
TW		 3209#define ASCII_STD true
3210static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3211 u8 *buf, u32 size, bool ascii)
b573d484
YG		 3212{
3213 int err = 0;
3214
3215 err = ufshcd_read_desc(hba,
3216 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3217
3218 if (err) {
3219 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3220 __func__, QUERY_REQ_RETRIES, err);
3221 goto out;
3222 }
3223
3224 if (ascii) {
3225 int desc_len;
3226 int ascii_len;
3227 int i;
3228 char *buff_ascii;
3229
3230 desc_len = buf[0];
3231 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3232 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3233 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3234 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3235 __func__);
3236 err = -ENOMEM;
3237 goto out;
3238 }
3239
3240 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3241 if (!buff_ascii) {
3242 err = -ENOMEM;
fcbefc3b 3243 goto out;
b573d484
YG		 3244 }
3245
3246 /*
3247 * the descriptor contains string in UTF16 format
3248 * we need to convert to utf-8 so it can be displayed
3249 */
3250 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3251 desc_len - QUERY_DESC_HDR_SIZE,
3252 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3253
3254 /* replace non-printable or non-ASCII characters with spaces */
3255 for (i = 0; i < ascii_len; i++)
3256 ufshcd_remove_non_printable(&buff_ascii[i]);
3257
3258 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3259 size - QUERY_DESC_HDR_SIZE);
3260 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3261 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 3262 kfree(buff_ascii);
3263 }
3264out:
3265 return err;
3266}
b573d484 3267
da461cec
SJ		 3268/**
3269 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3270 * @hba: Pointer to adapter instance
3271 * @lun: lun id
3272 * @param_offset: offset of the parameter to read
3273 * @param_read_buf: pointer to buffer where parameter would be read
3274 * @param_size: sizeof(param_read_buf)
3275 *
3276 * Return 0 in case of success, non-zero otherwise
3277 */
3278static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3279 int lun,
3280 enum unit_desc_param param_offset,
3281 u8 *param_read_buf,
3282 u32 param_size)
3283{
3284 /*
3285 * Unit descriptors are only available for general purpose LUs (LUN id
3286 * from 0 to 7) and RPMB Well known LU.
3287 */
0ce147d4 3288 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 3289 return -EOPNOTSUPP;
3290
3291 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3292 param_offset, param_read_buf, param_size);
3293}
3294
8d65d1bb 3295int ufshcd_read_health_desc(struct ufs_hba *hba, u8 *buf, u32 size)
3296{
3297 int err = 0;
3298
3299 err = ufshcd_read_desc(hba,
3300 QUERY_DESC_IDN_HEALTH, 0, buf, size);
3301
3302 if (err)
3303 dev_err(hba->dev, "%s: reading Device Health Desc failed. err = %d\n",
3304 __func__, err);
3305
3306 return err;
3307}
3308
7a3e97b0
SY		 3309/**
3310 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3311 * @hba: per adapter instance
3312 *
3313 * 1. Allocate DMA memory for Command Descriptor array
3314 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3315 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3316 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3317 * (UTMRDL)
3318 * 4. Allocate memory for local reference block(lrb).
3319 *
3320 * Returns 0 for success, non-zero in case of failure
3321 */
3322static int ufshcd_memory_alloc(struct ufs_hba *hba)
3323{
3324 size_t utmrdl_size, utrdl_size, ucdl_size;
3325
3326 /* Allocate memory for UTP command descriptors */
3327 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3328 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3329 ucdl_size,
3330 &hba->ucdl_dma_addr,
3331 GFP_KERNEL);
7a3e97b0
SY		 3332
3333 /*
3334 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3335 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3336 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3337 * be aligned to 128 bytes as well
3338 */
3339 if (!hba->ucdl_base_addr ||
3340 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3341 dev_err(hba->dev,
7a3e97b0
SY		 3342 "Command Descriptor Memory allocation failed\n");
3343 goto out;
3344 }
3345
3346 /*
3347 * Allocate memory for UTP Transfer descriptors
3348 * UFSHCI requires 1024 byte alignment of UTRD
3349 */
3350 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3351 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3352 utrdl_size,
3353 &hba->utrdl_dma_addr,
3354 GFP_KERNEL);
7a3e97b0
SY		 3355 if (!hba->utrdl_base_addr ||
3356 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3357 dev_err(hba->dev,
7a3e97b0
SY		 3358 "Transfer Descriptor Memory allocation failed\n");
3359 goto out;
3360 }
3361
3362 /*
3363 * Allocate memory for UTP Task Management descriptors
3364 * UFSHCI requires 1024 byte alignment of UTMRD
3365 */
3366 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3367 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3368 utmrdl_size,
3369 &hba->utmrdl_dma_addr,
3370 GFP_KERNEL);
7a3e97b0
SY		 3371 if (!hba->utmrdl_base_addr ||
3372 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3373 dev_err(hba->dev,
7a3e97b0
SY		 3374 "Task Management Descriptor Memory allocation failed\n");
3375 goto out;
3376 }
3377
3378 /* Allocate memory for local reference block */
2953f850
SJ		 3379 hba->lrb = devm_kzalloc(hba->dev,
3380 hba->nutrs * sizeof(struct ufshcd_lrb),
3381 GFP_KERNEL);
7a3e97b0 3382 if (!hba->lrb) {
3b1d0580 3383 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3384 goto out;
3385 }
3386 return 0;
3387out:
7a3e97b0
SY		 3388 return -ENOMEM;
3389}
3390
3391/**
3392 * ufshcd_host_memory_configure - configure local reference block with
3393 * memory offsets
3394 * @hba: per adapter instance
3395 *
3396 * Configure Host memory space
3397 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3398 * address.
3399 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3400 * and PRDT offset.
3401 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3402 * into local reference block.
3403 */
3404static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3405{
3406 struct utp_transfer_cmd_desc *cmd_descp;
3407 struct utp_transfer_req_desc *utrdlp;
3408 dma_addr_t cmd_desc_dma_addr;
3409 dma_addr_t cmd_desc_element_addr;
3410 u16 response_offset;
3411 u16 prdt_offset;
3412 int cmd_desc_size;
3413 int i;
3414
3415 utrdlp = hba->utrdl_base_addr;
3416 cmd_descp = hba->ucdl_base_addr;
3417
3418 response_offset =
3419 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3420 prdt_offset =
3421 offsetof(struct utp_transfer_cmd_desc, prd_table);
3422
3423 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3424 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3425
3426 for (i = 0; i < hba->nutrs; i++) {
3427 /* Configure UTRD with command descriptor base address */
3428 cmd_desc_element_addr =
3429 (cmd_desc_dma_addr + (cmd_desc_size * i));
3430 utrdlp[i].command_desc_base_addr_lo =
3431 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3432 utrdlp[i].command_desc_base_addr_hi =
3433 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3434
3435 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 3436 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3437 utrdlp[i].response_upiu_offset =
3438 cpu_to_le16(response_offset);
3439 utrdlp[i].prd_table_offset =
3440 cpu_to_le16(prdt_offset);
3441 utrdlp[i].response_upiu_length =
3442 cpu_to_le16(ALIGNED_UPIU_SIZE);
3443 } else {
3444 utrdlp[i].response_upiu_offset =
7a3e97b0 3445 cpu_to_le16((response_offset >> 2));
75b1cc4a 3446 utrdlp[i].prd_table_offset =
7a3e97b0 3447 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3448 utrdlp[i].response_upiu_length =
3ca316c5 3449 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3450 }
7a3e97b0
SY		 3451
3452 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR		 3453 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3454 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT		 3455 hba->lrb[i].ucd_req_ptr =
3456 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3457 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY		 3458 hba->lrb[i].ucd_rsp_ptr =
3459 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR		 3460 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3461 response_offset;
7a3e97b0
SY		 3462 hba->lrb[i].ucd_prdt_ptr =
3463 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR		 3464 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3465 prdt_offset;
7a3e97b0
SY		 3466 }
3467}
3468
3469/**
3470 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3471 * @hba: per adapter instance
3472 *
3473 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3474 * in order to initialize the Unipro link startup procedure.
3475 * Once the Unipro links are up, the device connected to the controller
3476 * is detected.
3477 *
3478 * Returns 0 on success, non-zero value on failure
3479 */
3480static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3481{
6ccf44fe
SJ		 3482 struct uic_command uic_cmd = {0};
3483 int ret;
7a3e97b0 3484
6ccf44fe 3485 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3486
6ccf44fe
SJ		 3487 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3488 if (ret)
ff8e20c6 3489 dev_dbg(hba->dev,
6ccf44fe
SJ		 3490 "dme-link-startup: error code %d\n", ret);
3491 return ret;
7a3e97b0
SY		 3492}
3493
cad2e03d
YG		 3494static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3495{
3496 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3497 unsigned long min_sleep_time_us;
3498
3499 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3500 return;
3501
3502 /*
3503 * last_dme_cmd_tstamp will be 0 only for 1st call to
3504 * this function
3505 */
3506 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3507 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3508 } else {
3509 unsigned long delta =
3510 (unsigned long) ktime_to_us(
3511 ktime_sub(ktime_get(),
3512 hba->last_dme_cmd_tstamp));
3513
3514 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3515 min_sleep_time_us =
3516 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3517 else
3518 return; /* no more delay required */
3519 }
3520
3521 /* allow sleep for extra 50us if needed */
3522 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3523}
3524
623b5fe3 3525static int ufshcd_dme_reset(struct ufs_hba *hba)
3526{
3527 struct uic_command uic_cmd = {0};
3528 int ret;
3529
3530 uic_cmd.command = UIC_CMD_DME_RESET;
3531 uic_cmd.argument1 = 0x1;
3532
3533 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3534 if (ret)
3535 dev_err(hba->dev,
3536 "dme-reset: error code %d\n", ret);
3537
3538 return ret;
3539}
3540
3541static int ufshcd_dme_enable(struct ufs_hba *hba)
3542{
3543 struct uic_command uic_cmd = {0};
3544 int ret;
3545
3546 uic_cmd.command = UIC_CMD_DME_ENABLE;
3547
3548 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3549 if (ret)
3550 dev_err(hba->dev,
3551 "dme-enable: error code %d\n", ret);
3552
3553 return ret;
3554}
3555
12b4fdb4
SJ		 3556/**
3557 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3558 * @hba: per adapter instance
3559 * @attr_sel: uic command argument1
3560 * @attr_set: attribute set type as uic command argument2
3561 * @mib_val: setting value as uic command argument3
3562 * @peer: indicate whether peer or local
3563 *
3564 * Returns 0 on success, non-zero value on failure
3565 */
3566int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3567 u8 attr_set, u32 mib_val, u8 peer)
3568{
3569 struct uic_command uic_cmd = {0};
3570 static const char *const action[] = {
3571 "dme-set",
3572 "dme-peer-set"
3573 };
3574 const char *set = action[!!peer];
3575 int ret;
64238fbd 3576 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3577
3578 uic_cmd.command = peer ?
3579 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3580 uic_cmd.argument1 = attr_sel;
3581 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3582 uic_cmd.argument3 = mib_val;
3583
64238fbd
YG		 3584 do {
3585 /* for peer attributes we retry upon failure */
3586 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3587 if (ret)
3588 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3589 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3590 } while (ret && peer && --retries);
3591
f37e9f8c 3592 if (ret)
64238fbd 3593 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3594 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3595 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3596
3597 return ret;
3598}
3599EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3600
3601/**
3602 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3603 * @hba: per adapter instance
3604 * @attr_sel: uic command argument1
3605 * @mib_val: the value of the attribute as returned by the UIC command
3606 * @peer: indicate whether peer or local
3607 *
3608 * Returns 0 on success, non-zero value on failure
3609 */
3610int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3611 u32 *mib_val, u8 peer)
3612{
3613 struct uic_command uic_cmd = {0};
3614 static const char *const action[] = {
3615 "dme-get",
3616 "dme-peer-get"
3617 };
3618 const char *get = action[!!peer];
3619 int ret;
64238fbd 3620 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3621 struct ufs_pa_layer_attr orig_pwr_info;
3622 struct ufs_pa_layer_attr temp_pwr_info;
3623 bool pwr_mode_change = false;
3624
3625 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3626 orig_pwr_info = hba->pwr_info;
3627 temp_pwr_info = orig_pwr_info;
3628
3629 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3630 orig_pwr_info.pwr_rx == FAST_MODE) {
3631 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3632 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3633 pwr_mode_change = true;
3634 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3635 orig_pwr_info.pwr_rx == SLOW_MODE) {
3636 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3637 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3638 pwr_mode_change = true;
3639 }
3640 if (pwr_mode_change) {
3641 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3642 if (ret)
3643 goto out;
3644 }
3645 }
12b4fdb4
SJ		 3646
3647 uic_cmd.command = peer ?
3648 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3649 uic_cmd.argument1 = attr_sel;
3650
64238fbd
YG		 3651 do {
3652 /* for peer attributes we retry upon failure */
3653 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3654 if (ret)
3655 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3656 get, UIC_GET_ATTR_ID(attr_sel), ret);
3657 } while (ret && peer && --retries);
3658
f37e9f8c 3659 if (ret)
64238fbd 3660 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3661 get, UIC_GET_ATTR_ID(attr_sel),
3662 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3663
64238fbd 3664 if (mib_val && !ret)
12b4fdb4 3665 *mib_val = uic_cmd.argument3;
874237f7
YG		 3666
3667 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3668 && pwr_mode_change)
3669 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3670out:
3671 return ret;
3672}
3673EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3674
53b3d9c3 3675/**
57d104c1
SJ		 3676 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3677 * state) and waits for it to take effect.
3678 *
53b3d9c3 3679 * @hba: per adapter instance
57d104c1
SJ		 3680 * @cmd: UIC command to execute
3681 *
3682 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3683 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3684 * and device UniPro link and hence it's final completion would be indicated by
3685 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3686 * addition to normal UIC command completion Status (UCCS). This function only
3687 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3688 *
3689 * Returns 0 on success, non-zero value on failure
3690 */
57d104c1 3691static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3692{
57d104c1 3693 struct completion uic_async_done;
53b3d9c3
SJ		 3694 unsigned long flags;
3695 u8 status;
3696 int ret;
d75f7fe4 3697 bool reenable_intr = false;
53b3d9c3 3698
53b3d9c3 3699 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3700 init_completion(&uic_async_done);
cad2e03d 3701 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3702
3703 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3704 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3705 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3706 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3707 /*
3708 * Make sure UIC command completion interrupt is disabled before
3709 * issuing UIC command.
3710 */
3711 wmb();
3712 reenable_intr = true;
57d104c1 3713 }
d75f7fe4
YG		 3714 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3715 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3716 if (ret) {
3717 dev_err(hba->dev,
3718 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3719 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3720 goto out;
3721 }
3722
57d104c1 3723 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3724 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3725 dev_err(hba->dev,
57d104c1
SJ		 3726 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3727 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3728 ret = -ETIMEDOUT;
3729 goto out;
3730 }
3731
3732 status = ufshcd_get_upmcrs(hba);
3733 if (status != PWR_LOCAL) {
3734 dev_err(hba->dev,
73615428 3735 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 3736 cmd->command, status);
53b3d9c3
SJ		 3737 ret = (status != PWR_OK) ? status : -1;
3738 }
3739out:
aee9809c 3740 /* Dump debugging information to system memory */
7942f7b5 3741 if (ret) {
aee9809c 3742 ufshcd_vops_dbg_register_dump(hba);
7942f7b5
VG		 3743 ufshcd_print_host_state(hba);
3744 ufshcd_print_pwr_info(hba);
3745 ufshcd_print_host_regs(hba);
3746 }
3747
53b3d9c3 3748 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3749 hba->active_uic_cmd = NULL;
57d104c1 3750 hba->uic_async_done = NULL;
d75f7fe4
YG		 3751 if (reenable_intr)
3752 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3753 spin_unlock_irqrestore(hba->host->host_lock, flags);
3754 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3755
53b3d9c3
SJ		 3756 return ret;
3757}
3758
57d104c1
SJ		 3759/**
3760 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3761 * using DME_SET primitives.
3762 * @hba: per adapter instance
3763 * @mode: powr mode value
3764 *
3765 * Returns 0 on success, non-zero value on failure
3766 */
3767static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3768{
3769 struct uic_command uic_cmd = {0};
1ab27c9c 3770 int ret;
57d104c1 3771
c3a2f9ee
YG		 3772 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3773 ret = ufshcd_dme_set(hba,
3774 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3775 if (ret) {
3776 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3777 __func__, ret);
3778 goto out;
3779 }
3780 }
3781
57d104c1
SJ		 3782 uic_cmd.command = UIC_CMD_DME_SET;
3783 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3784 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3785 ufshcd_hold(hba, false);
3786 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3787 ufshcd_release(hba);
57d104c1 3788
c3a2f9ee 3789out:
1ab27c9c 3790 return ret;
57d104c1
SJ		 3791}
3792
53c12d0e
YG		 3793static int ufshcd_link_recovery(struct ufs_hba *hba)
3794{
3795 int ret;
3796 unsigned long flags;
3797
3798 spin_lock_irqsave(hba->host->host_lock, flags);
3799 hba->ufshcd_state = UFSHCD_STATE_RESET;
3800 ufshcd_set_eh_in_progress(hba);
3801 spin_unlock_irqrestore(hba->host->host_lock, flags);
3802
3803 ret = ufshcd_host_reset_and_restore(hba);
3804
3805 spin_lock_irqsave(hba->host->host_lock, flags);
3806 if (ret)
3807 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3808 ufshcd_clear_eh_in_progress(hba);
3809 spin_unlock_irqrestore(hba->host->host_lock, flags);
3810
3811 if (ret)
3812 dev_err(hba->dev, "%s: link recovery failed, err %d",
3813 __func__, ret);
3814
3815 return ret;
3816}
3817
87d0b4a6 3818static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3819{
87d0b4a6 3820 int ret;
57d104c1 3821 struct uic_command uic_cmd = {0};
911a0771 3822 ktime_t start = ktime_get();
57d104c1 3823
ee32c909
KK		 3824 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3825
57d104c1 3826 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3827 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3828 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3829 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3830
53c12d0e 3831 if (ret) {
87d0b4a6
YG		 3832 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3833 __func__, ret);
3834
53c12d0e
YG		 3835 /*
3836 * If link recovery fails then return error so that caller
3837 * don't retry the hibern8 enter again.
3838 */
3839 if (ufshcd_link_recovery(hba))
3840 ret = -ENOLINK;
ee32c909
KK		 3841 } else
3842 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3843 POST_CHANGE);
53c12d0e 3844
87d0b4a6
YG		 3845 return ret;
3846}
3847
3848static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3849{
3850 int ret = 0, retries;
57d104c1 3851
87d0b4a6
YG		 3852 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3853 ret = __ufshcd_uic_hibern8_enter(hba);
3854 if (!ret || ret == -ENOLINK)
3855 goto out;
3856 }
3857out:
3858 return ret;
57d104c1
SJ		 3859}
3860
3861static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3862{
3863 struct uic_command uic_cmd = {0};
3864 int ret;
911a0771 3865 ktime_t start = ktime_get();
57d104c1 3866
ee32c909
KK		 3867 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3868
57d104c1
SJ		 3869 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3870 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3871 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3872 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3873
57d104c1 3874 if (ret) {
53c12d0e
YG		 3875 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3876 __func__, ret);
3877 ret = ufshcd_link_recovery(hba);
ff8e20c6 3878 } else {
ee32c909
KK		 3879 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3880 POST_CHANGE);
ff8e20c6
DR		 3881 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3882 hba->ufs_stats.hibern8_exit_cnt++;
3883 }
57d104c1
SJ		 3884
3885 return ret;
3886}
3887
5064636c
YG		 3888 /**
3889 * ufshcd_init_pwr_info - setting the POR (power on reset)
3890 * values in hba power info
3891 * @hba: per-adapter instance
3892 */
3893static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3894{
3895 hba->pwr_info.gear_rx = UFS_PWM_G1;
3896 hba->pwr_info.gear_tx = UFS_PWM_G1;
3897 hba->pwr_info.lane_rx = 1;
3898 hba->pwr_info.lane_tx = 1;
3899 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3900 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3901 hba->pwr_info.hs_rate = 0;
3902}
3903
0f7f11ff 3904static int ufshcd_link_hibern8_ctrl(struct ufs_hba *hba, bool en)
3905{
3906 int ret;
3907
3908 if (hba->vops && hba->vops->hibern8_notify)
3909 hba->vops->hibern8_notify(hba, en, PRE_CHANGE);
3910
3911 if (en)
3912 ret = ufshcd_uic_hibern8_enter(hba);
3913 else
3914 ret = ufshcd_uic_hibern8_exit(hba);
57579a4a 3915
3916 if (ret || (hba->saved_err & INT_FATAL_ERRORS) ||
3917 ((hba->saved_err & UIC_ERROR) &&
3918 ((hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
3919 (hba->saved_uic_err & UFSHCD_UIC_DL_ERROR)))) {
3920
3921 if (!ret)
3922 ret = hba->saved_err;
0f7f11ff 3923 goto out;
3924 }
3925 if (hba->vops && hba->vops->hibern8_notify)
3926 hba->vops->hibern8_notify(hba, en, POST_CHANGE);
3927out:
a60d7ef4 3928 hba->tcx_replay_timer_expired_cnt = 0;
3929 hba->fcx_protection_timer_expired_cnt = 0;
3930
0f7f11ff 3931 return ret;
3932}
3933
d3e89bac 3934/**
7eb584db
DR		 3935 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
3936 * @hba: per-adapter instance
d3e89bac 3937 */
7eb584db 3938static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 3939{
7eb584db
DR		 3940 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
3941
3942 if (hba->max_pwr_info.is_valid)
3943 return 0;
3944
2349b533
SJ		 3945 pwr_info->pwr_tx = FAST_MODE;
3946 pwr_info->pwr_rx = FAST_MODE;
7eb584db 3947 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 3948
3949 /* Get the connected lane count */
7eb584db
DR		 3950 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
3951 &pwr_info->lane_rx);
3952 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
3953 &pwr_info->lane_tx);
3954
3955 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
3956 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
3957 __func__,
3958 pwr_info->lane_rx,
3959 pwr_info->lane_tx);
3960 return -EINVAL;
3961 }
d3e89bac
SJ		 3962
3963 /*
3964 * First, get the maximum gears of HS speed.
3965 * If a zero value, it means there is no HSGEAR capability.
3966 * Then, get the maximum gears of PWM speed.
3967 */
7eb584db
DR		 3968 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
3969 if (!pwr_info->gear_rx) {
3970 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
3971 &pwr_info->gear_rx);
3972 if (!pwr_info->gear_rx) {
3973 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
3974 __func__, pwr_info->gear_rx);
3975 return -EINVAL;
3976 }
2349b533 3977 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 3978 }
3979
7eb584db
DR		 3980 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
3981 &pwr_info->gear_tx);
3982 if (!pwr_info->gear_tx) {
d3e89bac 3983 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 3984 &pwr_info->gear_tx);
3985 if (!pwr_info->gear_tx) {
3986 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
3987 __func__, pwr_info->gear_tx);
3988 return -EINVAL;
3989 }
2349b533 3990 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 3991 }
3992
3993 hba->max_pwr_info.is_valid = true;
3994 return 0;
3995}
3996
3997static int ufshcd_change_power_mode(struct ufs_hba *hba,
3998 struct ufs_pa_layer_attr *pwr_mode)
3999{
4000 int ret;
4001
4002 /* if already configured to the requested pwr_mode */
4003 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4004 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4005 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4006 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4007 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4008 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4009 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4010 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4011 return 0;
d3e89bac
SJ		 4012 }
4013
4014 /*
4015 * Configure attributes for power mode change with below.
4016 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4017 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4018 * - PA_HSSERIES
4019 */
7eb584db
DR		 4020 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4021 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4022 pwr_mode->lane_rx);
4023 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4024 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4025 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4026 else
4027 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4028
7eb584db
DR		 4029 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4030 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4031 pwr_mode->lane_tx);
4032 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4033 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4034 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4035 else
4036 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4037
7eb584db
DR		 4038 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4039 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4040 pwr_mode->pwr_rx == FAST_MODE ||
4041 pwr_mode->pwr_tx == FAST_MODE)
4042 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4043 pwr_mode->hs_rate);
d3e89bac 4044
7eb584db
DR		 4045 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4046 | pwr_mode->pwr_tx);
4047
4048 if (ret) {
d3e89bac 4049 dev_err(hba->dev,
7eb584db
DR		 4050 "%s: power mode change failed %d\n", __func__, ret);
4051 } else {
bea8340e 4052 ufshcd_hold(hba, false);
8214b377 4053 ret = ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
0263bcd0 4054 pwr_mode);
bea8340e 4055 ufshcd_release(hba);
8214b377 4056 if (ret)
4057 goto out;
7eb584db
DR		 4058
4059 memcpy(&hba->pwr_info, pwr_mode,
4060 sizeof(struct ufs_pa_layer_attr));
4061 }
4062
4063 return ret;
4064}
4065
4066/**
4067 * ufshcd_config_pwr_mode - configure a new power mode
4068 * @hba: per-adapter instance
4069 * @desired_pwr_mode: desired power configuration
4070 */
623b5fe3 4071int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4072 struct ufs_pa_layer_attr *desired_pwr_mode)
4073{
4074 struct ufs_pa_layer_attr final_params = { 0 };
4075 int ret;
4076
bea8340e 4077 ufshcd_hold(hba, false);
0263bcd0
YG		 4078 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4079 desired_pwr_mode, &final_params);
4080
8214b377 4081 if (ret) {
4082 if (ret == -ENOTSUPP)
4083 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4084 else
4085 goto out;
4086 }
7eb584db
DR		 4087
4088 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5
SJ		 4089 if (!ret)
4090 ufshcd_print_pwr_info(hba);
8214b377 4091out:
bea8340e 4092 ufshcd_release(hba);
d3e89bac
SJ		 4093 return ret;
4094}
623b5fe3 4095EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4096
68078d5c
DR		 4097/**
4098 * ufshcd_complete_dev_init() - checks device readiness
4099 * hba: per-adapter instance
4100 *
4101 * Set fDeviceInit flag and poll until device toggles it.
4102 */
4103static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4104{
dc3c8d3a
YG		 4105 int i;
4106 int err;
68078d5c
DR		 4107 bool flag_res = 1;
4108
dc3c8d3a
YG		 4109 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4110 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 4111 if (err) {
4112 dev_err(hba->dev,
4113 "%s setting fDeviceInit flag failed with error %d\n",
4114 __func__, err);
4115 goto out;
4116 }
4117
dc3c8d3a
YG		 4118 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
4119 for (i = 0; i < 1000 && !err && flag_res; i++)
4120 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4121 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4122
68078d5c
DR		 4123 if (err)
4124 dev_err(hba->dev,
4125 "%s reading fDeviceInit flag failed with error %d\n",
4126 __func__, err);
4127 else if (flag_res)
4128 dev_err(hba->dev,
4129 "%s fDeviceInit was not cleared by the device\n",
4130 __func__);
4131
4132out:
4133 return err;
4134}
4135
7a3e97b0
SY		 4136/**
4137 * ufshcd_make_hba_operational - Make UFS controller operational
4138 * @hba: per adapter instance
4139 *
4140 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4141 * 1. Enable required interrupts
4142 * 2. Configure interrupt aggregation
897efe62 4143 * 3. Program UTRL and UTMRL base address
5c0c28a8 4144 * 4. Configure run-stop-registers
7a3e97b0
SY		 4145 *
4146 * Returns 0 on success, non-zero value on failure
4147 */
4148static int ufshcd_make_hba_operational(struct ufs_hba *hba)
4149{
4150 int err = 0;
4151 u32 reg;
4152
6ccf44fe
SJ		 4153 /* Enable required interrupts */
4154 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4155
4156 /* Configure interrupt aggregation */
b852190e
YG		 4157 if (ufshcd_is_intr_aggr_allowed(hba))
4158 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4159 else
4160 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4161
4162 /* Configure UTRL and UTMRL base address registers */
4163 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4164 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4165 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4166 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4167 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4168 REG_UTP_TASK_REQ_LIST_BASE_L);
4169 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4170 REG_UTP_TASK_REQ_LIST_BASE_H);
4171
897efe62
YG		 4172 /*
4173 * Make sure base address and interrupt setup are updated before
4174 * enabling the run/stop registers below.
4175 */
4176 wmb();
4177
7a3e97b0
SY		 4178 /*
4179 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4180 */
5c0c28a8 4181 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4182 if (!(ufshcd_get_lists_status(reg))) {
4183 ufshcd_enable_run_stop_reg(hba);
4184 } else {
3b1d0580 4185 dev_err(hba->dev,
7a3e97b0
SY		 4186 "Host controller not ready to process requests");
4187 err = -EIO;
4188 goto out;
4189 }
4190
7a3e97b0
SY		 4191out:
4192 return err;
4193}
4194
596585a2
YG		 4195/**
4196 * ufshcd_hba_stop - Send controller to reset state
4197 * @hba: per adapter instance
4198 * @can_sleep: perform sleep or just spin
4199 */
4200static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4201{
4202 int err;
4203
4204 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4205 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4206 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4207 10, 1, can_sleep);
4208 if (err)
4209 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4210}
4211
7a3e97b0 4212/**
623b5fe3 4213 * _ufshcd_hba_enable - initialize the controller
7a3e97b0
SY		 4214 * @hba: per adapter instance
4215 *
4216 * The controller resets itself and controller firmware initialization
4217 * sequence kicks off. When controller is ready it will set
4218 * the Host Controller Enable bit to 1.
4219 *
4220 * Returns 0 on success, non-zero value on failure
4221 */
623b5fe3 4222static int __ufshcd_hba_enable(struct ufs_hba *hba)
7a3e97b0
SY		 4223{
4224 int retry;
4225
4226 /*
4227 * msleep of 1 and 5 used in this function might result in msleep(20),
4228 * but it was necessary to send the UFS FPGA to reset mode during
4229 * development and testing of this driver. msleep can be changed to
4230 * mdelay and retry count can be reduced based on the controller.
4231 */
596585a2 4232 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4233 /* change controller state to "reset state" */
596585a2 4234 ufshcd_hba_stop(hba, true);
7a3e97b0 4235
57d104c1
SJ		 4236 /* UniPro link is disabled at this point */
4237 ufshcd_set_link_off(hba);
4238
0263bcd0 4239 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4240
7a3e97b0
SY		 4241 /* start controller initialization sequence */
4242 ufshcd_hba_start(hba);
4243
4244 /*
4245 * To initialize a UFS host controller HCE bit must be set to 1.
4246 * During initialization the HCE bit value changes from 1->0->1.
4247 * When the host controller completes initialization sequence
4248 * it sets the value of HCE bit to 1. The same HCE bit is read back
4249 * to check if the controller has completed initialization sequence.
4250 * So without this delay the value HCE = 1, set in the previous
4251 * instruction might be read back.
4252 * This delay can be changed based on the controller.
4253 */
4254 msleep(1);
4255
4256 /* wait for the host controller to complete initialization */
4257 retry = 10;
4258 while (ufshcd_is_hba_active(hba)) {
4259 if (retry) {
4260 retry--;
4261 } else {
3b1d0580 4262 dev_err(hba->dev,
7a3e97b0
SY		 4263 "Controller enable failed\n");
4264 return -EIO;
4265 }
4266 msleep(5);
4267 }
5c0c28a8 4268
1d337ec2 4269 /* enable UIC related interrupts */
57d104c1 4270 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4271
0263bcd0 4272 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4273
7a3e97b0
SY		 4274 return 0;
4275}
4276
7ca38cf3
YG		 4277static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4278{
4279 int tx_lanes, i, err = 0;
4280
4281 if (!peer)
4282 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4283 &tx_lanes);
4284 else
4285 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4286 &tx_lanes);
4287 for (i = 0; i < tx_lanes; i++) {
4288 if (!peer)
4289 err = ufshcd_dme_set(hba,
4290 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4291 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4292 0);
4293 else
4294 err = ufshcd_dme_peer_set(hba,
4295 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4296 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4297 0);
4298 if (err) {
4299 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4300 __func__, peer, i, err);
4301 break;
4302 }
4303 }
4304
4305 return err;
4306}
4307
4308static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4309{
4310 return ufshcd_disable_tx_lcc(hba, true);
4311}
4312
623b5fe3 4313static int ufshcd_hba_enable(struct ufs_hba *hba)
4314{
4315 int ret;
2bfd4b44 4316 unsigned long flags;
4317
bea8340e 4318 ufshcd_hold(hba, false);
4319
2bfd4b44 4320 spin_lock_irqsave(hba->host->host_lock, flags);
5801290e 4321 hba->ufshcd_state = UFSHCD_STATE_RESET;
2bfd4b44 4322 spin_unlock_irqrestore(hba->host->host_lock, flags);
4323
623b5fe3 4324 if (hba->vops && hba->vops->host_reset)
4325 hba->vops->host_reset(hba);
4326 if (hba->quirks & UFSHCD_QUIRK_USE_OF_HCE) {
5801290e 4327 ufshcd_set_link_off(hba);
623b5fe3 4328 /* enable UIC related interrupts */
4329 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4330
4331 ret = ufshcd_dme_reset(hba);
4332 if (!ret)
4333 ret = ufshcd_dme_enable(hba);
4334 } else {
4335 ret = __ufshcd_hba_enable(hba);
4336 }
bea8340e 4337 ufshcd_release(hba);
4338
251f4e5f 4339 if (ret)
4340 dev_err(hba->dev, "Host controller enable failed\n");
4341
623b5fe3 4342 return ret;
4343}
4344
7a3e97b0 4345/**
6ccf44fe 4346 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4347 * @hba: per adapter instance
4348 *
6ccf44fe 4349 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4350 */
6ccf44fe 4351static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4352{
6ccf44fe 4353 int ret;
1d337ec2 4354 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4355 bool link_startup_again = false;
7a3e97b0 4356
bea8340e 4357
4358 ufshcd_hold(hba, false);
4359
7caf489b
SJ		 4360 /*
4361 * If UFS device isn't active then we will have to issue link startup
4362 * 2 times to make sure the device state move to active.
4363 */
4364 if (!ufshcd_is_ufs_dev_active(hba))
4365 link_startup_again = true;
7a3e97b0 4366
7caf489b 4367link_startup:
1d337ec2 4368 do {
0263bcd0 4369 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4370
1d337ec2 4371 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4372
1d337ec2
SRT		 4373 /* check if device is detected by inter-connect layer */
4374 if (!ret && !ufshcd_is_device_present(hba)) {
4375 dev_err(hba->dev, "%s: Device not present\n", __func__);
4376 ret = -ENXIO;
4377 goto out;
4378 }
6ccf44fe 4379
1d337ec2
SRT		 4380 /*
4381 * DME link lost indication is only received when link is up,
4382 * but we can't be sure if the link is up until link startup
4383 * succeeds. So reset the local Uni-Pro and try again.
4384 */
4385 if (ret && ufshcd_hba_enable(hba))
4386 goto out;
4387 } while (ret && retries--);
4388
4389 if (ret)
4390 /* failed to get the link up... retire */
5c0c28a8 4391 goto out;
5c0c28a8 4392
7caf489b
SJ		 4393 if (link_startup_again) {
4394 link_startup_again = false;
4395 retries = DME_LINKSTARTUP_RETRIES;
4396 goto link_startup;
4397 }
4398
d2aebb9b
SJ		 4399 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4400 ufshcd_init_pwr_info(hba);
4401 ufshcd_print_pwr_info(hba);
4402
7ca38cf3
YG		 4403 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4404 ret = ufshcd_disable_device_tx_lcc(hba);
4405 if (ret)
4406 goto out;
4407 }
4408
5c0c28a8 4409 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4410 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4411 if (ret)
4412 goto out;
7a3e97b0 4413
5c0c28a8 4414 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4415out:
bea8340e 4416 ufshcd_release(hba);
4417
7942f7b5 4418 if (ret) {
6ccf44fe 4419 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4420 ufshcd_print_host_state(hba);
4421 ufshcd_print_pwr_info(hba);
4422 ufshcd_print_host_regs(hba);
4423 }
6ccf44fe 4424 return ret;
7a3e97b0
SY		 4425}
4426
5a0b0cb9
SRT		 4427/**
4428 * ufshcd_verify_dev_init() - Verify device initialization
4429 * @hba: per-adapter instance
4430 *
4431 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4432 * device Transport Protocol (UTP) layer is ready after a reset.
4433 * If the UTP layer at the device side is not initialized, it may
4434 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4435 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4436 */
4437static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4438{
4439 int err = 0;
4440 int retries;
4441
1ab27c9c 4442 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4443 mutex_lock(&hba->dev_cmd.lock);
4444 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4445 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4446 NOP_OUT_TIMEOUT);
4447
4448 if (!err || err == -ETIMEDOUT)
4449 break;
4450
4451 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4452 }
4453 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4454 ufshcd_release(hba);
5a0b0cb9
SRT		 4455
4456 if (err)
4457 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4458 return err;
4459}
4460
0ce147d4
SJ		 4461/**
4462 * ufshcd_set_queue_depth - set lun queue depth
4463 * @sdev: pointer to SCSI device
4464 *
4465 * Read bLUQueueDepth value and activate scsi tagged command
4466 * queueing. For WLUN, queue depth is set to 1. For best-effort
4467 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4468 * value that host can queue.
4469 */
4470static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4471{
4472 int ret = 0;
4473 u8 lun_qdepth;
4474 struct ufs_hba *hba;
4475
4476 hba = shost_priv(sdev->host);
4477
4478 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4479 ret = ufshcd_read_unit_desc_param(hba,
4480 ufshcd_scsi_to_upiu_lun(sdev->lun),
4481 UNIT_DESC_PARAM_LU_Q_DEPTH,
4482 &lun_qdepth,
4483 sizeof(lun_qdepth));
0ce147d4
SJ		 4484
4485 /* Some WLUN doesn't support unit descriptor */
4486 if (ret == -EOPNOTSUPP)
4487 lun_qdepth = 1;
4488 else if (!lun_qdepth)
4489 /* eventually, we can figure out the real queue depth */
4490 lun_qdepth = hba->nutrs;
4491 else
4492 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4493
4494 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4495 __func__, lun_qdepth);
db5ed4df 4496 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4497}
4498
57d104c1
SJ		 4499/*
4500 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4501 * @hba: per-adapter instance
4502 * @lun: UFS device lun id
4503 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4504 *
4505 * Returns 0 in case of success and b_lu_write_protect status would be returned
4506 * @b_lu_write_protect parameter.
4507 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4508 * Returns -EINVAL in case of invalid parameters passed to this function.
4509 */
4510static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4511 u8 lun,
4512 u8 *b_lu_write_protect)
4513{
4514 int ret;
4515
4516 if (!b_lu_write_protect)
4517 ret = -EINVAL;
4518 /*
4519 * According to UFS device spec, RPMB LU can't be write
4520 * protected so skip reading bLUWriteProtect parameter for
4521 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4522 */
4523 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4524 ret = -ENOTSUPP;
4525 else
4526 ret = ufshcd_read_unit_desc_param(hba,
4527 lun,
4528 UNIT_DESC_PARAM_LU_WR_PROTECT,
4529 b_lu_write_protect,
4530 sizeof(*b_lu_write_protect));
4531 return ret;
4532}
4533
4534/**
4535 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4536 * status
4537 * @hba: per-adapter instance
4538 * @sdev: pointer to SCSI device
4539 *
4540 */
4541static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4542 struct scsi_device *sdev)
4543{
4544 if (hba->dev_info.f_power_on_wp_en &&
4545 !hba->dev_info.is_lu_power_on_wp) {
4546 u8 b_lu_write_protect;
4547
4548 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4549 &b_lu_write_protect) &&
4550 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4551 hba->dev_info.is_lu_power_on_wp = true;
4552 }
4553}
4554
7a3e97b0
SY		 4555/**
4556 * ufshcd_slave_alloc - handle initial SCSI device configurations
4557 * @sdev: pointer to SCSI device
4558 *
4559 * Returns success
4560 */
4561static int ufshcd_slave_alloc(struct scsi_device *sdev)
4562{
4563 struct ufs_hba *hba;
4564
4565 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4566
4567 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4568 sdev->use_10_for_ms = 1;
7a3e97b0 4569
e8e7f271
SRT		 4570 /* allow SCSI layer to restart the device in case of errors */
4571 sdev->allow_restart = 1;
4264fd61 4572
b2a6c522
SRT		 4573 /* REPORT SUPPORTED OPERATION CODES is not supported */
4574 sdev->no_report_opcodes = 1;
4575
e8e7f271 4576
0ce147d4 4577 ufshcd_set_queue_depth(sdev);
4264fd61 4578
57d104c1
SJ		 4579 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4580
7a3e97b0
SY		 4581 return 0;
4582}
4583
4264fd61
SRT		 4584/**
4585 * ufshcd_change_queue_depth - change queue depth
4586 * @sdev: pointer to SCSI device
4587 * @depth: required depth to set
4264fd61 4588 *
db5ed4df 4589 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4590 */
db5ed4df 4591static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4592{
4593 struct ufs_hba *hba = shost_priv(sdev->host);
4594
4595 if (depth > hba->nutrs)
4596 depth = hba->nutrs;
db5ed4df 4597 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4598}
4599
eeda4749
AM		 4600/**
4601 * ufshcd_slave_configure - adjust SCSI device configurations
4602 * @sdev: pointer to SCSI device
4603 */
4604static int ufshcd_slave_configure(struct scsi_device *sdev)
4605{
4606 struct request_queue *q = sdev->request_queue;
4607
4608 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4609 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
623b5fe3 4610 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
eeda4749
AM		 4611
4612 return 0;
4613}
4614
7a3e97b0
SY		 4615/**
4616 * ufshcd_slave_destroy - remove SCSI device configurations
4617 * @sdev: pointer to SCSI device
4618 */
4619static void ufshcd_slave_destroy(struct scsi_device *sdev)
4620{
4621 struct ufs_hba *hba;
4622
4623 hba = shost_priv(sdev->host);
0ce147d4 4624 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4625 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4626 unsigned long flags;
4627
4628 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4629 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4630 spin_unlock_irqrestore(hba->host->host_lock, flags);
4631 }
7a3e97b0
SY		 4632}
4633
4634/**
4635 * ufshcd_task_req_compl - handle task management request completion
4636 * @hba: per adapter instance
4637 * @index: index of the completed request
e2933132 4638 * @resp: task management service response
7a3e97b0 4639 *
e2933132 4640 * Returns non-zero value on error, zero on success
7a3e97b0 4641 */
e2933132 4642static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 4643{
4644 struct utp_task_req_desc *task_req_descp;
4645 struct utp_upiu_task_rsp *task_rsp_upiup;
4646 unsigned long flags;
4647 int ocs_value;
4648 int task_result;
4649
4650 spin_lock_irqsave(hba->host->host_lock, flags);
4651
7a3e97b0
SY		 4652 task_req_descp = hba->utmrdl_base_addr;
4653 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
4654
4655 if (ocs_value == OCS_SUCCESS) {
4656 task_rsp_upiup = (struct utp_upiu_task_rsp *)
4657 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 4658 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
4659 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 4660 if (resp)
4661 *resp = (u8)task_result;
7a3e97b0 4662 } else {
e2933132
SRT		 4663 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
4664 __func__, ocs_value);
7a3e97b0
SY		 4665 }
4666 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 4667
4668 return ocs_value;
7a3e97b0
SY		 4669}
4670
7a3e97b0
SY		 4671/**
4672 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
4673 * @lrb: pointer to local reference block of completed command
4674 * @scsi_status: SCSI command status
4675 *
4676 * Returns value base on SCSI command status
4677 */
4678static inline int
4679ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4680{
4681 int result = 0;
4682
4683 switch (scsi_status) {
7a3e97b0 4684 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 4685 ufshcd_copy_sense_data(lrbp);
4686 case SAM_STAT_GOOD:
7a3e97b0
SY		 4687 result |= DID_OK << 16 |
4688 COMMAND_COMPLETE << 8 |
1c2623c5 4689 scsi_status;
7a3e97b0
SY		 4690 break;
4691 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4692 case SAM_STAT_BUSY:
7a3e97b0 4693 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4694 ufshcd_copy_sense_data(lrbp);
4695 result |= scsi_status;
7a3e97b0
SY		 4696 break;
4697 default:
4698 result |= DID_ERROR << 16;
4699 break;
4700 } /* end of switch */
4701
4702 return result;
4703}
4704
4705/**
4706 * ufshcd_transfer_rsp_status - Get overall status of the response
4707 * @hba: per adapter instance
4708 * @lrb: pointer to local reference block of completed command
4709 *
4710 * Returns result of the command to notify SCSI midlayer
4711 */
4712static inline int
4713ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4714{
4715 int result = 0;
4716 int scsi_status;
4717 int ocs;
4718
4719 /* overall command status of utrd */
4720 ocs = ufshcd_get_tr_ocs(lrbp);
4721
4722 switch (ocs) {
4723 case OCS_SUCCESS:
623b5fe3 4724 case OCS_FATAL_ERROR:
5a0b0cb9 4725 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4726 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4727 switch (result) {
4728 case UPIU_TRANSACTION_RESPONSE:
4729 /*
4730 * get the response UPIU result to extract
4731 * the SCSI command status
4732 */
4733 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4734
4735 /*
4736 * get the result based on SCSI status response
4737 * to notify the SCSI midlayer of the command status
4738 */
4739 scsi_status = result & MASK_SCSI_STATUS;
4740 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4741
f05ac2e5
YG		 4742 /*
4743 * Currently we are only supporting BKOPs exception
4744 * events hence we can ignore BKOPs exception event
4745 * during power management callbacks. BKOPs exception
4746 * event is not expected to be raised in runtime suspend
4747 * callback as it allows the urgent bkops.
4748 * During system suspend, we are anyway forcefully
4749 * disabling the bkops and if urgent bkops is needed
4750 * it will be enabled on system resume. Long term
4751 * solution could be to abort the system suspend if
4752 * UFS device needs urgent BKOPs.
4753 */
4754 if (!hba->pm_op_in_progress &&
abebc6eb 4755 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr) &&
4756 scsi_host_in_recovery(hba->host)) {
66ec6d59 4757 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 4758 break;
4759 case UPIU_TRANSACTION_REJECT_UPIU:
4760 /* TODO: handle Reject UPIU Response */
4761 result = DID_ERROR << 16;
3b1d0580 4762 dev_err(hba->dev,
5a0b0cb9
SRT		 4763 "Reject UPIU not fully implemented\n");
4764 break;
4765 default:
4766 result = DID_ERROR << 16;
4767 dev_err(hba->dev,
4768 "Unexpected request response code = %x\n",
4769 result);
7a3e97b0
SY		 4770 break;
4771 }
7a3e97b0
SY		 4772 break;
4773 case OCS_ABORTED:
4774 result |= DID_ABORT << 16;
4775 break;
e8e7f271
SRT		 4776 case OCS_INVALID_COMMAND_STATUS:
4777 result |= DID_REQUEUE << 16;
4778 break;
7a3e97b0
SY		 4779 case OCS_INVALID_CMD_TABLE_ATTR:
4780 case OCS_INVALID_PRDT_ATTR:
4781 case OCS_MISMATCH_DATA_BUF_SIZE:
4782 case OCS_MISMATCH_RESP_UPIU_SIZE:
4783 case OCS_PEER_COMM_FAILURE:
7a3e97b0
SY		 4784 default:
4785 result |= DID_ERROR << 16;
3b1d0580 4786 dev_err(hba->dev,
ff8e20c6
DR		 4787 "OCS error from controller = %x for tag %d\n",
4788 ocs, lrbp->task_tag);
4789 ufshcd_print_host_regs(hba);
6ba65588 4790 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4791 break;
4792 } /* end of switch */
4793
66cc820f
DR		 4794 if (host_byte(result) != DID_OK)
4795 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4796 return result;
4797}
4798
6ccf44fe
SJ		 4799/**
4800 * ufshcd_uic_cmd_compl - handle completion of uic command
4801 * @hba: per adapter instance
53b3d9c3 4802 * @intr_status: interrupt status generated by the controller
6ccf44fe 4803 */
53b3d9c3 4804static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4805{
53b3d9c3 4806 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4807 hba->active_uic_cmd->argument2 |=
4808 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4809 hba->active_uic_cmd->argument3 =
4810 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 4811 complete(&hba->active_uic_cmd->done);
4812 }
53b3d9c3 4813
57d104c1
SJ		 4814 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4815 complete(hba->uic_async_done);
6ccf44fe
SJ		 4816}
4817
7a3e97b0 4818/**
9a47ec7c 4819 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4820 * @hba: per adapter instance
9a47ec7c 4821 * @completed_reqs: requests to complete
7a3e97b0 4822 */
5bb4e709 4823static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, int reason,
9a47ec7c 4824 unsigned long completed_reqs)
7a3e97b0 4825{
5a0b0cb9
SRT		 4826 struct ufshcd_lrb *lrbp;
4827 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4828 int result;
4829 int index;
e9d501b1 4830
e9d501b1
DR		 4831 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4832 lrbp = &hba->lrb[index];
4833 cmd = lrbp->cmd;
4834 if (cmd) {
1a07f2d9 4835 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1
DR		 4836 result = ufshcd_transfer_rsp_status(hba, lrbp);
4837 scsi_dma_unmap(cmd);
4838 cmd->result = result;
5bb4e709 4839 if (reason)
4840 set_host_byte(cmd, reason);
e9d501b1
DR		 4841 /* Mark completed command as NULL in LRB */
4842 lrbp->cmd = NULL;
4843 clear_bit_unlock(index, &hba->lrb_in_use);
4844 /* Do not touch lrbp after scsi done */
4845 cmd->scsi_done(cmd);
1ab27c9c 4846 __ufshcd_release(hba);
300bb13f
JP		 4847 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4848 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 4849 if (hba->dev_cmd.complete) {
4850 ufshcd_add_command_trace(hba, index,
4851 "dev_complete");
e9d501b1 4852 complete(hba->dev_cmd.complete);
1a07f2d9 4853 }
e9d501b1 4854 }
401f1e44
SJ		 4855 if (ufshcd_is_clkscaling_supported(hba))
4856 hba->clk_scaling.active_reqs--;
e9d501b1 4857 }
7a3e97b0
SY		 4858
4859 /* clear corresponding bits of completed commands */
4860 hba->outstanding_reqs ^= completed_reqs;
4861
856b3483
ST		 4862 ufshcd_clk_scaling_update_busy(hba);
4863
5a0b0cb9
SRT		 4864 /* we might have free'd some tags above */
4865 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 4866}
4867
9a47ec7c
YG		 4868/**
4869 * ufshcd_transfer_req_compl - handle SCSI and query command completion
4870 * @hba: per adapter instance
4871 */
4872static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
4873{
4874 unsigned long completed_reqs;
4875 u32 tr_doorbell;
4876
4877 /* Resetting interrupt aggregation counters first and reading the
4878 * DOOR_BELL afterward allows us to handle all the completed requests.
4879 * In order to prevent other interrupts starvation the DB is read once
4880 * after reset. The down side of this solution is the possibility of
4881 * false interrupt if device completes another request after resetting
4882 * aggregation and before reading the DB.
4883 */
4884 if (ufshcd_is_intr_aggr_allowed(hba))
4885 ufshcd_reset_intr_aggr(hba);
4886
4887 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
4888 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
4889
4890 __ufshcd_transfer_req_compl(hba, completed_reqs);
4891}
4892
66ec6d59
SRT		 4893/**
4894 * ufshcd_disable_ee - disable exception event
4895 * @hba: per-adapter instance
4896 * @mask: exception event to disable
4897 *
4898 * Disables exception event in the device so that the EVENT_ALERT
4899 * bit is not set.
4900 *
4901 * Returns zero on success, non-zero error value on failure.
4902 */
4903static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
4904{
4905 int err = 0;
4906 u32 val;
4907
4908 if (!(hba->ee_ctrl_mask & mask))
4909 goto out;
4910
4911 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 4912 val &= MASK_EE_STATUS;
5e86ae44 4913 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4914 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4915 if (!err)
4916 hba->ee_ctrl_mask &= ~mask;
4917out:
4918 return err;
4919}
4920
4921/**
4922 * ufshcd_enable_ee - enable exception event
4923 * @hba: per-adapter instance
4924 * @mask: exception event to enable
4925 *
4926 * Enable corresponding exception event in the device to allow
4927 * device to alert host in critical scenarios.
4928 *
4929 * Returns zero on success, non-zero error value on failure.
4930 */
4931static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
4932{
4933 int err = 0;
4934 u32 val;
4935
4936 if (hba->ee_ctrl_mask & mask)
4937 goto out;
4938
4939 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 4940 val &= MASK_EE_STATUS;
5e86ae44 4941 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 4942 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
4943 if (!err)
4944 hba->ee_ctrl_mask |= mask;
4945out:
4946 return err;
4947}
4948
4949/**
4950 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
4951 * @hba: per-adapter instance
4952 *
4953 * Allow device to manage background operations on its own. Enabling
4954 * this might lead to inconsistent latencies during normal data transfers
4955 * as the device is allowed to manage its own way of handling background
4956 * operations.
4957 *
4958 * Returns zero on success, non-zero on failure.
4959 */
4960static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
4961{
4962 int err = 0;
4963
4964 if (hba->auto_bkops_enabled)
4965 goto out;
4966
dc3c8d3a 4967 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 4968 QUERY_FLAG_IDN_BKOPS_EN, NULL);
4969 if (err) {
4970 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
4971 __func__, err);
4972 goto out;
4973 }
4974
4975 hba->auto_bkops_enabled = true;
7ff5ab47 4976 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 4977
4978 /* No need of URGENT_BKOPS exception from the device */
4979 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
4980 if (err)
4981 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
4982 __func__, err);
4983out:
4984 return err;
4985}
4986
4987/**
4988 * ufshcd_disable_auto_bkops - block device in doing background operations
4989 * @hba: per-adapter instance
4990 *
4991 * Disabling background operations improves command response latency but
4992 * has drawback of device moving into critical state where the device is
4993 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
4994 * host is idle so that BKOPS are managed effectively without any negative
4995 * impacts.
4996 *
4997 * Returns zero on success, non-zero on failure.
4998 */
4999static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5000{
5001 int err = 0;
5002
5003 if (!hba->auto_bkops_enabled)
5004 goto out;
5005
5006 /*
5007 * If host assisted BKOPs is to be enabled, make sure
5008 * urgent bkops exception is allowed.
5009 */
5010 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5011 if (err) {
5012 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5013 __func__, err);
5014 goto out;
5015 }
5016
dc3c8d3a 5017 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 5018 QUERY_FLAG_IDN_BKOPS_EN, NULL);
5019 if (err) {
5020 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5021 __func__, err);
5022 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5023 goto out;
5024 }
5025
5026 hba->auto_bkops_enabled = false;
7ff5ab47 5027 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT		 5028out:
5029 return err;
5030}
5031
5032/**
4e768e76 5033 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5034 * @hba: per adapter instance
5035 *
5036 * After a device reset the device may toggle the BKOPS_EN flag
5037 * to default value. The s/w tracking variables should be updated
4e768e76
SJ		 5038 * as well. This function would change the auto-bkops state based on
5039 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5040 */
4e768e76 5041static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5042{
4e768e76
SJ		 5043 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5044 hba->auto_bkops_enabled = false;
5045 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5046 ufshcd_enable_auto_bkops(hba);
5047 } else {
5048 hba->auto_bkops_enabled = true;
5049 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5050 ufshcd_disable_auto_bkops(hba);
5051 }
66ec6d59
SRT		 5052}
5053
5054static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5055{
5e86ae44 5056 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5057 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5058}
5059
5060/**
57d104c1 5061 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5062 * @hba: per-adapter instance
57d104c1 5063 * @status: bkops_status value
66ec6d59 5064 *
57d104c1
SJ		 5065 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5066 * flag in the device to permit background operations if the device
5067 * bkops_status is greater than or equal to "status" argument passed to
5068 * this function, disable otherwise.
5069 *
5070 * Returns 0 for success, non-zero in case of failure.
5071 *
5072 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5073 * to know whether auto bkops is enabled or disabled after this function
5074 * returns control to it.
66ec6d59 5075 */
57d104c1
SJ		 5076static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5077 enum bkops_status status)
66ec6d59
SRT		 5078{
5079 int err;
57d104c1 5080 u32 curr_status = 0;
66ec6d59 5081
57d104c1 5082 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5083 if (err) {
5084 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5085 __func__, err);
5086 goto out;
57d104c1
SJ		 5087 } else if (curr_status > BKOPS_STATUS_MAX) {
5088 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5089 __func__, curr_status);
5090 err = -EINVAL;
5091 goto out;
66ec6d59
SRT		 5092 }
5093
57d104c1 5094 if (curr_status >= status)
66ec6d59 5095 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 5096 else
5097 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5098out:
5099 return err;
5100}
5101
57d104c1
SJ		 5102/**
5103 * ufshcd_urgent_bkops - handle urgent bkops exception event
5104 * @hba: per-adapter instance
5105 *
5106 * Enable fBackgroundOpsEn flag in the device to permit background
5107 * operations.
5108 *
5109 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5110 * and negative error value for any other failure.
5111 */
5112static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5113{
afdfff59 5114 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5115}
5116
66ec6d59
SRT		 5117static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5118{
5e86ae44 5119 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5120 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5121}
5122
afdfff59
YG		 5123static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5124{
5125 int err;
5126 u32 curr_status = 0;
5127
5128 if (hba->is_urgent_bkops_lvl_checked)
5129 goto enable_auto_bkops;
5130
5131 err = ufshcd_get_bkops_status(hba, &curr_status);
5132 if (err) {
5133 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5134 __func__, err);
5135 goto out;
5136 }
5137
5138 /*
5139 * We are seeing that some devices are raising the urgent bkops
5140 * exception events even when BKOPS status doesn't indicate performace
5141 * impacted or critical. Handle these device by determining their urgent
5142 * bkops status at runtime.
5143 */
5144 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5145 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5146 __func__, curr_status);
5147 /* update the current status as the urgent bkops level */
5148 hba->urgent_bkops_lvl = curr_status;
5149 hba->is_urgent_bkops_lvl_checked = true;
5150 }
5151
5152enable_auto_bkops:
5153 err = ufshcd_enable_auto_bkops(hba);
5154out:
5155 if (err < 0)
5156 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5157 __func__, err);
5158}
5159
66ec6d59
SRT		 5160/**
5161 * ufshcd_exception_event_handler - handle exceptions raised by device
5162 * @work: pointer to work data
5163 *
5164 * Read bExceptionEventStatus attribute from the device and handle the
5165 * exception event accordingly.
5166 */
5167static void ufshcd_exception_event_handler(struct work_struct *work)
5168{
5169 struct ufs_hba *hba;
5170 int err;
5171 u32 status = 0;
5172 hba = container_of(work, struct ufs_hba, eeh_work);
5173
62694735 5174 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 5175 err = ufshcd_get_ee_status(hba, &status);
5176 if (err) {
5177 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5178 __func__, err);
5179 goto out;
5180 }
5181
5182 status &= hba->ee_ctrl_mask;
afdfff59
YG		 5183
5184 if (status & MASK_EE_URGENT_BKOPS)
5185 ufshcd_bkops_exception_event_handler(hba);
5186
66ec6d59 5187out:
62694735 5188 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 5189 return;
5190}
5191
9a47ec7c
YG		 5192/* Complete requests that have door-bell cleared */
5193static void ufshcd_complete_requests(struct ufs_hba *hba)
5194{
5195 ufshcd_transfer_req_compl(hba);
5196 ufshcd_tmc_handler(hba);
5197}
5198
583fa62d
YG		 5199/**
5200 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5201 * to recover from the DL NAC errors or not.
5202 * @hba: per-adapter instance
5203 *
5204 * Returns true if error handling is required, false otherwise
5205 */
5206static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5207{
5208 unsigned long flags;
5209 bool err_handling = true;
5210
5211 spin_lock_irqsave(hba->host->host_lock, flags);
5212 /*
5213 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5214 * device fatal error and/or DL NAC & REPLAY timeout errors.
5215 */
5216 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5217 goto out;
5218
5219 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5220 ((hba->saved_err & UIC_ERROR) &&
5221 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5222 goto out;
5223
5224 if ((hba->saved_err & UIC_ERROR) &&
5225 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5226 int err;
5227 /*
5228 * wait for 50ms to see if we can get any other errors or not.
5229 */
5230 spin_unlock_irqrestore(hba->host->host_lock, flags);
5231 msleep(50);
5232 spin_lock_irqsave(hba->host->host_lock, flags);
5233
5234 /*
5235 * now check if we have got any other severe errors other than
5236 * DL NAC error?
5237 */
5238 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5239 ((hba->saved_err & UIC_ERROR) &&
5240 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5241 goto out;
5242
5243 /*
5244 * As DL NAC is the only error received so far, send out NOP
5245 * command to confirm if link is still active or not.
5246 * - If we don't get any response then do error recovery.
5247 * - If we get response then clear the DL NAC error bit.
5248 */
5249
5250 spin_unlock_irqrestore(hba->host->host_lock, flags);
5251 err = ufshcd_verify_dev_init(hba);
5252 spin_lock_irqsave(hba->host->host_lock, flags);
5253
5254 if (err)
5255 goto out;
5256
5257 /* Link seems to be alive hence ignore the DL NAC errors */
5258 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5259 hba->saved_err &= ~UIC_ERROR;
5260 /* clear NAC error */
5261 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5262 if (!hba->saved_uic_err) {
5263 err_handling = false;
5264 goto out;
5265 }
5266 }
5267out:
5268 spin_unlock_irqrestore(hba->host->host_lock, flags);
5269 return err_handling;
5270}
5271
7a3e97b0 5272/**
e8e7f271
SRT		 5273 * ufshcd_err_handler - handle UFS errors that require s/w attention
5274 * @work: pointer to work structure
7a3e97b0 5275 */
e8e7f271 5276static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5277{
5278 struct ufs_hba *hba;
e8e7f271
SRT		 5279 unsigned long flags;
5280 u32 err_xfer = 0;
5281 u32 err_tm = 0;
5282 int err = 0;
5283 int tag;
9a47ec7c 5284 bool needs_reset = false;
e8e7f271
SRT		 5285
5286 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5287
62694735 5288 pm_runtime_get_sync(hba->dev);
1ab27c9c 5289 ufshcd_hold(hba, false);
e8e7f271 5290
aee9809c 5291 /* Dump debugging information to system memory */
5292 ufshcd_vops_dbg_register_dump(hba);
e8e7f271 5293 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5294 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5295 goto out;
e8e7f271
SRT		 5296
5297 hba->ufshcd_state = UFSHCD_STATE_RESET;
5298 ufshcd_set_eh_in_progress(hba);
5299
5300 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5301 ufshcd_complete_requests(hba);
583fa62d
YG		 5302
5303 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5304 bool ret;
5305
5306 spin_unlock_irqrestore(hba->host->host_lock, flags);
5307 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5308 ret = ufshcd_quirk_dl_nac_errors(hba);
5309 spin_lock_irqsave(hba->host->host_lock, flags);
5310 if (!ret)
5311 goto skip_err_handling;
5312 }
9a47ec7c
YG		 5313 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5314 ((hba->saved_err & UIC_ERROR) &&
5315 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5316 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5317 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5318 needs_reset = true;
e8e7f271 5319
9a47ec7c
YG		 5320 /*
5321 * if host reset is required then skip clearing the pending
5322 * transfers forcefully because they will automatically get
5323 * cleared after link startup.
5324 */
5325 if (needs_reset)
5326 goto skip_pending_xfer_clear;
5327
5328 /* release lock as clear command might sleep */
5329 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5330 /* Clear pending transfer requests */
9a47ec7c
YG		 5331 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5332 if (ufshcd_clear_cmd(hba, tag)) {
5333 err_xfer = true;
5334 goto lock_skip_pending_xfer_clear;
5335 }
5336 }
e8e7f271
SRT		 5337
5338 /* Clear pending task management requests */
9a47ec7c
YG		 5339 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5340 if (ufshcd_clear_tm_cmd(hba, tag)) {
5341 err_tm = true;
5342 goto lock_skip_pending_xfer_clear;
5343 }
5344 }
e8e7f271 5345
9a47ec7c 5346lock_skip_pending_xfer_clear:
e8e7f271 5347 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5348
9a47ec7c
YG		 5349 /* Complete the requests that are cleared by s/w */
5350 ufshcd_complete_requests(hba);
5351
5352 if (err_xfer || err_tm)
5353 needs_reset = true;
5354
5355skip_pending_xfer_clear:
e8e7f271 5356 /* Fatal errors need reset */
9a47ec7c
YG		 5357 if (needs_reset) {
5358 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5359
5360 /*
5361 * ufshcd_reset_and_restore() does the link reinitialization
5362 * which will need atleast one empty doorbell slot to send the
5363 * device management commands (NOP and query commands).
5364 * If there is no slot empty at this moment then free up last
5365 * slot forcefully.
5366 */
5367 if (hba->outstanding_reqs == max_doorbells)
5368 __ufshcd_transfer_req_compl(hba,
5369 (1UL << (hba->nutrs - 1)));
5370
5371 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5372 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5373 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5374 if (err) {
2bfd4b44 5375 spin_lock_irqsave(hba->host->host_lock, flags);
5376 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5377 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271
SRT		 5378 dev_err(hba->dev, "%s: reset and restore failed\n",
5379 __func__);
5380 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5381 }
e8e7f271
SRT		 5382 hba->saved_err = 0;
5383 hba->saved_uic_err = 0;
5384 }
9a47ec7c 5385
583fa62d 5386skip_err_handling:
9a47ec7c
YG		 5387 if (!needs_reset) {
5388 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5389 if (hba->saved_err || hba->saved_uic_err)
5390 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5391 __func__, hba->saved_err, hba->saved_uic_err);
5392 }
5393
e8e7f271
SRT		 5394 ufshcd_clear_eh_in_progress(hba);
5395
5396out:
9a47ec7c 5397 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5398 scsi_unblock_requests(hba->host);
1ab27c9c 5399 ufshcd_release(hba);
62694735 5400 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5401}
5402
ff8e20c6
DR		 5403static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5404 u32 reg)
5405{
5406 reg_hist->reg[reg_hist->pos] = reg;
5407 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5408 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5409}
5410
7a3e97b0 5411/**
e8e7f271
SRT		 5412 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5413 * @hba: per-adapter instance
7a3e97b0 5414 */
e8e7f271 5415static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5416{
5417 u32 reg;
5418
fb7b45f0
DR		 5419 /* PHY layer lane error */
5420 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5421 /* Ignore LINERESET indication, as this is not an error */
5422 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
ff8e20c6 5423 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5424 /*
5425 * To know whether this error is fatal or not, DB timeout
5426 * must be checked but this error is handled separately.
5427 */
5428 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
ff8e20c6
DR		 5429 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5430 }
fb7b45f0 5431
e8e7f271
SRT		 5432 /* PA_INIT_ERROR is fatal and needs UIC reset */
5433 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
ff8e20c6
DR		 5434 if (reg)
5435 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5436
e8e7f271
SRT		 5437 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5438 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 5439 else if (hba->dev_quirks &
5440 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5441 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5442 hba->uic_error |=
5443 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5444 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5445 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5446 }
e8e7f271 5447
a60d7ef4 5448 if (reg & UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP)
5449 hba->tcx_replay_timer_expired_cnt++;
5450
5451 if (reg & UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP)
5452 hba->fcx_protection_timer_expired_cnt++;
5453
5454 if (hba->tcx_replay_timer_expired_cnt >= 2 ||
5455 hba->fcx_protection_timer_expired_cnt >= 2)
5456 hba->uic_error |= UFSHCD_UIC_DL_ERROR;
5457
e8e7f271
SRT		 5458 /* UIC NL/TL/DME errors needs software retry */
5459 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
ff8e20c6
DR		 5460 if (reg) {
5461 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5462 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
ff8e20c6 5463 }
e8e7f271
SRT		 5464
5465 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
ff8e20c6
DR		 5466 if (reg) {
5467 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5468 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
ff8e20c6 5469 }
e8e7f271
SRT		 5470
5471 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
ff8e20c6
DR		 5472 if (reg) {
5473 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5474 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
ff8e20c6 5475 }
e8e7f271
SRT		 5476
5477 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5478 __func__, hba->uic_error);
5479}
5480
5481/**
5482 * ufshcd_check_errors - Check for errors that need s/w attention
5483 * @hba: per-adapter instance
5484 */
5485static void ufshcd_check_errors(struct ufs_hba *hba)
5486{
5487 bool queue_eh_work = false;
5488
7a3e97b0 5489 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 5490 queue_eh_work = true;
7a3e97b0
SY		 5491
5492 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 5493 hba->uic_error = 0;
5494 ufshcd_update_uic_error(hba);
5495 if (hba->uic_error)
5496 queue_eh_work = true;
7a3e97b0 5497 }
e8e7f271
SRT		 5498
5499 if (queue_eh_work) {
9a47ec7c
YG		 5500 /*
5501 * update the transfer error masks to sticky bits, let's do this
5502 * irrespective of current ufshcd_state.
5503 */
5504 hba->saved_err |= hba->errors;
5505 hba->saved_uic_err |= hba->uic_error;
5506
e8e7f271
SRT		 5507 /* handle fatal errors only when link is functional */
5508 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5509 /* block commands from scsi mid-layer */
5510 scsi_block_requests(hba->host);
5511
141f8165 5512 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5513
5514 /* dump controller state before resetting */
5515 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5516 bool pr_prdt = !!(hba->saved_err &
5517 SYSTEM_BUS_FATAL_ERROR);
5518
5519 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5520 __func__, hba->saved_err,
5521 hba->saved_uic_err);
5522
5523 ufshcd_print_host_regs(hba);
5524 ufshcd_print_pwr_info(hba);
5525 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5526 ufshcd_print_trs(hba, hba->outstanding_reqs,
5527 pr_prdt);
5528 }
e8e7f271
SRT		 5529 schedule_work(&hba->eh_work);
5530 }
3441da7d 5531 }
e8e7f271
SRT		 5532 /*
5533 * if (!queue_eh_work) -
5534 * Other errors are either non-fatal where host recovers
5535 * itself without s/w intervention or errors that will be
5536 * handled by the SCSI core layer.
5537 */
7a3e97b0
SY		 5538}
5539
5540/**
5541 * ufshcd_tmc_handler - handle task management function completion
5542 * @hba: per adapter instance
5543 */
5544static void ufshcd_tmc_handler(struct ufs_hba *hba)
5545{
5546 u32 tm_doorbell;
5547
b873a275 5548 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 5549 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
dbccd8eb 5550 hba->outstanding_tasks ^= hba->tm_condition;
e2933132 5551 wake_up(&hba->tm_wq);
7a3e97b0
SY		 5552}
5553
5554/**
5555 * ufshcd_sl_intr - Interrupt service routine
5556 * @hba: per adapter instance
5557 * @intr_status: contains interrupts generated by the controller
5558 */
5559static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5560{
5561 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5562 if (hba->errors)
e8e7f271 5563 ufshcd_check_errors(hba);
7a3e97b0 5564
53b3d9c3
SJ		 5565 if (intr_status & UFSHCD_UIC_MASK)
5566 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5567
5568 if (intr_status & UTP_TASK_REQ_COMPL)
5569 ufshcd_tmc_handler(hba);
5570
5571 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5572 ufshcd_transfer_req_compl(hba);
5573}
5574
5575/**
5576 * ufshcd_intr - Main interrupt service routine
5577 * @irq: irq number
5578 * @__hba: pointer to adapter instance
5579 *
5580 * Returns IRQ_HANDLED - If interrupt is valid
5581 * IRQ_NONE - If invalid interrupt
5582 */
5583static irqreturn_t ufshcd_intr(int irq, void *__hba)
5584{
d75f7fe4 5585 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5586 irqreturn_t retval = IRQ_NONE;
5587 struct ufs_hba *hba = __hba;
5588
5589 spin_lock(hba->host->host_lock);
b873a275 5590 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5591 enabled_intr_status =
5592 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 5593
d75f7fe4 5594 if (intr_status)
261ea452 5595 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5596
5597 if (enabled_intr_status) {
5598 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 5599 retval = IRQ_HANDLED;
5600 }
5601 spin_unlock(hba->host->host_lock);
5602 return retval;
5603}
5604
e2933132
SRT		 5605static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5606{
5607 int err = 0;
5608 u32 mask = 1 << tag;
5609 unsigned long flags;
5610
e2933132 5611 spin_lock_irqsave(hba->host->host_lock, flags);
86b7a91c 5612 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 5613 spin_unlock_irqrestore(hba->host->host_lock, flags);
5614
5615 /* poll for max. 1 sec to clear door bell register by h/w */
5616 err = ufshcd_wait_for_register(hba,
5617 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5618 mask, 0, 1000, 1000, true);
e2933132
SRT		 5619 return err;
5620}
5621
7a3e97b0
SY		 5622/**
5623 * ufshcd_issue_tm_cmd - issues task management commands to controller
5624 * @hba: per adapter instance
e2933132
SRT		 5625 * @lun_id: LUN ID to which TM command is sent
5626 * @task_id: task ID to which the TM command is applicable
5627 * @tm_function: task management function opcode
5628 * @tm_response: task management service response return value
7a3e97b0 5629 *
e2933132 5630 * Returns non-zero value on error, zero on success.
7a3e97b0 5631 */
e2933132
SRT		 5632static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5633 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 5634{
5635 struct utp_task_req_desc *task_req_descp;
5636 struct utp_upiu_task_req *task_req_upiup;
5637 struct Scsi_Host *host;
5638 unsigned long flags;
e2933132 5639 int free_slot;
7a3e97b0 5640 int err;
e2933132 5641 int task_tag;
7a3e97b0
SY		 5642
5643 host = hba->host;
5644
e2933132
SRT		 5645 /*
5646 * Get free slot, sleep if slots are unavailable.
5647 * Even though we use wait_event() which sleeps indefinitely,
5648 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5649 */
5650 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 5651 ufshcd_hold(hba, false);
7a3e97b0 5652
e2933132 5653 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 5654 task_req_descp = hba->utmrdl_base_addr;
5655 task_req_descp += free_slot;
5656
5657 /* Configure task request descriptor */
5658 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5659 task_req_descp->header.dword_2 =
5660 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5661
5662 /* Configure task request UPIU */
5663 task_req_upiup =
5664 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 5665 task_tag = hba->nutrs + free_slot;
7a3e97b0 5666 task_req_upiup->header.dword_0 =
5a0b0cb9 5667 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 5668 lun_id, task_tag);
7a3e97b0 5669 task_req_upiup->header.dword_1 =
5a0b0cb9 5670 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 5671 /*
5672 * The host shall provide the same value for LUN field in the basic
5673 * header and for Input Parameter.
5674 */
e2933132
SRT		 5675 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
5676 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 5677
d2877be4
KK		 5678 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5679
7a3e97b0 5680 /* send command to the controller */
03229397 5681 if (hba->vops && hba->vops->set_nexus_t_task_mgmt)
5682 hba->vops->set_nexus_t_task_mgmt(hba, free_slot, tm_function);
7a3e97b0 5683 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5684
5685 /* Make sure descriptors are ready before ringing the task doorbell */
5686 wmb();
5687
b873a275 5688 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5689 /* Make sure that doorbell is committed immediately */
5690 wmb();
7a3e97b0
SY		 5691
5692 spin_unlock_irqrestore(host->host_lock, flags);
5693
5694 /* wait until the task management command is completed */
e2933132
SRT		 5695 err = wait_event_timeout(hba->tm_wq,
5696 test_bit(free_slot, &hba->tm_condition),
5697 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5698 if (!err) {
e2933132
SRT		 5699 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5700 __func__, tm_function);
dbccd8eb 5701 if (!ufshcd_clear_tm_cmd(hba, free_slot)) {
5702 spin_lock_irqsave(hba->host->host_lock, flags);
5703 __clear_bit(free_slot, &hba->outstanding_tasks);
5704 spin_unlock_irqrestore(hba->host->host_lock, flags);
5705 } else {
e2933132
SRT		 5706 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5707 __func__, free_slot);
dbccd8eb 5708 }
e2933132
SRT		 5709 err = -ETIMEDOUT;
5710 } else {
5711 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 5712 }
e2933132 5713
7a3e97b0 5714 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 5715 ufshcd_put_tm_slot(hba, free_slot);
5716 wake_up(&hba->tm_tag_wq);
5717
1ab27c9c 5718 ufshcd_release(hba);
7a3e97b0
SY		 5719 return err;
5720}
5721
5722/**
3441da7d
SRT		 5723 * ufshcd_eh_device_reset_handler - device reset handler registered to
5724 * scsi layer.
7a3e97b0
SY		 5725 * @cmd: SCSI command pointer
5726 *
5727 * Returns SUCCESS/FAILED
5728 */
3441da7d 5729static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 5730{
5731 struct Scsi_Host *host;
5732 struct ufs_hba *hba;
5733 unsigned int tag;
5734 u32 pos;
5735 int err;
e2933132
SRT		 5736 u8 resp = 0xF;
5737 struct ufshcd_lrb *lrbp;
3441da7d 5738 unsigned long flags;
7a3e97b0
SY		 5739
5740 host = cmd->device->host;
5741 hba = shost_priv(host);
5742 tag = cmd->request->tag;
5743
aee9809c 5744 /* Dump debugging information to system memory */
5745 ufshcd_vops_dbg_register_dump(hba);
e2933132
SRT		 5746 lrbp = &hba->lrb[tag];
5747 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5748 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 5749 if (!err)
5750 err = resp;
7a3e97b0 5751 goto out;
e2933132 5752 }
7a3e97b0 5753
3441da7d
SRT		 5754 /* clear the commands that were pending for corresponding LUN */
5755 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5756 if (hba->lrb[pos].lun == lrbp->lun) {
5757 err = ufshcd_clear_cmd(hba, pos);
5758 if (err)
5759 break;
7a3e97b0 5760 }
3441da7d
SRT		 5761 }
5762 spin_lock_irqsave(host->host_lock, flags);
5763 ufshcd_transfer_req_compl(hba);
5764 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 5765
7a3e97b0 5766out:
7fabb77b 5767 hba->req_abort_count = 0;
3441da7d
SRT		 5768 if (!err) {
5769 err = SUCCESS;
5770 } else {
5771 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5772 err = FAILED;
5773 }
7a3e97b0
SY		 5774 return err;
5775}
5776
e0b299e3
GB		 5777static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5778{
5779 struct ufshcd_lrb *lrbp;
5780 int tag;
5781
5782 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5783 lrbp = &hba->lrb[tag];
5784 lrbp->req_abort_skip = true;
5785 }
5786}
5787
7a3e97b0
SY		 5788/**
5789 * ufshcd_abort - abort a specific command
5790 * @cmd: SCSI command pointer
5791 *
f20810d8
SRT		 5792 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5793 * command, and in host controller by clearing the door-bell register. There can
5794 * be race between controller sending the command to the device while abort is
5795 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5796 * really issued and then try to abort it.
5797 *
7a3e97b0
SY		 5798 * Returns SUCCESS/FAILED
5799 */
5800static int ufshcd_abort(struct scsi_cmnd *cmd)
5801{
5802 struct Scsi_Host *host;
5803 struct ufs_hba *hba;
5804 unsigned long flags;
5805 unsigned int tag;
f20810d8
SRT		 5806 int err = 0;
5807 int poll_cnt;
e2933132
SRT		 5808 u8 resp = 0xF;
5809 struct ufshcd_lrb *lrbp;
e9d501b1 5810 u32 reg;
7a3e97b0
SY		 5811
5812 host = cmd->device->host;
5813 hba = shost_priv(host);
5814 tag = cmd->request->tag;
e7d38257 5815 lrbp = &hba->lrb[tag];
14497328
YG		 5816 if (!ufshcd_valid_tag(hba, tag)) {
5817 dev_err(hba->dev,
5818 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5819 __func__, tag, cmd, cmd->request);
5820 BUG();
5821 }
7a3e97b0 5822
e7d38257
DR		 5823 /*
5824 * Task abort to the device W-LUN is illegal. When this command
5825 * will fail, due to spec violation, scsi err handling next step
5826 * will be to send LU reset which, again, is a spec violation.
5827 * To avoid these unnecessary/illegal step we skip to the last error
5828 * handling stage: reset and restore.
5829 */
5830 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5831 return ufshcd_eh_host_reset_handler(cmd);
5832
1ab27c9c 5833 ufshcd_hold(hba, false);
aee9809c 5834 /* Dump debugging information to system memory */
5835 ufshcd_vops_dbg_register_dump(hba);
14497328 5836 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 5837 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 5838 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5839 dev_err(hba->dev,
5840 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
5841 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 5842 goto out;
14497328 5843 }
7a3e97b0 5844
e9d501b1
DR		 5845 if (!(reg & (1 << tag))) {
5846 dev_err(hba->dev,
5847 "%s: cmd was completed, but without a notifying intr, tag = %d",
5848 __func__, tag);
f771f925 5849 goto clean;
e9d501b1
DR		 5850 }
5851
66cc820f
DR		 5852 /* Print Transfer Request of aborted task */
5853 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 5854
7fabb77b
GB		 5855 /*
5856 * Print detailed info about aborted request.
5857 * As more than one request might get aborted at the same time,
5858 * print full information only for the first aborted request in order
5859 * to reduce repeated printouts. For other aborted requests only print
5860 * basic details.
5861 */
5862 scsi_print_command(hba->lrb[tag].cmd);
5863 if (!hba->req_abort_count) {
5864 ufshcd_print_host_regs(hba);
6ba65588 5865 ufshcd_print_host_state(hba);
7fabb77b
GB		 5866 ufshcd_print_pwr_info(hba);
5867 ufshcd_print_trs(hba, 1 << tag, true);
5868 } else {
5869 ufshcd_print_trs(hba, 1 << tag, false);
5870 }
5871 hba->req_abort_count++;
e0b299e3
GB		 5872
5873 /* Skip task abort in case previous aborts failed and report failure */
5874 if (lrbp->req_abort_skip) {
5875 err = -EIO;
5876 goto out;
5877 }
5878
f20810d8
SRT		 5879 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
5880 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5881 UFS_QUERY_TASK, &resp);
5882 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
5883 /* cmd pending in the device */
ff8e20c6
DR		 5884 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
5885 __func__, tag);
f20810d8
SRT		 5886 break;
5887 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 5888 /*
5889 * cmd not pending in the device, check if it is
5890 * in transition.
5891 */
ff8e20c6
DR		 5892 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
5893 __func__, tag);
f20810d8
SRT		 5894 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5895 if (reg & (1 << tag)) {
5896 /* sleep for max. 200us to stabilize */
5897 usleep_range(100, 200);
5898 continue;
5899 }
5900 /* command completed already */
ff8e20c6
DR		 5901 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
5902 __func__, tag);
f20810d8
SRT		 5903 goto out;
5904 } else {
ff8e20c6
DR		 5905 dev_err(hba->dev,
5906 "%s: no response from device. tag = %d, err %d\n",
5907 __func__, tag, err);
f20810d8
SRT		 5908 if (!err)
5909 err = resp; /* service response error */
f771f925 5910 dev_err(hba->dev,
5911 "%s: query task failed with err %d\n",
5912 __func__, err);
f20810d8
SRT		 5913 goto out;
5914 }
5915 }
5916
5917 if (!poll_cnt) {
5918 err = -EBUSY;
f771f925 5919 dev_err(hba->dev,
5920 "%s: cmd might be missed, not pending in device\n",
5921 __func__);
7a3e97b0
SY		 5922 goto out;
5923 }
7a3e97b0 5924
e2933132
SRT		 5925 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
5926 UFS_ABORT_TASK, &resp);
5927 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 5928 if (!err) {
f20810d8 5929 err = resp; /* service response error */
ff8e20c6
DR		 5930 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
5931 __func__, tag, err);
5932 }
7a3e97b0 5933 goto out;
e2933132 5934 }
7a3e97b0 5935
f20810d8 5936 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 5937 if (err) {
5938 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
5939 __func__, tag, err);
f20810d8 5940 goto out;
ff8e20c6 5941 }
f771f925 5942clean:
7a3e97b0
SY		 5943 scsi_dma_unmap(cmd);
5944
5945 spin_lock_irqsave(host->host_lock, flags);
a48353f6 5946 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 5947 hba->lrb[tag].cmd = NULL;
5948 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 5949
5950 clear_bit_unlock(tag, &hba->lrb_in_use);
5951 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 5952
7a3e97b0 5953out:
f20810d8
SRT		 5954 if (!err) {
5955 err = SUCCESS;
5956 } else {
5957 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 5958 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 5959 err = FAILED;
5960 }
5961
1ab27c9c
ST		 5962 /*
5963 * This ufshcd_release() corresponds to the original scsi cmd that got
5964 * aborted here (as we won't get any IRQ for it).
5965 */
5966 ufshcd_release(hba);
7a3e97b0
SY		 5967 return err;
5968}
5969
3441da7d
SRT		 5970/**
5971 * ufshcd_host_reset_and_restore - reset and restore host controller
5972 * @hba: per-adapter instance
5973 *
5974 * Note that host controller reset may issue DME_RESET to
5975 * local and remote (device) Uni-Pro stack and the attributes
5976 * are reset to default state.
5977 *
5978 * Returns zero on success, non-zero on failure
5979 */
5980static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
5981{
5982 int err;
3441da7d
SRT		 5983 unsigned long flags;
5984
5985 /* Reset the host controller */
5986 spin_lock_irqsave(hba->host->host_lock, flags);
0f7f11ff 5987 hba->ufshcd_state = UFSHCD_STATE_RESET;
5988 ufshcd_set_eh_in_progress(hba);
596585a2 5989 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 5990 spin_unlock_irqrestore(hba->host->host_lock, flags);
5991
a3cd5ec5
SJ		 5992 /* scale up clocks to max frequency before full reinitialization */
5993 ufshcd_scale_clks(hba, true);
5994
3441da7d 5995 /* Establish the link again and restore the device */
1d337ec2
SRT		 5996 err = ufshcd_probe_hba(hba);
5997
251f4e5f 5998 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)) {
5999 dev_err(hba->dev, "%s: failed\n", __func__);
6000 err = -EIO;
6001 }
0f7f11ff 6002 spin_lock_irqsave(hba->host->host_lock, flags);
6003 ufshcd_clear_eh_in_progress(hba);
6004 spin_unlock_irqrestore(hba->host->host_lock, flags);
3441da7d
SRT		 6005
6006 return err;
6007}
6008
6009/**
6010 * ufshcd_reset_and_restore - reset and re-initialize host/device
6011 * @hba: per-adapter instance
6012 *
6013 * Reset and recover device, host and re-establish link. This
6014 * is helpful to recover the communication in fatal error conditions.
6015 *
6016 * Returns zero on success, non-zero on failure
6017 */
6018static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6019{
6020 int err = 0;
6021 unsigned long flags;
1d337ec2 6022 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 6023
5bb4e709 6024 int tag;
6025
6026 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
6027 ufshcd_clear_cmd(hba, tag);
6028
6029 spin_lock_irqsave(hba->host->host_lock, flags);
6030 ufshcd_transfer_req_compl(hba, DID_RESET);
6031 spin_unlock_irqrestore(hba->host->host_lock, flags);
6032
6033 ssleep(1);
6034
1d337ec2
SRT		 6035 do {
6036 err = ufshcd_host_reset_and_restore(hba);
6037 } while (err && --retries);
3441da7d
SRT		 6038
6039 /*
6040 * After reset the door-bell might be cleared, complete
6041 * outstanding requests in s/w here.
6042 */
6043 spin_lock_irqsave(hba->host->host_lock, flags);
6044 ufshcd_transfer_req_compl(hba);
6045 ufshcd_tmc_handler(hba);
6046 spin_unlock_irqrestore(hba->host->host_lock, flags);
6047
6048 return err;
6049}
6050
6051/**
6052 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
6053 * @cmd - SCSI command pointer
6054 *
6055 * Returns SUCCESS/FAILED
6056 */
6057static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6058{
6059 int err;
6060 unsigned long flags;
6061 struct ufs_hba *hba;
6062
6063 hba = shost_priv(cmd->device->host);
6064
1ab27c9c 6065 ufshcd_hold(hba, false);
3441da7d
SRT		 6066 /*
6067 * Check if there is any race with fatal error handling.
6068 * If so, wait for it to complete. Even though fatal error
6069 * handling does reset and restore in some cases, don't assume
6070 * anything out of it. We are just avoiding race here.
6071 */
6072 do {
6073 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6074 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 6075 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6076 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 6077 break;
6078 spin_unlock_irqrestore(hba->host->host_lock, flags);
6079 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 6080 flush_work(&hba->eh_work);
3441da7d
SRT		 6081 } while (1);
6082
6083 hba->ufshcd_state = UFSHCD_STATE_RESET;
6084 ufshcd_set_eh_in_progress(hba);
6085 spin_unlock_irqrestore(hba->host->host_lock, flags);
6086
6087 err = ufshcd_reset_and_restore(hba);
6088
6089 spin_lock_irqsave(hba->host->host_lock, flags);
6090 if (!err) {
6091 err = SUCCESS;
6092 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6093 } else {
6094 err = FAILED;
6095 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6096 }
6097 ufshcd_clear_eh_in_progress(hba);
6098 spin_unlock_irqrestore(hba->host->host_lock, flags);
6099
1ab27c9c 6100 ufshcd_release(hba);
3441da7d
SRT		 6101 return err;
6102}
6103
3a4bf06d
YG		 6104/**
6105 * ufshcd_get_max_icc_level - calculate the ICC level
6106 * @sup_curr_uA: max. current supported by the regulator
6107 * @start_scan: row at the desc table to start scan from
6108 * @buff: power descriptor buffer
6109 *
6110 * Returns calculated max ICC level for specific regulator
6111 */
6112static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6113{
6114 int i;
6115 int curr_uA;
6116 u16 data;
6117 u16 unit;
6118
6119 for (i = start_scan; i >= 0; i--) {
d79713f9 6120 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 6121 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6122 ATTR_ICC_LVL_UNIT_OFFSET;
6123 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6124 switch (unit) {
6125 case UFSHCD_NANO_AMP:
6126 curr_uA = curr_uA / 1000;
6127 break;
6128 case UFSHCD_MILI_AMP:
6129 curr_uA = curr_uA * 1000;
6130 break;
6131 case UFSHCD_AMP:
6132 curr_uA = curr_uA * 1000 * 1000;
6133 break;
6134 case UFSHCD_MICRO_AMP:
6135 default:
6136 break;
6137 }
6138 if (sup_curr_uA >= curr_uA)
6139 break;
6140 }
6141 if (i < 0) {
6142 i = 0;
6143 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6144 }
6145
6146 return (u32)i;
6147}
6148
6149/**
6150 * ufshcd_calc_icc_level - calculate the max ICC level
6151 * In case regulators are not initialized we'll return 0
6152 * @hba: per-adapter instance
6153 * @desc_buf: power descriptor buffer to extract ICC levels from.
6154 * @len: length of desc_buff
6155 *
6156 * Returns calculated ICC level
6157 */
6158static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6159 u8 *desc_buf, int len)
6160{
6161 u32 icc_level = 0;
6162
6163 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6164 !hba->vreg_info.vccq2) {
6165 dev_err(hba->dev,
6166 "%s: Regulator capability was not set, actvIccLevel=%d",
6167 __func__, icc_level);
6168 goto out;
6169 }
6170
6171 if (hba->vreg_info.vcc)
6172 icc_level = ufshcd_get_max_icc_level(
6173 hba->vreg_info.vcc->max_uA,
6174 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6175 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6176
6177 if (hba->vreg_info.vccq)
6178 icc_level = ufshcd_get_max_icc_level(
6179 hba->vreg_info.vccq->max_uA,
6180 icc_level,
6181 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6182
6183 if (hba->vreg_info.vccq2)
6184 icc_level = ufshcd_get_max_icc_level(
6185 hba->vreg_info.vccq2->max_uA,
6186 icc_level,
6187 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6188out:
6189 return icc_level;
6190}
6191
6192static void ufshcd_init_icc_levels(struct ufs_hba *hba)
6193{
6194 int ret;
a4b0e8a4
PM		 6195 int buff_len = hba->desc_size.pwr_desc;
6196 u8 desc_buf[hba->desc_size.pwr_desc];
3a4bf06d
YG		 6197
6198 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
6199 if (ret) {
6200 dev_err(hba->dev,
6201 "%s: Failed reading power descriptor.len = %d ret = %d",
6202 __func__, buff_len, ret);
6203 return;
6204 }
6205
6206 hba->init_prefetch_data.icc_level =
6207 ufshcd_find_max_sup_active_icc_level(hba,
6208 desc_buf, buff_len);
6209 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
6210 __func__, hba->init_prefetch_data.icc_level);
6211
dbd34a61
SM		 6212 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6213 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
6214 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 6215
6216 if (ret)
6217 dev_err(hba->dev,
6218 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
6219 __func__, hba->init_prefetch_data.icc_level , ret);
6220
6221}
6222
2a8fa600
SJ		 6223/**
6224 * ufshcd_scsi_add_wlus - Adds required W-LUs
6225 * @hba: per-adapter instance
6226 *
6227 * UFS device specification requires the UFS devices to support 4 well known
6228 * logical units:
6229 * "REPORT_LUNS" (address: 01h)
6230 * "UFS Device" (address: 50h)
6231 * "RPMB" (address: 44h)
6232 * "BOOT" (address: 30h)
6233 * UFS device's power management needs to be controlled by "POWER CONDITION"
6234 * field of SSU (START STOP UNIT) command. But this "power condition" field
6235 * will take effect only when its sent to "UFS device" well known logical unit
6236 * hence we require the scsi_device instance to represent this logical unit in
6237 * order for the UFS host driver to send the SSU command for power management.
6238
6239 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
6240 * Block) LU so user space process can control this LU. User space may also
6241 * want to have access to BOOT LU.
6242
6243 * This function adds scsi device instances for each of all well known LUs
6244 * (except "REPORT LUNS" LU).
6245 *
6246 * Returns zero on success (all required W-LUs are added successfully),
6247 * non-zero error value on failure (if failed to add any of the required W-LU).
6248 */
6249static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6250{
6251 int ret = 0;
7c48bfd0
AM		 6252 struct scsi_device *sdev_rpmb;
6253 struct scsi_device *sdev_boot;
2a8fa600
SJ		 6254
6255 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6256 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6257 if (IS_ERR(hba->sdev_ufs_device)) {
6258 ret = PTR_ERR(hba->sdev_ufs_device);
6259 hba->sdev_ufs_device = NULL;
6260 goto out;
6261 }
7c48bfd0 6262 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6263
7c48bfd0 6264 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6265 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 6266 if (IS_ERR(sdev_boot)) {
6267 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 6268 goto remove_sdev_ufs_device;
6269 }
7c48bfd0 6270 scsi_device_put(sdev_boot);
2a8fa600 6271
7c48bfd0 6272 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6273 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7c48bfd0
AM		 6274 if (IS_ERR(sdev_rpmb)) {
6275 ret = PTR_ERR(sdev_rpmb);
2a8fa600
SJ		 6276 goto remove_sdev_boot;
6277 }
7c48bfd0 6278 scsi_device_put(sdev_rpmb);
2a8fa600
SJ		 6279 goto out;
6280
6281remove_sdev_boot:
7c48bfd0 6282 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 6283remove_sdev_ufs_device:
6284 scsi_remove_device(hba->sdev_ufs_device);
6285out:
6286 return ret;
6287}
6288
93fdd5ac
TW		 6289static int ufs_get_device_desc(struct ufs_hba *hba,
6290 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG		 6291{
6292 int err;
6293 u8 model_index;
a4b0e8a4
PM		 6294 u8 str_desc_buf[QUERY_DESC_MAX_SIZE + 1] = {0};
6295 u8 desc_buf[hba->desc_size.dev_desc];
c58ab7aa 6296
a4b0e8a4 6297 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
c58ab7aa
YG		 6298 if (err) {
6299 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6300 __func__, err);
6301 goto out;
6302 }
6303
6304 /*
6305 * getting vendor (manufacturerID) and Bank Index in big endian
6306 * format
6307 */
93fdd5ac 6308 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6309 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6310
6311 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6312
6313 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
a4b0e8a4 6314 QUERY_DESC_MAX_SIZE, ASCII_STD);
c58ab7aa
YG		 6315 if (err) {
6316 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6317 __func__, err);
6318 goto out;
6319 }
6320
a4b0e8a4 6321 str_desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
93fdd5ac 6322 strlcpy(dev_desc->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
c58ab7aa
YG		 6323 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
6324 MAX_MODEL_LEN));
6325
6326 /* Null terminate the model string */
93fdd5ac 6327 dev_desc->model[MAX_MODEL_LEN] = '\0';
c58ab7aa
YG		 6328
6329out:
6330 return err;
6331}
6332
93fdd5ac
TW		 6333static void ufs_fixup_device_setup(struct ufs_hba *hba,
6334 struct ufs_dev_desc *dev_desc)
c58ab7aa 6335{
c58ab7aa 6336 struct ufs_dev_fix *f;
c58ab7aa
YG		 6337
6338 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW		 6339 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6340 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6341 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
c58ab7aa
YG		 6342 !strcmp(f->card.model, UFS_ANY_MODEL)))
6343 hba->dev_quirks |= f->quirk;
6344 }
6345}
6346
37113106
YG		 6347/**
6348 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6349 * @hba: per-adapter instance
6350 *
6351 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6352 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6353 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6354 * the hibern8 exit latency.
6355 *
6356 * Returns zero on success, non-zero error value on failure.
6357 */
6358static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6359{
6360 int ret = 0;
6361 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6362
6363 ret = ufshcd_dme_peer_get(hba,
6364 UIC_ARG_MIB_SEL(
6365 RX_MIN_ACTIVATETIME_CAPABILITY,
6366 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6367 &peer_rx_min_activatetime);
6368 if (ret)
6369 goto out;
6370
6371 /* make sure proper unit conversion is applied */
6372 tuned_pa_tactivate =
6373 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6374 / PA_TACTIVATE_TIME_UNIT_US);
6375 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6376 tuned_pa_tactivate);
6377
6378out:
6379 return ret;
6380}
6381
6382/**
6383 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6384 * @hba: per-adapter instance
6385 *
6386 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6387 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6388 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6389 * This optimal value can help reduce the hibern8 exit latency.
6390 *
6391 * Returns zero on success, non-zero error value on failure.
6392 */
6393static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6394{
6395 int ret = 0;
6396 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6397 u32 max_hibern8_time, tuned_pa_hibern8time;
6398
6399 ret = ufshcd_dme_get(hba,
6400 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6401 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6402 &local_tx_hibern8_time_cap);
6403 if (ret)
6404 goto out;
6405
6406 ret = ufshcd_dme_peer_get(hba,
6407 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6408 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6409 &peer_rx_hibern8_time_cap);
6410 if (ret)
6411 goto out;
6412
6413 max_hibern8_time = max(local_tx_hibern8_time_cap,
6414 peer_rx_hibern8_time_cap);
6415 /* make sure proper unit conversion is applied */
6416 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6417 / PA_HIBERN8_TIME_UNIT_US);
6418 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6419 tuned_pa_hibern8time);
6420out:
6421 return ret;
6422}
6423
c6a6db43
SJ		 6424/**
6425 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6426 * less than device PA_TACTIVATE time.
6427 * @hba: per-adapter instance
6428 *
6429 * Some UFS devices require host PA_TACTIVATE to be lower than device
6430 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6431 * for such devices.
6432 *
6433 * Returns zero on success, non-zero error value on failure.
6434 */
6435static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6436{
6437 int ret = 0;
6438 u32 granularity, peer_granularity;
6439 u32 pa_tactivate, peer_pa_tactivate;
6440 u32 pa_tactivate_us, peer_pa_tactivate_us;
6441 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6442
6443 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6444 &granularity);
6445 if (ret)
6446 goto out;
6447
6448 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6449 &peer_granularity);
6450 if (ret)
6451 goto out;
6452
6453 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6454 (granularity > PA_GRANULARITY_MAX_VAL)) {
6455 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6456 __func__, granularity);
6457 return -EINVAL;
6458 }
6459
6460 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6461 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6462 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6463 __func__, peer_granularity);
6464 return -EINVAL;
6465 }
6466
6467 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6468 if (ret)
6469 goto out;
6470
6471 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6472 &peer_pa_tactivate);
6473 if (ret)
6474 goto out;
6475
6476 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6477 peer_pa_tactivate_us = peer_pa_tactivate *
6478 gran_to_us_table[peer_granularity - 1];
6479
6480 if (pa_tactivate_us > peer_pa_tactivate_us) {
6481 u32 new_peer_pa_tactivate;
6482
6483 new_peer_pa_tactivate = pa_tactivate_us /
6484 gran_to_us_table[peer_granularity - 1];
6485 new_peer_pa_tactivate++;
6486 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6487 new_peer_pa_tactivate);
6488 }
6489
6490out:
6491 return ret;
6492}
6493
37113106
YG		 6494static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6495{
6496 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6497 ufshcd_tune_pa_tactivate(hba);
6498 ufshcd_tune_pa_hibern8time(hba);
6499 }
6500
6501 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6502 /* set 1ms timeout for PA_TACTIVATE */
6503 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43
SJ		 6504
6505 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6506 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 6507
6508 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 6509}
6510
ff8e20c6
DR		 6511static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6512{
6513 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6514
6515 hba->ufs_stats.hibern8_exit_cnt = 0;
6516 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6517
6518 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6519 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6520 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6521 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6522 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
7fabb77b
GB		 6523
6524 hba->req_abort_count = 0;
ff8e20c6
DR		 6525}
6526
a4b0e8a4
PM		 6527static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6528{
6529 int err;
6530
6531 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6532 &hba->desc_size.dev_desc);
6533 if (err)
6534 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6535
6536 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6537 &hba->desc_size.pwr_desc);
6538 if (err)
6539 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6540
6541 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6542 &hba->desc_size.interc_desc);
6543 if (err)
6544 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6545
6546 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6547 &hba->desc_size.conf_desc);
6548 if (err)
6549 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6550
6551 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6552 &hba->desc_size.unit_desc);
6553 if (err)
6554 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6555
6556 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6557 &hba->desc_size.geom_desc);
6558 if (err)
6559 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6560}
6561
6562static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
6563{
6564 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6565 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6566 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6567 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6568 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6569 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6570}
6571
6ccf44fe 6572/**
1d337ec2
SRT		 6573 * ufshcd_probe_hba - probe hba to detect device and initialize
6574 * @hba: per-adapter instance
6575 *
6576 * Execute link-startup and verify device initialization
6ccf44fe 6577 */
1d337ec2 6578static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6579{
93fdd5ac 6580 struct ufs_dev_desc card = {0};
623b5fe3 6581 int re_cnt = 0;
6ccf44fe 6582 int ret;
7ff5ab47 6583 ktime_t start = ktime_get();
2bfd4b44 6584 unsigned long flags;
6ccf44fe 6585
623b5fe3 6586retry:
251f4e5f 6587 ret = ufshcd_hba_enable(hba);
6588 if (ret)
6589 goto out;
6590
6ccf44fe 6591 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 6592 if (ret)
6593 goto out;
6594
afdfff59
YG		 6595 /* set the default level for urgent bkops */
6596 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6597 hba->is_urgent_bkops_lvl_checked = false;
6598
ff8e20c6
DR		 6599 /* Debug counters initialization */
6600 ufshcd_clear_dbg_ufs_stats(hba);
6601
57d104c1
SJ		 6602 /* UniPro link is active now */
6603 ufshcd_set_link_active(hba);
d3e89bac 6604
5a0b0cb9
SRT		 6605 ret = ufshcd_verify_dev_init(hba);
6606 if (ret)
6607 goto out;
68078d5c
DR		 6608
6609 ret = ufshcd_complete_dev_init(hba);
6610 if (ret)
6611 goto out;
5a0b0cb9 6612
a4b0e8a4
PM		 6613 /* Init check for device descriptor sizes */
6614 ufshcd_init_desc_sizes(hba);
6615
93fdd5ac
TW		 6616 ret = ufs_get_device_desc(hba, &card);
6617 if (ret) {
6618 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6619 __func__, ret);
6620 goto out;
6621 }
6622
6623 ufs_fixup_device_setup(hba, &card);
37113106 6624 ufshcd_tune_unipro_params(hba);
60f01870
YG		 6625
6626 ret = ufshcd_set_vccq_rail_unused(hba,
6627 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6628 if (ret)
6629 goto out;
6630
57d104c1
SJ		 6631 /* UFS device is also active now */
6632 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6633 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 6634 hba->wlun_dev_clr_ua = true;
6635
7eb584db
DR		 6636 if (ufshcd_get_max_pwr_mode(hba)) {
6637 dev_err(hba->dev,
6638 "%s: Failed getting max supported power mode\n",
6639 __func__);
6640 } else {
6641 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 6642 if (ret) {
7eb584db
DR		 6643 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6644 __func__, ret);
8643ae66
DL		 6645 goto out;
6646 }
7eb584db 6647 }
57d104c1 6648
53c12d0e
YG		 6649 /* set the state as operational after switching to desired gear */
6650 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 6651
57d104c1
SJ		 6652 /*
6653 * If we are in error handling context or in power management callbacks
6654 * context, no need to scan the host
6655 */
6656 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6657 bool flag;
6658
6659 /* clear any previous UFS device information */
6660 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 6661 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6662 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 6663 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 6664
3a4bf06d
YG		 6665 if (!hba->is_init_prefetch)
6666 ufshcd_init_icc_levels(hba);
6667
251f4e5f 6668 scsi_scan_host(hba->host);
6669
2a8fa600 6670 /* Add required well known logical units to scsi mid layer */
251f4e5f 6671 ret = ufshcd_scsi_add_wlus(hba);
6672 if (ret) {
6673 dev_warn(hba->dev, "%s failed to add w-lus %d\n",
6674 __func__, ret);
6675 ret = 0;
6676 }
2a8fa600 6677
0701e49d
SJ		 6678 /* Initialize devfreq after UFS device is detected */
6679 if (ufshcd_is_clkscaling_supported(hba)) {
6680 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6681 &hba->pwr_info,
6682 sizeof(struct ufs_pa_layer_attr));
6683 hba->clk_scaling.saved_pwr_info.is_valid = true;
6684 if (!hba->devfreq) {
6685 hba->devfreq = devm_devfreq_add_device(hba->dev,
6686 &ufs_devfreq_profile,
6687 "simple_ondemand",
6688 NULL);
6689 if (IS_ERR(hba->devfreq)) {
6690 ret = PTR_ERR(hba->devfreq);
6691 dev_err(hba->dev, "Unable to register with devfreq %d\n",
6692 ret);
6693 goto out;
6694 }
6695 }
6696 hba->clk_scaling.is_allowed = true;
6697 }
6698
3441da7d
SRT		 6699 pm_runtime_put_sync(hba->dev);
6700 }
3a4bf06d
YG		 6701
6702 if (!hba->is_init_prefetch)
6703 hba->is_init_prefetch = true;
6704
5a0b0cb9 6705out:
251f4e5f 6706 if (ret && re_cnt++ < UFS_LINK_SETUP_RETRIES) {
6707 dev_err(hba->dev, "%s failed with err %d, retrying:%d\n",
6708 __func__, ret, re_cnt);
623b5fe3 6709 goto retry;
2bfd4b44 6710 spin_lock_irqsave(hba->host->host_lock, flags);
6711 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6712 spin_unlock_irqrestore(hba->host->host_lock, flags);
623b5fe3 6713 }
251f4e5f 6714 }
1d337ec2
SRT		 6715 /*
6716 * If we failed to initialize the device or the device is not
6717 * present, turn off the power/clocks etc.
6718 */
57d104c1
SJ		 6719 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6720 pm_runtime_put_sync(hba->dev);
1d337ec2 6721 ufshcd_hba_exit(hba);
57d104c1 6722 }
1d337ec2 6723
7ff5ab47
SJ		 6724 trace_ufshcd_init(dev_name(hba->dev), ret,
6725 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 6726 hba->curr_dev_pwr_mode, hba->uic_link_state);
1d337ec2
SRT		 6727 return ret;
6728}
6729
6730/**
6731 * ufshcd_async_scan - asynchronous execution for probing hba
6732 * @data: data pointer to pass to this function
6733 * @cookie: cookie data
6734 */
6735static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6736{
6737 struct ufs_hba *hba = (struct ufs_hba *)data;
6738
6739 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 6740}
6741
f550c65b
YG		 6742static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6743{
6744 unsigned long flags;
6745 struct Scsi_Host *host;
6746 struct ufs_hba *hba;
6747 int index;
6748 bool found = false;
6749
6750 if (!scmd || !scmd->device || !scmd->device->host)
6751 return BLK_EH_NOT_HANDLED;
6752
6753 host = scmd->device->host;
6754 hba = shost_priv(host);
6755 if (!hba)
6756 return BLK_EH_NOT_HANDLED;
6757
6758 spin_lock_irqsave(host->host_lock, flags);
6759
6760 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6761 if (hba->lrb[index].cmd == scmd) {
6762 found = true;
6763 break;
6764 }
6765 }
6766
6767 spin_unlock_irqrestore(host->host_lock, flags);
6768
6769 /*
6770 * Bypass SCSI error handling and reset the block layer timer if this
6771 * SCSI command was not actually dispatched to UFS driver, otherwise
6772 * let SCSI layer handle the error as usual.
6773 */
6774 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
6775}
6776
7a3e97b0
SY		 6777static struct scsi_host_template ufshcd_driver_template = {
6778 .module = THIS_MODULE,
6779 .name = UFSHCD,
6780 .proc_name = UFSHCD,
6781 .queuecommand = ufshcd_queuecommand,
6782 .slave_alloc = ufshcd_slave_alloc,
eeda4749 6783 .slave_configure = ufshcd_slave_configure,
7a3e97b0 6784 .slave_destroy = ufshcd_slave_destroy,
4264fd61 6785 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 6786 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 6787 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
6788 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 6789 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 6790 .this_id = -1,
6791 .sg_tablesize = SG_ALL,
6792 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
6793 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 6794 .max_host_blocked = 1,
0f7f11ff 6795 .skip_settle_delay = 1,
c40ecc12 6796 .track_queue_depth = 1,
7a3e97b0
SY		 6797};
6798
57d104c1
SJ		 6799static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
6800 int ua)
6801{
7b16a07c 6802 int ret;
57d104c1 6803
7b16a07c
BA		 6804 if (!vreg)
6805 return 0;
57d104c1 6806
7b16a07c
BA		 6807 ret = regulator_set_load(vreg->reg, ua);
6808 if (ret < 0) {
6809 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
6810 __func__, vreg->name, ua, ret);
57d104c1
SJ		 6811 }
6812
6813 return ret;
6814}
6815
6816static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
6817 struct ufs_vreg *vreg)
6818{
60f01870
YG		 6819 if (!vreg)
6820 return 0;
6821 else if (vreg->unused)
6822 return 0;
6823 else
6824 return ufshcd_config_vreg_load(hba->dev, vreg,
6825 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 6826}
6827
6828static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
6829 struct ufs_vreg *vreg)
6830{
60f01870
YG		 6831 if (!vreg)
6832 return 0;
6833 else if (vreg->unused)
6834 return 0;
6835 else
6836 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 6837}
6838
aa497613
SRT		 6839static int ufshcd_config_vreg(struct device *dev,
6840 struct ufs_vreg *vreg, bool on)
6841{
6842 int ret = 0;
6c27a40c
GS		 6843 struct regulator *reg;
6844 const char *name;
aa497613
SRT		 6845 int min_uV, uA_load;
6846
6847 BUG_ON(!vreg);
6848
6c27a40c
GS		 6849 reg = vreg->reg;
6850 name = vreg->name;
6851
aa497613
SRT		 6852 if (regulator_count_voltages(reg) > 0) {
6853 min_uV = on ? vreg->min_uV : 0;
6854 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
6855 if (ret) {
6856 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
6857 __func__, name, ret);
6858 goto out;
6859 }
6860
6861 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 6862 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
6863 if (ret)
aa497613 6864 goto out;
aa497613
SRT		 6865 }
6866out:
6867 return ret;
6868}
6869
6870static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
6871{
6872 int ret = 0;
6873
60f01870
YG		 6874 if (!vreg)
6875 goto out;
6876 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 6877 goto out;
6878
6879 ret = ufshcd_config_vreg(dev, vreg, true);
6880 if (!ret)
6881 ret = regulator_enable(vreg->reg);
6882
6883 if (!ret)
6884 vreg->enabled = true;
6885 else
6886 dev_err(dev, "%s: %s enable failed, err=%d\n",
6887 __func__, vreg->name, ret);
6888out:
6889 return ret;
6890}
6891
6892static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
6893{
6894 int ret = 0;
6895
60f01870
YG		 6896 if (!vreg)
6897 goto out;
6898 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 6899 goto out;
6900
6901 ret = regulator_disable(vreg->reg);
6902
6903 if (!ret) {
6904 /* ignore errors on applying disable config */
6905 ufshcd_config_vreg(dev, vreg, false);
6906 vreg->enabled = false;
6907 } else {
6908 dev_err(dev, "%s: %s disable failed, err=%d\n",
6909 __func__, vreg->name, ret);
6910 }
6911out:
6912 return ret;
6913}
6914
6915static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
6916{
6917 int ret = 0;
6918 struct device *dev = hba->dev;
6919 struct ufs_vreg_info *info = &hba->vreg_info;
6920
6921 if (!info)
6922 goto out;
6923
6924 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
6925 if (ret)
6926 goto out;
6927
6928 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
6929 if (ret)
6930 goto out;
6931
6932 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
6933 if (ret)
6934 goto out;
6935
6936out:
6937 if (ret) {
6938 ufshcd_toggle_vreg(dev, info->vccq2, false);
6939 ufshcd_toggle_vreg(dev, info->vccq, false);
6940 ufshcd_toggle_vreg(dev, info->vcc, false);
6941 }
6942 return ret;
6943}
6944
6a771a65
RS		 6945static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
6946{
6947 struct ufs_vreg_info *info = &hba->vreg_info;
6948
6949 if (info)
6950 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
6951
6952 return 0;
6953}
6954
aa497613
SRT		 6955static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
6956{
6957 int ret = 0;
6958
6959 if (!vreg)
6960 goto out;
6961
6962 vreg->reg = devm_regulator_get(dev, vreg->name);
6963 if (IS_ERR(vreg->reg)) {
6964 ret = PTR_ERR(vreg->reg);
6965 dev_err(dev, "%s: %s get failed, err=%d\n",
6966 __func__, vreg->name, ret);
6967 }
6968out:
6969 return ret;
6970}
6971
6972static int ufshcd_init_vreg(struct ufs_hba *hba)
6973{
6974 int ret = 0;
6975 struct device *dev = hba->dev;
6976 struct ufs_vreg_info *info = &hba->vreg_info;
6977
6978 if (!info)
6979 goto out;
6980
6981 ret = ufshcd_get_vreg(dev, info->vcc);
6982 if (ret)
6983 goto out;
6984
6985 ret = ufshcd_get_vreg(dev, info->vccq);
6986 if (ret)
6987 goto out;
6988
6989 ret = ufshcd_get_vreg(dev, info->vccq2);
6990out:
6991 return ret;
6992}
6993
6a771a65
RS		 6994static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
6995{
6996 struct ufs_vreg_info *info = &hba->vreg_info;
6997
6998 if (info)
6999 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7000
7001 return 0;
7002}
7003
60f01870
YG		 7004static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
7005{
7006 int ret = 0;
7007 struct ufs_vreg_info *info = &hba->vreg_info;
7008
7009 if (!info)
7010 goto out;
7011 else if (!info->vccq)
7012 goto out;
7013
7014 if (unused) {
7015 /* shut off the rail here */
7016 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
7017 /*
7018 * Mark this rail as no longer used, so it doesn't get enabled
7019 * later by mistake
7020 */
7021 if (!ret)
7022 info->vccq->unused = true;
7023 } else {
7024 /*
7025 * rail should have been already enabled hence just make sure
7026 * that unused flag is cleared.
7027 */
7028 info->vccq->unused = false;
7029 }
7030out:
7031 return ret;
7032}
7033
57d104c1
SJ		 7034static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7035 bool skip_ref_clk)
c6e79dac
SRT		 7036{
7037 int ret = 0;
7038 struct ufs_clk_info *clki;
7039 struct list_head *head = &hba->clk_list_head;
8214b377 7040 const char *ref_clk = "ref_clk";
1ab27c9c 7041 unsigned long flags;
911a0771
SJ		 7042 ktime_t start = ktime_get();
7043 bool clk_state_changed = false;
c6e79dac 7044
566ec9ad 7045 if (list_empty(head))
c6e79dac
SRT		 7046 goto out;
7047
1e879e8f
SJ		 7048 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
7049 if (ret)
7050 return ret;
7051
c6e79dac
SRT		 7052 list_for_each_entry(clki, head, list) {
7053 if (!IS_ERR_OR_NULL(clki->clk)) {
8214b377 7054 if (skip_ref_clk &&
7055 !strncmp(clki->name, ref_clk, strlen(ref_clk)))
57d104c1
SJ		 7056 continue;
7057
911a0771 7058 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 7059 if (on && !clki->enabled) {
7060 ret = clk_prepare_enable(clki->clk);
7061 if (ret) {
7062 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7063 __func__, clki->name, ret);
7064 goto out;
7065 }
7066 } else if (!on && clki->enabled) {
7067 clk_disable_unprepare(clki->clk);
7068 }
7069 clki->enabled = on;
7070 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7071 clki->name, on ? "en" : "dis");
7072 }
7073 }
1ab27c9c 7074
1e879e8f
SJ		 7075 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7076 if (ret)
7077 return ret;
7078
c6e79dac
SRT		 7079out:
7080 if (ret) {
7081 list_for_each_entry(clki, head, list) {
7082 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7083 clk_disable_unprepare(clki->clk);
7084 }
7ff5ab47 7085 } else if (!ret && on) {
1ab27c9c
ST		 7086 spin_lock_irqsave(hba->host->host_lock, flags);
7087 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 7088 trace_ufshcd_clk_gating(dev_name(hba->dev),
7089 hba->clk_gating.state);
1ab27c9c 7090 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 7091 }
7ff5ab47 7092
911a0771
SJ		 7093 if (clk_state_changed)
7094 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7095 (on ? "on" : "off"),
7096 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 7097 return ret;
7098}
7099
57d104c1
SJ		 7100static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7101{
7102 return __ufshcd_setup_clocks(hba, on, false);
7103}
7104
c6e79dac
SRT		 7105static int ufshcd_init_clocks(struct ufs_hba *hba)
7106{
7107 int ret = 0;
7108 struct ufs_clk_info *clki;
7109 struct device *dev = hba->dev;
7110 struct list_head *head = &hba->clk_list_head;
7111
566ec9ad 7112 if (list_empty(head))
c6e79dac
SRT		 7113 goto out;
7114
7115 list_for_each_entry(clki, head, list) {
7116 if (!clki->name)
7117 continue;
7118
7119 clki->clk = devm_clk_get(dev, clki->name);
7120 if (IS_ERR(clki->clk)) {
7121 ret = PTR_ERR(clki->clk);
7122 dev_err(dev, "%s: %s clk get failed, %d\n",
7123 __func__, clki->name, ret);
7124 goto out;
7125 }
7126
7127 if (clki->max_freq) {
7128 ret = clk_set_rate(clki->clk, clki->max_freq);
7129 if (ret) {
7130 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7131 __func__, clki->name,
7132 clki->max_freq, ret);
7133 goto out;
7134 }
856b3483 7135 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 7136 }
7137 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7138 clki->name, clk_get_rate(clki->clk));
7139 }
7140out:
7141 return ret;
7142}
7143
5c0c28a8
SRT		 7144static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7145{
7146 int err = 0;
7147
7148 if (!hba->vops)
7149 goto out;
7150
0263bcd0
YG		 7151 err = ufshcd_vops_init(hba);
7152 if (err)
7153 goto out;
5c0c28a8 7154
0263bcd0
YG		 7155 err = ufshcd_vops_setup_regulators(hba, true);
7156 if (err)
7157 goto out_exit;
5c0c28a8
SRT		 7158
7159 goto out;
7160
5c0c28a8 7161out_exit:
0263bcd0 7162 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7163out:
7164 if (err)
7165 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 7166 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 7167 return err;
7168}
7169
7170static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7171{
7172 if (!hba->vops)
7173 return;
7174
0263bcd0 7175 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 7176
0263bcd0 7177 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7178}
7179
aa497613
SRT		 7180static int ufshcd_hba_init(struct ufs_hba *hba)
7181{
7182 int err;
7183
6a771a65
RS		 7184 /*
7185 * Handle host controller power separately from the UFS device power
7186 * rails as it will help controlling the UFS host controller power
7187 * collapse easily which is different than UFS device power collapse.
7188 * Also, enable the host controller power before we go ahead with rest
7189 * of the initialization here.
7190 */
7191 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 7192 if (err)
7193 goto out;
7194
6a771a65 7195 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 7196 if (err)
7197 goto out;
7198
6a771a65
RS		 7199 err = ufshcd_init_clocks(hba);
7200 if (err)
7201 goto out_disable_hba_vreg;
7202
7203 err = ufshcd_setup_clocks(hba, true);
7204 if (err)
7205 goto out_disable_hba_vreg;
7206
c6e79dac
SRT		 7207 err = ufshcd_init_vreg(hba);
7208 if (err)
7209 goto out_disable_clks;
7210
7211 err = ufshcd_setup_vreg(hba, true);
7212 if (err)
7213 goto out_disable_clks;
7214
aa497613
SRT		 7215 err = ufshcd_variant_hba_init(hba);
7216 if (err)
7217 goto out_disable_vreg;
7218
1d337ec2 7219 hba->is_powered = true;
aa497613
SRT		 7220 goto out;
7221
7222out_disable_vreg:
7223 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 7224out_disable_clks:
7225 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 7226out_disable_hba_vreg:
7227 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 7228out:
7229 return err;
7230}
7231
7232static void ufshcd_hba_exit(struct ufs_hba *hba)
7233{
1d337ec2
SRT		 7234 if (hba->is_powered) {
7235 ufshcd_variant_hba_exit(hba);
7236 ufshcd_setup_vreg(hba, false);
a508253d 7237 ufshcd_suspend_clkscaling(hba);
401f1e44 7238 if (ufshcd_is_clkscaling_supported(hba)) {
0701e49d
SJ		 7239 if (hba->devfreq)
7240 ufshcd_suspend_clkscaling(hba);
401f1e44
SJ		 7241 destroy_workqueue(hba->clk_scaling.workq);
7242 }
1d337ec2
SRT		 7243 ufshcd_setup_clocks(hba, false);
7244 ufshcd_setup_hba_vreg(hba, false);
7245 hba->is_powered = false;
7246 }
aa497613
SRT		 7247}
7248
57d104c1
SJ		 7249static int
7250ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7251{
7252 unsigned char cmd[6] = {REQUEST_SENSE,
7253 0,
7254 0,
7255 0,
dcea0bfb 7256 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 7257 0};
7258 char *buffer;
7259 int ret;
7260
dcea0bfb 7261 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 7262 if (!buffer) {
7263 ret = -ENOMEM;
7264 goto out;
7265 }
7266
fcbfffe2
CH		 7267 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
7268 UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
7269 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 7270 if (ret)
7271 pr_err("%s: failed with err %d\n", __func__, ret);
7272
7273 kfree(buffer);
7274out:
7275 return ret;
7276}
7277
7278/**
7279 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
7280 * power mode
7281 * @hba: per adapter instance
7282 * @pwr_mode: device power mode to set
7283 *
7284 * Returns 0 if requested power mode is set successfully
7285 * Returns non-zero if failed to set the requested power mode
7286 */
7287static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7288 enum ufs_dev_pwr_mode pwr_mode)
7289{
7290 unsigned char cmd[6] = { START_STOP };
7291 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7292 struct scsi_device *sdp;
7293 unsigned long flags;
57d104c1
SJ		 7294 int ret;
7295
7c48bfd0
AM		 7296 spin_lock_irqsave(hba->host->host_lock, flags);
7297 sdp = hba->sdev_ufs_device;
7298 if (sdp) {
7299 ret = scsi_device_get(sdp);
7300 if (!ret && !scsi_device_online(sdp)) {
7301 ret = -ENODEV;
7302 scsi_device_put(sdp);
7303 }
7304 } else {
7305 ret = -ENODEV;
7306 }
7307 spin_unlock_irqrestore(hba->host->host_lock, flags);
7308
7309 if (ret)
7310 return ret;
57d104c1
SJ		 7311
7312 /*
7313 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7314 * handling, which would wait for host to be resumed. Since we know
7315 * we are functional while we are here, skip host resume in error
7316 * handling context.
7317 */
7318 hba->host->eh_noresume = 1;
7319 if (hba->wlun_dev_clr_ua) {
7320 ret = ufshcd_send_request_sense(hba, sdp);
7321 if (ret)
7322 goto out;
7323 /* Unit attention condition is cleared now */
7324 hba->wlun_dev_clr_ua = false;
7325 }
7326
7327 cmd[4] = pwr_mode << 4;
7328
7329 /*
7330 * Current function would be generally called from the power management
e8064021 7331 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7332 * already suspended childs.
7333 */
fcbfffe2
CH		 7334 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7335 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7336 if (ret) {
7337 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7338 "START_STOP failed for power mode: %d, result %x\n",
7339 pwr_mode, ret);
21045519
HR		 7340 if (driver_byte(ret) & DRIVER_SENSE)
7341 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7342 }
7343
7344 if (!ret)
7345 hba->curr_dev_pwr_mode = pwr_mode;
7346out:
7c48bfd0 7347 scsi_device_put(sdp);
57d104c1
SJ		 7348 hba->host->eh_noresume = 0;
7349 return ret;
7350}
7351
7352static int ufshcd_link_state_transition(struct ufs_hba *hba,
7353 enum uic_link_state req_link_state,
7354 int check_for_bkops)
7355{
7356 int ret = 0;
7357
7358 if (req_link_state == hba->uic_link_state)
7359 return 0;
7360
7361 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
5801290e 7362 ufshcd_set_link_trans_hibern8(hba);
0f7f11ff 7363 ret = ufshcd_link_hibern8_ctrl(hba, true);
57d104c1
SJ		 7364 if (!ret)
7365 ufshcd_set_link_hibern8(hba);
5801290e 7366 else {
40e137af 7367 unsigned long flags;
7368 bool saved_is_suspended = hba->clk_gating.is_suspended;
7369
7370 spin_lock_irqsave(hba->host->host_lock, flags);
7371 hba->clk_gating.state = __CLKS_ON;
7372 spin_unlock_irqrestore(hba->host->host_lock, flags);
7373
7374 hba->clk_gating.is_suspended = true;
66a35665 7375 ufshcd_host_reset_and_restore(hba);
40e137af 7376 spin_lock_irqsave(hba->host->host_lock, flags);
7377 hba->clk_gating.state = CLKS_ON;
7378 spin_unlock_irqrestore(hba->host->host_lock, flags);
7379 hba->clk_gating.is_suspended = saved_is_suspended;
7380
57d104c1
SJ		 7381 goto out;
7382 }
7383 /*
7384 * If autobkops is enabled, link can't be turned off because
7385 * turning off the link would also turn off the device.
7386 */
7387 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
7388 (!check_for_bkops || (check_for_bkops &&
7389 !hba->auto_bkops_enabled))) {
f3099fbd
YG		 7390 /*
7391 * Let's make sure that link is in low power mode, we are doing
7392 * this currently by putting the link in Hibern8. Otherway to
7393 * put the link in low power mode is to send the DME end point
7394 * to device and then send the DME reset command to local
7395 * unipro. But putting the link in hibern8 is much faster.
7396 */
7397 ret = ufshcd_uic_hibern8_enter(hba);
7398 if (ret)
7399 goto out;
57d104c1
SJ		 7400 /*
7401 * Change controller state to "reset state" which
7402 * should also put the link in off/reset state
7403 */
2bfd4b44 7404 spin_lock_irqsave(hba->host->host_lock, flags);
7405 hba->ufshcd_state = UFSHCD_STATE_RESET;
7406 ufshcd_hba_stop(hba, true);
7407 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 7408 /*
7409 * TODO: Check if we need any delay to make sure that
7410 * controller is reset
7411 */
7412 ufshcd_set_link_off(hba);
7413 }
7414
7415out:
7416 return ret;
7417}
7418
7419static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7420{
b799fdf7
YG		 7421 /*
7422 * It seems some UFS devices may keep drawing more than sleep current
7423 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7424 * To avoid this situation, add 2ms delay before putting these UFS
7425 * rails in LPM mode.
7426 */
7427 if (!ufshcd_is_link_active(hba) &&
7428 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7429 usleep_range(2000, 2100);
7430
57d104c1
SJ		 7431 /*
7432 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7433 * power.
7434 *
7435 * If UFS device and link is in OFF state, all power supplies (VCC,
7436 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7437 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7438 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7439 *
7440 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7441 * in low power state which would save some power.
7442 */
7443 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7444 !hba->dev_info.is_lu_power_on_wp) {
7445 ufshcd_setup_vreg(hba, false);
7446 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7447 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7448 if (!ufshcd_is_link_active(hba)) {
7449 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7450 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7451 }
7452 }
7453}
7454
7455static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7456{
7457 int ret = 0;
7458
7459 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7460 !hba->dev_info.is_lu_power_on_wp) {
7461 ret = ufshcd_setup_vreg(hba, true);
7462 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7463 if (!ret && !ufshcd_is_link_active(hba)) {
7464 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7465 if (ret)
7466 goto vcc_disable;
7467 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7468 if (ret)
7469 goto vccq_lpm;
7470 }
69d72ac8 7471 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7472 }
7473 goto out;
7474
7475vccq_lpm:
7476 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7477vcc_disable:
7478 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7479out:
7480 return ret;
7481}
7482
7483static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7484{
7485 if (ufshcd_is_link_off(hba))
7486 ufshcd_setup_hba_vreg(hba, false);
7487}
7488
7489static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7490{
7491 if (ufshcd_is_link_off(hba))
7492 ufshcd_setup_hba_vreg(hba, true);
7493}
7494
7a3e97b0 7495/**
57d104c1 7496 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7497 * @hba: per adapter instance
57d104c1
SJ		 7498 * @pm_op: desired low power operation type
7499 *
7500 * This function will try to put the UFS device and link into low power
7501 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7502 * (System PM level).
7503 *
7504 * If this function is called during shutdown, it will make sure that
7505 * both UFS device and UFS link is powered off.
7a3e97b0 7506 *
57d104c1
SJ		 7507 * NOTE: UFS device & link must be active before we enter in this function.
7508 *
7509 * Returns 0 for success and non-zero for failure
7a3e97b0 7510 */
57d104c1 7511static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7512{
57d104c1
SJ		 7513 int ret = 0;
7514 enum ufs_pm_level pm_lvl;
7515 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7516 enum uic_link_state req_link_state;
5801290e 7517 bool gating_allowed = !ufshcd_can_fake_clkgating(hba);
57d104c1
SJ		 7518
7519 hba->pm_op_in_progress = 1;
7520 if (!ufshcd_is_shutdown_pm(pm_op)) {
7521 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7522 hba->rpm_lvl : hba->spm_lvl;
7523 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7524 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7525 } else {
7526 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7527 req_link_state = UIC_LINK_OFF_STATE;
7528 }
7529
7a3e97b0 7530 /*
57d104c1
SJ		 7531 * If we can't transition into any of the low power modes
7532 * just gate the clocks.
7a3e97b0 7533 */
1ab27c9c
ST		 7534 ufshcd_hold(hba, false);
7535 hba->clk_gating.is_suspended = true;
7536
401f1e44
SJ		 7537 if (hba->clk_scaling.is_allowed) {
7538 cancel_work_sync(&hba->clk_scaling.suspend_work);
7539 cancel_work_sync(&hba->clk_scaling.resume_work);
7540 ufshcd_suspend_clkscaling(hba);
7541 }
d6fcf81a 7542
57d104c1
SJ		 7543 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7544 req_link_state == UIC_LINK_ACTIVE_STATE) {
7545 goto disable_clks;
7546 }
7a3e97b0 7547
57d104c1
SJ		 7548 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7549 (req_link_state == hba->uic_link_state))
d6fcf81a 7550 goto enable_gating;
57d104c1
SJ		 7551
7552 /* UFS device & link must be active before we enter in this function */
7553 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
7554 ret = -EINVAL;
d6fcf81a 7555 goto enable_gating;
57d104c1
SJ		 7556 }
7557
7558 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 7559 if (ufshcd_can_autobkops_during_suspend(hba)) {
7560 /*
7561 * The device is idle with no requests in the queue,
7562 * allow background operations if bkops status shows
7563 * that performance might be impacted.
7564 */
7565 ret = ufshcd_urgent_bkops(hba);
7566 if (ret)
7567 goto enable_gating;
7568 } else {
7569 /* make sure that auto bkops is disabled */
7570 ufshcd_disable_auto_bkops(hba);
7571 }
57d104c1
SJ		 7572 }
7573
7574 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
7575 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
7576 !ufshcd_is_runtime_pm(pm_op))) {
7577 /* ensure that bkops is disabled */
7578 ufshcd_disable_auto_bkops(hba);
7579 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
7580 if (ret)
1ab27c9c 7581 goto enable_gating;
57d104c1
SJ		 7582 }
7583
7584 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
7585 if (ret)
7586 goto set_dev_active;
7587
57d104c1 7588disable_clks:
0f7f11ff 7589
7590 /*
7591 * Flush pending works before clock is disabled
7592 */
7593 cancel_work_sync(&hba->eh_work);
7594 cancel_work_sync(&hba->eeh_work);
7595
57d104c1 7596 /*
8214b377 7597 * Disable the host irq as host controller as there won't be any
7598 * host controller trasanction expected till resume.
57d104c1 7599 */
8214b377 7600 ufshcd_disable_irq(hba);
7601
57d104c1 7602
5801290e 7603 if (gating_allowed) {
7604 if (!ufshcd_is_link_active(hba))
7605 ufshcd_setup_clocks(hba, false);
7606 else
7607 /* If link is active, device ref_clk can't be switched off */
7608 __ufshcd_setup_clocks(hba, false, true);
7609 }
57d104c1 7610
1ab27c9c 7611 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 7612 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1 7613 /*
8214b377 7614 * Call vendor specific suspend callback. As these callbacks may access
7615 * vendor specific host controller register space call them before the
7616 * host clocks are ON.
57d104c1 7617 */
8214b377 7618 ret = ufshcd_vops_suspend(hba, pm_op);
7619 if (ret)
7620 goto set_link_active;
7621
7622
57d104c1
SJ		 7623 /* Put the host controller in low power mode if possible */
7624 ufshcd_hba_vreg_set_lpm(hba);
7625 goto out;
7626
57d104c1 7627set_link_active:
401f1e44
SJ		 7628 if (hba->clk_scaling.is_allowed)
7629 ufshcd_resume_clkscaling(hba);
5801290e 7630 if (ufshcd_is_link_hibern8(hba)) {
7631 ufshcd_set_link_trans_active(hba);
7632 if (!ufshcd_link_hibern8_ctrl(hba, false))
7633 ufshcd_set_link_active(hba);
7634 else
7635 ufshcd_set_link_off(hba);
7636 } else if (ufshcd_is_link_off(hba))
57d104c1
SJ		 7637 ufshcd_host_reset_and_restore(hba);
7638set_dev_active:
7639 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
7640 ufshcd_disable_auto_bkops(hba);
1ab27c9c 7641enable_gating:
401f1e44
SJ		 7642 if (hba->clk_scaling.is_allowed)
7643 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 7644 hba->clk_gating.is_suspended = false;
7645 ufshcd_release(hba);
57d104c1
SJ		 7646out:
7647 hba->pm_op_in_progress = 0;
7648 return ret;
7a3e97b0
SY		 7649}
7650
7651/**
57d104c1 7652 * ufshcd_resume - helper function for resume operations
3b1d0580 7653 * @hba: per adapter instance
57d104c1 7654 * @pm_op: runtime PM or system PM
7a3e97b0 7655 *
57d104c1
SJ		 7656 * This function basically brings the UFS device, UniPro link and controller
7657 * to active state.
7658 *
7659 * Returns 0 for success and non-zero for failure
7a3e97b0 7660 */
57d104c1 7661static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7662{
57d104c1
SJ		 7663 int ret;
7664 enum uic_link_state old_link_state;
3bc47bcc 7665 enum ufs_pm_level pm_lvl;
5801290e 7666 bool gating_allowed = !ufshcd_can_fake_clkgating(hba);
57d104c1
SJ		 7667
7668 hba->pm_op_in_progress = 1;
3bc47bcc 7669 if (ufshcd_is_system_pm(pm_op))
7670 pm_lvl = hba->spm_lvl;
7671 else
7672 pm_lvl = hba->rpm_lvl;
7673
7674 if (ufs_get_pm_lvl_to_link_pwr_state(pm_lvl) == UIC_LINK_OFF_STATE)
7675 hba->uic_link_state = UIC_LINK_OFF_STATE;
57d104c1
SJ		 7676 old_link_state = hba->uic_link_state;
7677
7678 ufshcd_hba_vreg_set_hpm(hba);
5801290e 7679
57d104c1 7680
57d104c1
SJ		 7681 /* enable the host irq as host controller would be active soon */
7682 ret = ufshcd_enable_irq(hba);
7683 if (ret)
7684 goto disable_irq_and_vops_clks;
7685
7686 ret = ufshcd_vreg_set_hpm(hba);
7687 if (ret)
7688 goto disable_irq_and_vops_clks;
7689
7a3e97b0 7690 /*
57d104c1
SJ		 7691 * Call vendor specific resume callback. As these callbacks may access
7692 * vendor specific host controller register space call them when the
7693 * host clocks are ON.
7a3e97b0 7694 */
0263bcd0
YG		 7695 ret = ufshcd_vops_resume(hba, pm_op);
7696 if (ret)
7697 goto disable_vreg;
57d104c1 7698
5801290e 7699 if (gating_allowed) {
7700 /* Make sure clocks are enabled before accessing controller */
7701 ret = ufshcd_setup_clocks(hba, true);
7702 if (ret)
7703 goto disable_vreg;
7704 }
57d104c1 7705 if (ufshcd_is_link_hibern8(hba)) {
5801290e 7706 ufshcd_set_link_trans_active(hba);
0f7f11ff 7707 ret = ufshcd_link_hibern8_ctrl(hba, false);
57d104c1
SJ		 7708 if (!ret)
7709 ufshcd_set_link_active(hba);
5801290e 7710 else {
7711 ufshcd_set_link_off(hba);
57d104c1 7712 goto vendor_suspend;
5801290e 7713 }
57d104c1
SJ		 7714 } else if (ufshcd_is_link_off(hba)) {
7715 ret = ufshcd_host_reset_and_restore(hba);
7716 /*
7717 * ufshcd_host_reset_and_restore() should have already
7718 * set the link state as active
7719 */
7720 if (ret || !ufshcd_is_link_active(hba))
7721 goto vendor_suspend;
7722 }
7723
7724 if (!ufshcd_is_ufs_dev_active(hba)) {
7725 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
7726 if (ret)
7727 goto set_old_link_state;
7728 }
7729
4e768e76
SJ		 7730 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
7731 ufshcd_enable_auto_bkops(hba);
7732 else
7733 /*
7734 * If BKOPs operations are urgently needed at this moment then
7735 * keep auto-bkops enabled or else disable it.
7736 */
7737 ufshcd_urgent_bkops(hba);
7738
1ab27c9c
ST		 7739 hba->clk_gating.is_suspended = false;
7740
fcb0c4b0
ST		 7741 if (hba->clk_scaling.is_allowed)
7742 ufshcd_resume_clkscaling(hba);
856b3483 7743
1ab27c9c
ST		 7744 /* Schedule clock gating in case of no access to UFS device yet */
7745 ufshcd_release(hba);
57d104c1
SJ		 7746 goto out;
7747
7748set_old_link_state:
7749 ufshcd_link_state_transition(hba, old_link_state, 0);
7750vendor_suspend:
0263bcd0 7751 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 7752disable_vreg:
7753 ufshcd_vreg_set_lpm(hba);
7754disable_irq_and_vops_clks:
7755 ufshcd_disable_irq(hba);
401f1e44
SJ		 7756 if (hba->clk_scaling.is_allowed)
7757 ufshcd_suspend_clkscaling(hba);
57d104c1
SJ		 7758 ufshcd_setup_clocks(hba, false);
7759out:
7760 hba->pm_op_in_progress = 0;
7761 return ret;
7762}
7763
7764/**
7765 * ufshcd_system_suspend - system suspend routine
7766 * @hba: per adapter instance
7767 * @pm_op: runtime PM or system PM
7768 *
7769 * Check the description of ufshcd_suspend() function for more details.
7770 *
7771 * Returns 0 for success and non-zero for failure
7772 */
7773int ufshcd_system_suspend(struct ufs_hba *hba)
7774{
7775 int ret = 0;
7ff5ab47 7776 ktime_t start = ktime_get();
57d104c1
SJ		 7777
7778 if (!hba || !hba->is_powered)
233b594b 7779 return 0;
57d104c1 7780
0b257734
SJ		 7781 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
7782 hba->curr_dev_pwr_mode) &&
7783 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
7784 hba->uic_link_state))
7785 goto out;
57d104c1 7786
0b257734 7787 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 7788 /*
7789 * UFS device and/or UFS link low power states during runtime
7790 * suspend seems to be different than what is expected during
7791 * system suspend. Hence runtime resume the devic & link and
7792 * let the system suspend low power states to take effect.
7793 * TODO: If resume takes longer time, we might have optimize
7794 * it in future by not resuming everything if possible.
7795 */
7796 ret = ufshcd_runtime_resume(hba);
7797 if (ret)
7798 goto out;
7799 }
7800
7801 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
7802out:
7ff5ab47
SJ		 7803 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
7804 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7805 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 7806 if (!ret)
7807 hba->is_sys_suspended = true;
57d104c1
SJ		 7808 return ret;
7809}
7810EXPORT_SYMBOL(ufshcd_system_suspend);
7811
7812/**
7813 * ufshcd_system_resume - system resume routine
7814 * @hba: per adapter instance
7815 *
7816 * Returns 0 for success and non-zero for failure
7817 */
7a3e97b0 7818
57d104c1
SJ		 7819int ufshcd_system_resume(struct ufs_hba *hba)
7820{
7ff5ab47
SJ		 7821 int ret = 0;
7822 ktime_t start = ktime_get();
7823
e3ce73d6
YG		 7824 if (!hba)
7825 return -EINVAL;
7826
7827 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 7828 /*
7829 * Let the runtime resume take care of resuming
7830 * if runtime suspended.
7831 */
7ff5ab47
SJ		 7832 goto out;
7833 else
7834 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
7835out:
7836 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
7837 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7838 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7839 return ret;
7a3e97b0 7840}
57d104c1 7841EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 7842
57d104c1
SJ		 7843/**
7844 * ufshcd_runtime_suspend - runtime suspend routine
7845 * @hba: per adapter instance
7846 *
7847 * Check the description of ufshcd_suspend() function for more details.
7848 *
7849 * Returns 0 for success and non-zero for failure
7850 */
66ec6d59
SRT		 7851int ufshcd_runtime_suspend(struct ufs_hba *hba)
7852{
7ff5ab47
SJ		 7853 int ret = 0;
7854 ktime_t start = ktime_get();
7855
e3ce73d6
YG		 7856 if (!hba)
7857 return -EINVAL;
7858
7859 if (!hba->is_powered)
7ff5ab47
SJ		 7860 goto out;
7861 else
7862 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
7863out:
7864 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
7865 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7866 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7867 return ret;
66ec6d59
SRT		 7868}
7869EXPORT_SYMBOL(ufshcd_runtime_suspend);
7870
57d104c1
SJ		 7871/**
7872 * ufshcd_runtime_resume - runtime resume routine
7873 * @hba: per adapter instance
7874 *
7875 * This function basically brings the UFS device, UniPro link and controller
7876 * to active state. Following operations are done in this function:
7877 *
7878 * 1. Turn on all the controller related clocks
7879 * 2. Bring the UniPro link out of Hibernate state
7880 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
7881 * to active state.
7882 * 4. If auto-bkops is enabled on the device, disable it.
7883 *
7884 * So following would be the possible power state after this function return
7885 * successfully:
7886 * S1: UFS device in Active state with VCC rail ON
7887 * UniPro link in Active state
7888 * All the UFS/UniPro controller clocks are ON
7889 *
7890 * Returns 0 for success and non-zero for failure
7891 */
66ec6d59
SRT		 7892int ufshcd_runtime_resume(struct ufs_hba *hba)
7893{
7ff5ab47
SJ		 7894 int ret = 0;
7895 ktime_t start = ktime_get();
7896
e3ce73d6
YG		 7897 if (!hba)
7898 return -EINVAL;
7899
7900 if (!hba->is_powered)
7ff5ab47
SJ		 7901 goto out;
7902 else
7903 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
7904out:
7905 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
7906 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 7907 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 7908 return ret;
66ec6d59
SRT		 7909}
7910EXPORT_SYMBOL(ufshcd_runtime_resume);
7911
7912int ufshcd_runtime_idle(struct ufs_hba *hba)
7913{
7914 return 0;
7915}
7916EXPORT_SYMBOL(ufshcd_runtime_idle);
7917
09690d5a
SJ		 7918static inline ssize_t ufshcd_pm_lvl_store(struct device *dev,
7919 struct device_attribute *attr,
7920 const char *buf, size_t count,
7921 bool rpm)
7922{
7923 struct ufs_hba *hba = dev_get_drvdata(dev);
7924 unsigned long flags, value;
7925
7926 if (kstrtoul(buf, 0, &value))
7927 return -EINVAL;
7928
949d7fa1 7929 if (value >= UFS_PM_LVL_MAX)
09690d5a
SJ		 7930 return -EINVAL;
7931
7932 spin_lock_irqsave(hba->host->host_lock, flags);
7933 if (rpm)
7934 hba->rpm_lvl = value;
7935 else
7936 hba->spm_lvl = value;
7937 spin_unlock_irqrestore(hba->host->host_lock, flags);
7938 return count;
7939}
7940
7941static ssize_t ufshcd_rpm_lvl_show(struct device *dev,
7942 struct device_attribute *attr, char *buf)
7943{
7944 struct ufs_hba *hba = dev_get_drvdata(dev);
7945 int curr_len;
7946 u8 lvl;
7947
7948 curr_len = snprintf(buf, PAGE_SIZE,
7949 "\nCurrent Runtime PM level [%d] => dev_state [%s] link_state [%s]\n",
7950 hba->rpm_lvl,
7951 ufschd_ufs_dev_pwr_mode_to_string(
7952 ufs_pm_lvl_states[hba->rpm_lvl].dev_state),
7953 ufschd_uic_link_state_to_string(
7954 ufs_pm_lvl_states[hba->rpm_lvl].link_state));
7955
7956 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7957 "\nAll available Runtime PM levels info:\n");
7958 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
7959 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
7960 "\tRuntime PM level [%d] => dev_state [%s] link_state [%s]\n",
7961 lvl,
7962 ufschd_ufs_dev_pwr_mode_to_string(
7963 ufs_pm_lvl_states[lvl].dev_state),
7964 ufschd_uic_link_state_to_string(
7965 ufs_pm_lvl_states[lvl].link_state));
7966
7967 return curr_len;
7968}
7969
7970static ssize_t ufshcd_rpm_lvl_store(struct device *dev,
7971 struct device_attribute *attr, const char *buf, size_t count)
7972{
7973 return ufshcd_pm_lvl_store(dev, attr, buf, count, true);
7974}
7975
7976static void ufshcd_add_rpm_lvl_sysfs_nodes(struct ufs_hba *hba)
7977{
7978 hba->rpm_lvl_attr.show = ufshcd_rpm_lvl_show;
7979 hba->rpm_lvl_attr.store = ufshcd_rpm_lvl_store;
7980 sysfs_attr_init(&hba->rpm_lvl_attr.attr);
7981 hba->rpm_lvl_attr.attr.name = "rpm_lvl";
7982 hba->rpm_lvl_attr.attr.mode = 0644;
7983 if (device_create_file(hba->dev, &hba->rpm_lvl_attr))
7984 dev_err(hba->dev, "Failed to create sysfs for rpm_lvl\n");
7985}
7986
7987static ssize_t ufshcd_spm_lvl_show(struct device *dev,
7988 struct device_attribute *attr, char *buf)
7989{
7990 struct ufs_hba *hba = dev_get_drvdata(dev);
7991 int curr_len;
7992 u8 lvl;
7993
7994 curr_len = snprintf(buf, PAGE_SIZE,
7995 "\nCurrent System PM level [%d] => dev_state [%s] link_state [%s]\n",
7996 hba->spm_lvl,
7997 ufschd_ufs_dev_pwr_mode_to_string(
7998 ufs_pm_lvl_states[hba->spm_lvl].dev_state),
7999 ufschd_uic_link_state_to_string(
8000 ufs_pm_lvl_states[hba->spm_lvl].link_state));
8001
8002 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
8003 "\nAll available System PM levels info:\n");
8004 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
8005 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
8006 "\tSystem PM level [%d] => dev_state [%s] link_state [%s]\n",
8007 lvl,
8008 ufschd_ufs_dev_pwr_mode_to_string(
8009 ufs_pm_lvl_states[lvl].dev_state),
8010 ufschd_uic_link_state_to_string(
8011 ufs_pm_lvl_states[lvl].link_state));
8012
8013 return curr_len;
8014}
8015
8016static ssize_t ufshcd_spm_lvl_store(struct device *dev,
8017 struct device_attribute *attr, const char *buf, size_t count)
8018{
8019 return ufshcd_pm_lvl_store(dev, attr, buf, count, false);
8020}
8021
8022static void ufshcd_add_spm_lvl_sysfs_nodes(struct ufs_hba *hba)
8023{
8024 hba->spm_lvl_attr.show = ufshcd_spm_lvl_show;
8025 hba->spm_lvl_attr.store = ufshcd_spm_lvl_store;
8026 sysfs_attr_init(&hba->spm_lvl_attr.attr);
8027 hba->spm_lvl_attr.attr.name = "spm_lvl";
8028 hba->spm_lvl_attr.attr.mode = 0644;
8029 if (device_create_file(hba->dev, &hba->spm_lvl_attr))
8030 dev_err(hba->dev, "Failed to create sysfs for spm_lvl\n");
8031}
8032
8033static inline void ufshcd_add_sysfs_nodes(struct ufs_hba *hba)
8034{
8035 ufshcd_add_rpm_lvl_sysfs_nodes(hba);
8036 ufshcd_add_spm_lvl_sysfs_nodes(hba);
8037}
8038
463f620b
MP		 8039static inline void ufshcd_remove_sysfs_nodes(struct ufs_hba *hba)
8040{
8041 device_remove_file(hba->dev, &hba->rpm_lvl_attr);
8042 device_remove_file(hba->dev, &hba->spm_lvl_attr);
8043}
8044
57d104c1
SJ		 8045/**
8046 * ufshcd_shutdown - shutdown routine
8047 * @hba: per adapter instance
8048 *
8049 * This function would power off both UFS device and UFS link.
8050 *
8051 * Returns 0 always to allow force shutdown even in case of errors.
8052 */
8053int ufshcd_shutdown(struct ufs_hba *hba)
8054{
8055 int ret = 0;
8056
8057 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8058 goto out;
8059
8060 if (pm_runtime_suspended(hba->dev)) {
8061 ret = ufshcd_runtime_resume(hba);
8062 if (ret)
8063 goto out;
8064 }
8065
8066 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8067out:
8068 if (ret)
8069 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8070 /* allow force shutdown even in case of errors */
8071 return 0;
8072}
8073EXPORT_SYMBOL(ufshcd_shutdown);
8074
7a3e97b0 8075/**
3b1d0580 8076 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 8077 * data structure memory
3b1d0580 8078 * @hba - per adapter instance
7a3e97b0 8079 */
3b1d0580 8080void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 8081{
463f620b 8082 ufshcd_remove_sysfs_nodes(hba);
cfdf9c91 8083 scsi_remove_host(hba->host);
7a3e97b0 8084 /* disable interrupts */
2fbd009b 8085 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 8086 ufshcd_hba_stop(hba, true);
7a3e97b0 8087
1ab27c9c 8088 ufshcd_exit_clk_gating(hba);
fcb0c4b0
ST		 8089 if (ufshcd_is_clkscaling_supported(hba))
8090 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
aa497613 8091 ufshcd_hba_exit(hba);
3b1d0580
VH		 8092}
8093EXPORT_SYMBOL_GPL(ufshcd_remove);
8094
47555a5c
YG		 8095/**
8096 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
8097 * @hba: pointer to Host Bus Adapter (HBA)
8098 */
8099void ufshcd_dealloc_host(struct ufs_hba *hba)
8100{
8101 scsi_host_put(hba->host);
8102}
8103EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8104
ca3d7bf9
AM		 8105/**
8106 * ufshcd_set_dma_mask - Set dma mask based on the controller
8107 * addressing capability
8108 * @hba: per adapter instance
8109 *
8110 * Returns 0 for success, non-zero for failure
8111 */
8112static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8113{
8114 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8115 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8116 return 0;
8117 }
8118 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8119}
8120
7a3e97b0 8121/**
5c0c28a8 8122 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 8123 * @dev: pointer to device handle
8124 * @hba_handle: driver private handle
7a3e97b0
SY		 8125 * Returns 0 on success, non-zero value on failure
8126 */
5c0c28a8 8127int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 8128{
8129 struct Scsi_Host *host;
8130 struct ufs_hba *hba;
5c0c28a8 8131 int err = 0;
7a3e97b0 8132
3b1d0580
VH		 8133 if (!dev) {
8134 dev_err(dev,
8135 "Invalid memory reference for dev is NULL\n");
8136 err = -ENODEV;
7a3e97b0
SY		 8137 goto out_error;
8138 }
8139
7a3e97b0
SY		 8140 host = scsi_host_alloc(&ufshcd_driver_template,
8141 sizeof(struct ufs_hba));
8142 if (!host) {
3b1d0580 8143 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 8144 err = -ENOMEM;
3b1d0580 8145 goto out_error;
7a3e97b0
SY		 8146 }
8147 hba = shost_priv(host);
7a3e97b0 8148 hba->host = host;
3b1d0580 8149 hba->dev = dev;
5c0c28a8
SRT		 8150 *hba_handle = hba;
8151
566ec9ad
SM		 8152 INIT_LIST_HEAD(&hba->clk_list_head);
8153
5c0c28a8
SRT		 8154out_error:
8155 return err;
8156}
8157EXPORT_SYMBOL(ufshcd_alloc_host);
8158
8159/**
8160 * ufshcd_init - Driver initialization routine
8161 * @hba: per-adapter instance
8162 * @mmio_base: base register address
8163 * @irq: Interrupt line of device
8164 * Returns 0 on success, non-zero value on failure
8165 */
8166int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
8167{
8168 int err;
8169 struct Scsi_Host *host = hba->host;
8170 struct device *dev = hba->dev;
8171
8172 if (!mmio_base) {
8173 dev_err(hba->dev,
8174 "Invalid memory reference for mmio_base is NULL\n");
8175 err = -ENODEV;
8176 goto out_error;
8177 }
8178
3b1d0580
VH		 8179 hba->mmio_base = mmio_base;
8180 hba->irq = irq;
7a3e97b0 8181
a4b0e8a4
PM		 8182 /* Set descriptor lengths to specification defaults */
8183 ufshcd_def_desc_sizes(hba);
8184
aa497613 8185 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 8186 if (err)
8187 goto out_error;
8188
7a3e97b0
SY		 8189 /* Read capabilities registers */
8190 ufshcd_hba_capabilities(hba);
8191
8192 /* Get UFS version supported by the controller */
8193 hba->ufs_version = ufshcd_get_ufs_version(hba);
8194
c01848c6
YG		 8195 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
8196 (hba->ufs_version != UFSHCI_VERSION_11) &&
8197 (hba->ufs_version != UFSHCI_VERSION_20) &&
8198 (hba->ufs_version != UFSHCI_VERSION_21))
8199 dev_err(hba->dev, "invalid UFS version 0x%x\n",
8200 hba->ufs_version);
8201
2fbd009b
SJ		 8202 /* Get Interrupt bit mask per version */
8203 hba->intr_mask = ufshcd_get_intr_mask(hba);
8204
ca3d7bf9
AM		 8205 err = ufshcd_set_dma_mask(hba);
8206 if (err) {
8207 dev_err(hba->dev, "set dma mask failed\n");
8208 goto out_disable;
8209 }
8210
7a3e97b0
SY		 8211 /* Allocate memory for host memory space */
8212 err = ufshcd_memory_alloc(hba);
8213 if (err) {
3b1d0580
VH		 8214 dev_err(hba->dev, "Memory allocation failed\n");
8215 goto out_disable;
7a3e97b0
SY		 8216 }
8217
8218 /* Configure LRB */
8219 ufshcd_host_memory_configure(hba);
8220
8221 host->can_queue = hba->nutrs;
8222 host->cmd_per_lun = hba->nutrs;
8223 host->max_id = UFSHCD_MAX_ID;
0ce147d4 8224 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 8225 host->max_channel = UFSHCD_MAX_CHANNEL;
8226 host->unique_id = host->host_no;
8227 host->max_cmd_len = MAX_CDB_SIZE;
8228
7eb584db
DR		 8229 hba->max_pwr_info.is_valid = false;
8230
7a3e97b0 8231 /* Initailize wait queue for task management */
e2933132
SRT		 8232 init_waitqueue_head(&hba->tm_wq);
8233 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 8234
8235 /* Initialize work queues */
e8e7f271 8236 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 8237 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 8238
6ccf44fe
SJ		 8239 /* Initialize UIC command mutex */
8240 mutex_init(&hba->uic_cmd_mutex);
8241
5a0b0cb9
SRT		 8242 /* Initialize mutex for device management commands */
8243 mutex_init(&hba->dev_cmd.lock);
8244
a3cd5ec5
SJ		 8245 init_rwsem(&hba->clk_scaling_lock);
8246
5a0b0cb9
SRT		 8247 /* Initialize device management tag acquire wait queue */
8248 init_waitqueue_head(&hba->dev_cmd.tag_wq);
8249
9087ff6a 8250
8251 err = ufshcd_init_clk_gating(hba);
8252 if (err) {
8253 dev_err(hba->dev, "init clk_gating failed\n");
8254 goto out_disable;
8255 }
199ef13c
YG		 8256
8257 /*
8258 * In order to avoid any spurious interrupt immediately after
8259 * registering UFS controller interrupt handler, clear any pending UFS
8260 * interrupt status and disable all the UFS interrupts.
8261 */
8262 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8263 REG_INTERRUPT_STATUS);
8264 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8265 /*
8266 * Make sure that UFS interrupts are disabled and any pending interrupt
8267 * status is cleared before registering UFS interrupt handler.
8268 */
8269 mb();
8270
7a3e97b0 8271 /* IRQ registration */
2953f850 8272 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 8273 if (err) {
3b1d0580 8274 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 8275 goto exit_gating;
57d104c1
SJ		 8276 } else {
8277 hba->is_irq_enabled = true;
7a3e97b0
SY		 8278 }
8279
3b1d0580 8280 err = scsi_add_host(host, hba->dev);
7a3e97b0 8281 if (err) {
3b1d0580 8282 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 8283 goto exit_gating;
7a3e97b0
SY		 8284 }
8285
fcb0c4b0 8286 if (ufshcd_is_clkscaling_supported(hba)) {
401f1e44
SJ		 8287 char wq_name[sizeof("ufs_clkscaling_00")];
8288
401f1e44
SJ		 8289 INIT_WORK(&hba->clk_scaling.suspend_work,
8290 ufshcd_clk_scaling_suspend_work);
8291 INIT_WORK(&hba->clk_scaling.resume_work,
8292 ufshcd_clk_scaling_resume_work);
8293
d985c6ea 8294 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
401f1e44
SJ		 8295 host->host_no);
8296 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
8297
fcb0c4b0 8298 ufshcd_clkscaling_init_sysfs(hba);
856b3483
ST		 8299 }
8300
0c8f7586
SJ		 8301 /*
8302 * Set the default power management level for runtime and system PM.
8303 * Default power saving mode is to keep UFS link in Hibern8 state
8304 * and UFS device in sleep state.
8305 */
8306 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8307 UFS_SLEEP_PWR_MODE,
8308 UIC_LINK_HIBERN8_STATE);
8309 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8310 UFS_SLEEP_PWR_MODE,
8311 UIC_LINK_HIBERN8_STATE);
8312
62694735
SRT		 8313 /* Hold auto suspend until async scan completes */
8314 pm_runtime_get_sync(dev);
8315
57d104c1 8316 /*
7caf489b
SJ		 8317 * We are assuming that device wasn't put in sleep/power-down
8318 * state exclusively during the boot stage before kernel.
8319 * This assumption helps avoid doing link startup twice during
8320 * ufshcd_probe_hba().
57d104c1 8321 */
7caf489b 8322 ufshcd_set_ufs_dev_active(hba);
57d104c1 8323
6ccf44fe 8324 async_schedule(ufshcd_async_scan, hba);
09690d5a 8325 ufshcd_add_sysfs_nodes(hba);
6ccf44fe 8326
7a3e97b0
SY		 8327 return 0;
8328
3b1d0580
VH		 8329out_remove_scsi_host:
8330 scsi_remove_host(hba->host);
1ab27c9c
ST		 8331exit_gating:
8332 ufshcd_exit_clk_gating(hba);
3b1d0580 8333out_disable:
57d104c1 8334 hba->is_irq_enabled = false;
aa497613 8335 ufshcd_hba_exit(hba);
3b1d0580
VH		 8336out_error:
8337 return err;
8338}
8339EXPORT_SYMBOL_GPL(ufshcd_init);
8340
3b1d0580
VH		 8341MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8342MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8343MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8344MODULE_LICENSE("GPL");
8345MODULE_VERSION(UFSHCD_DRIVER_VERSION);