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scsi: separate out scsi_(host|driver)byte_string()
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
5c0c28a8 6 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
856b3483 41#include <linux/devfreq.h>
6ccf44fe 42
e0eca63e 43#include "ufshcd.h"
53b3d9c3 44#include "unipro.h"
7a3e97b0 45
2fbd009b
SJ		 46#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
47 UTP_TASK_REQ_COMPL |\
48 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 49/* UIC command timeout, unit: ms */
50#define UIC_CMD_TIMEOUT 500
2fbd009b 51
5a0b0cb9
SRT		 52/* NOP OUT retries waiting for NOP IN response */
53#define NOP_OUT_RETRIES 10
54/* Timeout after 30 msecs if NOP OUT hangs without response */
55#define NOP_OUT_TIMEOUT 30 /* msecs */
56
68078d5c
DR		 57/* Query request retries */
58#define QUERY_REQ_RETRIES 10
59/* Query request timeout */
60#define QUERY_REQ_TIMEOUT 30 /* msec */
61
e2933132
SRT		 62/* Task management command timeout */
63#define TM_CMD_TIMEOUT 100 /* msecs */
64
1d337ec2
SRT		 65/* maximum number of link-startup retries */
66#define DME_LINKSTARTUP_RETRIES 3
67
68/* maximum number of reset retries before giving up */
69#define MAX_HOST_RESET_RETRIES 5
70
68078d5c
DR		 71/* Expose the flag value from utp_upiu_query.value */
72#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
73
7d568652
SJ		 74/* Interrupt aggregation default timeout, unit: 40us */
75#define INT_AGGR_DEF_TO 0x02
76
aa497613
SRT		 77#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
78 ({ \
79 int _ret; \
80 if (_on) \
81 _ret = ufshcd_enable_vreg(_dev, _vreg); \
82 else \
83 _ret = ufshcd_disable_vreg(_dev, _vreg); \
84 _ret; \
85 })
86
da461cec
SJ		 87static u32 ufs_query_desc_max_size[] = {
88 QUERY_DESC_DEVICE_MAX_SIZE,
89 QUERY_DESC_CONFIGURAION_MAX_SIZE,
90 QUERY_DESC_UNIT_MAX_SIZE,
91 QUERY_DESC_RFU_MAX_SIZE,
92 QUERY_DESC_INTERCONNECT_MAX_SIZE,
93 QUERY_DESC_STRING_MAX_SIZE,
94 QUERY_DESC_RFU_MAX_SIZE,
95 QUERY_DESC_GEOMETRY_MAZ_SIZE,
96 QUERY_DESC_POWER_MAX_SIZE,
97 QUERY_DESC_RFU_MAX_SIZE,
98};
99
7a3e97b0
SY		 100enum {
101 UFSHCD_MAX_CHANNEL = 0,
102 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 103 UFSHCD_CMD_PER_LUN = 32,
104 UFSHCD_CAN_QUEUE = 32,
105};
106
107/* UFSHCD states */
108enum {
7a3e97b0
SY		 109 UFSHCD_STATE_RESET,
110 UFSHCD_STATE_ERROR,
3441da7d
SRT		 111 UFSHCD_STATE_OPERATIONAL,
112};
113
114/* UFSHCD error handling flags */
115enum {
116 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 117};
118
e8e7f271
SRT		 119/* UFSHCD UIC layer error flags */
120enum {
121 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
122 UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */
123 UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */
124 UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */
125};
126
7a3e97b0
SY		 127/* Interrupt configuration options */
128enum {
129 UFSHCD_INT_DISABLE,
130 UFSHCD_INT_ENABLE,
131 UFSHCD_INT_CLEAR,
132};
133
3441da7d
SRT		 134#define ufshcd_set_eh_in_progress(h) \
135 (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
136#define ufshcd_eh_in_progress(h) \
137 (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
138#define ufshcd_clear_eh_in_progress(h) \
139 (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
140
57d104c1
SJ		 141#define ufshcd_set_ufs_dev_active(h) \
142 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
143#define ufshcd_set_ufs_dev_sleep(h) \
144 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
145#define ufshcd_set_ufs_dev_poweroff(h) \
146 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
147#define ufshcd_is_ufs_dev_active(h) \
148 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
149#define ufshcd_is_ufs_dev_sleep(h) \
150 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
151#define ufshcd_is_ufs_dev_poweroff(h) \
152 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
153
154static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
155 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
156 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
157 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
158 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
159 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
160 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
161};
162
163static inline enum ufs_dev_pwr_mode
164ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
165{
166 return ufs_pm_lvl_states[lvl].dev_state;
167}
168
169static inline enum uic_link_state
170ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
171{
172 return ufs_pm_lvl_states[lvl].link_state;
173}
174
3441da7d
SRT		 175static void ufshcd_tmc_handler(struct ufs_hba *hba);
176static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271
SRT		 177static int ufshcd_reset_and_restore(struct ufs_hba *hba);
178static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 179static void ufshcd_hba_exit(struct ufs_hba *hba);
180static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 181static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
182 bool skip_ref_clk);
183static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
184static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
185static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
57d104c1
SJ		 186static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
187static irqreturn_t ufshcd_intr(int irq, void *__hba);
7eb584db
DR		 188static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
189 struct ufs_pa_layer_attr *desired_pwr_mode);
57d104c1
SJ		 190
191static inline int ufshcd_enable_irq(struct ufs_hba *hba)
192{
193 int ret = 0;
194
195 if (!hba->is_irq_enabled) {
196 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
197 hba);
198 if (ret)
199 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
200 __func__, ret);
201 hba->is_irq_enabled = true;
202 }
203
204 return ret;
205}
206
207static inline void ufshcd_disable_irq(struct ufs_hba *hba)
208{
209 if (hba->is_irq_enabled) {
210 free_irq(hba->irq, hba);
211 hba->is_irq_enabled = false;
212 }
213}
3441da7d 214
5a0b0cb9
SRT		 215/*
216 * ufshcd_wait_for_register - wait for register value to change
217 * @hba - per-adapter interface
218 * @reg - mmio register offset
219 * @mask - mask to apply to read register value
220 * @val - wait condition
221 * @interval_us - polling interval in microsecs
222 * @timeout_ms - timeout in millisecs
223 *
224 * Returns -ETIMEDOUT on error, zero on success
225 */
226static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
227 u32 val, unsigned long interval_us, unsigned long timeout_ms)
228{
229 int err = 0;
230 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
231
232 /* ignore bits that we don't intend to wait on */
233 val = val & mask;
234
235 while ((ufshcd_readl(hba, reg) & mask) != val) {
236 /* wakeup within 50us of expiry */
237 usleep_range(interval_us, interval_us + 50);
238
239 if (time_after(jiffies, timeout)) {
240 if ((ufshcd_readl(hba, reg) & mask) != val)
241 err = -ETIMEDOUT;
242 break;
243 }
244 }
245
246 return err;
247}
248
2fbd009b
SJ		 249/**
250 * ufshcd_get_intr_mask - Get the interrupt bit mask
251 * @hba - Pointer to adapter instance
252 *
253 * Returns interrupt bit mask per version
254 */
255static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
256{
257 if (hba->ufs_version == UFSHCI_VERSION_10)
258 return INTERRUPT_MASK_ALL_VER_10;
259 else
260 return INTERRUPT_MASK_ALL_VER_11;
261}
262
7a3e97b0
SY		 263/**
264 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
265 * @hba - Pointer to adapter instance
266 *
267 * Returns UFSHCI version supported by the controller
268 */
269static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
270{
b873a275 271 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 272}
273
274/**
275 * ufshcd_is_device_present - Check if any device connected to
276 * the host controller
5c0c28a8 277 * @hba: pointer to adapter instance
7a3e97b0 278 *
73ec513a 279 * Returns 1 if device present, 0 if no device detected
7a3e97b0 280 */
5c0c28a8 281static inline int ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 282{
5c0c28a8
SRT		 283 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
284 DEVICE_PRESENT) ? 1 : 0;
7a3e97b0
SY		 285}
286
287/**
288 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
289 * @lrb: pointer to local command reference block
290 *
291 * This function is used to get the OCS field from UTRD
292 * Returns the OCS field in the UTRD
293 */
294static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
295{
e8c8e82a 296 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 297}
298
299/**
300 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
301 * @task_req_descp: pointer to utp_task_req_desc structure
302 *
303 * This function is used to get the OCS field from UTMRD
304 * Returns the OCS field in the UTMRD
305 */
306static inline int
307ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
308{
e8c8e82a 309 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 310}
311
312/**
313 * ufshcd_get_tm_free_slot - get a free slot for task management request
314 * @hba: per adapter instance
e2933132 315 * @free_slot: pointer to variable with available slot value
7a3e97b0 316 *
e2933132
SRT		 317 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
318 * Returns 0 if free slot is not available, else return 1 with tag value
319 * in @free_slot.
7a3e97b0 320 */
e2933132 321static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 322{
e2933132
SRT		 323 int tag;
324 bool ret = false;
325
326 if (!free_slot)
327 goto out;
328
329 do {
330 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
331 if (tag >= hba->nutmrs)
332 goto out;
333 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
334
335 *free_slot = tag;
336 ret = true;
337out:
338 return ret;
339}
340
341static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
342{
343 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 344}
345
346/**
347 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
348 * @hba: per adapter instance
349 * @pos: position of the bit to be cleared
350 */
351static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
352{
b873a275 353 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
7a3e97b0
SY		 354}
355
356/**
357 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
358 * @reg: Register value of host controller status
359 *
360 * Returns integer, 0 on Success and positive value if failed
361 */
362static inline int ufshcd_get_lists_status(u32 reg)
363{
364 /*
365 * The mask 0xFF is for the following HCS register bits
366 * Bit Description
367 * 0 Device Present
368 * 1 UTRLRDY
369 * 2 UTMRLRDY
370 * 3 UCRDY
371 * 4 HEI
372 * 5 DEI
373 * 6-7 reserved
374 */
375 return (((reg) & (0xFF)) >> 1) ^ (0x07);
376}
377
378/**
379 * ufshcd_get_uic_cmd_result - Get the UIC command result
380 * @hba: Pointer to adapter instance
381 *
382 * This function gets the result of UIC command completion
383 * Returns 0 on success, non zero value on error
384 */
385static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
386{
b873a275 387 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 388 MASK_UIC_COMMAND_RESULT;
389}
390
12b4fdb4
SJ		 391/**
392 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
393 * @hba: Pointer to adapter instance
394 *
395 * This function gets UIC command argument3
396 * Returns 0 on success, non zero value on error
397 */
398static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
399{
400 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
401}
402
7a3e97b0 403/**
5a0b0cb9 404 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 405 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 406 */
407static inline int
5a0b0cb9 408ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 409{
5a0b0cb9 410 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 411}
412
413/**
414 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
415 * @ucd_rsp_ptr: pointer to response UPIU
416 *
417 * This function gets the response status and scsi_status from response UPIU
418 * Returns the response result code.
419 */
420static inline int
421ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
422{
423 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
424}
425
1c2623c5
SJ		 426/*
427 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
428 * from response UPIU
429 * @ucd_rsp_ptr: pointer to response UPIU
430 *
431 * Return the data segment length.
432 */
433static inline unsigned int
434ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
435{
436 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
437 MASK_RSP_UPIU_DATA_SEG_LEN;
438}
439
66ec6d59
SRT		 440/**
441 * ufshcd_is_exception_event - Check if the device raised an exception event
442 * @ucd_rsp_ptr: pointer to response UPIU
443 *
444 * The function checks if the device raised an exception event indicated in
445 * the Device Information field of response UPIU.
446 *
447 * Returns true if exception is raised, false otherwise.
448 */
449static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
450{
451 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
452 MASK_RSP_EXCEPTION_EVENT ? true : false;
453}
454
7a3e97b0 455/**
7d568652 456 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 457 * @hba: per adapter instance
7a3e97b0
SY		 458 */
459static inline void
7d568652 460ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 461{
7d568652
SJ		 462 ufshcd_writel(hba, INT_AGGR_ENABLE |
463 INT_AGGR_COUNTER_AND_TIMER_RESET,
464 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
465}
466
467/**
468 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
469 * @hba: per adapter instance
470 * @cnt: Interrupt aggregation counter threshold
471 * @tmout: Interrupt aggregation timeout value
472 */
473static inline void
474ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
475{
476 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
477 INT_AGGR_COUNTER_THLD_VAL(cnt) |
478 INT_AGGR_TIMEOUT_VAL(tmout),
479 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 480}
481
482/**
483 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
484 * When run-stop registers are set to 1, it indicates the
485 * host controller that it can process the requests
486 * @hba: per adapter instance
487 */
488static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
489{
b873a275
SJ		 490 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
491 REG_UTP_TASK_REQ_LIST_RUN_STOP);
492 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
493 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 494}
495
7a3e97b0
SY		 496/**
497 * ufshcd_hba_start - Start controller initialization sequence
498 * @hba: per adapter instance
499 */
500static inline void ufshcd_hba_start(struct ufs_hba *hba)
501{
b873a275 502 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 503}
504
505/**
506 * ufshcd_is_hba_active - Get controller state
507 * @hba: per adapter instance
508 *
509 * Returns zero if controller is active, 1 otherwise
510 */
511static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
512{
b873a275 513 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
7a3e97b0
SY		 514}
515
1ab27c9c
ST		 516static void ufshcd_ungate_work(struct work_struct *work)
517{
518 int ret;
519 unsigned long flags;
520 struct ufs_hba *hba = container_of(work, struct ufs_hba,
521 clk_gating.ungate_work);
522
523 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
524
525 spin_lock_irqsave(hba->host->host_lock, flags);
526 if (hba->clk_gating.state == CLKS_ON) {
527 spin_unlock_irqrestore(hba->host->host_lock, flags);
528 goto unblock_reqs;
529 }
530
531 spin_unlock_irqrestore(hba->host->host_lock, flags);
532 ufshcd_setup_clocks(hba, true);
533
534 /* Exit from hibern8 */
535 if (ufshcd_can_hibern8_during_gating(hba)) {
536 /* Prevent gating in this path */
537 hba->clk_gating.is_suspended = true;
538 if (ufshcd_is_link_hibern8(hba)) {
539 ret = ufshcd_uic_hibern8_exit(hba);
540 if (ret)
541 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
542 __func__, ret);
543 else
544 ufshcd_set_link_active(hba);
545 }
546 hba->clk_gating.is_suspended = false;
547 }
548unblock_reqs:
856b3483
ST		 549 if (ufshcd_is_clkscaling_enabled(hba))
550 devfreq_resume_device(hba->devfreq);
1ab27c9c
ST		 551 scsi_unblock_requests(hba->host);
552}
553
554/**
555 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
556 * Also, exit from hibern8 mode and set the link as active.
557 * @hba: per adapter instance
558 * @async: This indicates whether caller should ungate clocks asynchronously.
559 */
560int ufshcd_hold(struct ufs_hba *hba, bool async)
561{
562 int rc = 0;
563 unsigned long flags;
564
565 if (!ufshcd_is_clkgating_allowed(hba))
566 goto out;
1ab27c9c
ST		 567 spin_lock_irqsave(hba->host->host_lock, flags);
568 hba->clk_gating.active_reqs++;
569
856b3483 570start:
1ab27c9c
ST		 571 switch (hba->clk_gating.state) {
572 case CLKS_ON:
573 break;
574 case REQ_CLKS_OFF:
575 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
576 hba->clk_gating.state = CLKS_ON;
577 break;
578 }
579 /*
580 * If we here, it means gating work is either done or
581 * currently running. Hence, fall through to cancel gating
582 * work and to enable clocks.
583 */
584 case CLKS_OFF:
585 scsi_block_requests(hba->host);
586 hba->clk_gating.state = REQ_CLKS_ON;
587 schedule_work(&hba->clk_gating.ungate_work);
588 /*
589 * fall through to check if we should wait for this
590 * work to be done or not.
591 */
592 case REQ_CLKS_ON:
593 if (async) {
594 rc = -EAGAIN;
595 hba->clk_gating.active_reqs--;
596 break;
597 }
598
599 spin_unlock_irqrestore(hba->host->host_lock, flags);
600 flush_work(&hba->clk_gating.ungate_work);
601 /* Make sure state is CLKS_ON before returning */
856b3483 602 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 603 goto start;
604 default:
605 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
606 __func__, hba->clk_gating.state);
607 break;
608 }
609 spin_unlock_irqrestore(hba->host->host_lock, flags);
610out:
611 return rc;
612}
613
614static void ufshcd_gate_work(struct work_struct *work)
615{
616 struct ufs_hba *hba = container_of(work, struct ufs_hba,
617 clk_gating.gate_work.work);
618 unsigned long flags;
619
620 spin_lock_irqsave(hba->host->host_lock, flags);
621 if (hba->clk_gating.is_suspended) {
622 hba->clk_gating.state = CLKS_ON;
623 goto rel_lock;
624 }
625
626 if (hba->clk_gating.active_reqs
627 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
628 || hba->lrb_in_use || hba->outstanding_tasks
629 || hba->active_uic_cmd || hba->uic_async_done)
630 goto rel_lock;
631
632 spin_unlock_irqrestore(hba->host->host_lock, flags);
633
634 /* put the link into hibern8 mode before turning off clocks */
635 if (ufshcd_can_hibern8_during_gating(hba)) {
636 if (ufshcd_uic_hibern8_enter(hba)) {
637 hba->clk_gating.state = CLKS_ON;
638 goto out;
639 }
640 ufshcd_set_link_hibern8(hba);
641 }
642
856b3483
ST		 643 if (ufshcd_is_clkscaling_enabled(hba)) {
644 devfreq_suspend_device(hba->devfreq);
645 hba->clk_scaling.window_start_t = 0;
646 }
647
1ab27c9c
ST		 648 if (!ufshcd_is_link_active(hba))
649 ufshcd_setup_clocks(hba, false);
650 else
651 /* If link is active, device ref_clk can't be switched off */
652 __ufshcd_setup_clocks(hba, false, true);
653
654 /*
655 * In case you are here to cancel this work the gating state
656 * would be marked as REQ_CLKS_ON. In this case keep the state
657 * as REQ_CLKS_ON which would anyway imply that clocks are off
658 * and a request to turn them on is pending. By doing this way,
659 * we keep the state machine in tact and this would ultimately
660 * prevent from doing cancel work multiple times when there are
661 * new requests arriving before the current cancel work is done.
662 */
663 spin_lock_irqsave(hba->host->host_lock, flags);
664 if (hba->clk_gating.state == REQ_CLKS_OFF)
665 hba->clk_gating.state = CLKS_OFF;
666
667rel_lock:
668 spin_unlock_irqrestore(hba->host->host_lock, flags);
669out:
670 return;
671}
672
673/* host lock must be held before calling this variant */
674static void __ufshcd_release(struct ufs_hba *hba)
675{
676 if (!ufshcd_is_clkgating_allowed(hba))
677 return;
678
679 hba->clk_gating.active_reqs--;
680
681 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
682 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
683 || hba->lrb_in_use || hba->outstanding_tasks
684 || hba->active_uic_cmd || hba->uic_async_done)
685 return;
686
687 hba->clk_gating.state = REQ_CLKS_OFF;
688 schedule_delayed_work(&hba->clk_gating.gate_work,
689 msecs_to_jiffies(hba->clk_gating.delay_ms));
690}
691
692void ufshcd_release(struct ufs_hba *hba)
693{
694 unsigned long flags;
695
696 spin_lock_irqsave(hba->host->host_lock, flags);
697 __ufshcd_release(hba);
698 spin_unlock_irqrestore(hba->host->host_lock, flags);
699}
700
701static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
702 struct device_attribute *attr, char *buf)
703{
704 struct ufs_hba *hba = dev_get_drvdata(dev);
705
706 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
707}
708
709static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
710 struct device_attribute *attr, const char *buf, size_t count)
711{
712 struct ufs_hba *hba = dev_get_drvdata(dev);
713 unsigned long flags, value;
714
715 if (kstrtoul(buf, 0, &value))
716 return -EINVAL;
717
718 spin_lock_irqsave(hba->host->host_lock, flags);
719 hba->clk_gating.delay_ms = value;
720 spin_unlock_irqrestore(hba->host->host_lock, flags);
721 return count;
722}
723
724static void ufshcd_init_clk_gating(struct ufs_hba *hba)
725{
726 if (!ufshcd_is_clkgating_allowed(hba))
727 return;
728
729 hba->clk_gating.delay_ms = 150;
730 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
731 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
732
733 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
734 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
735 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
736 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
737 hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
738 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
739 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
740}
741
742static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
743{
744 if (!ufshcd_is_clkgating_allowed(hba))
745 return;
746 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
747}
748
856b3483
ST		 749/* Must be called with host lock acquired */
750static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
751{
752 if (!ufshcd_is_clkscaling_enabled(hba))
753 return;
754
755 if (!hba->clk_scaling.is_busy_started) {
756 hba->clk_scaling.busy_start_t = ktime_get();
757 hba->clk_scaling.is_busy_started = true;
758 }
759}
760
761static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
762{
763 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
764
765 if (!ufshcd_is_clkscaling_enabled(hba))
766 return;
767
768 if (!hba->outstanding_reqs && scaling->is_busy_started) {
769 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
770 scaling->busy_start_t));
771 scaling->busy_start_t = ktime_set(0, 0);
772 scaling->is_busy_started = false;
773 }
774}
7a3e97b0
SY		 775/**
776 * ufshcd_send_command - Send SCSI or device management commands
777 * @hba: per adapter instance
778 * @task_tag: Task tag of the command
779 */
780static inline
781void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
782{
856b3483 783 ufshcd_clk_scaling_start_busy(hba);
7a3e97b0 784 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 785 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 786}
787
788/**
789 * ufshcd_copy_sense_data - Copy sense data in case of check condition
790 * @lrb - pointer to local reference block
791 */
792static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
793{
794 int len;
1c2623c5
SJ		 795 if (lrbp->sense_buffer &&
796 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
5a0b0cb9 797 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
7a3e97b0 798 memcpy(lrbp->sense_buffer,
5a0b0cb9 799 lrbp->ucd_rsp_ptr->sr.sense_data,
7a3e97b0
SY		 800 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
801 }
802}
803
68078d5c
DR		 804/**
805 * ufshcd_copy_query_response() - Copy the Query Response and the data
806 * descriptor
807 * @hba: per adapter instance
808 * @lrb - pointer to local reference block
809 */
810static
c6d4a831 811int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 812{
813 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
814
68078d5c 815 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 816
68078d5c
DR		 817 /* Get the descriptor */
818 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 819 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 820 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 821 u16 resp_len;
822 u16 buf_len;
68078d5c
DR		 823
824 /* data segment length */
c6d4a831 825 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 826 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 827 buf_len = be16_to_cpu(
828 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 829 if (likely(buf_len >= resp_len)) {
830 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
831 } else {
832 dev_warn(hba->dev,
833 "%s: Response size is bigger than buffer",
834 __func__);
835 return -EINVAL;
836 }
68078d5c 837 }
c6d4a831
DR		 838
839 return 0;
68078d5c
DR		 840}
841
7a3e97b0
SY		 842/**
843 * ufshcd_hba_capabilities - Read controller capabilities
844 * @hba: per adapter instance
845 */
846static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
847{
b873a275 848 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 849
850 /* nutrs and nutmrs are 0 based values */
851 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
852 hba->nutmrs =
853 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
854}
855
856/**
6ccf44fe
SJ		 857 * ufshcd_ready_for_uic_cmd - Check if controller is ready
858 * to accept UIC commands
7a3e97b0 859 * @hba: per adapter instance
6ccf44fe
SJ		 860 * Return true on success, else false
861 */
862static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
863{
864 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
865 return true;
866 else
867 return false;
868}
869
53b3d9c3
SJ		 870/**
871 * ufshcd_get_upmcrs - Get the power mode change request status
872 * @hba: Pointer to adapter instance
873 *
874 * This function gets the UPMCRS field of HCS register
875 * Returns value of UPMCRS field
876 */
877static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
878{
879 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
880}
881
6ccf44fe
SJ		 882/**
883 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
884 * @hba: per adapter instance
885 * @uic_cmd: UIC command
886 *
887 * Mutex must be held.
7a3e97b0
SY		 888 */
889static inline void
6ccf44fe 890ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 891{
6ccf44fe
SJ		 892 WARN_ON(hba->active_uic_cmd);
893
894 hba->active_uic_cmd = uic_cmd;
895
7a3e97b0 896 /* Write Args */
6ccf44fe
SJ		 897 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
898 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
899 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 900
901 /* Write UIC Cmd */
6ccf44fe 902 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 903 REG_UIC_COMMAND);
7a3e97b0
SY		 904}
905
6ccf44fe
SJ		 906/**
907 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
908 * @hba: per adapter instance
909 * @uic_command: UIC command
910 *
911 * Must be called with mutex held.
912 * Returns 0 only if success.
913 */
914static int
915ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
916{
917 int ret;
918 unsigned long flags;
919
920 if (wait_for_completion_timeout(&uic_cmd->done,
921 msecs_to_jiffies(UIC_CMD_TIMEOUT)))
922 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
923 else
924 ret = -ETIMEDOUT;
925
926 spin_lock_irqsave(hba->host->host_lock, flags);
927 hba->active_uic_cmd = NULL;
928 spin_unlock_irqrestore(hba->host->host_lock, flags);
929
930 return ret;
931}
932
933/**
934 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
935 * @hba: per adapter instance
936 * @uic_cmd: UIC command
937 *
938 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 939 * with mutex held and host_lock locked.
6ccf44fe
SJ		 940 * Returns 0 only if success.
941 */
942static int
943__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
944{
6ccf44fe
SJ		 945 if (!ufshcd_ready_for_uic_cmd(hba)) {
946 dev_err(hba->dev,
947 "Controller not ready to accept UIC commands\n");
948 return -EIO;
949 }
950
951 init_completion(&uic_cmd->done);
952
6ccf44fe 953 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 954
57d104c1 955 return 0;
6ccf44fe
SJ		 956}
957
958/**
959 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
960 * @hba: per adapter instance
961 * @uic_cmd: UIC command
962 *
963 * Returns 0 only if success.
964 */
965static int
966ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
967{
968 int ret;
57d104c1 969 unsigned long flags;
6ccf44fe 970
1ab27c9c 971 ufshcd_hold(hba, false);
6ccf44fe 972 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 973 spin_lock_irqsave(hba->host->host_lock, flags);
6ccf44fe 974 ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
57d104c1
SJ		 975 spin_unlock_irqrestore(hba->host->host_lock, flags);
976 if (!ret)
977 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
978
6ccf44fe
SJ		 979 mutex_unlock(&hba->uic_cmd_mutex);
980
1ab27c9c 981 ufshcd_release(hba);
6ccf44fe
SJ		 982 return ret;
983}
984
7a3e97b0
SY		 985/**
986 * ufshcd_map_sg - Map scatter-gather list to prdt
987 * @lrbp - pointer to local reference block
988 *
989 * Returns 0 in case of success, non-zero value in case of failure
990 */
991static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
992{
993 struct ufshcd_sg_entry *prd_table;
994 struct scatterlist *sg;
995 struct scsi_cmnd *cmd;
996 int sg_segments;
997 int i;
998
999 cmd = lrbp->cmd;
1000 sg_segments = scsi_dma_map(cmd);
1001 if (sg_segments < 0)
1002 return sg_segments;
1003
1004 if (sg_segments) {
1005 lrbp->utr_descriptor_ptr->prd_table_length =
1006 cpu_to_le16((u16) (sg_segments));
1007
1008 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
1009
1010 scsi_for_each_sg(cmd, sg, sg_segments, i) {
1011 prd_table[i].size =
1012 cpu_to_le32(((u32) sg_dma_len(sg))-1);
1013 prd_table[i].base_addr =
1014 cpu_to_le32(lower_32_bits(sg->dma_address));
1015 prd_table[i].upper_addr =
1016 cpu_to_le32(upper_32_bits(sg->dma_address));
1017 }
1018 } else {
1019 lrbp->utr_descriptor_ptr->prd_table_length = 0;
1020 }
1021
1022 return 0;
1023}
1024
1025/**
2fbd009b 1026 * ufshcd_enable_intr - enable interrupts
7a3e97b0 1027 * @hba: per adapter instance
2fbd009b 1028 * @intrs: interrupt bits
7a3e97b0 1029 */
2fbd009b 1030static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 1031{
2fbd009b
SJ		 1032 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1033
1034 if (hba->ufs_version == UFSHCI_VERSION_10) {
1035 u32 rw;
1036 rw = set & INTERRUPT_MASK_RW_VER_10;
1037 set = rw | ((set ^ intrs) & intrs);
1038 } else {
1039 set |= intrs;
1040 }
1041
1042 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
1043}
1044
1045/**
1046 * ufshcd_disable_intr - disable interrupts
1047 * @hba: per adapter instance
1048 * @intrs: interrupt bits
1049 */
1050static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
1051{
1052 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
1053
1054 if (hba->ufs_version == UFSHCI_VERSION_10) {
1055 u32 rw;
1056 rw = (set & INTERRUPT_MASK_RW_VER_10) &
1057 ~(intrs & INTERRUPT_MASK_RW_VER_10);
1058 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
1059
1060 } else {
1061 set &= ~intrs;
7a3e97b0 1062 }
2fbd009b
SJ		 1063
1064 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 1065}
1066
5a0b0cb9
SRT		 1067/**
1068 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
1069 * descriptor according to request
1070 * @lrbp: pointer to local reference block
1071 * @upiu_flags: flags required in the header
1072 * @cmd_dir: requests data direction
1073 */
1074static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
1075 u32 *upiu_flags, enum dma_data_direction cmd_dir)
1076{
1077 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
1078 u32 data_direction;
1079 u32 dword_0;
1080
1081 if (cmd_dir == DMA_FROM_DEVICE) {
1082 data_direction = UTP_DEVICE_TO_HOST;
1083 *upiu_flags = UPIU_CMD_FLAGS_READ;
1084 } else if (cmd_dir == DMA_TO_DEVICE) {
1085 data_direction = UTP_HOST_TO_DEVICE;
1086 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
1087 } else {
1088 data_direction = UTP_NO_DATA_TRANSFER;
1089 *upiu_flags = UPIU_CMD_FLAGS_NONE;
1090 }
1091
1092 dword_0 = data_direction | (lrbp->command_type
1093 << UPIU_COMMAND_TYPE_OFFSET);
1094 if (lrbp->intr_cmd)
1095 dword_0 |= UTP_REQ_DESC_INT_CMD;
1096
1097 /* Transfer request descriptor header fields */
1098 req_desc->header.dword_0 = cpu_to_le32(dword_0);
1099
1100 /*
1101 * assigning invalid value for command status. Controller
1102 * updates OCS on command completion, with the command
1103 * status
1104 */
1105 req_desc->header.dword_2 =
1106 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
1107}
1108
1109/**
1110 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
1111 * for scsi commands
1112 * @lrbp - local reference block pointer
1113 * @upiu_flags - flags
1114 */
1115static
1116void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
1117{
1118 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1119
1120 /* command descriptor fields */
1121 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1122 UPIU_TRANSACTION_COMMAND, upiu_flags,
1123 lrbp->lun, lrbp->task_tag);
1124 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1125 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1126
1127 /* Total EHS length and Data segment length will be zero */
1128 ucd_req_ptr->header.dword_2 = 0;
1129
1130 ucd_req_ptr->sc.exp_data_transfer_len =
1131 cpu_to_be32(lrbp->cmd->sdb.length);
1132
1133 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd,
1134 (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE)));
1135}
1136
68078d5c
DR		 1137/**
1138 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
1139 * for query requsts
1140 * @hba: UFS hba
1141 * @lrbp: local reference block pointer
1142 * @upiu_flags: flags
1143 */
1144static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
1145 struct ufshcd_lrb *lrbp, u32 upiu_flags)
1146{
1147 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1148 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 1149 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 1150 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
1151
1152 /* Query request header */
1153 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
1154 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
1155 lrbp->lun, lrbp->task_tag);
1156 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
1157 0, query->request.query_func, 0, 0);
1158
1159 /* Data segment length */
1160 ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
1161 0, 0, len >> 8, (u8)len);
1162
1163 /* Copy the Query Request buffer as is */
1164 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
1165 QUERY_OSF_SIZE);
68078d5c
DR		 1166
1167 /* Copy the Descriptor */
c6d4a831
DR		 1168 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
1169 memcpy(descp, query->descriptor, len);
1170
68078d5c
DR		 1171}
1172
5a0b0cb9
SRT		 1173static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
1174{
1175 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
1176
1177 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
1178
1179 /* command descriptor fields */
1180 ucd_req_ptr->header.dword_0 =
1181 UPIU_HEADER_DWORD(
1182 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
1183}
1184
7a3e97b0
SY		 1185/**
1186 * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
5a0b0cb9 1187 * @hba - per adapter instance
7a3e97b0
SY		 1188 * @lrb - pointer to local reference block
1189 */
5a0b0cb9 1190static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 1191{
7a3e97b0 1192 u32 upiu_flags;
5a0b0cb9 1193 int ret = 0;
7a3e97b0
SY		 1194
1195 switch (lrbp->command_type) {
1196 case UTP_CMD_TYPE_SCSI:
5a0b0cb9
SRT		 1197 if (likely(lrbp->cmd)) {
1198 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
1199 lrbp->cmd->sc_data_direction);
1200 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
7a3e97b0 1201 } else {
5a0b0cb9 1202 ret = -EINVAL;
7a3e97b0 1203 }
7a3e97b0
SY		 1204 break;
1205 case UTP_CMD_TYPE_DEV_MANAGE:
5a0b0cb9 1206 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
68078d5c
DR		 1207 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
1208 ufshcd_prepare_utp_query_req_upiu(
1209 hba, lrbp, upiu_flags);
1210 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
5a0b0cb9
SRT		 1211 ufshcd_prepare_utp_nop_upiu(lrbp);
1212 else
1213 ret = -EINVAL;
7a3e97b0
SY		 1214 break;
1215 case UTP_CMD_TYPE_UFS:
1216 /* For UFS native command implementation */
5a0b0cb9
SRT		 1217 ret = -ENOTSUPP;
1218 dev_err(hba->dev, "%s: UFS native command are not supported\n",
1219 __func__);
1220 break;
1221 default:
1222 ret = -ENOTSUPP;
1223 dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
1224 __func__, lrbp->command_type);
7a3e97b0
SY		 1225 break;
1226 } /* end of switch */
5a0b0cb9
SRT		 1227
1228 return ret;
7a3e97b0
SY		 1229}
1230
0ce147d4
SJ		 1231/*
1232 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
1233 * @scsi_lun: scsi LUN id
1234 *
1235 * Returns UPIU LUN id
1236 */
1237static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
1238{
1239 if (scsi_is_wlun(scsi_lun))
1240 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
1241 | UFS_UPIU_WLUN_ID;
1242 else
1243 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
1244}
1245
2a8fa600
SJ		 1246/**
1247 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
1248 * @scsi_lun: UPIU W-LUN id
1249 *
1250 * Returns SCSI W-LUN id
1251 */
1252static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
1253{
1254 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
1255}
1256
7a3e97b0
SY		 1257/**
1258 * ufshcd_queuecommand - main entry point for SCSI requests
1259 * @cmd: command from SCSI Midlayer
1260 * @done: call back function
1261 *
1262 * Returns 0 for success, non-zero in case of failure
1263 */
1264static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
1265{
1266 struct ufshcd_lrb *lrbp;
1267 struct ufs_hba *hba;
1268 unsigned long flags;
1269 int tag;
1270 int err = 0;
1271
1272 hba = shost_priv(host);
1273
1274 tag = cmd->request->tag;
1275
3441da7d
SRT		 1276 spin_lock_irqsave(hba->host->host_lock, flags);
1277 switch (hba->ufshcd_state) {
1278 case UFSHCD_STATE_OPERATIONAL:
1279 break;
1280 case UFSHCD_STATE_RESET:
7a3e97b0 1281 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 1282 goto out_unlock;
1283 case UFSHCD_STATE_ERROR:
1284 set_host_byte(cmd, DID_ERROR);
1285 cmd->scsi_done(cmd);
1286 goto out_unlock;
1287 default:
1288 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
1289 __func__, hba->ufshcd_state);
1290 set_host_byte(cmd, DID_BAD_TARGET);
1291 cmd->scsi_done(cmd);
1292 goto out_unlock;
7a3e97b0 1293 }
3441da7d 1294 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 1295
5a0b0cb9
SRT		 1296 /* acquire the tag to make sure device cmds don't use it */
1297 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
1298 /*
1299 * Dev manage command in progress, requeue the command.
1300 * Requeuing the command helps in cases where the request *may*
1301 * find different tag instead of waiting for dev manage command
1302 * completion.
1303 */
1304 err = SCSI_MLQUEUE_HOST_BUSY;
1305 goto out;
1306 }
1307
1ab27c9c
ST		 1308 err = ufshcd_hold(hba, true);
1309 if (err) {
1310 err = SCSI_MLQUEUE_HOST_BUSY;
1311 clear_bit_unlock(tag, &hba->lrb_in_use);
1312 goto out;
1313 }
1314 WARN_ON(hba->clk_gating.state != CLKS_ON);
1315
7a3e97b0
SY		 1316 lrbp = &hba->lrb[tag];
1317
5a0b0cb9 1318 WARN_ON(lrbp->cmd);
7a3e97b0
SY		 1319 lrbp->cmd = cmd;
1320 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
1321 lrbp->sense_buffer = cmd->sense_buffer;
1322 lrbp->task_tag = tag;
0ce147d4 1323 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
5a0b0cb9 1324 lrbp->intr_cmd = false;
7a3e97b0
SY		 1325 lrbp->command_type = UTP_CMD_TYPE_SCSI;
1326
1327 /* form UPIU before issuing the command */
5a0b0cb9 1328 ufshcd_compose_upiu(hba, lrbp);
7a3e97b0 1329 err = ufshcd_map_sg(lrbp);
5a0b0cb9
SRT		 1330 if (err) {
1331 lrbp->cmd = NULL;
1332 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 1333 goto out;
5a0b0cb9 1334 }
7a3e97b0
SY		 1335
1336 /* issue command to the controller */
1337 spin_lock_irqsave(hba->host->host_lock, flags);
1338 ufshcd_send_command(hba, tag);
3441da7d 1339out_unlock:
7a3e97b0
SY		 1340 spin_unlock_irqrestore(hba->host->host_lock, flags);
1341out:
1342 return err;
1343}
1344
5a0b0cb9
SRT		 1345static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
1346 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
1347{
1348 lrbp->cmd = NULL;
1349 lrbp->sense_bufflen = 0;
1350 lrbp->sense_buffer = NULL;
1351 lrbp->task_tag = tag;
1352 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
1353 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
1354 lrbp->intr_cmd = true; /* No interrupt aggregation */
1355 hba->dev_cmd.type = cmd_type;
1356
1357 return ufshcd_compose_upiu(hba, lrbp);
1358}
1359
1360static int
1361ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
1362{
1363 int err = 0;
1364 unsigned long flags;
1365 u32 mask = 1 << tag;
1366
1367 /* clear outstanding transaction before retry */
1368 spin_lock_irqsave(hba->host->host_lock, flags);
1369 ufshcd_utrl_clear(hba, tag);
1370 spin_unlock_irqrestore(hba->host->host_lock, flags);
1371
1372 /*
1373 * wait for for h/w to clear corresponding bit in door-bell.
1374 * max. wait is 1 sec.
1375 */
1376 err = ufshcd_wait_for_register(hba,
1377 REG_UTP_TRANSFER_REQ_DOOR_BELL,
1378 mask, ~mask, 1000, 1000);
1379
1380 return err;
1381}
1382
c6d4a831
DR		 1383static int
1384ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1385{
1386 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1387
1388 /* Get the UPIU response */
1389 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
1390 UPIU_RSP_CODE_OFFSET;
1391 return query_res->response;
1392}
1393
5a0b0cb9
SRT		 1394/**
1395 * ufshcd_dev_cmd_completion() - handles device management command responses
1396 * @hba: per adapter instance
1397 * @lrbp: pointer to local reference block
1398 */
1399static int
1400ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1401{
1402 int resp;
1403 int err = 0;
1404
1405 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
1406
1407 switch (resp) {
1408 case UPIU_TRANSACTION_NOP_IN:
1409 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
1410 err = -EINVAL;
1411 dev_err(hba->dev, "%s: unexpected response %x\n",
1412 __func__, resp);
1413 }
1414 break;
68078d5c 1415 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 1416 err = ufshcd_check_query_response(hba, lrbp);
1417 if (!err)
1418 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 1419 break;
5a0b0cb9
SRT		 1420 case UPIU_TRANSACTION_REJECT_UPIU:
1421 /* TODO: handle Reject UPIU Response */
1422 err = -EPERM;
1423 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
1424 __func__);
1425 break;
1426 default:
1427 err = -EINVAL;
1428 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
1429 __func__, resp);
1430 break;
1431 }
1432
1433 return err;
1434}
1435
1436static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
1437 struct ufshcd_lrb *lrbp, int max_timeout)
1438{
1439 int err = 0;
1440 unsigned long time_left;
1441 unsigned long flags;
1442
1443 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
1444 msecs_to_jiffies(max_timeout));
1445
1446 spin_lock_irqsave(hba->host->host_lock, flags);
1447 hba->dev_cmd.complete = NULL;
1448 if (likely(time_left)) {
1449 err = ufshcd_get_tr_ocs(lrbp);
1450 if (!err)
1451 err = ufshcd_dev_cmd_completion(hba, lrbp);
1452 }
1453 spin_unlock_irqrestore(hba->host->host_lock, flags);
1454
1455 if (!time_left) {
1456 err = -ETIMEDOUT;
1457 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
1458 /* sucessfully cleared the command, retry if needed */
1459 err = -EAGAIN;
1460 }
1461
1462 return err;
1463}
1464
1465/**
1466 * ufshcd_get_dev_cmd_tag - Get device management command tag
1467 * @hba: per-adapter instance
1468 * @tag: pointer to variable with available slot value
1469 *
1470 * Get a free slot and lock it until device management command
1471 * completes.
1472 *
1473 * Returns false if free slot is unavailable for locking, else
1474 * return true with tag value in @tag.
1475 */
1476static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
1477{
1478 int tag;
1479 bool ret = false;
1480 unsigned long tmp;
1481
1482 if (!tag_out)
1483 goto out;
1484
1485 do {
1486 tmp = ~hba->lrb_in_use;
1487 tag = find_last_bit(&tmp, hba->nutrs);
1488 if (tag >= hba->nutrs)
1489 goto out;
1490 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
1491
1492 *tag_out = tag;
1493 ret = true;
1494out:
1495 return ret;
1496}
1497
1498static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
1499{
1500 clear_bit_unlock(tag, &hba->lrb_in_use);
1501}
1502
1503/**
1504 * ufshcd_exec_dev_cmd - API for sending device management requests
1505 * @hba - UFS hba
1506 * @cmd_type - specifies the type (NOP, Query...)
1507 * @timeout - time in seconds
1508 *
68078d5c
DR		 1509 * NOTE: Since there is only one available tag for device management commands,
1510 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 1511 */
1512static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
1513 enum dev_cmd_type cmd_type, int timeout)
1514{
1515 struct ufshcd_lrb *lrbp;
1516 int err;
1517 int tag;
1518 struct completion wait;
1519 unsigned long flags;
1520
1521 /*
1522 * Get free slot, sleep if slots are unavailable.
1523 * Even though we use wait_event() which sleeps indefinitely,
1524 * the maximum wait time is bounded by SCSI request timeout.
1525 */
1526 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
1527
1528 init_completion(&wait);
1529 lrbp = &hba->lrb[tag];
1530 WARN_ON(lrbp->cmd);
1531 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
1532 if (unlikely(err))
1533 goto out_put_tag;
1534
1535 hba->dev_cmd.complete = &wait;
1536
1537 spin_lock_irqsave(hba->host->host_lock, flags);
1538 ufshcd_send_command(hba, tag);
1539 spin_unlock_irqrestore(hba->host->host_lock, flags);
1540
1541 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
1542
1543out_put_tag:
1544 ufshcd_put_dev_cmd_tag(hba, tag);
1545 wake_up(&hba->dev_cmd.tag_wq);
1546 return err;
1547}
1548
d44a5f98
DR		 1549/**
1550 * ufshcd_init_query() - init the query response and request parameters
1551 * @hba: per-adapter instance
1552 * @request: address of the request pointer to be initialized
1553 * @response: address of the response pointer to be initialized
1554 * @opcode: operation to perform
1555 * @idn: flag idn to access
1556 * @index: LU number to access
1557 * @selector: query/flag/descriptor further identification
1558 */
1559static inline void ufshcd_init_query(struct ufs_hba *hba,
1560 struct ufs_query_req **request, struct ufs_query_res **response,
1561 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
1562{
1563 *request = &hba->dev_cmd.query.request;
1564 *response = &hba->dev_cmd.query.response;
1565 memset(*request, 0, sizeof(struct ufs_query_req));
1566 memset(*response, 0, sizeof(struct ufs_query_res));
1567 (*request)->upiu_req.opcode = opcode;
1568 (*request)->upiu_req.idn = idn;
1569 (*request)->upiu_req.index = index;
1570 (*request)->upiu_req.selector = selector;
1571}
1572
68078d5c
DR		 1573/**
1574 * ufshcd_query_flag() - API function for sending flag query requests
1575 * hba: per-adapter instance
1576 * query_opcode: flag query to perform
1577 * idn: flag idn to access
1578 * flag_res: the flag value after the query request completes
1579 *
1580 * Returns 0 for success, non-zero in case of failure
1581 */
1582static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
1583 enum flag_idn idn, bool *flag_res)
1584{
d44a5f98
DR		 1585 struct ufs_query_req *request = NULL;
1586 struct ufs_query_res *response = NULL;
1587 int err, index = 0, selector = 0;
68078d5c
DR		 1588
1589 BUG_ON(!hba);
1590
1ab27c9c 1591 ufshcd_hold(hba, false);
68078d5c 1592 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1593 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1594 selector);
68078d5c
DR		 1595
1596 switch (opcode) {
1597 case UPIU_QUERY_OPCODE_SET_FLAG:
1598 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
1599 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
1600 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1601 break;
1602 case UPIU_QUERY_OPCODE_READ_FLAG:
1603 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1604 if (!flag_res) {
1605 /* No dummy reads */
1606 dev_err(hba->dev, "%s: Invalid argument for read request\n",
1607 __func__);
1608 err = -EINVAL;
1609 goto out_unlock;
1610 }
1611 break;
1612 default:
1613 dev_err(hba->dev,
1614 "%s: Expected query flag opcode but got = %d\n",
1615 __func__, opcode);
1616 err = -EINVAL;
1617 goto out_unlock;
1618 }
68078d5c 1619
d44a5f98 1620 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
68078d5c
DR		 1621
1622 if (err) {
1623 dev_err(hba->dev,
1624 "%s: Sending flag query for idn %d failed, err = %d\n",
1625 __func__, idn, err);
1626 goto out_unlock;
1627 }
1628
1629 if (flag_res)
e8c8e82a 1630 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 1631 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1632
1633out_unlock:
1634 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 1635 ufshcd_release(hba);
68078d5c
DR		 1636 return err;
1637}
1638
66ec6d59
SRT		 1639/**
1640 * ufshcd_query_attr - API function for sending attribute requests
1641 * hba: per-adapter instance
1642 * opcode: attribute opcode
1643 * idn: attribute idn to access
1644 * index: index field
1645 * selector: selector field
1646 * attr_val: the attribute value after the query request completes
1647 *
1648 * Returns 0 for success, non-zero in case of failure
1649*/
bdbe5d2f 1650static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 1651 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
1652{
d44a5f98
DR		 1653 struct ufs_query_req *request = NULL;
1654 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 1655 int err;
1656
1657 BUG_ON(!hba);
1658
1ab27c9c 1659 ufshcd_hold(hba, false);
66ec6d59
SRT		 1660 if (!attr_val) {
1661 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
1662 __func__, opcode);
1663 err = -EINVAL;
1664 goto out;
1665 }
1666
1667 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 1668 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1669 selector);
66ec6d59
SRT		 1670
1671 switch (opcode) {
1672 case UPIU_QUERY_OPCODE_WRITE_ATTR:
1673 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 1674 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 1675 break;
1676 case UPIU_QUERY_OPCODE_READ_ATTR:
1677 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1678 break;
1679 default:
1680 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
1681 __func__, opcode);
1682 err = -EINVAL;
1683 goto out_unlock;
1684 }
1685
d44a5f98 1686 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 1687
1688 if (err) {
1689 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1690 __func__, opcode, idn, err);
1691 goto out_unlock;
1692 }
1693
e8c8e82a 1694 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 1695
1696out_unlock:
1697 mutex_unlock(&hba->dev_cmd.lock);
1698out:
1ab27c9c 1699 ufshcd_release(hba);
66ec6d59
SRT		 1700 return err;
1701}
1702
d44a5f98
DR		 1703/**
1704 * ufshcd_query_descriptor - API function for sending descriptor requests
1705 * hba: per-adapter instance
1706 * opcode: attribute opcode
1707 * idn: attribute idn to access
1708 * index: index field
1709 * selector: selector field
1710 * desc_buf: the buffer that contains the descriptor
1711 * buf_len: length parameter passed to the device
1712 *
1713 * Returns 0 for success, non-zero in case of failure.
1714 * The buf_len parameter will contain, on return, the length parameter
1715 * received on the response.
1716 */
7289f983 1717static int ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 1718 enum query_opcode opcode, enum desc_idn idn, u8 index,
1719 u8 selector, u8 *desc_buf, int *buf_len)
1720{
1721 struct ufs_query_req *request = NULL;
1722 struct ufs_query_res *response = NULL;
1723 int err;
1724
1725 BUG_ON(!hba);
1726
1ab27c9c 1727 ufshcd_hold(hba, false);
d44a5f98
DR		 1728 if (!desc_buf) {
1729 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1730 __func__, opcode);
1731 err = -EINVAL;
1732 goto out;
1733 }
1734
1735 if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1736 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1737 __func__, *buf_len);
1738 err = -EINVAL;
1739 goto out;
1740 }
1741
1742 mutex_lock(&hba->dev_cmd.lock);
1743 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1744 selector);
1745 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 1746 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 1747
1748 switch (opcode) {
1749 case UPIU_QUERY_OPCODE_WRITE_DESC:
1750 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1751 break;
1752 case UPIU_QUERY_OPCODE_READ_DESC:
1753 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1754 break;
1755 default:
1756 dev_err(hba->dev,
1757 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1758 __func__, opcode);
1759 err = -EINVAL;
1760 goto out_unlock;
1761 }
1762
1763 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1764
1765 if (err) {
1766 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
1767 __func__, opcode, idn, err);
1768 goto out_unlock;
1769 }
1770
1771 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 1772 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 1773
1774out_unlock:
1775 mutex_unlock(&hba->dev_cmd.lock);
1776out:
1ab27c9c 1777 ufshcd_release(hba);
d44a5f98
DR		 1778 return err;
1779}
1780
da461cec
SJ		 1781/**
1782 * ufshcd_read_desc_param - read the specified descriptor parameter
1783 * @hba: Pointer to adapter instance
1784 * @desc_id: descriptor idn value
1785 * @desc_index: descriptor index
1786 * @param_offset: offset of the parameter to read
1787 * @param_read_buf: pointer to buffer where parameter would be read
1788 * @param_size: sizeof(param_read_buf)
1789 *
1790 * Return 0 in case of success, non-zero otherwise
1791 */
1792static int ufshcd_read_desc_param(struct ufs_hba *hba,
1793 enum desc_idn desc_id,
1794 int desc_index,
1795 u32 param_offset,
1796 u8 *param_read_buf,
1797 u32 param_size)
1798{
1799 int ret;
1800 u8 *desc_buf;
1801 u32 buff_len;
1802 bool is_kmalloc = true;
1803
1804 /* safety checks */
1805 if (desc_id >= QUERY_DESC_IDN_MAX)
1806 return -EINVAL;
1807
1808 buff_len = ufs_query_desc_max_size[desc_id];
1809 if ((param_offset + param_size) > buff_len)
1810 return -EINVAL;
1811
1812 if (!param_offset && (param_size == buff_len)) {
1813 /* memory space already available to hold full descriptor */
1814 desc_buf = param_read_buf;
1815 is_kmalloc = false;
1816 } else {
1817 /* allocate memory to hold full descriptor */
1818 desc_buf = kmalloc(buff_len, GFP_KERNEL);
1819 if (!desc_buf)
1820 return -ENOMEM;
1821 }
1822
1823 ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC,
1824 desc_id, desc_index, 0, desc_buf,
1825 &buff_len);
1826
1827 if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
1828 (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
1829 ufs_query_desc_max_size[desc_id])
1830 || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
1831 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
1832 __func__, desc_id, param_offset, buff_len, ret);
1833 if (!ret)
1834 ret = -EINVAL;
1835
1836 goto out;
1837 }
1838
1839 if (is_kmalloc)
1840 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
1841out:
1842 if (is_kmalloc)
1843 kfree(desc_buf);
1844 return ret;
1845}
1846
1847static inline int ufshcd_read_desc(struct ufs_hba *hba,
1848 enum desc_idn desc_id,
1849 int desc_index,
1850 u8 *buf,
1851 u32 size)
1852{
1853 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
1854}
1855
1856static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
1857 u8 *buf,
1858 u32 size)
1859{
1860 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
1861}
1862
1863/**
1864 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
1865 * @hba: Pointer to adapter instance
1866 * @lun: lun id
1867 * @param_offset: offset of the parameter to read
1868 * @param_read_buf: pointer to buffer where parameter would be read
1869 * @param_size: sizeof(param_read_buf)
1870 *
1871 * Return 0 in case of success, non-zero otherwise
1872 */
1873static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
1874 int lun,
1875 enum unit_desc_param param_offset,
1876 u8 *param_read_buf,
1877 u32 param_size)
1878{
1879 /*
1880 * Unit descriptors are only available for general purpose LUs (LUN id
1881 * from 0 to 7) and RPMB Well known LU.
1882 */
0ce147d4 1883 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 1884 return -EOPNOTSUPP;
1885
1886 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
1887 param_offset, param_read_buf, param_size);
1888}
1889
7a3e97b0
SY		 1890/**
1891 * ufshcd_memory_alloc - allocate memory for host memory space data structures
1892 * @hba: per adapter instance
1893 *
1894 * 1. Allocate DMA memory for Command Descriptor array
1895 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
1896 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
1897 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
1898 * (UTMRDL)
1899 * 4. Allocate memory for local reference block(lrb).
1900 *
1901 * Returns 0 for success, non-zero in case of failure
1902 */
1903static int ufshcd_memory_alloc(struct ufs_hba *hba)
1904{
1905 size_t utmrdl_size, utrdl_size, ucdl_size;
1906
1907 /* Allocate memory for UTP command descriptors */
1908 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 1909 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
1910 ucdl_size,
1911 &hba->ucdl_dma_addr,
1912 GFP_KERNEL);
7a3e97b0
SY		 1913
1914 /*
1915 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
1916 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
1917 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
1918 * be aligned to 128 bytes as well
1919 */
1920 if (!hba->ucdl_base_addr ||
1921 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1922 dev_err(hba->dev,
7a3e97b0
SY		 1923 "Command Descriptor Memory allocation failed\n");
1924 goto out;
1925 }
1926
1927 /*
1928 * Allocate memory for UTP Transfer descriptors
1929 * UFSHCI requires 1024 byte alignment of UTRD
1930 */
1931 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 1932 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
1933 utrdl_size,
1934 &hba->utrdl_dma_addr,
1935 GFP_KERNEL);
7a3e97b0
SY		 1936 if (!hba->utrdl_base_addr ||
1937 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1938 dev_err(hba->dev,
7a3e97b0
SY		 1939 "Transfer Descriptor Memory allocation failed\n");
1940 goto out;
1941 }
1942
1943 /*
1944 * Allocate memory for UTP Task Management descriptors
1945 * UFSHCI requires 1024 byte alignment of UTMRD
1946 */
1947 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 1948 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
1949 utmrdl_size,
1950 &hba->utmrdl_dma_addr,
1951 GFP_KERNEL);
7a3e97b0
SY		 1952 if (!hba->utmrdl_base_addr ||
1953 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 1954 dev_err(hba->dev,
7a3e97b0
SY		 1955 "Task Management Descriptor Memory allocation failed\n");
1956 goto out;
1957 }
1958
1959 /* Allocate memory for local reference block */
2953f850
SJ		 1960 hba->lrb = devm_kzalloc(hba->dev,
1961 hba->nutrs * sizeof(struct ufshcd_lrb),
1962 GFP_KERNEL);
7a3e97b0 1963 if (!hba->lrb) {
3b1d0580 1964 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 1965 goto out;
1966 }
1967 return 0;
1968out:
7a3e97b0
SY		 1969 return -ENOMEM;
1970}
1971
1972/**
1973 * ufshcd_host_memory_configure - configure local reference block with
1974 * memory offsets
1975 * @hba: per adapter instance
1976 *
1977 * Configure Host memory space
1978 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
1979 * address.
1980 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
1981 * and PRDT offset.
1982 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
1983 * into local reference block.
1984 */
1985static void ufshcd_host_memory_configure(struct ufs_hba *hba)
1986{
1987 struct utp_transfer_cmd_desc *cmd_descp;
1988 struct utp_transfer_req_desc *utrdlp;
1989 dma_addr_t cmd_desc_dma_addr;
1990 dma_addr_t cmd_desc_element_addr;
1991 u16 response_offset;
1992 u16 prdt_offset;
1993 int cmd_desc_size;
1994 int i;
1995
1996 utrdlp = hba->utrdl_base_addr;
1997 cmd_descp = hba->ucdl_base_addr;
1998
1999 response_offset =
2000 offsetof(struct utp_transfer_cmd_desc, response_upiu);
2001 prdt_offset =
2002 offsetof(struct utp_transfer_cmd_desc, prd_table);
2003
2004 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
2005 cmd_desc_dma_addr = hba->ucdl_dma_addr;
2006
2007 for (i = 0; i < hba->nutrs; i++) {
2008 /* Configure UTRD with command descriptor base address */
2009 cmd_desc_element_addr =
2010 (cmd_desc_dma_addr + (cmd_desc_size * i));
2011 utrdlp[i].command_desc_base_addr_lo =
2012 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
2013 utrdlp[i].command_desc_base_addr_hi =
2014 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
2015
2016 /* Response upiu and prdt offset should be in double words */
2017 utrdlp[i].response_upiu_offset =
2018 cpu_to_le16((response_offset >> 2));
2019 utrdlp[i].prd_table_offset =
2020 cpu_to_le16((prdt_offset >> 2));
2021 utrdlp[i].response_upiu_length =
3ca316c5 2022 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
7a3e97b0
SY		 2023
2024 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
5a0b0cb9
SRT		 2025 hba->lrb[i].ucd_req_ptr =
2026 (struct utp_upiu_req *)(cmd_descp + i);
7a3e97b0
SY		 2027 hba->lrb[i].ucd_rsp_ptr =
2028 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2029 hba->lrb[i].ucd_prdt_ptr =
2030 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
2031 }
2032}
2033
2034/**
2035 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
2036 * @hba: per adapter instance
2037 *
2038 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
2039 * in order to initialize the Unipro link startup procedure.
2040 * Once the Unipro links are up, the device connected to the controller
2041 * is detected.
2042 *
2043 * Returns 0 on success, non-zero value on failure
2044 */
2045static int ufshcd_dme_link_startup(struct ufs_hba *hba)
2046{
6ccf44fe
SJ		 2047 struct uic_command uic_cmd = {0};
2048 int ret;
7a3e97b0 2049
6ccf44fe 2050 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 2051
6ccf44fe
SJ		 2052 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2053 if (ret)
2054 dev_err(hba->dev,
2055 "dme-link-startup: error code %d\n", ret);
2056 return ret;
7a3e97b0
SY		 2057}
2058
12b4fdb4
SJ		 2059/**
2060 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
2061 * @hba: per adapter instance
2062 * @attr_sel: uic command argument1
2063 * @attr_set: attribute set type as uic command argument2
2064 * @mib_val: setting value as uic command argument3
2065 * @peer: indicate whether peer or local
2066 *
2067 * Returns 0 on success, non-zero value on failure
2068 */
2069int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
2070 u8 attr_set, u32 mib_val, u8 peer)
2071{
2072 struct uic_command uic_cmd = {0};
2073 static const char *const action[] = {
2074 "dme-set",
2075 "dme-peer-set"
2076 };
2077 const char *set = action[!!peer];
2078 int ret;
2079
2080 uic_cmd.command = peer ?
2081 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
2082 uic_cmd.argument1 = attr_sel;
2083 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
2084 uic_cmd.argument3 = mib_val;
2085
2086 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2087 if (ret)
2088 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
2089 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
2090
2091 return ret;
2092}
2093EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
2094
2095/**
2096 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
2097 * @hba: per adapter instance
2098 * @attr_sel: uic command argument1
2099 * @mib_val: the value of the attribute as returned by the UIC command
2100 * @peer: indicate whether peer or local
2101 *
2102 * Returns 0 on success, non-zero value on failure
2103 */
2104int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
2105 u32 *mib_val, u8 peer)
2106{
2107 struct uic_command uic_cmd = {0};
2108 static const char *const action[] = {
2109 "dme-get",
2110 "dme-peer-get"
2111 };
2112 const char *get = action[!!peer];
2113 int ret;
2114
2115 uic_cmd.command = peer ?
2116 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
2117 uic_cmd.argument1 = attr_sel;
2118
2119 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
2120 if (ret) {
2121 dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n",
2122 get, UIC_GET_ATTR_ID(attr_sel), ret);
2123 goto out;
2124 }
2125
2126 if (mib_val)
2127 *mib_val = uic_cmd.argument3;
2128out:
2129 return ret;
2130}
2131EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
2132
53b3d9c3 2133/**
57d104c1
SJ		 2134 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
2135 * state) and waits for it to take effect.
2136 *
53b3d9c3 2137 * @hba: per adapter instance
57d104c1
SJ		 2138 * @cmd: UIC command to execute
2139 *
2140 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
2141 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
2142 * and device UniPro link and hence it's final completion would be indicated by
2143 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
2144 * addition to normal UIC command completion Status (UCCS). This function only
2145 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 2146 *
2147 * Returns 0 on success, non-zero value on failure
2148 */
57d104c1 2149static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 2150{
57d104c1 2151 struct completion uic_async_done;
53b3d9c3
SJ		 2152 unsigned long flags;
2153 u8 status;
2154 int ret;
2155
53b3d9c3 2156 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 2157 init_completion(&uic_async_done);
53b3d9c3
SJ		 2158
2159 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1
SJ		 2160 hba->uic_async_done = &uic_async_done;
2161 ret = __ufshcd_send_uic_cmd(hba, cmd);
53b3d9c3 2162 spin_unlock_irqrestore(hba->host->host_lock, flags);
53b3d9c3
SJ		 2163 if (ret) {
2164 dev_err(hba->dev,
57d104c1
SJ		 2165 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2166 cmd->command, cmd->argument3, ret);
2167 goto out;
2168 }
2169 ret = ufshcd_wait_for_uic_cmd(hba, cmd);
2170 if (ret) {
2171 dev_err(hba->dev,
2172 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
2173 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 2174 goto out;
2175 }
2176
57d104c1 2177 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 2178 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2179 dev_err(hba->dev,
57d104c1
SJ		 2180 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
2181 cmd->command, cmd->argument3);
53b3d9c3
SJ		 2182 ret = -ETIMEDOUT;
2183 goto out;
2184 }
2185
2186 status = ufshcd_get_upmcrs(hba);
2187 if (status != PWR_LOCAL) {
2188 dev_err(hba->dev,
57d104c1
SJ		 2189 "pwr ctrl cmd 0x%0x failed, host umpcrs:0x%x\n",
2190 cmd->command, status);
53b3d9c3
SJ		 2191 ret = (status != PWR_OK) ? status : -1;
2192 }
2193out:
2194 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 2195 hba->uic_async_done = NULL;
53b3d9c3
SJ		 2196 spin_unlock_irqrestore(hba->host->host_lock, flags);
2197 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 2198
53b3d9c3
SJ		 2199 return ret;
2200}
2201
57d104c1
SJ		 2202/**
2203 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
2204 * using DME_SET primitives.
2205 * @hba: per adapter instance
2206 * @mode: powr mode value
2207 *
2208 * Returns 0 on success, non-zero value on failure
2209 */
2210static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
2211{
2212 struct uic_command uic_cmd = {0};
1ab27c9c 2213 int ret;
57d104c1
SJ		 2214
2215 uic_cmd.command = UIC_CMD_DME_SET;
2216 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
2217 uic_cmd.argument3 = mode;
1ab27c9c
ST		 2218 ufshcd_hold(hba, false);
2219 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2220 ufshcd_release(hba);
57d104c1 2221
1ab27c9c 2222 return ret;
57d104c1
SJ		 2223}
2224
2225static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
2226{
2227 struct uic_command uic_cmd = {0};
2228
2229 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
2230
2231 return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2232}
2233
2234static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
2235{
2236 struct uic_command uic_cmd = {0};
2237 int ret;
2238
2239 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
2240 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
2241 if (ret) {
2242 ufshcd_set_link_off(hba);
2243 ret = ufshcd_host_reset_and_restore(hba);
2244 }
2245
2246 return ret;
2247}
2248
d3e89bac 2249/**
7eb584db
DR		 2250 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
2251 * @hba: per-adapter instance
d3e89bac 2252 */
7eb584db 2253static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 2254{
7eb584db
DR		 2255 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
2256
2257 if (hba->max_pwr_info.is_valid)
2258 return 0;
2259
2260 pwr_info->pwr_tx = FASTAUTO_MODE;
2261 pwr_info->pwr_rx = FASTAUTO_MODE;
2262 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 2263
2264 /* Get the connected lane count */
7eb584db
DR		 2265 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
2266 &pwr_info->lane_rx);
2267 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
2268 &pwr_info->lane_tx);
2269
2270 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
2271 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
2272 __func__,
2273 pwr_info->lane_rx,
2274 pwr_info->lane_tx);
2275 return -EINVAL;
2276 }
d3e89bac
SJ		 2277
2278 /*
2279 * First, get the maximum gears of HS speed.
2280 * If a zero value, it means there is no HSGEAR capability.
2281 * Then, get the maximum gears of PWM speed.
2282 */
7eb584db
DR		 2283 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
2284 if (!pwr_info->gear_rx) {
2285 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
2286 &pwr_info->gear_rx);
2287 if (!pwr_info->gear_rx) {
2288 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
2289 __func__, pwr_info->gear_rx);
2290 return -EINVAL;
2291 }
2292 pwr_info->pwr_rx = SLOWAUTO_MODE;
d3e89bac
SJ		 2293 }
2294
7eb584db
DR		 2295 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
2296 &pwr_info->gear_tx);
2297 if (!pwr_info->gear_tx) {
d3e89bac 2298 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 2299 &pwr_info->gear_tx);
2300 if (!pwr_info->gear_tx) {
2301 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
2302 __func__, pwr_info->gear_tx);
2303 return -EINVAL;
2304 }
2305 pwr_info->pwr_tx = SLOWAUTO_MODE;
2306 }
2307
2308 hba->max_pwr_info.is_valid = true;
2309 return 0;
2310}
2311
2312static int ufshcd_change_power_mode(struct ufs_hba *hba,
2313 struct ufs_pa_layer_attr *pwr_mode)
2314{
2315 int ret;
2316
2317 /* if already configured to the requested pwr_mode */
2318 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
2319 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
2320 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
2321 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
2322 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
2323 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
2324 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
2325 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
2326 return 0;
d3e89bac
SJ		 2327 }
2328
2329 /*
2330 * Configure attributes for power mode change with below.
2331 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
2332 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
2333 * - PA_HSSERIES
2334 */
7eb584db
DR		 2335 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
2336 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
2337 pwr_mode->lane_rx);
2338 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2339 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 2340 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 2341 else
2342 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 2343
7eb584db
DR		 2344 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
2345 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
2346 pwr_mode->lane_tx);
2347 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
2348 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 2349 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 2350 else
2351 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 2352
7eb584db
DR		 2353 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
2354 pwr_mode->pwr_tx == FASTAUTO_MODE ||
2355 pwr_mode->pwr_rx == FAST_MODE ||
2356 pwr_mode->pwr_tx == FAST_MODE)
2357 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
2358 pwr_mode->hs_rate);
d3e89bac 2359
7eb584db
DR		 2360 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
2361 | pwr_mode->pwr_tx);
2362
2363 if (ret) {
d3e89bac 2364 dev_err(hba->dev,
7eb584db
DR		 2365 "%s: power mode change failed %d\n", __func__, ret);
2366 } else {
2367 if (hba->vops && hba->vops->pwr_change_notify)
2368 hba->vops->pwr_change_notify(hba,
2369 POST_CHANGE, NULL, pwr_mode);
2370
2371 memcpy(&hba->pwr_info, pwr_mode,
2372 sizeof(struct ufs_pa_layer_attr));
2373 }
2374
2375 return ret;
2376}
2377
2378/**
2379 * ufshcd_config_pwr_mode - configure a new power mode
2380 * @hba: per-adapter instance
2381 * @desired_pwr_mode: desired power configuration
2382 */
2383static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
2384 struct ufs_pa_layer_attr *desired_pwr_mode)
2385{
2386 struct ufs_pa_layer_attr final_params = { 0 };
2387 int ret;
2388
2389 if (hba->vops && hba->vops->pwr_change_notify)
2390 hba->vops->pwr_change_notify(hba,
2391 PRE_CHANGE, desired_pwr_mode, &final_params);
2392 else
2393 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
2394
2395 ret = ufshcd_change_power_mode(hba, &final_params);
d3e89bac
SJ		 2396
2397 return ret;
2398}
2399
68078d5c
DR		 2400/**
2401 * ufshcd_complete_dev_init() - checks device readiness
2402 * hba: per-adapter instance
2403 *
2404 * Set fDeviceInit flag and poll until device toggles it.
2405 */
2406static int ufshcd_complete_dev_init(struct ufs_hba *hba)
2407{
2408 int i, retries, err = 0;
2409 bool flag_res = 1;
2410
2411 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2412 /* Set the fDeviceInit flag */
2413 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
2414 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
2415 if (!err || err == -ETIMEDOUT)
2416 break;
2417 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2418 }
2419 if (err) {
2420 dev_err(hba->dev,
2421 "%s setting fDeviceInit flag failed with error %d\n",
2422 __func__, err);
2423 goto out;
2424 }
2425
2426 /* poll for max. 100 iterations for fDeviceInit flag to clear */
2427 for (i = 0; i < 100 && !err && flag_res; i++) {
2428 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2429 err = ufshcd_query_flag(hba,
2430 UPIU_QUERY_OPCODE_READ_FLAG,
2431 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
2432 if (!err || err == -ETIMEDOUT)
2433 break;
2434 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__,
2435 err);
2436 }
2437 }
2438 if (err)
2439 dev_err(hba->dev,
2440 "%s reading fDeviceInit flag failed with error %d\n",
2441 __func__, err);
2442 else if (flag_res)
2443 dev_err(hba->dev,
2444 "%s fDeviceInit was not cleared by the device\n",
2445 __func__);
2446
2447out:
2448 return err;
2449}
2450
7a3e97b0
SY		 2451/**
2452 * ufshcd_make_hba_operational - Make UFS controller operational
2453 * @hba: per adapter instance
2454 *
2455 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 2456 * 1. Enable required interrupts
2457 * 2. Configure interrupt aggregation
2458 * 3. Program UTRL and UTMRL base addres
2459 * 4. Configure run-stop-registers
7a3e97b0
SY		 2460 *
2461 * Returns 0 on success, non-zero value on failure
2462 */
2463static int ufshcd_make_hba_operational(struct ufs_hba *hba)
2464{
2465 int err = 0;
2466 u32 reg;
2467
6ccf44fe
SJ		 2468 /* Enable required interrupts */
2469 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
2470
2471 /* Configure interrupt aggregation */
7d568652 2472 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
6ccf44fe
SJ		 2473
2474 /* Configure UTRL and UTMRL base address registers */
2475 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
2476 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
2477 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
2478 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
2479 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
2480 REG_UTP_TASK_REQ_LIST_BASE_L);
2481 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
2482 REG_UTP_TASK_REQ_LIST_BASE_H);
2483
7a3e97b0
SY		 2484 /*
2485 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
2486 * DEI, HEI bits must be 0
2487 */
5c0c28a8 2488 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 2489 if (!(ufshcd_get_lists_status(reg))) {
2490 ufshcd_enable_run_stop_reg(hba);
2491 } else {
3b1d0580 2492 dev_err(hba->dev,
7a3e97b0
SY		 2493 "Host controller not ready to process requests");
2494 err = -EIO;
2495 goto out;
2496 }
2497
7a3e97b0
SY		 2498out:
2499 return err;
2500}
2501
2502/**
2503 * ufshcd_hba_enable - initialize the controller
2504 * @hba: per adapter instance
2505 *
2506 * The controller resets itself and controller firmware initialization
2507 * sequence kicks off. When controller is ready it will set
2508 * the Host Controller Enable bit to 1.
2509 *
2510 * Returns 0 on success, non-zero value on failure
2511 */
2512static int ufshcd_hba_enable(struct ufs_hba *hba)
2513{
2514 int retry;
2515
2516 /*
2517 * msleep of 1 and 5 used in this function might result in msleep(20),
2518 * but it was necessary to send the UFS FPGA to reset mode during
2519 * development and testing of this driver. msleep can be changed to
2520 * mdelay and retry count can be reduced based on the controller.
2521 */
2522 if (!ufshcd_is_hba_active(hba)) {
2523
2524 /* change controller state to "reset state" */
2525 ufshcd_hba_stop(hba);
2526
2527 /*
2528 * This delay is based on the testing done with UFS host
2529 * controller FPGA. The delay can be changed based on the
2530 * host controller used.
2531 */
2532 msleep(5);
2533 }
2534
57d104c1
SJ		 2535 /* UniPro link is disabled at this point */
2536 ufshcd_set_link_off(hba);
2537
5c0c28a8
SRT		 2538 if (hba->vops && hba->vops->hce_enable_notify)
2539 hba->vops->hce_enable_notify(hba, PRE_CHANGE);
2540
7a3e97b0
SY		 2541 /* start controller initialization sequence */
2542 ufshcd_hba_start(hba);
2543
2544 /*
2545 * To initialize a UFS host controller HCE bit must be set to 1.
2546 * During initialization the HCE bit value changes from 1->0->1.
2547 * When the host controller completes initialization sequence
2548 * it sets the value of HCE bit to 1. The same HCE bit is read back
2549 * to check if the controller has completed initialization sequence.
2550 * So without this delay the value HCE = 1, set in the previous
2551 * instruction might be read back.
2552 * This delay can be changed based on the controller.
2553 */
2554 msleep(1);
2555
2556 /* wait for the host controller to complete initialization */
2557 retry = 10;
2558 while (ufshcd_is_hba_active(hba)) {
2559 if (retry) {
2560 retry--;
2561 } else {
3b1d0580 2562 dev_err(hba->dev,
7a3e97b0
SY		 2563 "Controller enable failed\n");
2564 return -EIO;
2565 }
2566 msleep(5);
2567 }
5c0c28a8 2568
1d337ec2 2569 /* enable UIC related interrupts */
57d104c1 2570 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 2571
5c0c28a8
SRT		 2572 if (hba->vops && hba->vops->hce_enable_notify)
2573 hba->vops->hce_enable_notify(hba, POST_CHANGE);
2574
7a3e97b0
SY		 2575 return 0;
2576}
2577
2578/**
6ccf44fe 2579 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 2580 * @hba: per adapter instance
2581 *
6ccf44fe 2582 * Returns 0 for success, non-zero in case of failure
7a3e97b0 2583 */
6ccf44fe 2584static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 2585{
6ccf44fe 2586 int ret;
1d337ec2 2587 int retries = DME_LINKSTARTUP_RETRIES;
7a3e97b0 2588
1d337ec2
SRT		 2589 do {
2590 if (hba->vops && hba->vops->link_startup_notify)
2591 hba->vops->link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 2592
1d337ec2 2593 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 2594
1d337ec2
SRT		 2595 /* check if device is detected by inter-connect layer */
2596 if (!ret && !ufshcd_is_device_present(hba)) {
2597 dev_err(hba->dev, "%s: Device not present\n", __func__);
2598 ret = -ENXIO;
2599 goto out;
2600 }
6ccf44fe 2601
1d337ec2
SRT		 2602 /*
2603 * DME link lost indication is only received when link is up,
2604 * but we can't be sure if the link is up until link startup
2605 * succeeds. So reset the local Uni-Pro and try again.
2606 */
2607 if (ret && ufshcd_hba_enable(hba))
2608 goto out;
2609 } while (ret && retries--);
2610
2611 if (ret)
2612 /* failed to get the link up... retire */
5c0c28a8 2613 goto out;
5c0c28a8
SRT		 2614
2615 /* Include any host controller configuration via UIC commands */
2616 if (hba->vops && hba->vops->link_startup_notify) {
2617 ret = hba->vops->link_startup_notify(hba, POST_CHANGE);
2618 if (ret)
2619 goto out;
2620 }
7a3e97b0 2621
5c0c28a8 2622 ret = ufshcd_make_hba_operational(hba);
6ccf44fe
SJ		 2623out:
2624 if (ret)
2625 dev_err(hba->dev, "link startup failed %d\n", ret);
2626 return ret;
7a3e97b0
SY		 2627}
2628
5a0b0cb9
SRT		 2629/**
2630 * ufshcd_verify_dev_init() - Verify device initialization
2631 * @hba: per-adapter instance
2632 *
2633 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
2634 * device Transport Protocol (UTP) layer is ready after a reset.
2635 * If the UTP layer at the device side is not initialized, it may
2636 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
2637 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
2638 */
2639static int ufshcd_verify_dev_init(struct ufs_hba *hba)
2640{
2641 int err = 0;
2642 int retries;
2643
1ab27c9c 2644 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 2645 mutex_lock(&hba->dev_cmd.lock);
2646 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
2647 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
2648 NOP_OUT_TIMEOUT);
2649
2650 if (!err || err == -ETIMEDOUT)
2651 break;
2652
2653 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
2654 }
2655 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2656 ufshcd_release(hba);
5a0b0cb9
SRT		 2657
2658 if (err)
2659 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
2660 return err;
2661}
2662
0ce147d4
SJ		 2663/**
2664 * ufshcd_set_queue_depth - set lun queue depth
2665 * @sdev: pointer to SCSI device
2666 *
2667 * Read bLUQueueDepth value and activate scsi tagged command
2668 * queueing. For WLUN, queue depth is set to 1. For best-effort
2669 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
2670 * value that host can queue.
2671 */
2672static void ufshcd_set_queue_depth(struct scsi_device *sdev)
2673{
2674 int ret = 0;
2675 u8 lun_qdepth;
2676 struct ufs_hba *hba;
2677
2678 hba = shost_priv(sdev->host);
2679
2680 lun_qdepth = hba->nutrs;
2681 ret = ufshcd_read_unit_desc_param(hba,
2682 ufshcd_scsi_to_upiu_lun(sdev->lun),
2683 UNIT_DESC_PARAM_LU_Q_DEPTH,
2684 &lun_qdepth,
2685 sizeof(lun_qdepth));
2686
2687 /* Some WLUN doesn't support unit descriptor */
2688 if (ret == -EOPNOTSUPP)
2689 lun_qdepth = 1;
2690 else if (!lun_qdepth)
2691 /* eventually, we can figure out the real queue depth */
2692 lun_qdepth = hba->nutrs;
2693 else
2694 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
2695
2696 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
2697 __func__, lun_qdepth);
2698 scsi_activate_tcq(sdev, lun_qdepth);
2699}
2700
57d104c1
SJ		 2701/*
2702 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
2703 * @hba: per-adapter instance
2704 * @lun: UFS device lun id
2705 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
2706 *
2707 * Returns 0 in case of success and b_lu_write_protect status would be returned
2708 * @b_lu_write_protect parameter.
2709 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
2710 * Returns -EINVAL in case of invalid parameters passed to this function.
2711 */
2712static int ufshcd_get_lu_wp(struct ufs_hba *hba,
2713 u8 lun,
2714 u8 *b_lu_write_protect)
2715{
2716 int ret;
2717
2718 if (!b_lu_write_protect)
2719 ret = -EINVAL;
2720 /*
2721 * According to UFS device spec, RPMB LU can't be write
2722 * protected so skip reading bLUWriteProtect parameter for
2723 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
2724 */
2725 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
2726 ret = -ENOTSUPP;
2727 else
2728 ret = ufshcd_read_unit_desc_param(hba,
2729 lun,
2730 UNIT_DESC_PARAM_LU_WR_PROTECT,
2731 b_lu_write_protect,
2732 sizeof(*b_lu_write_protect));
2733 return ret;
2734}
2735
2736/**
2737 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
2738 * status
2739 * @hba: per-adapter instance
2740 * @sdev: pointer to SCSI device
2741 *
2742 */
2743static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
2744 struct scsi_device *sdev)
2745{
2746 if (hba->dev_info.f_power_on_wp_en &&
2747 !hba->dev_info.is_lu_power_on_wp) {
2748 u8 b_lu_write_protect;
2749
2750 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
2751 &b_lu_write_protect) &&
2752 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
2753 hba->dev_info.is_lu_power_on_wp = true;
2754 }
2755}
2756
7a3e97b0
SY		 2757/**
2758 * ufshcd_slave_alloc - handle initial SCSI device configurations
2759 * @sdev: pointer to SCSI device
2760 *
2761 * Returns success
2762 */
2763static int ufshcd_slave_alloc(struct scsi_device *sdev)
2764{
2765 struct ufs_hba *hba;
2766
2767 hba = shost_priv(sdev->host);
2768 sdev->tagged_supported = 1;
2769
2770 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
2771 sdev->use_10_for_ms = 1;
2772 scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
2773
e8e7f271
SRT		 2774 /* allow SCSI layer to restart the device in case of errors */
2775 sdev->allow_restart = 1;
4264fd61 2776
b2a6c522
SRT		 2777 /* REPORT SUPPORTED OPERATION CODES is not supported */
2778 sdev->no_report_opcodes = 1;
2779
e8e7f271 2780
0ce147d4 2781 ufshcd_set_queue_depth(sdev);
4264fd61 2782
57d104c1
SJ		 2783 ufshcd_get_lu_power_on_wp_status(hba, sdev);
2784
7a3e97b0
SY		 2785 return 0;
2786}
2787
4264fd61
SRT		 2788/**
2789 * ufshcd_change_queue_depth - change queue depth
2790 * @sdev: pointer to SCSI device
2791 * @depth: required depth to set
2792 * @reason: reason for changing the depth
2793 *
2794 * Change queue depth according to the reason and make sure
2795 * the max. limits are not crossed.
2796 */
7289f983
SRT		 2797static int ufshcd_change_queue_depth(struct scsi_device *sdev,
2798 int depth, int reason)
4264fd61
SRT		 2799{
2800 struct ufs_hba *hba = shost_priv(sdev->host);
2801
2802 if (depth > hba->nutrs)
2803 depth = hba->nutrs;
2804
2805 switch (reason) {
2806 case SCSI_QDEPTH_DEFAULT:
2807 case SCSI_QDEPTH_RAMP_UP:
2808 if (!sdev->tagged_supported)
2809 depth = 1;
2810 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), depth);
2811 break;
2812 case SCSI_QDEPTH_QFULL:
2813 scsi_track_queue_full(sdev, depth);
2814 break;
2815 default:
2816 return -EOPNOTSUPP;
2817 }
2818
2819 return depth;
2820}
2821
eeda4749
AM		 2822/**
2823 * ufshcd_slave_configure - adjust SCSI device configurations
2824 * @sdev: pointer to SCSI device
2825 */
2826static int ufshcd_slave_configure(struct scsi_device *sdev)
2827{
2828 struct request_queue *q = sdev->request_queue;
2829
2830 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
2831 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
2832
2833 return 0;
2834}
2835
7a3e97b0
SY		 2836/**
2837 * ufshcd_slave_destroy - remove SCSI device configurations
2838 * @sdev: pointer to SCSI device
2839 */
2840static void ufshcd_slave_destroy(struct scsi_device *sdev)
2841{
2842 struct ufs_hba *hba;
2843
2844 hba = shost_priv(sdev->host);
2845 scsi_deactivate_tcq(sdev, hba->nutrs);
0ce147d4
SJ		 2846 /* Drop the reference as it won't be needed anymore */
2847 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN)
2848 hba->sdev_ufs_device = NULL;
7a3e97b0
SY		 2849}
2850
2851/**
2852 * ufshcd_task_req_compl - handle task management request completion
2853 * @hba: per adapter instance
2854 * @index: index of the completed request
e2933132 2855 * @resp: task management service response
7a3e97b0 2856 *
e2933132 2857 * Returns non-zero value on error, zero on success
7a3e97b0 2858 */
e2933132 2859static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 2860{
2861 struct utp_task_req_desc *task_req_descp;
2862 struct utp_upiu_task_rsp *task_rsp_upiup;
2863 unsigned long flags;
2864 int ocs_value;
2865 int task_result;
2866
2867 spin_lock_irqsave(hba->host->host_lock, flags);
2868
2869 /* Clear completed tasks from outstanding_tasks */
2870 __clear_bit(index, &hba->outstanding_tasks);
2871
2872 task_req_descp = hba->utmrdl_base_addr;
2873 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
2874
2875 if (ocs_value == OCS_SUCCESS) {
2876 task_rsp_upiup = (struct utp_upiu_task_rsp *)
2877 task_req_descp[index].task_rsp_upiu;
2878 task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
2879 task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
e2933132
SRT		 2880 if (resp)
2881 *resp = (u8)task_result;
7a3e97b0 2882 } else {
e2933132
SRT		 2883 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
2884 __func__, ocs_value);
7a3e97b0
SY		 2885 }
2886 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 2887
2888 return ocs_value;
7a3e97b0
SY		 2889}
2890
7a3e97b0
SY		 2891/**
2892 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
2893 * @lrb: pointer to local reference block of completed command
2894 * @scsi_status: SCSI command status
2895 *
2896 * Returns value base on SCSI command status
2897 */
2898static inline int
2899ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
2900{
2901 int result = 0;
2902
2903 switch (scsi_status) {
7a3e97b0 2904 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 2905 ufshcd_copy_sense_data(lrbp);
2906 case SAM_STAT_GOOD:
7a3e97b0
SY		 2907 result |= DID_OK << 16 |
2908 COMMAND_COMPLETE << 8 |
1c2623c5 2909 scsi_status;
7a3e97b0
SY		 2910 break;
2911 case SAM_STAT_TASK_SET_FULL:
1c2623c5 2912 case SAM_STAT_BUSY:
7a3e97b0 2913 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 2914 ufshcd_copy_sense_data(lrbp);
2915 result |= scsi_status;
7a3e97b0
SY		 2916 break;
2917 default:
2918 result |= DID_ERROR << 16;
2919 break;
2920 } /* end of switch */
2921
2922 return result;
2923}
2924
2925/**
2926 * ufshcd_transfer_rsp_status - Get overall status of the response
2927 * @hba: per adapter instance
2928 * @lrb: pointer to local reference block of completed command
2929 *
2930 * Returns result of the command to notify SCSI midlayer
2931 */
2932static inline int
2933ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2934{
2935 int result = 0;
2936 int scsi_status;
2937 int ocs;
2938
2939 /* overall command status of utrd */
2940 ocs = ufshcd_get_tr_ocs(lrbp);
2941
2942 switch (ocs) {
2943 case OCS_SUCCESS:
5a0b0cb9 2944 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
7a3e97b0 2945
5a0b0cb9
SRT		 2946 switch (result) {
2947 case UPIU_TRANSACTION_RESPONSE:
2948 /*
2949 * get the response UPIU result to extract
2950 * the SCSI command status
2951 */
2952 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
2953
2954 /*
2955 * get the result based on SCSI status response
2956 * to notify the SCSI midlayer of the command status
2957 */
2958 scsi_status = result & MASK_SCSI_STATUS;
2959 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59
SRT		 2960
2961 if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
2962 schedule_work(&hba->eeh_work);
5a0b0cb9
SRT		 2963 break;
2964 case UPIU_TRANSACTION_REJECT_UPIU:
2965 /* TODO: handle Reject UPIU Response */
2966 result = DID_ERROR << 16;
3b1d0580 2967 dev_err(hba->dev,
5a0b0cb9
SRT		 2968 "Reject UPIU not fully implemented\n");
2969 break;
2970 default:
2971 result = DID_ERROR << 16;
2972 dev_err(hba->dev,
2973 "Unexpected request response code = %x\n",
2974 result);
7a3e97b0
SY		 2975 break;
2976 }
7a3e97b0
SY		 2977 break;
2978 case OCS_ABORTED:
2979 result |= DID_ABORT << 16;
2980 break;
e8e7f271
SRT		 2981 case OCS_INVALID_COMMAND_STATUS:
2982 result |= DID_REQUEUE << 16;
2983 break;
7a3e97b0
SY		 2984 case OCS_INVALID_CMD_TABLE_ATTR:
2985 case OCS_INVALID_PRDT_ATTR:
2986 case OCS_MISMATCH_DATA_BUF_SIZE:
2987 case OCS_MISMATCH_RESP_UPIU_SIZE:
2988 case OCS_PEER_COMM_FAILURE:
2989 case OCS_FATAL_ERROR:
2990 default:
2991 result |= DID_ERROR << 16;
3b1d0580 2992 dev_err(hba->dev,
7a3e97b0
SY		 2993 "OCS error from controller = %x\n", ocs);
2994 break;
2995 } /* end of switch */
2996
2997 return result;
2998}
2999
6ccf44fe
SJ		 3000/**
3001 * ufshcd_uic_cmd_compl - handle completion of uic command
3002 * @hba: per adapter instance
53b3d9c3 3003 * @intr_status: interrupt status generated by the controller
6ccf44fe 3004 */
53b3d9c3 3005static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 3006{
53b3d9c3 3007 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 3008 hba->active_uic_cmd->argument2 |=
3009 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 3010 hba->active_uic_cmd->argument3 =
3011 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 3012 complete(&hba->active_uic_cmd->done);
3013 }
53b3d9c3 3014
57d104c1
SJ		 3015 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
3016 complete(hba->uic_async_done);
6ccf44fe
SJ		 3017}
3018
7a3e97b0
SY		 3019/**
3020 * ufshcd_transfer_req_compl - handle SCSI and query command completion
3021 * @hba: per adapter instance
3022 */
3023static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
3024{
5a0b0cb9
SRT		 3025 struct ufshcd_lrb *lrbp;
3026 struct scsi_cmnd *cmd;
7a3e97b0
SY		 3027 unsigned long completed_reqs;
3028 u32 tr_doorbell;
3029 int result;
3030 int index;
e9d501b1
DR		 3031
3032 /* Resetting interrupt aggregation counters first and reading the
3033 * DOOR_BELL afterward allows us to handle all the completed requests.
3034 * In order to prevent other interrupts starvation the DB is read once
3035 * after reset. The down side of this solution is the possibility of
3036 * false interrupt if device completes another request after resetting
3037 * aggregation and before reading the DB.
3038 */
3039 ufshcd_reset_intr_aggr(hba);
7a3e97b0 3040
b873a275 3041 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7a3e97b0
SY		 3042 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
3043
e9d501b1
DR		 3044 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
3045 lrbp = &hba->lrb[index];
3046 cmd = lrbp->cmd;
3047 if (cmd) {
3048 result = ufshcd_transfer_rsp_status(hba, lrbp);
3049 scsi_dma_unmap(cmd);
3050 cmd->result = result;
3051 /* Mark completed command as NULL in LRB */
3052 lrbp->cmd = NULL;
3053 clear_bit_unlock(index, &hba->lrb_in_use);
3054 /* Do not touch lrbp after scsi done */
3055 cmd->scsi_done(cmd);
1ab27c9c 3056 __ufshcd_release(hba);
e9d501b1
DR		 3057 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) {
3058 if (hba->dev_cmd.complete)
3059 complete(hba->dev_cmd.complete);
3060 }
3061 }
7a3e97b0
SY		 3062
3063 /* clear corresponding bits of completed commands */
3064 hba->outstanding_reqs ^= completed_reqs;
3065
856b3483
ST		 3066 ufshcd_clk_scaling_update_busy(hba);
3067
5a0b0cb9
SRT		 3068 /* we might have free'd some tags above */
3069 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 3070}
3071
66ec6d59
SRT		 3072/**
3073 * ufshcd_disable_ee - disable exception event
3074 * @hba: per-adapter instance
3075 * @mask: exception event to disable
3076 *
3077 * Disables exception event in the device so that the EVENT_ALERT
3078 * bit is not set.
3079 *
3080 * Returns zero on success, non-zero error value on failure.
3081 */
3082static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
3083{
3084 int err = 0;
3085 u32 val;
3086
3087 if (!(hba->ee_ctrl_mask & mask))
3088 goto out;
3089
3090 val = hba->ee_ctrl_mask & ~mask;
3091 val &= 0xFFFF; /* 2 bytes */
3092 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3093 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3094 if (!err)
3095 hba->ee_ctrl_mask &= ~mask;
3096out:
3097 return err;
3098}
3099
3100/**
3101 * ufshcd_enable_ee - enable exception event
3102 * @hba: per-adapter instance
3103 * @mask: exception event to enable
3104 *
3105 * Enable corresponding exception event in the device to allow
3106 * device to alert host in critical scenarios.
3107 *
3108 * Returns zero on success, non-zero error value on failure.
3109 */
3110static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
3111{
3112 int err = 0;
3113 u32 val;
3114
3115 if (hba->ee_ctrl_mask & mask)
3116 goto out;
3117
3118 val = hba->ee_ctrl_mask | mask;
3119 val &= 0xFFFF; /* 2 bytes */
3120 err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
3121 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
3122 if (!err)
3123 hba->ee_ctrl_mask |= mask;
3124out:
3125 return err;
3126}
3127
3128/**
3129 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
3130 * @hba: per-adapter instance
3131 *
3132 * Allow device to manage background operations on its own. Enabling
3133 * this might lead to inconsistent latencies during normal data transfers
3134 * as the device is allowed to manage its own way of handling background
3135 * operations.
3136 *
3137 * Returns zero on success, non-zero on failure.
3138 */
3139static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
3140{
3141 int err = 0;
3142
3143 if (hba->auto_bkops_enabled)
3144 goto out;
3145
3146 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
3147 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3148 if (err) {
3149 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
3150 __func__, err);
3151 goto out;
3152 }
3153
3154 hba->auto_bkops_enabled = true;
3155
3156 /* No need of URGENT_BKOPS exception from the device */
3157 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3158 if (err)
3159 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
3160 __func__, err);
3161out:
3162 return err;
3163}
3164
3165/**
3166 * ufshcd_disable_auto_bkops - block device in doing background operations
3167 * @hba: per-adapter instance
3168 *
3169 * Disabling background operations improves command response latency but
3170 * has drawback of device moving into critical state where the device is
3171 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
3172 * host is idle so that BKOPS are managed effectively without any negative
3173 * impacts.
3174 *
3175 * Returns zero on success, non-zero on failure.
3176 */
3177static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
3178{
3179 int err = 0;
3180
3181 if (!hba->auto_bkops_enabled)
3182 goto out;
3183
3184 /*
3185 * If host assisted BKOPs is to be enabled, make sure
3186 * urgent bkops exception is allowed.
3187 */
3188 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
3189 if (err) {
3190 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
3191 __func__, err);
3192 goto out;
3193 }
3194
3195 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
3196 QUERY_FLAG_IDN_BKOPS_EN, NULL);
3197 if (err) {
3198 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
3199 __func__, err);
3200 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
3201 goto out;
3202 }
3203
3204 hba->auto_bkops_enabled = false;
3205out:
3206 return err;
3207}
3208
3209/**
3210 * ufshcd_force_reset_auto_bkops - force enable of auto bkops
3211 * @hba: per adapter instance
3212 *
3213 * After a device reset the device may toggle the BKOPS_EN flag
3214 * to default value. The s/w tracking variables should be updated
3215 * as well. Do this by forcing enable of auto bkops.
3216 */
3217static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
3218{
3219 hba->auto_bkops_enabled = false;
3220 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
3221 ufshcd_enable_auto_bkops(hba);
3222}
3223
3224static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
3225{
3226 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3227 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
3228}
3229
3230/**
57d104c1 3231 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 3232 * @hba: per-adapter instance
57d104c1 3233 * @status: bkops_status value
66ec6d59 3234 *
57d104c1
SJ		 3235 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
3236 * flag in the device to permit background operations if the device
3237 * bkops_status is greater than or equal to "status" argument passed to
3238 * this function, disable otherwise.
3239 *
3240 * Returns 0 for success, non-zero in case of failure.
3241 *
3242 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
3243 * to know whether auto bkops is enabled or disabled after this function
3244 * returns control to it.
66ec6d59 3245 */
57d104c1
SJ		 3246static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
3247 enum bkops_status status)
66ec6d59
SRT		 3248{
3249 int err;
57d104c1 3250 u32 curr_status = 0;
66ec6d59 3251
57d104c1 3252 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 3253 if (err) {
3254 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
3255 __func__, err);
3256 goto out;
57d104c1
SJ		 3257 } else if (curr_status > BKOPS_STATUS_MAX) {
3258 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
3259 __func__, curr_status);
3260 err = -EINVAL;
3261 goto out;
66ec6d59
SRT		 3262 }
3263
57d104c1 3264 if (curr_status >= status)
66ec6d59 3265 err = ufshcd_enable_auto_bkops(hba);
57d104c1
SJ		 3266 else
3267 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 3268out:
3269 return err;
3270}
3271
57d104c1
SJ		 3272/**
3273 * ufshcd_urgent_bkops - handle urgent bkops exception event
3274 * @hba: per-adapter instance
3275 *
3276 * Enable fBackgroundOpsEn flag in the device to permit background
3277 * operations.
3278 *
3279 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
3280 * and negative error value for any other failure.
3281 */
3282static int ufshcd_urgent_bkops(struct ufs_hba *hba)
3283{
3284 return ufshcd_bkops_ctrl(hba, BKOPS_STATUS_PERF_IMPACT);
3285}
3286
66ec6d59
SRT		 3287static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
3288{
3289 return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3290 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
3291}
3292
3293/**
3294 * ufshcd_exception_event_handler - handle exceptions raised by device
3295 * @work: pointer to work data
3296 *
3297 * Read bExceptionEventStatus attribute from the device and handle the
3298 * exception event accordingly.
3299 */
3300static void ufshcd_exception_event_handler(struct work_struct *work)
3301{
3302 struct ufs_hba *hba;
3303 int err;
3304 u32 status = 0;
3305 hba = container_of(work, struct ufs_hba, eeh_work);
3306
62694735 3307 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 3308 err = ufshcd_get_ee_status(hba, &status);
3309 if (err) {
3310 dev_err(hba->dev, "%s: failed to get exception status %d\n",
3311 __func__, err);
3312 goto out;
3313 }
3314
3315 status &= hba->ee_ctrl_mask;
3316 if (status & MASK_EE_URGENT_BKOPS) {
3317 err = ufshcd_urgent_bkops(hba);
57d104c1 3318 if (err < 0)
66ec6d59
SRT		 3319 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
3320 __func__, err);
3321 }
3322out:
62694735 3323 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 3324 return;
3325}
3326
7a3e97b0 3327/**
e8e7f271
SRT		 3328 * ufshcd_err_handler - handle UFS errors that require s/w attention
3329 * @work: pointer to work structure
7a3e97b0 3330 */
e8e7f271 3331static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 3332{
3333 struct ufs_hba *hba;
e8e7f271
SRT		 3334 unsigned long flags;
3335 u32 err_xfer = 0;
3336 u32 err_tm = 0;
3337 int err = 0;
3338 int tag;
3339
3340 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 3341
62694735 3342 pm_runtime_get_sync(hba->dev);
1ab27c9c 3343 ufshcd_hold(hba, false);
e8e7f271
SRT		 3344
3345 spin_lock_irqsave(hba->host->host_lock, flags);
3346 if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
3347 spin_unlock_irqrestore(hba->host->host_lock, flags);
3348 goto out;
3349 }
3350
3351 hba->ufshcd_state = UFSHCD_STATE_RESET;
3352 ufshcd_set_eh_in_progress(hba);
3353
3354 /* Complete requests that have door-bell cleared by h/w */
3355 ufshcd_transfer_req_compl(hba);
3356 ufshcd_tmc_handler(hba);
3357 spin_unlock_irqrestore(hba->host->host_lock, flags);
3358
3359 /* Clear pending transfer requests */
3360 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
3361 if (ufshcd_clear_cmd(hba, tag))
3362 err_xfer |= 1 << tag;
3363
3364 /* Clear pending task management requests */
3365 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs)
3366 if (ufshcd_clear_tm_cmd(hba, tag))
3367 err_tm |= 1 << tag;
3368
3369 /* Complete the requests that are cleared by s/w */
3370 spin_lock_irqsave(hba->host->host_lock, flags);
3371 ufshcd_transfer_req_compl(hba);
3372 ufshcd_tmc_handler(hba);
3373 spin_unlock_irqrestore(hba->host->host_lock, flags);
3374
3375 /* Fatal errors need reset */
3376 if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) ||
3377 ((hba->saved_err & UIC_ERROR) &&
3378 (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) {
3379 err = ufshcd_reset_and_restore(hba);
3380 if (err) {
3381 dev_err(hba->dev, "%s: reset and restore failed\n",
3382 __func__);
3383 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3384 }
3385 /*
3386 * Inform scsi mid-layer that we did reset and allow to handle
3387 * Unit Attention properly.
3388 */
3389 scsi_report_bus_reset(hba->host, 0);
3390 hba->saved_err = 0;
3391 hba->saved_uic_err = 0;
3392 }
3393 ufshcd_clear_eh_in_progress(hba);
3394
3395out:
3396 scsi_unblock_requests(hba->host);
1ab27c9c 3397 ufshcd_release(hba);
62694735 3398 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 3399}
3400
3401/**
e8e7f271
SRT		 3402 * ufshcd_update_uic_error - check and set fatal UIC error flags.
3403 * @hba: per-adapter instance
7a3e97b0 3404 */
e8e7f271 3405static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 3406{
3407 u32 reg;
3408
e8e7f271
SRT		 3409 /* PA_INIT_ERROR is fatal and needs UIC reset */
3410 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
3411 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
3412 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
3413
3414 /* UIC NL/TL/DME errors needs software retry */
3415 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
3416 if (reg)
3417 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
3418
3419 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
3420 if (reg)
3421 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
3422
3423 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
3424 if (reg)
3425 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
3426
3427 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
3428 __func__, hba->uic_error);
3429}
3430
3431/**
3432 * ufshcd_check_errors - Check for errors that need s/w attention
3433 * @hba: per-adapter instance
3434 */
3435static void ufshcd_check_errors(struct ufs_hba *hba)
3436{
3437 bool queue_eh_work = false;
3438
7a3e97b0 3439 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 3440 queue_eh_work = true;
7a3e97b0
SY		 3441
3442 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 3443 hba->uic_error = 0;
3444 ufshcd_update_uic_error(hba);
3445 if (hba->uic_error)
3446 queue_eh_work = true;
7a3e97b0 3447 }
e8e7f271
SRT		 3448
3449 if (queue_eh_work) {
3450 /* handle fatal errors only when link is functional */
3451 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
3452 /* block commands from scsi mid-layer */
3453 scsi_block_requests(hba->host);
3454
3455 /* transfer error masks to sticky bits */
3456 hba->saved_err |= hba->errors;
3457 hba->saved_uic_err |= hba->uic_error;
3458
3459 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3460 schedule_work(&hba->eh_work);
3461 }
3441da7d 3462 }
e8e7f271
SRT		 3463 /*
3464 * if (!queue_eh_work) -
3465 * Other errors are either non-fatal where host recovers
3466 * itself without s/w intervention or errors that will be
3467 * handled by the SCSI core layer.
3468 */
7a3e97b0
SY		 3469}
3470
3471/**
3472 * ufshcd_tmc_handler - handle task management function completion
3473 * @hba: per adapter instance
3474 */
3475static void ufshcd_tmc_handler(struct ufs_hba *hba)
3476{
3477 u32 tm_doorbell;
3478
b873a275 3479 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 3480 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
e2933132 3481 wake_up(&hba->tm_wq);
7a3e97b0
SY		 3482}
3483
3484/**
3485 * ufshcd_sl_intr - Interrupt service routine
3486 * @hba: per adapter instance
3487 * @intr_status: contains interrupts generated by the controller
3488 */
3489static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
3490{
3491 hba->errors = UFSHCD_ERROR_MASK & intr_status;
3492 if (hba->errors)
e8e7f271 3493 ufshcd_check_errors(hba);
7a3e97b0 3494
53b3d9c3
SJ		 3495 if (intr_status & UFSHCD_UIC_MASK)
3496 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 3497
3498 if (intr_status & UTP_TASK_REQ_COMPL)
3499 ufshcd_tmc_handler(hba);
3500
3501 if (intr_status & UTP_TRANSFER_REQ_COMPL)
3502 ufshcd_transfer_req_compl(hba);
3503}
3504
3505/**
3506 * ufshcd_intr - Main interrupt service routine
3507 * @irq: irq number
3508 * @__hba: pointer to adapter instance
3509 *
3510 * Returns IRQ_HANDLED - If interrupt is valid
3511 * IRQ_NONE - If invalid interrupt
3512 */
3513static irqreturn_t ufshcd_intr(int irq, void *__hba)
3514{
3515 u32 intr_status;
3516 irqreturn_t retval = IRQ_NONE;
3517 struct ufs_hba *hba = __hba;
3518
3519 spin_lock(hba->host->host_lock);
b873a275 3520 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7a3e97b0
SY		 3521
3522 if (intr_status) {
261ea452 3523 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
7a3e97b0 3524 ufshcd_sl_intr(hba, intr_status);
7a3e97b0
SY		 3525 retval = IRQ_HANDLED;
3526 }
3527 spin_unlock(hba->host->host_lock);
3528 return retval;
3529}
3530
e2933132
SRT		 3531static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
3532{
3533 int err = 0;
3534 u32 mask = 1 << tag;
3535 unsigned long flags;
3536
3537 if (!test_bit(tag, &hba->outstanding_tasks))
3538 goto out;
3539
3540 spin_lock_irqsave(hba->host->host_lock, flags);
3541 ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
3542 spin_unlock_irqrestore(hba->host->host_lock, flags);
3543
3544 /* poll for max. 1 sec to clear door bell register by h/w */
3545 err = ufshcd_wait_for_register(hba,
3546 REG_UTP_TASK_REQ_DOOR_BELL,
3547 mask, 0, 1000, 1000);
3548out:
3549 return err;
3550}
3551
7a3e97b0
SY		 3552/**
3553 * ufshcd_issue_tm_cmd - issues task management commands to controller
3554 * @hba: per adapter instance
e2933132
SRT		 3555 * @lun_id: LUN ID to which TM command is sent
3556 * @task_id: task ID to which the TM command is applicable
3557 * @tm_function: task management function opcode
3558 * @tm_response: task management service response return value
7a3e97b0 3559 *
e2933132 3560 * Returns non-zero value on error, zero on success.
7a3e97b0 3561 */
e2933132
SRT		 3562static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
3563 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 3564{
3565 struct utp_task_req_desc *task_req_descp;
3566 struct utp_upiu_task_req *task_req_upiup;
3567 struct Scsi_Host *host;
3568 unsigned long flags;
e2933132 3569 int free_slot;
7a3e97b0 3570 int err;
e2933132 3571 int task_tag;
7a3e97b0
SY		 3572
3573 host = hba->host;
3574
e2933132
SRT		 3575 /*
3576 * Get free slot, sleep if slots are unavailable.
3577 * Even though we use wait_event() which sleeps indefinitely,
3578 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
3579 */
3580 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 3581 ufshcd_hold(hba, false);
7a3e97b0 3582
e2933132 3583 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 3584 task_req_descp = hba->utmrdl_base_addr;
3585 task_req_descp += free_slot;
3586
3587 /* Configure task request descriptor */
3588 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
3589 task_req_descp->header.dword_2 =
3590 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
3591
3592 /* Configure task request UPIU */
3593 task_req_upiup =
3594 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 3595 task_tag = hba->nutrs + free_slot;
7a3e97b0 3596 task_req_upiup->header.dword_0 =
5a0b0cb9 3597 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 3598 lun_id, task_tag);
7a3e97b0 3599 task_req_upiup->header.dword_1 =
5a0b0cb9 3600 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 3601 /*
3602 * The host shall provide the same value for LUN field in the basic
3603 * header and for Input Parameter.
3604 */
e2933132
SRT		 3605 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
3606 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0
SY		 3607
3608 /* send command to the controller */
3609 __set_bit(free_slot, &hba->outstanding_tasks);
b873a275 3610 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0
SY		 3611
3612 spin_unlock_irqrestore(host->host_lock, flags);
3613
3614 /* wait until the task management command is completed */
e2933132
SRT		 3615 err = wait_event_timeout(hba->tm_wq,
3616 test_bit(free_slot, &hba->tm_condition),
3617 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 3618 if (!err) {
e2933132
SRT		 3619 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
3620 __func__, tm_function);
3621 if (ufshcd_clear_tm_cmd(hba, free_slot))
3622 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
3623 __func__, free_slot);
3624 err = -ETIMEDOUT;
3625 } else {
3626 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 3627 }
e2933132 3628
7a3e97b0 3629 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 3630 ufshcd_put_tm_slot(hba, free_slot);
3631 wake_up(&hba->tm_tag_wq);
3632
1ab27c9c 3633 ufshcd_release(hba);
7a3e97b0
SY		 3634 return err;
3635}
3636
3637/**
3441da7d
SRT		 3638 * ufshcd_eh_device_reset_handler - device reset handler registered to
3639 * scsi layer.
7a3e97b0
SY		 3640 * @cmd: SCSI command pointer
3641 *
3642 * Returns SUCCESS/FAILED
3643 */
3441da7d 3644static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 3645{
3646 struct Scsi_Host *host;
3647 struct ufs_hba *hba;
3648 unsigned int tag;
3649 u32 pos;
3650 int err;
e2933132
SRT		 3651 u8 resp = 0xF;
3652 struct ufshcd_lrb *lrbp;
3441da7d 3653 unsigned long flags;
7a3e97b0
SY		 3654
3655 host = cmd->device->host;
3656 hba = shost_priv(host);
3657 tag = cmd->request->tag;
3658
e2933132
SRT		 3659 lrbp = &hba->lrb[tag];
3660 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
3661 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 3662 if (!err)
3663 err = resp;
7a3e97b0 3664 goto out;
e2933132 3665 }
7a3e97b0 3666
3441da7d
SRT		 3667 /* clear the commands that were pending for corresponding LUN */
3668 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
3669 if (hba->lrb[pos].lun == lrbp->lun) {
3670 err = ufshcd_clear_cmd(hba, pos);
3671 if (err)
3672 break;
7a3e97b0 3673 }
3441da7d
SRT		 3674 }
3675 spin_lock_irqsave(host->host_lock, flags);
3676 ufshcd_transfer_req_compl(hba);
3677 spin_unlock_irqrestore(host->host_lock, flags);
7a3e97b0 3678out:
3441da7d
SRT		 3679 if (!err) {
3680 err = SUCCESS;
3681 } else {
3682 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3683 err = FAILED;
3684 }
7a3e97b0
SY		 3685 return err;
3686}
3687
7a3e97b0
SY		 3688/**
3689 * ufshcd_abort - abort a specific command
3690 * @cmd: SCSI command pointer
3691 *
f20810d8
SRT		 3692 * Abort the pending command in device by sending UFS_ABORT_TASK task management
3693 * command, and in host controller by clearing the door-bell register. There can
3694 * be race between controller sending the command to the device while abort is
3695 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
3696 * really issued and then try to abort it.
3697 *
7a3e97b0
SY		 3698 * Returns SUCCESS/FAILED
3699 */
3700static int ufshcd_abort(struct scsi_cmnd *cmd)
3701{
3702 struct Scsi_Host *host;
3703 struct ufs_hba *hba;
3704 unsigned long flags;
3705 unsigned int tag;
f20810d8
SRT		 3706 int err = 0;
3707 int poll_cnt;
e2933132
SRT		 3708 u8 resp = 0xF;
3709 struct ufshcd_lrb *lrbp;
e9d501b1 3710 u32 reg;
7a3e97b0
SY		 3711
3712 host = cmd->device->host;
3713 hba = shost_priv(host);
3714 tag = cmd->request->tag;
3715
1ab27c9c 3716 ufshcd_hold(hba, false);
f20810d8
SRT		 3717 /* If command is already aborted/completed, return SUCCESS */
3718 if (!(test_bit(tag, &hba->outstanding_reqs)))
3719 goto out;
7a3e97b0 3720
e9d501b1
DR		 3721 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3722 if (!(reg & (1 << tag))) {
3723 dev_err(hba->dev,
3724 "%s: cmd was completed, but without a notifying intr, tag = %d",
3725 __func__, tag);
3726 }
3727
f20810d8
SRT		 3728 lrbp = &hba->lrb[tag];
3729 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
3730 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3731 UFS_QUERY_TASK, &resp);
3732 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
3733 /* cmd pending in the device */
3734 break;
3735 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3736 /*
3737 * cmd not pending in the device, check if it is
3738 * in transition.
3739 */
3740 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
3741 if (reg & (1 << tag)) {
3742 /* sleep for max. 200us to stabilize */
3743 usleep_range(100, 200);
3744 continue;
3745 }
3746 /* command completed already */
3747 goto out;
3748 } else {
3749 if (!err)
3750 err = resp; /* service response error */
3751 goto out;
3752 }
3753 }
3754
3755 if (!poll_cnt) {
3756 err = -EBUSY;
7a3e97b0
SY		 3757 goto out;
3758 }
7a3e97b0 3759
e2933132
SRT		 3760 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
3761 UFS_ABORT_TASK, &resp);
3762 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 3763 if (!err)
3764 err = resp; /* service response error */
7a3e97b0 3765 goto out;
e2933132 3766 }
7a3e97b0 3767
f20810d8
SRT		 3768 err = ufshcd_clear_cmd(hba, tag);
3769 if (err)
3770 goto out;
3771
7a3e97b0
SY		 3772 scsi_dma_unmap(cmd);
3773
3774 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 3775 __clear_bit(tag, &hba->outstanding_reqs);
3776 hba->lrb[tag].cmd = NULL;
3777 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 3778
3779 clear_bit_unlock(tag, &hba->lrb_in_use);
3780 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 3781
7a3e97b0 3782out:
f20810d8
SRT		 3783 if (!err) {
3784 err = SUCCESS;
3785 } else {
3786 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
3787 err = FAILED;
3788 }
3789
1ab27c9c
ST		 3790 /*
3791 * This ufshcd_release() corresponds to the original scsi cmd that got
3792 * aborted here (as we won't get any IRQ for it).
3793 */
3794 ufshcd_release(hba);
7a3e97b0
SY		 3795 return err;
3796}
3797
3441da7d
SRT		 3798/**
3799 * ufshcd_host_reset_and_restore - reset and restore host controller
3800 * @hba: per-adapter instance
3801 *
3802 * Note that host controller reset may issue DME_RESET to
3803 * local and remote (device) Uni-Pro stack and the attributes
3804 * are reset to default state.
3805 *
3806 * Returns zero on success, non-zero on failure
3807 */
3808static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
3809{
3810 int err;
3441da7d
SRT		 3811 unsigned long flags;
3812
3813 /* Reset the host controller */
3814 spin_lock_irqsave(hba->host->host_lock, flags);
3815 ufshcd_hba_stop(hba);
3816 spin_unlock_irqrestore(hba->host->host_lock, flags);
3817
3818 err = ufshcd_hba_enable(hba);
3819 if (err)
3820 goto out;
3821
3822 /* Establish the link again and restore the device */
1d337ec2
SRT		 3823 err = ufshcd_probe_hba(hba);
3824
3825 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
3441da7d
SRT		 3826 err = -EIO;
3827out:
3828 if (err)
3829 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
3830
3831 return err;
3832}
3833
3834/**
3835 * ufshcd_reset_and_restore - reset and re-initialize host/device
3836 * @hba: per-adapter instance
3837 *
3838 * Reset and recover device, host and re-establish link. This
3839 * is helpful to recover the communication in fatal error conditions.
3840 *
3841 * Returns zero on success, non-zero on failure
3842 */
3843static int ufshcd_reset_and_restore(struct ufs_hba *hba)
3844{
3845 int err = 0;
3846 unsigned long flags;
1d337ec2 3847 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 3848
1d337ec2
SRT		 3849 do {
3850 err = ufshcd_host_reset_and_restore(hba);
3851 } while (err && --retries);
3441da7d
SRT		 3852
3853 /*
3854 * After reset the door-bell might be cleared, complete
3855 * outstanding requests in s/w here.
3856 */
3857 spin_lock_irqsave(hba->host->host_lock, flags);
3858 ufshcd_transfer_req_compl(hba);
3859 ufshcd_tmc_handler(hba);
3860 spin_unlock_irqrestore(hba->host->host_lock, flags);
3861
3862 return err;
3863}
3864
3865/**
3866 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
3867 * @cmd - SCSI command pointer
3868 *
3869 * Returns SUCCESS/FAILED
3870 */
3871static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
3872{
3873 int err;
3874 unsigned long flags;
3875 struct ufs_hba *hba;
3876
3877 hba = shost_priv(cmd->device->host);
3878
1ab27c9c 3879 ufshcd_hold(hba, false);
3441da7d
SRT		 3880 /*
3881 * Check if there is any race with fatal error handling.
3882 * If so, wait for it to complete. Even though fatal error
3883 * handling does reset and restore in some cases, don't assume
3884 * anything out of it. We are just avoiding race here.
3885 */
3886 do {
3887 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 3888 if (!(work_pending(&hba->eh_work) ||
3441da7d
SRT		 3889 hba->ufshcd_state == UFSHCD_STATE_RESET))
3890 break;
3891 spin_unlock_irqrestore(hba->host->host_lock, flags);
3892 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 3893 flush_work(&hba->eh_work);
3441da7d
SRT		 3894 } while (1);
3895
3896 hba->ufshcd_state = UFSHCD_STATE_RESET;
3897 ufshcd_set_eh_in_progress(hba);
3898 spin_unlock_irqrestore(hba->host->host_lock, flags);
3899
3900 err = ufshcd_reset_and_restore(hba);
3901
3902 spin_lock_irqsave(hba->host->host_lock, flags);
3903 if (!err) {
3904 err = SUCCESS;
3905 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
3906 } else {
3907 err = FAILED;
3908 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3909 }
3910 ufshcd_clear_eh_in_progress(hba);
3911 spin_unlock_irqrestore(hba->host->host_lock, flags);
3912
1ab27c9c 3913 ufshcd_release(hba);
3441da7d
SRT		 3914 return err;
3915}
3916
3a4bf06d
YG		 3917/**
3918 * ufshcd_get_max_icc_level - calculate the ICC level
3919 * @sup_curr_uA: max. current supported by the regulator
3920 * @start_scan: row at the desc table to start scan from
3921 * @buff: power descriptor buffer
3922 *
3923 * Returns calculated max ICC level for specific regulator
3924 */
3925static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
3926{
3927 int i;
3928 int curr_uA;
3929 u16 data;
3930 u16 unit;
3931
3932 for (i = start_scan; i >= 0; i--) {
3933 data = be16_to_cpu(*((u16 *)(buff + 2*i)));
3934 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
3935 ATTR_ICC_LVL_UNIT_OFFSET;
3936 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
3937 switch (unit) {
3938 case UFSHCD_NANO_AMP:
3939 curr_uA = curr_uA / 1000;
3940 break;
3941 case UFSHCD_MILI_AMP:
3942 curr_uA = curr_uA * 1000;
3943 break;
3944 case UFSHCD_AMP:
3945 curr_uA = curr_uA * 1000 * 1000;
3946 break;
3947 case UFSHCD_MICRO_AMP:
3948 default:
3949 break;
3950 }
3951 if (sup_curr_uA >= curr_uA)
3952 break;
3953 }
3954 if (i < 0) {
3955 i = 0;
3956 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
3957 }
3958
3959 return (u32)i;
3960}
3961
3962/**
3963 * ufshcd_calc_icc_level - calculate the max ICC level
3964 * In case regulators are not initialized we'll return 0
3965 * @hba: per-adapter instance
3966 * @desc_buf: power descriptor buffer to extract ICC levels from.
3967 * @len: length of desc_buff
3968 *
3969 * Returns calculated ICC level
3970 */
3971static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
3972 u8 *desc_buf, int len)
3973{
3974 u32 icc_level = 0;
3975
3976 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
3977 !hba->vreg_info.vccq2) {
3978 dev_err(hba->dev,
3979 "%s: Regulator capability was not set, actvIccLevel=%d",
3980 __func__, icc_level);
3981 goto out;
3982 }
3983
3984 if (hba->vreg_info.vcc)
3985 icc_level = ufshcd_get_max_icc_level(
3986 hba->vreg_info.vcc->max_uA,
3987 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
3988 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
3989
3990 if (hba->vreg_info.vccq)
3991 icc_level = ufshcd_get_max_icc_level(
3992 hba->vreg_info.vccq->max_uA,
3993 icc_level,
3994 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
3995
3996 if (hba->vreg_info.vccq2)
3997 icc_level = ufshcd_get_max_icc_level(
3998 hba->vreg_info.vccq2->max_uA,
3999 icc_level,
4000 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
4001out:
4002 return icc_level;
4003}
4004
4005static void ufshcd_init_icc_levels(struct ufs_hba *hba)
4006{
4007 int ret;
4008 int buff_len = QUERY_DESC_POWER_MAX_SIZE;
4009 u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
4010
4011 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
4012 if (ret) {
4013 dev_err(hba->dev,
4014 "%s: Failed reading power descriptor.len = %d ret = %d",
4015 __func__, buff_len, ret);
4016 return;
4017 }
4018
4019 hba->init_prefetch_data.icc_level =
4020 ufshcd_find_max_sup_active_icc_level(hba,
4021 desc_buf, buff_len);
4022 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
4023 __func__, hba->init_prefetch_data.icc_level);
4024
4025 ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
4026 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
4027 &hba->init_prefetch_data.icc_level);
4028
4029 if (ret)
4030 dev_err(hba->dev,
4031 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
4032 __func__, hba->init_prefetch_data.icc_level , ret);
4033
4034}
4035
2a8fa600
SJ		 4036/**
4037 * ufshcd_scsi_add_wlus - Adds required W-LUs
4038 * @hba: per-adapter instance
4039 *
4040 * UFS device specification requires the UFS devices to support 4 well known
4041 * logical units:
4042 * "REPORT_LUNS" (address: 01h)
4043 * "UFS Device" (address: 50h)
4044 * "RPMB" (address: 44h)
4045 * "BOOT" (address: 30h)
4046 * UFS device's power management needs to be controlled by "POWER CONDITION"
4047 * field of SSU (START STOP UNIT) command. But this "power condition" field
4048 * will take effect only when its sent to "UFS device" well known logical unit
4049 * hence we require the scsi_device instance to represent this logical unit in
4050 * order for the UFS host driver to send the SSU command for power management.
4051
4052 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
4053 * Block) LU so user space process can control this LU. User space may also
4054 * want to have access to BOOT LU.
4055
4056 * This function adds scsi device instances for each of all well known LUs
4057 * (except "REPORT LUNS" LU).
4058 *
4059 * Returns zero on success (all required W-LUs are added successfully),
4060 * non-zero error value on failure (if failed to add any of the required W-LU).
4061 */
4062static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
4063{
4064 int ret = 0;
4065
4066 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
4067 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
4068 if (IS_ERR(hba->sdev_ufs_device)) {
4069 ret = PTR_ERR(hba->sdev_ufs_device);
4070 hba->sdev_ufs_device = NULL;
4071 goto out;
4072 }
4073
4074 hba->sdev_boot = __scsi_add_device(hba->host, 0, 0,
4075 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
4076 if (IS_ERR(hba->sdev_boot)) {
4077 ret = PTR_ERR(hba->sdev_boot);
4078 hba->sdev_boot = NULL;
4079 goto remove_sdev_ufs_device;
4080 }
4081
4082 hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
4083 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
4084 if (IS_ERR(hba->sdev_rpmb)) {
4085 ret = PTR_ERR(hba->sdev_rpmb);
4086 hba->sdev_rpmb = NULL;
4087 goto remove_sdev_boot;
4088 }
4089 goto out;
4090
4091remove_sdev_boot:
4092 scsi_remove_device(hba->sdev_boot);
4093remove_sdev_ufs_device:
4094 scsi_remove_device(hba->sdev_ufs_device);
4095out:
4096 return ret;
4097}
4098
4099/**
4100 * ufshcd_scsi_remove_wlus - Removes the W-LUs which were added by
4101 * ufshcd_scsi_add_wlus()
4102 * @hba: per-adapter instance
4103 *
4104 */
4105static void ufshcd_scsi_remove_wlus(struct ufs_hba *hba)
4106{
4107 if (hba->sdev_ufs_device) {
4108 scsi_remove_device(hba->sdev_ufs_device);
4109 hba->sdev_ufs_device = NULL;
4110 }
4111
4112 if (hba->sdev_boot) {
4113 scsi_remove_device(hba->sdev_boot);
4114 hba->sdev_boot = NULL;
4115 }
4116
4117 if (hba->sdev_rpmb) {
4118 scsi_remove_device(hba->sdev_rpmb);
4119 hba->sdev_rpmb = NULL;
4120 }
4121}
4122
6ccf44fe 4123/**
1d337ec2
SRT		 4124 * ufshcd_probe_hba - probe hba to detect device and initialize
4125 * @hba: per-adapter instance
4126 *
4127 * Execute link-startup and verify device initialization
6ccf44fe 4128 */
1d337ec2 4129static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 4130{
6ccf44fe
SJ		 4131 int ret;
4132
4133 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 4134 if (ret)
4135 goto out;
4136
57d104c1
SJ		 4137 /* UniPro link is active now */
4138 ufshcd_set_link_active(hba);
d3e89bac 4139
5a0b0cb9
SRT		 4140 ret = ufshcd_verify_dev_init(hba);
4141 if (ret)
4142 goto out;
68078d5c
DR		 4143
4144 ret = ufshcd_complete_dev_init(hba);
4145 if (ret)
4146 goto out;
5a0b0cb9 4147
57d104c1
SJ		 4148 /* UFS device is also active now */
4149 ufshcd_set_ufs_dev_active(hba);
66ec6d59 4150 ufshcd_force_reset_auto_bkops(hba);
3441da7d 4151 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
57d104c1
SJ		 4152 hba->wlun_dev_clr_ua = true;
4153
7eb584db
DR		 4154 if (ufshcd_get_max_pwr_mode(hba)) {
4155 dev_err(hba->dev,
4156 "%s: Failed getting max supported power mode\n",
4157 __func__);
4158 } else {
4159 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
4160 if (ret)
4161 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
4162 __func__, ret);
4163 }
57d104c1
SJ		 4164
4165 /*
4166 * If we are in error handling context or in power management callbacks
4167 * context, no need to scan the host
4168 */
4169 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4170 bool flag;
4171
4172 /* clear any previous UFS device information */
4173 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
4174 if (!ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4175 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
4176 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 4177
3a4bf06d
YG		 4178 if (!hba->is_init_prefetch)
4179 ufshcd_init_icc_levels(hba);
4180
2a8fa600
SJ		 4181 /* Add required well known logical units to scsi mid layer */
4182 if (ufshcd_scsi_add_wlus(hba))
4183 goto out;
4184
3441da7d
SRT		 4185 scsi_scan_host(hba->host);
4186 pm_runtime_put_sync(hba->dev);
4187 }
3a4bf06d
YG		 4188
4189 if (!hba->is_init_prefetch)
4190 hba->is_init_prefetch = true;
4191
856b3483
ST		 4192 /* Resume devfreq after UFS device is detected */
4193 if (ufshcd_is_clkscaling_enabled(hba))
4194 devfreq_resume_device(hba->devfreq);
4195
5a0b0cb9 4196out:
1d337ec2
SRT		 4197 /*
4198 * If we failed to initialize the device or the device is not
4199 * present, turn off the power/clocks etc.
4200 */
57d104c1
SJ		 4201 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
4202 pm_runtime_put_sync(hba->dev);
1d337ec2 4203 ufshcd_hba_exit(hba);
57d104c1 4204 }
1d337ec2
SRT		 4205
4206 return ret;
4207}
4208
4209/**
4210 * ufshcd_async_scan - asynchronous execution for probing hba
4211 * @data: data pointer to pass to this function
4212 * @cookie: cookie data
4213 */
4214static void ufshcd_async_scan(void *data, async_cookie_t cookie)
4215{
4216 struct ufs_hba *hba = (struct ufs_hba *)data;
4217
4218 ufshcd_probe_hba(hba);
6ccf44fe
SJ		 4219}
4220
7a3e97b0
SY		 4221static struct scsi_host_template ufshcd_driver_template = {
4222 .module = THIS_MODULE,
4223 .name = UFSHCD,
4224 .proc_name = UFSHCD,
4225 .queuecommand = ufshcd_queuecommand,
4226 .slave_alloc = ufshcd_slave_alloc,
eeda4749 4227 .slave_configure = ufshcd_slave_configure,
7a3e97b0 4228 .slave_destroy = ufshcd_slave_destroy,
4264fd61 4229 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 4230 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 4231 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
4232 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
7a3e97b0
SY		 4233 .this_id = -1,
4234 .sg_tablesize = SG_ALL,
4235 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
4236 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 4237 .max_host_blocked = 1,
7a3e97b0
SY		 4238};
4239
57d104c1
SJ		 4240static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
4241 int ua)
4242{
4243 int ret = 0;
4244 struct regulator *reg = vreg->reg;
4245 const char *name = vreg->name;
4246
4247 BUG_ON(!vreg);
4248
4249 ret = regulator_set_optimum_mode(reg, ua);
4250 if (ret >= 0) {
4251 /*
4252 * regulator_set_optimum_mode() returns new regulator
4253 * mode upon success.
4254 */
4255 ret = 0;
4256 } else {
4257 dev_err(dev, "%s: %s set optimum mode(ua=%d) failed, err=%d\n",
4258 __func__, name, ua, ret);
4259 }
4260
4261 return ret;
4262}
4263
4264static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
4265 struct ufs_vreg *vreg)
4266{
4267 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
4268}
4269
4270static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
4271 struct ufs_vreg *vreg)
4272{
4273 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
4274}
4275
aa497613
SRT		 4276static int ufshcd_config_vreg(struct device *dev,
4277 struct ufs_vreg *vreg, bool on)
4278{
4279 int ret = 0;
4280 struct regulator *reg = vreg->reg;
4281 const char *name = vreg->name;
4282 int min_uV, uA_load;
4283
4284 BUG_ON(!vreg);
4285
4286 if (regulator_count_voltages(reg) > 0) {
4287 min_uV = on ? vreg->min_uV : 0;
4288 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
4289 if (ret) {
4290 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
4291 __func__, name, ret);
4292 goto out;
4293 }
4294
4295 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 4296 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
4297 if (ret)
aa497613 4298 goto out;
aa497613
SRT		 4299 }
4300out:
4301 return ret;
4302}
4303
4304static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
4305{
4306 int ret = 0;
4307
4308 if (!vreg || vreg->enabled)
4309 goto out;
4310
4311 ret = ufshcd_config_vreg(dev, vreg, true);
4312 if (!ret)
4313 ret = regulator_enable(vreg->reg);
4314
4315 if (!ret)
4316 vreg->enabled = true;
4317 else
4318 dev_err(dev, "%s: %s enable failed, err=%d\n",
4319 __func__, vreg->name, ret);
4320out:
4321 return ret;
4322}
4323
4324static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
4325{
4326 int ret = 0;
4327
4328 if (!vreg || !vreg->enabled)
4329 goto out;
4330
4331 ret = regulator_disable(vreg->reg);
4332
4333 if (!ret) {
4334 /* ignore errors on applying disable config */
4335 ufshcd_config_vreg(dev, vreg, false);
4336 vreg->enabled = false;
4337 } else {
4338 dev_err(dev, "%s: %s disable failed, err=%d\n",
4339 __func__, vreg->name, ret);
4340 }
4341out:
4342 return ret;
4343}
4344
4345static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
4346{
4347 int ret = 0;
4348 struct device *dev = hba->dev;
4349 struct ufs_vreg_info *info = &hba->vreg_info;
4350
4351 if (!info)
4352 goto out;
4353
4354 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
4355 if (ret)
4356 goto out;
4357
4358 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
4359 if (ret)
4360 goto out;
4361
4362 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
4363 if (ret)
4364 goto out;
4365
4366out:
4367 if (ret) {
4368 ufshcd_toggle_vreg(dev, info->vccq2, false);
4369 ufshcd_toggle_vreg(dev, info->vccq, false);
4370 ufshcd_toggle_vreg(dev, info->vcc, false);
4371 }
4372 return ret;
4373}
4374
6a771a65
RS		 4375static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
4376{
4377 struct ufs_vreg_info *info = &hba->vreg_info;
4378
4379 if (info)
4380 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
4381
4382 return 0;
4383}
4384
aa497613
SRT		 4385static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
4386{
4387 int ret = 0;
4388
4389 if (!vreg)
4390 goto out;
4391
4392 vreg->reg = devm_regulator_get(dev, vreg->name);
4393 if (IS_ERR(vreg->reg)) {
4394 ret = PTR_ERR(vreg->reg);
4395 dev_err(dev, "%s: %s get failed, err=%d\n",
4396 __func__, vreg->name, ret);
4397 }
4398out:
4399 return ret;
4400}
4401
4402static int ufshcd_init_vreg(struct ufs_hba *hba)
4403{
4404 int ret = 0;
4405 struct device *dev = hba->dev;
4406 struct ufs_vreg_info *info = &hba->vreg_info;
4407
4408 if (!info)
4409 goto out;
4410
4411 ret = ufshcd_get_vreg(dev, info->vcc);
4412 if (ret)
4413 goto out;
4414
4415 ret = ufshcd_get_vreg(dev, info->vccq);
4416 if (ret)
4417 goto out;
4418
4419 ret = ufshcd_get_vreg(dev, info->vccq2);
4420out:
4421 return ret;
4422}
4423
6a771a65
RS		 4424static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
4425{
4426 struct ufs_vreg_info *info = &hba->vreg_info;
4427
4428 if (info)
4429 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
4430
4431 return 0;
4432}
4433
57d104c1
SJ		 4434static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
4435 bool skip_ref_clk)
c6e79dac
SRT		 4436{
4437 int ret = 0;
4438 struct ufs_clk_info *clki;
4439 struct list_head *head = &hba->clk_list_head;
1ab27c9c 4440 unsigned long flags;
c6e79dac
SRT		 4441
4442 if (!head || list_empty(head))
4443 goto out;
4444
4445 list_for_each_entry(clki, head, list) {
4446 if (!IS_ERR_OR_NULL(clki->clk)) {
57d104c1
SJ		 4447 if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
4448 continue;
4449
c6e79dac
SRT		 4450 if (on && !clki->enabled) {
4451 ret = clk_prepare_enable(clki->clk);
4452 if (ret) {
4453 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
4454 __func__, clki->name, ret);
4455 goto out;
4456 }
4457 } else if (!on && clki->enabled) {
4458 clk_disable_unprepare(clki->clk);
4459 }
4460 clki->enabled = on;
4461 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
4462 clki->name, on ? "en" : "dis");
4463 }
4464 }
1ab27c9c
ST		 4465
4466 if (hba->vops && hba->vops->setup_clocks)
4467 ret = hba->vops->setup_clocks(hba, on);
c6e79dac
SRT		 4468out:
4469 if (ret) {
4470 list_for_each_entry(clki, head, list) {
4471 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
4472 clk_disable_unprepare(clki->clk);
4473 }
1ab27c9c
ST		 4474 } else if (!ret && on) {
4475 spin_lock_irqsave(hba->host->host_lock, flags);
4476 hba->clk_gating.state = CLKS_ON;
4477 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac
SRT		 4478 }
4479 return ret;
4480}
4481
57d104c1
SJ		 4482static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
4483{
4484 return __ufshcd_setup_clocks(hba, on, false);
4485}
4486
c6e79dac
SRT		 4487static int ufshcd_init_clocks(struct ufs_hba *hba)
4488{
4489 int ret = 0;
4490 struct ufs_clk_info *clki;
4491 struct device *dev = hba->dev;
4492 struct list_head *head = &hba->clk_list_head;
4493
4494 if (!head || list_empty(head))
4495 goto out;
4496
4497 list_for_each_entry(clki, head, list) {
4498 if (!clki->name)
4499 continue;
4500
4501 clki->clk = devm_clk_get(dev, clki->name);
4502 if (IS_ERR(clki->clk)) {
4503 ret = PTR_ERR(clki->clk);
4504 dev_err(dev, "%s: %s clk get failed, %d\n",
4505 __func__, clki->name, ret);
4506 goto out;
4507 }
4508
4509 if (clki->max_freq) {
4510 ret = clk_set_rate(clki->clk, clki->max_freq);
4511 if (ret) {
4512 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
4513 __func__, clki->name,
4514 clki->max_freq, ret);
4515 goto out;
4516 }
856b3483 4517 clki->curr_freq = clki->max_freq;
c6e79dac
SRT		 4518 }
4519 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
4520 clki->name, clk_get_rate(clki->clk));
4521 }
4522out:
4523 return ret;
4524}
4525
5c0c28a8
SRT		 4526static int ufshcd_variant_hba_init(struct ufs_hba *hba)
4527{
4528 int err = 0;
4529
4530 if (!hba->vops)
4531 goto out;
4532
4533 if (hba->vops->init) {
4534 err = hba->vops->init(hba);
4535 if (err)
4536 goto out;
4537 }
4538
5c0c28a8
SRT		 4539 if (hba->vops->setup_regulators) {
4540 err = hba->vops->setup_regulators(hba, true);
4541 if (err)
1ab27c9c 4542 goto out_exit;
5c0c28a8
SRT		 4543 }
4544
4545 goto out;
4546
5c0c28a8
SRT		 4547out_exit:
4548 if (hba->vops->exit)
4549 hba->vops->exit(hba);
4550out:
4551 if (err)
4552 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
4553 __func__, hba->vops ? hba->vops->name : "", err);
4554 return err;
4555}
4556
4557static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
4558{
4559 if (!hba->vops)
4560 return;
4561
4562 if (hba->vops->setup_clocks)
4563 hba->vops->setup_clocks(hba, false);
4564
4565 if (hba->vops->setup_regulators)
4566 hba->vops->setup_regulators(hba, false);
4567
4568 if (hba->vops->exit)
4569 hba->vops->exit(hba);
4570}
4571
aa497613
SRT		 4572static int ufshcd_hba_init(struct ufs_hba *hba)
4573{
4574 int err;
4575
6a771a65
RS		 4576 /*
4577 * Handle host controller power separately from the UFS device power
4578 * rails as it will help controlling the UFS host controller power
4579 * collapse easily which is different than UFS device power collapse.
4580 * Also, enable the host controller power before we go ahead with rest
4581 * of the initialization here.
4582 */
4583 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 4584 if (err)
4585 goto out;
4586
6a771a65 4587 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 4588 if (err)
4589 goto out;
4590
6a771a65
RS		 4591 err = ufshcd_init_clocks(hba);
4592 if (err)
4593 goto out_disable_hba_vreg;
4594
4595 err = ufshcd_setup_clocks(hba, true);
4596 if (err)
4597 goto out_disable_hba_vreg;
4598
c6e79dac
SRT		 4599 err = ufshcd_init_vreg(hba);
4600 if (err)
4601 goto out_disable_clks;
4602
4603 err = ufshcd_setup_vreg(hba, true);
4604 if (err)
4605 goto out_disable_clks;
4606
aa497613
SRT		 4607 err = ufshcd_variant_hba_init(hba);
4608 if (err)
4609 goto out_disable_vreg;
4610
1d337ec2 4611 hba->is_powered = true;
aa497613
SRT		 4612 goto out;
4613
4614out_disable_vreg:
4615 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 4616out_disable_clks:
4617 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 4618out_disable_hba_vreg:
4619 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 4620out:
4621 return err;
4622}
4623
4624static void ufshcd_hba_exit(struct ufs_hba *hba)
4625{
1d337ec2
SRT		 4626 if (hba->is_powered) {
4627 ufshcd_variant_hba_exit(hba);
4628 ufshcd_setup_vreg(hba, false);
4629 ufshcd_setup_clocks(hba, false);
4630 ufshcd_setup_hba_vreg(hba, false);
4631 hba->is_powered = false;
4632 }
aa497613
SRT		 4633}
4634
57d104c1
SJ		 4635static int
4636ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
4637{
4638 unsigned char cmd[6] = {REQUEST_SENSE,
4639 0,
4640 0,
4641 0,
4642 SCSI_SENSE_BUFFERSIZE,
4643 0};
4644 char *buffer;
4645 int ret;
4646
4647 buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4648 if (!buffer) {
4649 ret = -ENOMEM;
4650 goto out;
4651 }
4652
4653 ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
4654 SCSI_SENSE_BUFFERSIZE, NULL,
4655 msecs_to_jiffies(1000), 3, NULL, REQ_PM);
4656 if (ret)
4657 pr_err("%s: failed with err %d\n", __func__, ret);
4658
4659 kfree(buffer);
4660out:
4661 return ret;
4662}
4663
4664/**
4665 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
4666 * power mode
4667 * @hba: per adapter instance
4668 * @pwr_mode: device power mode to set
4669 *
4670 * Returns 0 if requested power mode is set successfully
4671 * Returns non-zero if failed to set the requested power mode
4672 */
4673static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
4674 enum ufs_dev_pwr_mode pwr_mode)
4675{
4676 unsigned char cmd[6] = { START_STOP };
4677 struct scsi_sense_hdr sshdr;
4678 struct scsi_device *sdp = hba->sdev_ufs_device;
4679 int ret;
4680
4681 if (!sdp || !scsi_device_online(sdp))
4682 return -ENODEV;
4683
4684 /*
4685 * If scsi commands fail, the scsi mid-layer schedules scsi error-
4686 * handling, which would wait for host to be resumed. Since we know
4687 * we are functional while we are here, skip host resume in error
4688 * handling context.
4689 */
4690 hba->host->eh_noresume = 1;
4691 if (hba->wlun_dev_clr_ua) {
4692 ret = ufshcd_send_request_sense(hba, sdp);
4693 if (ret)
4694 goto out;
4695 /* Unit attention condition is cleared now */
4696 hba->wlun_dev_clr_ua = false;
4697 }
4698
4699 cmd[4] = pwr_mode << 4;
4700
4701 /*
4702 * Current function would be generally called from the power management
4703 * callbacks hence set the REQ_PM flag so that it doesn't resume the
4704 * already suspended childs.
4705 */
4706 ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
4707 START_STOP_TIMEOUT, 0, NULL, REQ_PM);
4708 if (ret) {
4709 sdev_printk(KERN_WARNING, sdp,
4710 "START_STOP failed for power mode: %d\n", pwr_mode);
4711 scsi_show_result(ret);
4712 if (driver_byte(ret) & DRIVER_SENSE) {
d811b848
HR		 4713 scsi_show_sense_hdr(sdp, NULL, &sshdr);
4714 scsi_show_extd_sense(sdp, NULL, sshdr.asc, sshdr.ascq);
57d104c1
SJ		 4715 }
4716 }
4717
4718 if (!ret)
4719 hba->curr_dev_pwr_mode = pwr_mode;
4720out:
4721 hba->host->eh_noresume = 0;
4722 return ret;
4723}
4724
4725static int ufshcd_link_state_transition(struct ufs_hba *hba,
4726 enum uic_link_state req_link_state,
4727 int check_for_bkops)
4728{
4729 int ret = 0;
4730
4731 if (req_link_state == hba->uic_link_state)
4732 return 0;
4733
4734 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
4735 ret = ufshcd_uic_hibern8_enter(hba);
4736 if (!ret)
4737 ufshcd_set_link_hibern8(hba);
4738 else
4739 goto out;
4740 }
4741 /*
4742 * If autobkops is enabled, link can't be turned off because
4743 * turning off the link would also turn off the device.
4744 */
4745 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
4746 (!check_for_bkops || (check_for_bkops &&
4747 !hba->auto_bkops_enabled))) {
4748 /*
4749 * Change controller state to "reset state" which
4750 * should also put the link in off/reset state
4751 */
4752 ufshcd_hba_stop(hba);
4753 /*
4754 * TODO: Check if we need any delay to make sure that
4755 * controller is reset
4756 */
4757 ufshcd_set_link_off(hba);
4758 }
4759
4760out:
4761 return ret;
4762}
4763
4764static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
4765{
4766 /*
4767 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
4768 * power.
4769 *
4770 * If UFS device and link is in OFF state, all power supplies (VCC,
4771 * VCCQ, VCCQ2) can be turned off if power on write protect is not
4772 * required. If UFS link is inactive (Hibern8 or OFF state) and device
4773 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
4774 *
4775 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
4776 * in low power state which would save some power.
4777 */
4778 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4779 !hba->dev_info.is_lu_power_on_wp) {
4780 ufshcd_setup_vreg(hba, false);
4781 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4782 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
4783 if (!ufshcd_is_link_active(hba)) {
4784 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
4785 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
4786 }
4787 }
4788}
4789
4790static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
4791{
4792 int ret = 0;
4793
4794 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
4795 !hba->dev_info.is_lu_power_on_wp) {
4796 ret = ufshcd_setup_vreg(hba, true);
4797 } else if (!ufshcd_is_ufs_dev_active(hba)) {
4798 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
4799 if (!ret && !ufshcd_is_link_active(hba)) {
4800 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
4801 if (ret)
4802 goto vcc_disable;
4803 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
4804 if (ret)
4805 goto vccq_lpm;
4806 }
4807 }
4808 goto out;
4809
4810vccq_lpm:
4811 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
4812vcc_disable:
4813 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
4814out:
4815 return ret;
4816}
4817
4818static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
4819{
4820 if (ufshcd_is_link_off(hba))
4821 ufshcd_setup_hba_vreg(hba, false);
4822}
4823
4824static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
4825{
4826 if (ufshcd_is_link_off(hba))
4827 ufshcd_setup_hba_vreg(hba, true);
4828}
4829
7a3e97b0 4830/**
57d104c1 4831 * ufshcd_suspend - helper function for suspend operations
3b1d0580 4832 * @hba: per adapter instance
57d104c1
SJ		 4833 * @pm_op: desired low power operation type
4834 *
4835 * This function will try to put the UFS device and link into low power
4836 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
4837 * (System PM level).
4838 *
4839 * If this function is called during shutdown, it will make sure that
4840 * both UFS device and UFS link is powered off.
7a3e97b0 4841 *
57d104c1
SJ		 4842 * NOTE: UFS device & link must be active before we enter in this function.
4843 *
4844 * Returns 0 for success and non-zero for failure
7a3e97b0 4845 */
57d104c1 4846static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 4847{
57d104c1
SJ		 4848 int ret = 0;
4849 enum ufs_pm_level pm_lvl;
4850 enum ufs_dev_pwr_mode req_dev_pwr_mode;
4851 enum uic_link_state req_link_state;
4852
4853 hba->pm_op_in_progress = 1;
4854 if (!ufshcd_is_shutdown_pm(pm_op)) {
4855 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
4856 hba->rpm_lvl : hba->spm_lvl;
4857 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
4858 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
4859 } else {
4860 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
4861 req_link_state = UIC_LINK_OFF_STATE;
4862 }
4863
7a3e97b0 4864 /*
57d104c1
SJ		 4865 * If we can't transition into any of the low power modes
4866 * just gate the clocks.
7a3e97b0 4867 */
1ab27c9c
ST		 4868 ufshcd_hold(hba, false);
4869 hba->clk_gating.is_suspended = true;
4870
57d104c1
SJ		 4871 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
4872 req_link_state == UIC_LINK_ACTIVE_STATE) {
4873 goto disable_clks;
4874 }
7a3e97b0 4875
57d104c1
SJ		 4876 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
4877 (req_link_state == hba->uic_link_state))
4878 goto out;
4879
4880 /* UFS device & link must be active before we enter in this function */
4881 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
4882 ret = -EINVAL;
4883 goto out;
4884 }
4885
4886 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 4887 if (ufshcd_can_autobkops_during_suspend(hba)) {
4888 /*
4889 * The device is idle with no requests in the queue,
4890 * allow background operations if bkops status shows
4891 * that performance might be impacted.
4892 */
4893 ret = ufshcd_urgent_bkops(hba);
4894 if (ret)
4895 goto enable_gating;
4896 } else {
4897 /* make sure that auto bkops is disabled */
4898 ufshcd_disable_auto_bkops(hba);
4899 }
57d104c1
SJ		 4900 }
4901
4902 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
4903 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
4904 !ufshcd_is_runtime_pm(pm_op))) {
4905 /* ensure that bkops is disabled */
4906 ufshcd_disable_auto_bkops(hba);
4907 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
4908 if (ret)
1ab27c9c 4909 goto enable_gating;
57d104c1
SJ		 4910 }
4911
4912 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
4913 if (ret)
4914 goto set_dev_active;
4915
4916 ufshcd_vreg_set_lpm(hba);
4917
4918disable_clks:
856b3483
ST		 4919 /*
4920 * The clock scaling needs access to controller registers. Hence, Wait
4921 * for pending clock scaling work to be done before clocks are
4922 * turned off.
4923 */
4924 if (ufshcd_is_clkscaling_enabled(hba)) {
4925 devfreq_suspend_device(hba->devfreq);
4926 hba->clk_scaling.window_start_t = 0;
4927 }
57d104c1
SJ		 4928 /*
4929 * Call vendor specific suspend callback. As these callbacks may access
4930 * vendor specific host controller register space call them before the
4931 * host clocks are ON.
4932 */
4933 if (hba->vops && hba->vops->suspend) {
4934 ret = hba->vops->suspend(hba, pm_op);
4935 if (ret)
4936 goto set_link_active;
4937 }
4938
4939 if (hba->vops && hba->vops->setup_clocks) {
4940 ret = hba->vops->setup_clocks(hba, false);
4941 if (ret)
4942 goto vops_resume;
4943 }
4944
4945 if (!ufshcd_is_link_active(hba))
4946 ufshcd_setup_clocks(hba, false);
4947 else
4948 /* If link is active, device ref_clk can't be switched off */
4949 __ufshcd_setup_clocks(hba, false, true);
4950
1ab27c9c 4951 hba->clk_gating.state = CLKS_OFF;
57d104c1
SJ		 4952 /*
4953 * Disable the host irq as host controller as there won't be any
4954 * host controller trasanction expected till resume.
4955 */
4956 ufshcd_disable_irq(hba);
4957 /* Put the host controller in low power mode if possible */
4958 ufshcd_hba_vreg_set_lpm(hba);
4959 goto out;
4960
4961vops_resume:
4962 if (hba->vops && hba->vops->resume)
4963 hba->vops->resume(hba, pm_op);
4964set_link_active:
4965 ufshcd_vreg_set_hpm(hba);
4966 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
4967 ufshcd_set_link_active(hba);
4968 else if (ufshcd_is_link_off(hba))
4969 ufshcd_host_reset_and_restore(hba);
4970set_dev_active:
4971 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
4972 ufshcd_disable_auto_bkops(hba);
1ab27c9c
ST		 4973enable_gating:
4974 hba->clk_gating.is_suspended = false;
4975 ufshcd_release(hba);
57d104c1
SJ		 4976out:
4977 hba->pm_op_in_progress = 0;
4978 return ret;
7a3e97b0
SY		 4979}
4980
4981/**
57d104c1 4982 * ufshcd_resume - helper function for resume operations
3b1d0580 4983 * @hba: per adapter instance
57d104c1 4984 * @pm_op: runtime PM or system PM
7a3e97b0 4985 *
57d104c1
SJ		 4986 * This function basically brings the UFS device, UniPro link and controller
4987 * to active state.
4988 *
4989 * Returns 0 for success and non-zero for failure
7a3e97b0 4990 */
57d104c1 4991static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 4992{
57d104c1
SJ		 4993 int ret;
4994 enum uic_link_state old_link_state;
4995
4996 hba->pm_op_in_progress = 1;
4997 old_link_state = hba->uic_link_state;
4998
4999 ufshcd_hba_vreg_set_hpm(hba);
5000 /* Make sure clocks are enabled before accessing controller */
5001 ret = ufshcd_setup_clocks(hba, true);
5002 if (ret)
5003 goto out;
5004
57d104c1
SJ		 5005 /* enable the host irq as host controller would be active soon */
5006 ret = ufshcd_enable_irq(hba);
5007 if (ret)
5008 goto disable_irq_and_vops_clks;
5009
5010 ret = ufshcd_vreg_set_hpm(hba);
5011 if (ret)
5012 goto disable_irq_and_vops_clks;
5013
7a3e97b0 5014 /*
57d104c1
SJ		 5015 * Call vendor specific resume callback. As these callbacks may access
5016 * vendor specific host controller register space call them when the
5017 * host clocks are ON.
7a3e97b0 5018 */
57d104c1
SJ		 5019 if (hba->vops && hba->vops->resume) {
5020 ret = hba->vops->resume(hba, pm_op);
5021 if (ret)
5022 goto disable_vreg;
5023 }
5024
5025 if (ufshcd_is_link_hibern8(hba)) {
5026 ret = ufshcd_uic_hibern8_exit(hba);
5027 if (!ret)
5028 ufshcd_set_link_active(hba);
5029 else
5030 goto vendor_suspend;
5031 } else if (ufshcd_is_link_off(hba)) {
5032 ret = ufshcd_host_reset_and_restore(hba);
5033 /*
5034 * ufshcd_host_reset_and_restore() should have already
5035 * set the link state as active
5036 */
5037 if (ret || !ufshcd_is_link_active(hba))
5038 goto vendor_suspend;
5039 }
5040
5041 if (!ufshcd_is_ufs_dev_active(hba)) {
5042 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
5043 if (ret)
5044 goto set_old_link_state;
5045 }
5046
374a246e
SJ		 5047 /*
5048 * If BKOPs operations are urgently needed at this moment then
5049 * keep auto-bkops enabled or else disable it.
5050 */
5051 ufshcd_urgent_bkops(hba);
1ab27c9c
ST		 5052 hba->clk_gating.is_suspended = false;
5053
856b3483
ST		 5054 if (ufshcd_is_clkscaling_enabled(hba))
5055 devfreq_resume_device(hba->devfreq);
5056
1ab27c9c
ST		 5057 /* Schedule clock gating in case of no access to UFS device yet */
5058 ufshcd_release(hba);
57d104c1
SJ		 5059 goto out;
5060
5061set_old_link_state:
5062 ufshcd_link_state_transition(hba, old_link_state, 0);
5063vendor_suspend:
5064 if (hba->vops && hba->vops->suspend)
5065 hba->vops->suspend(hba, pm_op);
5066disable_vreg:
5067 ufshcd_vreg_set_lpm(hba);
5068disable_irq_and_vops_clks:
5069 ufshcd_disable_irq(hba);
57d104c1
SJ		 5070 ufshcd_setup_clocks(hba, false);
5071out:
5072 hba->pm_op_in_progress = 0;
5073 return ret;
5074}
5075
5076/**
5077 * ufshcd_system_suspend - system suspend routine
5078 * @hba: per adapter instance
5079 * @pm_op: runtime PM or system PM
5080 *
5081 * Check the description of ufshcd_suspend() function for more details.
5082 *
5083 * Returns 0 for success and non-zero for failure
5084 */
5085int ufshcd_system_suspend(struct ufs_hba *hba)
5086{
5087 int ret = 0;
5088
5089 if (!hba || !hba->is_powered)
5090 goto out;
5091
5092 if (pm_runtime_suspended(hba->dev)) {
5093 if (hba->rpm_lvl == hba->spm_lvl)
5094 /*
5095 * There is possibility that device may still be in
5096 * active state during the runtime suspend.
5097 */
5098 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
5099 hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
5100 goto out;
5101
5102 /*
5103 * UFS device and/or UFS link low power states during runtime
5104 * suspend seems to be different than what is expected during
5105 * system suspend. Hence runtime resume the devic & link and
5106 * let the system suspend low power states to take effect.
5107 * TODO: If resume takes longer time, we might have optimize
5108 * it in future by not resuming everything if possible.
5109 */
5110 ret = ufshcd_runtime_resume(hba);
5111 if (ret)
5112 goto out;
5113 }
5114
5115 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
5116out:
e785060e
DR		 5117 if (!ret)
5118 hba->is_sys_suspended = true;
57d104c1
SJ		 5119 return ret;
5120}
5121EXPORT_SYMBOL(ufshcd_system_suspend);
5122
5123/**
5124 * ufshcd_system_resume - system resume routine
5125 * @hba: per adapter instance
5126 *
5127 * Returns 0 for success and non-zero for failure
5128 */
7a3e97b0 5129
57d104c1
SJ		 5130int ufshcd_system_resume(struct ufs_hba *hba)
5131{
5132 if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev))
5133 /*
5134 * Let the runtime resume take care of resuming
5135 * if runtime suspended.
5136 */
5137 return 0;
5138
5139 return ufshcd_resume(hba, UFS_SYSTEM_PM);
7a3e97b0 5140}
57d104c1 5141EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 5142
57d104c1
SJ		 5143/**
5144 * ufshcd_runtime_suspend - runtime suspend routine
5145 * @hba: per adapter instance
5146 *
5147 * Check the description of ufshcd_suspend() function for more details.
5148 *
5149 * Returns 0 for success and non-zero for failure
5150 */
66ec6d59
SRT		 5151int ufshcd_runtime_suspend(struct ufs_hba *hba)
5152{
57d104c1 5153 if (!hba || !hba->is_powered)
66ec6d59
SRT		 5154 return 0;
5155
57d104c1 5156 return ufshcd_suspend(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 5157}
5158EXPORT_SYMBOL(ufshcd_runtime_suspend);
5159
57d104c1
SJ		 5160/**
5161 * ufshcd_runtime_resume - runtime resume routine
5162 * @hba: per adapter instance
5163 *
5164 * This function basically brings the UFS device, UniPro link and controller
5165 * to active state. Following operations are done in this function:
5166 *
5167 * 1. Turn on all the controller related clocks
5168 * 2. Bring the UniPro link out of Hibernate state
5169 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
5170 * to active state.
5171 * 4. If auto-bkops is enabled on the device, disable it.
5172 *
5173 * So following would be the possible power state after this function return
5174 * successfully:
5175 * S1: UFS device in Active state with VCC rail ON
5176 * UniPro link in Active state
5177 * All the UFS/UniPro controller clocks are ON
5178 *
5179 * Returns 0 for success and non-zero for failure
5180 */
66ec6d59
SRT		 5181int ufshcd_runtime_resume(struct ufs_hba *hba)
5182{
57d104c1 5183 if (!hba || !hba->is_powered)
66ec6d59 5184 return 0;
57d104c1
SJ		 5185 else
5186 return ufshcd_resume(hba, UFS_RUNTIME_PM);
66ec6d59
SRT		 5187}
5188EXPORT_SYMBOL(ufshcd_runtime_resume);
5189
5190int ufshcd_runtime_idle(struct ufs_hba *hba)
5191{
5192 return 0;
5193}
5194EXPORT_SYMBOL(ufshcd_runtime_idle);
5195
57d104c1
SJ		 5196/**
5197 * ufshcd_shutdown - shutdown routine
5198 * @hba: per adapter instance
5199 *
5200 * This function would power off both UFS device and UFS link.
5201 *
5202 * Returns 0 always to allow force shutdown even in case of errors.
5203 */
5204int ufshcd_shutdown(struct ufs_hba *hba)
5205{
5206 int ret = 0;
5207
5208 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
5209 goto out;
5210
5211 if (pm_runtime_suspended(hba->dev)) {
5212 ret = ufshcd_runtime_resume(hba);
5213 if (ret)
5214 goto out;
5215 }
5216
5217 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
5218out:
5219 if (ret)
5220 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
5221 /* allow force shutdown even in case of errors */
5222 return 0;
5223}
5224EXPORT_SYMBOL(ufshcd_shutdown);
5225
7a3e97b0 5226/**
3b1d0580 5227 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 5228 * data structure memory
3b1d0580 5229 * @hba - per adapter instance
7a3e97b0 5230 */
3b1d0580 5231void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 5232{
cfdf9c91 5233 scsi_remove_host(hba->host);
2a8fa600 5234 ufshcd_scsi_remove_wlus(hba);
7a3e97b0 5235 /* disable interrupts */
2fbd009b 5236 ufshcd_disable_intr(hba, hba->intr_mask);
7a3e97b0 5237 ufshcd_hba_stop(hba);
7a3e97b0 5238
7a3e97b0 5239 scsi_host_put(hba->host);
5c0c28a8 5240
1ab27c9c 5241 ufshcd_exit_clk_gating(hba);
856b3483
ST		 5242 if (ufshcd_is_clkscaling_enabled(hba))
5243 devfreq_remove_device(hba->devfreq);
aa497613 5244 ufshcd_hba_exit(hba);
3b1d0580
VH		 5245}
5246EXPORT_SYMBOL_GPL(ufshcd_remove);
5247
ca3d7bf9
AM		 5248/**
5249 * ufshcd_set_dma_mask - Set dma mask based on the controller
5250 * addressing capability
5251 * @hba: per adapter instance
5252 *
5253 * Returns 0 for success, non-zero for failure
5254 */
5255static int ufshcd_set_dma_mask(struct ufs_hba *hba)
5256{
5257 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
5258 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
5259 return 0;
5260 }
5261 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
5262}
5263
7a3e97b0 5264/**
5c0c28a8 5265 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 5266 * @dev: pointer to device handle
5267 * @hba_handle: driver private handle
7a3e97b0
SY		 5268 * Returns 0 on success, non-zero value on failure
5269 */
5c0c28a8 5270int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 5271{
5272 struct Scsi_Host *host;
5273 struct ufs_hba *hba;
5c0c28a8 5274 int err = 0;
7a3e97b0 5275
3b1d0580
VH		 5276 if (!dev) {
5277 dev_err(dev,
5278 "Invalid memory reference for dev is NULL\n");
5279 err = -ENODEV;
7a3e97b0
SY		 5280 goto out_error;
5281 }
5282
7a3e97b0
SY		 5283 host = scsi_host_alloc(&ufshcd_driver_template,
5284 sizeof(struct ufs_hba));
5285 if (!host) {
3b1d0580 5286 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 5287 err = -ENOMEM;
3b1d0580 5288 goto out_error;
7a3e97b0
SY		 5289 }
5290 hba = shost_priv(host);
7a3e97b0 5291 hba->host = host;
3b1d0580 5292 hba->dev = dev;
5c0c28a8
SRT		 5293 *hba_handle = hba;
5294
5295out_error:
5296 return err;
5297}
5298EXPORT_SYMBOL(ufshcd_alloc_host);
5299
856b3483
ST		 5300static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
5301{
5302 int ret = 0;
5303 struct ufs_clk_info *clki;
5304 struct list_head *head = &hba->clk_list_head;
5305
5306 if (!head || list_empty(head))
5307 goto out;
5308
5309 list_for_each_entry(clki, head, list) {
5310 if (!IS_ERR_OR_NULL(clki->clk)) {
5311 if (scale_up && clki->max_freq) {
5312 if (clki->curr_freq == clki->max_freq)
5313 continue;
5314 ret = clk_set_rate(clki->clk, clki->max_freq);
5315 if (ret) {
5316 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5317 __func__, clki->name,
5318 clki->max_freq, ret);
5319 break;
5320 }
5321 clki->curr_freq = clki->max_freq;
5322
5323 } else if (!scale_up && clki->min_freq) {
5324 if (clki->curr_freq == clki->min_freq)
5325 continue;
5326 ret = clk_set_rate(clki->clk, clki->min_freq);
5327 if (ret) {
5328 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
5329 __func__, clki->name,
5330 clki->min_freq, ret);
5331 break;
5332 }
5333 clki->curr_freq = clki->min_freq;
5334 }
5335 }
5336 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
5337 clki->name, clk_get_rate(clki->clk));
5338 }
5339 if (hba->vops->clk_scale_notify)
5340 hba->vops->clk_scale_notify(hba);
5341out:
5342 return ret;
5343}
5344
5345static int ufshcd_devfreq_target(struct device *dev,
5346 unsigned long *freq, u32 flags)
5347{
5348 int err = 0;
5349 struct ufs_hba *hba = dev_get_drvdata(dev);
5350
5351 if (!ufshcd_is_clkscaling_enabled(hba))
5352 return -EINVAL;
5353
5354 if (*freq == UINT_MAX)
5355 err = ufshcd_scale_clks(hba, true);
5356 else if (*freq == 0)
5357 err = ufshcd_scale_clks(hba, false);
5358
5359 return err;
5360}
5361
5362static int ufshcd_devfreq_get_dev_status(struct device *dev,
5363 struct devfreq_dev_status *stat)
5364{
5365 struct ufs_hba *hba = dev_get_drvdata(dev);
5366 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
5367 unsigned long flags;
5368
5369 if (!ufshcd_is_clkscaling_enabled(hba))
5370 return -EINVAL;
5371
5372 memset(stat, 0, sizeof(*stat));
5373
5374 spin_lock_irqsave(hba->host->host_lock, flags);
5375 if (!scaling->window_start_t)
5376 goto start_window;
5377
5378 if (scaling->is_busy_started)
5379 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
5380 scaling->busy_start_t));
5381
5382 stat->total_time = jiffies_to_usecs((long)jiffies -
5383 (long)scaling->window_start_t);
5384 stat->busy_time = scaling->tot_busy_t;
5385start_window:
5386 scaling->window_start_t = jiffies;
5387 scaling->tot_busy_t = 0;
5388
5389 if (hba->outstanding_reqs) {
5390 scaling->busy_start_t = ktime_get();
5391 scaling->is_busy_started = true;
5392 } else {
5393 scaling->busy_start_t = ktime_set(0, 0);
5394 scaling->is_busy_started = false;
5395 }
5396 spin_unlock_irqrestore(hba->host->host_lock, flags);
5397 return 0;
5398}
5399
5400static struct devfreq_dev_profile ufs_devfreq_profile = {
5401 .polling_ms = 100,
5402 .target = ufshcd_devfreq_target,
5403 .get_dev_status = ufshcd_devfreq_get_dev_status,
5404};
5405
5c0c28a8
SRT		 5406/**
5407 * ufshcd_init - Driver initialization routine
5408 * @hba: per-adapter instance
5409 * @mmio_base: base register address
5410 * @irq: Interrupt line of device
5411 * Returns 0 on success, non-zero value on failure
5412 */
5413int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
5414{
5415 int err;
5416 struct Scsi_Host *host = hba->host;
5417 struct device *dev = hba->dev;
5418
5419 if (!mmio_base) {
5420 dev_err(hba->dev,
5421 "Invalid memory reference for mmio_base is NULL\n");
5422 err = -ENODEV;
5423 goto out_error;
5424 }
5425
3b1d0580
VH		 5426 hba->mmio_base = mmio_base;
5427 hba->irq = irq;
7a3e97b0 5428
aa497613 5429 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 5430 if (err)
5431 goto out_error;
5432
7a3e97b0
SY		 5433 /* Read capabilities registers */
5434 ufshcd_hba_capabilities(hba);
5435
5436 /* Get UFS version supported by the controller */
5437 hba->ufs_version = ufshcd_get_ufs_version(hba);
5438
2fbd009b
SJ		 5439 /* Get Interrupt bit mask per version */
5440 hba->intr_mask = ufshcd_get_intr_mask(hba);
5441
ca3d7bf9
AM		 5442 err = ufshcd_set_dma_mask(hba);
5443 if (err) {
5444 dev_err(hba->dev, "set dma mask failed\n");
5445 goto out_disable;
5446 }
5447
7a3e97b0
SY		 5448 /* Allocate memory for host memory space */
5449 err = ufshcd_memory_alloc(hba);
5450 if (err) {
3b1d0580
VH		 5451 dev_err(hba->dev, "Memory allocation failed\n");
5452 goto out_disable;
7a3e97b0
SY		 5453 }
5454
5455 /* Configure LRB */
5456 ufshcd_host_memory_configure(hba);
5457
5458 host->can_queue = hba->nutrs;
5459 host->cmd_per_lun = hba->nutrs;
5460 host->max_id = UFSHCD_MAX_ID;
0ce147d4 5461 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 5462 host->max_channel = UFSHCD_MAX_CHANNEL;
5463 host->unique_id = host->host_no;
5464 host->max_cmd_len = MAX_CDB_SIZE;
5465
7eb584db
DR		 5466 hba->max_pwr_info.is_valid = false;
5467
7a3e97b0 5468 /* Initailize wait queue for task management */
e2933132
SRT		 5469 init_waitqueue_head(&hba->tm_wq);
5470 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 5471
5472 /* Initialize work queues */
e8e7f271 5473 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 5474 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 5475
6ccf44fe
SJ		 5476 /* Initialize UIC command mutex */
5477 mutex_init(&hba->uic_cmd_mutex);
5478
5a0b0cb9
SRT		 5479 /* Initialize mutex for device management commands */
5480 mutex_init(&hba->dev_cmd.lock);
5481
5482 /* Initialize device management tag acquire wait queue */
5483 init_waitqueue_head(&hba->dev_cmd.tag_wq);
5484
1ab27c9c 5485 ufshcd_init_clk_gating(hba);
7a3e97b0 5486 /* IRQ registration */
2953f850 5487 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 5488 if (err) {
3b1d0580 5489 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 5490 goto exit_gating;
57d104c1
SJ		 5491 } else {
5492 hba->is_irq_enabled = true;
7a3e97b0
SY		 5493 }
5494
5495 /* Enable SCSI tag mapping */
5496 err = scsi_init_shared_tag_map(host, host->can_queue);
5497 if (err) {
3b1d0580 5498 dev_err(hba->dev, "init shared queue failed\n");
1ab27c9c 5499 goto exit_gating;
7a3e97b0
SY		 5500 }
5501
3b1d0580 5502 err = scsi_add_host(host, hba->dev);
7a3e97b0 5503 if (err) {
3b1d0580 5504 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 5505 goto exit_gating;
7a3e97b0
SY		 5506 }
5507
6ccf44fe
SJ		 5508 /* Host controller enable */
5509 err = ufshcd_hba_enable(hba);
7a3e97b0 5510 if (err) {
6ccf44fe 5511 dev_err(hba->dev, "Host controller enable failed\n");
3b1d0580 5512 goto out_remove_scsi_host;
7a3e97b0 5513 }
6ccf44fe 5514
856b3483
ST		 5515 if (ufshcd_is_clkscaling_enabled(hba)) {
5516 hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
5517 "simple_ondemand", NULL);
5518 if (IS_ERR(hba->devfreq)) {
5519 dev_err(hba->dev, "Unable to register with devfreq %ld\n",
5520 PTR_ERR(hba->devfreq));
5521 goto out_remove_scsi_host;
5522 }
5523 /* Suspend devfreq until the UFS device is detected */
5524 devfreq_suspend_device(hba->devfreq);
5525 hba->clk_scaling.window_start_t = 0;
5526 }
5527
62694735
SRT		 5528 /* Hold auto suspend until async scan completes */
5529 pm_runtime_get_sync(dev);
5530
57d104c1
SJ		 5531 /*
5532 * The device-initialize-sequence hasn't been invoked yet.
5533 * Set the device to power-off state
5534 */
5535 ufshcd_set_ufs_dev_poweroff(hba);
5536
6ccf44fe
SJ		 5537 async_schedule(ufshcd_async_scan, hba);
5538
7a3e97b0
SY		 5539 return 0;
5540
3b1d0580
VH		 5541out_remove_scsi_host:
5542 scsi_remove_host(hba->host);
1ab27c9c
ST		 5543exit_gating:
5544 ufshcd_exit_clk_gating(hba);
3b1d0580 5545out_disable:
57d104c1 5546 hba->is_irq_enabled = false;
3b1d0580 5547 scsi_host_put(host);
aa497613 5548 ufshcd_hba_exit(hba);
3b1d0580
VH		 5549out_error:
5550 return err;
5551}
5552EXPORT_SYMBOL_GPL(ufshcd_init);
5553
3b1d0580
VH		 5554MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
5555MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 5556MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 5557MODULE_LICENSE("GPL");
5558MODULE_VERSION(UFSHCD_DRIVER_VERSION);