Commit | Line | Data |
---|---|---|
7a3e97b0 | 1 | /* |
e0eca63e | 2 | * Universal Flash Storage Host controller driver Core |
7a3e97b0 SY |
3 | * |
4 | * This code is based on drivers/scsi/ufs/ufshcd.c | |
3b1d0580 | 5 | * Copyright (C) 2011-2013 Samsung India Software Operations |
5c0c28a8 | 6 | * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
7a3e97b0 | 7 | * |
3b1d0580 VH |
8 | * Authors: |
9 | * Santosh Yaraganavi <santosh.sy@samsung.com> | |
10 | * Vinayak Holikatti <h.vinayak@samsung.com> | |
7a3e97b0 SY |
11 | * |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version 2 | |
15 | * of the License, or (at your option) any later version. | |
3b1d0580 VH |
16 | * See the COPYING file in the top-level directory or visit |
17 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
7a3e97b0 SY |
18 | * |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
3b1d0580 VH |
24 | * This program is provided "AS IS" and "WITH ALL FAULTS" and |
25 | * without warranty of any kind. You are solely responsible for | |
26 | * determining the appropriateness of using and distributing | |
27 | * the program and assume all risks associated with your exercise | |
28 | * of rights with respect to the program, including but not limited | |
29 | * to infringement of third party rights, the risks and costs of | |
30 | * program errors, damage to or loss of data, programs or equipment, | |
31 | * and unavailability or interruption of operations. Under no | |
32 | * circumstances will the contributor of this Program be liable for | |
33 | * any damages of any kind arising from your use or distribution of | |
34 | * this program. | |
5c0c28a8 SRT |
35 | * |
36 | * The Linux Foundation chooses to take subject only to the GPLv2 | |
37 | * license terms, and distributes only under these terms. | |
7a3e97b0 SY |
38 | */ |
39 | ||
6ccf44fe SJ |
40 | #include <linux/async.h> |
41 | ||
e0eca63e | 42 | #include "ufshcd.h" |
53b3d9c3 | 43 | #include "unipro.h" |
7a3e97b0 | 44 | |
2fbd009b SJ |
45 | #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ |
46 | UTP_TASK_REQ_COMPL |\ | |
53b3d9c3 | 47 | UIC_POWER_MODE |\ |
2fbd009b | 48 | UFSHCD_ERROR_MASK) |
6ccf44fe SJ |
49 | /* UIC command timeout, unit: ms */ |
50 | #define UIC_CMD_TIMEOUT 500 | |
2fbd009b | 51 | |
5a0b0cb9 SRT |
52 | /* NOP OUT retries waiting for NOP IN response */ |
53 | #define NOP_OUT_RETRIES 10 | |
54 | /* Timeout after 30 msecs if NOP OUT hangs without response */ | |
55 | #define NOP_OUT_TIMEOUT 30 /* msecs */ | |
56 | ||
68078d5c DR |
57 | /* Query request retries */ |
58 | #define QUERY_REQ_RETRIES 10 | |
59 | /* Query request timeout */ | |
60 | #define QUERY_REQ_TIMEOUT 30 /* msec */ | |
61 | ||
e2933132 SRT |
62 | /* Task management command timeout */ |
63 | #define TM_CMD_TIMEOUT 100 /* msecs */ | |
64 | ||
1d337ec2 SRT |
65 | /* maximum number of link-startup retries */ |
66 | #define DME_LINKSTARTUP_RETRIES 3 | |
67 | ||
68 | /* maximum number of reset retries before giving up */ | |
69 | #define MAX_HOST_RESET_RETRIES 5 | |
70 | ||
68078d5c DR |
71 | /* Expose the flag value from utp_upiu_query.value */ |
72 | #define MASK_QUERY_UPIU_FLAG_LOC 0xFF | |
73 | ||
7d568652 SJ |
74 | /* Interrupt aggregation default timeout, unit: 40us */ |
75 | #define INT_AGGR_DEF_TO 0x02 | |
76 | ||
aa497613 SRT |
77 | #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ |
78 | ({ \ | |
79 | int _ret; \ | |
80 | if (_on) \ | |
81 | _ret = ufshcd_enable_vreg(_dev, _vreg); \ | |
82 | else \ | |
83 | _ret = ufshcd_disable_vreg(_dev, _vreg); \ | |
84 | _ret; \ | |
85 | }) | |
86 | ||
da461cec SJ |
87 | static u32 ufs_query_desc_max_size[] = { |
88 | QUERY_DESC_DEVICE_MAX_SIZE, | |
89 | QUERY_DESC_CONFIGURAION_MAX_SIZE, | |
90 | QUERY_DESC_UNIT_MAX_SIZE, | |
91 | QUERY_DESC_RFU_MAX_SIZE, | |
92 | QUERY_DESC_INTERCONNECT_MAX_SIZE, | |
93 | QUERY_DESC_STRING_MAX_SIZE, | |
94 | QUERY_DESC_RFU_MAX_SIZE, | |
95 | QUERY_DESC_GEOMETRY_MAZ_SIZE, | |
96 | QUERY_DESC_POWER_MAX_SIZE, | |
97 | QUERY_DESC_RFU_MAX_SIZE, | |
98 | }; | |
99 | ||
7a3e97b0 SY |
100 | enum { |
101 | UFSHCD_MAX_CHANNEL = 0, | |
102 | UFSHCD_MAX_ID = 1, | |
103 | UFSHCD_MAX_LUNS = 8, | |
104 | UFSHCD_CMD_PER_LUN = 32, | |
105 | UFSHCD_CAN_QUEUE = 32, | |
106 | }; | |
107 | ||
108 | /* UFSHCD states */ | |
109 | enum { | |
7a3e97b0 SY |
110 | UFSHCD_STATE_RESET, |
111 | UFSHCD_STATE_ERROR, | |
3441da7d SRT |
112 | UFSHCD_STATE_OPERATIONAL, |
113 | }; | |
114 | ||
115 | /* UFSHCD error handling flags */ | |
116 | enum { | |
117 | UFSHCD_EH_IN_PROGRESS = (1 << 0), | |
7a3e97b0 SY |
118 | }; |
119 | ||
e8e7f271 SRT |
120 | /* UFSHCD UIC layer error flags */ |
121 | enum { | |
122 | UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ | |
123 | UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */ | |
124 | UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */ | |
125 | UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */ | |
126 | }; | |
127 | ||
7a3e97b0 SY |
128 | /* Interrupt configuration options */ |
129 | enum { | |
130 | UFSHCD_INT_DISABLE, | |
131 | UFSHCD_INT_ENABLE, | |
132 | UFSHCD_INT_CLEAR, | |
133 | }; | |
134 | ||
3441da7d SRT |
135 | #define ufshcd_set_eh_in_progress(h) \ |
136 | (h->eh_flags |= UFSHCD_EH_IN_PROGRESS) | |
137 | #define ufshcd_eh_in_progress(h) \ | |
138 | (h->eh_flags & UFSHCD_EH_IN_PROGRESS) | |
139 | #define ufshcd_clear_eh_in_progress(h) \ | |
140 | (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) | |
141 | ||
142 | static void ufshcd_tmc_handler(struct ufs_hba *hba); | |
143 | static void ufshcd_async_scan(void *data, async_cookie_t cookie); | |
e8e7f271 SRT |
144 | static int ufshcd_reset_and_restore(struct ufs_hba *hba); |
145 | static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); | |
1d337ec2 SRT |
146 | static void ufshcd_hba_exit(struct ufs_hba *hba); |
147 | static int ufshcd_probe_hba(struct ufs_hba *hba); | |
3441da7d | 148 | |
5a0b0cb9 SRT |
149 | /* |
150 | * ufshcd_wait_for_register - wait for register value to change | |
151 | * @hba - per-adapter interface | |
152 | * @reg - mmio register offset | |
153 | * @mask - mask to apply to read register value | |
154 | * @val - wait condition | |
155 | * @interval_us - polling interval in microsecs | |
156 | * @timeout_ms - timeout in millisecs | |
157 | * | |
158 | * Returns -ETIMEDOUT on error, zero on success | |
159 | */ | |
160 | static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, | |
161 | u32 val, unsigned long interval_us, unsigned long timeout_ms) | |
162 | { | |
163 | int err = 0; | |
164 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); | |
165 | ||
166 | /* ignore bits that we don't intend to wait on */ | |
167 | val = val & mask; | |
168 | ||
169 | while ((ufshcd_readl(hba, reg) & mask) != val) { | |
170 | /* wakeup within 50us of expiry */ | |
171 | usleep_range(interval_us, interval_us + 50); | |
172 | ||
173 | if (time_after(jiffies, timeout)) { | |
174 | if ((ufshcd_readl(hba, reg) & mask) != val) | |
175 | err = -ETIMEDOUT; | |
176 | break; | |
177 | } | |
178 | } | |
179 | ||
180 | return err; | |
181 | } | |
182 | ||
2fbd009b SJ |
183 | /** |
184 | * ufshcd_get_intr_mask - Get the interrupt bit mask | |
185 | * @hba - Pointer to adapter instance | |
186 | * | |
187 | * Returns interrupt bit mask per version | |
188 | */ | |
189 | static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) | |
190 | { | |
191 | if (hba->ufs_version == UFSHCI_VERSION_10) | |
192 | return INTERRUPT_MASK_ALL_VER_10; | |
193 | else | |
194 | return INTERRUPT_MASK_ALL_VER_11; | |
195 | } | |
196 | ||
7a3e97b0 SY |
197 | /** |
198 | * ufshcd_get_ufs_version - Get the UFS version supported by the HBA | |
199 | * @hba - Pointer to adapter instance | |
200 | * | |
201 | * Returns UFSHCI version supported by the controller | |
202 | */ | |
203 | static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) | |
204 | { | |
b873a275 | 205 | return ufshcd_readl(hba, REG_UFS_VERSION); |
7a3e97b0 SY |
206 | } |
207 | ||
208 | /** | |
209 | * ufshcd_is_device_present - Check if any device connected to | |
210 | * the host controller | |
5c0c28a8 | 211 | * @hba: pointer to adapter instance |
7a3e97b0 | 212 | * |
73ec513a | 213 | * Returns 1 if device present, 0 if no device detected |
7a3e97b0 | 214 | */ |
5c0c28a8 | 215 | static inline int ufshcd_is_device_present(struct ufs_hba *hba) |
7a3e97b0 | 216 | { |
5c0c28a8 SRT |
217 | return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & |
218 | DEVICE_PRESENT) ? 1 : 0; | |
7a3e97b0 SY |
219 | } |
220 | ||
221 | /** | |
222 | * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status | |
223 | * @lrb: pointer to local command reference block | |
224 | * | |
225 | * This function is used to get the OCS field from UTRD | |
226 | * Returns the OCS field in the UTRD | |
227 | */ | |
228 | static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp) | |
229 | { | |
e8c8e82a | 230 | return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS; |
7a3e97b0 SY |
231 | } |
232 | ||
233 | /** | |
234 | * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status | |
235 | * @task_req_descp: pointer to utp_task_req_desc structure | |
236 | * | |
237 | * This function is used to get the OCS field from UTMRD | |
238 | * Returns the OCS field in the UTMRD | |
239 | */ | |
240 | static inline int | |
241 | ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp) | |
242 | { | |
e8c8e82a | 243 | return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS; |
7a3e97b0 SY |
244 | } |
245 | ||
246 | /** | |
247 | * ufshcd_get_tm_free_slot - get a free slot for task management request | |
248 | * @hba: per adapter instance | |
e2933132 | 249 | * @free_slot: pointer to variable with available slot value |
7a3e97b0 | 250 | * |
e2933132 SRT |
251 | * Get a free tag and lock it until ufshcd_put_tm_slot() is called. |
252 | * Returns 0 if free slot is not available, else return 1 with tag value | |
253 | * in @free_slot. | |
7a3e97b0 | 254 | */ |
e2933132 | 255 | static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot) |
7a3e97b0 | 256 | { |
e2933132 SRT |
257 | int tag; |
258 | bool ret = false; | |
259 | ||
260 | if (!free_slot) | |
261 | goto out; | |
262 | ||
263 | do { | |
264 | tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs); | |
265 | if (tag >= hba->nutmrs) | |
266 | goto out; | |
267 | } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use)); | |
268 | ||
269 | *free_slot = tag; | |
270 | ret = true; | |
271 | out: | |
272 | return ret; | |
273 | } | |
274 | ||
275 | static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot) | |
276 | { | |
277 | clear_bit_unlock(slot, &hba->tm_slots_in_use); | |
7a3e97b0 SY |
278 | } |
279 | ||
280 | /** | |
281 | * ufshcd_utrl_clear - Clear a bit in UTRLCLR register | |
282 | * @hba: per adapter instance | |
283 | * @pos: position of the bit to be cleared | |
284 | */ | |
285 | static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos) | |
286 | { | |
b873a275 | 287 | ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR); |
7a3e97b0 SY |
288 | } |
289 | ||
290 | /** | |
291 | * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY | |
292 | * @reg: Register value of host controller status | |
293 | * | |
294 | * Returns integer, 0 on Success and positive value if failed | |
295 | */ | |
296 | static inline int ufshcd_get_lists_status(u32 reg) | |
297 | { | |
298 | /* | |
299 | * The mask 0xFF is for the following HCS register bits | |
300 | * Bit Description | |
301 | * 0 Device Present | |
302 | * 1 UTRLRDY | |
303 | * 2 UTMRLRDY | |
304 | * 3 UCRDY | |
305 | * 4 HEI | |
306 | * 5 DEI | |
307 | * 6-7 reserved | |
308 | */ | |
309 | return (((reg) & (0xFF)) >> 1) ^ (0x07); | |
310 | } | |
311 | ||
312 | /** | |
313 | * ufshcd_get_uic_cmd_result - Get the UIC command result | |
314 | * @hba: Pointer to adapter instance | |
315 | * | |
316 | * This function gets the result of UIC command completion | |
317 | * Returns 0 on success, non zero value on error | |
318 | */ | |
319 | static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) | |
320 | { | |
b873a275 | 321 | return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & |
7a3e97b0 SY |
322 | MASK_UIC_COMMAND_RESULT; |
323 | } | |
324 | ||
12b4fdb4 SJ |
325 | /** |
326 | * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command | |
327 | * @hba: Pointer to adapter instance | |
328 | * | |
329 | * This function gets UIC command argument3 | |
330 | * Returns 0 on success, non zero value on error | |
331 | */ | |
332 | static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) | |
333 | { | |
334 | return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); | |
335 | } | |
336 | ||
7a3e97b0 | 337 | /** |
5a0b0cb9 | 338 | * ufshcd_get_req_rsp - returns the TR response transaction type |
7a3e97b0 | 339 | * @ucd_rsp_ptr: pointer to response UPIU |
7a3e97b0 SY |
340 | */ |
341 | static inline int | |
5a0b0cb9 | 342 | ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) |
7a3e97b0 | 343 | { |
5a0b0cb9 | 344 | return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24; |
7a3e97b0 SY |
345 | } |
346 | ||
347 | /** | |
348 | * ufshcd_get_rsp_upiu_result - Get the result from response UPIU | |
349 | * @ucd_rsp_ptr: pointer to response UPIU | |
350 | * | |
351 | * This function gets the response status and scsi_status from response UPIU | |
352 | * Returns the response result code. | |
353 | */ | |
354 | static inline int | |
355 | ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr) | |
356 | { | |
357 | return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT; | |
358 | } | |
359 | ||
1c2623c5 SJ |
360 | /* |
361 | * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length | |
362 | * from response UPIU | |
363 | * @ucd_rsp_ptr: pointer to response UPIU | |
364 | * | |
365 | * Return the data segment length. | |
366 | */ | |
367 | static inline unsigned int | |
368 | ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr) | |
369 | { | |
370 | return be32_to_cpu(ucd_rsp_ptr->header.dword_2) & | |
371 | MASK_RSP_UPIU_DATA_SEG_LEN; | |
372 | } | |
373 | ||
66ec6d59 SRT |
374 | /** |
375 | * ufshcd_is_exception_event - Check if the device raised an exception event | |
376 | * @ucd_rsp_ptr: pointer to response UPIU | |
377 | * | |
378 | * The function checks if the device raised an exception event indicated in | |
379 | * the Device Information field of response UPIU. | |
380 | * | |
381 | * Returns true if exception is raised, false otherwise. | |
382 | */ | |
383 | static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) | |
384 | { | |
385 | return be32_to_cpu(ucd_rsp_ptr->header.dword_2) & | |
386 | MASK_RSP_EXCEPTION_EVENT ? true : false; | |
387 | } | |
388 | ||
7a3e97b0 | 389 | /** |
7d568652 | 390 | * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. |
7a3e97b0 | 391 | * @hba: per adapter instance |
7a3e97b0 SY |
392 | */ |
393 | static inline void | |
7d568652 | 394 | ufshcd_reset_intr_aggr(struct ufs_hba *hba) |
7a3e97b0 | 395 | { |
7d568652 SJ |
396 | ufshcd_writel(hba, INT_AGGR_ENABLE | |
397 | INT_AGGR_COUNTER_AND_TIMER_RESET, | |
398 | REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); | |
399 | } | |
400 | ||
401 | /** | |
402 | * ufshcd_config_intr_aggr - Configure interrupt aggregation values. | |
403 | * @hba: per adapter instance | |
404 | * @cnt: Interrupt aggregation counter threshold | |
405 | * @tmout: Interrupt aggregation timeout value | |
406 | */ | |
407 | static inline void | |
408 | ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) | |
409 | { | |
410 | ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | | |
411 | INT_AGGR_COUNTER_THLD_VAL(cnt) | | |
412 | INT_AGGR_TIMEOUT_VAL(tmout), | |
413 | REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); | |
7a3e97b0 SY |
414 | } |
415 | ||
416 | /** | |
417 | * ufshcd_enable_run_stop_reg - Enable run-stop registers, | |
418 | * When run-stop registers are set to 1, it indicates the | |
419 | * host controller that it can process the requests | |
420 | * @hba: per adapter instance | |
421 | */ | |
422 | static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) | |
423 | { | |
b873a275 SJ |
424 | ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, |
425 | REG_UTP_TASK_REQ_LIST_RUN_STOP); | |
426 | ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, | |
427 | REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); | |
7a3e97b0 SY |
428 | } |
429 | ||
7a3e97b0 SY |
430 | /** |
431 | * ufshcd_hba_start - Start controller initialization sequence | |
432 | * @hba: per adapter instance | |
433 | */ | |
434 | static inline void ufshcd_hba_start(struct ufs_hba *hba) | |
435 | { | |
b873a275 | 436 | ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE); |
7a3e97b0 SY |
437 | } |
438 | ||
439 | /** | |
440 | * ufshcd_is_hba_active - Get controller state | |
441 | * @hba: per adapter instance | |
442 | * | |
443 | * Returns zero if controller is active, 1 otherwise | |
444 | */ | |
445 | static inline int ufshcd_is_hba_active(struct ufs_hba *hba) | |
446 | { | |
b873a275 | 447 | return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1; |
7a3e97b0 SY |
448 | } |
449 | ||
450 | /** | |
451 | * ufshcd_send_command - Send SCSI or device management commands | |
452 | * @hba: per adapter instance | |
453 | * @task_tag: Task tag of the command | |
454 | */ | |
455 | static inline | |
456 | void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag) | |
457 | { | |
458 | __set_bit(task_tag, &hba->outstanding_reqs); | |
b873a275 | 459 | ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); |
7a3e97b0 SY |
460 | } |
461 | ||
462 | /** | |
463 | * ufshcd_copy_sense_data - Copy sense data in case of check condition | |
464 | * @lrb - pointer to local reference block | |
465 | */ | |
466 | static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) | |
467 | { | |
468 | int len; | |
1c2623c5 SJ |
469 | if (lrbp->sense_buffer && |
470 | ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) { | |
5a0b0cb9 | 471 | len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); |
7a3e97b0 | 472 | memcpy(lrbp->sense_buffer, |
5a0b0cb9 | 473 | lrbp->ucd_rsp_ptr->sr.sense_data, |
7a3e97b0 SY |
474 | min_t(int, len, SCSI_SENSE_BUFFERSIZE)); |
475 | } | |
476 | } | |
477 | ||
68078d5c DR |
478 | /** |
479 | * ufshcd_copy_query_response() - Copy the Query Response and the data | |
480 | * descriptor | |
481 | * @hba: per adapter instance | |
482 | * @lrb - pointer to local reference block | |
483 | */ | |
484 | static | |
c6d4a831 | 485 | int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) |
68078d5c DR |
486 | { |
487 | struct ufs_query_res *query_res = &hba->dev_cmd.query.response; | |
488 | ||
68078d5c | 489 | memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); |
68078d5c | 490 | |
68078d5c DR |
491 | /* Get the descriptor */ |
492 | if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { | |
d44a5f98 | 493 | u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + |
68078d5c | 494 | GENERAL_UPIU_REQUEST_SIZE; |
c6d4a831 DR |
495 | u16 resp_len; |
496 | u16 buf_len; | |
68078d5c DR |
497 | |
498 | /* data segment length */ | |
c6d4a831 | 499 | resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) & |
68078d5c | 500 | MASK_QUERY_DATA_SEG_LEN; |
ea2aab24 SRT |
501 | buf_len = be16_to_cpu( |
502 | hba->dev_cmd.query.request.upiu_req.length); | |
c6d4a831 DR |
503 | if (likely(buf_len >= resp_len)) { |
504 | memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); | |
505 | } else { | |
506 | dev_warn(hba->dev, | |
507 | "%s: Response size is bigger than buffer", | |
508 | __func__); | |
509 | return -EINVAL; | |
510 | } | |
68078d5c | 511 | } |
c6d4a831 DR |
512 | |
513 | return 0; | |
68078d5c DR |
514 | } |
515 | ||
7a3e97b0 SY |
516 | /** |
517 | * ufshcd_hba_capabilities - Read controller capabilities | |
518 | * @hba: per adapter instance | |
519 | */ | |
520 | static inline void ufshcd_hba_capabilities(struct ufs_hba *hba) | |
521 | { | |
b873a275 | 522 | hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); |
7a3e97b0 SY |
523 | |
524 | /* nutrs and nutmrs are 0 based values */ | |
525 | hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; | |
526 | hba->nutmrs = | |
527 | ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; | |
528 | } | |
529 | ||
530 | /** | |
6ccf44fe SJ |
531 | * ufshcd_ready_for_uic_cmd - Check if controller is ready |
532 | * to accept UIC commands | |
7a3e97b0 | 533 | * @hba: per adapter instance |
6ccf44fe SJ |
534 | * Return true on success, else false |
535 | */ | |
536 | static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) | |
537 | { | |
538 | if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY) | |
539 | return true; | |
540 | else | |
541 | return false; | |
542 | } | |
543 | ||
53b3d9c3 SJ |
544 | /** |
545 | * ufshcd_get_upmcrs - Get the power mode change request status | |
546 | * @hba: Pointer to adapter instance | |
547 | * | |
548 | * This function gets the UPMCRS field of HCS register | |
549 | * Returns value of UPMCRS field | |
550 | */ | |
551 | static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) | |
552 | { | |
553 | return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; | |
554 | } | |
555 | ||
6ccf44fe SJ |
556 | /** |
557 | * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers | |
558 | * @hba: per adapter instance | |
559 | * @uic_cmd: UIC command | |
560 | * | |
561 | * Mutex must be held. | |
7a3e97b0 SY |
562 | */ |
563 | static inline void | |
6ccf44fe | 564 | ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) |
7a3e97b0 | 565 | { |
6ccf44fe SJ |
566 | WARN_ON(hba->active_uic_cmd); |
567 | ||
568 | hba->active_uic_cmd = uic_cmd; | |
569 | ||
7a3e97b0 | 570 | /* Write Args */ |
6ccf44fe SJ |
571 | ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); |
572 | ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); | |
573 | ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); | |
7a3e97b0 SY |
574 | |
575 | /* Write UIC Cmd */ | |
6ccf44fe | 576 | ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, |
b873a275 | 577 | REG_UIC_COMMAND); |
7a3e97b0 SY |
578 | } |
579 | ||
6ccf44fe SJ |
580 | /** |
581 | * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command | |
582 | * @hba: per adapter instance | |
583 | * @uic_command: UIC command | |
584 | * | |
585 | * Must be called with mutex held. | |
586 | * Returns 0 only if success. | |
587 | */ | |
588 | static int | |
589 | ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) | |
590 | { | |
591 | int ret; | |
592 | unsigned long flags; | |
593 | ||
594 | if (wait_for_completion_timeout(&uic_cmd->done, | |
595 | msecs_to_jiffies(UIC_CMD_TIMEOUT))) | |
596 | ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; | |
597 | else | |
598 | ret = -ETIMEDOUT; | |
599 | ||
600 | spin_lock_irqsave(hba->host->host_lock, flags); | |
601 | hba->active_uic_cmd = NULL; | |
602 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
603 | ||
604 | return ret; | |
605 | } | |
606 | ||
607 | /** | |
608 | * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result | |
609 | * @hba: per adapter instance | |
610 | * @uic_cmd: UIC command | |
611 | * | |
612 | * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called | |
613 | * with mutex held. | |
614 | * Returns 0 only if success. | |
615 | */ | |
616 | static int | |
617 | __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) | |
618 | { | |
619 | int ret; | |
620 | unsigned long flags; | |
621 | ||
622 | if (!ufshcd_ready_for_uic_cmd(hba)) { | |
623 | dev_err(hba->dev, | |
624 | "Controller not ready to accept UIC commands\n"); | |
625 | return -EIO; | |
626 | } | |
627 | ||
628 | init_completion(&uic_cmd->done); | |
629 | ||
630 | spin_lock_irqsave(hba->host->host_lock, flags); | |
631 | ufshcd_dispatch_uic_cmd(hba, uic_cmd); | |
632 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
633 | ||
634 | ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); | |
635 | ||
636 | return ret; | |
637 | } | |
638 | ||
639 | /** | |
640 | * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result | |
641 | * @hba: per adapter instance | |
642 | * @uic_cmd: UIC command | |
643 | * | |
644 | * Returns 0 only if success. | |
645 | */ | |
646 | static int | |
647 | ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) | |
648 | { | |
649 | int ret; | |
650 | ||
651 | mutex_lock(&hba->uic_cmd_mutex); | |
652 | ret = __ufshcd_send_uic_cmd(hba, uic_cmd); | |
653 | mutex_unlock(&hba->uic_cmd_mutex); | |
654 | ||
655 | return ret; | |
656 | } | |
657 | ||
7a3e97b0 SY |
658 | /** |
659 | * ufshcd_map_sg - Map scatter-gather list to prdt | |
660 | * @lrbp - pointer to local reference block | |
661 | * | |
662 | * Returns 0 in case of success, non-zero value in case of failure | |
663 | */ | |
664 | static int ufshcd_map_sg(struct ufshcd_lrb *lrbp) | |
665 | { | |
666 | struct ufshcd_sg_entry *prd_table; | |
667 | struct scatterlist *sg; | |
668 | struct scsi_cmnd *cmd; | |
669 | int sg_segments; | |
670 | int i; | |
671 | ||
672 | cmd = lrbp->cmd; | |
673 | sg_segments = scsi_dma_map(cmd); | |
674 | if (sg_segments < 0) | |
675 | return sg_segments; | |
676 | ||
677 | if (sg_segments) { | |
678 | lrbp->utr_descriptor_ptr->prd_table_length = | |
679 | cpu_to_le16((u16) (sg_segments)); | |
680 | ||
681 | prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr; | |
682 | ||
683 | scsi_for_each_sg(cmd, sg, sg_segments, i) { | |
684 | prd_table[i].size = | |
685 | cpu_to_le32(((u32) sg_dma_len(sg))-1); | |
686 | prd_table[i].base_addr = | |
687 | cpu_to_le32(lower_32_bits(sg->dma_address)); | |
688 | prd_table[i].upper_addr = | |
689 | cpu_to_le32(upper_32_bits(sg->dma_address)); | |
690 | } | |
691 | } else { | |
692 | lrbp->utr_descriptor_ptr->prd_table_length = 0; | |
693 | } | |
694 | ||
695 | return 0; | |
696 | } | |
697 | ||
698 | /** | |
2fbd009b | 699 | * ufshcd_enable_intr - enable interrupts |
7a3e97b0 | 700 | * @hba: per adapter instance |
2fbd009b | 701 | * @intrs: interrupt bits |
7a3e97b0 | 702 | */ |
2fbd009b | 703 | static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) |
7a3e97b0 | 704 | { |
2fbd009b SJ |
705 | u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); |
706 | ||
707 | if (hba->ufs_version == UFSHCI_VERSION_10) { | |
708 | u32 rw; | |
709 | rw = set & INTERRUPT_MASK_RW_VER_10; | |
710 | set = rw | ((set ^ intrs) & intrs); | |
711 | } else { | |
712 | set |= intrs; | |
713 | } | |
714 | ||
715 | ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); | |
716 | } | |
717 | ||
718 | /** | |
719 | * ufshcd_disable_intr - disable interrupts | |
720 | * @hba: per adapter instance | |
721 | * @intrs: interrupt bits | |
722 | */ | |
723 | static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) | |
724 | { | |
725 | u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); | |
726 | ||
727 | if (hba->ufs_version == UFSHCI_VERSION_10) { | |
728 | u32 rw; | |
729 | rw = (set & INTERRUPT_MASK_RW_VER_10) & | |
730 | ~(intrs & INTERRUPT_MASK_RW_VER_10); | |
731 | set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10); | |
732 | ||
733 | } else { | |
734 | set &= ~intrs; | |
7a3e97b0 | 735 | } |
2fbd009b SJ |
736 | |
737 | ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); | |
7a3e97b0 SY |
738 | } |
739 | ||
5a0b0cb9 SRT |
740 | /** |
741 | * ufshcd_prepare_req_desc_hdr() - Fills the requests header | |
742 | * descriptor according to request | |
743 | * @lrbp: pointer to local reference block | |
744 | * @upiu_flags: flags required in the header | |
745 | * @cmd_dir: requests data direction | |
746 | */ | |
747 | static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, | |
748 | u32 *upiu_flags, enum dma_data_direction cmd_dir) | |
749 | { | |
750 | struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; | |
751 | u32 data_direction; | |
752 | u32 dword_0; | |
753 | ||
754 | if (cmd_dir == DMA_FROM_DEVICE) { | |
755 | data_direction = UTP_DEVICE_TO_HOST; | |
756 | *upiu_flags = UPIU_CMD_FLAGS_READ; | |
757 | } else if (cmd_dir == DMA_TO_DEVICE) { | |
758 | data_direction = UTP_HOST_TO_DEVICE; | |
759 | *upiu_flags = UPIU_CMD_FLAGS_WRITE; | |
760 | } else { | |
761 | data_direction = UTP_NO_DATA_TRANSFER; | |
762 | *upiu_flags = UPIU_CMD_FLAGS_NONE; | |
763 | } | |
764 | ||
765 | dword_0 = data_direction | (lrbp->command_type | |
766 | << UPIU_COMMAND_TYPE_OFFSET); | |
767 | if (lrbp->intr_cmd) | |
768 | dword_0 |= UTP_REQ_DESC_INT_CMD; | |
769 | ||
770 | /* Transfer request descriptor header fields */ | |
771 | req_desc->header.dword_0 = cpu_to_le32(dword_0); | |
772 | ||
773 | /* | |
774 | * assigning invalid value for command status. Controller | |
775 | * updates OCS on command completion, with the command | |
776 | * status | |
777 | */ | |
778 | req_desc->header.dword_2 = | |
779 | cpu_to_le32(OCS_INVALID_COMMAND_STATUS); | |
780 | } | |
781 | ||
782 | /** | |
783 | * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, | |
784 | * for scsi commands | |
785 | * @lrbp - local reference block pointer | |
786 | * @upiu_flags - flags | |
787 | */ | |
788 | static | |
789 | void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags) | |
790 | { | |
791 | struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; | |
792 | ||
793 | /* command descriptor fields */ | |
794 | ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD( | |
795 | UPIU_TRANSACTION_COMMAND, upiu_flags, | |
796 | lrbp->lun, lrbp->task_tag); | |
797 | ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD( | |
798 | UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0); | |
799 | ||
800 | /* Total EHS length and Data segment length will be zero */ | |
801 | ucd_req_ptr->header.dword_2 = 0; | |
802 | ||
803 | ucd_req_ptr->sc.exp_data_transfer_len = | |
804 | cpu_to_be32(lrbp->cmd->sdb.length); | |
805 | ||
806 | memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, | |
807 | (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE))); | |
808 | } | |
809 | ||
68078d5c DR |
810 | /** |
811 | * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc, | |
812 | * for query requsts | |
813 | * @hba: UFS hba | |
814 | * @lrbp: local reference block pointer | |
815 | * @upiu_flags: flags | |
816 | */ | |
817 | static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, | |
818 | struct ufshcd_lrb *lrbp, u32 upiu_flags) | |
819 | { | |
820 | struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; | |
821 | struct ufs_query *query = &hba->dev_cmd.query; | |
e8c8e82a | 822 | u16 len = be16_to_cpu(query->request.upiu_req.length); |
68078d5c DR |
823 | u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE; |
824 | ||
825 | /* Query request header */ | |
826 | ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD( | |
827 | UPIU_TRANSACTION_QUERY_REQ, upiu_flags, | |
828 | lrbp->lun, lrbp->task_tag); | |
829 | ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD( | |
830 | 0, query->request.query_func, 0, 0); | |
831 | ||
832 | /* Data segment length */ | |
833 | ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD( | |
834 | 0, 0, len >> 8, (u8)len); | |
835 | ||
836 | /* Copy the Query Request buffer as is */ | |
837 | memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, | |
838 | QUERY_OSF_SIZE); | |
68078d5c DR |
839 | |
840 | /* Copy the Descriptor */ | |
c6d4a831 DR |
841 | if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) |
842 | memcpy(descp, query->descriptor, len); | |
843 | ||
68078d5c DR |
844 | } |
845 | ||
5a0b0cb9 SRT |
846 | static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) |
847 | { | |
848 | struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; | |
849 | ||
850 | memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); | |
851 | ||
852 | /* command descriptor fields */ | |
853 | ucd_req_ptr->header.dword_0 = | |
854 | UPIU_HEADER_DWORD( | |
855 | UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag); | |
856 | } | |
857 | ||
7a3e97b0 SY |
858 | /** |
859 | * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU) | |
5a0b0cb9 | 860 | * @hba - per adapter instance |
7a3e97b0 SY |
861 | * @lrb - pointer to local reference block |
862 | */ | |
5a0b0cb9 | 863 | static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) |
7a3e97b0 | 864 | { |
7a3e97b0 | 865 | u32 upiu_flags; |
5a0b0cb9 | 866 | int ret = 0; |
7a3e97b0 SY |
867 | |
868 | switch (lrbp->command_type) { | |
869 | case UTP_CMD_TYPE_SCSI: | |
5a0b0cb9 SRT |
870 | if (likely(lrbp->cmd)) { |
871 | ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, | |
872 | lrbp->cmd->sc_data_direction); | |
873 | ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); | |
7a3e97b0 | 874 | } else { |
5a0b0cb9 | 875 | ret = -EINVAL; |
7a3e97b0 | 876 | } |
7a3e97b0 SY |
877 | break; |
878 | case UTP_CMD_TYPE_DEV_MANAGE: | |
5a0b0cb9 | 879 | ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE); |
68078d5c DR |
880 | if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) |
881 | ufshcd_prepare_utp_query_req_upiu( | |
882 | hba, lrbp, upiu_flags); | |
883 | else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) | |
5a0b0cb9 SRT |
884 | ufshcd_prepare_utp_nop_upiu(lrbp); |
885 | else | |
886 | ret = -EINVAL; | |
7a3e97b0 SY |
887 | break; |
888 | case UTP_CMD_TYPE_UFS: | |
889 | /* For UFS native command implementation */ | |
5a0b0cb9 SRT |
890 | ret = -ENOTSUPP; |
891 | dev_err(hba->dev, "%s: UFS native command are not supported\n", | |
892 | __func__); | |
893 | break; | |
894 | default: | |
895 | ret = -ENOTSUPP; | |
896 | dev_err(hba->dev, "%s: unknown command type: 0x%x\n", | |
897 | __func__, lrbp->command_type); | |
7a3e97b0 SY |
898 | break; |
899 | } /* end of switch */ | |
5a0b0cb9 SRT |
900 | |
901 | return ret; | |
7a3e97b0 SY |
902 | } |
903 | ||
904 | /** | |
905 | * ufshcd_queuecommand - main entry point for SCSI requests | |
906 | * @cmd: command from SCSI Midlayer | |
907 | * @done: call back function | |
908 | * | |
909 | * Returns 0 for success, non-zero in case of failure | |
910 | */ | |
911 | static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) | |
912 | { | |
913 | struct ufshcd_lrb *lrbp; | |
914 | struct ufs_hba *hba; | |
915 | unsigned long flags; | |
916 | int tag; | |
917 | int err = 0; | |
918 | ||
919 | hba = shost_priv(host); | |
920 | ||
921 | tag = cmd->request->tag; | |
922 | ||
3441da7d SRT |
923 | spin_lock_irqsave(hba->host->host_lock, flags); |
924 | switch (hba->ufshcd_state) { | |
925 | case UFSHCD_STATE_OPERATIONAL: | |
926 | break; | |
927 | case UFSHCD_STATE_RESET: | |
7a3e97b0 | 928 | err = SCSI_MLQUEUE_HOST_BUSY; |
3441da7d SRT |
929 | goto out_unlock; |
930 | case UFSHCD_STATE_ERROR: | |
931 | set_host_byte(cmd, DID_ERROR); | |
932 | cmd->scsi_done(cmd); | |
933 | goto out_unlock; | |
934 | default: | |
935 | dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n", | |
936 | __func__, hba->ufshcd_state); | |
937 | set_host_byte(cmd, DID_BAD_TARGET); | |
938 | cmd->scsi_done(cmd); | |
939 | goto out_unlock; | |
7a3e97b0 | 940 | } |
3441da7d | 941 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
7a3e97b0 | 942 | |
5a0b0cb9 SRT |
943 | /* acquire the tag to make sure device cmds don't use it */ |
944 | if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) { | |
945 | /* | |
946 | * Dev manage command in progress, requeue the command. | |
947 | * Requeuing the command helps in cases where the request *may* | |
948 | * find different tag instead of waiting for dev manage command | |
949 | * completion. | |
950 | */ | |
951 | err = SCSI_MLQUEUE_HOST_BUSY; | |
952 | goto out; | |
953 | } | |
954 | ||
7a3e97b0 SY |
955 | lrbp = &hba->lrb[tag]; |
956 | ||
5a0b0cb9 | 957 | WARN_ON(lrbp->cmd); |
7a3e97b0 SY |
958 | lrbp->cmd = cmd; |
959 | lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE; | |
960 | lrbp->sense_buffer = cmd->sense_buffer; | |
961 | lrbp->task_tag = tag; | |
962 | lrbp->lun = cmd->device->lun; | |
5a0b0cb9 | 963 | lrbp->intr_cmd = false; |
7a3e97b0 SY |
964 | lrbp->command_type = UTP_CMD_TYPE_SCSI; |
965 | ||
966 | /* form UPIU before issuing the command */ | |
5a0b0cb9 | 967 | ufshcd_compose_upiu(hba, lrbp); |
7a3e97b0 | 968 | err = ufshcd_map_sg(lrbp); |
5a0b0cb9 SRT |
969 | if (err) { |
970 | lrbp->cmd = NULL; | |
971 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
7a3e97b0 | 972 | goto out; |
5a0b0cb9 | 973 | } |
7a3e97b0 SY |
974 | |
975 | /* issue command to the controller */ | |
976 | spin_lock_irqsave(hba->host->host_lock, flags); | |
977 | ufshcd_send_command(hba, tag); | |
3441da7d | 978 | out_unlock: |
7a3e97b0 SY |
979 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
980 | out: | |
981 | return err; | |
982 | } | |
983 | ||
5a0b0cb9 SRT |
984 | static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, |
985 | struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) | |
986 | { | |
987 | lrbp->cmd = NULL; | |
988 | lrbp->sense_bufflen = 0; | |
989 | lrbp->sense_buffer = NULL; | |
990 | lrbp->task_tag = tag; | |
991 | lrbp->lun = 0; /* device management cmd is not specific to any LUN */ | |
992 | lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; | |
993 | lrbp->intr_cmd = true; /* No interrupt aggregation */ | |
994 | hba->dev_cmd.type = cmd_type; | |
995 | ||
996 | return ufshcd_compose_upiu(hba, lrbp); | |
997 | } | |
998 | ||
999 | static int | |
1000 | ufshcd_clear_cmd(struct ufs_hba *hba, int tag) | |
1001 | { | |
1002 | int err = 0; | |
1003 | unsigned long flags; | |
1004 | u32 mask = 1 << tag; | |
1005 | ||
1006 | /* clear outstanding transaction before retry */ | |
1007 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1008 | ufshcd_utrl_clear(hba, tag); | |
1009 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1010 | ||
1011 | /* | |
1012 | * wait for for h/w to clear corresponding bit in door-bell. | |
1013 | * max. wait is 1 sec. | |
1014 | */ | |
1015 | err = ufshcd_wait_for_register(hba, | |
1016 | REG_UTP_TRANSFER_REQ_DOOR_BELL, | |
1017 | mask, ~mask, 1000, 1000); | |
1018 | ||
1019 | return err; | |
1020 | } | |
1021 | ||
c6d4a831 DR |
1022 | static int |
1023 | ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) | |
1024 | { | |
1025 | struct ufs_query_res *query_res = &hba->dev_cmd.query.response; | |
1026 | ||
1027 | /* Get the UPIU response */ | |
1028 | query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >> | |
1029 | UPIU_RSP_CODE_OFFSET; | |
1030 | return query_res->response; | |
1031 | } | |
1032 | ||
5a0b0cb9 SRT |
1033 | /** |
1034 | * ufshcd_dev_cmd_completion() - handles device management command responses | |
1035 | * @hba: per adapter instance | |
1036 | * @lrbp: pointer to local reference block | |
1037 | */ | |
1038 | static int | |
1039 | ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) | |
1040 | { | |
1041 | int resp; | |
1042 | int err = 0; | |
1043 | ||
1044 | resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); | |
1045 | ||
1046 | switch (resp) { | |
1047 | case UPIU_TRANSACTION_NOP_IN: | |
1048 | if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { | |
1049 | err = -EINVAL; | |
1050 | dev_err(hba->dev, "%s: unexpected response %x\n", | |
1051 | __func__, resp); | |
1052 | } | |
1053 | break; | |
68078d5c | 1054 | case UPIU_TRANSACTION_QUERY_RSP: |
c6d4a831 DR |
1055 | err = ufshcd_check_query_response(hba, lrbp); |
1056 | if (!err) | |
1057 | err = ufshcd_copy_query_response(hba, lrbp); | |
68078d5c | 1058 | break; |
5a0b0cb9 SRT |
1059 | case UPIU_TRANSACTION_REJECT_UPIU: |
1060 | /* TODO: handle Reject UPIU Response */ | |
1061 | err = -EPERM; | |
1062 | dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", | |
1063 | __func__); | |
1064 | break; | |
1065 | default: | |
1066 | err = -EINVAL; | |
1067 | dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", | |
1068 | __func__, resp); | |
1069 | break; | |
1070 | } | |
1071 | ||
1072 | return err; | |
1073 | } | |
1074 | ||
1075 | static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, | |
1076 | struct ufshcd_lrb *lrbp, int max_timeout) | |
1077 | { | |
1078 | int err = 0; | |
1079 | unsigned long time_left; | |
1080 | unsigned long flags; | |
1081 | ||
1082 | time_left = wait_for_completion_timeout(hba->dev_cmd.complete, | |
1083 | msecs_to_jiffies(max_timeout)); | |
1084 | ||
1085 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1086 | hba->dev_cmd.complete = NULL; | |
1087 | if (likely(time_left)) { | |
1088 | err = ufshcd_get_tr_ocs(lrbp); | |
1089 | if (!err) | |
1090 | err = ufshcd_dev_cmd_completion(hba, lrbp); | |
1091 | } | |
1092 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1093 | ||
1094 | if (!time_left) { | |
1095 | err = -ETIMEDOUT; | |
1096 | if (!ufshcd_clear_cmd(hba, lrbp->task_tag)) | |
1097 | /* sucessfully cleared the command, retry if needed */ | |
1098 | err = -EAGAIN; | |
1099 | } | |
1100 | ||
1101 | return err; | |
1102 | } | |
1103 | ||
1104 | /** | |
1105 | * ufshcd_get_dev_cmd_tag - Get device management command tag | |
1106 | * @hba: per-adapter instance | |
1107 | * @tag: pointer to variable with available slot value | |
1108 | * | |
1109 | * Get a free slot and lock it until device management command | |
1110 | * completes. | |
1111 | * | |
1112 | * Returns false if free slot is unavailable for locking, else | |
1113 | * return true with tag value in @tag. | |
1114 | */ | |
1115 | static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out) | |
1116 | { | |
1117 | int tag; | |
1118 | bool ret = false; | |
1119 | unsigned long tmp; | |
1120 | ||
1121 | if (!tag_out) | |
1122 | goto out; | |
1123 | ||
1124 | do { | |
1125 | tmp = ~hba->lrb_in_use; | |
1126 | tag = find_last_bit(&tmp, hba->nutrs); | |
1127 | if (tag >= hba->nutrs) | |
1128 | goto out; | |
1129 | } while (test_and_set_bit_lock(tag, &hba->lrb_in_use)); | |
1130 | ||
1131 | *tag_out = tag; | |
1132 | ret = true; | |
1133 | out: | |
1134 | return ret; | |
1135 | } | |
1136 | ||
1137 | static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag) | |
1138 | { | |
1139 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
1140 | } | |
1141 | ||
1142 | /** | |
1143 | * ufshcd_exec_dev_cmd - API for sending device management requests | |
1144 | * @hba - UFS hba | |
1145 | * @cmd_type - specifies the type (NOP, Query...) | |
1146 | * @timeout - time in seconds | |
1147 | * | |
68078d5c DR |
1148 | * NOTE: Since there is only one available tag for device management commands, |
1149 | * it is expected you hold the hba->dev_cmd.lock mutex. | |
5a0b0cb9 SRT |
1150 | */ |
1151 | static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, | |
1152 | enum dev_cmd_type cmd_type, int timeout) | |
1153 | { | |
1154 | struct ufshcd_lrb *lrbp; | |
1155 | int err; | |
1156 | int tag; | |
1157 | struct completion wait; | |
1158 | unsigned long flags; | |
1159 | ||
1160 | /* | |
1161 | * Get free slot, sleep if slots are unavailable. | |
1162 | * Even though we use wait_event() which sleeps indefinitely, | |
1163 | * the maximum wait time is bounded by SCSI request timeout. | |
1164 | */ | |
1165 | wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag)); | |
1166 | ||
1167 | init_completion(&wait); | |
1168 | lrbp = &hba->lrb[tag]; | |
1169 | WARN_ON(lrbp->cmd); | |
1170 | err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); | |
1171 | if (unlikely(err)) | |
1172 | goto out_put_tag; | |
1173 | ||
1174 | hba->dev_cmd.complete = &wait; | |
1175 | ||
1176 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1177 | ufshcd_send_command(hba, tag); | |
1178 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1179 | ||
1180 | err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); | |
1181 | ||
1182 | out_put_tag: | |
1183 | ufshcd_put_dev_cmd_tag(hba, tag); | |
1184 | wake_up(&hba->dev_cmd.tag_wq); | |
1185 | return err; | |
1186 | } | |
1187 | ||
d44a5f98 DR |
1188 | /** |
1189 | * ufshcd_init_query() - init the query response and request parameters | |
1190 | * @hba: per-adapter instance | |
1191 | * @request: address of the request pointer to be initialized | |
1192 | * @response: address of the response pointer to be initialized | |
1193 | * @opcode: operation to perform | |
1194 | * @idn: flag idn to access | |
1195 | * @index: LU number to access | |
1196 | * @selector: query/flag/descriptor further identification | |
1197 | */ | |
1198 | static inline void ufshcd_init_query(struct ufs_hba *hba, | |
1199 | struct ufs_query_req **request, struct ufs_query_res **response, | |
1200 | enum query_opcode opcode, u8 idn, u8 index, u8 selector) | |
1201 | { | |
1202 | *request = &hba->dev_cmd.query.request; | |
1203 | *response = &hba->dev_cmd.query.response; | |
1204 | memset(*request, 0, sizeof(struct ufs_query_req)); | |
1205 | memset(*response, 0, sizeof(struct ufs_query_res)); | |
1206 | (*request)->upiu_req.opcode = opcode; | |
1207 | (*request)->upiu_req.idn = idn; | |
1208 | (*request)->upiu_req.index = index; | |
1209 | (*request)->upiu_req.selector = selector; | |
1210 | } | |
1211 | ||
68078d5c DR |
1212 | /** |
1213 | * ufshcd_query_flag() - API function for sending flag query requests | |
1214 | * hba: per-adapter instance | |
1215 | * query_opcode: flag query to perform | |
1216 | * idn: flag idn to access | |
1217 | * flag_res: the flag value after the query request completes | |
1218 | * | |
1219 | * Returns 0 for success, non-zero in case of failure | |
1220 | */ | |
1221 | static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, | |
1222 | enum flag_idn idn, bool *flag_res) | |
1223 | { | |
d44a5f98 DR |
1224 | struct ufs_query_req *request = NULL; |
1225 | struct ufs_query_res *response = NULL; | |
1226 | int err, index = 0, selector = 0; | |
68078d5c DR |
1227 | |
1228 | BUG_ON(!hba); | |
1229 | ||
1230 | mutex_lock(&hba->dev_cmd.lock); | |
d44a5f98 DR |
1231 | ufshcd_init_query(hba, &request, &response, opcode, idn, index, |
1232 | selector); | |
68078d5c DR |
1233 | |
1234 | switch (opcode) { | |
1235 | case UPIU_QUERY_OPCODE_SET_FLAG: | |
1236 | case UPIU_QUERY_OPCODE_CLEAR_FLAG: | |
1237 | case UPIU_QUERY_OPCODE_TOGGLE_FLAG: | |
1238 | request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; | |
1239 | break; | |
1240 | case UPIU_QUERY_OPCODE_READ_FLAG: | |
1241 | request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; | |
1242 | if (!flag_res) { | |
1243 | /* No dummy reads */ | |
1244 | dev_err(hba->dev, "%s: Invalid argument for read request\n", | |
1245 | __func__); | |
1246 | err = -EINVAL; | |
1247 | goto out_unlock; | |
1248 | } | |
1249 | break; | |
1250 | default: | |
1251 | dev_err(hba->dev, | |
1252 | "%s: Expected query flag opcode but got = %d\n", | |
1253 | __func__, opcode); | |
1254 | err = -EINVAL; | |
1255 | goto out_unlock; | |
1256 | } | |
68078d5c | 1257 | |
d44a5f98 | 1258 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); |
68078d5c DR |
1259 | |
1260 | if (err) { | |
1261 | dev_err(hba->dev, | |
1262 | "%s: Sending flag query for idn %d failed, err = %d\n", | |
1263 | __func__, idn, err); | |
1264 | goto out_unlock; | |
1265 | } | |
1266 | ||
1267 | if (flag_res) | |
e8c8e82a | 1268 | *flag_res = (be32_to_cpu(response->upiu_res.value) & |
68078d5c DR |
1269 | MASK_QUERY_UPIU_FLAG_LOC) & 0x1; |
1270 | ||
1271 | out_unlock: | |
1272 | mutex_unlock(&hba->dev_cmd.lock); | |
1273 | return err; | |
1274 | } | |
1275 | ||
66ec6d59 SRT |
1276 | /** |
1277 | * ufshcd_query_attr - API function for sending attribute requests | |
1278 | * hba: per-adapter instance | |
1279 | * opcode: attribute opcode | |
1280 | * idn: attribute idn to access | |
1281 | * index: index field | |
1282 | * selector: selector field | |
1283 | * attr_val: the attribute value after the query request completes | |
1284 | * | |
1285 | * Returns 0 for success, non-zero in case of failure | |
1286 | */ | |
bdbe5d2f | 1287 | static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, |
66ec6d59 SRT |
1288 | enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) |
1289 | { | |
d44a5f98 DR |
1290 | struct ufs_query_req *request = NULL; |
1291 | struct ufs_query_res *response = NULL; | |
66ec6d59 SRT |
1292 | int err; |
1293 | ||
1294 | BUG_ON(!hba); | |
1295 | ||
1296 | if (!attr_val) { | |
1297 | dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", | |
1298 | __func__, opcode); | |
1299 | err = -EINVAL; | |
1300 | goto out; | |
1301 | } | |
1302 | ||
1303 | mutex_lock(&hba->dev_cmd.lock); | |
d44a5f98 DR |
1304 | ufshcd_init_query(hba, &request, &response, opcode, idn, index, |
1305 | selector); | |
66ec6d59 SRT |
1306 | |
1307 | switch (opcode) { | |
1308 | case UPIU_QUERY_OPCODE_WRITE_ATTR: | |
1309 | request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; | |
e8c8e82a | 1310 | request->upiu_req.value = cpu_to_be32(*attr_val); |
66ec6d59 SRT |
1311 | break; |
1312 | case UPIU_QUERY_OPCODE_READ_ATTR: | |
1313 | request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; | |
1314 | break; | |
1315 | default: | |
1316 | dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", | |
1317 | __func__, opcode); | |
1318 | err = -EINVAL; | |
1319 | goto out_unlock; | |
1320 | } | |
1321 | ||
d44a5f98 | 1322 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); |
66ec6d59 SRT |
1323 | |
1324 | if (err) { | |
1325 | dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n", | |
1326 | __func__, opcode, idn, err); | |
1327 | goto out_unlock; | |
1328 | } | |
1329 | ||
e8c8e82a | 1330 | *attr_val = be32_to_cpu(response->upiu_res.value); |
66ec6d59 SRT |
1331 | |
1332 | out_unlock: | |
1333 | mutex_unlock(&hba->dev_cmd.lock); | |
1334 | out: | |
1335 | return err; | |
1336 | } | |
1337 | ||
d44a5f98 DR |
1338 | /** |
1339 | * ufshcd_query_descriptor - API function for sending descriptor requests | |
1340 | * hba: per-adapter instance | |
1341 | * opcode: attribute opcode | |
1342 | * idn: attribute idn to access | |
1343 | * index: index field | |
1344 | * selector: selector field | |
1345 | * desc_buf: the buffer that contains the descriptor | |
1346 | * buf_len: length parameter passed to the device | |
1347 | * | |
1348 | * Returns 0 for success, non-zero in case of failure. | |
1349 | * The buf_len parameter will contain, on return, the length parameter | |
1350 | * received on the response. | |
1351 | */ | |
7289f983 | 1352 | static int ufshcd_query_descriptor(struct ufs_hba *hba, |
d44a5f98 DR |
1353 | enum query_opcode opcode, enum desc_idn idn, u8 index, |
1354 | u8 selector, u8 *desc_buf, int *buf_len) | |
1355 | { | |
1356 | struct ufs_query_req *request = NULL; | |
1357 | struct ufs_query_res *response = NULL; | |
1358 | int err; | |
1359 | ||
1360 | BUG_ON(!hba); | |
1361 | ||
1362 | if (!desc_buf) { | |
1363 | dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", | |
1364 | __func__, opcode); | |
1365 | err = -EINVAL; | |
1366 | goto out; | |
1367 | } | |
1368 | ||
1369 | if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { | |
1370 | dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", | |
1371 | __func__, *buf_len); | |
1372 | err = -EINVAL; | |
1373 | goto out; | |
1374 | } | |
1375 | ||
1376 | mutex_lock(&hba->dev_cmd.lock); | |
1377 | ufshcd_init_query(hba, &request, &response, opcode, idn, index, | |
1378 | selector); | |
1379 | hba->dev_cmd.query.descriptor = desc_buf; | |
ea2aab24 | 1380 | request->upiu_req.length = cpu_to_be16(*buf_len); |
d44a5f98 DR |
1381 | |
1382 | switch (opcode) { | |
1383 | case UPIU_QUERY_OPCODE_WRITE_DESC: | |
1384 | request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; | |
1385 | break; | |
1386 | case UPIU_QUERY_OPCODE_READ_DESC: | |
1387 | request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; | |
1388 | break; | |
1389 | default: | |
1390 | dev_err(hba->dev, | |
1391 | "%s: Expected query descriptor opcode but got = 0x%.2x\n", | |
1392 | __func__, opcode); | |
1393 | err = -EINVAL; | |
1394 | goto out_unlock; | |
1395 | } | |
1396 | ||
1397 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); | |
1398 | ||
1399 | if (err) { | |
1400 | dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n", | |
1401 | __func__, opcode, idn, err); | |
1402 | goto out_unlock; | |
1403 | } | |
1404 | ||
1405 | hba->dev_cmd.query.descriptor = NULL; | |
ea2aab24 | 1406 | *buf_len = be16_to_cpu(response->upiu_res.length); |
d44a5f98 DR |
1407 | |
1408 | out_unlock: | |
1409 | mutex_unlock(&hba->dev_cmd.lock); | |
1410 | out: | |
1411 | return err; | |
1412 | } | |
1413 | ||
da461cec SJ |
1414 | /** |
1415 | * ufshcd_read_desc_param - read the specified descriptor parameter | |
1416 | * @hba: Pointer to adapter instance | |
1417 | * @desc_id: descriptor idn value | |
1418 | * @desc_index: descriptor index | |
1419 | * @param_offset: offset of the parameter to read | |
1420 | * @param_read_buf: pointer to buffer where parameter would be read | |
1421 | * @param_size: sizeof(param_read_buf) | |
1422 | * | |
1423 | * Return 0 in case of success, non-zero otherwise | |
1424 | */ | |
1425 | static int ufshcd_read_desc_param(struct ufs_hba *hba, | |
1426 | enum desc_idn desc_id, | |
1427 | int desc_index, | |
1428 | u32 param_offset, | |
1429 | u8 *param_read_buf, | |
1430 | u32 param_size) | |
1431 | { | |
1432 | int ret; | |
1433 | u8 *desc_buf; | |
1434 | u32 buff_len; | |
1435 | bool is_kmalloc = true; | |
1436 | ||
1437 | /* safety checks */ | |
1438 | if (desc_id >= QUERY_DESC_IDN_MAX) | |
1439 | return -EINVAL; | |
1440 | ||
1441 | buff_len = ufs_query_desc_max_size[desc_id]; | |
1442 | if ((param_offset + param_size) > buff_len) | |
1443 | return -EINVAL; | |
1444 | ||
1445 | if (!param_offset && (param_size == buff_len)) { | |
1446 | /* memory space already available to hold full descriptor */ | |
1447 | desc_buf = param_read_buf; | |
1448 | is_kmalloc = false; | |
1449 | } else { | |
1450 | /* allocate memory to hold full descriptor */ | |
1451 | desc_buf = kmalloc(buff_len, GFP_KERNEL); | |
1452 | if (!desc_buf) | |
1453 | return -ENOMEM; | |
1454 | } | |
1455 | ||
1456 | ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC, | |
1457 | desc_id, desc_index, 0, desc_buf, | |
1458 | &buff_len); | |
1459 | ||
1460 | if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) || | |
1461 | (desc_buf[QUERY_DESC_LENGTH_OFFSET] != | |
1462 | ufs_query_desc_max_size[desc_id]) | |
1463 | || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) { | |
1464 | dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d", | |
1465 | __func__, desc_id, param_offset, buff_len, ret); | |
1466 | if (!ret) | |
1467 | ret = -EINVAL; | |
1468 | ||
1469 | goto out; | |
1470 | } | |
1471 | ||
1472 | if (is_kmalloc) | |
1473 | memcpy(param_read_buf, &desc_buf[param_offset], param_size); | |
1474 | out: | |
1475 | if (is_kmalloc) | |
1476 | kfree(desc_buf); | |
1477 | return ret; | |
1478 | } | |
1479 | ||
1480 | static inline int ufshcd_read_desc(struct ufs_hba *hba, | |
1481 | enum desc_idn desc_id, | |
1482 | int desc_index, | |
1483 | u8 *buf, | |
1484 | u32 size) | |
1485 | { | |
1486 | return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size); | |
1487 | } | |
1488 | ||
1489 | static inline int ufshcd_read_power_desc(struct ufs_hba *hba, | |
1490 | u8 *buf, | |
1491 | u32 size) | |
1492 | { | |
1493 | return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size); | |
1494 | } | |
1495 | ||
1496 | /** | |
1497 | * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter | |
1498 | * @hba: Pointer to adapter instance | |
1499 | * @lun: lun id | |
1500 | * @param_offset: offset of the parameter to read | |
1501 | * @param_read_buf: pointer to buffer where parameter would be read | |
1502 | * @param_size: sizeof(param_read_buf) | |
1503 | * | |
1504 | * Return 0 in case of success, non-zero otherwise | |
1505 | */ | |
1506 | static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, | |
1507 | int lun, | |
1508 | enum unit_desc_param param_offset, | |
1509 | u8 *param_read_buf, | |
1510 | u32 param_size) | |
1511 | { | |
1512 | /* | |
1513 | * Unit descriptors are only available for general purpose LUs (LUN id | |
1514 | * from 0 to 7) and RPMB Well known LU. | |
1515 | */ | |
1516 | if (lun >= UFS_UPIU_MAX_GENERAL_LUN) | |
1517 | return -EOPNOTSUPP; | |
1518 | ||
1519 | return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, | |
1520 | param_offset, param_read_buf, param_size); | |
1521 | } | |
1522 | ||
7a3e97b0 SY |
1523 | /** |
1524 | * ufshcd_memory_alloc - allocate memory for host memory space data structures | |
1525 | * @hba: per adapter instance | |
1526 | * | |
1527 | * 1. Allocate DMA memory for Command Descriptor array | |
1528 | * Each command descriptor consist of Command UPIU, Response UPIU and PRDT | |
1529 | * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). | |
1530 | * 3. Allocate DMA memory for UTP Task Management Request Descriptor List | |
1531 | * (UTMRDL) | |
1532 | * 4. Allocate memory for local reference block(lrb). | |
1533 | * | |
1534 | * Returns 0 for success, non-zero in case of failure | |
1535 | */ | |
1536 | static int ufshcd_memory_alloc(struct ufs_hba *hba) | |
1537 | { | |
1538 | size_t utmrdl_size, utrdl_size, ucdl_size; | |
1539 | ||
1540 | /* Allocate memory for UTP command descriptors */ | |
1541 | ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs); | |
2953f850 SJ |
1542 | hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, |
1543 | ucdl_size, | |
1544 | &hba->ucdl_dma_addr, | |
1545 | GFP_KERNEL); | |
7a3e97b0 SY |
1546 | |
1547 | /* | |
1548 | * UFSHCI requires UTP command descriptor to be 128 byte aligned. | |
1549 | * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE | |
1550 | * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will | |
1551 | * be aligned to 128 bytes as well | |
1552 | */ | |
1553 | if (!hba->ucdl_base_addr || | |
1554 | WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) { | |
3b1d0580 | 1555 | dev_err(hba->dev, |
7a3e97b0 SY |
1556 | "Command Descriptor Memory allocation failed\n"); |
1557 | goto out; | |
1558 | } | |
1559 | ||
1560 | /* | |
1561 | * Allocate memory for UTP Transfer descriptors | |
1562 | * UFSHCI requires 1024 byte alignment of UTRD | |
1563 | */ | |
1564 | utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); | |
2953f850 SJ |
1565 | hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, |
1566 | utrdl_size, | |
1567 | &hba->utrdl_dma_addr, | |
1568 | GFP_KERNEL); | |
7a3e97b0 SY |
1569 | if (!hba->utrdl_base_addr || |
1570 | WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) { | |
3b1d0580 | 1571 | dev_err(hba->dev, |
7a3e97b0 SY |
1572 | "Transfer Descriptor Memory allocation failed\n"); |
1573 | goto out; | |
1574 | } | |
1575 | ||
1576 | /* | |
1577 | * Allocate memory for UTP Task Management descriptors | |
1578 | * UFSHCI requires 1024 byte alignment of UTMRD | |
1579 | */ | |
1580 | utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; | |
2953f850 SJ |
1581 | hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, |
1582 | utmrdl_size, | |
1583 | &hba->utmrdl_dma_addr, | |
1584 | GFP_KERNEL); | |
7a3e97b0 SY |
1585 | if (!hba->utmrdl_base_addr || |
1586 | WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) { | |
3b1d0580 | 1587 | dev_err(hba->dev, |
7a3e97b0 SY |
1588 | "Task Management Descriptor Memory allocation failed\n"); |
1589 | goto out; | |
1590 | } | |
1591 | ||
1592 | /* Allocate memory for local reference block */ | |
2953f850 SJ |
1593 | hba->lrb = devm_kzalloc(hba->dev, |
1594 | hba->nutrs * sizeof(struct ufshcd_lrb), | |
1595 | GFP_KERNEL); | |
7a3e97b0 | 1596 | if (!hba->lrb) { |
3b1d0580 | 1597 | dev_err(hba->dev, "LRB Memory allocation failed\n"); |
7a3e97b0 SY |
1598 | goto out; |
1599 | } | |
1600 | return 0; | |
1601 | out: | |
7a3e97b0 SY |
1602 | return -ENOMEM; |
1603 | } | |
1604 | ||
1605 | /** | |
1606 | * ufshcd_host_memory_configure - configure local reference block with | |
1607 | * memory offsets | |
1608 | * @hba: per adapter instance | |
1609 | * | |
1610 | * Configure Host memory space | |
1611 | * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA | |
1612 | * address. | |
1613 | * 2. Update each UTRD with Response UPIU offset, Response UPIU length | |
1614 | * and PRDT offset. | |
1615 | * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT | |
1616 | * into local reference block. | |
1617 | */ | |
1618 | static void ufshcd_host_memory_configure(struct ufs_hba *hba) | |
1619 | { | |
1620 | struct utp_transfer_cmd_desc *cmd_descp; | |
1621 | struct utp_transfer_req_desc *utrdlp; | |
1622 | dma_addr_t cmd_desc_dma_addr; | |
1623 | dma_addr_t cmd_desc_element_addr; | |
1624 | u16 response_offset; | |
1625 | u16 prdt_offset; | |
1626 | int cmd_desc_size; | |
1627 | int i; | |
1628 | ||
1629 | utrdlp = hba->utrdl_base_addr; | |
1630 | cmd_descp = hba->ucdl_base_addr; | |
1631 | ||
1632 | response_offset = | |
1633 | offsetof(struct utp_transfer_cmd_desc, response_upiu); | |
1634 | prdt_offset = | |
1635 | offsetof(struct utp_transfer_cmd_desc, prd_table); | |
1636 | ||
1637 | cmd_desc_size = sizeof(struct utp_transfer_cmd_desc); | |
1638 | cmd_desc_dma_addr = hba->ucdl_dma_addr; | |
1639 | ||
1640 | for (i = 0; i < hba->nutrs; i++) { | |
1641 | /* Configure UTRD with command descriptor base address */ | |
1642 | cmd_desc_element_addr = | |
1643 | (cmd_desc_dma_addr + (cmd_desc_size * i)); | |
1644 | utrdlp[i].command_desc_base_addr_lo = | |
1645 | cpu_to_le32(lower_32_bits(cmd_desc_element_addr)); | |
1646 | utrdlp[i].command_desc_base_addr_hi = | |
1647 | cpu_to_le32(upper_32_bits(cmd_desc_element_addr)); | |
1648 | ||
1649 | /* Response upiu and prdt offset should be in double words */ | |
1650 | utrdlp[i].response_upiu_offset = | |
1651 | cpu_to_le16((response_offset >> 2)); | |
1652 | utrdlp[i].prd_table_offset = | |
1653 | cpu_to_le16((prdt_offset >> 2)); | |
1654 | utrdlp[i].response_upiu_length = | |
3ca316c5 | 1655 | cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); |
7a3e97b0 SY |
1656 | |
1657 | hba->lrb[i].utr_descriptor_ptr = (utrdlp + i); | |
5a0b0cb9 SRT |
1658 | hba->lrb[i].ucd_req_ptr = |
1659 | (struct utp_upiu_req *)(cmd_descp + i); | |
7a3e97b0 SY |
1660 | hba->lrb[i].ucd_rsp_ptr = |
1661 | (struct utp_upiu_rsp *)cmd_descp[i].response_upiu; | |
1662 | hba->lrb[i].ucd_prdt_ptr = | |
1663 | (struct ufshcd_sg_entry *)cmd_descp[i].prd_table; | |
1664 | } | |
1665 | } | |
1666 | ||
1667 | /** | |
1668 | * ufshcd_dme_link_startup - Notify Unipro to perform link startup | |
1669 | * @hba: per adapter instance | |
1670 | * | |
1671 | * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, | |
1672 | * in order to initialize the Unipro link startup procedure. | |
1673 | * Once the Unipro links are up, the device connected to the controller | |
1674 | * is detected. | |
1675 | * | |
1676 | * Returns 0 on success, non-zero value on failure | |
1677 | */ | |
1678 | static int ufshcd_dme_link_startup(struct ufs_hba *hba) | |
1679 | { | |
6ccf44fe SJ |
1680 | struct uic_command uic_cmd = {0}; |
1681 | int ret; | |
7a3e97b0 | 1682 | |
6ccf44fe | 1683 | uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; |
7a3e97b0 | 1684 | |
6ccf44fe SJ |
1685 | ret = ufshcd_send_uic_cmd(hba, &uic_cmd); |
1686 | if (ret) | |
1687 | dev_err(hba->dev, | |
1688 | "dme-link-startup: error code %d\n", ret); | |
1689 | return ret; | |
7a3e97b0 SY |
1690 | } |
1691 | ||
12b4fdb4 SJ |
1692 | /** |
1693 | * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET | |
1694 | * @hba: per adapter instance | |
1695 | * @attr_sel: uic command argument1 | |
1696 | * @attr_set: attribute set type as uic command argument2 | |
1697 | * @mib_val: setting value as uic command argument3 | |
1698 | * @peer: indicate whether peer or local | |
1699 | * | |
1700 | * Returns 0 on success, non-zero value on failure | |
1701 | */ | |
1702 | int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, | |
1703 | u8 attr_set, u32 mib_val, u8 peer) | |
1704 | { | |
1705 | struct uic_command uic_cmd = {0}; | |
1706 | static const char *const action[] = { | |
1707 | "dme-set", | |
1708 | "dme-peer-set" | |
1709 | }; | |
1710 | const char *set = action[!!peer]; | |
1711 | int ret; | |
1712 | ||
1713 | uic_cmd.command = peer ? | |
1714 | UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; | |
1715 | uic_cmd.argument1 = attr_sel; | |
1716 | uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); | |
1717 | uic_cmd.argument3 = mib_val; | |
1718 | ||
1719 | ret = ufshcd_send_uic_cmd(hba, &uic_cmd); | |
1720 | if (ret) | |
1721 | dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", | |
1722 | set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); | |
1723 | ||
1724 | return ret; | |
1725 | } | |
1726 | EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); | |
1727 | ||
1728 | /** | |
1729 | * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET | |
1730 | * @hba: per adapter instance | |
1731 | * @attr_sel: uic command argument1 | |
1732 | * @mib_val: the value of the attribute as returned by the UIC command | |
1733 | * @peer: indicate whether peer or local | |
1734 | * | |
1735 | * Returns 0 on success, non-zero value on failure | |
1736 | */ | |
1737 | int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, | |
1738 | u32 *mib_val, u8 peer) | |
1739 | { | |
1740 | struct uic_command uic_cmd = {0}; | |
1741 | static const char *const action[] = { | |
1742 | "dme-get", | |
1743 | "dme-peer-get" | |
1744 | }; | |
1745 | const char *get = action[!!peer]; | |
1746 | int ret; | |
1747 | ||
1748 | uic_cmd.command = peer ? | |
1749 | UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; | |
1750 | uic_cmd.argument1 = attr_sel; | |
1751 | ||
1752 | ret = ufshcd_send_uic_cmd(hba, &uic_cmd); | |
1753 | if (ret) { | |
1754 | dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n", | |
1755 | get, UIC_GET_ATTR_ID(attr_sel), ret); | |
1756 | goto out; | |
1757 | } | |
1758 | ||
1759 | if (mib_val) | |
1760 | *mib_val = uic_cmd.argument3; | |
1761 | out: | |
1762 | return ret; | |
1763 | } | |
1764 | EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); | |
1765 | ||
53b3d9c3 SJ |
1766 | /** |
1767 | * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage | |
1768 | * using DME_SET primitives. | |
1769 | * @hba: per adapter instance | |
1770 | * @mode: powr mode value | |
1771 | * | |
1772 | * Returns 0 on success, non-zero value on failure | |
1773 | */ | |
bdbe5d2f | 1774 | static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) |
53b3d9c3 SJ |
1775 | { |
1776 | struct uic_command uic_cmd = {0}; | |
1777 | struct completion pwr_done; | |
1778 | unsigned long flags; | |
1779 | u8 status; | |
1780 | int ret; | |
1781 | ||
1782 | uic_cmd.command = UIC_CMD_DME_SET; | |
1783 | uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); | |
1784 | uic_cmd.argument3 = mode; | |
1785 | init_completion(&pwr_done); | |
1786 | ||
1787 | mutex_lock(&hba->uic_cmd_mutex); | |
1788 | ||
1789 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1790 | hba->pwr_done = &pwr_done; | |
1791 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1792 | ret = __ufshcd_send_uic_cmd(hba, &uic_cmd); | |
1793 | if (ret) { | |
1794 | dev_err(hba->dev, | |
1795 | "pwr mode change with mode 0x%x uic error %d\n", | |
1796 | mode, ret); | |
1797 | goto out; | |
1798 | } | |
1799 | ||
1800 | if (!wait_for_completion_timeout(hba->pwr_done, | |
1801 | msecs_to_jiffies(UIC_CMD_TIMEOUT))) { | |
1802 | dev_err(hba->dev, | |
1803 | "pwr mode change with mode 0x%x completion timeout\n", | |
1804 | mode); | |
1805 | ret = -ETIMEDOUT; | |
1806 | goto out; | |
1807 | } | |
1808 | ||
1809 | status = ufshcd_get_upmcrs(hba); | |
1810 | if (status != PWR_LOCAL) { | |
1811 | dev_err(hba->dev, | |
1812 | "pwr mode change failed, host umpcrs:0x%x\n", | |
1813 | status); | |
1814 | ret = (status != PWR_OK) ? status : -1; | |
1815 | } | |
1816 | out: | |
1817 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1818 | hba->pwr_done = NULL; | |
1819 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1820 | mutex_unlock(&hba->uic_cmd_mutex); | |
1821 | return ret; | |
1822 | } | |
1823 | ||
d3e89bac SJ |
1824 | /** |
1825 | * ufshcd_config_max_pwr_mode - Set & Change power mode with | |
1826 | * maximum capability attribute information. | |
1827 | * @hba: per adapter instance | |
1828 | * | |
1829 | * Returns 0 on success, non-zero value on failure | |
1830 | */ | |
1831 | static int ufshcd_config_max_pwr_mode(struct ufs_hba *hba) | |
1832 | { | |
1833 | enum {RX = 0, TX = 1}; | |
1834 | u32 lanes[] = {1, 1}; | |
1835 | u32 gear[] = {1, 1}; | |
1836 | u8 pwr[] = {FASTAUTO_MODE, FASTAUTO_MODE}; | |
1837 | int ret; | |
1838 | ||
1839 | /* Get the connected lane count */ | |
1840 | ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), &lanes[RX]); | |
1841 | ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), &lanes[TX]); | |
1842 | ||
1843 | /* | |
1844 | * First, get the maximum gears of HS speed. | |
1845 | * If a zero value, it means there is no HSGEAR capability. | |
1846 | * Then, get the maximum gears of PWM speed. | |
1847 | */ | |
1848 | ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &gear[RX]); | |
1849 | if (!gear[RX]) { | |
1850 | ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), &gear[RX]); | |
1851 | pwr[RX] = SLOWAUTO_MODE; | |
1852 | } | |
1853 | ||
1854 | ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &gear[TX]); | |
1855 | if (!gear[TX]) { | |
1856 | ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), | |
1857 | &gear[TX]); | |
1858 | pwr[TX] = SLOWAUTO_MODE; | |
1859 | } | |
1860 | ||
1861 | /* | |
1862 | * Configure attributes for power mode change with below. | |
1863 | * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, | |
1864 | * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, | |
1865 | * - PA_HSSERIES | |
1866 | */ | |
1867 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), gear[RX]); | |
1868 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), lanes[RX]); | |
1869 | if (pwr[RX] == FASTAUTO_MODE) | |
1870 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE); | |
1871 | ||
1872 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), gear[TX]); | |
1873 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), lanes[TX]); | |
1874 | if (pwr[TX] == FASTAUTO_MODE) | |
1875 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE); | |
1876 | ||
1877 | if (pwr[RX] == FASTAUTO_MODE || pwr[TX] == FASTAUTO_MODE) | |
1878 | ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), PA_HS_MODE_B); | |
1879 | ||
1880 | ret = ufshcd_uic_change_pwr_mode(hba, pwr[RX] << 4 | pwr[TX]); | |
1881 | if (ret) | |
1882 | dev_err(hba->dev, | |
1883 | "pwr_mode: power mode change failed %d\n", ret); | |
1884 | ||
1885 | return ret; | |
1886 | } | |
1887 | ||
68078d5c DR |
1888 | /** |
1889 | * ufshcd_complete_dev_init() - checks device readiness | |
1890 | * hba: per-adapter instance | |
1891 | * | |
1892 | * Set fDeviceInit flag and poll until device toggles it. | |
1893 | */ | |
1894 | static int ufshcd_complete_dev_init(struct ufs_hba *hba) | |
1895 | { | |
1896 | int i, retries, err = 0; | |
1897 | bool flag_res = 1; | |
1898 | ||
1899 | for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { | |
1900 | /* Set the fDeviceInit flag */ | |
1901 | err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG, | |
1902 | QUERY_FLAG_IDN_FDEVICEINIT, NULL); | |
1903 | if (!err || err == -ETIMEDOUT) | |
1904 | break; | |
1905 | dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); | |
1906 | } | |
1907 | if (err) { | |
1908 | dev_err(hba->dev, | |
1909 | "%s setting fDeviceInit flag failed with error %d\n", | |
1910 | __func__, err); | |
1911 | goto out; | |
1912 | } | |
1913 | ||
1914 | /* poll for max. 100 iterations for fDeviceInit flag to clear */ | |
1915 | for (i = 0; i < 100 && !err && flag_res; i++) { | |
1916 | for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { | |
1917 | err = ufshcd_query_flag(hba, | |
1918 | UPIU_QUERY_OPCODE_READ_FLAG, | |
1919 | QUERY_FLAG_IDN_FDEVICEINIT, &flag_res); | |
1920 | if (!err || err == -ETIMEDOUT) | |
1921 | break; | |
1922 | dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, | |
1923 | err); | |
1924 | } | |
1925 | } | |
1926 | if (err) | |
1927 | dev_err(hba->dev, | |
1928 | "%s reading fDeviceInit flag failed with error %d\n", | |
1929 | __func__, err); | |
1930 | else if (flag_res) | |
1931 | dev_err(hba->dev, | |
1932 | "%s fDeviceInit was not cleared by the device\n", | |
1933 | __func__); | |
1934 | ||
1935 | out: | |
1936 | return err; | |
1937 | } | |
1938 | ||
7a3e97b0 SY |
1939 | /** |
1940 | * ufshcd_make_hba_operational - Make UFS controller operational | |
1941 | * @hba: per adapter instance | |
1942 | * | |
1943 | * To bring UFS host controller to operational state, | |
5c0c28a8 SRT |
1944 | * 1. Enable required interrupts |
1945 | * 2. Configure interrupt aggregation | |
1946 | * 3. Program UTRL and UTMRL base addres | |
1947 | * 4. Configure run-stop-registers | |
7a3e97b0 SY |
1948 | * |
1949 | * Returns 0 on success, non-zero value on failure | |
1950 | */ | |
1951 | static int ufshcd_make_hba_operational(struct ufs_hba *hba) | |
1952 | { | |
1953 | int err = 0; | |
1954 | u32 reg; | |
1955 | ||
6ccf44fe SJ |
1956 | /* Enable required interrupts */ |
1957 | ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); | |
1958 | ||
1959 | /* Configure interrupt aggregation */ | |
7d568652 | 1960 | ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); |
6ccf44fe SJ |
1961 | |
1962 | /* Configure UTRL and UTMRL base address registers */ | |
1963 | ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), | |
1964 | REG_UTP_TRANSFER_REQ_LIST_BASE_L); | |
1965 | ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), | |
1966 | REG_UTP_TRANSFER_REQ_LIST_BASE_H); | |
1967 | ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), | |
1968 | REG_UTP_TASK_REQ_LIST_BASE_L); | |
1969 | ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), | |
1970 | REG_UTP_TASK_REQ_LIST_BASE_H); | |
1971 | ||
7a3e97b0 SY |
1972 | /* |
1973 | * UCRDY, UTMRLDY and UTRLRDY bits must be 1 | |
1974 | * DEI, HEI bits must be 0 | |
1975 | */ | |
5c0c28a8 | 1976 | reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); |
7a3e97b0 SY |
1977 | if (!(ufshcd_get_lists_status(reg))) { |
1978 | ufshcd_enable_run_stop_reg(hba); | |
1979 | } else { | |
3b1d0580 | 1980 | dev_err(hba->dev, |
7a3e97b0 SY |
1981 | "Host controller not ready to process requests"); |
1982 | err = -EIO; | |
1983 | goto out; | |
1984 | } | |
1985 | ||
7a3e97b0 SY |
1986 | out: |
1987 | return err; | |
1988 | } | |
1989 | ||
1990 | /** | |
1991 | * ufshcd_hba_enable - initialize the controller | |
1992 | * @hba: per adapter instance | |
1993 | * | |
1994 | * The controller resets itself and controller firmware initialization | |
1995 | * sequence kicks off. When controller is ready it will set | |
1996 | * the Host Controller Enable bit to 1. | |
1997 | * | |
1998 | * Returns 0 on success, non-zero value on failure | |
1999 | */ | |
2000 | static int ufshcd_hba_enable(struct ufs_hba *hba) | |
2001 | { | |
2002 | int retry; | |
2003 | ||
2004 | /* | |
2005 | * msleep of 1 and 5 used in this function might result in msleep(20), | |
2006 | * but it was necessary to send the UFS FPGA to reset mode during | |
2007 | * development and testing of this driver. msleep can be changed to | |
2008 | * mdelay and retry count can be reduced based on the controller. | |
2009 | */ | |
2010 | if (!ufshcd_is_hba_active(hba)) { | |
2011 | ||
2012 | /* change controller state to "reset state" */ | |
2013 | ufshcd_hba_stop(hba); | |
2014 | ||
2015 | /* | |
2016 | * This delay is based on the testing done with UFS host | |
2017 | * controller FPGA. The delay can be changed based on the | |
2018 | * host controller used. | |
2019 | */ | |
2020 | msleep(5); | |
2021 | } | |
2022 | ||
5c0c28a8 SRT |
2023 | if (hba->vops && hba->vops->hce_enable_notify) |
2024 | hba->vops->hce_enable_notify(hba, PRE_CHANGE); | |
2025 | ||
7a3e97b0 SY |
2026 | /* start controller initialization sequence */ |
2027 | ufshcd_hba_start(hba); | |
2028 | ||
2029 | /* | |
2030 | * To initialize a UFS host controller HCE bit must be set to 1. | |
2031 | * During initialization the HCE bit value changes from 1->0->1. | |
2032 | * When the host controller completes initialization sequence | |
2033 | * it sets the value of HCE bit to 1. The same HCE bit is read back | |
2034 | * to check if the controller has completed initialization sequence. | |
2035 | * So without this delay the value HCE = 1, set in the previous | |
2036 | * instruction might be read back. | |
2037 | * This delay can be changed based on the controller. | |
2038 | */ | |
2039 | msleep(1); | |
2040 | ||
2041 | /* wait for the host controller to complete initialization */ | |
2042 | retry = 10; | |
2043 | while (ufshcd_is_hba_active(hba)) { | |
2044 | if (retry) { | |
2045 | retry--; | |
2046 | } else { | |
3b1d0580 | 2047 | dev_err(hba->dev, |
7a3e97b0 SY |
2048 | "Controller enable failed\n"); |
2049 | return -EIO; | |
2050 | } | |
2051 | msleep(5); | |
2052 | } | |
5c0c28a8 | 2053 | |
1d337ec2 SRT |
2054 | /* enable UIC related interrupts */ |
2055 | ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); | |
2056 | ||
5c0c28a8 SRT |
2057 | if (hba->vops && hba->vops->hce_enable_notify) |
2058 | hba->vops->hce_enable_notify(hba, POST_CHANGE); | |
2059 | ||
7a3e97b0 SY |
2060 | return 0; |
2061 | } | |
2062 | ||
2063 | /** | |
6ccf44fe | 2064 | * ufshcd_link_startup - Initialize unipro link startup |
7a3e97b0 SY |
2065 | * @hba: per adapter instance |
2066 | * | |
6ccf44fe | 2067 | * Returns 0 for success, non-zero in case of failure |
7a3e97b0 | 2068 | */ |
6ccf44fe | 2069 | static int ufshcd_link_startup(struct ufs_hba *hba) |
7a3e97b0 | 2070 | { |
6ccf44fe | 2071 | int ret; |
1d337ec2 | 2072 | int retries = DME_LINKSTARTUP_RETRIES; |
7a3e97b0 | 2073 | |
1d337ec2 SRT |
2074 | do { |
2075 | if (hba->vops && hba->vops->link_startup_notify) | |
2076 | hba->vops->link_startup_notify(hba, PRE_CHANGE); | |
6ccf44fe | 2077 | |
1d337ec2 | 2078 | ret = ufshcd_dme_link_startup(hba); |
5c0c28a8 | 2079 | |
1d337ec2 SRT |
2080 | /* check if device is detected by inter-connect layer */ |
2081 | if (!ret && !ufshcd_is_device_present(hba)) { | |
2082 | dev_err(hba->dev, "%s: Device not present\n", __func__); | |
2083 | ret = -ENXIO; | |
2084 | goto out; | |
2085 | } | |
6ccf44fe | 2086 | |
1d337ec2 SRT |
2087 | /* |
2088 | * DME link lost indication is only received when link is up, | |
2089 | * but we can't be sure if the link is up until link startup | |
2090 | * succeeds. So reset the local Uni-Pro and try again. | |
2091 | */ | |
2092 | if (ret && ufshcd_hba_enable(hba)) | |
2093 | goto out; | |
2094 | } while (ret && retries--); | |
2095 | ||
2096 | if (ret) | |
2097 | /* failed to get the link up... retire */ | |
5c0c28a8 | 2098 | goto out; |
5c0c28a8 SRT |
2099 | |
2100 | /* Include any host controller configuration via UIC commands */ | |
2101 | if (hba->vops && hba->vops->link_startup_notify) { | |
2102 | ret = hba->vops->link_startup_notify(hba, POST_CHANGE); | |
2103 | if (ret) | |
2104 | goto out; | |
2105 | } | |
7a3e97b0 | 2106 | |
5c0c28a8 | 2107 | ret = ufshcd_make_hba_operational(hba); |
6ccf44fe SJ |
2108 | out: |
2109 | if (ret) | |
2110 | dev_err(hba->dev, "link startup failed %d\n", ret); | |
2111 | return ret; | |
7a3e97b0 SY |
2112 | } |
2113 | ||
5a0b0cb9 SRT |
2114 | /** |
2115 | * ufshcd_verify_dev_init() - Verify device initialization | |
2116 | * @hba: per-adapter instance | |
2117 | * | |
2118 | * Send NOP OUT UPIU and wait for NOP IN response to check whether the | |
2119 | * device Transport Protocol (UTP) layer is ready after a reset. | |
2120 | * If the UTP layer at the device side is not initialized, it may | |
2121 | * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT | |
2122 | * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. | |
2123 | */ | |
2124 | static int ufshcd_verify_dev_init(struct ufs_hba *hba) | |
2125 | { | |
2126 | int err = 0; | |
2127 | int retries; | |
2128 | ||
2129 | mutex_lock(&hba->dev_cmd.lock); | |
2130 | for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { | |
2131 | err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, | |
2132 | NOP_OUT_TIMEOUT); | |
2133 | ||
2134 | if (!err || err == -ETIMEDOUT) | |
2135 | break; | |
2136 | ||
2137 | dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); | |
2138 | } | |
2139 | mutex_unlock(&hba->dev_cmd.lock); | |
2140 | ||
2141 | if (err) | |
2142 | dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); | |
2143 | return err; | |
2144 | } | |
2145 | ||
7a3e97b0 SY |
2146 | /** |
2147 | * ufshcd_slave_alloc - handle initial SCSI device configurations | |
2148 | * @sdev: pointer to SCSI device | |
2149 | * | |
2150 | * Returns success | |
2151 | */ | |
2152 | static int ufshcd_slave_alloc(struct scsi_device *sdev) | |
2153 | { | |
2154 | struct ufs_hba *hba; | |
da461cec SJ |
2155 | u8 lun_qdepth; |
2156 | int ret; | |
7a3e97b0 SY |
2157 | |
2158 | hba = shost_priv(sdev->host); | |
2159 | sdev->tagged_supported = 1; | |
2160 | ||
2161 | /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ | |
2162 | sdev->use_10_for_ms = 1; | |
2163 | scsi_set_tag_type(sdev, MSG_SIMPLE_TAG); | |
2164 | ||
e8e7f271 SRT |
2165 | /* allow SCSI layer to restart the device in case of errors */ |
2166 | sdev->allow_restart = 1; | |
4264fd61 | 2167 | |
b2a6c522 SRT |
2168 | /* REPORT SUPPORTED OPERATION CODES is not supported */ |
2169 | sdev->no_report_opcodes = 1; | |
2170 | ||
da461cec SJ |
2171 | ret = ufshcd_read_unit_desc_param(hba, |
2172 | sdev->lun, | |
2173 | UNIT_DESC_PARAM_LU_Q_DEPTH, | |
2174 | &lun_qdepth, | |
2175 | sizeof(lun_qdepth)); | |
2176 | if (!ret || !lun_qdepth) | |
4264fd61 | 2177 | /* eventually, we can figure out the real queue depth */ |
1b3e8956 | 2178 | lun_qdepth = hba->nutrs; |
4264fd61 SRT |
2179 | else |
2180 | lun_qdepth = min_t(int, lun_qdepth, hba->nutrs); | |
e8e7f271 | 2181 | |
4264fd61 SRT |
2182 | dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n", |
2183 | __func__, lun_qdepth); | |
1b3e8956 | 2184 | scsi_activate_tcq(sdev, lun_qdepth); |
4264fd61 | 2185 | |
7a3e97b0 SY |
2186 | return 0; |
2187 | } | |
2188 | ||
4264fd61 SRT |
2189 | /** |
2190 | * ufshcd_change_queue_depth - change queue depth | |
2191 | * @sdev: pointer to SCSI device | |
2192 | * @depth: required depth to set | |
2193 | * @reason: reason for changing the depth | |
2194 | * | |
2195 | * Change queue depth according to the reason and make sure | |
2196 | * the max. limits are not crossed. | |
2197 | */ | |
7289f983 SRT |
2198 | static int ufshcd_change_queue_depth(struct scsi_device *sdev, |
2199 | int depth, int reason) | |
4264fd61 SRT |
2200 | { |
2201 | struct ufs_hba *hba = shost_priv(sdev->host); | |
2202 | ||
2203 | if (depth > hba->nutrs) | |
2204 | depth = hba->nutrs; | |
2205 | ||
2206 | switch (reason) { | |
2207 | case SCSI_QDEPTH_DEFAULT: | |
2208 | case SCSI_QDEPTH_RAMP_UP: | |
2209 | if (!sdev->tagged_supported) | |
2210 | depth = 1; | |
2211 | scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), depth); | |
2212 | break; | |
2213 | case SCSI_QDEPTH_QFULL: | |
2214 | scsi_track_queue_full(sdev, depth); | |
2215 | break; | |
2216 | default: | |
2217 | return -EOPNOTSUPP; | |
2218 | } | |
2219 | ||
2220 | return depth; | |
2221 | } | |
2222 | ||
eeda4749 AM |
2223 | /** |
2224 | * ufshcd_slave_configure - adjust SCSI device configurations | |
2225 | * @sdev: pointer to SCSI device | |
2226 | */ | |
2227 | static int ufshcd_slave_configure(struct scsi_device *sdev) | |
2228 | { | |
2229 | struct request_queue *q = sdev->request_queue; | |
2230 | ||
2231 | blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); | |
2232 | blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX); | |
2233 | ||
2234 | return 0; | |
2235 | } | |
2236 | ||
7a3e97b0 SY |
2237 | /** |
2238 | * ufshcd_slave_destroy - remove SCSI device configurations | |
2239 | * @sdev: pointer to SCSI device | |
2240 | */ | |
2241 | static void ufshcd_slave_destroy(struct scsi_device *sdev) | |
2242 | { | |
2243 | struct ufs_hba *hba; | |
2244 | ||
2245 | hba = shost_priv(sdev->host); | |
2246 | scsi_deactivate_tcq(sdev, hba->nutrs); | |
2247 | } | |
2248 | ||
2249 | /** | |
2250 | * ufshcd_task_req_compl - handle task management request completion | |
2251 | * @hba: per adapter instance | |
2252 | * @index: index of the completed request | |
e2933132 | 2253 | * @resp: task management service response |
7a3e97b0 | 2254 | * |
e2933132 | 2255 | * Returns non-zero value on error, zero on success |
7a3e97b0 | 2256 | */ |
e2933132 | 2257 | static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp) |
7a3e97b0 SY |
2258 | { |
2259 | struct utp_task_req_desc *task_req_descp; | |
2260 | struct utp_upiu_task_rsp *task_rsp_upiup; | |
2261 | unsigned long flags; | |
2262 | int ocs_value; | |
2263 | int task_result; | |
2264 | ||
2265 | spin_lock_irqsave(hba->host->host_lock, flags); | |
2266 | ||
2267 | /* Clear completed tasks from outstanding_tasks */ | |
2268 | __clear_bit(index, &hba->outstanding_tasks); | |
2269 | ||
2270 | task_req_descp = hba->utmrdl_base_addr; | |
2271 | ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]); | |
2272 | ||
2273 | if (ocs_value == OCS_SUCCESS) { | |
2274 | task_rsp_upiup = (struct utp_upiu_task_rsp *) | |
2275 | task_req_descp[index].task_rsp_upiu; | |
2276 | task_result = be32_to_cpu(task_rsp_upiup->header.dword_1); | |
2277 | task_result = ((task_result & MASK_TASK_RESPONSE) >> 8); | |
e2933132 SRT |
2278 | if (resp) |
2279 | *resp = (u8)task_result; | |
7a3e97b0 | 2280 | } else { |
e2933132 SRT |
2281 | dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", |
2282 | __func__, ocs_value); | |
7a3e97b0 SY |
2283 | } |
2284 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
e2933132 SRT |
2285 | |
2286 | return ocs_value; | |
7a3e97b0 SY |
2287 | } |
2288 | ||
7a3e97b0 SY |
2289 | /** |
2290 | * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status | |
2291 | * @lrb: pointer to local reference block of completed command | |
2292 | * @scsi_status: SCSI command status | |
2293 | * | |
2294 | * Returns value base on SCSI command status | |
2295 | */ | |
2296 | static inline int | |
2297 | ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) | |
2298 | { | |
2299 | int result = 0; | |
2300 | ||
2301 | switch (scsi_status) { | |
7a3e97b0 | 2302 | case SAM_STAT_CHECK_CONDITION: |
1c2623c5 SJ |
2303 | ufshcd_copy_sense_data(lrbp); |
2304 | case SAM_STAT_GOOD: | |
7a3e97b0 SY |
2305 | result |= DID_OK << 16 | |
2306 | COMMAND_COMPLETE << 8 | | |
1c2623c5 | 2307 | scsi_status; |
7a3e97b0 SY |
2308 | break; |
2309 | case SAM_STAT_TASK_SET_FULL: | |
1c2623c5 | 2310 | case SAM_STAT_BUSY: |
7a3e97b0 | 2311 | case SAM_STAT_TASK_ABORTED: |
1c2623c5 SJ |
2312 | ufshcd_copy_sense_data(lrbp); |
2313 | result |= scsi_status; | |
7a3e97b0 SY |
2314 | break; |
2315 | default: | |
2316 | result |= DID_ERROR << 16; | |
2317 | break; | |
2318 | } /* end of switch */ | |
2319 | ||
2320 | return result; | |
2321 | } | |
2322 | ||
2323 | /** | |
2324 | * ufshcd_transfer_rsp_status - Get overall status of the response | |
2325 | * @hba: per adapter instance | |
2326 | * @lrb: pointer to local reference block of completed command | |
2327 | * | |
2328 | * Returns result of the command to notify SCSI midlayer | |
2329 | */ | |
2330 | static inline int | |
2331 | ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) | |
2332 | { | |
2333 | int result = 0; | |
2334 | int scsi_status; | |
2335 | int ocs; | |
2336 | ||
2337 | /* overall command status of utrd */ | |
2338 | ocs = ufshcd_get_tr_ocs(lrbp); | |
2339 | ||
2340 | switch (ocs) { | |
2341 | case OCS_SUCCESS: | |
5a0b0cb9 | 2342 | result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); |
7a3e97b0 | 2343 | |
5a0b0cb9 SRT |
2344 | switch (result) { |
2345 | case UPIU_TRANSACTION_RESPONSE: | |
2346 | /* | |
2347 | * get the response UPIU result to extract | |
2348 | * the SCSI command status | |
2349 | */ | |
2350 | result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr); | |
2351 | ||
2352 | /* | |
2353 | * get the result based on SCSI status response | |
2354 | * to notify the SCSI midlayer of the command status | |
2355 | */ | |
2356 | scsi_status = result & MASK_SCSI_STATUS; | |
2357 | result = ufshcd_scsi_cmd_status(lrbp, scsi_status); | |
66ec6d59 SRT |
2358 | |
2359 | if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) | |
2360 | schedule_work(&hba->eeh_work); | |
5a0b0cb9 SRT |
2361 | break; |
2362 | case UPIU_TRANSACTION_REJECT_UPIU: | |
2363 | /* TODO: handle Reject UPIU Response */ | |
2364 | result = DID_ERROR << 16; | |
3b1d0580 | 2365 | dev_err(hba->dev, |
5a0b0cb9 SRT |
2366 | "Reject UPIU not fully implemented\n"); |
2367 | break; | |
2368 | default: | |
2369 | result = DID_ERROR << 16; | |
2370 | dev_err(hba->dev, | |
2371 | "Unexpected request response code = %x\n", | |
2372 | result); | |
7a3e97b0 SY |
2373 | break; |
2374 | } | |
7a3e97b0 SY |
2375 | break; |
2376 | case OCS_ABORTED: | |
2377 | result |= DID_ABORT << 16; | |
2378 | break; | |
e8e7f271 SRT |
2379 | case OCS_INVALID_COMMAND_STATUS: |
2380 | result |= DID_REQUEUE << 16; | |
2381 | break; | |
7a3e97b0 SY |
2382 | case OCS_INVALID_CMD_TABLE_ATTR: |
2383 | case OCS_INVALID_PRDT_ATTR: | |
2384 | case OCS_MISMATCH_DATA_BUF_SIZE: | |
2385 | case OCS_MISMATCH_RESP_UPIU_SIZE: | |
2386 | case OCS_PEER_COMM_FAILURE: | |
2387 | case OCS_FATAL_ERROR: | |
2388 | default: | |
2389 | result |= DID_ERROR << 16; | |
3b1d0580 | 2390 | dev_err(hba->dev, |
7a3e97b0 SY |
2391 | "OCS error from controller = %x\n", ocs); |
2392 | break; | |
2393 | } /* end of switch */ | |
2394 | ||
2395 | return result; | |
2396 | } | |
2397 | ||
6ccf44fe SJ |
2398 | /** |
2399 | * ufshcd_uic_cmd_compl - handle completion of uic command | |
2400 | * @hba: per adapter instance | |
53b3d9c3 | 2401 | * @intr_status: interrupt status generated by the controller |
6ccf44fe | 2402 | */ |
53b3d9c3 | 2403 | static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) |
6ccf44fe | 2404 | { |
53b3d9c3 | 2405 | if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { |
6ccf44fe SJ |
2406 | hba->active_uic_cmd->argument2 |= |
2407 | ufshcd_get_uic_cmd_result(hba); | |
12b4fdb4 SJ |
2408 | hba->active_uic_cmd->argument3 = |
2409 | ufshcd_get_dme_attr_val(hba); | |
6ccf44fe SJ |
2410 | complete(&hba->active_uic_cmd->done); |
2411 | } | |
53b3d9c3 SJ |
2412 | |
2413 | if ((intr_status & UIC_POWER_MODE) && hba->pwr_done) | |
2414 | complete(hba->pwr_done); | |
6ccf44fe SJ |
2415 | } |
2416 | ||
7a3e97b0 SY |
2417 | /** |
2418 | * ufshcd_transfer_req_compl - handle SCSI and query command completion | |
2419 | * @hba: per adapter instance | |
2420 | */ | |
2421 | static void ufshcd_transfer_req_compl(struct ufs_hba *hba) | |
2422 | { | |
5a0b0cb9 SRT |
2423 | struct ufshcd_lrb *lrbp; |
2424 | struct scsi_cmnd *cmd; | |
7a3e97b0 SY |
2425 | unsigned long completed_reqs; |
2426 | u32 tr_doorbell; | |
2427 | int result; | |
2428 | int index; | |
e9d501b1 DR |
2429 | |
2430 | /* Resetting interrupt aggregation counters first and reading the | |
2431 | * DOOR_BELL afterward allows us to handle all the completed requests. | |
2432 | * In order to prevent other interrupts starvation the DB is read once | |
2433 | * after reset. The down side of this solution is the possibility of | |
2434 | * false interrupt if device completes another request after resetting | |
2435 | * aggregation and before reading the DB. | |
2436 | */ | |
2437 | ufshcd_reset_intr_aggr(hba); | |
7a3e97b0 | 2438 | |
b873a275 | 2439 | tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); |
7a3e97b0 SY |
2440 | completed_reqs = tr_doorbell ^ hba->outstanding_reqs; |
2441 | ||
e9d501b1 DR |
2442 | for_each_set_bit(index, &completed_reqs, hba->nutrs) { |
2443 | lrbp = &hba->lrb[index]; | |
2444 | cmd = lrbp->cmd; | |
2445 | if (cmd) { | |
2446 | result = ufshcd_transfer_rsp_status(hba, lrbp); | |
2447 | scsi_dma_unmap(cmd); | |
2448 | cmd->result = result; | |
2449 | /* Mark completed command as NULL in LRB */ | |
2450 | lrbp->cmd = NULL; | |
2451 | clear_bit_unlock(index, &hba->lrb_in_use); | |
2452 | /* Do not touch lrbp after scsi done */ | |
2453 | cmd->scsi_done(cmd); | |
2454 | } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) { | |
2455 | if (hba->dev_cmd.complete) | |
2456 | complete(hba->dev_cmd.complete); | |
2457 | } | |
2458 | } | |
7a3e97b0 SY |
2459 | |
2460 | /* clear corresponding bits of completed commands */ | |
2461 | hba->outstanding_reqs ^= completed_reqs; | |
2462 | ||
5a0b0cb9 SRT |
2463 | /* we might have free'd some tags above */ |
2464 | wake_up(&hba->dev_cmd.tag_wq); | |
7a3e97b0 SY |
2465 | } |
2466 | ||
66ec6d59 SRT |
2467 | /** |
2468 | * ufshcd_disable_ee - disable exception event | |
2469 | * @hba: per-adapter instance | |
2470 | * @mask: exception event to disable | |
2471 | * | |
2472 | * Disables exception event in the device so that the EVENT_ALERT | |
2473 | * bit is not set. | |
2474 | * | |
2475 | * Returns zero on success, non-zero error value on failure. | |
2476 | */ | |
2477 | static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) | |
2478 | { | |
2479 | int err = 0; | |
2480 | u32 val; | |
2481 | ||
2482 | if (!(hba->ee_ctrl_mask & mask)) | |
2483 | goto out; | |
2484 | ||
2485 | val = hba->ee_ctrl_mask & ~mask; | |
2486 | val &= 0xFFFF; /* 2 bytes */ | |
2487 | err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, | |
2488 | QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); | |
2489 | if (!err) | |
2490 | hba->ee_ctrl_mask &= ~mask; | |
2491 | out: | |
2492 | return err; | |
2493 | } | |
2494 | ||
2495 | /** | |
2496 | * ufshcd_enable_ee - enable exception event | |
2497 | * @hba: per-adapter instance | |
2498 | * @mask: exception event to enable | |
2499 | * | |
2500 | * Enable corresponding exception event in the device to allow | |
2501 | * device to alert host in critical scenarios. | |
2502 | * | |
2503 | * Returns zero on success, non-zero error value on failure. | |
2504 | */ | |
2505 | static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) | |
2506 | { | |
2507 | int err = 0; | |
2508 | u32 val; | |
2509 | ||
2510 | if (hba->ee_ctrl_mask & mask) | |
2511 | goto out; | |
2512 | ||
2513 | val = hba->ee_ctrl_mask | mask; | |
2514 | val &= 0xFFFF; /* 2 bytes */ | |
2515 | err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, | |
2516 | QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val); | |
2517 | if (!err) | |
2518 | hba->ee_ctrl_mask |= mask; | |
2519 | out: | |
2520 | return err; | |
2521 | } | |
2522 | ||
2523 | /** | |
2524 | * ufshcd_enable_auto_bkops - Allow device managed BKOPS | |
2525 | * @hba: per-adapter instance | |
2526 | * | |
2527 | * Allow device to manage background operations on its own. Enabling | |
2528 | * this might lead to inconsistent latencies during normal data transfers | |
2529 | * as the device is allowed to manage its own way of handling background | |
2530 | * operations. | |
2531 | * | |
2532 | * Returns zero on success, non-zero on failure. | |
2533 | */ | |
2534 | static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) | |
2535 | { | |
2536 | int err = 0; | |
2537 | ||
2538 | if (hba->auto_bkops_enabled) | |
2539 | goto out; | |
2540 | ||
2541 | err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG, | |
2542 | QUERY_FLAG_IDN_BKOPS_EN, NULL); | |
2543 | if (err) { | |
2544 | dev_err(hba->dev, "%s: failed to enable bkops %d\n", | |
2545 | __func__, err); | |
2546 | goto out; | |
2547 | } | |
2548 | ||
2549 | hba->auto_bkops_enabled = true; | |
2550 | ||
2551 | /* No need of URGENT_BKOPS exception from the device */ | |
2552 | err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); | |
2553 | if (err) | |
2554 | dev_err(hba->dev, "%s: failed to disable exception event %d\n", | |
2555 | __func__, err); | |
2556 | out: | |
2557 | return err; | |
2558 | } | |
2559 | ||
2560 | /** | |
2561 | * ufshcd_disable_auto_bkops - block device in doing background operations | |
2562 | * @hba: per-adapter instance | |
2563 | * | |
2564 | * Disabling background operations improves command response latency but | |
2565 | * has drawback of device moving into critical state where the device is | |
2566 | * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the | |
2567 | * host is idle so that BKOPS are managed effectively without any negative | |
2568 | * impacts. | |
2569 | * | |
2570 | * Returns zero on success, non-zero on failure. | |
2571 | */ | |
2572 | static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) | |
2573 | { | |
2574 | int err = 0; | |
2575 | ||
2576 | if (!hba->auto_bkops_enabled) | |
2577 | goto out; | |
2578 | ||
2579 | /* | |
2580 | * If host assisted BKOPs is to be enabled, make sure | |
2581 | * urgent bkops exception is allowed. | |
2582 | */ | |
2583 | err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); | |
2584 | if (err) { | |
2585 | dev_err(hba->dev, "%s: failed to enable exception event %d\n", | |
2586 | __func__, err); | |
2587 | goto out; | |
2588 | } | |
2589 | ||
2590 | err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, | |
2591 | QUERY_FLAG_IDN_BKOPS_EN, NULL); | |
2592 | if (err) { | |
2593 | dev_err(hba->dev, "%s: failed to disable bkops %d\n", | |
2594 | __func__, err); | |
2595 | ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); | |
2596 | goto out; | |
2597 | } | |
2598 | ||
2599 | hba->auto_bkops_enabled = false; | |
2600 | out: | |
2601 | return err; | |
2602 | } | |
2603 | ||
2604 | /** | |
2605 | * ufshcd_force_reset_auto_bkops - force enable of auto bkops | |
2606 | * @hba: per adapter instance | |
2607 | * | |
2608 | * After a device reset the device may toggle the BKOPS_EN flag | |
2609 | * to default value. The s/w tracking variables should be updated | |
2610 | * as well. Do this by forcing enable of auto bkops. | |
2611 | */ | |
2612 | static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) | |
2613 | { | |
2614 | hba->auto_bkops_enabled = false; | |
2615 | hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; | |
2616 | ufshcd_enable_auto_bkops(hba); | |
2617 | } | |
2618 | ||
2619 | static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) | |
2620 | { | |
2621 | return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR, | |
2622 | QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); | |
2623 | } | |
2624 | ||
2625 | /** | |
2626 | * ufshcd_urgent_bkops - handle urgent bkops exception event | |
2627 | * @hba: per-adapter instance | |
2628 | * | |
2629 | * Enable fBackgroundOpsEn flag in the device to permit background | |
2630 | * operations. | |
2631 | */ | |
2632 | static int ufshcd_urgent_bkops(struct ufs_hba *hba) | |
2633 | { | |
2634 | int err; | |
2635 | u32 status = 0; | |
2636 | ||
2637 | err = ufshcd_get_bkops_status(hba, &status); | |
2638 | if (err) { | |
2639 | dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", | |
2640 | __func__, err); | |
2641 | goto out; | |
2642 | } | |
2643 | ||
2644 | status = status & 0xF; | |
2645 | ||
2646 | /* handle only if status indicates performance impact or critical */ | |
2647 | if (status >= BKOPS_STATUS_PERF_IMPACT) | |
2648 | err = ufshcd_enable_auto_bkops(hba); | |
2649 | out: | |
2650 | return err; | |
2651 | } | |
2652 | ||
2653 | static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) | |
2654 | { | |
2655 | return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR, | |
2656 | QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); | |
2657 | } | |
2658 | ||
2659 | /** | |
2660 | * ufshcd_exception_event_handler - handle exceptions raised by device | |
2661 | * @work: pointer to work data | |
2662 | * | |
2663 | * Read bExceptionEventStatus attribute from the device and handle the | |
2664 | * exception event accordingly. | |
2665 | */ | |
2666 | static void ufshcd_exception_event_handler(struct work_struct *work) | |
2667 | { | |
2668 | struct ufs_hba *hba; | |
2669 | int err; | |
2670 | u32 status = 0; | |
2671 | hba = container_of(work, struct ufs_hba, eeh_work); | |
2672 | ||
62694735 | 2673 | pm_runtime_get_sync(hba->dev); |
66ec6d59 SRT |
2674 | err = ufshcd_get_ee_status(hba, &status); |
2675 | if (err) { | |
2676 | dev_err(hba->dev, "%s: failed to get exception status %d\n", | |
2677 | __func__, err); | |
2678 | goto out; | |
2679 | } | |
2680 | ||
2681 | status &= hba->ee_ctrl_mask; | |
2682 | if (status & MASK_EE_URGENT_BKOPS) { | |
2683 | err = ufshcd_urgent_bkops(hba); | |
2684 | if (err) | |
2685 | dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", | |
2686 | __func__, err); | |
2687 | } | |
2688 | out: | |
62694735 | 2689 | pm_runtime_put_sync(hba->dev); |
66ec6d59 SRT |
2690 | return; |
2691 | } | |
2692 | ||
7a3e97b0 | 2693 | /** |
e8e7f271 SRT |
2694 | * ufshcd_err_handler - handle UFS errors that require s/w attention |
2695 | * @work: pointer to work structure | |
7a3e97b0 | 2696 | */ |
e8e7f271 | 2697 | static void ufshcd_err_handler(struct work_struct *work) |
7a3e97b0 SY |
2698 | { |
2699 | struct ufs_hba *hba; | |
e8e7f271 SRT |
2700 | unsigned long flags; |
2701 | u32 err_xfer = 0; | |
2702 | u32 err_tm = 0; | |
2703 | int err = 0; | |
2704 | int tag; | |
2705 | ||
2706 | hba = container_of(work, struct ufs_hba, eh_work); | |
7a3e97b0 | 2707 | |
62694735 | 2708 | pm_runtime_get_sync(hba->dev); |
e8e7f271 SRT |
2709 | |
2710 | spin_lock_irqsave(hba->host->host_lock, flags); | |
2711 | if (hba->ufshcd_state == UFSHCD_STATE_RESET) { | |
2712 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
2713 | goto out; | |
2714 | } | |
2715 | ||
2716 | hba->ufshcd_state = UFSHCD_STATE_RESET; | |
2717 | ufshcd_set_eh_in_progress(hba); | |
2718 | ||
2719 | /* Complete requests that have door-bell cleared by h/w */ | |
2720 | ufshcd_transfer_req_compl(hba); | |
2721 | ufshcd_tmc_handler(hba); | |
2722 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
2723 | ||
2724 | /* Clear pending transfer requests */ | |
2725 | for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) | |
2726 | if (ufshcd_clear_cmd(hba, tag)) | |
2727 | err_xfer |= 1 << tag; | |
2728 | ||
2729 | /* Clear pending task management requests */ | |
2730 | for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) | |
2731 | if (ufshcd_clear_tm_cmd(hba, tag)) | |
2732 | err_tm |= 1 << tag; | |
2733 | ||
2734 | /* Complete the requests that are cleared by s/w */ | |
2735 | spin_lock_irqsave(hba->host->host_lock, flags); | |
2736 | ufshcd_transfer_req_compl(hba); | |
2737 | ufshcd_tmc_handler(hba); | |
2738 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
2739 | ||
2740 | /* Fatal errors need reset */ | |
2741 | if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) || | |
2742 | ((hba->saved_err & UIC_ERROR) && | |
2743 | (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) { | |
2744 | err = ufshcd_reset_and_restore(hba); | |
2745 | if (err) { | |
2746 | dev_err(hba->dev, "%s: reset and restore failed\n", | |
2747 | __func__); | |
2748 | hba->ufshcd_state = UFSHCD_STATE_ERROR; | |
2749 | } | |
2750 | /* | |
2751 | * Inform scsi mid-layer that we did reset and allow to handle | |
2752 | * Unit Attention properly. | |
2753 | */ | |
2754 | scsi_report_bus_reset(hba->host, 0); | |
2755 | hba->saved_err = 0; | |
2756 | hba->saved_uic_err = 0; | |
2757 | } | |
2758 | ufshcd_clear_eh_in_progress(hba); | |
2759 | ||
2760 | out: | |
2761 | scsi_unblock_requests(hba->host); | |
62694735 | 2762 | pm_runtime_put_sync(hba->dev); |
7a3e97b0 SY |
2763 | } |
2764 | ||
2765 | /** | |
e8e7f271 SRT |
2766 | * ufshcd_update_uic_error - check and set fatal UIC error flags. |
2767 | * @hba: per-adapter instance | |
7a3e97b0 | 2768 | */ |
e8e7f271 | 2769 | static void ufshcd_update_uic_error(struct ufs_hba *hba) |
7a3e97b0 SY |
2770 | { |
2771 | u32 reg; | |
2772 | ||
e8e7f271 SRT |
2773 | /* PA_INIT_ERROR is fatal and needs UIC reset */ |
2774 | reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); | |
2775 | if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) | |
2776 | hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; | |
2777 | ||
2778 | /* UIC NL/TL/DME errors needs software retry */ | |
2779 | reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); | |
2780 | if (reg) | |
2781 | hba->uic_error |= UFSHCD_UIC_NL_ERROR; | |
2782 | ||
2783 | reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); | |
2784 | if (reg) | |
2785 | hba->uic_error |= UFSHCD_UIC_TL_ERROR; | |
2786 | ||
2787 | reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); | |
2788 | if (reg) | |
2789 | hba->uic_error |= UFSHCD_UIC_DME_ERROR; | |
2790 | ||
2791 | dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", | |
2792 | __func__, hba->uic_error); | |
2793 | } | |
2794 | ||
2795 | /** | |
2796 | * ufshcd_check_errors - Check for errors that need s/w attention | |
2797 | * @hba: per-adapter instance | |
2798 | */ | |
2799 | static void ufshcd_check_errors(struct ufs_hba *hba) | |
2800 | { | |
2801 | bool queue_eh_work = false; | |
2802 | ||
7a3e97b0 | 2803 | if (hba->errors & INT_FATAL_ERRORS) |
e8e7f271 | 2804 | queue_eh_work = true; |
7a3e97b0 SY |
2805 | |
2806 | if (hba->errors & UIC_ERROR) { | |
e8e7f271 SRT |
2807 | hba->uic_error = 0; |
2808 | ufshcd_update_uic_error(hba); | |
2809 | if (hba->uic_error) | |
2810 | queue_eh_work = true; | |
7a3e97b0 | 2811 | } |
e8e7f271 SRT |
2812 | |
2813 | if (queue_eh_work) { | |
2814 | /* handle fatal errors only when link is functional */ | |
2815 | if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) { | |
2816 | /* block commands from scsi mid-layer */ | |
2817 | scsi_block_requests(hba->host); | |
2818 | ||
2819 | /* transfer error masks to sticky bits */ | |
2820 | hba->saved_err |= hba->errors; | |
2821 | hba->saved_uic_err |= hba->uic_error; | |
2822 | ||
2823 | hba->ufshcd_state = UFSHCD_STATE_ERROR; | |
2824 | schedule_work(&hba->eh_work); | |
2825 | } | |
3441da7d | 2826 | } |
e8e7f271 SRT |
2827 | /* |
2828 | * if (!queue_eh_work) - | |
2829 | * Other errors are either non-fatal where host recovers | |
2830 | * itself without s/w intervention or errors that will be | |
2831 | * handled by the SCSI core layer. | |
2832 | */ | |
7a3e97b0 SY |
2833 | } |
2834 | ||
2835 | /** | |
2836 | * ufshcd_tmc_handler - handle task management function completion | |
2837 | * @hba: per adapter instance | |
2838 | */ | |
2839 | static void ufshcd_tmc_handler(struct ufs_hba *hba) | |
2840 | { | |
2841 | u32 tm_doorbell; | |
2842 | ||
b873a275 | 2843 | tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); |
7a3e97b0 | 2844 | hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks; |
e2933132 | 2845 | wake_up(&hba->tm_wq); |
7a3e97b0 SY |
2846 | } |
2847 | ||
2848 | /** | |
2849 | * ufshcd_sl_intr - Interrupt service routine | |
2850 | * @hba: per adapter instance | |
2851 | * @intr_status: contains interrupts generated by the controller | |
2852 | */ | |
2853 | static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) | |
2854 | { | |
2855 | hba->errors = UFSHCD_ERROR_MASK & intr_status; | |
2856 | if (hba->errors) | |
e8e7f271 | 2857 | ufshcd_check_errors(hba); |
7a3e97b0 | 2858 | |
53b3d9c3 SJ |
2859 | if (intr_status & UFSHCD_UIC_MASK) |
2860 | ufshcd_uic_cmd_compl(hba, intr_status); | |
7a3e97b0 SY |
2861 | |
2862 | if (intr_status & UTP_TASK_REQ_COMPL) | |
2863 | ufshcd_tmc_handler(hba); | |
2864 | ||
2865 | if (intr_status & UTP_TRANSFER_REQ_COMPL) | |
2866 | ufshcd_transfer_req_compl(hba); | |
2867 | } | |
2868 | ||
2869 | /** | |
2870 | * ufshcd_intr - Main interrupt service routine | |
2871 | * @irq: irq number | |
2872 | * @__hba: pointer to adapter instance | |
2873 | * | |
2874 | * Returns IRQ_HANDLED - If interrupt is valid | |
2875 | * IRQ_NONE - If invalid interrupt | |
2876 | */ | |
2877 | static irqreturn_t ufshcd_intr(int irq, void *__hba) | |
2878 | { | |
2879 | u32 intr_status; | |
2880 | irqreturn_t retval = IRQ_NONE; | |
2881 | struct ufs_hba *hba = __hba; | |
2882 | ||
2883 | spin_lock(hba->host->host_lock); | |
b873a275 | 2884 | intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); |
7a3e97b0 SY |
2885 | |
2886 | if (intr_status) { | |
261ea452 | 2887 | ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); |
7a3e97b0 | 2888 | ufshcd_sl_intr(hba, intr_status); |
7a3e97b0 SY |
2889 | retval = IRQ_HANDLED; |
2890 | } | |
2891 | spin_unlock(hba->host->host_lock); | |
2892 | return retval; | |
2893 | } | |
2894 | ||
e2933132 SRT |
2895 | static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) |
2896 | { | |
2897 | int err = 0; | |
2898 | u32 mask = 1 << tag; | |
2899 | unsigned long flags; | |
2900 | ||
2901 | if (!test_bit(tag, &hba->outstanding_tasks)) | |
2902 | goto out; | |
2903 | ||
2904 | spin_lock_irqsave(hba->host->host_lock, flags); | |
2905 | ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR); | |
2906 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
2907 | ||
2908 | /* poll for max. 1 sec to clear door bell register by h/w */ | |
2909 | err = ufshcd_wait_for_register(hba, | |
2910 | REG_UTP_TASK_REQ_DOOR_BELL, | |
2911 | mask, 0, 1000, 1000); | |
2912 | out: | |
2913 | return err; | |
2914 | } | |
2915 | ||
7a3e97b0 SY |
2916 | /** |
2917 | * ufshcd_issue_tm_cmd - issues task management commands to controller | |
2918 | * @hba: per adapter instance | |
e2933132 SRT |
2919 | * @lun_id: LUN ID to which TM command is sent |
2920 | * @task_id: task ID to which the TM command is applicable | |
2921 | * @tm_function: task management function opcode | |
2922 | * @tm_response: task management service response return value | |
7a3e97b0 | 2923 | * |
e2933132 | 2924 | * Returns non-zero value on error, zero on success. |
7a3e97b0 | 2925 | */ |
e2933132 SRT |
2926 | static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, |
2927 | u8 tm_function, u8 *tm_response) | |
7a3e97b0 SY |
2928 | { |
2929 | struct utp_task_req_desc *task_req_descp; | |
2930 | struct utp_upiu_task_req *task_req_upiup; | |
2931 | struct Scsi_Host *host; | |
2932 | unsigned long flags; | |
e2933132 | 2933 | int free_slot; |
7a3e97b0 | 2934 | int err; |
e2933132 | 2935 | int task_tag; |
7a3e97b0 SY |
2936 | |
2937 | host = hba->host; | |
2938 | ||
e2933132 SRT |
2939 | /* |
2940 | * Get free slot, sleep if slots are unavailable. | |
2941 | * Even though we use wait_event() which sleeps indefinitely, | |
2942 | * the maximum wait time is bounded by %TM_CMD_TIMEOUT. | |
2943 | */ | |
2944 | wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot)); | |
7a3e97b0 | 2945 | |
e2933132 | 2946 | spin_lock_irqsave(host->host_lock, flags); |
7a3e97b0 SY |
2947 | task_req_descp = hba->utmrdl_base_addr; |
2948 | task_req_descp += free_slot; | |
2949 | ||
2950 | /* Configure task request descriptor */ | |
2951 | task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD); | |
2952 | task_req_descp->header.dword_2 = | |
2953 | cpu_to_le32(OCS_INVALID_COMMAND_STATUS); | |
2954 | ||
2955 | /* Configure task request UPIU */ | |
2956 | task_req_upiup = | |
2957 | (struct utp_upiu_task_req *) task_req_descp->task_req_upiu; | |
e2933132 | 2958 | task_tag = hba->nutrs + free_slot; |
7a3e97b0 | 2959 | task_req_upiup->header.dword_0 = |
5a0b0cb9 | 2960 | UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0, |
e2933132 | 2961 | lun_id, task_tag); |
7a3e97b0 | 2962 | task_req_upiup->header.dword_1 = |
5a0b0cb9 | 2963 | UPIU_HEADER_DWORD(0, tm_function, 0, 0); |
7a3e97b0 | 2964 | |
e2933132 SRT |
2965 | task_req_upiup->input_param1 = cpu_to_be32(lun_id); |
2966 | task_req_upiup->input_param2 = cpu_to_be32(task_id); | |
7a3e97b0 SY |
2967 | |
2968 | /* send command to the controller */ | |
2969 | __set_bit(free_slot, &hba->outstanding_tasks); | |
b873a275 | 2970 | ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL); |
7a3e97b0 SY |
2971 | |
2972 | spin_unlock_irqrestore(host->host_lock, flags); | |
2973 | ||
2974 | /* wait until the task management command is completed */ | |
e2933132 SRT |
2975 | err = wait_event_timeout(hba->tm_wq, |
2976 | test_bit(free_slot, &hba->tm_condition), | |
2977 | msecs_to_jiffies(TM_CMD_TIMEOUT)); | |
7a3e97b0 | 2978 | if (!err) { |
e2933132 SRT |
2979 | dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", |
2980 | __func__, tm_function); | |
2981 | if (ufshcd_clear_tm_cmd(hba, free_slot)) | |
2982 | dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n", | |
2983 | __func__, free_slot); | |
2984 | err = -ETIMEDOUT; | |
2985 | } else { | |
2986 | err = ufshcd_task_req_compl(hba, free_slot, tm_response); | |
7a3e97b0 | 2987 | } |
e2933132 | 2988 | |
7a3e97b0 | 2989 | clear_bit(free_slot, &hba->tm_condition); |
e2933132 SRT |
2990 | ufshcd_put_tm_slot(hba, free_slot); |
2991 | wake_up(&hba->tm_tag_wq); | |
2992 | ||
7a3e97b0 SY |
2993 | return err; |
2994 | } | |
2995 | ||
2996 | /** | |
3441da7d SRT |
2997 | * ufshcd_eh_device_reset_handler - device reset handler registered to |
2998 | * scsi layer. | |
7a3e97b0 SY |
2999 | * @cmd: SCSI command pointer |
3000 | * | |
3001 | * Returns SUCCESS/FAILED | |
3002 | */ | |
3441da7d | 3003 | static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) |
7a3e97b0 SY |
3004 | { |
3005 | struct Scsi_Host *host; | |
3006 | struct ufs_hba *hba; | |
3007 | unsigned int tag; | |
3008 | u32 pos; | |
3009 | int err; | |
e2933132 SRT |
3010 | u8 resp = 0xF; |
3011 | struct ufshcd_lrb *lrbp; | |
3441da7d | 3012 | unsigned long flags; |
7a3e97b0 SY |
3013 | |
3014 | host = cmd->device->host; | |
3015 | hba = shost_priv(host); | |
3016 | tag = cmd->request->tag; | |
3017 | ||
e2933132 SRT |
3018 | lrbp = &hba->lrb[tag]; |
3019 | err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp); | |
3020 | if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { | |
3441da7d SRT |
3021 | if (!err) |
3022 | err = resp; | |
7a3e97b0 | 3023 | goto out; |
e2933132 | 3024 | } |
7a3e97b0 | 3025 | |
3441da7d SRT |
3026 | /* clear the commands that were pending for corresponding LUN */ |
3027 | for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) { | |
3028 | if (hba->lrb[pos].lun == lrbp->lun) { | |
3029 | err = ufshcd_clear_cmd(hba, pos); | |
3030 | if (err) | |
3031 | break; | |
7a3e97b0 | 3032 | } |
3441da7d SRT |
3033 | } |
3034 | spin_lock_irqsave(host->host_lock, flags); | |
3035 | ufshcd_transfer_req_compl(hba); | |
3036 | spin_unlock_irqrestore(host->host_lock, flags); | |
7a3e97b0 | 3037 | out: |
3441da7d SRT |
3038 | if (!err) { |
3039 | err = SUCCESS; | |
3040 | } else { | |
3041 | dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); | |
3042 | err = FAILED; | |
3043 | } | |
7a3e97b0 SY |
3044 | return err; |
3045 | } | |
3046 | ||
7a3e97b0 SY |
3047 | /** |
3048 | * ufshcd_abort - abort a specific command | |
3049 | * @cmd: SCSI command pointer | |
3050 | * | |
f20810d8 SRT |
3051 | * Abort the pending command in device by sending UFS_ABORT_TASK task management |
3052 | * command, and in host controller by clearing the door-bell register. There can | |
3053 | * be race between controller sending the command to the device while abort is | |
3054 | * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is | |
3055 | * really issued and then try to abort it. | |
3056 | * | |
7a3e97b0 SY |
3057 | * Returns SUCCESS/FAILED |
3058 | */ | |
3059 | static int ufshcd_abort(struct scsi_cmnd *cmd) | |
3060 | { | |
3061 | struct Scsi_Host *host; | |
3062 | struct ufs_hba *hba; | |
3063 | unsigned long flags; | |
3064 | unsigned int tag; | |
f20810d8 SRT |
3065 | int err = 0; |
3066 | int poll_cnt; | |
e2933132 SRT |
3067 | u8 resp = 0xF; |
3068 | struct ufshcd_lrb *lrbp; | |
e9d501b1 | 3069 | u32 reg; |
7a3e97b0 SY |
3070 | |
3071 | host = cmd->device->host; | |
3072 | hba = shost_priv(host); | |
3073 | tag = cmd->request->tag; | |
3074 | ||
f20810d8 SRT |
3075 | /* If command is already aborted/completed, return SUCCESS */ |
3076 | if (!(test_bit(tag, &hba->outstanding_reqs))) | |
3077 | goto out; | |
7a3e97b0 | 3078 | |
e9d501b1 DR |
3079 | reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); |
3080 | if (!(reg & (1 << tag))) { | |
3081 | dev_err(hba->dev, | |
3082 | "%s: cmd was completed, but without a notifying intr, tag = %d", | |
3083 | __func__, tag); | |
3084 | } | |
3085 | ||
f20810d8 SRT |
3086 | lrbp = &hba->lrb[tag]; |
3087 | for (poll_cnt = 100; poll_cnt; poll_cnt--) { | |
3088 | err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, | |
3089 | UFS_QUERY_TASK, &resp); | |
3090 | if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { | |
3091 | /* cmd pending in the device */ | |
3092 | break; | |
3093 | } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { | |
f20810d8 SRT |
3094 | /* |
3095 | * cmd not pending in the device, check if it is | |
3096 | * in transition. | |
3097 | */ | |
3098 | reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); | |
3099 | if (reg & (1 << tag)) { | |
3100 | /* sleep for max. 200us to stabilize */ | |
3101 | usleep_range(100, 200); | |
3102 | continue; | |
3103 | } | |
3104 | /* command completed already */ | |
3105 | goto out; | |
3106 | } else { | |
3107 | if (!err) | |
3108 | err = resp; /* service response error */ | |
3109 | goto out; | |
3110 | } | |
3111 | } | |
3112 | ||
3113 | if (!poll_cnt) { | |
3114 | err = -EBUSY; | |
7a3e97b0 SY |
3115 | goto out; |
3116 | } | |
7a3e97b0 | 3117 | |
e2933132 SRT |
3118 | err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, |
3119 | UFS_ABORT_TASK, &resp); | |
3120 | if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { | |
f20810d8 SRT |
3121 | if (!err) |
3122 | err = resp; /* service response error */ | |
7a3e97b0 | 3123 | goto out; |
e2933132 | 3124 | } |
7a3e97b0 | 3125 | |
f20810d8 SRT |
3126 | err = ufshcd_clear_cmd(hba, tag); |
3127 | if (err) | |
3128 | goto out; | |
3129 | ||
7a3e97b0 SY |
3130 | scsi_dma_unmap(cmd); |
3131 | ||
3132 | spin_lock_irqsave(host->host_lock, flags); | |
7a3e97b0 SY |
3133 | __clear_bit(tag, &hba->outstanding_reqs); |
3134 | hba->lrb[tag].cmd = NULL; | |
3135 | spin_unlock_irqrestore(host->host_lock, flags); | |
5a0b0cb9 SRT |
3136 | |
3137 | clear_bit_unlock(tag, &hba->lrb_in_use); | |
3138 | wake_up(&hba->dev_cmd.tag_wq); | |
7a3e97b0 | 3139 | out: |
f20810d8 SRT |
3140 | if (!err) { |
3141 | err = SUCCESS; | |
3142 | } else { | |
3143 | dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); | |
3144 | err = FAILED; | |
3145 | } | |
3146 | ||
7a3e97b0 SY |
3147 | return err; |
3148 | } | |
3149 | ||
3441da7d SRT |
3150 | /** |
3151 | * ufshcd_host_reset_and_restore - reset and restore host controller | |
3152 | * @hba: per-adapter instance | |
3153 | * | |
3154 | * Note that host controller reset may issue DME_RESET to | |
3155 | * local and remote (device) Uni-Pro stack and the attributes | |
3156 | * are reset to default state. | |
3157 | * | |
3158 | * Returns zero on success, non-zero on failure | |
3159 | */ | |
3160 | static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) | |
3161 | { | |
3162 | int err; | |
3441da7d SRT |
3163 | unsigned long flags; |
3164 | ||
3165 | /* Reset the host controller */ | |
3166 | spin_lock_irqsave(hba->host->host_lock, flags); | |
3167 | ufshcd_hba_stop(hba); | |
3168 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3169 | ||
3170 | err = ufshcd_hba_enable(hba); | |
3171 | if (err) | |
3172 | goto out; | |
3173 | ||
3174 | /* Establish the link again and restore the device */ | |
1d337ec2 SRT |
3175 | err = ufshcd_probe_hba(hba); |
3176 | ||
3177 | if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)) | |
3441da7d SRT |
3178 | err = -EIO; |
3179 | out: | |
3180 | if (err) | |
3181 | dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); | |
3182 | ||
3183 | return err; | |
3184 | } | |
3185 | ||
3186 | /** | |
3187 | * ufshcd_reset_and_restore - reset and re-initialize host/device | |
3188 | * @hba: per-adapter instance | |
3189 | * | |
3190 | * Reset and recover device, host and re-establish link. This | |
3191 | * is helpful to recover the communication in fatal error conditions. | |
3192 | * | |
3193 | * Returns zero on success, non-zero on failure | |
3194 | */ | |
3195 | static int ufshcd_reset_and_restore(struct ufs_hba *hba) | |
3196 | { | |
3197 | int err = 0; | |
3198 | unsigned long flags; | |
1d337ec2 | 3199 | int retries = MAX_HOST_RESET_RETRIES; |
3441da7d | 3200 | |
1d337ec2 SRT |
3201 | do { |
3202 | err = ufshcd_host_reset_and_restore(hba); | |
3203 | } while (err && --retries); | |
3441da7d SRT |
3204 | |
3205 | /* | |
3206 | * After reset the door-bell might be cleared, complete | |
3207 | * outstanding requests in s/w here. | |
3208 | */ | |
3209 | spin_lock_irqsave(hba->host->host_lock, flags); | |
3210 | ufshcd_transfer_req_compl(hba); | |
3211 | ufshcd_tmc_handler(hba); | |
3212 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3213 | ||
3214 | return err; | |
3215 | } | |
3216 | ||
3217 | /** | |
3218 | * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer | |
3219 | * @cmd - SCSI command pointer | |
3220 | * | |
3221 | * Returns SUCCESS/FAILED | |
3222 | */ | |
3223 | static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) | |
3224 | { | |
3225 | int err; | |
3226 | unsigned long flags; | |
3227 | struct ufs_hba *hba; | |
3228 | ||
3229 | hba = shost_priv(cmd->device->host); | |
3230 | ||
3231 | /* | |
3232 | * Check if there is any race with fatal error handling. | |
3233 | * If so, wait for it to complete. Even though fatal error | |
3234 | * handling does reset and restore in some cases, don't assume | |
3235 | * anything out of it. We are just avoiding race here. | |
3236 | */ | |
3237 | do { | |
3238 | spin_lock_irqsave(hba->host->host_lock, flags); | |
e8e7f271 | 3239 | if (!(work_pending(&hba->eh_work) || |
3441da7d SRT |
3240 | hba->ufshcd_state == UFSHCD_STATE_RESET)) |
3241 | break; | |
3242 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3243 | dev_dbg(hba->dev, "%s: reset in progress\n", __func__); | |
e8e7f271 | 3244 | flush_work(&hba->eh_work); |
3441da7d SRT |
3245 | } while (1); |
3246 | ||
3247 | hba->ufshcd_state = UFSHCD_STATE_RESET; | |
3248 | ufshcd_set_eh_in_progress(hba); | |
3249 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3250 | ||
3251 | err = ufshcd_reset_and_restore(hba); | |
3252 | ||
3253 | spin_lock_irqsave(hba->host->host_lock, flags); | |
3254 | if (!err) { | |
3255 | err = SUCCESS; | |
3256 | hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; | |
3257 | } else { | |
3258 | err = FAILED; | |
3259 | hba->ufshcd_state = UFSHCD_STATE_ERROR; | |
3260 | } | |
3261 | ufshcd_clear_eh_in_progress(hba); | |
3262 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
3263 | ||
3264 | return err; | |
3265 | } | |
3266 | ||
3a4bf06d YG |
3267 | /** |
3268 | * ufshcd_get_max_icc_level - calculate the ICC level | |
3269 | * @sup_curr_uA: max. current supported by the regulator | |
3270 | * @start_scan: row at the desc table to start scan from | |
3271 | * @buff: power descriptor buffer | |
3272 | * | |
3273 | * Returns calculated max ICC level for specific regulator | |
3274 | */ | |
3275 | static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff) | |
3276 | { | |
3277 | int i; | |
3278 | int curr_uA; | |
3279 | u16 data; | |
3280 | u16 unit; | |
3281 | ||
3282 | for (i = start_scan; i >= 0; i--) { | |
3283 | data = be16_to_cpu(*((u16 *)(buff + 2*i))); | |
3284 | unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> | |
3285 | ATTR_ICC_LVL_UNIT_OFFSET; | |
3286 | curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; | |
3287 | switch (unit) { | |
3288 | case UFSHCD_NANO_AMP: | |
3289 | curr_uA = curr_uA / 1000; | |
3290 | break; | |
3291 | case UFSHCD_MILI_AMP: | |
3292 | curr_uA = curr_uA * 1000; | |
3293 | break; | |
3294 | case UFSHCD_AMP: | |
3295 | curr_uA = curr_uA * 1000 * 1000; | |
3296 | break; | |
3297 | case UFSHCD_MICRO_AMP: | |
3298 | default: | |
3299 | break; | |
3300 | } | |
3301 | if (sup_curr_uA >= curr_uA) | |
3302 | break; | |
3303 | } | |
3304 | if (i < 0) { | |
3305 | i = 0; | |
3306 | pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); | |
3307 | } | |
3308 | ||
3309 | return (u32)i; | |
3310 | } | |
3311 | ||
3312 | /** | |
3313 | * ufshcd_calc_icc_level - calculate the max ICC level | |
3314 | * In case regulators are not initialized we'll return 0 | |
3315 | * @hba: per-adapter instance | |
3316 | * @desc_buf: power descriptor buffer to extract ICC levels from. | |
3317 | * @len: length of desc_buff | |
3318 | * | |
3319 | * Returns calculated ICC level | |
3320 | */ | |
3321 | static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, | |
3322 | u8 *desc_buf, int len) | |
3323 | { | |
3324 | u32 icc_level = 0; | |
3325 | ||
3326 | if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || | |
3327 | !hba->vreg_info.vccq2) { | |
3328 | dev_err(hba->dev, | |
3329 | "%s: Regulator capability was not set, actvIccLevel=%d", | |
3330 | __func__, icc_level); | |
3331 | goto out; | |
3332 | } | |
3333 | ||
3334 | if (hba->vreg_info.vcc) | |
3335 | icc_level = ufshcd_get_max_icc_level( | |
3336 | hba->vreg_info.vcc->max_uA, | |
3337 | POWER_DESC_MAX_ACTV_ICC_LVLS - 1, | |
3338 | &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); | |
3339 | ||
3340 | if (hba->vreg_info.vccq) | |
3341 | icc_level = ufshcd_get_max_icc_level( | |
3342 | hba->vreg_info.vccq->max_uA, | |
3343 | icc_level, | |
3344 | &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); | |
3345 | ||
3346 | if (hba->vreg_info.vccq2) | |
3347 | icc_level = ufshcd_get_max_icc_level( | |
3348 | hba->vreg_info.vccq2->max_uA, | |
3349 | icc_level, | |
3350 | &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); | |
3351 | out: | |
3352 | return icc_level; | |
3353 | } | |
3354 | ||
3355 | static void ufshcd_init_icc_levels(struct ufs_hba *hba) | |
3356 | { | |
3357 | int ret; | |
3358 | int buff_len = QUERY_DESC_POWER_MAX_SIZE; | |
3359 | u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE]; | |
3360 | ||
3361 | ret = ufshcd_read_power_desc(hba, desc_buf, buff_len); | |
3362 | if (ret) { | |
3363 | dev_err(hba->dev, | |
3364 | "%s: Failed reading power descriptor.len = %d ret = %d", | |
3365 | __func__, buff_len, ret); | |
3366 | return; | |
3367 | } | |
3368 | ||
3369 | hba->init_prefetch_data.icc_level = | |
3370 | ufshcd_find_max_sup_active_icc_level(hba, | |
3371 | desc_buf, buff_len); | |
3372 | dev_dbg(hba->dev, "%s: setting icc_level 0x%x", | |
3373 | __func__, hba->init_prefetch_data.icc_level); | |
3374 | ||
3375 | ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, | |
3376 | QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, | |
3377 | &hba->init_prefetch_data.icc_level); | |
3378 | ||
3379 | if (ret) | |
3380 | dev_err(hba->dev, | |
3381 | "%s: Failed configuring bActiveICCLevel = %d ret = %d", | |
3382 | __func__, hba->init_prefetch_data.icc_level , ret); | |
3383 | ||
3384 | } | |
3385 | ||
6ccf44fe | 3386 | /** |
1d337ec2 SRT |
3387 | * ufshcd_probe_hba - probe hba to detect device and initialize |
3388 | * @hba: per-adapter instance | |
3389 | * | |
3390 | * Execute link-startup and verify device initialization | |
6ccf44fe | 3391 | */ |
1d337ec2 | 3392 | static int ufshcd_probe_hba(struct ufs_hba *hba) |
6ccf44fe | 3393 | { |
6ccf44fe SJ |
3394 | int ret; |
3395 | ||
3396 | ret = ufshcd_link_startup(hba); | |
5a0b0cb9 SRT |
3397 | if (ret) |
3398 | goto out; | |
3399 | ||
d3e89bac SJ |
3400 | ufshcd_config_max_pwr_mode(hba); |
3401 | ||
5a0b0cb9 SRT |
3402 | ret = ufshcd_verify_dev_init(hba); |
3403 | if (ret) | |
3404 | goto out; | |
68078d5c DR |
3405 | |
3406 | ret = ufshcd_complete_dev_init(hba); | |
3407 | if (ret) | |
3408 | goto out; | |
5a0b0cb9 | 3409 | |
66ec6d59 | 3410 | ufshcd_force_reset_auto_bkops(hba); |
3441da7d SRT |
3411 | hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; |
3412 | ||
3413 | /* If we are in error handling context no need to scan the host */ | |
3414 | if (!ufshcd_eh_in_progress(hba)) { | |
3a4bf06d YG |
3415 | if (!hba->is_init_prefetch) |
3416 | ufshcd_init_icc_levels(hba); | |
3417 | ||
3441da7d SRT |
3418 | scsi_scan_host(hba->host); |
3419 | pm_runtime_put_sync(hba->dev); | |
3420 | } | |
3a4bf06d YG |
3421 | |
3422 | if (!hba->is_init_prefetch) | |
3423 | hba->is_init_prefetch = true; | |
3424 | ||
5a0b0cb9 | 3425 | out: |
1d337ec2 SRT |
3426 | /* |
3427 | * If we failed to initialize the device or the device is not | |
3428 | * present, turn off the power/clocks etc. | |
3429 | */ | |
3430 | if (ret && !ufshcd_eh_in_progress(hba)) | |
3431 | ufshcd_hba_exit(hba); | |
3432 | ||
3433 | return ret; | |
3434 | } | |
3435 | ||
3436 | /** | |
3437 | * ufshcd_async_scan - asynchronous execution for probing hba | |
3438 | * @data: data pointer to pass to this function | |
3439 | * @cookie: cookie data | |
3440 | */ | |
3441 | static void ufshcd_async_scan(void *data, async_cookie_t cookie) | |
3442 | { | |
3443 | struct ufs_hba *hba = (struct ufs_hba *)data; | |
3444 | ||
3445 | ufshcd_probe_hba(hba); | |
6ccf44fe SJ |
3446 | } |
3447 | ||
7a3e97b0 SY |
3448 | static struct scsi_host_template ufshcd_driver_template = { |
3449 | .module = THIS_MODULE, | |
3450 | .name = UFSHCD, | |
3451 | .proc_name = UFSHCD, | |
3452 | .queuecommand = ufshcd_queuecommand, | |
3453 | .slave_alloc = ufshcd_slave_alloc, | |
eeda4749 | 3454 | .slave_configure = ufshcd_slave_configure, |
7a3e97b0 | 3455 | .slave_destroy = ufshcd_slave_destroy, |
4264fd61 | 3456 | .change_queue_depth = ufshcd_change_queue_depth, |
7a3e97b0 | 3457 | .eh_abort_handler = ufshcd_abort, |
3441da7d SRT |
3458 | .eh_device_reset_handler = ufshcd_eh_device_reset_handler, |
3459 | .eh_host_reset_handler = ufshcd_eh_host_reset_handler, | |
7a3e97b0 SY |
3460 | .this_id = -1, |
3461 | .sg_tablesize = SG_ALL, | |
3462 | .cmd_per_lun = UFSHCD_CMD_PER_LUN, | |
3463 | .can_queue = UFSHCD_CAN_QUEUE, | |
3464 | }; | |
3465 | ||
aa497613 SRT |
3466 | static int ufshcd_config_vreg(struct device *dev, |
3467 | struct ufs_vreg *vreg, bool on) | |
3468 | { | |
3469 | int ret = 0; | |
3470 | struct regulator *reg = vreg->reg; | |
3471 | const char *name = vreg->name; | |
3472 | int min_uV, uA_load; | |
3473 | ||
3474 | BUG_ON(!vreg); | |
3475 | ||
3476 | if (regulator_count_voltages(reg) > 0) { | |
3477 | min_uV = on ? vreg->min_uV : 0; | |
3478 | ret = regulator_set_voltage(reg, min_uV, vreg->max_uV); | |
3479 | if (ret) { | |
3480 | dev_err(dev, "%s: %s set voltage failed, err=%d\n", | |
3481 | __func__, name, ret); | |
3482 | goto out; | |
3483 | } | |
3484 | ||
3485 | uA_load = on ? vreg->max_uA : 0; | |
3486 | ret = regulator_set_optimum_mode(reg, uA_load); | |
3487 | if (ret >= 0) { | |
3488 | /* | |
3489 | * regulator_set_optimum_mode() returns new regulator | |
3490 | * mode upon success. | |
3491 | */ | |
3492 | ret = 0; | |
3493 | } else { | |
3494 | dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n", | |
3495 | __func__, name, uA_load, ret); | |
3496 | goto out; | |
3497 | } | |
3498 | } | |
3499 | out: | |
3500 | return ret; | |
3501 | } | |
3502 | ||
3503 | static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) | |
3504 | { | |
3505 | int ret = 0; | |
3506 | ||
3507 | if (!vreg || vreg->enabled) | |
3508 | goto out; | |
3509 | ||
3510 | ret = ufshcd_config_vreg(dev, vreg, true); | |
3511 | if (!ret) | |
3512 | ret = regulator_enable(vreg->reg); | |
3513 | ||
3514 | if (!ret) | |
3515 | vreg->enabled = true; | |
3516 | else | |
3517 | dev_err(dev, "%s: %s enable failed, err=%d\n", | |
3518 | __func__, vreg->name, ret); | |
3519 | out: | |
3520 | return ret; | |
3521 | } | |
3522 | ||
3523 | static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) | |
3524 | { | |
3525 | int ret = 0; | |
3526 | ||
3527 | if (!vreg || !vreg->enabled) | |
3528 | goto out; | |
3529 | ||
3530 | ret = regulator_disable(vreg->reg); | |
3531 | ||
3532 | if (!ret) { | |
3533 | /* ignore errors on applying disable config */ | |
3534 | ufshcd_config_vreg(dev, vreg, false); | |
3535 | vreg->enabled = false; | |
3536 | } else { | |
3537 | dev_err(dev, "%s: %s disable failed, err=%d\n", | |
3538 | __func__, vreg->name, ret); | |
3539 | } | |
3540 | out: | |
3541 | return ret; | |
3542 | } | |
3543 | ||
3544 | static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) | |
3545 | { | |
3546 | int ret = 0; | |
3547 | struct device *dev = hba->dev; | |
3548 | struct ufs_vreg_info *info = &hba->vreg_info; | |
3549 | ||
3550 | if (!info) | |
3551 | goto out; | |
3552 | ||
3553 | ret = ufshcd_toggle_vreg(dev, info->vcc, on); | |
3554 | if (ret) | |
3555 | goto out; | |
3556 | ||
3557 | ret = ufshcd_toggle_vreg(dev, info->vccq, on); | |
3558 | if (ret) | |
3559 | goto out; | |
3560 | ||
3561 | ret = ufshcd_toggle_vreg(dev, info->vccq2, on); | |
3562 | if (ret) | |
3563 | goto out; | |
3564 | ||
3565 | out: | |
3566 | if (ret) { | |
3567 | ufshcd_toggle_vreg(dev, info->vccq2, false); | |
3568 | ufshcd_toggle_vreg(dev, info->vccq, false); | |
3569 | ufshcd_toggle_vreg(dev, info->vcc, false); | |
3570 | } | |
3571 | return ret; | |
3572 | } | |
3573 | ||
6a771a65 RS |
3574 | static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) |
3575 | { | |
3576 | struct ufs_vreg_info *info = &hba->vreg_info; | |
3577 | ||
3578 | if (info) | |
3579 | return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); | |
3580 | ||
3581 | return 0; | |
3582 | } | |
3583 | ||
aa497613 SRT |
3584 | static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) |
3585 | { | |
3586 | int ret = 0; | |
3587 | ||
3588 | if (!vreg) | |
3589 | goto out; | |
3590 | ||
3591 | vreg->reg = devm_regulator_get(dev, vreg->name); | |
3592 | if (IS_ERR(vreg->reg)) { | |
3593 | ret = PTR_ERR(vreg->reg); | |
3594 | dev_err(dev, "%s: %s get failed, err=%d\n", | |
3595 | __func__, vreg->name, ret); | |
3596 | } | |
3597 | out: | |
3598 | return ret; | |
3599 | } | |
3600 | ||
3601 | static int ufshcd_init_vreg(struct ufs_hba *hba) | |
3602 | { | |
3603 | int ret = 0; | |
3604 | struct device *dev = hba->dev; | |
3605 | struct ufs_vreg_info *info = &hba->vreg_info; | |
3606 | ||
3607 | if (!info) | |
3608 | goto out; | |
3609 | ||
3610 | ret = ufshcd_get_vreg(dev, info->vcc); | |
3611 | if (ret) | |
3612 | goto out; | |
3613 | ||
3614 | ret = ufshcd_get_vreg(dev, info->vccq); | |
3615 | if (ret) | |
3616 | goto out; | |
3617 | ||
3618 | ret = ufshcd_get_vreg(dev, info->vccq2); | |
3619 | out: | |
3620 | return ret; | |
3621 | } | |
3622 | ||
6a771a65 RS |
3623 | static int ufshcd_init_hba_vreg(struct ufs_hba *hba) |
3624 | { | |
3625 | struct ufs_vreg_info *info = &hba->vreg_info; | |
3626 | ||
3627 | if (info) | |
3628 | return ufshcd_get_vreg(hba->dev, info->vdd_hba); | |
3629 | ||
3630 | return 0; | |
3631 | } | |
3632 | ||
c6e79dac SRT |
3633 | static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) |
3634 | { | |
3635 | int ret = 0; | |
3636 | struct ufs_clk_info *clki; | |
3637 | struct list_head *head = &hba->clk_list_head; | |
3638 | ||
3639 | if (!head || list_empty(head)) | |
3640 | goto out; | |
3641 | ||
3642 | list_for_each_entry(clki, head, list) { | |
3643 | if (!IS_ERR_OR_NULL(clki->clk)) { | |
3644 | if (on && !clki->enabled) { | |
3645 | ret = clk_prepare_enable(clki->clk); | |
3646 | if (ret) { | |
3647 | dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", | |
3648 | __func__, clki->name, ret); | |
3649 | goto out; | |
3650 | } | |
3651 | } else if (!on && clki->enabled) { | |
3652 | clk_disable_unprepare(clki->clk); | |
3653 | } | |
3654 | clki->enabled = on; | |
3655 | dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, | |
3656 | clki->name, on ? "en" : "dis"); | |
3657 | } | |
3658 | } | |
3659 | out: | |
3660 | if (ret) { | |
3661 | list_for_each_entry(clki, head, list) { | |
3662 | if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) | |
3663 | clk_disable_unprepare(clki->clk); | |
3664 | } | |
3665 | } | |
3666 | return ret; | |
3667 | } | |
3668 | ||
3669 | static int ufshcd_init_clocks(struct ufs_hba *hba) | |
3670 | { | |
3671 | int ret = 0; | |
3672 | struct ufs_clk_info *clki; | |
3673 | struct device *dev = hba->dev; | |
3674 | struct list_head *head = &hba->clk_list_head; | |
3675 | ||
3676 | if (!head || list_empty(head)) | |
3677 | goto out; | |
3678 | ||
3679 | list_for_each_entry(clki, head, list) { | |
3680 | if (!clki->name) | |
3681 | continue; | |
3682 | ||
3683 | clki->clk = devm_clk_get(dev, clki->name); | |
3684 | if (IS_ERR(clki->clk)) { | |
3685 | ret = PTR_ERR(clki->clk); | |
3686 | dev_err(dev, "%s: %s clk get failed, %d\n", | |
3687 | __func__, clki->name, ret); | |
3688 | goto out; | |
3689 | } | |
3690 | ||
3691 | if (clki->max_freq) { | |
3692 | ret = clk_set_rate(clki->clk, clki->max_freq); | |
3693 | if (ret) { | |
3694 | dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", | |
3695 | __func__, clki->name, | |
3696 | clki->max_freq, ret); | |
3697 | goto out; | |
3698 | } | |
3699 | } | |
3700 | dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, | |
3701 | clki->name, clk_get_rate(clki->clk)); | |
3702 | } | |
3703 | out: | |
3704 | return ret; | |
3705 | } | |
3706 | ||
5c0c28a8 SRT |
3707 | static int ufshcd_variant_hba_init(struct ufs_hba *hba) |
3708 | { | |
3709 | int err = 0; | |
3710 | ||
3711 | if (!hba->vops) | |
3712 | goto out; | |
3713 | ||
3714 | if (hba->vops->init) { | |
3715 | err = hba->vops->init(hba); | |
3716 | if (err) | |
3717 | goto out; | |
3718 | } | |
3719 | ||
3720 | if (hba->vops->setup_clocks) { | |
3721 | err = hba->vops->setup_clocks(hba, true); | |
3722 | if (err) | |
3723 | goto out_exit; | |
3724 | } | |
3725 | ||
3726 | if (hba->vops->setup_regulators) { | |
3727 | err = hba->vops->setup_regulators(hba, true); | |
3728 | if (err) | |
3729 | goto out_clks; | |
3730 | } | |
3731 | ||
3732 | goto out; | |
3733 | ||
3734 | out_clks: | |
3735 | if (hba->vops->setup_clocks) | |
3736 | hba->vops->setup_clocks(hba, false); | |
3737 | out_exit: | |
3738 | if (hba->vops->exit) | |
3739 | hba->vops->exit(hba); | |
3740 | out: | |
3741 | if (err) | |
3742 | dev_err(hba->dev, "%s: variant %s init failed err %d\n", | |
3743 | __func__, hba->vops ? hba->vops->name : "", err); | |
3744 | return err; | |
3745 | } | |
3746 | ||
3747 | static void ufshcd_variant_hba_exit(struct ufs_hba *hba) | |
3748 | { | |
3749 | if (!hba->vops) | |
3750 | return; | |
3751 | ||
3752 | if (hba->vops->setup_clocks) | |
3753 | hba->vops->setup_clocks(hba, false); | |
3754 | ||
3755 | if (hba->vops->setup_regulators) | |
3756 | hba->vops->setup_regulators(hba, false); | |
3757 | ||
3758 | if (hba->vops->exit) | |
3759 | hba->vops->exit(hba); | |
3760 | } | |
3761 | ||
aa497613 SRT |
3762 | static int ufshcd_hba_init(struct ufs_hba *hba) |
3763 | { | |
3764 | int err; | |
3765 | ||
6a771a65 RS |
3766 | /* |
3767 | * Handle host controller power separately from the UFS device power | |
3768 | * rails as it will help controlling the UFS host controller power | |
3769 | * collapse easily which is different than UFS device power collapse. | |
3770 | * Also, enable the host controller power before we go ahead with rest | |
3771 | * of the initialization here. | |
3772 | */ | |
3773 | err = ufshcd_init_hba_vreg(hba); | |
aa497613 SRT |
3774 | if (err) |
3775 | goto out; | |
3776 | ||
6a771a65 | 3777 | err = ufshcd_setup_hba_vreg(hba, true); |
aa497613 SRT |
3778 | if (err) |
3779 | goto out; | |
3780 | ||
6a771a65 RS |
3781 | err = ufshcd_init_clocks(hba); |
3782 | if (err) | |
3783 | goto out_disable_hba_vreg; | |
3784 | ||
3785 | err = ufshcd_setup_clocks(hba, true); | |
3786 | if (err) | |
3787 | goto out_disable_hba_vreg; | |
3788 | ||
c6e79dac SRT |
3789 | err = ufshcd_init_vreg(hba); |
3790 | if (err) | |
3791 | goto out_disable_clks; | |
3792 | ||
3793 | err = ufshcd_setup_vreg(hba, true); | |
3794 | if (err) | |
3795 | goto out_disable_clks; | |
3796 | ||
aa497613 SRT |
3797 | err = ufshcd_variant_hba_init(hba); |
3798 | if (err) | |
3799 | goto out_disable_vreg; | |
3800 | ||
1d337ec2 | 3801 | hba->is_powered = true; |
aa497613 SRT |
3802 | goto out; |
3803 | ||
3804 | out_disable_vreg: | |
3805 | ufshcd_setup_vreg(hba, false); | |
c6e79dac SRT |
3806 | out_disable_clks: |
3807 | ufshcd_setup_clocks(hba, false); | |
6a771a65 RS |
3808 | out_disable_hba_vreg: |
3809 | ufshcd_setup_hba_vreg(hba, false); | |
aa497613 SRT |
3810 | out: |
3811 | return err; | |
3812 | } | |
3813 | ||
3814 | static void ufshcd_hba_exit(struct ufs_hba *hba) | |
3815 | { | |
1d337ec2 SRT |
3816 | if (hba->is_powered) { |
3817 | ufshcd_variant_hba_exit(hba); | |
3818 | ufshcd_setup_vreg(hba, false); | |
3819 | ufshcd_setup_clocks(hba, false); | |
3820 | ufshcd_setup_hba_vreg(hba, false); | |
3821 | hba->is_powered = false; | |
3822 | } | |
aa497613 SRT |
3823 | } |
3824 | ||
7a3e97b0 SY |
3825 | /** |
3826 | * ufshcd_suspend - suspend power management function | |
3b1d0580 | 3827 | * @hba: per adapter instance |
7a3e97b0 SY |
3828 | * @state: power state |
3829 | * | |
3830 | * Returns -ENOSYS | |
3831 | */ | |
3b1d0580 | 3832 | int ufshcd_suspend(struct ufs_hba *hba, pm_message_t state) |
7a3e97b0 SY |
3833 | { |
3834 | /* | |
3835 | * TODO: | |
3836 | * 1. Block SCSI requests from SCSI midlayer | |
3837 | * 2. Change the internal driver state to non operational | |
3838 | * 3. Set UTRLRSR and UTMRLRSR bits to zero | |
3839 | * 4. Wait until outstanding commands are completed | |
3840 | * 5. Set HCE to zero to send the UFS host controller to reset state | |
3841 | */ | |
3842 | ||
3843 | return -ENOSYS; | |
3844 | } | |
3b1d0580 | 3845 | EXPORT_SYMBOL_GPL(ufshcd_suspend); |
7a3e97b0 SY |
3846 | |
3847 | /** | |
3848 | * ufshcd_resume - resume power management function | |
3b1d0580 | 3849 | * @hba: per adapter instance |
7a3e97b0 SY |
3850 | * |
3851 | * Returns -ENOSYS | |
3852 | */ | |
3b1d0580 | 3853 | int ufshcd_resume(struct ufs_hba *hba) |
7a3e97b0 SY |
3854 | { |
3855 | /* | |
3856 | * TODO: | |
3857 | * 1. Set HCE to 1, to start the UFS host controller | |
3858 | * initialization process | |
3859 | * 2. Set UTRLRSR and UTMRLRSR bits to 1 | |
3860 | * 3. Change the internal driver state to operational | |
3861 | * 4. Unblock SCSI requests from SCSI midlayer | |
3862 | */ | |
3863 | ||
3864 | return -ENOSYS; | |
3865 | } | |
3b1d0580 VH |
3866 | EXPORT_SYMBOL_GPL(ufshcd_resume); |
3867 | ||
66ec6d59 SRT |
3868 | int ufshcd_runtime_suspend(struct ufs_hba *hba) |
3869 | { | |
3870 | if (!hba) | |
3871 | return 0; | |
3872 | ||
3873 | /* | |
3874 | * The device is idle with no requests in the queue, | |
3875 | * allow background operations. | |
3876 | */ | |
3877 | return ufshcd_enable_auto_bkops(hba); | |
3878 | } | |
3879 | EXPORT_SYMBOL(ufshcd_runtime_suspend); | |
3880 | ||
3881 | int ufshcd_runtime_resume(struct ufs_hba *hba) | |
3882 | { | |
3883 | if (!hba) | |
3884 | return 0; | |
3885 | ||
3886 | return ufshcd_disable_auto_bkops(hba); | |
3887 | } | |
3888 | EXPORT_SYMBOL(ufshcd_runtime_resume); | |
3889 | ||
3890 | int ufshcd_runtime_idle(struct ufs_hba *hba) | |
3891 | { | |
3892 | return 0; | |
3893 | } | |
3894 | EXPORT_SYMBOL(ufshcd_runtime_idle); | |
3895 | ||
7a3e97b0 | 3896 | /** |
3b1d0580 | 3897 | * ufshcd_remove - de-allocate SCSI host and host memory space |
7a3e97b0 | 3898 | * data structure memory |
3b1d0580 | 3899 | * @hba - per adapter instance |
7a3e97b0 | 3900 | */ |
3b1d0580 | 3901 | void ufshcd_remove(struct ufs_hba *hba) |
7a3e97b0 | 3902 | { |
cfdf9c91 | 3903 | scsi_remove_host(hba->host); |
7a3e97b0 | 3904 | /* disable interrupts */ |
2fbd009b | 3905 | ufshcd_disable_intr(hba, hba->intr_mask); |
7a3e97b0 | 3906 | ufshcd_hba_stop(hba); |
7a3e97b0 | 3907 | |
7a3e97b0 | 3908 | scsi_host_put(hba->host); |
5c0c28a8 | 3909 | |
aa497613 | 3910 | ufshcd_hba_exit(hba); |
3b1d0580 VH |
3911 | } |
3912 | EXPORT_SYMBOL_GPL(ufshcd_remove); | |
3913 | ||
ca3d7bf9 AM |
3914 | /** |
3915 | * ufshcd_set_dma_mask - Set dma mask based on the controller | |
3916 | * addressing capability | |
3917 | * @hba: per adapter instance | |
3918 | * | |
3919 | * Returns 0 for success, non-zero for failure | |
3920 | */ | |
3921 | static int ufshcd_set_dma_mask(struct ufs_hba *hba) | |
3922 | { | |
3923 | if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { | |
3924 | if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) | |
3925 | return 0; | |
3926 | } | |
3927 | return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); | |
3928 | } | |
3929 | ||
7a3e97b0 | 3930 | /** |
5c0c28a8 | 3931 | * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) |
3b1d0580 VH |
3932 | * @dev: pointer to device handle |
3933 | * @hba_handle: driver private handle | |
7a3e97b0 SY |
3934 | * Returns 0 on success, non-zero value on failure |
3935 | */ | |
5c0c28a8 | 3936 | int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) |
7a3e97b0 SY |
3937 | { |
3938 | struct Scsi_Host *host; | |
3939 | struct ufs_hba *hba; | |
5c0c28a8 | 3940 | int err = 0; |
7a3e97b0 | 3941 | |
3b1d0580 VH |
3942 | if (!dev) { |
3943 | dev_err(dev, | |
3944 | "Invalid memory reference for dev is NULL\n"); | |
3945 | err = -ENODEV; | |
7a3e97b0 SY |
3946 | goto out_error; |
3947 | } | |
3948 | ||
7a3e97b0 SY |
3949 | host = scsi_host_alloc(&ufshcd_driver_template, |
3950 | sizeof(struct ufs_hba)); | |
3951 | if (!host) { | |
3b1d0580 | 3952 | dev_err(dev, "scsi_host_alloc failed\n"); |
7a3e97b0 | 3953 | err = -ENOMEM; |
3b1d0580 | 3954 | goto out_error; |
7a3e97b0 SY |
3955 | } |
3956 | hba = shost_priv(host); | |
7a3e97b0 | 3957 | hba->host = host; |
3b1d0580 | 3958 | hba->dev = dev; |
5c0c28a8 SRT |
3959 | *hba_handle = hba; |
3960 | ||
3961 | out_error: | |
3962 | return err; | |
3963 | } | |
3964 | EXPORT_SYMBOL(ufshcd_alloc_host); | |
3965 | ||
3966 | /** | |
3967 | * ufshcd_init - Driver initialization routine | |
3968 | * @hba: per-adapter instance | |
3969 | * @mmio_base: base register address | |
3970 | * @irq: Interrupt line of device | |
3971 | * Returns 0 on success, non-zero value on failure | |
3972 | */ | |
3973 | int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) | |
3974 | { | |
3975 | int err; | |
3976 | struct Scsi_Host *host = hba->host; | |
3977 | struct device *dev = hba->dev; | |
3978 | ||
3979 | if (!mmio_base) { | |
3980 | dev_err(hba->dev, | |
3981 | "Invalid memory reference for mmio_base is NULL\n"); | |
3982 | err = -ENODEV; | |
3983 | goto out_error; | |
3984 | } | |
3985 | ||
3b1d0580 VH |
3986 | hba->mmio_base = mmio_base; |
3987 | hba->irq = irq; | |
7a3e97b0 | 3988 | |
aa497613 | 3989 | err = ufshcd_hba_init(hba); |
5c0c28a8 SRT |
3990 | if (err) |
3991 | goto out_error; | |
3992 | ||
7a3e97b0 SY |
3993 | /* Read capabilities registers */ |
3994 | ufshcd_hba_capabilities(hba); | |
3995 | ||
3996 | /* Get UFS version supported by the controller */ | |
3997 | hba->ufs_version = ufshcd_get_ufs_version(hba); | |
3998 | ||
2fbd009b SJ |
3999 | /* Get Interrupt bit mask per version */ |
4000 | hba->intr_mask = ufshcd_get_intr_mask(hba); | |
4001 | ||
ca3d7bf9 AM |
4002 | err = ufshcd_set_dma_mask(hba); |
4003 | if (err) { | |
4004 | dev_err(hba->dev, "set dma mask failed\n"); | |
4005 | goto out_disable; | |
4006 | } | |
4007 | ||
7a3e97b0 SY |
4008 | /* Allocate memory for host memory space */ |
4009 | err = ufshcd_memory_alloc(hba); | |
4010 | if (err) { | |
3b1d0580 VH |
4011 | dev_err(hba->dev, "Memory allocation failed\n"); |
4012 | goto out_disable; | |
7a3e97b0 SY |
4013 | } |
4014 | ||
4015 | /* Configure LRB */ | |
4016 | ufshcd_host_memory_configure(hba); | |
4017 | ||
4018 | host->can_queue = hba->nutrs; | |
4019 | host->cmd_per_lun = hba->nutrs; | |
4020 | host->max_id = UFSHCD_MAX_ID; | |
4021 | host->max_lun = UFSHCD_MAX_LUNS; | |
4022 | host->max_channel = UFSHCD_MAX_CHANNEL; | |
4023 | host->unique_id = host->host_no; | |
4024 | host->max_cmd_len = MAX_CDB_SIZE; | |
4025 | ||
4026 | /* Initailize wait queue for task management */ | |
e2933132 SRT |
4027 | init_waitqueue_head(&hba->tm_wq); |
4028 | init_waitqueue_head(&hba->tm_tag_wq); | |
7a3e97b0 SY |
4029 | |
4030 | /* Initialize work queues */ | |
e8e7f271 | 4031 | INIT_WORK(&hba->eh_work, ufshcd_err_handler); |
66ec6d59 | 4032 | INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); |
7a3e97b0 | 4033 | |
6ccf44fe SJ |
4034 | /* Initialize UIC command mutex */ |
4035 | mutex_init(&hba->uic_cmd_mutex); | |
4036 | ||
5a0b0cb9 SRT |
4037 | /* Initialize mutex for device management commands */ |
4038 | mutex_init(&hba->dev_cmd.lock); | |
4039 | ||
4040 | /* Initialize device management tag acquire wait queue */ | |
4041 | init_waitqueue_head(&hba->dev_cmd.tag_wq); | |
4042 | ||
7a3e97b0 | 4043 | /* IRQ registration */ |
2953f850 | 4044 | err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); |
7a3e97b0 | 4045 | if (err) { |
3b1d0580 | 4046 | dev_err(hba->dev, "request irq failed\n"); |
2953f850 | 4047 | goto out_disable; |
7a3e97b0 SY |
4048 | } |
4049 | ||
4050 | /* Enable SCSI tag mapping */ | |
4051 | err = scsi_init_shared_tag_map(host, host->can_queue); | |
4052 | if (err) { | |
3b1d0580 | 4053 | dev_err(hba->dev, "init shared queue failed\n"); |
2953f850 | 4054 | goto out_disable; |
7a3e97b0 SY |
4055 | } |
4056 | ||
3b1d0580 | 4057 | err = scsi_add_host(host, hba->dev); |
7a3e97b0 | 4058 | if (err) { |
3b1d0580 | 4059 | dev_err(hba->dev, "scsi_add_host failed\n"); |
2953f850 | 4060 | goto out_disable; |
7a3e97b0 SY |
4061 | } |
4062 | ||
6ccf44fe SJ |
4063 | /* Host controller enable */ |
4064 | err = ufshcd_hba_enable(hba); | |
7a3e97b0 | 4065 | if (err) { |
6ccf44fe | 4066 | dev_err(hba->dev, "Host controller enable failed\n"); |
3b1d0580 | 4067 | goto out_remove_scsi_host; |
7a3e97b0 | 4068 | } |
6ccf44fe | 4069 | |
62694735 SRT |
4070 | /* Hold auto suspend until async scan completes */ |
4071 | pm_runtime_get_sync(dev); | |
4072 | ||
6ccf44fe SJ |
4073 | async_schedule(ufshcd_async_scan, hba); |
4074 | ||
7a3e97b0 SY |
4075 | return 0; |
4076 | ||
3b1d0580 VH |
4077 | out_remove_scsi_host: |
4078 | scsi_remove_host(hba->host); | |
3b1d0580 VH |
4079 | out_disable: |
4080 | scsi_host_put(host); | |
aa497613 | 4081 | ufshcd_hba_exit(hba); |
3b1d0580 VH |
4082 | out_error: |
4083 | return err; | |
4084 | } | |
4085 | EXPORT_SYMBOL_GPL(ufshcd_init); | |
4086 | ||
3b1d0580 VH |
4087 | MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); |
4088 | MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); | |
e0eca63e | 4089 | MODULE_DESCRIPTION("Generic UFS host controller driver Core"); |
7a3e97b0 SY |
4090 | MODULE_LICENSE("GPL"); |
4091 | MODULE_VERSION(UFSHCD_DRIVER_VERSION); |