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[COMMON] scsi: ufs: exynos: update error handling code when probe
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / scsi / ufs / ufshcd.c
CommitLineData
7a3e97b0 1/*
e0eca63e 2 * Universal Flash Storage Host controller driver Core
7a3e97b0
SY		 3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
3b1d0580 5 * Copyright (C) 2011-2013 Samsung India Software Operations
52ac95fe 6 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
7a3e97b0 7 *
3b1d0580
VH		 8 * Authors:
9 * Santosh Yaraganavi <santosh.sy@samsung.com>
10 * Vinayak Holikatti <h.vinayak@samsung.com>
7a3e97b0
SY		 11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
3b1d0580
VH		 16 * See the COPYING file in the top-level directory or visit
17 * <http://www.gnu.org/licenses/gpl-2.0.html>
7a3e97b0
SY		 18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
3b1d0580
VH		 24 * This program is provided "AS IS" and "WITH ALL FAULTS" and
25 * without warranty of any kind. You are solely responsible for
26 * determining the appropriateness of using and distributing
27 * the program and assume all risks associated with your exercise
28 * of rights with respect to the program, including but not limited
29 * to infringement of third party rights, the risks and costs of
30 * program errors, damage to or loss of data, programs or equipment,
31 * and unavailability or interruption of operations. Under no
32 * circumstances will the contributor of this Program be liable for
33 * any damages of any kind arising from your use or distribution of
34 * this program.
5c0c28a8
SRT		 35 *
36 * The Linux Foundation chooses to take subject only to the GPLv2
37 * license terms, and distributes only under these terms.
7a3e97b0
SY		 38 */
39
6ccf44fe 40#include <linux/async.h>
b393aa4d 41#if defined(CONFIG_PM_DEVFREQ)
856b3483 42#include <linux/devfreq.h>
b393aa4d 43#endif
b573d484 44#include <linux/nls.h>
c2e6ab68 45#include <scsi/ufs/ioctl.h>
54b879b7 46#include <linux/of.h>
e0eca63e 47#include "ufshcd.h"
c58ab7aa 48#include "ufs_quirks.h"
53b3d9c3 49#include "unipro.h"
8d65d1bb 50#include "ufs-exynos.h"
51#include "ufs_quirks.h"
7a3e97b0 52
7ff5ab47
SJ		 53#define CREATE_TRACE_POINTS
54#include <trace/events/ufs.h>
55
dcea0bfb
GB		 56#define UFSHCD_REQ_SENSE_SIZE 18
57
2fbd009b
SJ		 58#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
59 UTP_TASK_REQ_COMPL |\
60 UFSHCD_ERROR_MASK)
6ccf44fe
SJ		 61/* UIC command timeout, unit: ms */
62#define UIC_CMD_TIMEOUT 500
2fbd009b 63
5a0b0cb9
SRT		 64/* NOP OUT retries waiting for NOP IN response */
65#define NOP_OUT_RETRIES 10
66/* Timeout after 30 msecs if NOP OUT hangs without response */
67#define NOP_OUT_TIMEOUT 30 /* msecs */
68
68078d5c 69/* Query request retries */
10fe5888 70#define QUERY_REQ_RETRIES 3
68078d5c 71/* Query request timeout */
10fe5888 72#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
68078d5c 73
e2933132
SRT		 74/* Task management command timeout */
75#define TM_CMD_TIMEOUT 100 /* msecs */
76
64238fbd
YG		 77/* maximum number of retries for a general UIC command */
78#define UFS_UIC_COMMAND_RETRIES 3
79
1d337ec2
SRT		 80/* maximum number of link-startup retries */
81#define DME_LINKSTARTUP_RETRIES 3
82
87d0b4a6
YG		 83/* Maximum retries for Hibern8 enter */
84#define UIC_HIBERN8_ENTER_RETRIES 3
85
1d337ec2
SRT		 86/* maximum number of reset retries before giving up */
87#define MAX_HOST_RESET_RETRIES 5
88
68078d5c
DR		 89/* Expose the flag value from utp_upiu_query.value */
90#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
91
7d568652 92/* Interrupt aggregation default timeout, unit: 40us */
623b5fe3 93#define INT_AGGR_DEF_TO 0x01
94
95/* Link Hibernation delay, msecs */
96#define LINK_H8_DELAY 20
97
251f4e5f 98/* UFS link setup retries */
99#define UFS_LINK_SETUP_RETRIES 5
7d568652 100
c2e6ab68 101/* IOCTL opcode for command - ufs set device read only */
102#define UFS_IOCTL_BLKROSET BLKROSET
103
aa497613
SRT		 104#define ufshcd_toggle_vreg(_dev, _vreg, _on) \
105 ({ \
106 int _ret; \
107 if (_on) \
108 _ret = ufshcd_enable_vreg(_dev, _vreg); \
109 else \
110 _ret = ufshcd_disable_vreg(_dev, _vreg); \
111 _ret; \
112 })
113
ce96cf1c 114static int ufs_shutdown_state = 0;
115
66cc820f
DR		 116#define ufshcd_hex_dump(prefix_str, buf, len) \
117print_hex_dump(KERN_ERR, prefix_str, DUMP_PREFIX_OFFSET, 16, 4, buf, len, false)
118
7a3e97b0
SY		 119enum {
120 UFSHCD_MAX_CHANNEL = 0,
121 UFSHCD_MAX_ID = 1,
7a3e97b0
SY		 122 UFSHCD_CMD_PER_LUN = 32,
123 UFSHCD_CAN_QUEUE = 32,
124};
125
126/* UFSHCD states */
127enum {
7a3e97b0
SY		 128 UFSHCD_STATE_RESET,
129 UFSHCD_STATE_ERROR,
3441da7d 130 UFSHCD_STATE_OPERATIONAL,
141f8165 131 UFSHCD_STATE_EH_SCHEDULED,
3441da7d
SRT		 132};
133
134/* UFSHCD error handling flags */
135enum {
136 UFSHCD_EH_IN_PROGRESS = (1 << 0),
7a3e97b0
SY		 137};
138
e8e7f271
SRT		 139/* UFSHCD UIC layer error flags */
140enum {
141 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
9a47ec7c
YG		 142 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
143 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
144 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
145 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
146 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
a60d7ef4 147 UFSHCD_UIC_DL_ERROR = (1 << 6), /* Data link layer error */
e8e7f271
SRT		 148};
149
3441da7d 150#define ufshcd_set_eh_in_progress(h) \
9c490d2d 151 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
3441da7d 152#define ufshcd_eh_in_progress(h) \
9c490d2d 153 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
3441da7d 154#define ufshcd_clear_eh_in_progress(h) \
9c490d2d 155 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
3441da7d 156
57d104c1
SJ		 157#define ufshcd_set_ufs_dev_active(h) \
158 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
159#define ufshcd_set_ufs_dev_sleep(h) \
160 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
161#define ufshcd_set_ufs_dev_poweroff(h) \
162 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
163#define ufshcd_is_ufs_dev_active(h) \
164 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
165#define ufshcd_is_ufs_dev_sleep(h) \
166 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
167#define ufshcd_is_ufs_dev_poweroff(h) \
168 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
169
170static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
171 {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
172 {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
173 {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
174 {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
175 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
176 {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
177};
178
179static inline enum ufs_dev_pwr_mode
180ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
181{
182 return ufs_pm_lvl_states[lvl].dev_state;
183}
184
185static inline enum uic_link_state
186ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
187{
188 return ufs_pm_lvl_states[lvl].link_state;
189}
190
0c8f7586
SJ		 191static inline enum ufs_pm_level
192ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
193 enum uic_link_state link_state)
194{
195 enum ufs_pm_level lvl;
196
197 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
198 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
199 (ufs_pm_lvl_states[lvl].link_state == link_state))
200 return lvl;
201 }
202
203 /* if no match found, return the level 0 */
204 return UFS_PM_LVL_0;
205}
206
56d4a186
SJ		 207static struct ufs_dev_fix ufs_fixups[] = {
208 /* UFS cards deviations table */
209 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
210 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
211 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
212 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
213 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS),
214 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
215 UFS_DEVICE_NO_FASTAUTO),
216 UFS_FIX(UFS_VENDOR_SAMSUNG, UFS_ANY_MODEL,
217 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE),
218 UFS_FIX(UFS_VENDOR_TOSHIBA, UFS_ANY_MODEL,
219 UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM),
220 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9C8KBADG",
221 UFS_DEVICE_QUIRK_PA_TACTIVATE),
222 UFS_FIX(UFS_VENDOR_TOSHIBA, "THGLF2G9D8KBADG",
223 UFS_DEVICE_QUIRK_PA_TACTIVATE),
224 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL, UFS_DEVICE_NO_VCCQ),
225 UFS_FIX(UFS_VENDOR_SKHYNIX, UFS_ANY_MODEL,
226 UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME),
227
228 END_FIX
229};
230
3441da7d
SRT		 231static void ufshcd_tmc_handler(struct ufs_hba *hba);
232static void ufshcd_async_scan(void *data, async_cookie_t cookie);
e8e7f271 233static int ufshcd_reset_and_restore(struct ufs_hba *hba);
e7d38257 234static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
e8e7f271 235static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
1d337ec2
SRT		 236static void ufshcd_hba_exit(struct ufs_hba *hba);
237static int ufshcd_probe_hba(struct ufs_hba *hba);
1ab27c9c
ST		 238static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
239 bool skip_ref_clk);
240static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
60f01870 241static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused);
1ab27c9c
ST		 242static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
243static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
0f7f11ff 244static int ufshcd_link_hibern8_ctrl(struct ufs_hba *hba, bool en);
cad2e03d 245static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
57d104c1 246static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
fcb0c4b0
ST		 247static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
248static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
401f1e44 249static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
fcb0c4b0 250static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
57d104c1 251static irqreturn_t ufshcd_intr(int irq, void *__hba);
874237f7
YG		 252static int ufshcd_change_power_mode(struct ufs_hba *hba,
253 struct ufs_pa_layer_attr *pwr_mode);
14497328
YG		 254static inline bool ufshcd_valid_tag(struct ufs_hba *hba, int tag)
255{
256 return tag >= 0 && tag < hba->nutrs;
257}
57d104c1 258
9632ac5f 259static ssize_t ufshcd_monitor_show(struct device *dev,
260 struct device_attribute *attr, char *buf)
261{
262 struct ufs_hba *hba = dev_get_drvdata(dev);
263
264 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->monitor.flag);
265}
266
267static ssize_t ufshcd_monitor_store(struct device *dev,
268 struct device_attribute *attr, const char *buf, size_t count)
269{
270 struct ufs_hba *hba = dev_get_drvdata(dev);
271 unsigned long value;
272
273 if (kstrtoul(buf, 0, &value))
274 return -EINVAL;
275
276 hba->monitor.flag = value;
277 return count;
278}
279
280static void ufshcd_init_monitor(struct ufs_hba *hba)
281{
282 hba->monitor.attrs.show = ufshcd_monitor_show;
283 hba->monitor.attrs.store = ufshcd_monitor_store;
284 sysfs_attr_init(&hba->monitor.attrs.attr);
285 hba->monitor.attrs.attr.name = "monitor";
286 hba->monitor.attrs.attr.mode = S_IRUGO | S_IWUSR;
287 if (device_create_file(hba->dev, &hba->monitor.attrs))
288 dev_err(hba->dev, "Failed to create sysfs for monitor\n");
289}
290
291
57d104c1
SJ		 292static inline int ufshcd_enable_irq(struct ufs_hba *hba)
293{
294 int ret = 0;
295
296 if (!hba->is_irq_enabled) {
297 ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
298 hba);
299 if (ret)
300 dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
301 __func__, ret);
302 hba->is_irq_enabled = true;
303 }
304
305 return ret;
306}
307
308static inline void ufshcd_disable_irq(struct ufs_hba *hba)
309{
310 if (hba->is_irq_enabled) {
311 free_irq(hba->irq, hba);
312 hba->is_irq_enabled = false;
313 }
314}
3441da7d 315
b573d484
YG		 316/* replace non-printable or non-ASCII characters with spaces */
317static inline void ufshcd_remove_non_printable(char *val)
318{
319 if (!val)
320 return;
321
322 if (*val < 0x20 || *val > 0x7e)
323 *val = ' ';
324}
325
1a07f2d9
LS		 326static void ufshcd_add_command_trace(struct ufs_hba *hba,
327 unsigned int tag, const char *str)
328{
329 sector_t lba = -1;
330 u8 opcode = 0;
331 u32 intr, doorbell;
332 struct ufshcd_lrb *lrbp;
333 int transfer_len = -1;
334
335 if (!trace_ufshcd_command_enabled())
336 return;
337
338 lrbp = &hba->lrb[tag];
339
340 if (lrbp->cmd) { /* data phase exists */
341 opcode = (u8)(*lrbp->cmd->cmnd);
342 if ((opcode == READ_10) || (opcode == WRITE_10)) {
343 /*
344 * Currently we only fully trace read(10) and write(10)
345 * commands
346 */
347 if (lrbp->cmd->request && lrbp->cmd->request->bio)
348 lba =
349 lrbp->cmd->request->bio->bi_iter.bi_sector;
350 transfer_len = be32_to_cpu(
351 lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
352 }
353 }
354
355 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
356 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
357 trace_ufshcd_command(dev_name(hba->dev), str, tag,
358 doorbell, transfer_len, intr, lba, opcode);
359}
360
ff8e20c6
DR		 361static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
362{
363 struct ufs_clk_info *clki;
364 struct list_head *head = &hba->clk_list_head;
365
566ec9ad 366 if (list_empty(head))
ff8e20c6
DR		 367 return;
368
369 list_for_each_entry(clki, head, list) {
370 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
371 clki->max_freq)
372 dev_err(hba->dev, "clk: %s, rate: %u\n",
373 clki->name, clki->curr_freq);
374 }
375}
376
377static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
378 struct ufs_uic_err_reg_hist *err_hist, char *err_name)
379{
380 int i;
381
382 for (i = 0; i < UIC_ERR_REG_HIST_LENGTH; i++) {
383 int p = (i + err_hist->pos - 1) % UIC_ERR_REG_HIST_LENGTH;
384
385 if (err_hist->reg[p] == 0)
386 continue;
387 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, i,
388 err_hist->reg[p], ktime_to_us(err_hist->tstamp[p]));
389 }
390}
391
66cc820f
DR		 392static void ufshcd_print_host_regs(struct ufs_hba *hba)
393{
394 /*
395 * hex_dump reads its data without the readl macro. This might
396 * cause inconsistency issues on some platform, as the printed
397 * values may be from cache and not the most recent value.
398 * To know whether you are looking at an un-cached version verify
399 * that IORESOURCE_MEM flag is on when xxx_get_resource() is invoked
400 * during platform/pci probe function.
401 */
402 ufshcd_hex_dump("host regs: ", hba->mmio_base, UFSHCI_REG_SPACE_SIZE);
403 dev_err(hba->dev, "hba->ufs_version = 0x%x, hba->capabilities = 0x%x\n",
404 hba->ufs_version, hba->capabilities);
405 dev_err(hba->dev,
406 "hba->outstanding_reqs = 0x%x, hba->outstanding_tasks = 0x%x\n",
407 (u32)hba->outstanding_reqs, (u32)hba->outstanding_tasks);
ff8e20c6
DR		 408 dev_err(hba->dev,
409 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt = %d\n",
410 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
411 hba->ufs_stats.hibern8_exit_cnt);
412
413 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.pa_err, "pa_err");
414 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dl_err, "dl_err");
415 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.nl_err, "nl_err");
416 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.tl_err, "tl_err");
417 ufshcd_print_uic_err_hist(hba, &hba->ufs_stats.dme_err, "dme_err");
418
419 ufshcd_print_clk_freqs(hba);
420
421 if (hba->vops && hba->vops->dbg_register_dump)
422 hba->vops->dbg_register_dump(hba);
66cc820f
DR		 423}
424
425static
426void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
427{
428 struct ufshcd_lrb *lrbp;
7fabb77b 429 int prdt_length;
66cc820f
DR		 430 int tag;
431
432 for_each_set_bit(tag, &bitmap, hba->nutrs) {
433 lrbp = &hba->lrb[tag];
434
ff8e20c6
DR		 435 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
436 tag, ktime_to_us(lrbp->issue_time_stamp));
437 dev_err(hba->dev,
438 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
439 tag, (u64)lrbp->utrd_dma_addr);
440
66cc820f
DR		 441 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
442 sizeof(struct utp_transfer_req_desc));
ff8e20c6
DR		 443 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
444 (u64)lrbp->ucd_req_dma_addr);
66cc820f
DR		 445 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
446 sizeof(struct utp_upiu_req));
ff8e20c6
DR		 447 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
448 (u64)lrbp->ucd_rsp_dma_addr);
66cc820f
DR		 449 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
450 sizeof(struct utp_upiu_rsp));
66cc820f 451
7fabb77b
GB		 452 prdt_length = le16_to_cpu(
453 lrbp->utr_descriptor_ptr->prd_table_length);
454 dev_err(hba->dev,
455 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
456 tag, prdt_length,
457 (u64)lrbp->ucd_prdt_dma_addr);
458
459 if (pr_prdt)
66cc820f 460 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
7fabb77b 461 sizeof(struct ufshcd_sg_entry) * prdt_length);
66cc820f
DR		 462 }
463}
464
465static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
466{
467 struct utp_task_req_desc *tmrdp;
468 int tag;
469
470 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
471 tmrdp = &hba->utmrdl_base_addr[tag];
472 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
473 ufshcd_hex_dump("TM TRD: ", &tmrdp->header,
474 sizeof(struct request_desc_header));
475 dev_err(hba->dev, "TM[%d] - Task Management Request UPIU\n",
476 tag);
477 ufshcd_hex_dump("TM REQ: ", tmrdp->task_req_upiu,
478 sizeof(struct utp_upiu_req));
479 dev_err(hba->dev, "TM[%d] - Task Management Response UPIU\n",
480 tag);
481 ufshcd_hex_dump("TM RSP: ", tmrdp->task_rsp_upiu,
482 sizeof(struct utp_task_req_desc));
483 }
484}
485
6ba65588
GB		 486static void ufshcd_print_host_state(struct ufs_hba *hba)
487{
488 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
489 dev_err(hba->dev, "lrb in use=0x%lx, outstanding reqs=0x%lx tasks=0x%lx\n",
e002e651 490 hba->lrb_in_use, hba->outstanding_reqs, hba->outstanding_tasks);
6ba65588
GB		 491 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
492 hba->saved_err, hba->saved_uic_err);
493 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
494 hba->curr_dev_pwr_mode, hba->uic_link_state);
495 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
496 hba->pm_op_in_progress, hba->is_sys_suspended);
497 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
498 hba->auto_bkops_enabled, hba->host->host_self_blocked);
499 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
500 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
501 hba->eh_flags, hba->req_abort_count);
502 dev_err(hba->dev, "Host capabilities=0x%x, caps=0x%x\n",
503 hba->capabilities, hba->caps);
504 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
505 hba->dev_quirks);
506}
507
ff8e20c6
DR		 508/**
509 * ufshcd_print_pwr_info - print power params as saved in hba
510 * power info
511 * @hba: per-adapter instance
512 */
513static void ufshcd_print_pwr_info(struct ufs_hba *hba)
514{
515 static const char * const names[] = {
516 "INVALID MODE",
517 "FAST MODE",
518 "SLOW_MODE",
519 "INVALID MODE",
520 "FASTAUTO_MODE",
521 "SLOWAUTO_MODE",
522 "INVALID MODE",
523 };
524
525 dev_err(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
526 __func__,
527 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
528 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
529 names[hba->pwr_info.pwr_rx],
530 names[hba->pwr_info.pwr_tx],
531 hba->pwr_info.hs_rate);
532}
533
5a0b0cb9
SRT		 534/*
535 * ufshcd_wait_for_register - wait for register value to change
536 * @hba - per-adapter interface
537 * @reg - mmio register offset
538 * @mask - mask to apply to read register value
539 * @val - wait condition
540 * @interval_us - polling interval in microsecs
541 * @timeout_ms - timeout in millisecs
596585a2 542 * @can_sleep - perform sleep or just spin
5a0b0cb9
SRT		 543 *
544 * Returns -ETIMEDOUT on error, zero on success
545 */
596585a2
YG		 546int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
547 u32 val, unsigned long interval_us,
548 unsigned long timeout_ms, bool can_sleep)
5a0b0cb9
SRT		 549{
550 int err = 0;
551 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
552
553 /* ignore bits that we don't intend to wait on */
554 val = val & mask;
555
556 while ((ufshcd_readl(hba, reg) & mask) != val) {
596585a2
YG		 557 if (can_sleep)
558 usleep_range(interval_us, interval_us + 50);
559 else
560 udelay(interval_us);
5a0b0cb9
SRT		 561 if (time_after(jiffies, timeout)) {
562 if ((ufshcd_readl(hba, reg) & mask) != val)
563 err = -ETIMEDOUT;
564 break;
565 }
566 }
567
568 return err;
569}
570
2fbd009b
SJ		 571/**
572 * ufshcd_get_intr_mask - Get the interrupt bit mask
573 * @hba - Pointer to adapter instance
574 *
575 * Returns interrupt bit mask per version
576 */
577static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
578{
c01848c6
YG		 579 u32 intr_mask = 0;
580
581 switch (hba->ufs_version) {
582 case UFSHCI_VERSION_10:
583 intr_mask = INTERRUPT_MASK_ALL_VER_10;
584 break;
c01848c6
YG		 585 case UFSHCI_VERSION_11:
586 case UFSHCI_VERSION_20:
587 intr_mask = INTERRUPT_MASK_ALL_VER_11;
588 break;
c01848c6
YG		 589 case UFSHCI_VERSION_21:
590 default:
591 intr_mask = INTERRUPT_MASK_ALL_VER_21;
031d1e0f 592 break;
c01848c6
YG		 593 }
594
595 return intr_mask;
2fbd009b
SJ		 596}
597
7a3e97b0
SY		 598/**
599 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
600 * @hba - Pointer to adapter instance
601 *
602 * Returns UFSHCI version supported by the controller
603 */
604static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
605{
0263bcd0
YG		 606 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
607 return ufshcd_vops_get_ufs_hci_version(hba);
9949e702 608
b873a275 609 return ufshcd_readl(hba, REG_UFS_VERSION);
7a3e97b0
SY		 610}
611
612/**
613 * ufshcd_is_device_present - Check if any device connected to
614 * the host controller
5c0c28a8 615 * @hba: pointer to adapter instance
7a3e97b0 616 *
c9e6010b 617 * Returns true if device present, false if no device detected
7a3e97b0 618 */
c9e6010b 619static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
7a3e97b0 620{
5c0c28a8 621 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
c9e6010b 622 DEVICE_PRESENT) ? true : false;
7a3e97b0
SY		 623}
624
625/**
626 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
627 * @lrb: pointer to local command reference block
628 *
629 * This function is used to get the OCS field from UTRD
630 * Returns the OCS field in the UTRD
631 */
632static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
633{
e8c8e82a 634 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 635}
636
637/**
638 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
639 * @task_req_descp: pointer to utp_task_req_desc structure
640 *
641 * This function is used to get the OCS field from UTMRD
642 * Returns the OCS field in the UTMRD
643 */
644static inline int
645ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
646{
e8c8e82a 647 return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
7a3e97b0
SY		 648}
649
650/**
651 * ufshcd_get_tm_free_slot - get a free slot for task management request
652 * @hba: per adapter instance
e2933132 653 * @free_slot: pointer to variable with available slot value
7a3e97b0 654 *
e2933132
SRT		 655 * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
656 * Returns 0 if free slot is not available, else return 1 with tag value
657 * in @free_slot.
7a3e97b0 658 */
e2933132 659static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
7a3e97b0 660{
e2933132
SRT		 661 int tag;
662 bool ret = false;
663
664 if (!free_slot)
665 goto out;
666
667 do {
668 tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
669 if (tag >= hba->nutmrs)
670 goto out;
671 } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
672
673 *free_slot = tag;
674 ret = true;
675out:
676 return ret;
677}
678
679static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
680{
681 clear_bit_unlock(slot, &hba->tm_slots_in_use);
7a3e97b0
SY		 682}
683
684/**
685 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
686 * @hba: per adapter instance
687 * @pos: position of the bit to be cleared
688 */
689static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
690{
86b7a91c 691 u32 clear;
692
693 if (hba->quirks & UFSHCD_QUIRK_BROKEN_REQ_LIST_CLR)
694 clear = (1 << pos);
695 else
696 clear = ~(1 << pos);
697
698 ufshcd_writel(hba, clear, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
699}
700
701/**
702 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
703 * @hba: per adapter instance
704 * @pos: position of the bit to be cleared
705 */
706static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
707{
708 u32 clear;
709
710 if (hba->quirks & UFSHCD_QUIRK_BROKEN_REQ_LIST_CLR)
711 clear = (1 << pos);
712 else
713 clear = ~(1 << pos);
714
715 ufshcd_writel(hba, clear, REG_UTP_TASK_REQ_LIST_CLEAR);
7a3e97b0
SY		 716}
717
a48353f6
YG		 718/**
719 * ufshcd_outstanding_req_clear - Clear a bit in outstanding request field
720 * @hba: per adapter instance
721 * @tag: position of the bit to be cleared
722 */
723static inline void ufshcd_outstanding_req_clear(struct ufs_hba *hba, int tag)
724{
725 __clear_bit(tag, &hba->outstanding_reqs);
726}
727
7a3e97b0
SY		 728/**
729 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
730 * @reg: Register value of host controller status
731 *
732 * Returns integer, 0 on Success and positive value if failed
733 */
734static inline int ufshcd_get_lists_status(u32 reg)
735{
6cf16115 736 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
7a3e97b0
SY		 737}
738
739/**
740 * ufshcd_get_uic_cmd_result - Get the UIC command result
741 * @hba: Pointer to adapter instance
742 *
743 * This function gets the result of UIC command completion
744 * Returns 0 on success, non zero value on error
745 */
746static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
747{
b873a275 748 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
7a3e97b0
SY		 749 MASK_UIC_COMMAND_RESULT;
750}
751
12b4fdb4
SJ		 752/**
753 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
754 * @hba: Pointer to adapter instance
755 *
756 * This function gets UIC command argument3
757 * Returns 0 on success, non zero value on error
758 */
759static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
760{
761 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
762}
763
7a3e97b0 764/**
5a0b0cb9 765 * ufshcd_get_req_rsp - returns the TR response transaction type
7a3e97b0 766 * @ucd_rsp_ptr: pointer to response UPIU
7a3e97b0
SY		 767 */
768static inline int
5a0b0cb9 769ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
7a3e97b0 770{
5a0b0cb9 771 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
7a3e97b0
SY		 772}
773
774/**
775 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
776 * @ucd_rsp_ptr: pointer to response UPIU
777 *
778 * This function gets the response status and scsi_status from response UPIU
779 * Returns the response result code.
780 */
781static inline int
782ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
783{
784 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
785}
786
1c2623c5
SJ		 787/*
788 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
789 * from response UPIU
790 * @ucd_rsp_ptr: pointer to response UPIU
791 *
792 * Return the data segment length.
793 */
794static inline unsigned int
795ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
796{
797 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
798 MASK_RSP_UPIU_DATA_SEG_LEN;
799}
800
66ec6d59
SRT		 801/**
802 * ufshcd_is_exception_event - Check if the device raised an exception event
803 * @ucd_rsp_ptr: pointer to response UPIU
804 *
805 * The function checks if the device raised an exception event indicated in
806 * the Device Information field of response UPIU.
807 *
808 * Returns true if exception is raised, false otherwise.
809 */
810static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
811{
812 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
813 MASK_RSP_EXCEPTION_EVENT ? true : false;
814}
815
7a3e97b0 816/**
7d568652 817 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
7a3e97b0 818 * @hba: per adapter instance
7a3e97b0
SY		 819 */
820static inline void
7d568652 821ufshcd_reset_intr_aggr(struct ufs_hba *hba)
7a3e97b0 822{
7d568652
SJ		 823 ufshcd_writel(hba, INT_AGGR_ENABLE |
824 INT_AGGR_COUNTER_AND_TIMER_RESET,
825 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
826}
827
828/**
829 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
830 * @hba: per adapter instance
831 * @cnt: Interrupt aggregation counter threshold
832 * @tmout: Interrupt aggregation timeout value
833 */
834static inline void
835ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
836{
837 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
838 INT_AGGR_COUNTER_THLD_VAL(cnt) |
839 INT_AGGR_TIMEOUT_VAL(tmout),
840 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
7a3e97b0
SY		 841}
842
b852190e
YG		 843/**
844 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
845 * @hba: per adapter instance
846 */
847static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
848{
849 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
850}
851
7a3e97b0
SY		 852/**
853 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
854 * When run-stop registers are set to 1, it indicates the
855 * host controller that it can process the requests
856 * @hba: per adapter instance
857 */
858static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
859{
b873a275
SJ		 860 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
861 REG_UTP_TASK_REQ_LIST_RUN_STOP);
862 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
863 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
7a3e97b0
SY		 864}
865
7a3e97b0
SY		 866/**
867 * ufshcd_hba_start - Start controller initialization sequence
868 * @hba: per adapter instance
869 */
870static inline void ufshcd_hba_start(struct ufs_hba *hba)
871{
b873a275 872 ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
7a3e97b0
SY		 873}
874
875/**
876 * ufshcd_is_hba_active - Get controller state
877 * @hba: per adapter instance
878 *
c9e6010b 879 * Returns false if controller is active, true otherwise
7a3e97b0 880 */
c9e6010b 881static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
7a3e97b0 882{
4a8eec2b
TK		 883 return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
884 ? false : true;
7a3e97b0
SY		 885}
886
09690d5a
SJ		 887static const char *ufschd_uic_link_state_to_string(
888 enum uic_link_state state)
889{
890 switch (state) {
891 case UIC_LINK_OFF_STATE: return "OFF";
892 case UIC_LINK_ACTIVE_STATE: return "ACTIVE";
893 case UIC_LINK_HIBERN8_STATE: return "HIBERN8";
894 default: return "UNKNOWN";
895 }
896}
897
898static const char *ufschd_ufs_dev_pwr_mode_to_string(
899 enum ufs_dev_pwr_mode state)
900{
901 switch (state) {
902 case UFS_ACTIVE_PWR_MODE: return "ACTIVE";
903 case UFS_SLEEP_PWR_MODE: return "SLEEP";
904 case UFS_POWERDOWN_PWR_MODE: return "POWERDOWN";
905 default: return "UNKNOWN";
906 }
907}
908
37113106
YG		 909u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
910{
911 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
912 if ((hba->ufs_version == UFSHCI_VERSION_10) ||
913 (hba->ufs_version == UFSHCI_VERSION_11))
914 return UFS_UNIPRO_VER_1_41;
915 else
916 return UFS_UNIPRO_VER_1_6;
917}
918EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
919
920static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
921{
922 /*
923 * If both host and device support UniPro ver1.6 or later, PA layer
924 * parameters tuning happens during link startup itself.
925 *
926 * We can manually tune PA layer parameters if either host or device
927 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
928 * logic simple, we will only do manual tuning if local unipro version
929 * doesn't support ver1.6 or later.
930 */
931 if (ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6)
932 return true;
933 else
934 return false;
935}
936
b393aa4d 937#if defined(CONFIG_PM_DEVFREQ)
a3cd5ec5
SJ		 938static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
939{
940 int ret = 0;
941 struct ufs_clk_info *clki;
942 struct list_head *head = &hba->clk_list_head;
943 ktime_t start = ktime_get();
944 bool clk_state_changed = false;
945
566ec9ad 946 if (list_empty(head))
a3cd5ec5
SJ		 947 goto out;
948
949 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
950 if (ret)
951 return ret;
952
953 list_for_each_entry(clki, head, list) {
954 if (!IS_ERR_OR_NULL(clki->clk)) {
955 if (scale_up && clki->max_freq) {
956 if (clki->curr_freq == clki->max_freq)
957 continue;
958
959 clk_state_changed = true;
960 ret = clk_set_rate(clki->clk, clki->max_freq);
961 if (ret) {
962 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
963 __func__, clki->name,
964 clki->max_freq, ret);
965 break;
966 }
967 trace_ufshcd_clk_scaling(dev_name(hba->dev),
968 "scaled up", clki->name,
969 clki->curr_freq,
970 clki->max_freq);
971
972 clki->curr_freq = clki->max_freq;
973
974 } else if (!scale_up && clki->min_freq) {
975 if (clki->curr_freq == clki->min_freq)
976 continue;
977
978 clk_state_changed = true;
979 ret = clk_set_rate(clki->clk, clki->min_freq);
980 if (ret) {
981 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
982 __func__, clki->name,
983 clki->min_freq, ret);
984 break;
985 }
986 trace_ufshcd_clk_scaling(dev_name(hba->dev),
987 "scaled down", clki->name,
988 clki->curr_freq,
989 clki->min_freq);
990 clki->curr_freq = clki->min_freq;
991 }
992 }
993 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
994 clki->name, clk_get_rate(clki->clk));
995 }
996
997 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
998
999out:
1000 if (clk_state_changed)
1001 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1002 (scale_up ? "up" : "down"),
1003 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1004 return ret;
1005}
1006
1007/**
1008 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1009 * @hba: per adapter instance
1010 * @scale_up: True if scaling up and false if scaling down
1011 *
1012 * Returns true if scaling is required, false otherwise.
1013 */
1014static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1015 bool scale_up)
1016{
1017 struct ufs_clk_info *clki;
1018 struct list_head *head = &hba->clk_list_head;
1019
566ec9ad 1020 if (list_empty(head))
a3cd5ec5
SJ		 1021 return false;
1022
1023 list_for_each_entry(clki, head, list) {
1024 if (!IS_ERR_OR_NULL(clki->clk)) {
1025 if (scale_up && clki->max_freq) {
1026 if (clki->curr_freq == clki->max_freq)
1027 continue;
1028 return true;
1029 } else if (!scale_up && clki->min_freq) {
1030 if (clki->curr_freq == clki->min_freq)
1031 continue;
1032 return true;
1033 }
1034 }
1035 }
1036
1037 return false;
1038}
1039
1040static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1041 u64 wait_timeout_us)
1042{
1043 unsigned long flags;
1044 int ret = 0;
1045 u32 tm_doorbell;
1046 u32 tr_doorbell;
1047 bool timeout = false, do_last_check = false;
1048 ktime_t start;
1049
1050 ufshcd_hold(hba, false);
1051 spin_lock_irqsave(hba->host->host_lock, flags);
1052 /*
1053 * Wait for all the outstanding tasks/transfer requests.
1054 * Verify by checking the doorbell registers are clear.
1055 */
1056 start = ktime_get();
1057 do {
1058 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1059 ret = -EBUSY;
1060 goto out;
1061 }
1062
1063 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1064 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
1065 if (!tm_doorbell && !tr_doorbell) {
1066 timeout = false;
1067 break;
1068 } else if (do_last_check) {
1069 break;
1070 }
1071
1072 spin_unlock_irqrestore(hba->host->host_lock, flags);
1073 schedule();
1074 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1075 wait_timeout_us) {
1076 timeout = true;
1077 /*
1078 * We might have scheduled out for long time so make
1079 * sure to check if doorbells are cleared by this time
1080 * or not.
1081 */
1082 do_last_check = true;
1083 }
1084 spin_lock_irqsave(hba->host->host_lock, flags);
1085 } while (tm_doorbell || tr_doorbell);
1086
1087 if (timeout) {
1088 dev_err(hba->dev,
1089 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1090 __func__, tm_doorbell, tr_doorbell);
1091 ret = -EBUSY;
1092 }
1093out:
1094 spin_unlock_irqrestore(hba->host->host_lock, flags);
1095 ufshcd_release(hba);
1096 return ret;
1097}
1098
1099/**
1100 * ufshcd_scale_gear - scale up/down UFS gear
1101 * @hba: per adapter instance
1102 * @scale_up: True for scaling up gear and false for scaling down
1103 *
1104 * Returns 0 for success,
1105 * Returns -EBUSY if scaling can't happen at this time
1106 * Returns non-zero for any other errors
1107 */
1108static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1109{
1110 #define UFS_MIN_GEAR_TO_SCALE_DOWN UFS_HS_G1
1111 int ret = 0;
1112 struct ufs_pa_layer_attr new_pwr_info;
1113
1114 if (scale_up) {
1115 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1116 sizeof(struct ufs_pa_layer_attr));
1117 } else {
1118 memcpy(&new_pwr_info, &hba->pwr_info,
1119 sizeof(struct ufs_pa_layer_attr));
1120
1121 if (hba->pwr_info.gear_tx > UFS_MIN_GEAR_TO_SCALE_DOWN
1122 || hba->pwr_info.gear_rx > UFS_MIN_GEAR_TO_SCALE_DOWN) {
1123 /* save the current power mode */
1124 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1125 &hba->pwr_info,
1126 sizeof(struct ufs_pa_layer_attr));
1127
1128 /* scale down gear */
1129 new_pwr_info.gear_tx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1130 new_pwr_info.gear_rx = UFS_MIN_GEAR_TO_SCALE_DOWN;
1131 }
1132 }
1133
1134 /* check if the power mode needs to be changed or not? */
1135 ret = ufshcd_change_power_mode(hba, &new_pwr_info);
1136
1137 if (ret)
1138 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1139 __func__, ret,
1140 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1141 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1142
1143 return ret;
1144}
1145
1146static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1147{
1148 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1149 int ret = 0;
1150 /*
1151 * make sure that there are no outstanding requests when
1152 * clock scaling is in progress
1153 */
1154 scsi_block_requests(hba->host);
1155 down_write(&hba->clk_scaling_lock);
1156 if (ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1157 ret = -EBUSY;
1158 up_write(&hba->clk_scaling_lock);
1159 scsi_unblock_requests(hba->host);
1160 }
1161
1162 return ret;
1163}
1164
1165static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba)
1166{
1167 up_write(&hba->clk_scaling_lock);
1168 scsi_unblock_requests(hba->host);
1169}
1170
1171/**
1172 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1173 * @hba: per adapter instance
1174 * @scale_up: True for scaling up and false for scalin down
1175 *
1176 * Returns 0 for success,
1177 * Returns -EBUSY if scaling can't happen at this time
1178 * Returns non-zero for any other errors
1179 */
1180static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1181{
1182 int ret = 0;
1183
401f1e44
SJ		 1184 /* let's not get into low power until clock scaling is completed */
1185 ufshcd_hold(hba, false);
1186
a3cd5ec5
SJ		 1187 ret = ufshcd_clock_scaling_prepare(hba);
1188 if (ret)
1189 return ret;
1190
1191 /* scale down the gear before scaling down clocks */
1192 if (!scale_up) {
1193 ret = ufshcd_scale_gear(hba, false);
1194 if (ret)
1195 goto out;
1196 }
1197
1198 ret = ufshcd_scale_clks(hba, scale_up);
1199 if (ret) {
1200 if (!scale_up)
1201 ufshcd_scale_gear(hba, true);
1202 goto out;
1203 }
1204
1205 /* scale up the gear after scaling up clocks */
1206 if (scale_up) {
1207 ret = ufshcd_scale_gear(hba, true);
1208 if (ret) {
1209 ufshcd_scale_clks(hba, false);
1210 goto out;
1211 }
1212 }
1213
1214 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1215
1216out:
1217 ufshcd_clock_scaling_unprepare(hba);
401f1e44 1218 ufshcd_release(hba);
a3cd5ec5
SJ		 1219 return ret;
1220}
1221
401f1e44
SJ		 1222static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1223{
1224 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1225 clk_scaling.suspend_work);
1226 unsigned long irq_flags;
1227
1228 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1229 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1230 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1231 return;
1232 }
1233 hba->clk_scaling.is_suspended = true;
1234 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1235
1236 __ufshcd_suspend_clkscaling(hba);
1237}
1238
1239static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1240{
1241 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1242 clk_scaling.resume_work);
1243 unsigned long irq_flags;
1244
1245 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1246 if (!hba->clk_scaling.is_suspended) {
1247 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1248 return;
1249 }
1250 hba->clk_scaling.is_suspended = false;
1251 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1252
1253 devfreq_resume_device(hba->devfreq);
1254}
1255
a3cd5ec5
SJ		 1256static int ufshcd_devfreq_target(struct device *dev,
1257 unsigned long *freq, u32 flags)
1258{
1259 int ret = 0;
1260 struct ufs_hba *hba = dev_get_drvdata(dev);
1261 ktime_t start;
401f1e44 1262 bool scale_up, sched_clk_scaling_suspend_work = false;
a3cd5ec5
SJ		 1263 unsigned long irq_flags;
1264
1265 if (!ufshcd_is_clkscaling_supported(hba))
1266 return -EINVAL;
1267
1268 if ((*freq > 0) && (*freq < UINT_MAX)) {
1269 dev_err(hba->dev, "%s: invalid freq = %lu\n", __func__, *freq);
1270 return -EINVAL;
1271 }
1272
a3cd5ec5
SJ		 1273 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1274 if (ufshcd_eh_in_progress(hba)) {
1275 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1276 return 0;
1277 }
1278
401f1e44
SJ		 1279 if (!hba->clk_scaling.active_reqs)
1280 sched_clk_scaling_suspend_work = true;
1281
1282 scale_up = (*freq == UINT_MAX) ? true : false;
1283 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1284 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1285 ret = 0;
1286 goto out; /* no state change required */
a3cd5ec5
SJ		 1287 }
1288 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1289
1290 start = ktime_get();
a3cd5ec5
SJ		 1291 ret = ufshcd_devfreq_scale(hba, scale_up);
1292
a3cd5ec5
SJ		 1293 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1294 (scale_up ? "up" : "down"),
1295 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1296
401f1e44
SJ		 1297out:
1298 if (sched_clk_scaling_suspend_work)
1299 queue_work(hba->clk_scaling.workq,
1300 &hba->clk_scaling.suspend_work);
1301
a3cd5ec5
SJ		 1302 return ret;
1303}
1304
1305
1306static int ufshcd_devfreq_get_dev_status(struct device *dev,
1307 struct devfreq_dev_status *stat)
1308{
1309 struct ufs_hba *hba = dev_get_drvdata(dev);
1310 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1311 unsigned long flags;
1312
1313 if (!ufshcd_is_clkscaling_supported(hba))
1314 return -EINVAL;
1315
1316 memset(stat, 0, sizeof(*stat));
1317
1318 spin_lock_irqsave(hba->host->host_lock, flags);
1319 if (!scaling->window_start_t)
1320 goto start_window;
1321
1322 if (scaling->is_busy_started)
1323 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1324 scaling->busy_start_t));
1325
1326 stat->total_time = jiffies_to_usecs((long)jiffies -
1327 (long)scaling->window_start_t);
1328 stat->busy_time = scaling->tot_busy_t;
1329start_window:
1330 scaling->window_start_t = jiffies;
1331 scaling->tot_busy_t = 0;
1332
1333 if (hba->outstanding_reqs) {
1334 scaling->busy_start_t = ktime_get();
1335 scaling->is_busy_started = true;
1336 } else {
1337 scaling->busy_start_t = 0;
1338 scaling->is_busy_started = false;
1339 }
1340 spin_unlock_irqrestore(hba->host->host_lock, flags);
1341 return 0;
1342}
1343
1344static struct devfreq_dev_profile ufs_devfreq_profile = {
1345 .polling_ms = 100,
1346 .target = ufshcd_devfreq_target,
1347 .get_dev_status = ufshcd_devfreq_get_dev_status,
1348};
1349
401f1e44
SJ		 1350static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1351{
1352 unsigned long flags;
1353
1354 devfreq_suspend_device(hba->devfreq);
1355 spin_lock_irqsave(hba->host->host_lock, flags);
1356 hba->clk_scaling.window_start_t = 0;
1357 spin_unlock_irqrestore(hba->host->host_lock, flags);
1358}
a3cd5ec5 1359
a508253d
GB		 1360static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1361{
401f1e44
SJ		 1362 unsigned long flags;
1363 bool suspend = false;
1364
fcb0c4b0
ST		 1365 if (!ufshcd_is_clkscaling_supported(hba))
1366 return;
1367
401f1e44
SJ		 1368 spin_lock_irqsave(hba->host->host_lock, flags);
1369 if (!hba->clk_scaling.is_suspended) {
1370 suspend = true;
1371 hba->clk_scaling.is_suspended = true;
1372 }
1373 spin_unlock_irqrestore(hba->host->host_lock, flags);
1374
1375 if (suspend)
1376 __ufshcd_suspend_clkscaling(hba);
a508253d
GB		 1377}
1378
1379static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1380{
401f1e44
SJ		 1381 unsigned long flags;
1382 bool resume = false;
1383
1384 if (!ufshcd_is_clkscaling_supported(hba))
1385 return;
1386
1387 spin_lock_irqsave(hba->host->host_lock, flags);
1388 if (hba->clk_scaling.is_suspended) {
1389 resume = true;
1390 hba->clk_scaling.is_suspended = false;
1391 }
1392 spin_unlock_irqrestore(hba->host->host_lock, flags);
1393
1394 if (resume)
1395 devfreq_resume_device(hba->devfreq);
fcb0c4b0
ST		 1396}
1397
1398static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1399 struct device_attribute *attr, char *buf)
1400{
1401 struct ufs_hba *hba = dev_get_drvdata(dev);
1402
1403 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_scaling.is_allowed);
1404}
1405
1406static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1407 struct device_attribute *attr, const char *buf, size_t count)
1408{
1409 struct ufs_hba *hba = dev_get_drvdata(dev);
1410 u32 value;
1411 int err;
1412
1413 if (kstrtou32(buf, 0, &value))
1414 return -EINVAL;
1415
1416 value = !!value;
1417 if (value == hba->clk_scaling.is_allowed)
1418 goto out;
1419
1420 pm_runtime_get_sync(hba->dev);
1421 ufshcd_hold(hba, false);
1422
401f1e44
SJ		 1423 cancel_work_sync(&hba->clk_scaling.suspend_work);
1424 cancel_work_sync(&hba->clk_scaling.resume_work);
1425
1426 hba->clk_scaling.is_allowed = value;
1427
fcb0c4b0
ST		 1428 if (value) {
1429 ufshcd_resume_clkscaling(hba);
1430 } else {
1431 ufshcd_suspend_clkscaling(hba);
a3cd5ec5 1432 err = ufshcd_devfreq_scale(hba, true);
fcb0c4b0
ST		 1433 if (err)
1434 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1435 __func__, err);
1436 }
fcb0c4b0
ST		 1437
1438 ufshcd_release(hba);
1439 pm_runtime_put_sync(hba->dev);
1440out:
1441 return count;
a508253d
GB		 1442}
1443
a3cd5ec5
SJ		 1444static void ufshcd_clkscaling_init_sysfs(struct ufs_hba *hba)
1445{
1446 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1447 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1448 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1449 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1450 hba->clk_scaling.enable_attr.attr.mode = 0644;
1451 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1452 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1453}
b393aa4d 1454#endif
a3cd5ec5 1455
1ab27c9c
ST		 1456static void ufshcd_ungate_work(struct work_struct *work)
1457{
1458 int ret;
1459 unsigned long flags;
1460 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1461 clk_gating.ungate_work);
5801290e 1462 bool gating_allowed = !ufshcd_can_fake_clkgating(hba);
1ab27c9c
ST		 1463
1464 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1465
1466 spin_lock_irqsave(hba->host->host_lock, flags);
5801290e 1467 if (hba->clk_gating.state == CLKS_ON && gating_allowed) {
1ab27c9c
ST		 1468 spin_unlock_irqrestore(hba->host->host_lock, flags);
1469 goto unblock_reqs;
1470 }
1471
1472 spin_unlock_irqrestore(hba->host->host_lock, flags);
5801290e 1473 if (gating_allowed) {
1474 ufshcd_setup_clocks(hba, true);
1475 } else {
66a35665 1476 spin_lock_irqsave(hba->host->host_lock, flags);
5801290e 1477 hba->clk_gating.state = CLKS_ON;
66a35665 1478 spin_unlock_irqrestore(hba->host->host_lock, flags);
5801290e 1479 }
1ab27c9c
ST		 1480
1481 /* Exit from hibern8 */
1482 if (ufshcd_can_hibern8_during_gating(hba)) {
1483 /* Prevent gating in this path */
1484 hba->clk_gating.is_suspended = true;
1485 if (ufshcd_is_link_hibern8(hba)) {
5801290e 1486 ufshcd_set_link_trans_active(hba);
0f7f11ff 1487 ret = ufshcd_link_hibern8_ctrl(hba, false);
5801290e 1488 if (ret) {
1489 ufshcd_set_link_off(hba);
1ab27c9c
ST		 1490 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1491 __func__, ret);
5801290e 1492 } else {
1ab27c9c 1493 ufshcd_set_link_active(hba);
5801290e 1494 }
1ab27c9c
ST		 1495 }
1496 hba->clk_gating.is_suspended = false;
1497 }
1498unblock_reqs:
1499 scsi_unblock_requests(hba->host);
1500}
1501
1502/**
1503 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1504 * Also, exit from hibern8 mode and set the link as active.
1505 * @hba: per adapter instance
1506 * @async: This indicates whether caller should ungate clocks asynchronously.
1507 */
1508int ufshcd_hold(struct ufs_hba *hba, bool async)
1509{
1510 int rc = 0;
1511 unsigned long flags;
1512
1513 if (!ufshcd_is_clkgating_allowed(hba))
1514 goto out;
1ab27c9c
ST		 1515 spin_lock_irqsave(hba->host->host_lock, flags);
1516 hba->clk_gating.active_reqs++;
1517
53c12d0e
YG		 1518 if (ufshcd_eh_in_progress(hba)) {
1519 spin_unlock_irqrestore(hba->host->host_lock, flags);
1520 return 0;
1521 }
1522
856b3483 1523start:
1ab27c9c 1524 switch (hba->clk_gating.state) {
40e137af 1525 case __CLKS_ON:
1526 rc = -EAGAIN;
1527 if (async)
1528 hba->clk_gating.active_reqs--;
1ab27c9c 1529 case CLKS_ON:
f2a785ac
VG		 1530 /*
1531 * Wait for the ungate work to complete if in progress.
1532 * Though the clocks may be in ON state, the link could
1533 * still be in hibner8 state if hibern8 is allowed
1534 * during clock gating.
1535 * Make sure we exit hibern8 state also in addition to
1536 * clocks being ON.
1537 */
1538 if (ufshcd_can_hibern8_during_gating(hba) &&
1539 ufshcd_is_link_hibern8(hba)) {
1540 spin_unlock_irqrestore(hba->host->host_lock, flags);
1541 flush_work(&hba->clk_gating.ungate_work);
1542 spin_lock_irqsave(hba->host->host_lock, flags);
1543 goto start;
1544 }
1ab27c9c
ST		 1545 break;
1546 case REQ_CLKS_OFF:
1547 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1548 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1549 trace_ufshcd_clk_gating(dev_name(hba->dev),
1550 hba->clk_gating.state);
1ab27c9c
ST		 1551 break;
1552 }
1553 /*
9c490d2d 1554 * If we are here, it means gating work is either done or
1ab27c9c
ST		 1555 * currently running. Hence, fall through to cancel gating
1556 * work and to enable clocks.
1557 */
1558 case CLKS_OFF:
1559 scsi_block_requests(hba->host);
1560 hba->clk_gating.state = REQ_CLKS_ON;
7ff5ab47
SJ		 1561 trace_ufshcd_clk_gating(dev_name(hba->dev),
1562 hba->clk_gating.state);
9087ff6a 1563 queue_work(hba->ufshcd_workq, &hba->clk_gating.ungate_work);
1ab27c9c
ST		 1564 /*
1565 * fall through to check if we should wait for this
1566 * work to be done or not.
1567 */
1568 case REQ_CLKS_ON:
1569 if (async) {
1570 rc = -EAGAIN;
1571 hba->clk_gating.active_reqs--;
1572 break;
1573 }
1574
1575 spin_unlock_irqrestore(hba->host->host_lock, flags);
1576 flush_work(&hba->clk_gating.ungate_work);
1577 /* Make sure state is CLKS_ON before returning */
856b3483 1578 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c
ST		 1579 goto start;
1580 default:
1581 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1582 __func__, hba->clk_gating.state);
1583 break;
1584 }
1585 spin_unlock_irqrestore(hba->host->host_lock, flags);
1586out:
1587 return rc;
1588}
6e3fd44d 1589EXPORT_SYMBOL_GPL(ufshcd_hold);
1ab27c9c
ST		 1590
1591static void ufshcd_gate_work(struct work_struct *work)
1592{
1593 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1594 clk_gating.gate_work.work);
5801290e 1595 bool gating_allowed = !ufshcd_can_fake_clkgating(hba);
1ab27c9c
ST		 1596 unsigned long flags;
1597
1598 spin_lock_irqsave(hba->host->host_lock, flags);
3f0c06de
VG		 1599 /*
1600 * In case you are here to cancel this work the gating state
1601 * would be marked as REQ_CLKS_ON. In this case save time by
1602 * skipping the gating work and exit after changing the clock
1603 * state to CLKS_ON.
1604 */
1605 if (hba->clk_gating.is_suspended ||
1606 (hba->clk_gating.state == REQ_CLKS_ON)) {
1ab27c9c 1607 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 1608 trace_ufshcd_clk_gating(dev_name(hba->dev),
1609 hba->clk_gating.state);
1ab27c9c
ST		 1610 goto rel_lock;
1611 }
1612
1613 if (hba->clk_gating.active_reqs
1614 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1615 || hba->lrb_in_use || hba->outstanding_tasks
abebc6eb 1616 || hba->active_uic_cmd || hba->uic_async_done
1617 || scsi_host_in_recovery(hba->host))
1ab27c9c
ST		 1618 goto rel_lock;
1619
1620 spin_unlock_irqrestore(hba->host->host_lock, flags);
1621
1622 /* put the link into hibern8 mode before turning off clocks */
1623 if (ufshcd_can_hibern8_during_gating(hba)) {
5801290e 1624 ufshcd_set_link_trans_hibern8(hba);
0f7f11ff 1625 if (ufshcd_link_hibern8_ctrl(hba, true)) {
66a35665 1626 spin_lock_irqsave(hba->host->host_lock, flags);
1627 hba->clk_gating.state = __CLKS_ON;
1628 spin_unlock_irqrestore(hba->host->host_lock, flags);
1629 hba->clk_gating.is_suspended = true;
1630 ufshcd_reset_and_restore(hba);
40e137af 1631 spin_lock_irqsave(hba->host->host_lock, flags);
1ab27c9c 1632 hba->clk_gating.state = CLKS_ON;
40e137af 1633 spin_unlock_irqrestore(hba->host->host_lock, flags);
66a35665 1634 hba->clk_gating.is_suspended = false;
7ff5ab47
SJ		 1635 trace_ufshcd_clk_gating(dev_name(hba->dev),
1636 hba->clk_gating.state);
1ab27c9c
ST		 1637 goto out;
1638 }
1639 ufshcd_set_link_hibern8(hba);
1640 }
1641
5801290e 1642 if (gating_allowed) {
1643 if (!ufshcd_is_link_active(hba))
1644 ufshcd_setup_clocks(hba, false);
1645 else
1646 /* If link is active, device ref_clk can't be switched off */
1647 __ufshcd_setup_clocks(hba, false, true);
1648 }
1ab27c9c
ST		 1649
1650 /*
1651 * In case you are here to cancel this work the gating state
1652 * would be marked as REQ_CLKS_ON. In this case keep the state
1653 * as REQ_CLKS_ON which would anyway imply that clocks are off
1654 * and a request to turn them on is pending. By doing this way,
1655 * we keep the state machine in tact and this would ultimately
1656 * prevent from doing cancel work multiple times when there are
1657 * new requests arriving before the current cancel work is done.
1658 */
1659 spin_lock_irqsave(hba->host->host_lock, flags);
7ff5ab47 1660 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1ab27c9c 1661 hba->clk_gating.state = CLKS_OFF;
7ff5ab47
SJ		 1662 trace_ufshcd_clk_gating(dev_name(hba->dev),
1663 hba->clk_gating.state);
1664 }
1ab27c9c
ST		 1665rel_lock:
1666 spin_unlock_irqrestore(hba->host->host_lock, flags);
1667out:
1668 return;
1669}
1670
1671/* host lock must be held before calling this variant */
1672static void __ufshcd_release(struct ufs_hba *hba)
1673{
1674 if (!ufshcd_is_clkgating_allowed(hba))
1675 return;
1676
1677 hba->clk_gating.active_reqs--;
1678
1679 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
1680 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1681 || hba->lrb_in_use || hba->outstanding_tasks
53c12d0e 1682 || hba->active_uic_cmd || hba->uic_async_done
abebc6eb 1683 || scsi_host_in_recovery(hba->host)
53c12d0e 1684 || ufshcd_eh_in_progress(hba))
1ab27c9c
ST		 1685 return;
1686
1687 hba->clk_gating.state = REQ_CLKS_OFF;
7ff5ab47 1688 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
9087ff6a 1689 queue_delayed_work(hba->ufshcd_workq, &hba->clk_gating.gate_work,
1ab27c9c
ST		 1690 msecs_to_jiffies(hba->clk_gating.delay_ms));
1691}
1692
1693void ufshcd_release(struct ufs_hba *hba)
1694{
1695 unsigned long flags;
1696
1697 spin_lock_irqsave(hba->host->host_lock, flags);
1698 __ufshcd_release(hba);
1699 spin_unlock_irqrestore(hba->host->host_lock, flags);
1700}
6e3fd44d 1701EXPORT_SYMBOL_GPL(ufshcd_release);
1ab27c9c
ST		 1702
1703static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1704 struct device_attribute *attr, char *buf)
1705{
1706 struct ufs_hba *hba = dev_get_drvdata(dev);
1707
1708 return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
1709}
1710
1711static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1712 struct device_attribute *attr, const char *buf, size_t count)
1713{
1714 struct ufs_hba *hba = dev_get_drvdata(dev);
1715 unsigned long flags, value;
1716
1717 if (kstrtoul(buf, 0, &value))
1718 return -EINVAL;
1719
1720 spin_lock_irqsave(hba->host->host_lock, flags);
1721 hba->clk_gating.delay_ms = value;
1722 spin_unlock_irqrestore(hba->host->host_lock, flags);
1723 return count;
1724}
1725
b427411a
ST		 1726static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1727 struct device_attribute *attr, char *buf)
1728{
1729 struct ufs_hba *hba = dev_get_drvdata(dev);
1730
1731 return snprintf(buf, PAGE_SIZE, "%d\n", hba->clk_gating.is_enabled);
1732}
1733
1734static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1735 struct device_attribute *attr, const char *buf, size_t count)
1736{
1737 struct ufs_hba *hba = dev_get_drvdata(dev);
1738 unsigned long flags;
1739 u32 value;
1740
1741 if (kstrtou32(buf, 0, &value))
1742 return -EINVAL;
1743
1744 value = !!value;
1745 if (value == hba->clk_gating.is_enabled)
1746 goto out;
1747
1748 if (value) {
1749 ufshcd_release(hba);
1750 } else {
1751 spin_lock_irqsave(hba->host->host_lock, flags);
1752 hba->clk_gating.active_reqs++;
1753 spin_unlock_irqrestore(hba->host->host_lock, flags);
1754 }
1755
1756 hba->clk_gating.is_enabled = value;
1757out:
1758 return count;
1759}
1760
9087ff6a 1761static int ufshcd_init_clk_gating(struct ufs_hba *hba)
1ab27c9c 1762{
9087ff6a 1763 int ret = 0;
1764
1ab27c9c 1765 if (!ufshcd_is_clkgating_allowed(hba))
9087ff6a 1766 goto out;
1767
1768 hba->ufshcd_workq = alloc_workqueue("ufshcd_wq", WQ_HIGHPRI, 0);
1769 if (!hba->ufshcd_workq) {
1770 ret = -ENOMEM;
1771 goto out;
1772 }
1ab27c9c 1773
0f7f11ff 1774 hba->clk_gating.delay_ms = LINK_H8_DELAY;
1ab27c9c
ST		 1775 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1776 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1777
b427411a
ST		 1778 hba->clk_gating.is_enabled = true;
1779
1ab27c9c
ST		 1780 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1781 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1782 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1783 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
b427411a 1784 hba->clk_gating.delay_attr.attr.mode = 0644;
1ab27c9c
ST		 1785 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1786 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
b427411a
ST		 1787
1788 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1789 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1790 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1791 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1792 hba->clk_gating.enable_attr.attr.mode = 0644;
1793 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1794 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
9087ff6a 1795
1796out:
1797 return ret;
1ab27c9c
ST		 1798}
1799
1800static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
1801{
1802 if (!ufshcd_is_clkgating_allowed(hba))
1803 return;
9087ff6a 1804 destroy_workqueue(hba->ufshcd_workq);
1ab27c9c 1805 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
b427411a 1806 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1ab27c9c
ST		 1807}
1808
b393aa4d 1809#if defined(CONFIG_PM_DEVFREQ)
856b3483
ST		 1810/* Must be called with host lock acquired */
1811static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
1812{
401f1e44
SJ		 1813 bool queue_resume_work = false;
1814
fcb0c4b0 1815 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1816 return;
1817
401f1e44
SJ		 1818 if (!hba->clk_scaling.active_reqs++)
1819 queue_resume_work = true;
1820
1821 if (!hba->clk_scaling.is_allowed || hba->pm_op_in_progress)
1822 return;
1823
1824 if (queue_resume_work)
1825 queue_work(hba->clk_scaling.workq,
1826 &hba->clk_scaling.resume_work);
1827
1828 if (!hba->clk_scaling.window_start_t) {
1829 hba->clk_scaling.window_start_t = jiffies;
1830 hba->clk_scaling.tot_busy_t = 0;
1831 hba->clk_scaling.is_busy_started = false;
1832 }
1833
856b3483
ST		 1834 if (!hba->clk_scaling.is_busy_started) {
1835 hba->clk_scaling.busy_start_t = ktime_get();
1836 hba->clk_scaling.is_busy_started = true;
1837 }
1838}
1839
1840static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
1841{
1842 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1843
fcb0c4b0 1844 if (!ufshcd_is_clkscaling_supported(hba))
856b3483
ST		 1845 return;
1846
1847 if (!hba->outstanding_reqs && scaling->is_busy_started) {
1848 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
1849 scaling->busy_start_t));
8b0e1953 1850 scaling->busy_start_t = 0;
856b3483
ST		 1851 scaling->is_busy_started = false;
1852 }
1853}
b393aa4d 1854#endif
1855
7a3e97b0
SY		 1856/**
1857 * ufshcd_send_command - Send SCSI or device management commands
1858 * @hba: per adapter instance
1859 * @task_tag: Task tag of the command
1860 */
1861static inline
1862void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
1863{
ff8e20c6 1864 hba->lrb[task_tag].issue_time_stamp = ktime_get();
b393aa4d 1865#if defined(CONFIG_PM_DEVFREQ)
856b3483 1866 ufshcd_clk_scaling_start_busy(hba);
b393aa4d 1867#endif
7a3e97b0 1868 __set_bit(task_tag, &hba->outstanding_reqs);
b873a275 1869 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
ad1a1b9c
GB		 1870 /* Make sure that doorbell is committed immediately */
1871 wmb();
1a07f2d9 1872 ufshcd_add_command_trace(hba, task_tag, "send");
7a3e97b0
SY		 1873}
1874
1875/**
1876 * ufshcd_copy_sense_data - Copy sense data in case of check condition
1877 * @lrb - pointer to local reference block
1878 */
1879static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
1880{
1881 int len;
1c2623c5
SJ		 1882 if (lrbp->sense_buffer &&
1883 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
e3ce73d6
YG		 1884 int len_to_copy;
1885
5a0b0cb9 1886 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
e3ce73d6
YG		 1887 len_to_copy = min_t(int, RESPONSE_UPIU_SENSE_DATA_LENGTH, len);
1888
7a3e97b0 1889 memcpy(lrbp->sense_buffer,
5a0b0cb9 1890 lrbp->ucd_rsp_ptr->sr.sense_data,
dcea0bfb 1891 min_t(int, len_to_copy, UFSHCD_REQ_SENSE_SIZE));
7a3e97b0
SY		 1892 }
1893}
1894
68078d5c
DR		 1895/**
1896 * ufshcd_copy_query_response() - Copy the Query Response and the data
1897 * descriptor
1898 * @hba: per adapter instance
1899 * @lrb - pointer to local reference block
1900 */
1901static
c6d4a831 1902int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
68078d5c
DR		 1903{
1904 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
1905
68078d5c 1906 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
68078d5c 1907
68078d5c
DR		 1908 /* Get the descriptor */
1909 if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
d44a5f98 1910 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
68078d5c 1911 GENERAL_UPIU_REQUEST_SIZE;
c6d4a831
DR		 1912 u16 resp_len;
1913 u16 buf_len;
68078d5c
DR		 1914
1915 /* data segment length */
c6d4a831 1916 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
68078d5c 1917 MASK_QUERY_DATA_SEG_LEN;
ea2aab24
SRT		 1918 buf_len = be16_to_cpu(
1919 hba->dev_cmd.query.request.upiu_req.length);
c6d4a831
DR		 1920 if (likely(buf_len >= resp_len)) {
1921 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
1922 } else {
1923 dev_warn(hba->dev,
1924 "%s: Response size is bigger than buffer",
1925 __func__);
1926 return -EINVAL;
1927 }
68078d5c 1928 }
c6d4a831
DR		 1929
1930 return 0;
68078d5c
DR		 1931}
1932
7a3e97b0
SY		 1933/**
1934 * ufshcd_hba_capabilities - Read controller capabilities
1935 * @hba: per adapter instance
1936 */
1937static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
1938{
b873a275 1939 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
7a3e97b0
SY		 1940
1941 /* nutrs and nutmrs are 0 based values */
1942 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
1943 hba->nutmrs =
1944 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
1945}
1946
1947/**
6ccf44fe
SJ		 1948 * ufshcd_ready_for_uic_cmd - Check if controller is ready
1949 * to accept UIC commands
7a3e97b0 1950 * @hba: per adapter instance
6ccf44fe
SJ		 1951 * Return true on success, else false
1952 */
1953static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
1954{
1955 if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
1956 return true;
1957 else
1958 return false;
1959}
1960
53b3d9c3
SJ		 1961/**
1962 * ufshcd_get_upmcrs - Get the power mode change request status
1963 * @hba: Pointer to adapter instance
1964 *
1965 * This function gets the UPMCRS field of HCS register
1966 * Returns value of UPMCRS field
1967 */
cef1bd92 1968static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 1969{
02527a32 1970 if (hba->quirks & UFSHCD_QUIRK_GET_GENERRCODE_DIRECT) {
cef1bd92 1971 if (cmd->command == UIC_CMD_DME_SET &&
1972 cmd->argument1 == UIC_ARG_MIB(PA_PWRMODE))
02527a32 1973 return ufshcd_vops_get_unipro(hba, 3);
cef1bd92 1974 else if (cmd->command == UIC_CMD_DME_HIBER_ENTER)
1975 return ufshcd_vops_get_unipro(hba, 4);
1976 else if (cmd->command == UIC_CMD_DME_HIBER_EXIT)
1977 return ufshcd_vops_get_unipro(hba, 5);
1978 else
1979 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
02527a32 1980 } else
cef1bd92 1981 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
53b3d9c3
SJ		 1982}
1983
6ccf44fe
SJ		 1984/**
1985 * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
1986 * @hba: per adapter instance
1987 * @uic_cmd: UIC command
1988 *
1989 * Mutex must be held.
7a3e97b0
SY		 1990 */
1991static inline void
6ccf44fe 1992ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
7a3e97b0 1993{
6ccf44fe
SJ		 1994 WARN_ON(hba->active_uic_cmd);
1995
1996 hba->active_uic_cmd = uic_cmd;
1997
7a3e97b0 1998 /* Write Args */
6ccf44fe
SJ		 1999 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2000 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2001 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
7a3e97b0
SY		 2002
2003 /* Write UIC Cmd */
6ccf44fe 2004 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
b873a275 2005 REG_UIC_COMMAND);
7a3e97b0
SY		 2006}
2007
6ccf44fe
SJ		 2008/**
2009 * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
2010 * @hba: per adapter instance
2011 * @uic_command: UIC command
2012 *
2013 * Must be called with mutex held.
2014 * Returns 0 only if success.
2015 */
2016static int
2017ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2018{
2019 int ret;
2020 unsigned long flags;
02527a32 2021 int index;
2022
2023 if (uic_cmd->command == UIC_CMD_DME_LINK_STARTUP)
2024 index = 0;
2025 else if ((uic_cmd->command == UIC_CMD_DME_HIBER_ENTER))
2026 index = 1;
2027 else if ((uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
2028 index = 2;
2029 else
2030 index = -1;
6ccf44fe
SJ		 2031
2032 if (wait_for_completion_timeout(&uic_cmd->done,
02527a32 2033 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2034 if ((hba->quirks & UFSHCD_QUIRK_GET_GENERRCODE_DIRECT) && (index != -1))
2035 ret = ufshcd_vops_get_unipro(hba, index);
2036 else
2037 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2038 } else
6ccf44fe
SJ		 2039 ret = -ETIMEDOUT;
2040
2041 spin_lock_irqsave(hba->host->host_lock, flags);
2042 hba->active_uic_cmd = NULL;
2043 spin_unlock_irqrestore(hba->host->host_lock, flags);
2044
2045 return ret;
2046}
2047
2048/**
2049 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2050 * @hba: per adapter instance
2051 * @uic_cmd: UIC command
d75f7fe4 2052 * @completion: initialize the completion only if this is set to true
6ccf44fe
SJ		 2053 *
2054 * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
57d104c1 2055 * with mutex held and host_lock locked.
6ccf44fe
SJ		 2056 * Returns 0 only if success.
2057 */
2058static int
d75f7fe4
YG		 2059__ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2060 bool completion)
6ccf44fe 2061{
6ccf44fe
SJ		 2062 if (!ufshcd_ready_for_uic_cmd(hba)) {
2063 dev_err(hba->dev,
2064 "Controller not ready to accept UIC commands\n");
2065 return -EIO;
2066 }
2067
d75f7fe4
YG		 2068 if (completion)
2069 init_completion(&uic_cmd->done);
6ccf44fe 2070
6ccf44fe 2071 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
6ccf44fe 2072
57d104c1 2073 return 0;
6ccf44fe
SJ		 2074}
2075
2076/**
2077 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2078 * @hba: per adapter instance
2079 * @uic_cmd: UIC command
2080 *
2081 * Returns 0 only if success.
2082 */
2083static int
2084ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2085{
2086 int ret;
57d104c1 2087 unsigned long flags;
6ccf44fe 2088
1ab27c9c 2089 ufshcd_hold(hba, false);
6ccf44fe 2090 mutex_lock(&hba->uic_cmd_mutex);
cad2e03d
YG		 2091 ufshcd_add_delay_before_dme_cmd(hba);
2092
57d104c1 2093 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 2094 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
57d104c1
SJ		 2095 spin_unlock_irqrestore(hba->host->host_lock, flags);
2096 if (!ret)
2097 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2098
6ccf44fe
SJ		 2099 mutex_unlock(&hba->uic_cmd_mutex);
2100
1ab27c9c 2101 ufshcd_release(hba);
6ccf44fe
SJ		 2102 return ret;
2103}
2104
7a3e97b0
SY		 2105/**
2106 * ufshcd_map_sg - Map scatter-gather list to prdt
2107 * @lrbp - pointer to local reference block
2108 *
2109 * Returns 0 in case of success, non-zero value in case of failure
2110 */
75b1cc4a 2111static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0
SY		 2112{
2113 struct ufshcd_sg_entry *prd_table;
2114 struct scatterlist *sg;
2115 struct scsi_cmnd *cmd;
2116 int sg_segments;
2117 int i;
2118
2119 cmd = lrbp->cmd;
2120 sg_segments = scsi_dma_map(cmd);
2121 if (sg_segments < 0)
2122 return sg_segments;
2123
2124 if (sg_segments) {
75b1cc4a
KK		 2125 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2126 lrbp->utr_descriptor_ptr->prd_table_length =
2127 cpu_to_le16((u16)(sg_segments *
2128 sizeof(struct ufshcd_sg_entry)));
2129 else
2130 lrbp->utr_descriptor_ptr->prd_table_length =
2131 cpu_to_le16((u16) (sg_segments));
7a3e97b0
SY		 2132
2133 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
2134
2135 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2136 prd_table[i].size =
2137 cpu_to_le32(((u32) sg_dma_len(sg))-1);
2138 prd_table[i].base_addr =
2139 cpu_to_le32(lower_32_bits(sg->dma_address));
2140 prd_table[i].upper_addr =
2141 cpu_to_le32(upper_32_bits(sg->dma_address));
52ac95fe 2142 prd_table[i].reserved = 0;
60916a7e 2143 hba->transferred_sector += prd_table[i].size;
2144
7a3e97b0
SY		 2145 }
2146 } else {
2147 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2148 }
2149
2150 return 0;
2151}
2152
2153/**
2fbd009b 2154 * ufshcd_enable_intr - enable interrupts
7a3e97b0 2155 * @hba: per adapter instance
2fbd009b 2156 * @intrs: interrupt bits
7a3e97b0 2157 */
2fbd009b 2158static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
7a3e97b0 2159{
2fbd009b
SJ		 2160 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2161
2162 if (hba->ufs_version == UFSHCI_VERSION_10) {
2163 u32 rw;
2164 rw = set & INTERRUPT_MASK_RW_VER_10;
2165 set = rw | ((set ^ intrs) & intrs);
2166 } else {
2167 set |= intrs;
2168 }
2169
2170 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2171}
2172
2173/**
2174 * ufshcd_disable_intr - disable interrupts
2175 * @hba: per adapter instance
2176 * @intrs: interrupt bits
2177 */
2178static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2179{
2180 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2181
2182 if (hba->ufs_version == UFSHCI_VERSION_10) {
2183 u32 rw;
2184 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2185 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2186 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2187
2188 } else {
2189 set &= ~intrs;
7a3e97b0 2190 }
2fbd009b
SJ		 2191
2192 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
7a3e97b0
SY		 2193}
2194
5a0b0cb9
SRT		 2195/**
2196 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2197 * descriptor according to request
2198 * @lrbp: pointer to local reference block
2199 * @upiu_flags: flags required in the header
2200 * @cmd_dir: requests data direction
2201 */
2202static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
300bb13f 2203 u32 *upiu_flags, enum dma_data_direction cmd_dir)
5a0b0cb9
SRT		 2204{
2205 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2206 u32 data_direction;
2207 u32 dword_0;
2208
2209 if (cmd_dir == DMA_FROM_DEVICE) {
2210 data_direction = UTP_DEVICE_TO_HOST;
2211 *upiu_flags = UPIU_CMD_FLAGS_READ;
2212 } else if (cmd_dir == DMA_TO_DEVICE) {
2213 data_direction = UTP_HOST_TO_DEVICE;
2214 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2215 } else {
2216 data_direction = UTP_NO_DATA_TRANSFER;
2217 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2218 }
2219
2220 dword_0 = data_direction | (lrbp->command_type
2221 << UPIU_COMMAND_TYPE_OFFSET);
2222 if (lrbp->intr_cmd)
2223 dword_0 |= UTP_REQ_DESC_INT_CMD;
2224
2225 /* Transfer request descriptor header fields */
2226 req_desc->header.dword_0 = cpu_to_le32(dword_0);
52ac95fe
YG		 2227 /* dword_1 is reserved, hence it is set to 0 */
2228 req_desc->header.dword_1 = 0;
5a0b0cb9
SRT		 2229 /*
2230 * assigning invalid value for command status. Controller
2231 * updates OCS on command completion, with the command
2232 * status
2233 */
2234 req_desc->header.dword_2 =
2235 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
52ac95fe
YG		 2236 /* dword_3 is reserved, hence it is set to 0 */
2237 req_desc->header.dword_3 = 0;
51047266
YG		 2238
2239 req_desc->prd_table_length = 0;
5a0b0cb9
SRT		 2240}
2241
2242/**
2243 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2244 * for scsi commands
2245 * @lrbp - local reference block pointer
2246 * @upiu_flags - flags
2247 */
2248static
2249void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
2250{
2251 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
52ac95fe 2252 unsigned short cdb_len;
5a0b0cb9
SRT		 2253
2254 /* command descriptor fields */
2255 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2256 UPIU_TRANSACTION_COMMAND, upiu_flags,
2257 lrbp->lun, lrbp->task_tag);
2258 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2259 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2260
2261 /* Total EHS length and Data segment length will be zero */
2262 ucd_req_ptr->header.dword_2 = 0;
2263
2264 ucd_req_ptr->sc.exp_data_transfer_len =
2265 cpu_to_be32(lrbp->cmd->sdb.length);
2266
52ac95fe
YG		 2267 cdb_len = min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE);
2268 memset(ucd_req_ptr->sc.cdb, 0, MAX_CDB_SIZE);
2269 memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd, cdb_len);
2270
2271 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2272}
2273
68078d5c
DR		 2274/**
2275 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2276 * for query requsts
2277 * @hba: UFS hba
2278 * @lrbp: local reference block pointer
2279 * @upiu_flags: flags
2280 */
2281static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2282 struct ufshcd_lrb *lrbp, u32 upiu_flags)
2283{
2284 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2285 struct ufs_query *query = &hba->dev_cmd.query;
e8c8e82a 2286 u16 len = be16_to_cpu(query->request.upiu_req.length);
68078d5c
DR		 2287 u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
2288
2289 /* Query request header */
2290 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2291 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2292 lrbp->lun, lrbp->task_tag);
2293 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2294 0, query->request.query_func, 0, 0);
2295
74cf8b55 2296 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_READ_DESC)
2297 len = 0;
2298
6861285c
ZL		 2299 /* Data segment length only need for WRITE_DESC */
2300 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2301 ucd_req_ptr->header.dword_2 =
2302 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2303 else
2304 ucd_req_ptr->header.dword_2 = 0;
68078d5c
DR		 2305
2306 /* Copy the Query Request buffer as is */
2307 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2308 QUERY_OSF_SIZE);
68078d5c
DR		 2309
2310 /* Copy the Descriptor */
c6d4a831
DR		 2311 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2312 memcpy(descp, query->descriptor, len);
2313
51047266 2314 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
68078d5c
DR		 2315}
2316
5a0b0cb9
SRT		 2317static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2318{
2319 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2320
2321 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2322
2323 /* command descriptor fields */
2324 ucd_req_ptr->header.dword_0 =
2325 UPIU_HEADER_DWORD(
2326 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
51047266
YG		 2327 /* clear rest of the fields of basic header */
2328 ucd_req_ptr->header.dword_1 = 0;
2329 ucd_req_ptr->header.dword_2 = 0;
2330
2331 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
5a0b0cb9
SRT		 2332}
2333
7a3e97b0 2334/**
300bb13f
JP		 2335 * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
2336 * for Device Management Purposes
5a0b0cb9 2337 * @hba - per adapter instance
7a3e97b0
SY		 2338 * @lrb - pointer to local reference block
2339 */
300bb13f 2340static int ufshcd_comp_devman_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
7a3e97b0 2341{
7a3e97b0 2342 u32 upiu_flags;
5a0b0cb9 2343 int ret = 0;
7a3e97b0 2344
300bb13f
JP		 2345 if (hba->ufs_version == UFSHCI_VERSION_20)
2346 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2347 else
2348 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2349
2350 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2351 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2352 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2353 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2354 ufshcd_prepare_utp_nop_upiu(lrbp);
2355 else
2356 ret = -EINVAL;
2357
2358 return ret;
2359}
2360
2361/**
2362 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2363 * for SCSI Purposes
2364 * @hba - per adapter instance
2365 * @lrb - pointer to local reference block
2366 */
2367static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2368{
2369 u32 upiu_flags;
2370 int ret = 0;
2371
2372 if (hba->ufs_version == UFSHCI_VERSION_20)
2373 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2374 else
2375 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2376
2377 if (likely(lrbp->cmd)) {
2378 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2379 lrbp->cmd->sc_data_direction);
2380 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2381 } else {
2382 ret = -EINVAL;
2383 }
5a0b0cb9
SRT		 2384
2385 return ret;
7a3e97b0
SY		 2386}
2387
0ce147d4
SJ		 2388/*
2389 * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
2390 * @scsi_lun: scsi LUN id
2391 *
2392 * Returns UPIU LUN id
2393 */
2394static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
2395{
2396 if (scsi_is_wlun(scsi_lun))
2397 return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
2398 | UFS_UPIU_WLUN_ID;
2399 else
2400 return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
2401}
2402
071b73ac 2403static inline unsigned int ufshcd_get_scsi_lun(struct scsi_cmnd *cmd)
2404{
2405 if (cmd->cmnd[0] == SECURITY_PROTOCOL_IN ||
2406 cmd->cmnd[0] == SECURITY_PROTOCOL_OUT)
2407 return (SCSI_W_LUN_BASE |
2408 (UFS_UPIU_RPMB_WLUN & UFS_UPIU_MAX_UNIT_NUM_ID));
2409 else
2410 return cmd->device->lun;
2411}
2412
2a8fa600
SJ		 2413/**
2414 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2415 * @scsi_lun: UPIU W-LUN id
2416 *
2417 * Returns SCSI W-LUN id
2418 */
2419static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2420{
2421 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2422}
2423
7a3e97b0
SY		 2424/**
2425 * ufshcd_queuecommand - main entry point for SCSI requests
2426 * @cmd: command from SCSI Midlayer
2427 * @done: call back function
2428 *
2429 * Returns 0 for success, non-zero in case of failure
2430 */
2431static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2432{
2433 struct ufshcd_lrb *lrbp;
2434 struct ufs_hba *hba;
2435 unsigned long flags;
2436 int tag;
2437 int err = 0;
2438
2439 hba = shost_priv(host);
2440
2441 tag = cmd->request->tag;
14497328
YG		 2442 if (!ufshcd_valid_tag(hba, tag)) {
2443 dev_err(hba->dev,
2444 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
2445 __func__, tag, cmd, cmd->request);
2446 BUG();
2447 }
7a3e97b0 2448
a3cd5ec5
SJ		 2449 if (!down_read_trylock(&hba->clk_scaling_lock))
2450 return SCSI_MLQUEUE_HOST_BUSY;
ce96cf1c 2451 if ((ufs_shutdown_state == 1) && (cmd->cmnd[0] == START_STOP)) {
2452 scsi_block_requests(hba->host);
2453 cancel_work_sync(&hba->clk_gating.ungate_work);
2454 }
a3cd5ec5 2455
3441da7d
SRT		 2456 spin_lock_irqsave(hba->host->host_lock, flags);
2457 switch (hba->ufshcd_state) {
2458 case UFSHCD_STATE_OPERATIONAL:
2459 break;
141f8165 2460 case UFSHCD_STATE_EH_SCHEDULED:
3441da7d 2461 case UFSHCD_STATE_RESET:
7a3e97b0 2462 err = SCSI_MLQUEUE_HOST_BUSY;
3441da7d
SRT		 2463 goto out_unlock;
2464 case UFSHCD_STATE_ERROR:
2465 set_host_byte(cmd, DID_ERROR);
a782a88e 2466 scsi_dma_map(cmd);
3441da7d
SRT		 2467 cmd->scsi_done(cmd);
2468 goto out_unlock;
2469 default:
2470 dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
2471 __func__, hba->ufshcd_state);
2472 set_host_byte(cmd, DID_BAD_TARGET);
2473 cmd->scsi_done(cmd);
2474 goto out_unlock;
7a3e97b0 2475 }
53c12d0e
YG		 2476
2477 /* if error handling is in progress, don't issue commands */
2478 if (ufshcd_eh_in_progress(hba)) {
2479 set_host_byte(cmd, DID_ERROR);
2480 cmd->scsi_done(cmd);
2481 goto out_unlock;
2482 }
3441da7d 2483 spin_unlock_irqrestore(hba->host->host_lock, flags);
7a3e97b0 2484
7fabb77b
GB		 2485 hba->req_abort_count = 0;
2486
5a0b0cb9
SRT		 2487 /* acquire the tag to make sure device cmds don't use it */
2488 if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
2489 /*
2490 * Dev manage command in progress, requeue the command.
2491 * Requeuing the command helps in cases where the request *may*
2492 * find different tag instead of waiting for dev manage command
2493 * completion.
2494 */
2495 err = SCSI_MLQUEUE_HOST_BUSY;
2496 goto out;
2497 }
2498
1ab27c9c
ST		 2499 err = ufshcd_hold(hba, true);
2500 if (err) {
2501 err = SCSI_MLQUEUE_HOST_BUSY;
2502 clear_bit_unlock(tag, &hba->lrb_in_use);
2503 goto out;
2504 }
2505 WARN_ON(hba->clk_gating.state != CLKS_ON);
2506
7a3e97b0
SY		 2507 lrbp = &hba->lrb[tag];
2508
5a0b0cb9 2509 WARN_ON(lrbp->cmd);
7a3e97b0 2510 lrbp->cmd = cmd;
dcea0bfb 2511 lrbp->sense_bufflen = UFSHCD_REQ_SENSE_SIZE;
7a3e97b0
SY		 2512 lrbp->sense_buffer = cmd->sense_buffer;
2513 lrbp->task_tag = tag;
0ce147d4 2514 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
b852190e 2515 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba) ? true : false;
e0b299e3 2516 lrbp->req_abort_skip = false;
7a3e97b0 2517
300bb13f
JP		 2518 ufshcd_comp_scsi_upiu(hba, lrbp);
2519
75b1cc4a 2520 err = ufshcd_map_sg(hba, lrbp);
5a0b0cb9
SRT		 2521 if (err) {
2522 lrbp->cmd = NULL;
2523 clear_bit_unlock(tag, &hba->lrb_in_use);
7a3e97b0 2524 goto out;
5a0b0cb9 2525 }
ad1a1b9c
GB		 2526 /* Make sure descriptors are ready before ringing the doorbell */
2527 wmb();
7a3e97b0
SY		 2528
2529 /* issue command to the controller */
2530 spin_lock_irqsave(hba->host->host_lock, flags);
03229397 2531 if (hba->vops && hba->vops->set_nexus_t_xfer_req)
2532 hba->vops->set_nexus_t_xfer_req(hba, tag, lrbp->cmd);
2ea8cc4d 2533#ifdef CONFIG_SCSI_UFS_CMD_LOGGING
2534 exynos_ufs_cmd_log_start(hba, cmd);
2535#endif
7a3e97b0 2536 ufshcd_send_command(hba, tag);
9632ac5f 2537
2538 if (hba->monitor.flag & UFSHCD_MONITOR_LEVEL1)
2539 dev_info(hba->dev, "IO issued(%d)\n", tag);
3441da7d 2540out_unlock:
7a3e97b0
SY		 2541 spin_unlock_irqrestore(hba->host->host_lock, flags);
2542out:
a3cd5ec5 2543 up_read(&hba->clk_scaling_lock);
7a3e97b0
SY		 2544 return err;
2545}
2546
5a0b0cb9
SRT		 2547static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2548 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2549{
2550 lrbp->cmd = NULL;
2551 lrbp->sense_bufflen = 0;
2552 lrbp->sense_buffer = NULL;
2553 lrbp->task_tag = tag;
2554 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
5a0b0cb9
SRT		 2555 lrbp->intr_cmd = true; /* No interrupt aggregation */
2556 hba->dev_cmd.type = cmd_type;
2557
300bb13f 2558 return ufshcd_comp_devman_upiu(hba, lrbp);
5a0b0cb9
SRT		 2559}
2560
2561static int
2562ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
2563{
2564 int err = 0;
2565 unsigned long flags;
2566 u32 mask = 1 << tag;
2567
2568 /* clear outstanding transaction before retry */
2569 spin_lock_irqsave(hba->host->host_lock, flags);
2570 ufshcd_utrl_clear(hba, tag);
2571 spin_unlock_irqrestore(hba->host->host_lock, flags);
2572
2573 /*
2574 * wait for for h/w to clear corresponding bit in door-bell.
2575 * max. wait is 1 sec.
2576 */
2577 err = ufshcd_wait_for_register(hba,
2578 REG_UTP_TRANSFER_REQ_DOOR_BELL,
596585a2 2579 mask, ~mask, 1000, 1000, true);
5a0b0cb9
SRT		 2580
2581 return err;
2582}
2583
c6d4a831
DR		 2584static int
2585ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2586{
2587 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2588
2589 /* Get the UPIU response */
2590 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2591 UPIU_RSP_CODE_OFFSET;
2592 return query_res->response;
2593}
2594
5a0b0cb9
SRT		 2595/**
2596 * ufshcd_dev_cmd_completion() - handles device management command responses
2597 * @hba: per adapter instance
2598 * @lrbp: pointer to local reference block
2599 */
2600static int
2601ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2602{
2603 int resp;
2604 int err = 0;
2605
ff8e20c6 2606 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 2607 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2608
2609 switch (resp) {
2610 case UPIU_TRANSACTION_NOP_IN:
2611 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2612 err = -EINVAL;
2613 dev_err(hba->dev, "%s: unexpected response %x\n",
2614 __func__, resp);
2615 }
2616 break;
68078d5c 2617 case UPIU_TRANSACTION_QUERY_RSP:
c6d4a831
DR		 2618 err = ufshcd_check_query_response(hba, lrbp);
2619 if (!err)
2620 err = ufshcd_copy_query_response(hba, lrbp);
68078d5c 2621 break;
5a0b0cb9
SRT		 2622 case UPIU_TRANSACTION_REJECT_UPIU:
2623 /* TODO: handle Reject UPIU Response */
2624 err = -EPERM;
2625 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2626 __func__);
2627 break;
2628 default:
2629 err = -EINVAL;
2630 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2631 __func__, resp);
2632 break;
2633 }
2634
2635 return err;
2636}
2637
2638static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2639 struct ufshcd_lrb *lrbp, int max_timeout)
2640{
2641 int err = 0;
2642 unsigned long time_left;
2643 unsigned long flags;
2644
2645 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2646 msecs_to_jiffies(max_timeout));
2647
ad1a1b9c
GB		 2648 /* Make sure descriptors are ready before ringing the doorbell */
2649 wmb();
5a0b0cb9
SRT		 2650 spin_lock_irqsave(hba->host->host_lock, flags);
2651 hba->dev_cmd.complete = NULL;
2652 if (likely(time_left)) {
2653 err = ufshcd_get_tr_ocs(lrbp);
2654 if (!err)
2655 err = ufshcd_dev_cmd_completion(hba, lrbp);
2656 }
2657 spin_unlock_irqrestore(hba->host->host_lock, flags);
2658
2659 if (!time_left) {
2660 err = -ETIMEDOUT;
a48353f6
YG		 2661 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2662 __func__, lrbp->task_tag);
5a0b0cb9 2663 if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
a48353f6 2664 /* successfully cleared the command, retry if needed */
5a0b0cb9 2665 err = -EAGAIN;
a48353f6
YG		 2666 /*
2667 * in case of an error, after clearing the doorbell,
2668 * we also need to clear the outstanding_request
2669 * field in hba
2670 */
2671 ufshcd_outstanding_req_clear(hba, lrbp->task_tag);
5a0b0cb9
SRT		 2672 }
2673
2674 return err;
2675}
2676
2677/**
2678 * ufshcd_get_dev_cmd_tag - Get device management command tag
2679 * @hba: per-adapter instance
2680 * @tag: pointer to variable with available slot value
2681 *
2682 * Get a free slot and lock it until device management command
2683 * completes.
2684 *
2685 * Returns false if free slot is unavailable for locking, else
2686 * return true with tag value in @tag.
2687 */
2688static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
2689{
2690 int tag;
2691 bool ret = false;
2692 unsigned long tmp;
2693
2694 if (!tag_out)
2695 goto out;
2696
2697 do {
2698 tmp = ~hba->lrb_in_use;
2699 tag = find_last_bit(&tmp, hba->nutrs);
2700 if (tag >= hba->nutrs)
2701 goto out;
2702 } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
2703
2704 *tag_out = tag;
2705 ret = true;
2706out:
2707 return ret;
2708}
2709
2710static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
2711{
2712 clear_bit_unlock(tag, &hba->lrb_in_use);
2713}
2714
2715/**
2716 * ufshcd_exec_dev_cmd - API for sending device management requests
2717 * @hba - UFS hba
2718 * @cmd_type - specifies the type (NOP, Query...)
2719 * @timeout - time in seconds
2720 *
68078d5c
DR		 2721 * NOTE: Since there is only one available tag for device management commands,
2722 * it is expected you hold the hba->dev_cmd.lock mutex.
5a0b0cb9
SRT		 2723 */
2724static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
2725 enum dev_cmd_type cmd_type, int timeout)
2726{
2727 struct ufshcd_lrb *lrbp;
2728 int err;
2729 int tag;
2730 struct completion wait;
2731 unsigned long flags;
2732
0f7f11ff 2733 if (!ufshcd_is_link_active(hba)) {
c7cf4cc2 2734 flush_work(&hba->clk_gating.ungate_work);
2735 if (!ufshcd_is_link_active(hba))
0f7f11ff 2736 return -EPERM;
2737 }
a3cd5ec5
SJ		 2738 down_read(&hba->clk_scaling_lock);
2739
5a0b0cb9
SRT		 2740 /*
2741 * Get free slot, sleep if slots are unavailable.
2742 * Even though we use wait_event() which sleeps indefinitely,
2743 * the maximum wait time is bounded by SCSI request timeout.
2744 */
2745 wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
2746
2747 init_completion(&wait);
2748 lrbp = &hba->lrb[tag];
2749 WARN_ON(lrbp->cmd);
2750 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
2751 if (unlikely(err))
2752 goto out_put_tag;
2753
2754 hba->dev_cmd.complete = &wait;
2755
e3dfdc53
YG		 2756 /* Make sure descriptors are ready before ringing the doorbell */
2757 wmb();
5a0b0cb9 2758 spin_lock_irqsave(hba->host->host_lock, flags);
03229397 2759 if (hba->vops && hba->vops->set_nexus_t_xfer_req)
2760 hba->vops->set_nexus_t_xfer_req(hba, tag, lrbp->cmd);
5a0b0cb9
SRT		 2761 ufshcd_send_command(hba, tag);
2762 spin_unlock_irqrestore(hba->host->host_lock, flags);
2763
2764 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
2765
2766out_put_tag:
2767 ufshcd_put_dev_cmd_tag(hba, tag);
2768 wake_up(&hba->dev_cmd.tag_wq);
a3cd5ec5 2769 up_read(&hba->clk_scaling_lock);
5a0b0cb9
SRT		 2770 return err;
2771}
2772
d44a5f98
DR		 2773/**
2774 * ufshcd_init_query() - init the query response and request parameters
2775 * @hba: per-adapter instance
2776 * @request: address of the request pointer to be initialized
2777 * @response: address of the response pointer to be initialized
2778 * @opcode: operation to perform
2779 * @idn: flag idn to access
2780 * @index: LU number to access
2781 * @selector: query/flag/descriptor further identification
2782 */
2783static inline void ufshcd_init_query(struct ufs_hba *hba,
2784 struct ufs_query_req **request, struct ufs_query_res **response,
2785 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
2786{
2787 *request = &hba->dev_cmd.query.request;
2788 *response = &hba->dev_cmd.query.response;
2789 memset(*request, 0, sizeof(struct ufs_query_req));
2790 memset(*response, 0, sizeof(struct ufs_query_res));
2791 (*request)->upiu_req.opcode = opcode;
2792 (*request)->upiu_req.idn = idn;
2793 (*request)->upiu_req.index = index;
2794 (*request)->upiu_req.selector = selector;
2795}
2796
dc3c8d3a
YG		 2797static int ufshcd_query_flag_retry(struct ufs_hba *hba,
2798 enum query_opcode opcode, enum flag_idn idn, bool *flag_res)
2799{
2800 int ret;
2801 int retries;
2802
2803 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
2804 ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
2805 if (ret)
2806 dev_dbg(hba->dev,
2807 "%s: failed with error %d, retries %d\n",
2808 __func__, ret, retries);
2809 else
2810 break;
2811 }
2812
2813 if (ret)
2814 dev_err(hba->dev,
2815 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
2816 __func__, opcode, idn, ret, retries);
2817 return ret;
2818}
2819
68078d5c
DR		 2820/**
2821 * ufshcd_query_flag() - API function for sending flag query requests
2822 * hba: per-adapter instance
2823 * query_opcode: flag query to perform
2824 * idn: flag idn to access
2825 * flag_res: the flag value after the query request completes
2826 *
2827 * Returns 0 for success, non-zero in case of failure
2828 */
dc3c8d3a 2829int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
68078d5c
DR		 2830 enum flag_idn idn, bool *flag_res)
2831{
d44a5f98
DR		 2832 struct ufs_query_req *request = NULL;
2833 struct ufs_query_res *response = NULL;
2834 int err, index = 0, selector = 0;
e5ad406c 2835 int timeout = QUERY_REQ_TIMEOUT;
68078d5c
DR		 2836
2837 BUG_ON(!hba);
2838
1ab27c9c 2839 ufshcd_hold(hba, false);
68078d5c 2840 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2841 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2842 selector);
68078d5c
DR		 2843
2844 switch (opcode) {
2845 case UPIU_QUERY_OPCODE_SET_FLAG:
2846 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
2847 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
2848 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
2849 break;
2850 case UPIU_QUERY_OPCODE_READ_FLAG:
2851 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2852 if (!flag_res) {
2853 /* No dummy reads */
2854 dev_err(hba->dev, "%s: Invalid argument for read request\n",
2855 __func__);
2856 err = -EINVAL;
2857 goto out_unlock;
2858 }
2859 break;
2860 default:
2861 dev_err(hba->dev,
2862 "%s: Expected query flag opcode but got = %d\n",
2863 __func__, opcode);
2864 err = -EINVAL;
2865 goto out_unlock;
2866 }
68078d5c 2867
e5ad406c 2868 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
68078d5c
DR		 2869
2870 if (err) {
2871 dev_err(hba->dev,
2872 "%s: Sending flag query for idn %d failed, err = %d\n",
2873 __func__, idn, err);
2874 goto out_unlock;
2875 }
2876
2877 if (flag_res)
e8c8e82a 2878 *flag_res = (be32_to_cpu(response->upiu_res.value) &
68078d5c
DR		 2879 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
2880
2881out_unlock:
2882 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 2883 ufshcd_release(hba);
68078d5c
DR		 2884 return err;
2885}
2886
66ec6d59
SRT		 2887/**
2888 * ufshcd_query_attr - API function for sending attribute requests
2889 * hba: per-adapter instance
2890 * opcode: attribute opcode
2891 * idn: attribute idn to access
2892 * index: index field
2893 * selector: selector field
2894 * attr_val: the attribute value after the query request completes
2895 *
2896 * Returns 0 for success, non-zero in case of failure
2897*/
bdbe5d2f 2898static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
66ec6d59
SRT		 2899 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
2900{
d44a5f98
DR		 2901 struct ufs_query_req *request = NULL;
2902 struct ufs_query_res *response = NULL;
66ec6d59
SRT		 2903 int err;
2904
2905 BUG_ON(!hba);
2906
1ab27c9c 2907 ufshcd_hold(hba, false);
66ec6d59
SRT		 2908 if (!attr_val) {
2909 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
2910 __func__, opcode);
2911 err = -EINVAL;
2912 goto out;
2913 }
2914
2915 mutex_lock(&hba->dev_cmd.lock);
d44a5f98
DR		 2916 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
2917 selector);
66ec6d59
SRT		 2918
2919 switch (opcode) {
2920 case UPIU_QUERY_OPCODE_WRITE_ATTR:
2921 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
e8c8e82a 2922 request->upiu_req.value = cpu_to_be32(*attr_val);
66ec6d59
SRT		 2923 break;
2924 case UPIU_QUERY_OPCODE_READ_ATTR:
2925 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
2926 break;
2927 default:
2928 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
2929 __func__, opcode);
2930 err = -EINVAL;
2931 goto out_unlock;
2932 }
2933
d44a5f98 2934 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
66ec6d59
SRT		 2935
2936 if (err) {
4b761b58
YG		 2937 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
2938 __func__, opcode, idn, index, err);
66ec6d59
SRT		 2939 goto out_unlock;
2940 }
2941
e8c8e82a 2942 *attr_val = be32_to_cpu(response->upiu_res.value);
66ec6d59
SRT		 2943
2944out_unlock:
2945 mutex_unlock(&hba->dev_cmd.lock);
2946out:
1ab27c9c 2947 ufshcd_release(hba);
66ec6d59
SRT		 2948 return err;
2949}
2950
5e86ae44
YG		 2951/**
2952 * ufshcd_query_attr_retry() - API function for sending query
2953 * attribute with retries
2954 * @hba: per-adapter instance
2955 * @opcode: attribute opcode
2956 * @idn: attribute idn to access
2957 * @index: index field
2958 * @selector: selector field
2959 * @attr_val: the attribute value after the query request
2960 * completes
2961 *
2962 * Returns 0 for success, non-zero in case of failure
2963*/
2964static int ufshcd_query_attr_retry(struct ufs_hba *hba,
2965 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
2966 u32 *attr_val)
2967{
2968 int ret = 0;
2969 u32 retries;
2970
2971 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
2972 ret = ufshcd_query_attr(hba, opcode, idn, index,
2973 selector, attr_val);
2974 if (ret)
2975 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
2976 __func__, ret, retries);
2977 else
2978 break;
2979 }
2980
2981 if (ret)
2982 dev_err(hba->dev,
2983 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
2984 __func__, idn, ret, QUERY_REQ_RETRIES);
2985 return ret;
2986}
2987
a70e91b8 2988static int __ufshcd_query_descriptor(struct ufs_hba *hba,
d44a5f98
DR		 2989 enum query_opcode opcode, enum desc_idn idn, u8 index,
2990 u8 selector, u8 *desc_buf, int *buf_len)
2991{
2992 struct ufs_query_req *request = NULL;
2993 struct ufs_query_res *response = NULL;
508cb48c 2994 int err = 0;
d44a5f98
DR		 2995
2996 BUG_ON(!hba);
2997
1ab27c9c 2998 ufshcd_hold(hba, false);
d44a5f98
DR		 2999 if (!desc_buf) {
3000 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3001 __func__, opcode);
3002 err = -EINVAL;
3003 goto out;
3004 }
3005
a4b0e8a4 3006 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
d44a5f98
DR		 3007 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3008 __func__, *buf_len);
3009 err = -EINVAL;
3010 goto out;
3011 }
3012
3013 mutex_lock(&hba->dev_cmd.lock);
3014 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3015 selector);
3016 hba->dev_cmd.query.descriptor = desc_buf;
ea2aab24 3017 request->upiu_req.length = cpu_to_be16(*buf_len);
d44a5f98
DR		 3018
3019 switch (opcode) {
3020 case UPIU_QUERY_OPCODE_WRITE_DESC:
3021 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3022 break;
3023 case UPIU_QUERY_OPCODE_READ_DESC:
3024 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3025 break;
3026 default:
3027 dev_err(hba->dev,
3028 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3029 __func__, opcode);
3030 err = -EINVAL;
3031 goto out_unlock;
3032 }
3033
3034 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3035
3036 if (err) {
4b761b58
YG		 3037 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3038 __func__, opcode, idn, index, err);
d44a5f98
DR		 3039 goto out_unlock;
3040 }
3041
3042 hba->dev_cmd.query.descriptor = NULL;
ea2aab24 3043 *buf_len = be16_to_cpu(response->upiu_res.length);
d44a5f98
DR		 3044
3045out_unlock:
3046 mutex_unlock(&hba->dev_cmd.lock);
3047out:
1ab27c9c 3048 ufshcd_release(hba);
d44a5f98
DR		 3049 return err;
3050}
3051
a70e91b8
YG		 3052/**
3053 * ufshcd_query_descriptor_retry - API function for sending descriptor
3054 * requests
3055 * hba: per-adapter instance
3056 * opcode: attribute opcode
3057 * idn: attribute idn to access
3058 * index: index field
3059 * selector: selector field
3060 * desc_buf: the buffer that contains the descriptor
3061 * buf_len: length parameter passed to the device
3062 *
3063 * Returns 0 for success, non-zero in case of failure.
3064 * The buf_len parameter will contain, on return, the length parameter
3065 * received on the response.
3066 */
26cf9155
TW		 3067static int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3068 enum query_opcode opcode,
3069 enum desc_idn idn, u8 index,
3070 u8 selector,
3071 u8 *desc_buf, int *buf_len)
a70e91b8
YG		 3072{
3073 int err;
3074 int retries;
3075
3076 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3077 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3078 selector, desc_buf, buf_len);
3079 if (!err || err == -EINVAL)
3080 break;
3081 }
3082
3083 return err;
3084}
a70e91b8 3085
a4b0e8a4
PM		 3086/**
3087 * ufshcd_read_desc_length - read the specified descriptor length from header
3088 * @hba: Pointer to adapter instance
3089 * @desc_id: descriptor idn value
3090 * @desc_index: descriptor index
3091 * @desc_length: pointer to variable to read the length of descriptor
3092 *
3093 * Return 0 in case of success, non-zero otherwise
3094 */
3095static int ufshcd_read_desc_length(struct ufs_hba *hba,
3096 enum desc_idn desc_id,
3097 int desc_index,
3098 int *desc_length)
3099{
3100 int ret;
3101 u8 header[QUERY_DESC_HDR_SIZE];
3102 int header_len = QUERY_DESC_HDR_SIZE;
3103
3104 if (desc_id >= QUERY_DESC_IDN_MAX)
3105 return -EINVAL;
3106
3107 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3108 desc_id, desc_index, 0, header,
3109 &header_len);
3110
3111 if (ret) {
3112 dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
3113 __func__, desc_id);
3114 return ret;
3115 } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
3116 dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
3117 __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
3118 desc_id);
3119 ret = -EINVAL;
3120 }
3121
3122 *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
3123 return ret;
3124
3125}
3126
3127/**
3128 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3129 * @hba: Pointer to adapter instance
3130 * @desc_id: descriptor idn value
3131 * @desc_len: mapped desc length (out)
3132 *
3133 * Return 0 in case of success, non-zero otherwise
3134 */
3135int ufshcd_map_desc_id_to_length(struct ufs_hba *hba,
3136 enum desc_idn desc_id, int *desc_len)
3137{
3138 switch (desc_id) {
3139 case QUERY_DESC_IDN_DEVICE:
3140 *desc_len = hba->desc_size.dev_desc;
3141 break;
3142 case QUERY_DESC_IDN_POWER:
3143 *desc_len = hba->desc_size.pwr_desc;
3144 break;
3145 case QUERY_DESC_IDN_GEOMETRY:
3146 *desc_len = hba->desc_size.geom_desc;
3147 break;
3148 case QUERY_DESC_IDN_CONFIGURATION:
3149 *desc_len = hba->desc_size.conf_desc;
3150 break;
3151 case QUERY_DESC_IDN_UNIT:
3152 *desc_len = hba->desc_size.unit_desc;
3153 break;
3154 case QUERY_DESC_IDN_INTERCONNECT:
3155 *desc_len = hba->desc_size.interc_desc;
3156 break;
3157 case QUERY_DESC_IDN_STRING:
3158 *desc_len = QUERY_DESC_MAX_SIZE;
3159 break;
3160 case QUERY_DESC_IDN_RFU_0:
3161 case QUERY_DESC_IDN_RFU_1:
3162 *desc_len = 0;
3163 break;
3164 default:
3165 *desc_len = 0;
3166 return -EINVAL;
3167 }
3168 return 0;
3169}
3170EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3171
da461cec
SJ		 3172/**
3173 * ufshcd_read_desc_param - read the specified descriptor parameter
3174 * @hba: Pointer to adapter instance
3175 * @desc_id: descriptor idn value
3176 * @desc_index: descriptor index
3177 * @param_offset: offset of the parameter to read
3178 * @param_read_buf: pointer to buffer where parameter would be read
3179 * @param_size: sizeof(param_read_buf)
3180 *
3181 * Return 0 in case of success, non-zero otherwise
3182 */
3183static int ufshcd_read_desc_param(struct ufs_hba *hba,
3184 enum desc_idn desc_id,
3185 int desc_index,
a4b0e8a4 3186 u8 param_offset,
da461cec 3187 u8 *param_read_buf,
a4b0e8a4 3188 u8 param_size)
da461cec
SJ		 3189{
3190 int ret;
3191 u8 *desc_buf;
a4b0e8a4 3192 int buff_len;
da461cec
SJ		 3193 bool is_kmalloc = true;
3194
a4b0e8a4
PM		 3195 /* Safety check */
3196 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
da461cec
SJ		 3197 return -EINVAL;
3198
a4b0e8a4
PM		 3199 /* Get the max length of descriptor from structure filled up at probe
3200 * time.
3201 */
3202 ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
da461cec 3203
a4b0e8a4
PM		 3204 /* Sanity checks */
3205 if (ret || !buff_len) {
3206 dev_err(hba->dev, "%s: Failed to get full descriptor length",
3207 __func__);
3208 return ret;
3209 }
3210
3211 /* Check whether we need temp memory */
3212 if (param_offset != 0 || param_size < buff_len) {
da461cec
SJ		 3213 desc_buf = kmalloc(buff_len, GFP_KERNEL);
3214 if (!desc_buf)
3215 return -ENOMEM;
a4b0e8a4
PM		 3216 } else {
3217 desc_buf = param_read_buf;
3218 is_kmalloc = false;
da461cec
SJ		 3219 }
3220
a4b0e8a4 3221 /* Request for full descriptor */
a70e91b8 3222 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
a4b0e8a4
PM		 3223 desc_id, desc_index, 0,
3224 desc_buf, &buff_len);
da461cec 3225
bde44bb6
SJ		 3226 if (ret) {
3227 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
3228 __func__, desc_id, desc_index, param_offset, ret);
da461cec
SJ		 3229 goto out;
3230 }
3231
bde44bb6
SJ		 3232 /* Sanity check */
3233 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3234 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
3235 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3236 ret = -EINVAL;
3237 goto out;
3238 }
3239
8d65d1bb 3240 /*
3241 * While reading variable size descriptors (like string descriptor),
3242 * some UFS devices may report the "LENGTH" (field in "Transaction
3243 * Specific fields" of Query Response UPIU) same as what was requested
3244 * in Query Request UPIU instead of reporting the actual size of the
3245 * variable size descriptor.
3246 * Although it's safe to ignore the "LENGTH" field for variable size
3247 * descriptors as we can always derive the length of the descriptor from
3248 * the descriptor header fields. Hence this change impose the length
3249 * match check only for fixed size descriptors (for which we always
3250 * request the correct size as part of Query Request UPIU).
3251 */
3252 if ((desc_id != QUERY_DESC_IDN_STRING) &&
3253 (buff_len != desc_buf[QUERY_DESC_LENGTH_OFFSET])) {
3254 dev_err(hba->dev, "%s: desc_buf length mismatch: buff_len %d, buff_len(desc_header) %d",
3255 __func__, buff_len, desc_buf[QUERY_DESC_LENGTH_OFFSET]);
3256 ret = -EINVAL;
3257 goto out;
3258 }
a4b0e8a4
PM		 3259 /* Check wherher we will not copy more data, than available */
3260 if (is_kmalloc && param_size > buff_len)
3261 param_size = buff_len;
bde44bb6 3262
da461cec
SJ		 3263 if (is_kmalloc)
3264 memcpy(param_read_buf, &desc_buf[param_offset], param_size);
3265out:
3266 if (is_kmalloc)
3267 kfree(desc_buf);
3268 return ret;
3269}
3270
3271static inline int ufshcd_read_desc(struct ufs_hba *hba,
3272 enum desc_idn desc_id,
3273 int desc_index,
3274 u8 *buf,
3275 u32 size)
3276{
3277 return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
3278}
3279
3280static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
3281 u8 *buf,
3282 u32 size)
3283{
dbd34a61 3284 return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
da461cec
SJ		 3285}
3286
8209b6d5 3287static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
b573d484
YG		 3288{
3289 return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
3290}
b573d484
YG		 3291
3292/**
3293 * ufshcd_read_string_desc - read string descriptor
3294 * @hba: pointer to adapter instance
3295 * @desc_index: descriptor index
3296 * @buf: pointer to buffer where descriptor would be read
3297 * @size: size of buf
3298 * @ascii: if true convert from unicode to ascii characters
3299 *
3300 * Return 0 in case of success, non-zero otherwise
3301 */
8209b6d5
TW		 3302#define ASCII_STD true
3303static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
3304 u8 *buf, u32 size, bool ascii)
b573d484
YG		 3305{
3306 int err = 0;
3307
3308 err = ufshcd_read_desc(hba,
3309 QUERY_DESC_IDN_STRING, desc_index, buf, size);
3310
3311 if (err) {
3312 dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
3313 __func__, QUERY_REQ_RETRIES, err);
3314 goto out;
3315 }
3316
3317 if (ascii) {
3318 int desc_len;
3319 int ascii_len;
3320 int i;
3321 char *buff_ascii;
3322
3323 desc_len = buf[0];
3324 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3325 ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3326 if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
3327 dev_err(hba->dev, "%s: buffer allocated size is too small\n",
3328 __func__);
3329 err = -ENOMEM;
3330 goto out;
3331 }
3332
3333 buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
3334 if (!buff_ascii) {
3335 err = -ENOMEM;
fcbefc3b 3336 goto out;
b573d484
YG		 3337 }
3338
3339 /*
3340 * the descriptor contains string in UTF16 format
3341 * we need to convert to utf-8 so it can be displayed
3342 */
3343 utf16s_to_utf8s((wchar_t *)&buf[QUERY_DESC_HDR_SIZE],
3344 desc_len - QUERY_DESC_HDR_SIZE,
3345 UTF16_BIG_ENDIAN, buff_ascii, ascii_len);
3346
3347 /* replace non-printable or non-ASCII characters with spaces */
3348 for (i = 0; i < ascii_len; i++)
3349 ufshcd_remove_non_printable(&buff_ascii[i]);
3350
3351 memset(buf + QUERY_DESC_HDR_SIZE, 0,
3352 size - QUERY_DESC_HDR_SIZE);
3353 memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
3354 buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
b573d484
YG		 3355 kfree(buff_ascii);
3356 }
3357out:
3358 return err;
3359}
b573d484 3360
da461cec
SJ		 3361/**
3362 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3363 * @hba: Pointer to adapter instance
3364 * @lun: lun id
3365 * @param_offset: offset of the parameter to read
3366 * @param_read_buf: pointer to buffer where parameter would be read
3367 * @param_size: sizeof(param_read_buf)
3368 *
3369 * Return 0 in case of success, non-zero otherwise
3370 */
3371static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3372 int lun,
3373 enum unit_desc_param param_offset,
3374 u8 *param_read_buf,
3375 u32 param_size)
3376{
3377 /*
3378 * Unit descriptors are only available for general purpose LUs (LUN id
3379 * from 0 to 7) and RPMB Well known LU.
3380 */
0ce147d4 3381 if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
da461cec
SJ		 3382 return -EOPNOTSUPP;
3383
3384 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3385 param_offset, param_read_buf, param_size);
3386}
3387
8d65d1bb 3388int ufshcd_read_health_desc(struct ufs_hba *hba, u8 *buf, u32 size)
3389{
3390 int err = 0;
3391
3392 err = ufshcd_read_desc(hba,
3393 QUERY_DESC_IDN_HEALTH, 0, buf, size);
3394
3395 if (err)
3396 dev_err(hba->dev, "%s: reading Device Health Desc failed. err = %d\n",
3397 __func__, err);
3398
3399 return err;
3400}
3401
7a3e97b0
SY		 3402/**
3403 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3404 * @hba: per adapter instance
3405 *
3406 * 1. Allocate DMA memory for Command Descriptor array
3407 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3408 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3409 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3410 * (UTMRDL)
3411 * 4. Allocate memory for local reference block(lrb).
3412 *
3413 * Returns 0 for success, non-zero in case of failure
3414 */
3415static int ufshcd_memory_alloc(struct ufs_hba *hba)
3416{
3417 size_t utmrdl_size, utrdl_size, ucdl_size;
3418
3419 /* Allocate memory for UTP command descriptors */
3420 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
2953f850
SJ		 3421 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3422 ucdl_size,
3423 &hba->ucdl_dma_addr,
3424 GFP_KERNEL);
7a3e97b0
SY		 3425
3426 /*
3427 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3428 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3429 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3430 * be aligned to 128 bytes as well
3431 */
3432 if (!hba->ucdl_base_addr ||
3433 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3434 dev_err(hba->dev,
7a3e97b0
SY		 3435 "Command Descriptor Memory allocation failed\n");
3436 goto out;
3437 }
3438
3439 /*
3440 * Allocate memory for UTP Transfer descriptors
3441 * UFSHCI requires 1024 byte alignment of UTRD
3442 */
3443 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
2953f850
SJ		 3444 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3445 utrdl_size,
3446 &hba->utrdl_dma_addr,
3447 GFP_KERNEL);
7a3e97b0
SY		 3448 if (!hba->utrdl_base_addr ||
3449 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3450 dev_err(hba->dev,
7a3e97b0
SY		 3451 "Transfer Descriptor Memory allocation failed\n");
3452 goto out;
3453 }
3454
3455 /*
3456 * Allocate memory for UTP Task Management descriptors
3457 * UFSHCI requires 1024 byte alignment of UTMRD
3458 */
3459 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
2953f850
SJ		 3460 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3461 utmrdl_size,
3462 &hba->utmrdl_dma_addr,
3463 GFP_KERNEL);
7a3e97b0
SY		 3464 if (!hba->utmrdl_base_addr ||
3465 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3b1d0580 3466 dev_err(hba->dev,
7a3e97b0
SY		 3467 "Task Management Descriptor Memory allocation failed\n");
3468 goto out;
3469 }
3470
3471 /* Allocate memory for local reference block */
2953f850
SJ		 3472 hba->lrb = devm_kzalloc(hba->dev,
3473 hba->nutrs * sizeof(struct ufshcd_lrb),
3474 GFP_KERNEL);
7a3e97b0 3475 if (!hba->lrb) {
3b1d0580 3476 dev_err(hba->dev, "LRB Memory allocation failed\n");
7a3e97b0
SY		 3477 goto out;
3478 }
3479 return 0;
3480out:
7a3e97b0
SY		 3481 return -ENOMEM;
3482}
3483
3484/**
3485 * ufshcd_host_memory_configure - configure local reference block with
3486 * memory offsets
3487 * @hba: per adapter instance
3488 *
3489 * Configure Host memory space
3490 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3491 * address.
3492 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3493 * and PRDT offset.
3494 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3495 * into local reference block.
3496 */
3497static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3498{
3499 struct utp_transfer_cmd_desc *cmd_descp;
3500 struct utp_transfer_req_desc *utrdlp;
3501 dma_addr_t cmd_desc_dma_addr;
3502 dma_addr_t cmd_desc_element_addr;
3503 u16 response_offset;
3504 u16 prdt_offset;
3505 int cmd_desc_size;
3506 int i;
3507
3508 utrdlp = hba->utrdl_base_addr;
3509 cmd_descp = hba->ucdl_base_addr;
3510
3511 response_offset =
3512 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3513 prdt_offset =
3514 offsetof(struct utp_transfer_cmd_desc, prd_table);
3515
3516 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3517 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3518
3519 for (i = 0; i < hba->nutrs; i++) {
3520 /* Configure UTRD with command descriptor base address */
3521 cmd_desc_element_addr =
3522 (cmd_desc_dma_addr + (cmd_desc_size * i));
3523 utrdlp[i].command_desc_base_addr_lo =
3524 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3525 utrdlp[i].command_desc_base_addr_hi =
3526 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3527
3528 /* Response upiu and prdt offset should be in double words */
75b1cc4a
KK		 3529 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3530 utrdlp[i].response_upiu_offset =
3531 cpu_to_le16(response_offset);
3532 utrdlp[i].prd_table_offset =
3533 cpu_to_le16(prdt_offset);
3534 utrdlp[i].response_upiu_length =
3535 cpu_to_le16(ALIGNED_UPIU_SIZE);
3536 } else {
3537 utrdlp[i].response_upiu_offset =
7a3e97b0 3538 cpu_to_le16((response_offset >> 2));
75b1cc4a 3539 utrdlp[i].prd_table_offset =
7a3e97b0 3540 cpu_to_le16((prdt_offset >> 2));
75b1cc4a 3541 utrdlp[i].response_upiu_length =
3ca316c5 3542 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
75b1cc4a 3543 }
7a3e97b0
SY		 3544
3545 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
ff8e20c6
DR		 3546 hba->lrb[i].utrd_dma_addr = hba->utrdl_dma_addr +
3547 (i * sizeof(struct utp_transfer_req_desc));
5a0b0cb9
SRT		 3548 hba->lrb[i].ucd_req_ptr =
3549 (struct utp_upiu_req *)(cmd_descp + i);
ff8e20c6 3550 hba->lrb[i].ucd_req_dma_addr = cmd_desc_element_addr;
7a3e97b0
SY		 3551 hba->lrb[i].ucd_rsp_ptr =
3552 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
ff8e20c6
DR		 3553 hba->lrb[i].ucd_rsp_dma_addr = cmd_desc_element_addr +
3554 response_offset;
7a3e97b0
SY		 3555 hba->lrb[i].ucd_prdt_ptr =
3556 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
ff8e20c6
DR		 3557 hba->lrb[i].ucd_prdt_dma_addr = cmd_desc_element_addr +
3558 prdt_offset;
7a3e97b0
SY		 3559 }
3560}
3561
3562/**
3563 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3564 * @hba: per adapter instance
3565 *
3566 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3567 * in order to initialize the Unipro link startup procedure.
3568 * Once the Unipro links are up, the device connected to the controller
3569 * is detected.
3570 *
3571 * Returns 0 on success, non-zero value on failure
3572 */
3573static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3574{
6ccf44fe
SJ		 3575 struct uic_command uic_cmd = {0};
3576 int ret;
7a3e97b0 3577
6ccf44fe 3578 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
7a3e97b0 3579
6ccf44fe
SJ		 3580 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3581 if (ret)
ff8e20c6 3582 dev_dbg(hba->dev,
6ccf44fe
SJ		 3583 "dme-link-startup: error code %d\n", ret);
3584 return ret;
7a3e97b0
SY		 3585}
3586
cad2e03d
YG		 3587static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3588{
3589 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3590 unsigned long min_sleep_time_us;
3591
3592 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3593 return;
3594
3595 /*
3596 * last_dme_cmd_tstamp will be 0 only for 1st call to
3597 * this function
3598 */
3599 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3600 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3601 } else {
3602 unsigned long delta =
3603 (unsigned long) ktime_to_us(
3604 ktime_sub(ktime_get(),
3605 hba->last_dme_cmd_tstamp));
3606
3607 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3608 min_sleep_time_us =
3609 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3610 else
3611 return; /* no more delay required */
3612 }
3613
3614 /* allow sleep for extra 50us if needed */
3615 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3616}
3617
623b5fe3 3618static int ufshcd_dme_reset(struct ufs_hba *hba)
3619{
3620 struct uic_command uic_cmd = {0};
3621 int ret;
3622
3623 uic_cmd.command = UIC_CMD_DME_RESET;
3624 uic_cmd.argument1 = 0x1;
3625
3626 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3627 if (ret)
3628 dev_err(hba->dev,
3629 "dme-reset: error code %d\n", ret);
3630
3631 return ret;
3632}
3633
3634static int ufshcd_dme_enable(struct ufs_hba *hba)
3635{
3636 struct uic_command uic_cmd = {0};
3637 int ret;
3638
3639 uic_cmd.command = UIC_CMD_DME_ENABLE;
3640
3641 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3642 if (ret)
3643 dev_err(hba->dev,
3644 "dme-enable: error code %d\n", ret);
3645
3646 return ret;
3647}
3648
12b4fdb4
SJ		 3649/**
3650 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3651 * @hba: per adapter instance
3652 * @attr_sel: uic command argument1
3653 * @attr_set: attribute set type as uic command argument2
3654 * @mib_val: setting value as uic command argument3
3655 * @peer: indicate whether peer or local
3656 *
3657 * Returns 0 on success, non-zero value on failure
3658 */
3659int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3660 u8 attr_set, u32 mib_val, u8 peer)
3661{
3662 struct uic_command uic_cmd = {0};
3663 static const char *const action[] = {
3664 "dme-set",
3665 "dme-peer-set"
3666 };
3667 const char *set = action[!!peer];
3668 int ret;
64238fbd 3669 int retries = UFS_UIC_COMMAND_RETRIES;
12b4fdb4
SJ		 3670
3671 uic_cmd.command = peer ?
3672 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3673 uic_cmd.argument1 = attr_sel;
3674 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3675 uic_cmd.argument3 = mib_val;
3676
64238fbd
YG		 3677 do {
3678 /* for peer attributes we retry upon failure */
3679 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3680 if (ret)
3681 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3682 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3683 } while (ret && peer && --retries);
3684
f37e9f8c 3685 if (ret)
64238fbd 3686 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
f37e9f8c
YG		 3687 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3688 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4
SJ		 3689
3690 return ret;
3691}
3692EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3693
3694/**
3695 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3696 * @hba: per adapter instance
3697 * @attr_sel: uic command argument1
3698 * @mib_val: the value of the attribute as returned by the UIC command
3699 * @peer: indicate whether peer or local
3700 *
3701 * Returns 0 on success, non-zero value on failure
3702 */
3703int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3704 u32 *mib_val, u8 peer)
3705{
3706 struct uic_command uic_cmd = {0};
3707 static const char *const action[] = {
3708 "dme-get",
3709 "dme-peer-get"
3710 };
3711 const char *get = action[!!peer];
3712 int ret;
64238fbd 3713 int retries = UFS_UIC_COMMAND_RETRIES;
874237f7
YG		 3714 struct ufs_pa_layer_attr orig_pwr_info;
3715 struct ufs_pa_layer_attr temp_pwr_info;
3716 bool pwr_mode_change = false;
3717
3718 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3719 orig_pwr_info = hba->pwr_info;
3720 temp_pwr_info = orig_pwr_info;
3721
3722 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3723 orig_pwr_info.pwr_rx == FAST_MODE) {
3724 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3725 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3726 pwr_mode_change = true;
3727 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3728 orig_pwr_info.pwr_rx == SLOW_MODE) {
3729 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3730 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3731 pwr_mode_change = true;
3732 }
3733 if (pwr_mode_change) {
3734 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3735 if (ret)
3736 goto out;
3737 }
3738 }
12b4fdb4
SJ		 3739
3740 uic_cmd.command = peer ?
3741 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3742 uic_cmd.argument1 = attr_sel;
3743
64238fbd
YG		 3744 do {
3745 /* for peer attributes we retry upon failure */
3746 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3747 if (ret)
3748 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
3749 get, UIC_GET_ATTR_ID(attr_sel), ret);
3750 } while (ret && peer && --retries);
3751
f37e9f8c 3752 if (ret)
64238fbd 3753 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
f37e9f8c
YG		 3754 get, UIC_GET_ATTR_ID(attr_sel),
3755 UFS_UIC_COMMAND_RETRIES - retries);
12b4fdb4 3756
64238fbd 3757 if (mib_val && !ret)
12b4fdb4 3758 *mib_val = uic_cmd.argument3;
874237f7
YG		 3759
3760 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
3761 && pwr_mode_change)
3762 ufshcd_change_power_mode(hba, &orig_pwr_info);
12b4fdb4
SJ		 3763out:
3764 return ret;
3765}
3766EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
3767
53b3d9c3 3768/**
57d104c1
SJ		 3769 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
3770 * state) and waits for it to take effect.
3771 *
53b3d9c3 3772 * @hba: per adapter instance
57d104c1
SJ		 3773 * @cmd: UIC command to execute
3774 *
3775 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
3776 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
3777 * and device UniPro link and hence it's final completion would be indicated by
3778 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
3779 * addition to normal UIC command completion Status (UCCS). This function only
3780 * returns after the relevant status bits indicate the completion.
53b3d9c3
SJ		 3781 *
3782 * Returns 0 on success, non-zero value on failure
3783 */
57d104c1 3784static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
53b3d9c3 3785{
57d104c1 3786 struct completion uic_async_done;
53b3d9c3
SJ		 3787 unsigned long flags;
3788 u8 status;
3789 int ret;
d75f7fe4 3790 bool reenable_intr = false;
53b3d9c3 3791
53b3d9c3 3792 mutex_lock(&hba->uic_cmd_mutex);
57d104c1 3793 init_completion(&uic_async_done);
cad2e03d 3794 ufshcd_add_delay_before_dme_cmd(hba);
53b3d9c3
SJ		 3795
3796 spin_lock_irqsave(hba->host->host_lock, flags);
57d104c1 3797 hba->uic_async_done = &uic_async_done;
d75f7fe4
YG		 3798 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
3799 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
3800 /*
3801 * Make sure UIC command completion interrupt is disabled before
3802 * issuing UIC command.
3803 */
3804 wmb();
3805 reenable_intr = true;
57d104c1 3806 }
d75f7fe4
YG		 3807 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
3808 spin_unlock_irqrestore(hba->host->host_lock, flags);
57d104c1
SJ		 3809 if (ret) {
3810 dev_err(hba->dev,
3811 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
3812 cmd->command, cmd->argument3, ret);
53b3d9c3
SJ		 3813 goto out;
3814 }
3815
57d104c1 3816 if (!wait_for_completion_timeout(hba->uic_async_done,
53b3d9c3
SJ		 3817 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
3818 dev_err(hba->dev,
57d104c1
SJ		 3819 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
3820 cmd->command, cmd->argument3);
53b3d9c3
SJ		 3821 ret = -ETIMEDOUT;
3822 goto out;
3823 }
3824
cef1bd92 3825 status = ufshcd_get_upmcrs(hba, cmd);
53b3d9c3
SJ		 3826 if (status != PWR_LOCAL) {
3827 dev_err(hba->dev,
73615428 3828 "pwr ctrl cmd 0x%0x failed, host upmcrs:0x%x\n",
57d104c1 3829 cmd->command, status);
53b3d9c3
SJ		 3830 ret = (status != PWR_OK) ? status : -1;
3831 }
3832out:
aee9809c 3833 /* Dump debugging information to system memory */
7942f7b5 3834 if (ret) {
aee9809c 3835 ufshcd_vops_dbg_register_dump(hba);
cf632748 3836 exynos_ufs_show_uic_info(hba);
7942f7b5
VG		 3837 ufshcd_print_host_state(hba);
3838 ufshcd_print_pwr_info(hba);
3839 ufshcd_print_host_regs(hba);
3840 }
3841
53b3d9c3 3842 spin_lock_irqsave(hba->host->host_lock, flags);
d75f7fe4 3843 hba->active_uic_cmd = NULL;
57d104c1 3844 hba->uic_async_done = NULL;
d75f7fe4
YG		 3845 if (reenable_intr)
3846 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
53b3d9c3
SJ		 3847 spin_unlock_irqrestore(hba->host->host_lock, flags);
3848 mutex_unlock(&hba->uic_cmd_mutex);
1ab27c9c 3849
53b3d9c3
SJ		 3850 return ret;
3851}
3852
57d104c1
SJ		 3853/**
3854 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
3855 * using DME_SET primitives.
3856 * @hba: per adapter instance
3857 * @mode: powr mode value
3858 *
3859 * Returns 0 on success, non-zero value on failure
3860 */
3861static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
3862{
3863 struct uic_command uic_cmd = {0};
1ab27c9c 3864 int ret;
57d104c1 3865
c3a2f9ee
YG		 3866 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
3867 ret = ufshcd_dme_set(hba,
3868 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
3869 if (ret) {
3870 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
3871 __func__, ret);
3872 goto out;
3873 }
3874 }
3875
57d104c1
SJ		 3876 uic_cmd.command = UIC_CMD_DME_SET;
3877 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
3878 uic_cmd.argument3 = mode;
1ab27c9c
ST		 3879 ufshcd_hold(hba, false);
3880 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
3881 ufshcd_release(hba);
57d104c1 3882
c3a2f9ee 3883out:
1ab27c9c 3884 return ret;
57d104c1
SJ		 3885}
3886
53c12d0e
YG		 3887static int ufshcd_link_recovery(struct ufs_hba *hba)
3888{
3889 int ret;
3890 unsigned long flags;
3891
3892 spin_lock_irqsave(hba->host->host_lock, flags);
3893 hba->ufshcd_state = UFSHCD_STATE_RESET;
3894 ufshcd_set_eh_in_progress(hba);
3895 spin_unlock_irqrestore(hba->host->host_lock, flags);
3896
3897 ret = ufshcd_host_reset_and_restore(hba);
3898
3899 spin_lock_irqsave(hba->host->host_lock, flags);
3900 if (ret)
3901 hba->ufshcd_state = UFSHCD_STATE_ERROR;
3902 ufshcd_clear_eh_in_progress(hba);
3903 spin_unlock_irqrestore(hba->host->host_lock, flags);
3904
3905 if (ret)
3906 dev_err(hba->dev, "%s: link recovery failed, err %d",
3907 __func__, ret);
3908
3909 return ret;
3910}
3911
87d0b4a6 3912static int __ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
57d104c1 3913{
87d0b4a6 3914 int ret;
57d104c1 3915 struct uic_command uic_cmd = {0};
911a0771 3916 ktime_t start = ktime_get();
57d104c1 3917
ee32c909
KK		 3918 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
3919
57d104c1 3920 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
87d0b4a6 3921 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3922 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
3923 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
87d0b4a6 3924
53c12d0e 3925 if (ret) {
87d0b4a6
YG		 3926 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
3927 __func__, ret);
3928
53c12d0e
YG		 3929 /*
3930 * If link recovery fails then return error so that caller
3931 * don't retry the hibern8 enter again.
3932 */
3933 if (ufshcd_link_recovery(hba))
3934 ret = -ENOLINK;
ee32c909
KK		 3935 } else
3936 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
3937 POST_CHANGE);
53c12d0e 3938
87d0b4a6
YG		 3939 return ret;
3940}
3941
3942static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
3943{
3944 int ret = 0, retries;
57d104c1 3945
87d0b4a6
YG		 3946 for (retries = UIC_HIBERN8_ENTER_RETRIES; retries > 0; retries--) {
3947 ret = __ufshcd_uic_hibern8_enter(hba);
3948 if (!ret || ret == -ENOLINK)
3949 goto out;
3950 }
3951out:
3952 return ret;
57d104c1
SJ		 3953}
3954
3955static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
3956{
3957 struct uic_command uic_cmd = {0};
3958 int ret;
911a0771 3959 ktime_t start = ktime_get();
57d104c1 3960
ee32c909
KK		 3961 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
3962
57d104c1
SJ		 3963 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
3964 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
911a0771
SJ		 3965 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
3966 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
3967
57d104c1 3968 if (ret) {
53c12d0e
YG		 3969 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
3970 __func__, ret);
3971 ret = ufshcd_link_recovery(hba);
ff8e20c6 3972 } else {
ee32c909
KK		 3973 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
3974 POST_CHANGE);
ff8e20c6
DR		 3975 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
3976 hba->ufs_stats.hibern8_exit_cnt++;
3977 }
57d104c1
SJ		 3978
3979 return ret;
3980}
3981
5064636c
YG		 3982 /**
3983 * ufshcd_init_pwr_info - setting the POR (power on reset)
3984 * values in hba power info
3985 * @hba: per-adapter instance
3986 */
3987static void ufshcd_init_pwr_info(struct ufs_hba *hba)
3988{
3989 hba->pwr_info.gear_rx = UFS_PWM_G1;
3990 hba->pwr_info.gear_tx = UFS_PWM_G1;
3991 hba->pwr_info.lane_rx = 1;
3992 hba->pwr_info.lane_tx = 1;
3993 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
3994 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
3995 hba->pwr_info.hs_rate = 0;
3996}
3997
0f7f11ff 3998static int ufshcd_link_hibern8_ctrl(struct ufs_hba *hba, bool en)
3999{
4000 int ret;
4001
4002 if (hba->vops && hba->vops->hibern8_notify)
4003 hba->vops->hibern8_notify(hba, en, PRE_CHANGE);
4004
4005 if (en)
4006 ret = ufshcd_uic_hibern8_enter(hba);
4007 else
4008 ret = ufshcd_uic_hibern8_exit(hba);
57579a4a 4009
4010 if (ret || (hba->saved_err & INT_FATAL_ERRORS) ||
4011 ((hba->saved_err & UIC_ERROR) &&
4012 ((hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
4013 (hba->saved_uic_err & UFSHCD_UIC_DL_ERROR)))) {
4014
4015 if (!ret)
4016 ret = hba->saved_err;
0f7f11ff 4017 goto out;
4018 }
9632ac5f 4019
4020 if (hba->monitor.flag & UFSHCD_MONITOR_LEVEL2) {
4021 if (en)
4022 dev_info(hba->dev, "H8+\n");
4023 else
4024 dev_info(hba->dev, "H8-\n");
4025 }
4026
0f7f11ff 4027 if (hba->vops && hba->vops->hibern8_notify)
4028 hba->vops->hibern8_notify(hba, en, POST_CHANGE);
4029out:
a60d7ef4 4030 hba->tcx_replay_timer_expired_cnt = 0;
4031 hba->fcx_protection_timer_expired_cnt = 0;
4032
0f7f11ff 4033 return ret;
4034}
4035
d3e89bac 4036/**
7eb584db
DR		 4037 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4038 * @hba: per-adapter instance
d3e89bac 4039 */
7eb584db 4040static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
d3e89bac 4041{
7eb584db
DR		 4042 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4043
4044 if (hba->max_pwr_info.is_valid)
4045 return 0;
4046
2349b533
SJ		 4047 pwr_info->pwr_tx = FAST_MODE;
4048 pwr_info->pwr_rx = FAST_MODE;
7eb584db 4049 pwr_info->hs_rate = PA_HS_MODE_B;
d3e89bac
SJ		 4050
4051 /* Get the connected lane count */
7eb584db
DR		 4052 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4053 &pwr_info->lane_rx);
4054 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4055 &pwr_info->lane_tx);
4056
4057 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4058 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4059 __func__,
4060 pwr_info->lane_rx,
4061 pwr_info->lane_tx);
72c97747 4062
4063 hba->tcx_replay_timer_expired_cnt = 0;
4064 hba->fcx_protection_timer_expired_cnt = 0;
4065
4066 /* Get the peer available lane count */
4067 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
4068 &pwr_info->peer_available_lane_rx);
4069 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
4070 &pwr_info->peer_available_lane_tx);
4071
4072 if (!pwr_info->peer_available_lane_rx || !pwr_info->peer_available_lane_tx) {
4073 dev_err(hba->dev, "%s: invalid peer available lanes value. rx=%d, tx=%d\n",
4074 __func__,
4075 pwr_info->peer_available_lane_rx,
4076 pwr_info->peer_available_lane_tx);
7eb584db
DR		 4077 return -EINVAL;
4078 }
d3e89bac
SJ		 4079
4080 /*
4081 * First, get the maximum gears of HS speed.
4082 * If a zero value, it means there is no HSGEAR capability.
4083 * Then, get the maximum gears of PWM speed.
4084 */
7eb584db
DR		 4085 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4086 if (!pwr_info->gear_rx) {
4087 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4088 &pwr_info->gear_rx);
4089 if (!pwr_info->gear_rx) {
4090 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4091 __func__, pwr_info->gear_rx);
4092 return -EINVAL;
4093 }
2349b533 4094 pwr_info->pwr_rx = SLOW_MODE;
d3e89bac
SJ		 4095 }
4096
7eb584db
DR		 4097 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4098 &pwr_info->gear_tx);
4099 if (!pwr_info->gear_tx) {
d3e89bac 4100 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
7eb584db
DR		 4101 &pwr_info->gear_tx);
4102 if (!pwr_info->gear_tx) {
4103 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4104 __func__, pwr_info->gear_tx);
4105 return -EINVAL;
4106 }
2349b533 4107 pwr_info->pwr_tx = SLOW_MODE;
7eb584db
DR		 4108 }
4109
4110 hba->max_pwr_info.is_valid = true;
4111 return 0;
4112}
4113
4114static int ufshcd_change_power_mode(struct ufs_hba *hba,
4115 struct ufs_pa_layer_attr *pwr_mode)
4116{
4117 int ret;
4118
4119 /* if already configured to the requested pwr_mode */
4120 if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4121 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4122 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4123 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4124 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4125 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4126 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4127 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4128 return 0;
d3e89bac
SJ		 4129 }
4130
4131 /*
4132 * Configure attributes for power mode change with below.
4133 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4134 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4135 * - PA_HSSERIES
4136 */
7eb584db
DR		 4137 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4138 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4139 pwr_mode->lane_rx);
4140 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4141 pwr_mode->pwr_rx == FAST_MODE)
d3e89bac 4142 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
7eb584db
DR		 4143 else
4144 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
d3e89bac 4145
7eb584db
DR		 4146 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4147 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4148 pwr_mode->lane_tx);
4149 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4150 pwr_mode->pwr_tx == FAST_MODE)
d3e89bac 4151 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
7eb584db
DR		 4152 else
4153 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
d3e89bac 4154
7eb584db
DR		 4155 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4156 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4157 pwr_mode->pwr_rx == FAST_MODE ||
4158 pwr_mode->pwr_tx == FAST_MODE)
4159 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4160 pwr_mode->hs_rate);
d3e89bac 4161
7eb584db
DR		 4162 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4163 | pwr_mode->pwr_tx);
4164
4165 if (ret) {
d3e89bac 4166 dev_err(hba->dev,
7eb584db
DR		 4167 "%s: power mode change failed %d\n", __func__, ret);
4168 } else {
bea8340e 4169 ufshcd_hold(hba, false);
8214b377 4170 ret = ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
0263bcd0 4171 pwr_mode);
bea8340e 4172 ufshcd_release(hba);
8214b377 4173 if (ret)
4174 goto out;
7eb584db
DR		 4175
4176 memcpy(&hba->pwr_info, pwr_mode,
4177 sizeof(struct ufs_pa_layer_attr));
4178 }
4179
4180 return ret;
4181}
4182
4183/**
4184 * ufshcd_config_pwr_mode - configure a new power mode
4185 * @hba: per-adapter instance
4186 * @desired_pwr_mode: desired power configuration
4187 */
623b5fe3 4188int ufshcd_config_pwr_mode(struct ufs_hba *hba,
7eb584db
DR		 4189 struct ufs_pa_layer_attr *desired_pwr_mode)
4190{
4191 struct ufs_pa_layer_attr final_params = { 0 };
4192 int ret;
4193
bea8340e 4194 ufshcd_hold(hba, false);
0263bcd0
YG		 4195 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4196 desired_pwr_mode, &final_params);
4197
8214b377 4198 if (ret) {
4199 if (ret == -ENOTSUPP)
4200 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4201 else
4202 goto out;
4203 }
7eb584db
DR		 4204
4205 ret = ufshcd_change_power_mode(hba, &final_params);
a3cd5ec5
SJ		 4206 if (!ret)
4207 ufshcd_print_pwr_info(hba);
8214b377 4208out:
bea8340e 4209 ufshcd_release(hba);
d3e89bac
SJ		 4210 return ret;
4211}
623b5fe3 4212EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
d3e89bac 4213
68078d5c
DR		 4214/**
4215 * ufshcd_complete_dev_init() - checks device readiness
4216 * hba: per-adapter instance
4217 *
4218 * Set fDeviceInit flag and poll until device toggles it.
4219 */
4220static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4221{
dc3c8d3a
YG		 4222 int i;
4223 int err;
68078d5c
DR		 4224 bool flag_res = 1;
4225
dc3c8d3a
YG		 4226 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4227 QUERY_FLAG_IDN_FDEVICEINIT, NULL);
68078d5c
DR		 4228 if (err) {
4229 dev_err(hba->dev,
4230 "%s setting fDeviceInit flag failed with error %d\n",
4231 __func__, err);
4232 goto out;
4233 }
4234
dc3c8d3a
YG		 4235 /* poll for max. 1000 iterations for fDeviceInit flag to clear */
4236 for (i = 0; i < 1000 && !err && flag_res; i++)
4237 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4238 QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
4239
68078d5c
DR		 4240 if (err)
4241 dev_err(hba->dev,
4242 "%s reading fDeviceInit flag failed with error %d\n",
4243 __func__, err);
4244 else if (flag_res)
4245 dev_err(hba->dev,
4246 "%s fDeviceInit was not cleared by the device\n",
4247 __func__);
4248
4249out:
4250 return err;
4251}
4252
7a3e97b0
SY		 4253/**
4254 * ufshcd_make_hba_operational - Make UFS controller operational
4255 * @hba: per adapter instance
4256 *
4257 * To bring UFS host controller to operational state,
5c0c28a8
SRT		 4258 * 1. Enable required interrupts
4259 * 2. Configure interrupt aggregation
897efe62 4260 * 3. Program UTRL and UTMRL base address
5c0c28a8 4261 * 4. Configure run-stop-registers
7a3e97b0
SY		 4262 *
4263 * Returns 0 on success, non-zero value on failure
4264 */
4265static int ufshcd_make_hba_operational(struct ufs_hba *hba)
4266{
4267 int err = 0;
4268 u32 reg;
4269
6ccf44fe
SJ		 4270 /* Enable required interrupts */
4271 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4272
4273 /* Configure interrupt aggregation */
b852190e
YG		 4274 if (ufshcd_is_intr_aggr_allowed(hba))
4275 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4276 else
4277 ufshcd_disable_intr_aggr(hba);
6ccf44fe
SJ		 4278
4279 /* Configure UTRL and UTMRL base address registers */
4280 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4281 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4282 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4283 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4284 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4285 REG_UTP_TASK_REQ_LIST_BASE_L);
4286 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4287 REG_UTP_TASK_REQ_LIST_BASE_H);
4288
897efe62
YG		 4289 /*
4290 * Make sure base address and interrupt setup are updated before
4291 * enabling the run/stop registers below.
4292 */
4293 wmb();
4294
7a3e97b0
SY		 4295 /*
4296 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
7a3e97b0 4297 */
5c0c28a8 4298 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
7a3e97b0
SY		 4299 if (!(ufshcd_get_lists_status(reg))) {
4300 ufshcd_enable_run_stop_reg(hba);
4301 } else {
3b1d0580 4302 dev_err(hba->dev,
7a3e97b0
SY		 4303 "Host controller not ready to process requests");
4304 err = -EIO;
4305 goto out;
4306 }
4307
7a3e97b0
SY		 4308out:
4309 return err;
4310}
4311
596585a2
YG		 4312/**
4313 * ufshcd_hba_stop - Send controller to reset state
4314 * @hba: per adapter instance
4315 * @can_sleep: perform sleep or just spin
4316 */
4317static inline void ufshcd_hba_stop(struct ufs_hba *hba, bool can_sleep)
4318{
4319 int err;
4320
4321 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4322 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4323 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4324 10, 1, can_sleep);
4325 if (err)
4326 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4327}
4328
7a3e97b0 4329/**
623b5fe3 4330 * _ufshcd_hba_enable - initialize the controller
7a3e97b0
SY		 4331 * @hba: per adapter instance
4332 *
4333 * The controller resets itself and controller firmware initialization
4334 * sequence kicks off. When controller is ready it will set
4335 * the Host Controller Enable bit to 1.
4336 *
4337 * Returns 0 on success, non-zero value on failure
4338 */
623b5fe3 4339static int __ufshcd_hba_enable(struct ufs_hba *hba)
7a3e97b0
SY		 4340{
4341 int retry;
4342
4343 /*
4344 * msleep of 1 and 5 used in this function might result in msleep(20),
4345 * but it was necessary to send the UFS FPGA to reset mode during
4346 * development and testing of this driver. msleep can be changed to
4347 * mdelay and retry count can be reduced based on the controller.
4348 */
596585a2 4349 if (!ufshcd_is_hba_active(hba))
7a3e97b0 4350 /* change controller state to "reset state" */
596585a2 4351 ufshcd_hba_stop(hba, true);
7a3e97b0 4352
57d104c1
SJ		 4353 /* UniPro link is disabled at this point */
4354 ufshcd_set_link_off(hba);
4355
0263bcd0 4356 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
5c0c28a8 4357
7a3e97b0
SY		 4358 /* start controller initialization sequence */
4359 ufshcd_hba_start(hba);
4360
4361 /*
4362 * To initialize a UFS host controller HCE bit must be set to 1.
4363 * During initialization the HCE bit value changes from 1->0->1.
4364 * When the host controller completes initialization sequence
4365 * it sets the value of HCE bit to 1. The same HCE bit is read back
4366 * to check if the controller has completed initialization sequence.
4367 * So without this delay the value HCE = 1, set in the previous
4368 * instruction might be read back.
4369 * This delay can be changed based on the controller.
4370 */
4371 msleep(1);
4372
4373 /* wait for the host controller to complete initialization */
4374 retry = 10;
4375 while (ufshcd_is_hba_active(hba)) {
4376 if (retry) {
4377 retry--;
4378 } else {
3b1d0580 4379 dev_err(hba->dev,
7a3e97b0
SY		 4380 "Controller enable failed\n");
4381 return -EIO;
4382 }
4383 msleep(5);
4384 }
5c0c28a8 4385
1d337ec2 4386 /* enable UIC related interrupts */
57d104c1 4387 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
1d337ec2 4388
0263bcd0 4389 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
5c0c28a8 4390
7a3e97b0
SY		 4391 return 0;
4392}
4393
7ca38cf3
YG		 4394static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4395{
4396 int tx_lanes, i, err = 0;
4397
4398 if (!peer)
4399 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4400 &tx_lanes);
4401 else
4402 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4403 &tx_lanes);
4404 for (i = 0; i < tx_lanes; i++) {
4405 if (!peer)
4406 err = ufshcd_dme_set(hba,
4407 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4408 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4409 0);
4410 else
4411 err = ufshcd_dme_peer_set(hba,
4412 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4413 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4414 0);
4415 if (err) {
4416 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4417 __func__, peer, i, err);
4418 break;
4419 }
4420 }
4421
4422 return err;
4423}
4424
4425static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4426{
4427 return ufshcd_disable_tx_lcc(hba, true);
4428}
4429
623b5fe3 4430static int ufshcd_hba_enable(struct ufs_hba *hba)
4431{
4432 int ret;
2bfd4b44 4433 unsigned long flags;
4434
bea8340e 4435 ufshcd_hold(hba, false);
4436
2bfd4b44 4437 spin_lock_irqsave(hba->host->host_lock, flags);
5801290e 4438 hba->ufshcd_state = UFSHCD_STATE_RESET;
2bfd4b44 4439 spin_unlock_irqrestore(hba->host->host_lock, flags);
4440
623b5fe3 4441 if (hba->vops && hba->vops->host_reset)
4442 hba->vops->host_reset(hba);
4443 if (hba->quirks & UFSHCD_QUIRK_USE_OF_HCE) {
5801290e 4444 ufshcd_set_link_off(hba);
623b5fe3 4445 /* enable UIC related interrupts */
4446 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4447
4448 ret = ufshcd_dme_reset(hba);
4449 if (!ret)
4450 ret = ufshcd_dme_enable(hba);
4451 } else {
4452 ret = __ufshcd_hba_enable(hba);
4453 }
bea8340e 4454 ufshcd_release(hba);
4455
251f4e5f 4456 if (ret)
4457 dev_err(hba->dev, "Host controller enable failed\n");
4458
623b5fe3 4459 return ret;
4460}
4461
7a3e97b0 4462/**
6ccf44fe 4463 * ufshcd_link_startup - Initialize unipro link startup
7a3e97b0
SY		 4464 * @hba: per adapter instance
4465 *
6ccf44fe 4466 * Returns 0 for success, non-zero in case of failure
7a3e97b0 4467 */
6ccf44fe 4468static int ufshcd_link_startup(struct ufs_hba *hba)
7a3e97b0 4469{
6ccf44fe 4470 int ret;
1d337ec2 4471 int retries = DME_LINKSTARTUP_RETRIES;
7caf489b 4472 bool link_startup_again = false;
7a3e97b0 4473
bea8340e 4474
4475 ufshcd_hold(hba, false);
4476
7caf489b
SJ		 4477 /*
4478 * If UFS device isn't active then we will have to issue link startup
4479 * 2 times to make sure the device state move to active.
4480 */
4481 if (!ufshcd_is_ufs_dev_active(hba))
4482 link_startup_again = true;
7a3e97b0 4483
7caf489b 4484link_startup:
1d337ec2 4485 do {
0263bcd0 4486 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
6ccf44fe 4487
1d337ec2 4488 ret = ufshcd_dme_link_startup(hba);
5c0c28a8 4489
1d337ec2
SRT		 4490 /* check if device is detected by inter-connect layer */
4491 if (!ret && !ufshcd_is_device_present(hba)) {
4492 dev_err(hba->dev, "%s: Device not present\n", __func__);
4493 ret = -ENXIO;
4494 goto out;
4495 }
6ccf44fe 4496
1d337ec2
SRT		 4497 /*
4498 * DME link lost indication is only received when link is up,
4499 * but we can't be sure if the link is up until link startup
4500 * succeeds. So reset the local Uni-Pro and try again.
4501 */
4502 if (ret && ufshcd_hba_enable(hba))
4503 goto out;
4504 } while (ret && retries--);
4505
4506 if (ret)
4507 /* failed to get the link up... retire */
5c0c28a8 4508 goto out;
5c0c28a8 4509
7caf489b
SJ		 4510 if (link_startup_again) {
4511 link_startup_again = false;
4512 retries = DME_LINKSTARTUP_RETRIES;
4513 goto link_startup;
4514 }
4515
d2aebb9b
SJ		 4516 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4517 ufshcd_init_pwr_info(hba);
4518 ufshcd_print_pwr_info(hba);
4519
7ca38cf3
YG		 4520 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4521 ret = ufshcd_disable_device_tx_lcc(hba);
4522 if (ret)
4523 goto out;
4524 }
4525
5c0c28a8 4526 /* Include any host controller configuration via UIC commands */
0263bcd0
YG		 4527 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4528 if (ret)
4529 goto out;
7a3e97b0 4530
5c0c28a8 4531 ret = ufshcd_make_hba_operational(hba);
6ccf44fe 4532out:
bea8340e 4533 ufshcd_release(hba);
4534
7942f7b5 4535 if (ret) {
6ccf44fe 4536 dev_err(hba->dev, "link startup failed %d\n", ret);
7942f7b5
VG		 4537 ufshcd_print_host_state(hba);
4538 ufshcd_print_pwr_info(hba);
4539 ufshcd_print_host_regs(hba);
4540 }
6ccf44fe 4541 return ret;
7a3e97b0
SY		 4542}
4543
5a0b0cb9
SRT		 4544/**
4545 * ufshcd_verify_dev_init() - Verify device initialization
4546 * @hba: per-adapter instance
4547 *
4548 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4549 * device Transport Protocol (UTP) layer is ready after a reset.
4550 * If the UTP layer at the device side is not initialized, it may
4551 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4552 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4553 */
4554static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4555{
4556 int err = 0;
4557 int retries;
4558
1ab27c9c 4559 ufshcd_hold(hba, false);
5a0b0cb9
SRT		 4560 mutex_lock(&hba->dev_cmd.lock);
4561 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4562 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4563 NOP_OUT_TIMEOUT);
4564
4565 if (!err || err == -ETIMEDOUT)
4566 break;
4567
4568 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4569 }
4570 mutex_unlock(&hba->dev_cmd.lock);
1ab27c9c 4571 ufshcd_release(hba);
5a0b0cb9
SRT		 4572
4573 if (err)
4574 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4575 return err;
4576}
4577
0ce147d4
SJ		 4578/**
4579 * ufshcd_set_queue_depth - set lun queue depth
4580 * @sdev: pointer to SCSI device
4581 *
4582 * Read bLUQueueDepth value and activate scsi tagged command
4583 * queueing. For WLUN, queue depth is set to 1. For best-effort
4584 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4585 * value that host can queue.
4586 */
4587static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4588{
4589 int ret = 0;
4590 u8 lun_qdepth;
4591 struct ufs_hba *hba;
4592
4593 hba = shost_priv(sdev->host);
4594
4595 lun_qdepth = hba->nutrs;
dbd34a61
SM		 4596 ret = ufshcd_read_unit_desc_param(hba,
4597 ufshcd_scsi_to_upiu_lun(sdev->lun),
4598 UNIT_DESC_PARAM_LU_Q_DEPTH,
4599 &lun_qdepth,
4600 sizeof(lun_qdepth));
0ce147d4
SJ		 4601
4602 /* Some WLUN doesn't support unit descriptor */
4603 if (ret == -EOPNOTSUPP)
4604 lun_qdepth = 1;
4605 else if (!lun_qdepth)
4606 /* eventually, we can figure out the real queue depth */
4607 lun_qdepth = hba->nutrs;
4608 else
4609 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4610
4611 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4612 __func__, lun_qdepth);
db5ed4df 4613 scsi_change_queue_depth(sdev, lun_qdepth);
0ce147d4
SJ		 4614}
4615
57d104c1
SJ		 4616/*
4617 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4618 * @hba: per-adapter instance
4619 * @lun: UFS device lun id
4620 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4621 *
4622 * Returns 0 in case of success and b_lu_write_protect status would be returned
4623 * @b_lu_write_protect parameter.
4624 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4625 * Returns -EINVAL in case of invalid parameters passed to this function.
4626 */
4627static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4628 u8 lun,
4629 u8 *b_lu_write_protect)
4630{
4631 int ret;
4632
4633 if (!b_lu_write_protect)
4634 ret = -EINVAL;
4635 /*
4636 * According to UFS device spec, RPMB LU can't be write
4637 * protected so skip reading bLUWriteProtect parameter for
4638 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4639 */
4640 else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
4641 ret = -ENOTSUPP;
4642 else
4643 ret = ufshcd_read_unit_desc_param(hba,
4644 lun,
4645 UNIT_DESC_PARAM_LU_WR_PROTECT,
4646 b_lu_write_protect,
4647 sizeof(*b_lu_write_protect));
4648 return ret;
4649}
4650
4651/**
4652 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4653 * status
4654 * @hba: per-adapter instance
4655 * @sdev: pointer to SCSI device
4656 *
4657 */
4658static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4659 struct scsi_device *sdev)
4660{
4661 if (hba->dev_info.f_power_on_wp_en &&
4662 !hba->dev_info.is_lu_power_on_wp) {
4663 u8 b_lu_write_protect;
4664
4665 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4666 &b_lu_write_protect) &&
4667 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4668 hba->dev_info.is_lu_power_on_wp = true;
4669 }
4670}
4671
a782a88e 4672static void ufshcd_done(struct request *rq)
4673{
4674 struct scsi_cmnd *cmd = rq->special;
4675 scsi_dma_unmap(cmd);
4676 scsi_softirq_done(rq);
4677}
4678
7a3e97b0
SY		 4679/**
4680 * ufshcd_slave_alloc - handle initial SCSI device configurations
4681 * @sdev: pointer to SCSI device
4682 *
4683 * Returns success
4684 */
4685static int ufshcd_slave_alloc(struct scsi_device *sdev)
4686{
4687 struct ufs_hba *hba;
4688
4689 hba = shost_priv(sdev->host);
7a3e97b0
SY		 4690
4691 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4692 sdev->use_10_for_ms = 1;
7a3e97b0 4693
e8e7f271
SRT		 4694 /* allow SCSI layer to restart the device in case of errors */
4695 sdev->allow_restart = 1;
4264fd61 4696
b2a6c522
SRT		 4697 /* REPORT SUPPORTED OPERATION CODES is not supported */
4698 sdev->no_report_opcodes = 1;
4699
e8e7f271 4700
0ce147d4 4701 ufshcd_set_queue_depth(sdev);
4264fd61 4702
57d104c1
SJ		 4703 ufshcd_get_lu_power_on_wp_status(hba, sdev);
4704
a782a88e 4705 blk_queue_softirq_done(sdev->request_queue, ufshcd_done);
4706
61601236 4707 blk_queue_update_dma_alignment(sdev->request_queue, PAGE_SIZE - 1);
4708
7a3e97b0
SY		 4709 return 0;
4710}
4711
4264fd61
SRT		 4712/**
4713 * ufshcd_change_queue_depth - change queue depth
4714 * @sdev: pointer to SCSI device
4715 * @depth: required depth to set
4264fd61 4716 *
db5ed4df 4717 * Change queue depth and make sure the max. limits are not crossed.
4264fd61 4718 */
db5ed4df 4719static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
4264fd61
SRT		 4720{
4721 struct ufs_hba *hba = shost_priv(sdev->host);
4722
4723 if (depth > hba->nutrs)
4724 depth = hba->nutrs;
db5ed4df 4725 return scsi_change_queue_depth(sdev, depth);
4264fd61
SRT		 4726}
4727
eeda4749
AM		 4728/**
4729 * ufshcd_slave_configure - adjust SCSI device configurations
4730 * @sdev: pointer to SCSI device
4731 */
4732static int ufshcd_slave_configure(struct scsi_device *sdev)
4733{
4734 struct request_queue *q = sdev->request_queue;
4735
4736 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
4737 blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
623b5fe3 4738 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
eeda4749
AM		 4739
4740 return 0;
4741}
4742
7a3e97b0
SY		 4743/**
4744 * ufshcd_slave_destroy - remove SCSI device configurations
4745 * @sdev: pointer to SCSI device
4746 */
4747static void ufshcd_slave_destroy(struct scsi_device *sdev)
4748{
4749 struct ufs_hba *hba;
4750
4751 hba = shost_priv(sdev->host);
0ce147d4 4752 /* Drop the reference as it won't be needed anymore */
7c48bfd0
AM		 4753 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
4754 unsigned long flags;
4755
4756 spin_lock_irqsave(hba->host->host_lock, flags);
0ce147d4 4757 hba->sdev_ufs_device = NULL;
7c48bfd0
AM		 4758 spin_unlock_irqrestore(hba->host->host_lock, flags);
4759 }
7a3e97b0
SY		 4760}
4761
4762/**
4763 * ufshcd_task_req_compl - handle task management request completion
4764 * @hba: per adapter instance
4765 * @index: index of the completed request
e2933132 4766 * @resp: task management service response
7a3e97b0 4767 *
e2933132 4768 * Returns non-zero value on error, zero on success
7a3e97b0 4769 */
e2933132 4770static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
7a3e97b0
SY		 4771{
4772 struct utp_task_req_desc *task_req_descp;
4773 struct utp_upiu_task_rsp *task_rsp_upiup;
4774 unsigned long flags;
4775 int ocs_value;
4776 int task_result;
4777
4778 spin_lock_irqsave(hba->host->host_lock, flags);
4779
7a3e97b0
SY		 4780 task_req_descp = hba->utmrdl_base_addr;
4781 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
4782
4783 if (ocs_value == OCS_SUCCESS) {
4784 task_rsp_upiup = (struct utp_upiu_task_rsp *)
4785 task_req_descp[index].task_rsp_upiu;
8794ee0c
KK		 4786 task_result = be32_to_cpu(task_rsp_upiup->output_param1);
4787 task_result = task_result & MASK_TM_SERVICE_RESP;
e2933132
SRT		 4788 if (resp)
4789 *resp = (u8)task_result;
7a3e97b0 4790 } else {
e2933132
SRT		 4791 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
4792 __func__, ocs_value);
7a3e97b0
SY		 4793 }
4794 spin_unlock_irqrestore(hba->host->host_lock, flags);
e2933132
SRT		 4795
4796 return ocs_value;
7a3e97b0
SY		 4797}
4798
7a3e97b0
SY		 4799/**
4800 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
4801 * @lrb: pointer to local reference block of completed command
4802 * @scsi_status: SCSI command status
4803 *
4804 * Returns value base on SCSI command status
4805 */
4806static inline int
4807ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
4808{
4809 int result = 0;
4810
4811 switch (scsi_status) {
7a3e97b0 4812 case SAM_STAT_CHECK_CONDITION:
1c2623c5
SJ		 4813 ufshcd_copy_sense_data(lrbp);
4814 case SAM_STAT_GOOD:
7a3e97b0
SY		 4815 result |= DID_OK << 16 |
4816 COMMAND_COMPLETE << 8 |
1c2623c5 4817 scsi_status;
7a3e97b0
SY		 4818 break;
4819 case SAM_STAT_TASK_SET_FULL:
1c2623c5 4820 case SAM_STAT_BUSY:
7a3e97b0 4821 case SAM_STAT_TASK_ABORTED:
1c2623c5
SJ		 4822 ufshcd_copy_sense_data(lrbp);
4823 result |= scsi_status;
7a3e97b0
SY		 4824 break;
4825 default:
4826 result |= DID_ERROR << 16;
4827 break;
4828 } /* end of switch */
4829
4830 return result;
4831}
4832
4833/**
4834 * ufshcd_transfer_rsp_status - Get overall status of the response
4835 * @hba: per adapter instance
4836 * @lrb: pointer to local reference block of completed command
4837 *
4838 * Returns result of the command to notify SCSI midlayer
4839 */
4840static inline int
4841ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
4842{
4843 int result = 0;
4844 int scsi_status;
4845 int ocs;
4846
4847 /* overall command status of utrd */
4848 ocs = ufshcd_get_tr_ocs(lrbp);
4849
4850 switch (ocs) {
4851 case OCS_SUCCESS:
623b5fe3 4852 case OCS_FATAL_ERROR:
5a0b0cb9 4853 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
ff8e20c6 4854 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5a0b0cb9
SRT		 4855 switch (result) {
4856 case UPIU_TRANSACTION_RESPONSE:
4857 /*
4858 * get the response UPIU result to extract
4859 * the SCSI command status
4860 */
4861 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
4862
4863 /*
4864 * get the result based on SCSI status response
4865 * to notify the SCSI midlayer of the command status
4866 */
4867 scsi_status = result & MASK_SCSI_STATUS;
4868 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
66ec6d59 4869
f05ac2e5
YG		 4870 /*
4871 * Currently we are only supporting BKOPs exception
4872 * events hence we can ignore BKOPs exception event
4873 * during power management callbacks. BKOPs exception
4874 * event is not expected to be raised in runtime suspend
4875 * callback as it allows the urgent bkops.
4876 * During system suspend, we are anyway forcefully
4877 * disabling the bkops and if urgent bkops is needed
4878 * it will be enabled on system resume. Long term
4879 * solution could be to abort the system suspend if
4880 * UFS device needs urgent BKOPs.
4881 */
4882 if (!hba->pm_op_in_progress &&
abebc6eb 4883 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr) &&
4884 scsi_host_in_recovery(hba->host)) {
66ec6d59 4885 schedule_work(&hba->eeh_work);
cf632748 4886 dev_info(hba->dev, "execption event reported\n");
4887 }
4888
5a0b0cb9
SRT		 4889 break;
4890 case UPIU_TRANSACTION_REJECT_UPIU:
4891 /* TODO: handle Reject UPIU Response */
4892 result = DID_ERROR << 16;
3b1d0580 4893 dev_err(hba->dev,
5a0b0cb9
SRT		 4894 "Reject UPIU not fully implemented\n");
4895 break;
4896 default:
4897 result = DID_ERROR << 16;
4898 dev_err(hba->dev,
4899 "Unexpected request response code = %x\n",
4900 result);
7a3e97b0
SY		 4901 break;
4902 }
7a3e97b0
SY		 4903 break;
4904 case OCS_ABORTED:
4905 result |= DID_ABORT << 16;
4906 break;
e8e7f271
SRT		 4907 case OCS_INVALID_COMMAND_STATUS:
4908 result |= DID_REQUEUE << 16;
4909 break;
7a3e97b0
SY		 4910 case OCS_INVALID_CMD_TABLE_ATTR:
4911 case OCS_INVALID_PRDT_ATTR:
4912 case OCS_MISMATCH_DATA_BUF_SIZE:
4913 case OCS_MISMATCH_RESP_UPIU_SIZE:
4914 case OCS_PEER_COMM_FAILURE:
7a3e97b0
SY		 4915 default:
4916 result |= DID_ERROR << 16;
3b1d0580 4917 dev_err(hba->dev,
ff8e20c6
DR		 4918 "OCS error from controller = %x for tag %d\n",
4919 ocs, lrbp->task_tag);
4920 ufshcd_print_host_regs(hba);
6ba65588 4921 ufshcd_print_host_state(hba);
7a3e97b0
SY		 4922 break;
4923 } /* end of switch */
4924
66cc820f
DR		 4925 if (host_byte(result) != DID_OK)
4926 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
7a3e97b0
SY		 4927 return result;
4928}
4929
6ccf44fe
SJ		 4930/**
4931 * ufshcd_uic_cmd_compl - handle completion of uic command
4932 * @hba: per adapter instance
53b3d9c3 4933 * @intr_status: interrupt status generated by the controller
6ccf44fe 4934 */
53b3d9c3 4935static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
6ccf44fe 4936{
53b3d9c3 4937 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
6ccf44fe
SJ		 4938 hba->active_uic_cmd->argument2 |=
4939 ufshcd_get_uic_cmd_result(hba);
12b4fdb4
SJ		 4940 hba->active_uic_cmd->argument3 =
4941 ufshcd_get_dme_attr_val(hba);
6ccf44fe
SJ		 4942 complete(&hba->active_uic_cmd->done);
4943 }
53b3d9c3 4944
57d104c1
SJ		 4945 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
4946 complete(hba->uic_async_done);
6ccf44fe
SJ		 4947}
4948
7a3e97b0 4949/**
9a47ec7c 4950 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
7a3e97b0 4951 * @hba: per adapter instance
9a47ec7c 4952 * @completed_reqs: requests to complete
7a3e97b0 4953 */
5bb4e709 4954static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, int reason,
9a47ec7c 4955 unsigned long completed_reqs)
7a3e97b0 4956{
5a0b0cb9
SRT		 4957 struct ufshcd_lrb *lrbp;
4958 struct scsi_cmnd *cmd;
7a3e97b0
SY		 4959 int result;
4960 int index;
e9d501b1 4961
e9d501b1
DR		 4962 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
4963 lrbp = &hba->lrb[index];
4964 cmd = lrbp->cmd;
4965 if (cmd) {
1a07f2d9 4966 ufshcd_add_command_trace(hba, index, "complete");
e9d501b1 4967 result = ufshcd_transfer_rsp_status(hba, lrbp);
e9d501b1 4968 cmd->result = result;
5bb4e709 4969 if (reason)
4970 set_host_byte(cmd, reason);
e9d501b1
DR		 4971 /* Mark completed command as NULL in LRB */
4972 lrbp->cmd = NULL;
4973 clear_bit_unlock(index, &hba->lrb_in_use);
4974 /* Do not touch lrbp after scsi done */
4975 cmd->scsi_done(cmd);
2ea8cc4d 4976#ifdef CONFIG_SCSI_UFS_CMD_LOGGING
4977 exynos_ufs_cmd_log_end(hba, index);
4978#endif
1ab27c9c 4979 __ufshcd_release(hba);
9632ac5f 4980 if (hba->monitor.flag & UFSHCD_MONITOR_LEVEL1)
4981 dev_info(hba->dev, "Transfer Done(%d)\n",
4982 index);
4983
300bb13f
JP		 4984 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
4985 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
1a07f2d9
LS		 4986 if (hba->dev_cmd.complete) {
4987 ufshcd_add_command_trace(hba, index,
4988 "dev_complete");
e9d501b1 4989 complete(hba->dev_cmd.complete);
1a07f2d9 4990 }
e9d501b1 4991 }
401f1e44
SJ		 4992 if (ufshcd_is_clkscaling_supported(hba))
4993 hba->clk_scaling.active_reqs--;
e9d501b1 4994 }
7a3e97b0
SY		 4995
4996 /* clear corresponding bits of completed commands */
4997 hba->outstanding_reqs ^= completed_reqs;
b393aa4d 4998#if defined(CONFIG_PM_DEVFREQ)
856b3483 4999 ufshcd_clk_scaling_update_busy(hba);
b393aa4d 5000#endif
5a0b0cb9
SRT		 5001 /* we might have free'd some tags above */
5002 wake_up(&hba->dev_cmd.tag_wq);
7a3e97b0
SY		 5003}
5004
9a47ec7c
YG		 5005/**
5006 * ufshcd_transfer_req_compl - handle SCSI and query command completion
5007 * @hba: per adapter instance
5008 */
5009static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
5010{
5011 unsigned long completed_reqs;
5012 u32 tr_doorbell;
5013
5014 /* Resetting interrupt aggregation counters first and reading the
5015 * DOOR_BELL afterward allows us to handle all the completed requests.
5016 * In order to prevent other interrupts starvation the DB is read once
5017 * after reset. The down side of this solution is the possibility of
5018 * false interrupt if device completes another request after resetting
5019 * aggregation and before reading the DB.
5020 */
7e1cdfbd 5021 if (!ufshcd_can_reset_intr_aggr(hba) && ufshcd_is_intr_aggr_allowed(hba))
9a47ec7c
YG		 5022 ufshcd_reset_intr_aggr(hba);
5023
5024 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5025 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
5026
5027 __ufshcd_transfer_req_compl(hba, completed_reqs);
5028}
5029
66ec6d59
SRT		 5030/**
5031 * ufshcd_disable_ee - disable exception event
5032 * @hba: per-adapter instance
5033 * @mask: exception event to disable
5034 *
5035 * Disables exception event in the device so that the EVENT_ALERT
5036 * bit is not set.
5037 *
5038 * Returns zero on success, non-zero error value on failure.
5039 */
5040static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5041{
5042 int err = 0;
5043 u32 val;
5044
5045 if (!(hba->ee_ctrl_mask & mask))
5046 goto out;
5047
5048 val = hba->ee_ctrl_mask & ~mask;
d7e2ddd5 5049 val &= MASK_EE_STATUS;
5e86ae44 5050 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 5051 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
5052 if (!err)
5053 hba->ee_ctrl_mask &= ~mask;
5054out:
5055 return err;
5056}
5057
5058/**
5059 * ufshcd_enable_ee - enable exception event
5060 * @hba: per-adapter instance
5061 * @mask: exception event to enable
5062 *
5063 * Enable corresponding exception event in the device to allow
5064 * device to alert host in critical scenarios.
5065 *
5066 * Returns zero on success, non-zero error value on failure.
5067 */
5068static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5069{
5070 int err = 0;
5071 u32 val;
5072
5073 if (hba->ee_ctrl_mask & mask)
5074 goto out;
5075
5076 val = hba->ee_ctrl_mask | mask;
d7e2ddd5 5077 val &= MASK_EE_STATUS;
5e86ae44 5078 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
66ec6d59
SRT		 5079 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
5080 if (!err)
5081 hba->ee_ctrl_mask |= mask;
5082out:
5083 return err;
5084}
5085
5086/**
5087 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5088 * @hba: per-adapter instance
5089 *
5090 * Allow device to manage background operations on its own. Enabling
5091 * this might lead to inconsistent latencies during normal data transfers
5092 * as the device is allowed to manage its own way of handling background
5093 * operations.
5094 *
5095 * Returns zero on success, non-zero on failure.
5096 */
5097static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5098{
5099 int err = 0;
5100
5101 if (hba->auto_bkops_enabled)
5102 goto out;
5103
dc3c8d3a 5104 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
66ec6d59
SRT		 5105 QUERY_FLAG_IDN_BKOPS_EN, NULL);
5106 if (err) {
5107 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5108 __func__, err);
5109 goto out;
5110 }
5111
5112 hba->auto_bkops_enabled = true;
7ff5ab47 5113 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
66ec6d59
SRT		 5114
5115 /* No need of URGENT_BKOPS exception from the device */
5116 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5117 if (err)
5118 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5119 __func__, err);
5120out:
5121 return err;
5122}
5123
5124/**
5125 * ufshcd_disable_auto_bkops - block device in doing background operations
5126 * @hba: per-adapter instance
5127 *
5128 * Disabling background operations improves command response latency but
5129 * has drawback of device moving into critical state where the device is
5130 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5131 * host is idle so that BKOPS are managed effectively without any negative
5132 * impacts.
5133 *
5134 * Returns zero on success, non-zero on failure.
5135 */
5136static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5137{
5138 int err = 0;
5139
5140 if (!hba->auto_bkops_enabled)
5141 goto out;
5142
5143 /*
5144 * If host assisted BKOPs is to be enabled, make sure
5145 * urgent bkops exception is allowed.
5146 */
5147 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5148 if (err) {
5149 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5150 __func__, err);
5151 goto out;
5152 }
5153
dc3c8d3a 5154 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
66ec6d59
SRT		 5155 QUERY_FLAG_IDN_BKOPS_EN, NULL);
5156 if (err) {
5157 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5158 __func__, err);
5159 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5160 goto out;
5161 }
5162
5163 hba->auto_bkops_enabled = false;
7ff5ab47 5164 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
66ec6d59
SRT		 5165out:
5166 return err;
5167}
5168
5169/**
4e768e76 5170 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
66ec6d59
SRT		 5171 * @hba: per adapter instance
5172 *
5173 * After a device reset the device may toggle the BKOPS_EN flag
5174 * to default value. The s/w tracking variables should be updated
4e768e76
SJ		 5175 * as well. This function would change the auto-bkops state based on
5176 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
66ec6d59 5177 */
4e768e76 5178static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
66ec6d59 5179{
4e768e76
SJ		 5180 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5181 hba->auto_bkops_enabled = false;
5182 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5183 ufshcd_enable_auto_bkops(hba);
5184 } else {
5185 hba->auto_bkops_enabled = true;
5186 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5187 ufshcd_disable_auto_bkops(hba);
5188 }
66ec6d59
SRT		 5189}
5190
5191static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5192{
5e86ae44 5193 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5194 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5195}
5196
5197/**
57d104c1 5198 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
66ec6d59 5199 * @hba: per-adapter instance
57d104c1 5200 * @status: bkops_status value
66ec6d59 5201 *
57d104c1
SJ		 5202 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5203 * flag in the device to permit background operations if the device
5204 * bkops_status is greater than or equal to "status" argument passed to
5205 * this function, disable otherwise.
5206 *
5207 * Returns 0 for success, non-zero in case of failure.
5208 *
5209 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5210 * to know whether auto bkops is enabled or disabled after this function
5211 * returns control to it.
66ec6d59 5212 */
57d104c1
SJ		 5213static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5214 enum bkops_status status)
66ec6d59
SRT		 5215{
5216 int err;
57d104c1 5217 u32 curr_status = 0;
66ec6d59 5218
57d104c1 5219 err = ufshcd_get_bkops_status(hba, &curr_status);
66ec6d59
SRT		 5220 if (err) {
5221 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5222 __func__, err);
5223 goto out;
57d104c1
SJ		 5224 } else if (curr_status > BKOPS_STATUS_MAX) {
5225 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5226 __func__, curr_status);
5227 err = -EINVAL;
5228 goto out;
66ec6d59
SRT		 5229 }
5230
cf632748 5231 if (curr_status >= status) {
66ec6d59 5232 err = ufshcd_enable_auto_bkops(hba);
cf632748 5233 if (!err)
5234 dev_info(hba->dev, "%s: auto_bkops enabled, status : %d\n",
5235 __func__, curr_status);
5236 }
57d104c1
SJ		 5237 else
5238 err = ufshcd_disable_auto_bkops(hba);
66ec6d59
SRT		 5239out:
5240 return err;
5241}
5242
57d104c1
SJ		 5243/**
5244 * ufshcd_urgent_bkops - handle urgent bkops exception event
5245 * @hba: per-adapter instance
5246 *
5247 * Enable fBackgroundOpsEn flag in the device to permit background
5248 * operations.
5249 *
5250 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5251 * and negative error value for any other failure.
5252 */
5253static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5254{
afdfff59 5255 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
57d104c1
SJ		 5256}
5257
66ec6d59
SRT		 5258static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5259{
5e86ae44 5260 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
66ec6d59
SRT		 5261 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5262}
5263
afdfff59
YG		 5264static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5265{
5266 int err;
5267 u32 curr_status = 0;
5268
5269 if (hba->is_urgent_bkops_lvl_checked)
5270 goto enable_auto_bkops;
5271
5272 err = ufshcd_get_bkops_status(hba, &curr_status);
5273 if (err) {
5274 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5275 __func__, err);
5276 goto out;
5277 }
5278
5279 /*
5280 * We are seeing that some devices are raising the urgent bkops
5281 * exception events even when BKOPS status doesn't indicate performace
5282 * impacted or critical. Handle these device by determining their urgent
5283 * bkops status at runtime.
5284 */
5285 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5286 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5287 __func__, curr_status);
5288 /* update the current status as the urgent bkops level */
5289 hba->urgent_bkops_lvl = curr_status;
5290 hba->is_urgent_bkops_lvl_checked = true;
5291 }
5292
5293enable_auto_bkops:
5294 err = ufshcd_enable_auto_bkops(hba);
5295out:
5296 if (err < 0)
5297 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5298 __func__, err);
5299}
5300
66ec6d59
SRT		 5301/**
5302 * ufshcd_exception_event_handler - handle exceptions raised by device
5303 * @work: pointer to work data
5304 *
5305 * Read bExceptionEventStatus attribute from the device and handle the
5306 * exception event accordingly.
5307 */
5308static void ufshcd_exception_event_handler(struct work_struct *work)
5309{
5310 struct ufs_hba *hba;
5311 int err;
5312 u32 status = 0;
5313 hba = container_of(work, struct ufs_hba, eeh_work);
5314
62694735 5315 pm_runtime_get_sync(hba->dev);
66ec6d59
SRT		 5316 err = ufshcd_get_ee_status(hba, &status);
5317 if (err) {
5318 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5319 __func__, err);
5320 goto out;
5321 }
5322
5323 status &= hba->ee_ctrl_mask;
afdfff59
YG		 5324
5325 if (status & MASK_EE_URGENT_BKOPS)
5326 ufshcd_bkops_exception_event_handler(hba);
5327
66ec6d59 5328out:
62694735 5329 pm_runtime_put_sync(hba->dev);
66ec6d59
SRT		 5330 return;
5331}
5332
9a47ec7c
YG		 5333/* Complete requests that have door-bell cleared */
5334static void ufshcd_complete_requests(struct ufs_hba *hba)
5335{
5336 ufshcd_transfer_req_compl(hba);
5337 ufshcd_tmc_handler(hba);
5338}
5339
583fa62d
YG		 5340/**
5341 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5342 * to recover from the DL NAC errors or not.
5343 * @hba: per-adapter instance
5344 *
5345 * Returns true if error handling is required, false otherwise
5346 */
5347static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5348{
5349 unsigned long flags;
5350 bool err_handling = true;
5351
5352 spin_lock_irqsave(hba->host->host_lock, flags);
5353 /*
5354 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5355 * device fatal error and/or DL NAC & REPLAY timeout errors.
5356 */
5357 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5358 goto out;
5359
5360 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5361 ((hba->saved_err & UIC_ERROR) &&
5362 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5363 goto out;
5364
5365 if ((hba->saved_err & UIC_ERROR) &&
5366 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5367 int err;
5368 /*
5369 * wait for 50ms to see if we can get any other errors or not.
5370 */
5371 spin_unlock_irqrestore(hba->host->host_lock, flags);
5372 msleep(50);
5373 spin_lock_irqsave(hba->host->host_lock, flags);
5374
5375 /*
5376 * now check if we have got any other severe errors other than
5377 * DL NAC error?
5378 */
5379 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5380 ((hba->saved_err & UIC_ERROR) &&
5381 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
5382 goto out;
5383
5384 /*
5385 * As DL NAC is the only error received so far, send out NOP
5386 * command to confirm if link is still active or not.
5387 * - If we don't get any response then do error recovery.
5388 * - If we get response then clear the DL NAC error bit.
5389 */
5390
5391 spin_unlock_irqrestore(hba->host->host_lock, flags);
5392 err = ufshcd_verify_dev_init(hba);
5393 spin_lock_irqsave(hba->host->host_lock, flags);
5394
5395 if (err)
5396 goto out;
5397
5398 /* Link seems to be alive hence ignore the DL NAC errors */
5399 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
5400 hba->saved_err &= ~UIC_ERROR;
5401 /* clear NAC error */
5402 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5403 if (!hba->saved_uic_err) {
5404 err_handling = false;
5405 goto out;
5406 }
5407 }
5408out:
5409 spin_unlock_irqrestore(hba->host->host_lock, flags);
5410 return err_handling;
5411}
5412
7a3e97b0 5413/**
e8e7f271
SRT		 5414 * ufshcd_err_handler - handle UFS errors that require s/w attention
5415 * @work: pointer to work structure
7a3e97b0 5416 */
e8e7f271 5417static void ufshcd_err_handler(struct work_struct *work)
7a3e97b0
SY		 5418{
5419 struct ufs_hba *hba;
e8e7f271
SRT		 5420 unsigned long flags;
5421 u32 err_xfer = 0;
5422 u32 err_tm = 0;
5423 int err = 0;
5424 int tag;
9a47ec7c 5425 bool needs_reset = false;
e8e7f271
SRT		 5426
5427 hba = container_of(work, struct ufs_hba, eh_work);
7a3e97b0 5428
62694735 5429 pm_runtime_get_sync(hba->dev);
1ab27c9c 5430 ufshcd_hold(hba, false);
e8e7f271 5431
aee9809c 5432 /* Dump debugging information to system memory */
5433 ufshcd_vops_dbg_register_dump(hba);
e8e7f271 5434 spin_lock_irqsave(hba->host->host_lock, flags);
9a47ec7c 5435 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
e8e7f271 5436 goto out;
e8e7f271
SRT		 5437
5438 hba->ufshcd_state = UFSHCD_STATE_RESET;
5439 ufshcd_set_eh_in_progress(hba);
cf632748 5440 exynos_ufs_show_uic_info(hba);
e8e7f271
SRT		 5441
5442 /* Complete requests that have door-bell cleared by h/w */
9a47ec7c 5443 ufshcd_complete_requests(hba);
583fa62d
YG		 5444
5445 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5446 bool ret;
5447
5448 spin_unlock_irqrestore(hba->host->host_lock, flags);
5449 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
5450 ret = ufshcd_quirk_dl_nac_errors(hba);
5451 spin_lock_irqsave(hba->host->host_lock, flags);
5452 if (!ret)
5453 goto skip_err_handling;
5454 }
9a47ec7c
YG		 5455 if ((hba->saved_err & INT_FATAL_ERRORS) ||
5456 ((hba->saved_err & UIC_ERROR) &&
5457 (hba->saved_uic_err & (UFSHCD_UIC_DL_PA_INIT_ERROR |
5458 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
5459 UFSHCD_UIC_DL_TCx_REPLAY_ERROR))))
5460 needs_reset = true;
e8e7f271 5461
9a47ec7c
YG		 5462 /*
5463 * if host reset is required then skip clearing the pending
5464 * transfers forcefully because they will automatically get
5465 * cleared after link startup.
5466 */
5467 if (needs_reset)
5468 goto skip_pending_xfer_clear;
5469
5470 /* release lock as clear command might sleep */
5471 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5472 /* Clear pending transfer requests */
9a47ec7c
YG		 5473 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
5474 if (ufshcd_clear_cmd(hba, tag)) {
5475 err_xfer = true;
5476 goto lock_skip_pending_xfer_clear;
5477 }
5478 }
e8e7f271
SRT		 5479
5480 /* Clear pending task management requests */
9a47ec7c
YG		 5481 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
5482 if (ufshcd_clear_tm_cmd(hba, tag)) {
5483 err_tm = true;
5484 goto lock_skip_pending_xfer_clear;
5485 }
5486 }
e8e7f271 5487
9a47ec7c 5488lock_skip_pending_xfer_clear:
e8e7f271 5489 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5490
9a47ec7c
YG		 5491 /* Complete the requests that are cleared by s/w */
5492 ufshcd_complete_requests(hba);
5493
5494 if (err_xfer || err_tm)
5495 needs_reset = true;
5496
5497skip_pending_xfer_clear:
e8e7f271 5498 /* Fatal errors need reset */
9a47ec7c
YG		 5499 if (needs_reset) {
5500 unsigned long max_doorbells = (1UL << hba->nutrs) - 1;
5501
5502 /*
5503 * ufshcd_reset_and_restore() does the link reinitialization
5504 * which will need atleast one empty doorbell slot to send the
5505 * device management commands (NOP and query commands).
5506 * If there is no slot empty at this moment then free up last
5507 * slot forcefully.
5508 */
5509 if (hba->outstanding_reqs == max_doorbells)
5510 __ufshcd_transfer_req_compl(hba,
5511 (1UL << (hba->nutrs - 1)));
5512
5513 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5514 err = ufshcd_reset_and_restore(hba);
9a47ec7c 5515 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 5516 if (err) {
2bfd4b44 5517 spin_lock_irqsave(hba->host->host_lock, flags);
5518 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5519 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271
SRT		 5520 dev_err(hba->dev, "%s: reset and restore failed\n",
5521 __func__);
5522 hba->ufshcd_state = UFSHCD_STATE_ERROR;
5523 }
e8e7f271
SRT		 5524 hba->saved_err = 0;
5525 hba->saved_uic_err = 0;
5526 }
9a47ec7c 5527
583fa62d 5528skip_err_handling:
9a47ec7c
YG		 5529 if (!needs_reset) {
5530 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
5531 if (hba->saved_err || hba->saved_uic_err)
5532 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
5533 __func__, hba->saved_err, hba->saved_uic_err);
5534 }
5535
e8e7f271
SRT		 5536 ufshcd_clear_eh_in_progress(hba);
5537
5538out:
9a47ec7c 5539 spin_unlock_irqrestore(hba->host->host_lock, flags);
e8e7f271 5540 scsi_unblock_requests(hba->host);
1ab27c9c 5541 ufshcd_release(hba);
62694735 5542 pm_runtime_put_sync(hba->dev);
7a3e97b0
SY		 5543}
5544
ff8e20c6
DR		 5545static void ufshcd_update_uic_reg_hist(struct ufs_uic_err_reg_hist *reg_hist,
5546 u32 reg)
5547{
5548 reg_hist->reg[reg_hist->pos] = reg;
5549 reg_hist->tstamp[reg_hist->pos] = ktime_get();
5550 reg_hist->pos = (reg_hist->pos + 1) % UIC_ERR_REG_HIST_LENGTH;
5551}
5552
7a3e97b0 5553/**
e8e7f271
SRT		 5554 * ufshcd_update_uic_error - check and set fatal UIC error flags.
5555 * @hba: per-adapter instance
7a3e97b0 5556 */
e8e7f271 5557static void ufshcd_update_uic_error(struct ufs_hba *hba)
7a3e97b0
SY		 5558{
5559 u32 reg;
5560
fb7b45f0
DR		 5561 /* PHY layer lane error */
5562 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5563 /* Ignore LINERESET indication, as this is not an error */
5564 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
ff8e20c6 5565 (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)) {
fb7b45f0
DR		 5566 /*
5567 * To know whether this error is fatal or not, DB timeout
5568 * must be checked but this error is handled separately.
5569 */
5570 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", __func__);
ff8e20c6
DR		 5571 ufshcd_update_uic_reg_hist(&hba->ufs_stats.pa_err, reg);
5572 }
fb7b45f0 5573
e8e7f271
SRT		 5574 /* PA_INIT_ERROR is fatal and needs UIC reset */
5575 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
ff8e20c6
DR		 5576 if (reg)
5577 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dl_err, reg);
5578
e8e7f271
SRT		 5579 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
5580 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
583fa62d
YG		 5581 else if (hba->dev_quirks &
5582 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
5583 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
5584 hba->uic_error |=
5585 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
5586 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
5587 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
5588 }
e8e7f271 5589
a60d7ef4 5590 if (reg & UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP)
5591 hba->tcx_replay_timer_expired_cnt++;
5592
5593 if (reg & UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP)
5594 hba->fcx_protection_timer_expired_cnt++;
5595
5596 if (hba->tcx_replay_timer_expired_cnt >= 2 ||
5597 hba->fcx_protection_timer_expired_cnt >= 2)
5598 hba->uic_error |= UFSHCD_UIC_DL_ERROR;
5599
e8e7f271
SRT		 5600 /* UIC NL/TL/DME errors needs software retry */
5601 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
ff8e20c6
DR		 5602 if (reg) {
5603 ufshcd_update_uic_reg_hist(&hba->ufs_stats.nl_err, reg);
e8e7f271 5604 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
ff8e20c6 5605 }
e8e7f271
SRT		 5606
5607 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
ff8e20c6
DR		 5608 if (reg) {
5609 ufshcd_update_uic_reg_hist(&hba->ufs_stats.tl_err, reg);
e8e7f271 5610 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
ff8e20c6 5611 }
e8e7f271
SRT		 5612
5613 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
ff8e20c6
DR		 5614 if (reg) {
5615 ufshcd_update_uic_reg_hist(&hba->ufs_stats.dme_err, reg);
e8e7f271 5616 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
ff8e20c6 5617 }
e8e7f271
SRT		 5618
5619 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
5620 __func__, hba->uic_error);
5621}
5622
5623/**
5624 * ufshcd_check_errors - Check for errors that need s/w attention
5625 * @hba: per-adapter instance
5626 */
5627static void ufshcd_check_errors(struct ufs_hba *hba)
5628{
5629 bool queue_eh_work = false;
5630
7a3e97b0 5631 if (hba->errors & INT_FATAL_ERRORS)
e8e7f271 5632 queue_eh_work = true;
7a3e97b0
SY		 5633
5634 if (hba->errors & UIC_ERROR) {
e8e7f271
SRT		 5635 hba->uic_error = 0;
5636 ufshcd_update_uic_error(hba);
5637 if (hba->uic_error)
5638 queue_eh_work = true;
7a3e97b0 5639 }
e8e7f271
SRT		 5640
5641 if (queue_eh_work) {
9a47ec7c
YG		 5642 /*
5643 * update the transfer error masks to sticky bits, let's do this
5644 * irrespective of current ufshcd_state.
5645 */
5646 hba->saved_err |= hba->errors;
5647 hba->saved_uic_err |= hba->uic_error;
5648
e8e7f271
SRT		 5649 /* handle fatal errors only when link is functional */
5650 if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
5651 /* block commands from scsi mid-layer */
5652 scsi_block_requests(hba->host);
5653
141f8165 5654 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED;
66cc820f
DR		 5655
5656 /* dump controller state before resetting */
5657 if (hba->saved_err & (INT_FATAL_ERRORS | UIC_ERROR)) {
5658 bool pr_prdt = !!(hba->saved_err &
5659 SYSTEM_BUS_FATAL_ERROR);
5660
5661 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
5662 __func__, hba->saved_err,
5663 hba->saved_uic_err);
5664
5665 ufshcd_print_host_regs(hba);
5666 ufshcd_print_pwr_info(hba);
5667 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
5668 ufshcd_print_trs(hba, hba->outstanding_reqs,
5669 pr_prdt);
5670 }
e8e7f271
SRT		 5671 schedule_work(&hba->eh_work);
5672 }
3441da7d 5673 }
e8e7f271
SRT		 5674 /*
5675 * if (!queue_eh_work) -
5676 * Other errors are either non-fatal where host recovers
5677 * itself without s/w intervention or errors that will be
5678 * handled by the SCSI core layer.
5679 */
7a3e97b0
SY		 5680}
5681
5682/**
5683 * ufshcd_tmc_handler - handle task management function completion
5684 * @hba: per adapter instance
5685 */
5686static void ufshcd_tmc_handler(struct ufs_hba *hba)
5687{
5688 u32 tm_doorbell;
5689
b873a275 5690 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
7a3e97b0 5691 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
dbccd8eb 5692 hba->outstanding_tasks ^= hba->tm_condition;
e2933132 5693 wake_up(&hba->tm_wq);
7a3e97b0
SY		 5694}
5695
5696/**
5697 * ufshcd_sl_intr - Interrupt service routine
5698 * @hba: per adapter instance
5699 * @intr_status: contains interrupts generated by the controller
5700 */
5701static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
5702{
5703 hba->errors = UFSHCD_ERROR_MASK & intr_status;
5704 if (hba->errors)
e8e7f271 5705 ufshcd_check_errors(hba);
7a3e97b0 5706
53b3d9c3
SJ		 5707 if (intr_status & UFSHCD_UIC_MASK)
5708 ufshcd_uic_cmd_compl(hba, intr_status);
7a3e97b0
SY		 5709
5710 if (intr_status & UTP_TASK_REQ_COMPL)
5711 ufshcd_tmc_handler(hba);
5712
5713 if (intr_status & UTP_TRANSFER_REQ_COMPL)
5714 ufshcd_transfer_req_compl(hba);
5715}
5716
5717/**
5718 * ufshcd_intr - Main interrupt service routine
5719 * @irq: irq number
5720 * @__hba: pointer to adapter instance
5721 *
5722 * Returns IRQ_HANDLED - If interrupt is valid
5723 * IRQ_NONE - If invalid interrupt
5724 */
5725static irqreturn_t ufshcd_intr(int irq, void *__hba)
5726{
d75f7fe4 5727 u32 intr_status, enabled_intr_status;
7a3e97b0
SY		 5728 irqreturn_t retval = IRQ_NONE;
5729 struct ufs_hba *hba = __hba;
5730
5731 spin_lock(hba->host->host_lock);
b873a275 5732 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5733 enabled_intr_status =
5734 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7a3e97b0 5735
d75f7fe4 5736 if (intr_status)
261ea452 5737 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
d75f7fe4
YG		 5738
5739 if (enabled_intr_status) {
5740 ufshcd_sl_intr(hba, enabled_intr_status);
7a3e97b0
SY		 5741 retval = IRQ_HANDLED;
5742 }
5743 spin_unlock(hba->host->host_lock);
5744 return retval;
5745}
5746
e2933132
SRT		 5747static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
5748{
5749 int err = 0;
5750 u32 mask = 1 << tag;
5751 unsigned long flags;
5752
e2933132 5753 spin_lock_irqsave(hba->host->host_lock, flags);
86b7a91c 5754 ufshcd_utmrl_clear(hba, tag);
e2933132
SRT		 5755 spin_unlock_irqrestore(hba->host->host_lock, flags);
5756
5757 /* poll for max. 1 sec to clear door bell register by h/w */
5758 err = ufshcd_wait_for_register(hba,
5759 REG_UTP_TASK_REQ_DOOR_BELL,
596585a2 5760 mask, 0, 1000, 1000, true);
e2933132
SRT		 5761 return err;
5762}
5763
7a3e97b0
SY		 5764/**
5765 * ufshcd_issue_tm_cmd - issues task management commands to controller
5766 * @hba: per adapter instance
e2933132
SRT		 5767 * @lun_id: LUN ID to which TM command is sent
5768 * @task_id: task ID to which the TM command is applicable
5769 * @tm_function: task management function opcode
5770 * @tm_response: task management service response return value
7a3e97b0 5771 *
e2933132 5772 * Returns non-zero value on error, zero on success.
7a3e97b0 5773 */
e2933132
SRT		 5774static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
5775 u8 tm_function, u8 *tm_response)
7a3e97b0
SY		 5776{
5777 struct utp_task_req_desc *task_req_descp;
5778 struct utp_upiu_task_req *task_req_upiup;
5779 struct Scsi_Host *host;
5780 unsigned long flags;
e2933132 5781 int free_slot;
7a3e97b0 5782 int err;
e2933132 5783 int task_tag;
7a3e97b0
SY		 5784
5785 host = hba->host;
5786
e2933132
SRT		 5787 /*
5788 * Get free slot, sleep if slots are unavailable.
5789 * Even though we use wait_event() which sleeps indefinitely,
5790 * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
5791 */
5792 wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
1ab27c9c 5793 ufshcd_hold(hba, false);
7a3e97b0 5794
e2933132 5795 spin_lock_irqsave(host->host_lock, flags);
7a3e97b0
SY		 5796 task_req_descp = hba->utmrdl_base_addr;
5797 task_req_descp += free_slot;
5798
5799 /* Configure task request descriptor */
5800 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
5801 task_req_descp->header.dword_2 =
5802 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
5803
5804 /* Configure task request UPIU */
5805 task_req_upiup =
5806 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
e2933132 5807 task_tag = hba->nutrs + free_slot;
7a3e97b0 5808 task_req_upiup->header.dword_0 =
5a0b0cb9 5809 UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
e2933132 5810 lun_id, task_tag);
7a3e97b0 5811 task_req_upiup->header.dword_1 =
5a0b0cb9 5812 UPIU_HEADER_DWORD(0, tm_function, 0, 0);
0ce147d4
SJ		 5813 /*
5814 * The host shall provide the same value for LUN field in the basic
5815 * header and for Input Parameter.
5816 */
e2933132
SRT		 5817 task_req_upiup->input_param1 = cpu_to_be32(lun_id);
5818 task_req_upiup->input_param2 = cpu_to_be32(task_id);
7a3e97b0 5819
d2877be4
KK		 5820 ufshcd_vops_setup_task_mgmt(hba, free_slot, tm_function);
5821
7a3e97b0 5822 /* send command to the controller */
03229397 5823 if (hba->vops && hba->vops->set_nexus_t_task_mgmt)
5824 hba->vops->set_nexus_t_task_mgmt(hba, free_slot, tm_function);
7a3e97b0 5825 __set_bit(free_slot, &hba->outstanding_tasks);
897efe62
YG		 5826
5827 /* Make sure descriptors are ready before ringing the task doorbell */
5828 wmb();
5829
b873a275 5830 ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
ad1a1b9c
GB		 5831 /* Make sure that doorbell is committed immediately */
5832 wmb();
7a3e97b0
SY		 5833
5834 spin_unlock_irqrestore(host->host_lock, flags);
5835
5836 /* wait until the task management command is completed */
e2933132
SRT		 5837 err = wait_event_timeout(hba->tm_wq,
5838 test_bit(free_slot, &hba->tm_condition),
5839 msecs_to_jiffies(TM_CMD_TIMEOUT));
7a3e97b0 5840 if (!err) {
e2933132
SRT		 5841 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
5842 __func__, tm_function);
dbccd8eb 5843 if (!ufshcd_clear_tm_cmd(hba, free_slot)) {
5844 spin_lock_irqsave(hba->host->host_lock, flags);
5845 __clear_bit(free_slot, &hba->outstanding_tasks);
5846 spin_unlock_irqrestore(hba->host->host_lock, flags);
5847 } else {
e2933132
SRT		 5848 dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
5849 __func__, free_slot);
dbccd8eb 5850 }
e2933132
SRT		 5851 err = -ETIMEDOUT;
5852 } else {
5853 err = ufshcd_task_req_compl(hba, free_slot, tm_response);
7a3e97b0 5854 }
e2933132 5855
7a3e97b0 5856 clear_bit(free_slot, &hba->tm_condition);
e2933132
SRT		 5857 ufshcd_put_tm_slot(hba, free_slot);
5858 wake_up(&hba->tm_tag_wq);
5859
1ab27c9c 5860 ufshcd_release(hba);
7a3e97b0
SY		 5861 return err;
5862}
5863
5864/**
3441da7d
SRT		 5865 * ufshcd_eh_device_reset_handler - device reset handler registered to
5866 * scsi layer.
7a3e97b0
SY		 5867 * @cmd: SCSI command pointer
5868 *
5869 * Returns SUCCESS/FAILED
5870 */
3441da7d 5871static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7a3e97b0
SY		 5872{
5873 struct Scsi_Host *host;
5874 struct ufs_hba *hba;
5875 unsigned int tag;
5876 u32 pos;
5877 int err;
e2933132
SRT		 5878 u8 resp = 0xF;
5879 struct ufshcd_lrb *lrbp;
3441da7d 5880 unsigned long flags;
7a3e97b0
SY		 5881
5882 host = cmd->device->host;
5883 hba = shost_priv(host);
5884 tag = cmd->request->tag;
5885
aee9809c 5886 /* Dump debugging information to system memory */
5887 ufshcd_vops_dbg_register_dump(hba);
e2933132
SRT		 5888 lrbp = &hba->lrb[tag];
5889 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
5890 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
3441da7d
SRT		 5891 if (!err)
5892 err = resp;
7a3e97b0 5893 goto out;
e2933132 5894 }
7a3e97b0 5895
3441da7d
SRT		 5896 /* clear the commands that were pending for corresponding LUN */
5897 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
5898 if (hba->lrb[pos].lun == lrbp->lun) {
5899 err = ufshcd_clear_cmd(hba, pos);
5900 if (err)
5901 break;
7a3e97b0 5902 }
3441da7d
SRT		 5903 }
5904 spin_lock_irqsave(host->host_lock, flags);
5905 ufshcd_transfer_req_compl(hba);
5906 spin_unlock_irqrestore(host->host_lock, flags);
7fabb77b 5907
7a3e97b0 5908out:
7fabb77b 5909 hba->req_abort_count = 0;
3441da7d
SRT		 5910 if (!err) {
5911 err = SUCCESS;
5912 } else {
5913 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
5914 err = FAILED;
5915 }
7a3e97b0
SY		 5916 return err;
5917}
5918
e0b299e3
GB		 5919static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
5920{
5921 struct ufshcd_lrb *lrbp;
5922 int tag;
5923
5924 for_each_set_bit(tag, &bitmap, hba->nutrs) {
5925 lrbp = &hba->lrb[tag];
5926 lrbp->req_abort_skip = true;
5927 }
5928}
5929
7a3e97b0
SY		 5930/**
5931 * ufshcd_abort - abort a specific command
5932 * @cmd: SCSI command pointer
5933 *
f20810d8
SRT		 5934 * Abort the pending command in device by sending UFS_ABORT_TASK task management
5935 * command, and in host controller by clearing the door-bell register. There can
5936 * be race between controller sending the command to the device while abort is
5937 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
5938 * really issued and then try to abort it.
5939 *
7a3e97b0
SY		 5940 * Returns SUCCESS/FAILED
5941 */
5942static int ufshcd_abort(struct scsi_cmnd *cmd)
5943{
5944 struct Scsi_Host *host;
5945 struct ufs_hba *hba;
5946 unsigned long flags;
5947 unsigned int tag;
f20810d8
SRT		 5948 int err = 0;
5949 int poll_cnt;
e2933132
SRT		 5950 u8 resp = 0xF;
5951 struct ufshcd_lrb *lrbp;
e9d501b1 5952 u32 reg;
7a3e97b0
SY		 5953
5954 host = cmd->device->host;
5955 hba = shost_priv(host);
5956 tag = cmd->request->tag;
e7d38257 5957 lrbp = &hba->lrb[tag];
14497328
YG		 5958 if (!ufshcd_valid_tag(hba, tag)) {
5959 dev_err(hba->dev,
5960 "%s: invalid command tag %d: cmd=0x%p, cmd->request=0x%p",
5961 __func__, tag, cmd, cmd->request);
5962 BUG();
5963 }
7a3e97b0 5964
e7d38257
DR		 5965 /*
5966 * Task abort to the device W-LUN is illegal. When this command
5967 * will fail, due to spec violation, scsi err handling next step
5968 * will be to send LU reset which, again, is a spec violation.
5969 * To avoid these unnecessary/illegal step we skip to the last error
5970 * handling stage: reset and restore.
5971 */
5972 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN)
5973 return ufshcd_eh_host_reset_handler(cmd);
5974
888b9a69 5975
5976 if (cmd->cmnd[0] == READ_10 || cmd->cmnd[0] == WRITE_10) {
5977 unsigned long lba = (cmd->cmnd[2] << 24) |
5978 (cmd->cmnd[3] << 16) |
5979 (cmd->cmnd[4] << 8) |
5980 (cmd->cmnd[5] << 0);
5981 unsigned int sct = (cmd->cmnd[7] << 8) |
5982 (cmd->cmnd[8] << 0);
5983
5984 dev_err(hba->dev, "%s: tag:%d, cmd:0x%x, "
5985 "lba:0x%08lx, sct:0x%04x, retries %d\n",
5986 __func__, tag, cmd->cmnd[0], lba, sct, cmd->retries);
5987 } else {
5988 dev_err(hba->dev, "%s: tag:%d, cmd:0x%x, retries %d\n",
5989 __func__, tag, cmd->cmnd[0], cmd->retries);
5990 }
5991
1ab27c9c 5992 ufshcd_hold(hba, false);
aee9809c 5993 /* Dump debugging information to system memory */
5994 ufshcd_vops_dbg_register_dump(hba);
14497328 5995 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
f20810d8 5996 /* If command is already aborted/completed, return SUCCESS */
14497328
YG		 5997 if (!(test_bit(tag, &hba->outstanding_reqs))) {
5998 dev_err(hba->dev,
5999 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
6000 __func__, tag, hba->outstanding_reqs, reg);
f20810d8 6001 goto out;
14497328 6002 }
7a3e97b0 6003
e9d501b1
DR		 6004 if (!(reg & (1 << tag))) {
6005 dev_err(hba->dev,
6006 "%s: cmd was completed, but without a notifying intr, tag = %d",
6007 __func__, tag);
f771f925 6008 goto clean;
e9d501b1
DR		 6009 }
6010
66cc820f
DR		 6011 /* Print Transfer Request of aborted task */
6012 dev_err(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
66cc820f 6013
7fabb77b
GB		 6014 /*
6015 * Print detailed info about aborted request.
6016 * As more than one request might get aborted at the same time,
6017 * print full information only for the first aborted request in order
6018 * to reduce repeated printouts. For other aborted requests only print
6019 * basic details.
6020 */
6021 scsi_print_command(hba->lrb[tag].cmd);
6022 if (!hba->req_abort_count) {
6023 ufshcd_print_host_regs(hba);
6ba65588 6024 ufshcd_print_host_state(hba);
7fabb77b
GB		 6025 ufshcd_print_pwr_info(hba);
6026 ufshcd_print_trs(hba, 1 << tag, true);
6027 } else {
6028 ufshcd_print_trs(hba, 1 << tag, false);
6029 }
6030 hba->req_abort_count++;
e0b299e3
GB		 6031
6032 /* Skip task abort in case previous aborts failed and report failure */
6033 if (lrbp->req_abort_skip) {
6034 err = -EIO;
6035 goto out;
6036 }
6037
f20810d8
SRT		 6038 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
6039 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6040 UFS_QUERY_TASK, &resp);
6041 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
6042 /* cmd pending in the device */
ff8e20c6
DR		 6043 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
6044 __func__, tag);
f20810d8
SRT		 6045 break;
6046 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
f20810d8
SRT		 6047 /*
6048 * cmd not pending in the device, check if it is
6049 * in transition.
6050 */
ff8e20c6
DR		 6051 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
6052 __func__, tag);
f20810d8
SRT		 6053 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
6054 if (reg & (1 << tag)) {
6055 /* sleep for max. 200us to stabilize */
6056 usleep_range(100, 200);
6057 continue;
6058 }
6059 /* command completed already */
ff8e20c6
DR		 6060 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
6061 __func__, tag);
f20810d8
SRT		 6062 goto out;
6063 } else {
ff8e20c6
DR		 6064 dev_err(hba->dev,
6065 "%s: no response from device. tag = %d, err %d\n",
6066 __func__, tag, err);
f20810d8
SRT		 6067 if (!err)
6068 err = resp; /* service response error */
f771f925 6069 dev_err(hba->dev,
6070 "%s: query task failed with err %d\n",
6071 __func__, err);
f20810d8
SRT		 6072 goto out;
6073 }
6074 }
6075
6076 if (!poll_cnt) {
6077 err = -EBUSY;
f771f925 6078 dev_err(hba->dev,
6079 "%s: cmd might be missed, not pending in device\n",
6080 __func__);
7a3e97b0
SY		 6081 goto out;
6082 }
7a3e97b0 6083
e2933132
SRT		 6084 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
6085 UFS_ABORT_TASK, &resp);
6086 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
ff8e20c6 6087 if (!err) {
f20810d8 6088 err = resp; /* service response error */
ff8e20c6
DR		 6089 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
6090 __func__, tag, err);
6091 }
7a3e97b0 6092 goto out;
e2933132 6093 }
7a3e97b0 6094
f20810d8 6095 err = ufshcd_clear_cmd(hba, tag);
ff8e20c6
DR		 6096 if (err) {
6097 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
6098 __func__, tag, err);
f20810d8 6099 goto out;
ff8e20c6 6100 }
f771f925 6101clean:
7a3e97b0
SY		 6102 scsi_dma_unmap(cmd);
6103
6104 spin_lock_irqsave(host->host_lock, flags);
a48353f6 6105 ufshcd_outstanding_req_clear(hba, tag);
7a3e97b0
SY		 6106 hba->lrb[tag].cmd = NULL;
6107 spin_unlock_irqrestore(host->host_lock, flags);
5a0b0cb9
SRT		 6108
6109 clear_bit_unlock(tag, &hba->lrb_in_use);
6110 wake_up(&hba->dev_cmd.tag_wq);
1ab27c9c 6111
7a3e97b0 6112out:
f20810d8
SRT		 6113 if (!err) {
6114 err = SUCCESS;
6115 } else {
6116 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
e0b299e3 6117 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
f20810d8
SRT		 6118 err = FAILED;
6119 }
6120
1ab27c9c
ST		 6121 /*
6122 * This ufshcd_release() corresponds to the original scsi cmd that got
6123 * aborted here (as we won't get any IRQ for it).
6124 */
6125 ufshcd_release(hba);
7a3e97b0
SY		 6126 return err;
6127}
6128
3441da7d
SRT		 6129/**
6130 * ufshcd_host_reset_and_restore - reset and restore host controller
6131 * @hba: per-adapter instance
6132 *
6133 * Note that host controller reset may issue DME_RESET to
6134 * local and remote (device) Uni-Pro stack and the attributes
6135 * are reset to default state.
6136 *
6137 * Returns zero on success, non-zero on failure
6138 */
6139static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
6140{
105e2d39 6141 int err = 0;
3441da7d
SRT		 6142 unsigned long flags;
6143
6144 /* Reset the host controller */
6145 spin_lock_irqsave(hba->host->host_lock, flags);
0f7f11ff 6146 hba->ufshcd_state = UFSHCD_STATE_RESET;
6147 ufshcd_set_eh_in_progress(hba);
596585a2 6148 ufshcd_hba_stop(hba, false);
3441da7d
SRT		 6149 spin_unlock_irqrestore(hba->host->host_lock, flags);
6150
a3cd5ec5
SJ		 6151 /* scale up clocks to max frequency before full reinitialization */
6152 ufshcd_scale_clks(hba, true);
6153
3441da7d 6154 /* Establish the link again and restore the device */
105e2d39 6155#ifdef CONFIG_SCSI_UFS_ASYNC_RELINK
6156 if (hba->pm_op_in_progress)
6157 async_schedule(ufshcd_async_scan, hba);
6158 else
6159#endif
6160 {
6161 err = ufshcd_probe_hba(hba);
1d337ec2 6162
251f4e5f 6163 if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)) {
6164 dev_err(hba->dev, "%s: failed\n", __func__);
6165 err = -EIO;
6166 }
105e2d39 6167 }
6168
0f7f11ff 6169 spin_lock_irqsave(hba->host->host_lock, flags);
6170 ufshcd_clear_eh_in_progress(hba);
6171 spin_unlock_irqrestore(hba->host->host_lock, flags);
3441da7d
SRT		 6172
6173 return err;
6174}
6175
6176/**
6177 * ufshcd_reset_and_restore - reset and re-initialize host/device
6178 * @hba: per-adapter instance
6179 *
6180 * Reset and recover device, host and re-establish link. This
6181 * is helpful to recover the communication in fatal error conditions.
6182 *
6183 * Returns zero on success, non-zero on failure
6184 */
6185static int ufshcd_reset_and_restore(struct ufs_hba *hba)
6186{
6187 int err = 0;
6188 unsigned long flags;
1d337ec2 6189 int retries = MAX_HOST_RESET_RETRIES;
3441da7d 6190
5bb4e709 6191 int tag;
6192
6193 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
6194 ufshcd_clear_cmd(hba, tag);
6195
6196 spin_lock_irqsave(hba->host->host_lock, flags);
6197 ufshcd_transfer_req_compl(hba, DID_RESET);
6198 spin_unlock_irqrestore(hba->host->host_lock, flags);
6199
6200 ssleep(1);
6201
1d337ec2
SRT		 6202 do {
6203 err = ufshcd_host_reset_and_restore(hba);
6204 } while (err && --retries);
3441da7d
SRT		 6205
6206 /*
6207 * After reset the door-bell might be cleared, complete
6208 * outstanding requests in s/w here.
6209 */
6210 spin_lock_irqsave(hba->host->host_lock, flags);
6211 ufshcd_transfer_req_compl(hba);
6212 ufshcd_tmc_handler(hba);
6213 spin_unlock_irqrestore(hba->host->host_lock, flags);
6214
6215 return err;
6216}
6217
6218/**
6219 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
6220 * @cmd - SCSI command pointer
6221 *
6222 * Returns SUCCESS/FAILED
6223 */
6224static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
6225{
6226 int err;
6227 unsigned long flags;
6228 struct ufs_hba *hba;
6229
6230 hba = shost_priv(cmd->device->host);
6231
1ab27c9c 6232 ufshcd_hold(hba, false);
3441da7d
SRT		 6233 /*
6234 * Check if there is any race with fatal error handling.
6235 * If so, wait for it to complete. Even though fatal error
6236 * handling does reset and restore in some cases, don't assume
6237 * anything out of it. We are just avoiding race here.
6238 */
6239 do {
6240 spin_lock_irqsave(hba->host->host_lock, flags);
e8e7f271 6241 if (!(work_pending(&hba->eh_work) ||
8dc0da79
ZL		 6242 hba->ufshcd_state == UFSHCD_STATE_RESET ||
6243 hba->ufshcd_state == UFSHCD_STATE_EH_SCHEDULED))
3441da7d
SRT		 6244 break;
6245 spin_unlock_irqrestore(hba->host->host_lock, flags);
6246 dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
e8e7f271 6247 flush_work(&hba->eh_work);
3441da7d
SRT		 6248 } while (1);
6249
6250 hba->ufshcd_state = UFSHCD_STATE_RESET;
6251 ufshcd_set_eh_in_progress(hba);
6252 spin_unlock_irqrestore(hba->host->host_lock, flags);
6253
6254 err = ufshcd_reset_and_restore(hba);
6255
6256 spin_lock_irqsave(hba->host->host_lock, flags);
6257 if (!err) {
6258 err = SUCCESS;
6259 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6260 } else {
6261 err = FAILED;
6262 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6263 }
6264 ufshcd_clear_eh_in_progress(hba);
6265 spin_unlock_irqrestore(hba->host->host_lock, flags);
6266
1ab27c9c 6267 ufshcd_release(hba);
3441da7d
SRT		 6268 return err;
6269}
6270
3a4bf06d
YG		 6271/**
6272 * ufshcd_get_max_icc_level - calculate the ICC level
6273 * @sup_curr_uA: max. current supported by the regulator
6274 * @start_scan: row at the desc table to start scan from
6275 * @buff: power descriptor buffer
6276 *
6277 * Returns calculated max ICC level for specific regulator
6278 */
6279static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
6280{
6281 int i;
6282 int curr_uA;
6283 u16 data;
6284 u16 unit;
6285
6286 for (i = start_scan; i >= 0; i--) {
d79713f9 6287 data = be16_to_cpup((__be16 *)&buff[2 * i]);
3a4bf06d
YG		 6288 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
6289 ATTR_ICC_LVL_UNIT_OFFSET;
6290 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
6291 switch (unit) {
6292 case UFSHCD_NANO_AMP:
6293 curr_uA = curr_uA / 1000;
6294 break;
6295 case UFSHCD_MILI_AMP:
6296 curr_uA = curr_uA * 1000;
6297 break;
6298 case UFSHCD_AMP:
6299 curr_uA = curr_uA * 1000 * 1000;
6300 break;
6301 case UFSHCD_MICRO_AMP:
6302 default:
6303 break;
6304 }
6305 if (sup_curr_uA >= curr_uA)
6306 break;
6307 }
6308 if (i < 0) {
6309 i = 0;
6310 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
6311 }
6312
6313 return (u32)i;
6314}
6315
6316/**
6317 * ufshcd_calc_icc_level - calculate the max ICC level
6318 * In case regulators are not initialized we'll return 0
6319 * @hba: per-adapter instance
6320 * @desc_buf: power descriptor buffer to extract ICC levels from.
6321 * @len: length of desc_buff
6322 *
6323 * Returns calculated ICC level
6324 */
6325static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
6326 u8 *desc_buf, int len)
6327{
6328 u32 icc_level = 0;
6329
6330 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
6331 !hba->vreg_info.vccq2) {
6332 dev_err(hba->dev,
6333 "%s: Regulator capability was not set, actvIccLevel=%d",
6334 __func__, icc_level);
6335 goto out;
6336 }
6337
6338 if (hba->vreg_info.vcc)
6339 icc_level = ufshcd_get_max_icc_level(
6340 hba->vreg_info.vcc->max_uA,
6341 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
6342 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
6343
6344 if (hba->vreg_info.vccq)
6345 icc_level = ufshcd_get_max_icc_level(
6346 hba->vreg_info.vccq->max_uA,
6347 icc_level,
6348 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
6349
6350 if (hba->vreg_info.vccq2)
6351 icc_level = ufshcd_get_max_icc_level(
6352 hba->vreg_info.vccq2->max_uA,
6353 icc_level,
6354 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
6355out:
6356 return icc_level;
6357}
6358
6359static void ufshcd_init_icc_levels(struct ufs_hba *hba)
6360{
6361 int ret;
a4b0e8a4
PM		 6362 int buff_len = hba->desc_size.pwr_desc;
6363 u8 desc_buf[hba->desc_size.pwr_desc];
3a4bf06d
YG		 6364
6365 ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
6366 if (ret) {
6367 dev_err(hba->dev,
6368 "%s: Failed reading power descriptor.len = %d ret = %d",
6369 __func__, buff_len, ret);
6370 return;
6371 }
6372
6373 hba->init_prefetch_data.icc_level =
6374 ufshcd_find_max_sup_active_icc_level(hba,
6375 desc_buf, buff_len);
6376 dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
6377 __func__, hba->init_prefetch_data.icc_level);
6378
dbd34a61
SM		 6379 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
6380 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
6381 &hba->init_prefetch_data.icc_level);
3a4bf06d
YG		 6382
6383 if (ret)
6384 dev_err(hba->dev,
6385 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
6386 __func__, hba->init_prefetch_data.icc_level , ret);
6387
6388}
6389
2a8fa600
SJ		 6390/**
6391 * ufshcd_scsi_add_wlus - Adds required W-LUs
6392 * @hba: per-adapter instance
6393 *
6394 * UFS device specification requires the UFS devices to support 4 well known
6395 * logical units:
6396 * "REPORT_LUNS" (address: 01h)
6397 * "UFS Device" (address: 50h)
6398 * "RPMB" (address: 44h)
6399 * "BOOT" (address: 30h)
6400 * UFS device's power management needs to be controlled by "POWER CONDITION"
6401 * field of SSU (START STOP UNIT) command. But this "power condition" field
6402 * will take effect only when its sent to "UFS device" well known logical unit
6403 * hence we require the scsi_device instance to represent this logical unit in
6404 * order for the UFS host driver to send the SSU command for power management.
6405
6406 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
6407 * Block) LU so user space process can control this LU. User space may also
6408 * want to have access to BOOT LU.
6409
6410 * This function adds scsi device instances for each of all well known LUs
6411 * (except "REPORT LUNS" LU).
6412 *
6413 * Returns zero on success (all required W-LUs are added successfully),
6414 * non-zero error value on failure (if failed to add any of the required W-LU).
6415 */
6416static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
6417{
6418 int ret = 0;
7c48bfd0 6419 struct scsi_device *sdev_boot;
2a8fa600
SJ		 6420
6421 hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
6422 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
6423 if (IS_ERR(hba->sdev_ufs_device)) {
6424 ret = PTR_ERR(hba->sdev_ufs_device);
6425 hba->sdev_ufs_device = NULL;
6426 goto out;
6427 }
7c48bfd0 6428 scsi_device_put(hba->sdev_ufs_device);
2a8fa600 6429
7c48bfd0 6430 sdev_boot = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6431 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7c48bfd0
AM		 6432 if (IS_ERR(sdev_boot)) {
6433 ret = PTR_ERR(sdev_boot);
2a8fa600
SJ		 6434 goto remove_sdev_ufs_device;
6435 }
7c48bfd0 6436 scsi_device_put(sdev_boot);
2a8fa600 6437
071b73ac 6438 hba->sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
2a8fa600 6439 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
071b73ac 6440 if (IS_ERR(hba->sdev_rpmb)) {
6441 ret = PTR_ERR(hba->sdev_rpmb);
2a8fa600
SJ		 6442 goto remove_sdev_boot;
6443 }
071b73ac 6444 scsi_device_put(hba->sdev_rpmb);
2a8fa600
SJ		 6445 goto out;
6446
6447remove_sdev_boot:
7c48bfd0 6448 scsi_remove_device(sdev_boot);
2a8fa600
SJ		 6449remove_sdev_ufs_device:
6450 scsi_remove_device(hba->sdev_ufs_device);
6451out:
6452 return ret;
6453}
6454
93fdd5ac
TW		 6455static int ufs_get_device_desc(struct ufs_hba *hba,
6456 struct ufs_dev_desc *dev_desc)
c58ab7aa
YG		 6457{
6458 int err;
6459 u8 model_index;
a4b0e8a4
PM		 6460 u8 str_desc_buf[QUERY_DESC_MAX_SIZE + 1] = {0};
6461 u8 desc_buf[hba->desc_size.dev_desc];
c58ab7aa 6462
a4b0e8a4 6463 err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
c58ab7aa
YG		 6464 if (err) {
6465 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
6466 __func__, err);
6467 goto out;
6468 }
6469
6470 /*
6471 * getting vendor (manufacturerID) and Bank Index in big endian
6472 * format
6473 */
93fdd5ac 6474 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
c58ab7aa
YG		 6475 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
6476
6477 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
6478
6479 err = ufshcd_read_string_desc(hba, model_index, str_desc_buf,
a4b0e8a4 6480 QUERY_DESC_MAX_SIZE, ASCII_STD);
c58ab7aa
YG		 6481 if (err) {
6482 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
6483 __func__, err);
6484 goto out;
6485 }
6486
a4b0e8a4 6487 str_desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
93fdd5ac 6488 strlcpy(dev_desc->model, (str_desc_buf + QUERY_DESC_HDR_SIZE),
c58ab7aa
YG		 6489 min_t(u8, str_desc_buf[QUERY_DESC_LENGTH_OFFSET],
6490 MAX_MODEL_LEN));
6491
6492 /* Null terminate the model string */
93fdd5ac 6493 dev_desc->model[MAX_MODEL_LEN] = '\0';
c58ab7aa
YG		 6494
6495out:
6496 return err;
6497}
6498
93fdd5ac
TW		 6499static void ufs_fixup_device_setup(struct ufs_hba *hba,
6500 struct ufs_dev_desc *dev_desc)
c58ab7aa 6501{
c58ab7aa 6502 struct ufs_dev_fix *f;
c58ab7aa
YG		 6503
6504 for (f = ufs_fixups; f->quirk; f++) {
93fdd5ac
TW		 6505 if ((f->card.wmanufacturerid == dev_desc->wmanufacturerid ||
6506 f->card.wmanufacturerid == UFS_ANY_VENDOR) &&
6507 (STR_PRFX_EQUAL(f->card.model, dev_desc->model) ||
c58ab7aa
YG		 6508 !strcmp(f->card.model, UFS_ANY_MODEL)))
6509 hba->dev_quirks |= f->quirk;
6510 }
6511}
6512
37113106
YG		 6513/**
6514 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
6515 * @hba: per-adapter instance
6516 *
6517 * PA_TActivate parameter can be tuned manually if UniPro version is less than
6518 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
6519 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
6520 * the hibern8 exit latency.
6521 *
6522 * Returns zero on success, non-zero error value on failure.
6523 */
6524static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
6525{
6526 int ret = 0;
6527 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
6528
6529 ret = ufshcd_dme_peer_get(hba,
6530 UIC_ARG_MIB_SEL(
6531 RX_MIN_ACTIVATETIME_CAPABILITY,
6532 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6533 &peer_rx_min_activatetime);
6534 if (ret)
6535 goto out;
6536
6537 /* make sure proper unit conversion is applied */
6538 tuned_pa_tactivate =
6539 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
6540 / PA_TACTIVATE_TIME_UNIT_US);
6541 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6542 tuned_pa_tactivate);
6543
6544out:
6545 return ret;
6546}
6547
6548/**
6549 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
6550 * @hba: per-adapter instance
6551 *
6552 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
6553 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
6554 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
6555 * This optimal value can help reduce the hibern8 exit latency.
6556 *
6557 * Returns zero on success, non-zero error value on failure.
6558 */
6559static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
6560{
6561 int ret = 0;
6562 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
6563 u32 max_hibern8_time, tuned_pa_hibern8time;
6564
6565 ret = ufshcd_dme_get(hba,
6566 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
6567 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
6568 &local_tx_hibern8_time_cap);
6569 if (ret)
6570 goto out;
6571
6572 ret = ufshcd_dme_peer_get(hba,
6573 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
6574 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
6575 &peer_rx_hibern8_time_cap);
6576 if (ret)
6577 goto out;
6578
6579 max_hibern8_time = max(local_tx_hibern8_time_cap,
6580 peer_rx_hibern8_time_cap);
6581 /* make sure proper unit conversion is applied */
6582 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
6583 / PA_HIBERN8_TIME_UNIT_US);
6584 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
6585 tuned_pa_hibern8time);
6586out:
6587 return ret;
6588}
6589
c6a6db43
SJ		 6590/**
6591 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
6592 * less than device PA_TACTIVATE time.
6593 * @hba: per-adapter instance
6594 *
6595 * Some UFS devices require host PA_TACTIVATE to be lower than device
6596 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
6597 * for such devices.
6598 *
6599 * Returns zero on success, non-zero error value on failure.
6600 */
6601static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
6602{
6603 int ret = 0;
6604 u32 granularity, peer_granularity;
6605 u32 pa_tactivate, peer_pa_tactivate;
6606 u32 pa_tactivate_us, peer_pa_tactivate_us;
6607 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
6608
6609 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6610 &granularity);
6611 if (ret)
6612 goto out;
6613
6614 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
6615 &peer_granularity);
6616 if (ret)
6617 goto out;
6618
6619 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
6620 (granularity > PA_GRANULARITY_MAX_VAL)) {
6621 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
6622 __func__, granularity);
6623 return -EINVAL;
6624 }
6625
6626 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
6627 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
6628 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
6629 __func__, peer_granularity);
6630 return -EINVAL;
6631 }
6632
6633 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
6634 if (ret)
6635 goto out;
6636
6637 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
6638 &peer_pa_tactivate);
6639 if (ret)
6640 goto out;
6641
6642 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
6643 peer_pa_tactivate_us = peer_pa_tactivate *
6644 gran_to_us_table[peer_granularity - 1];
6645
6646 if (pa_tactivate_us > peer_pa_tactivate_us) {
6647 u32 new_peer_pa_tactivate;
6648
6649 new_peer_pa_tactivate = pa_tactivate_us /
6650 gran_to_us_table[peer_granularity - 1];
6651 new_peer_pa_tactivate++;
6652 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
6653 new_peer_pa_tactivate);
6654 }
6655
6656out:
6657 return ret;
6658}
6659
37113106
YG		 6660static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
6661{
6662 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
6663 ufshcd_tune_pa_tactivate(hba);
6664 ufshcd_tune_pa_hibern8time(hba);
6665 }
6666
6667 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
6668 /* set 1ms timeout for PA_TACTIVATE */
6669 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
c6a6db43
SJ		 6670
6671 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
6672 ufshcd_quirk_tune_host_pa_tactivate(hba);
56d4a186
SJ		 6673
6674 ufshcd_vops_apply_dev_quirks(hba);
37113106
YG		 6675}
6676
ff8e20c6
DR		 6677static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
6678{
6679 int err_reg_hist_size = sizeof(struct ufs_uic_err_reg_hist);
6680
6681 hba->ufs_stats.hibern8_exit_cnt = 0;
6682 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
6683
6684 memset(&hba->ufs_stats.pa_err, 0, err_reg_hist_size);
6685 memset(&hba->ufs_stats.dl_err, 0, err_reg_hist_size);
6686 memset(&hba->ufs_stats.nl_err, 0, err_reg_hist_size);
6687 memset(&hba->ufs_stats.tl_err, 0, err_reg_hist_size);
6688 memset(&hba->ufs_stats.dme_err, 0, err_reg_hist_size);
7fabb77b
GB		 6689
6690 hba->req_abort_count = 0;
ff8e20c6
DR		 6691}
6692
a4b0e8a4
PM		 6693static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
6694{
6695 int err;
6696
6697 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
6698 &hba->desc_size.dev_desc);
6699 if (err)
6700 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6701
6702 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
6703 &hba->desc_size.pwr_desc);
6704 if (err)
6705 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6706
6707 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
6708 &hba->desc_size.interc_desc);
6709 if (err)
6710 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6711
6712 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
6713 &hba->desc_size.conf_desc);
6714 if (err)
6715 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6716
6717 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
6718 &hba->desc_size.unit_desc);
6719 if (err)
6720 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6721
6722 err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
6723 &hba->desc_size.geom_desc);
6724 if (err)
6725 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6726}
6727
6728static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
6729{
6730 hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
6731 hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
6732 hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
6733 hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
6734 hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
6735 hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
6736}
6737
6ccf44fe 6738/**
1d337ec2
SRT		 6739 * ufshcd_probe_hba - probe hba to detect device and initialize
6740 * @hba: per-adapter instance
6741 *
6742 * Execute link-startup and verify device initialization
6ccf44fe 6743 */
1d337ec2 6744static int ufshcd_probe_hba(struct ufs_hba *hba)
6ccf44fe 6745{
93fdd5ac 6746 struct ufs_dev_desc card = {0};
72c97747 6747 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
623b5fe3 6748 int re_cnt = 0;
6ccf44fe 6749 int ret;
7ff5ab47 6750 ktime_t start = ktime_get();
2bfd4b44 6751 unsigned long flags;
6ccf44fe 6752
623b5fe3 6753retry:
251f4e5f 6754 ret = ufshcd_hba_enable(hba);
6755 if (ret)
6756 goto out;
6757
6ccf44fe 6758 ret = ufshcd_link_startup(hba);
5a0b0cb9
SRT		 6759 if (ret)
6760 goto out;
6761
508cb48c 6762 dev_info(hba->dev, "UFS link established\n");
6763
afdfff59
YG		 6764 /* set the default level for urgent bkops */
6765 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
6766 hba->is_urgent_bkops_lvl_checked = false;
6767
ff8e20c6
DR		 6768 /* Debug counters initialization */
6769 ufshcd_clear_dbg_ufs_stats(hba);
6770
57d104c1
SJ		 6771 /* UniPro link is active now */
6772 ufshcd_set_link_active(hba);
d3e89bac 6773
5a0b0cb9
SRT		 6774 ret = ufshcd_verify_dev_init(hba);
6775 if (ret)
6776 goto out;
68078d5c
DR		 6777
6778 ret = ufshcd_complete_dev_init(hba);
6779 if (ret)
6780 goto out;
5a0b0cb9 6781
a4b0e8a4
PM		 6782 /* Init check for device descriptor sizes */
6783 ufshcd_init_desc_sizes(hba);
6784
93fdd5ac
TW		 6785 ret = ufs_get_device_desc(hba, &card);
6786 if (ret) {
6787 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
6788 __func__, ret);
6789 goto out;
6790 }
6791
6792 ufs_fixup_device_setup(hba, &card);
37113106 6793 ufshcd_tune_unipro_params(hba);
60f01870
YG		 6794
6795 ret = ufshcd_set_vccq_rail_unused(hba,
6796 (hba->dev_quirks & UFS_DEVICE_NO_VCCQ) ? true : false);
6797 if (ret)
6798 goto out;
6799
57d104c1
SJ		 6800 /* UFS device is also active now */
6801 ufshcd_set_ufs_dev_active(hba);
66ec6d59 6802 ufshcd_force_reset_auto_bkops(hba);
57d104c1
SJ		 6803 hba->wlun_dev_clr_ua = true;
6804
7eb584db
DR		 6805 if (ufshcd_get_max_pwr_mode(hba)) {
6806 dev_err(hba->dev,
6807 "%s: Failed getting max supported power mode\n",
6808 __func__);
6809 } else {
72c97747 6810 if ((pwr_info->lane_rx != pwr_info->peer_available_lane_rx)
6811 || (pwr_info->lane_tx != pwr_info->peer_available_lane_tx)) {
6812 dev_err(hba->dev,
6813 "%s: peer availabele lanes are not equal to connected lanes\n",
6814 __func__);
6815 ret = -EINVAL;
6816 goto out;
6817 }
7eb584db 6818 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8643ae66 6819 if (ret) {
7eb584db
DR		 6820 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
6821 __func__, ret);
8643ae66
DL		 6822 goto out;
6823 }
508cb48c 6824
6825 if (hba->max_pwr_info.info.pwr_rx == FAST_MODE ||
6826 hba->max_pwr_info.info.pwr_tx == FAST_MODE ||
6827 hba->max_pwr_info.info.pwr_rx == FASTAUTO_MODE ||
6828 hba->max_pwr_info.info.pwr_tx == FASTAUTO_MODE)
6829 dev_info(hba->dev, "HS mode configured\n");
7eb584db 6830 }
57d104c1 6831
53c12d0e
YG		 6832 /* set the state as operational after switching to desired gear */
6833 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
a4b0e8a4 6834
57d104c1
SJ		 6835 /*
6836 * If we are in error handling context or in power management callbacks
6837 * context, no need to scan the host
6838 */
105e2d39 6839 if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress
6840 && !hba->async_resume) {
57d104c1
SJ		 6841 bool flag;
6842
6843 /* clear any previous UFS device information */
6844 memset(&hba->dev_info, 0, sizeof(hba->dev_info));
dc3c8d3a
YG		 6845 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
6846 QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
57d104c1 6847 hba->dev_info.f_power_on_wp_en = flag;
3441da7d 6848
3a4bf06d
YG		 6849 if (!hba->is_init_prefetch)
6850 ufshcd_init_icc_levels(hba);
6851
251f4e5f 6852 scsi_scan_host(hba->host);
6853
2a8fa600 6854 /* Add required well known logical units to scsi mid layer */
251f4e5f 6855 ret = ufshcd_scsi_add_wlus(hba);
6856 if (ret) {
6857 dev_warn(hba->dev, "%s failed to add w-lus %d\n",
6858 __func__, ret);
6859 ret = 0;
6860 }
2a8fa600 6861
0701e49d
SJ		 6862 /* Initialize devfreq after UFS device is detected */
6863 if (ufshcd_is_clkscaling_supported(hba)) {
6864 memcpy(&hba->clk_scaling.saved_pwr_info.info,
6865 &hba->pwr_info,
6866 sizeof(struct ufs_pa_layer_attr));
6867 hba->clk_scaling.saved_pwr_info.is_valid = true;
6868 if (!hba->devfreq) {
6869 hba->devfreq = devm_devfreq_add_device(hba->dev,
6870 &ufs_devfreq_profile,
6871 "simple_ondemand",
6872 NULL);
6873 if (IS_ERR(hba->devfreq)) {
6874 ret = PTR_ERR(hba->devfreq);
6875 dev_err(hba->dev, "Unable to register with devfreq %d\n",
6876 ret);
6877 goto out;
6878 }
6879 }
6880 hba->clk_scaling.is_allowed = true;
6881 }
6882
3441da7d
SRT		 6883 pm_runtime_put_sync(hba->dev);
6884 }
3a4bf06d 6885
071b73ac 6886 hba->host->wlun_clr_uac = true;
3a4bf06d
YG		 6887 if (!hba->is_init_prefetch)
6888 hba->is_init_prefetch = true;
6889
5a0b0cb9 6890out:
251f4e5f 6891 if (ret && re_cnt++ < UFS_LINK_SETUP_RETRIES) {
6892 dev_err(hba->dev, "%s failed with err %d, retrying:%d\n",
6893 __func__, ret, re_cnt);
623b5fe3 6894 goto retry;
19447496 6895 } else if (ret && re_cnt >= UFS_LINK_SETUP_RETRIES) {
6896 dev_err(hba->dev, "%s failed after retries with err %d\n",
6897 __func__, ret);
6898 exynos_ufs_dump_uic_info(hba);
2bfd4b44 6899 spin_lock_irqsave(hba->host->host_lock, flags);
0ead1777 6900 hba->ufshcd_state = UFSHCD_STATE_ERROR;
2bfd4b44 6901 spin_unlock_irqrestore(hba->host->host_lock, flags);
623b5fe3 6902 }
0ead1777 6903
1d337ec2
SRT		 6904 /*
6905 * If we failed to initialize the device or the device is not
6906 * present, turn off the power/clocks etc.
6907 */
57d104c1
SJ		 6908 if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
6909 pm_runtime_put_sync(hba->dev);
1d337ec2 6910 ufshcd_hba_exit(hba);
57d104c1 6911 }
1d337ec2 6912
7ff5ab47
SJ		 6913 trace_ufshcd_init(dev_name(hba->dev), ret,
6914 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 6915 hba->curr_dev_pwr_mode, hba->uic_link_state);
65c13297 6916
6917 if (!ret) {
6918 /*
6919 * Inform scsi mid-layer that we did reset and allow to handle
6920 * Unit Attention properly.
6921 */
6922 spin_lock_irqsave(hba->host->host_lock, flags);
6923 scsi_report_bus_reset(hba->host, 0);
6924 spin_unlock_irqrestore(hba->host->host_lock, flags);
6925 }
9632ac5f 6926
6927 hba->async_resume = false;
6928
1d337ec2
SRT		 6929 return ret;
6930}
6931
6932/**
6933 * ufshcd_async_scan - asynchronous execution for probing hba
6934 * @data: data pointer to pass to this function
6935 * @cookie: cookie data
6936 */
6937static void ufshcd_async_scan(void *data, async_cookie_t cookie)
6938{
6939 struct ufs_hba *hba = (struct ufs_hba *)data;
105e2d39 6940 int err = 0;
6941
6942 if (hba->async_resume) {
6943 scsi_block_requests(hba->host);
6944 err = ufshcd_probe_hba(hba);
6945 if (err)
6946 goto err;
1d337ec2 6947
105e2d39 6948 if (!ufshcd_is_ufs_dev_active(hba)) {
6949 scsi_unblock_requests(hba->host);
6950 ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
6951 scsi_block_requests(hba->host);
6952 }
6953
6954 /*
6955 * If BKOPs operations are urgently needed at this moment then
6956 * keep auto-bkops enabled or else disable it.
6957 */
6958 ufshcd_urgent_bkops(hba);
6959err:
6960 scsi_unblock_requests(hba->host);
6961 } else {
6962 ufshcd_probe_hba(hba);
6963 }
6ccf44fe
SJ		 6964}
6965
f550c65b
YG		 6966static enum blk_eh_timer_return ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
6967{
6968 unsigned long flags;
6969 struct Scsi_Host *host;
6970 struct ufs_hba *hba;
6971 int index;
6972 bool found = false;
6973
6974 if (!scmd || !scmd->device || !scmd->device->host)
6975 return BLK_EH_NOT_HANDLED;
6976
6977 host = scmd->device->host;
6978 hba = shost_priv(host);
6979 if (!hba)
6980 return BLK_EH_NOT_HANDLED;
6981
6982 spin_lock_irqsave(host->host_lock, flags);
6983
6984 for_each_set_bit(index, &hba->outstanding_reqs, hba->nutrs) {
6985 if (hba->lrb[index].cmd == scmd) {
6986 found = true;
6987 break;
6988 }
6989 }
6990
6991 spin_unlock_irqrestore(host->host_lock, flags);
6992
6993 /*
6994 * Bypass SCSI error handling and reset the block layer timer if this
6995 * SCSI command was not actually dispatched to UFS driver, otherwise
6996 * let SCSI layer handle the error as usual.
6997 */
6998 return found ? BLK_EH_NOT_HANDLED : BLK_EH_RESET_TIMER;
6999}
7000
c2e6ab68 7001/**
7002 * ufshcd_query_ioctl - perform user read queries
7003 * @hba: per-adapter instance
7004 * @lun: used for lun specific queries
7005 * @buffer: user space buffer for reading and submitting query data and params
7006 * @return: 0 for success negative error code otherwise
7007 *
7008 * Expected/Submitted buffer structure is struct ufs_ioctl_query_data.
7009 * It will read the opcode, idn and buf_length parameters, and, put the
7010 * response in the buffer field while updating the used size in buf_length.
7011 */
7012static int ufshcd_query_ioctl(struct ufs_hba *hba, u8 lun, void __user *buffer)
7013{
7014 struct ufs_ioctl_query_data *ioctl_data;
7015 int err = 0;
7016 int length = 0;
7017 void *data_ptr;
7018 bool flag;
7019 u32 att;
7020 u8 index;
7021 u8 *desc = NULL;
7022
7023 ioctl_data = kzalloc(sizeof(struct ufs_ioctl_query_data), GFP_KERNEL);
7024 if (!ioctl_data) {
7025 dev_err(hba->dev, "%s: Failed allocating %zu bytes\n", __func__,
7026 sizeof(struct ufs_ioctl_query_data));
7027 err = -ENOMEM;
7028 goto out;
7029 }
7030
7031 /* extract params from user buffer */
7032 err = copy_from_user(ioctl_data, buffer,
7033 sizeof(struct ufs_ioctl_query_data));
7034 if (err) {
7035 dev_err(hba->dev,
7036 "%s: Failed copying buffer from user, err %d\n",
7037 __func__, err);
7038 goto out_release_mem;
7039 }
7040
7041 /* verify legal parameters & send query */
7042 switch (ioctl_data->opcode) {
7043 case UPIU_QUERY_OPCODE_READ_DESC:
7044 switch (ioctl_data->idn) {
7045 case QUERY_DESC_IDN_DEVICE:
7046 case QUERY_DESC_IDN_CONFIGURATION:
7047 case QUERY_DESC_IDN_INTERCONNECT:
7048 case QUERY_DESC_IDN_GEOMETRY:
7049 case QUERY_DESC_IDN_POWER:
7050 case QUERY_DESC_IDN_HEALTH:
7051 index = 0;
7052 break;
7053 case QUERY_DESC_IDN_UNIT:
7054 if (!ufs_is_valid_unit_desc_lun(lun)) {
7055 dev_err(hba->dev,
7056 "%s: No unit descriptor for lun 0x%x\n",
7057 __func__, lun);
7058 err = -EINVAL;
7059 goto out_release_mem;
7060 }
7061 index = lun;
7062 break;
7063 default:
7064 goto out_einval;
7065 }
7066 length = min_t(int, QUERY_DESC_MAX_SIZE,
7067 ioctl_data->buf_size);
7068 desc = kzalloc(length, GFP_KERNEL);
7069 if (!desc) {
7070 dev_err(hba->dev, "%s: Failed allocating %d bytes\n",
7071 __func__, length);
7072 err = -ENOMEM;
7073 goto out_release_mem;
7074 }
7075 err = ufshcd_query_descriptor_retry(hba, ioctl_data->opcode,
7076 ioctl_data->idn, index, 0, desc, &length);
7077 break;
7078 case UPIU_QUERY_OPCODE_READ_ATTR:
7079 switch (ioctl_data->idn) {
7080 case QUERY_ATTR_IDN_BOOT_LU_EN:
7081 case QUERY_ATTR_IDN_POWER_MODE:
7082 case QUERY_ATTR_IDN_ACTIVE_ICC_LVL:
7083 case QUERY_ATTR_IDN_OOO_DATA_EN:
7084 case QUERY_ATTR_IDN_BKOPS_STATUS:
7085 case QUERY_ATTR_IDN_PURGE_STATUS:
7086 case QUERY_ATTR_IDN_MAX_DATA_IN:
7087 case QUERY_ATTR_IDN_MAX_DATA_OUT:
7088 case QUERY_ATTR_IDN_REF_CLK_FREQ:
7089 case QUERY_ATTR_IDN_CONF_DESC_LOCK:
7090 case QUERY_ATTR_IDN_MAX_NUM_OF_RTT:
7091 case QUERY_ATTR_IDN_EE_CONTROL:
7092 case QUERY_ATTR_IDN_EE_STATUS:
7093 case QUERY_ATTR_IDN_SECONDS_PASSED:
7094 index = 0;
7095 break;
7096 case QUERY_ATTR_IDN_DYN_CAP_NEEDED:
7097 case QUERY_ATTR_IDN_CORR_PRG_BLK_NUM:
7098 index = lun;
7099 break;
7100 default:
7101 goto out_einval;
7102 }
7103 err = ufshcd_query_attr_retry(hba, ioctl_data->opcode,
7104 ioctl_data->idn, index, 0, &att);
7105 break;
7106 case UPIU_QUERY_OPCODE_READ_FLAG:
7107 switch (ioctl_data->idn) {
7108 case QUERY_FLAG_IDN_FDEVICEINIT:
7109 case QUERY_FLAG_IDN_PERMANENT_WPE:
7110 case QUERY_FLAG_IDN_PWR_ON_WPE:
7111 case QUERY_FLAG_IDN_BKOPS_EN:
7112 case QUERY_FLAG_IDN_PURGE_ENABLE:
7113 case QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL:
7114 case QUERY_FLAG_IDN_BUSY_RTC:
7115 break;
7116 default:
7117 goto out_einval;
7118 }
7119 err = ufshcd_query_flag_retry(hba, ioctl_data->opcode,
7120 ioctl_data->idn, &flag);
7121 break;
7122 default:
7123 goto out_einval;
7124 }
7125
7126 if (err) {
7127 dev_err(hba->dev, "%s: Query for idn %d failed\n", __func__,
7128 ioctl_data->idn);
7129 goto out_release_mem;
7130 }
7131
7132 /*
7133 * copy response data
7134 * As we might end up reading less data then what is specified in
7135 * "ioct_data->buf_size". So we are updating "ioct_data->
7136 * buf_size" to what exactly we have read.
7137 */
7138 switch (ioctl_data->opcode) {
7139 case UPIU_QUERY_OPCODE_READ_DESC:
7140 ioctl_data->buf_size = min_t(int, ioctl_data->buf_size, length);
7141 data_ptr = desc;
7142 break;
7143 case UPIU_QUERY_OPCODE_READ_ATTR:
7144 ioctl_data->buf_size = sizeof(u32);
7145 data_ptr = &att;
7146 break;
7147 case UPIU_QUERY_OPCODE_READ_FLAG:
7148 ioctl_data->buf_size = 1;
7149 data_ptr = &flag;
7150 break;
7151 default:
7152 BUG_ON(true);
7153 }
7154
7155 /* copy to user */
7156 err = copy_to_user(buffer, ioctl_data,
7157 sizeof(struct ufs_ioctl_query_data));
7158 if (err)
7159 dev_err(hba->dev, "%s: Failed copying back to user.\n",
7160 __func__);
7161 err = copy_to_user(buffer + sizeof(struct ufs_ioctl_query_data),
7162 data_ptr, ioctl_data->buf_size);
7163 if (err)
7164 dev_err(hba->dev, "%s: err %d copying back to user.\n",
7165 __func__, err);
7166 goto out_release_mem;
7167
7168out_einval:
7169 dev_err(hba->dev,
7170 "%s: illegal ufs query ioctl data, opcode 0x%x, idn 0x%x\n",
7171 __func__, ioctl_data->opcode, (unsigned int)ioctl_data->idn);
7172 err = -EINVAL;
7173out_release_mem:
7174 kfree(ioctl_data);
7175 kfree(desc);
7176out:
7177 return err;
7178}
7179
7180/**
7181 * ufshcd_ioctl - ufs ioctl callback registered in scsi_host
7182 * @dev: scsi device required for per LUN queries
7183 * @cmd: command opcode
7184 * @buffer: user space buffer for transferring data
7185 *
7186 * Supported commands:
7187 * UFS_IOCTL_QUERY
7188 */
7189static int ufshcd_ioctl(struct scsi_device *dev, int cmd, void __user *buffer)
7190{
7191 struct ufs_hba *hba = shost_priv(dev->host);
7192 int err = 0;
7193
7194 BUG_ON(!hba);
7195 if (!buffer) {
7196 if (cmd != SCSI_UFS_REQUEST_SENSE) {
7197 dev_err(hba->dev, "%s: User buffer is NULL!\n", __func__);
7198 return -EINVAL;
7199 }
7200 }
7201 switch (cmd) {
7202 case SCSI_UFS_REQUEST_SENSE:
7203 err = ufshcd_send_request_sense(hba, hba->sdev_rpmb);
7204 if (err) {
7205 dev_warn(hba->dev, "%s failed to clear uac on rpmb(w-lu) %d\n",
7206 __func__, err);
7207 }
7208 hba->host->wlun_clr_uac = false;
7209 break;
7210 case UFS_IOCTL_QUERY:
7211 //pm_runtime_get_sync(hba->dev);
7212 err = ufshcd_query_ioctl(hba, ufshcd_scsi_to_upiu_lun(dev->lun),
7213 buffer);
7214 //pm_runtime_put_sync(hba->dev);
7215 break;
7216 case UFS_IOCTL_BLKROSET:
7217 err = -ENOIOCTLCMD;
7218 break;
7219 default:
7220 err = -EINVAL;
7221 dev_err(hba->dev, "%s: Illegal ufs-IOCTL cmd %d\n", __func__,
7222 cmd);
7223 break;
7224 }
7225
7226 return err;
7227}
7a3e97b0
SY		 7228static struct scsi_host_template ufshcd_driver_template = {
7229 .module = THIS_MODULE,
7230 .name = UFSHCD,
7231 .proc_name = UFSHCD,
7232 .queuecommand = ufshcd_queuecommand,
7233 .slave_alloc = ufshcd_slave_alloc,
eeda4749 7234 .slave_configure = ufshcd_slave_configure,
7a3e97b0 7235 .slave_destroy = ufshcd_slave_destroy,
4264fd61 7236 .change_queue_depth = ufshcd_change_queue_depth,
7a3e97b0 7237 .eh_abort_handler = ufshcd_abort,
3441da7d
SRT		 7238 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
7239 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
f550c65b 7240 .eh_timed_out = ufshcd_eh_timed_out,
7a3e97b0
SY		 7241 .this_id = -1,
7242 .sg_tablesize = SG_ALL,
7243 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
7244 .can_queue = UFSHCD_CAN_QUEUE,
1ab27c9c 7245 .max_host_blocked = 1,
0f7f11ff 7246 .skip_settle_delay = 1,
c40ecc12 7247 .track_queue_depth = 1,
7a3e97b0
SY		 7248};
7249
57d104c1
SJ		 7250static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
7251 int ua)
7252{
7b16a07c 7253 int ret;
57d104c1 7254
7b16a07c
BA		 7255 if (!vreg)
7256 return 0;
57d104c1 7257
7b16a07c
BA		 7258 ret = regulator_set_load(vreg->reg, ua);
7259 if (ret < 0) {
7260 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
7261 __func__, vreg->name, ua, ret);
57d104c1
SJ		 7262 }
7263
7264 return ret;
7265}
7266
7267static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
7268 struct ufs_vreg *vreg)
7269{
60f01870
YG		 7270 if (!vreg)
7271 return 0;
7272 else if (vreg->unused)
7273 return 0;
7274 else
7275 return ufshcd_config_vreg_load(hba->dev, vreg,
7276 UFS_VREG_LPM_LOAD_UA);
57d104c1
SJ		 7277}
7278
7279static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
7280 struct ufs_vreg *vreg)
7281{
60f01870
YG		 7282 if (!vreg)
7283 return 0;
7284 else if (vreg->unused)
7285 return 0;
7286 else
7287 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
57d104c1
SJ		 7288}
7289
aa497613
SRT		 7290static int ufshcd_config_vreg(struct device *dev,
7291 struct ufs_vreg *vreg, bool on)
7292{
7293 int ret = 0;
6c27a40c
GS		 7294 struct regulator *reg;
7295 const char *name;
aa497613
SRT		 7296 int min_uV, uA_load;
7297
7298 BUG_ON(!vreg);
7299
6c27a40c
GS		 7300 reg = vreg->reg;
7301 name = vreg->name;
7302
aa497613
SRT		 7303 if (regulator_count_voltages(reg) > 0) {
7304 min_uV = on ? vreg->min_uV : 0;
7305 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
7306 if (ret) {
7307 dev_err(dev, "%s: %s set voltage failed, err=%d\n",
7308 __func__, name, ret);
7309 goto out;
7310 }
7311
7312 uA_load = on ? vreg->max_uA : 0;
57d104c1
SJ		 7313 ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
7314 if (ret)
aa497613 7315 goto out;
aa497613
SRT		 7316 }
7317out:
7318 return ret;
7319}
7320
7321static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
7322{
7323 int ret = 0;
7324
60f01870
YG		 7325 if (!vreg)
7326 goto out;
7327 else if (vreg->enabled || vreg->unused)
aa497613
SRT		 7328 goto out;
7329
7330 ret = ufshcd_config_vreg(dev, vreg, true);
7331 if (!ret)
7332 ret = regulator_enable(vreg->reg);
7333
7334 if (!ret)
7335 vreg->enabled = true;
7336 else
7337 dev_err(dev, "%s: %s enable failed, err=%d\n",
7338 __func__, vreg->name, ret);
7339out:
7340 return ret;
7341}
7342
7343static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
7344{
7345 int ret = 0;
7346
60f01870
YG		 7347 if (!vreg)
7348 goto out;
7349 else if (!vreg->enabled || vreg->unused)
aa497613
SRT		 7350 goto out;
7351
7352 ret = regulator_disable(vreg->reg);
7353
7354 if (!ret) {
7355 /* ignore errors on applying disable config */
7356 ufshcd_config_vreg(dev, vreg, false);
7357 vreg->enabled = false;
7358 } else {
7359 dev_err(dev, "%s: %s disable failed, err=%d\n",
7360 __func__, vreg->name, ret);
7361 }
7362out:
7363 return ret;
7364}
7365
7366static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
7367{
7368 int ret = 0;
7369 struct device *dev = hba->dev;
7370 struct ufs_vreg_info *info = &hba->vreg_info;
7371
7372 if (!info)
7373 goto out;
7374
7375 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
7376 if (ret)
7377 goto out;
7378
7379 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
7380 if (ret)
7381 goto out;
7382
7383 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
7384 if (ret)
7385 goto out;
7386
7387out:
7388 if (ret) {
7389 ufshcd_toggle_vreg(dev, info->vccq2, false);
7390 ufshcd_toggle_vreg(dev, info->vccq, false);
7391 ufshcd_toggle_vreg(dev, info->vcc, false);
7392 }
7393 return ret;
7394}
7395
6a771a65
RS		 7396static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
7397{
7398 struct ufs_vreg_info *info = &hba->vreg_info;
7399
7400 if (info)
7401 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
7402
7403 return 0;
7404}
7405
aa497613
SRT		 7406static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
7407{
7408 int ret = 0;
7409
7410 if (!vreg)
7411 goto out;
7412
7413 vreg->reg = devm_regulator_get(dev, vreg->name);
7414 if (IS_ERR(vreg->reg)) {
7415 ret = PTR_ERR(vreg->reg);
7416 dev_err(dev, "%s: %s get failed, err=%d\n",
7417 __func__, vreg->name, ret);
7418 }
7419out:
7420 return ret;
7421}
7422
7423static int ufshcd_init_vreg(struct ufs_hba *hba)
7424{
7425 int ret = 0;
7426 struct device *dev = hba->dev;
7427 struct ufs_vreg_info *info = &hba->vreg_info;
7428
7429 if (!info)
7430 goto out;
7431
7432 ret = ufshcd_get_vreg(dev, info->vcc);
7433 if (ret)
7434 goto out;
7435
7436 ret = ufshcd_get_vreg(dev, info->vccq);
7437 if (ret)
7438 goto out;
7439
7440 ret = ufshcd_get_vreg(dev, info->vccq2);
7441out:
7442 return ret;
7443}
7444
6a771a65
RS		 7445static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
7446{
7447 struct ufs_vreg_info *info = &hba->vreg_info;
7448
7449 if (info)
7450 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
7451
7452 return 0;
7453}
7454
60f01870
YG		 7455static int ufshcd_set_vccq_rail_unused(struct ufs_hba *hba, bool unused)
7456{
7457 int ret = 0;
7458 struct ufs_vreg_info *info = &hba->vreg_info;
7459
7460 if (!info)
7461 goto out;
7462 else if (!info->vccq)
7463 goto out;
7464
7465 if (unused) {
7466 /* shut off the rail here */
7467 ret = ufshcd_toggle_vreg(hba->dev, info->vccq, false);
7468 /*
7469 * Mark this rail as no longer used, so it doesn't get enabled
7470 * later by mistake
7471 */
7472 if (!ret)
7473 info->vccq->unused = true;
7474 } else {
7475 /*
7476 * rail should have been already enabled hence just make sure
7477 * that unused flag is cleared.
7478 */
7479 info->vccq->unused = false;
7480 }
7481out:
7482 return ret;
7483}
7484
57d104c1
SJ		 7485static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
7486 bool skip_ref_clk)
c6e79dac
SRT		 7487{
7488 int ret = 0;
7489 struct ufs_clk_info *clki;
7490 struct list_head *head = &hba->clk_list_head;
8214b377 7491 const char *ref_clk = "ref_clk";
1ab27c9c 7492 unsigned long flags;
911a0771
SJ		 7493 ktime_t start = ktime_get();
7494 bool clk_state_changed = false;
c6e79dac 7495
566ec9ad 7496 if (list_empty(head))
c6e79dac
SRT		 7497 goto out;
7498
96495cde 7499 ufshcd_vops_pre_setup_clocks(hba, on);
1e879e8f 7500
c6e79dac
SRT		 7501 list_for_each_entry(clki, head, list) {
7502 if (!IS_ERR_OR_NULL(clki->clk)) {
8214b377 7503 if (skip_ref_clk &&
7504 !strncmp(clki->name, ref_clk, strlen(ref_clk)))
57d104c1
SJ		 7505 continue;
7506
911a0771 7507 clk_state_changed = on ^ clki->enabled;
c6e79dac
SRT		 7508 if (on && !clki->enabled) {
7509 ret = clk_prepare_enable(clki->clk);
7510 if (ret) {
7511 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
7512 __func__, clki->name, ret);
7513 goto out;
7514 }
7515 } else if (!on && clki->enabled) {
7516 clk_disable_unprepare(clki->clk);
7517 }
7518 clki->enabled = on;
7519 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
7520 clki->name, on ? "en" : "dis");
7521 }
7522 }
1ab27c9c 7523
1e879e8f
SJ		 7524 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
7525 if (ret)
7526 return ret;
7527
c6e79dac
SRT		 7528out:
7529 if (ret) {
7530 list_for_each_entry(clki, head, list) {
7531 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
7532 clk_disable_unprepare(clki->clk);
7533 }
7ff5ab47 7534 } else if (!ret && on) {
1ab27c9c
ST		 7535 spin_lock_irqsave(hba->host->host_lock, flags);
7536 hba->clk_gating.state = CLKS_ON;
7ff5ab47
SJ		 7537 trace_ufshcd_clk_gating(dev_name(hba->dev),
7538 hba->clk_gating.state);
1ab27c9c 7539 spin_unlock_irqrestore(hba->host->host_lock, flags);
c6e79dac 7540 }
7ff5ab47 7541
911a0771
SJ		 7542 if (clk_state_changed)
7543 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
7544 (on ? "on" : "off"),
7545 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
c6e79dac
SRT		 7546 return ret;
7547}
7548
57d104c1
SJ		 7549static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
7550{
7551 return __ufshcd_setup_clocks(hba, on, false);
7552}
7553
c6e79dac
SRT		 7554static int ufshcd_init_clocks(struct ufs_hba *hba)
7555{
7556 int ret = 0;
7557 struct ufs_clk_info *clki;
7558 struct device *dev = hba->dev;
7559 struct list_head *head = &hba->clk_list_head;
7560
566ec9ad 7561 if (list_empty(head))
c6e79dac
SRT		 7562 goto out;
7563
7564 list_for_each_entry(clki, head, list) {
7565 if (!clki->name)
7566 continue;
7567
7568 clki->clk = devm_clk_get(dev, clki->name);
7569 if (IS_ERR(clki->clk)) {
7570 ret = PTR_ERR(clki->clk);
7571 dev_err(dev, "%s: %s clk get failed, %d\n",
7572 __func__, clki->name, ret);
7573 goto out;
7574 }
7575
7576 if (clki->max_freq) {
7577 ret = clk_set_rate(clki->clk, clki->max_freq);
7578 if (ret) {
7579 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
7580 __func__, clki->name,
7581 clki->max_freq, ret);
7582 goto out;
7583 }
b393aa4d 7584#if defined(CONFIG_PM_DEVFREQ)
856b3483 7585 clki->curr_freq = clki->max_freq;
b393aa4d 7586#endif
c6e79dac
SRT		 7587 }
7588 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
7589 clki->name, clk_get_rate(clki->clk));
7590 }
7591out:
7592 return ret;
7593}
7594
5c0c28a8
SRT		 7595static int ufshcd_variant_hba_init(struct ufs_hba *hba)
7596{
7597 int err = 0;
7598
7599 if (!hba->vops)
7600 goto out;
7601
0263bcd0
YG		 7602 err = ufshcd_vops_init(hba);
7603 if (err)
7604 goto out;
5c0c28a8 7605
0263bcd0
YG		 7606 err = ufshcd_vops_setup_regulators(hba, true);
7607 if (err)
7608 goto out_exit;
5c0c28a8
SRT		 7609
7610 goto out;
7611
5c0c28a8 7612out_exit:
0263bcd0 7613 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7614out:
7615 if (err)
7616 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
0263bcd0 7617 __func__, ufshcd_get_var_name(hba), err);
5c0c28a8
SRT		 7618 return err;
7619}
7620
7621static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
7622{
7623 if (!hba->vops)
7624 return;
7625
0263bcd0 7626 ufshcd_vops_setup_regulators(hba, false);
5c0c28a8 7627
0263bcd0 7628 ufshcd_vops_exit(hba);
5c0c28a8
SRT		 7629}
7630
aa497613
SRT		 7631static int ufshcd_hba_init(struct ufs_hba *hba)
7632{
7633 int err;
7634
6a771a65
RS		 7635 /*
7636 * Handle host controller power separately from the UFS device power
7637 * rails as it will help controlling the UFS host controller power
7638 * collapse easily which is different than UFS device power collapse.
7639 * Also, enable the host controller power before we go ahead with rest
7640 * of the initialization here.
7641 */
7642 err = ufshcd_init_hba_vreg(hba);
aa497613
SRT		 7643 if (err)
7644 goto out;
7645
6a771a65 7646 err = ufshcd_setup_hba_vreg(hba, true);
aa497613
SRT		 7647 if (err)
7648 goto out;
7649
6a771a65
RS		 7650 err = ufshcd_init_clocks(hba);
7651 if (err)
7652 goto out_disable_hba_vreg;
7653
7654 err = ufshcd_setup_clocks(hba, true);
7655 if (err)
7656 goto out_disable_hba_vreg;
7657
c6e79dac
SRT		 7658 err = ufshcd_init_vreg(hba);
7659 if (err)
7660 goto out_disable_clks;
7661
7662 err = ufshcd_setup_vreg(hba, true);
7663 if (err)
7664 goto out_disable_clks;
7665
aa497613
SRT		 7666 err = ufshcd_variant_hba_init(hba);
7667 if (err)
7668 goto out_disable_vreg;
7669
1d337ec2 7670 hba->is_powered = true;
aa497613
SRT		 7671 goto out;
7672
7673out_disable_vreg:
7674 ufshcd_setup_vreg(hba, false);
c6e79dac
SRT		 7675out_disable_clks:
7676 ufshcd_setup_clocks(hba, false);
6a771a65
RS		 7677out_disable_hba_vreg:
7678 ufshcd_setup_hba_vreg(hba, false);
aa497613
SRT		 7679out:
7680 return err;
7681}
7682
7683static void ufshcd_hba_exit(struct ufs_hba *hba)
7684{
1d337ec2
SRT		 7685 if (hba->is_powered) {
7686 ufshcd_variant_hba_exit(hba);
7687 ufshcd_setup_vreg(hba, false);
a508253d 7688 ufshcd_suspend_clkscaling(hba);
401f1e44 7689 if (ufshcd_is_clkscaling_supported(hba)) {
0701e49d
SJ		 7690 if (hba->devfreq)
7691 ufshcd_suspend_clkscaling(hba);
401f1e44
SJ		 7692 destroy_workqueue(hba->clk_scaling.workq);
7693 }
1d337ec2
SRT		 7694 ufshcd_setup_clocks(hba, false);
7695 ufshcd_setup_hba_vreg(hba, false);
7696 hba->is_powered = false;
7697 }
aa497613
SRT		 7698}
7699
57d104c1
SJ		 7700static int
7701ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
7702{
7703 unsigned char cmd[6] = {REQUEST_SENSE,
7704 0,
7705 0,
7706 0,
dcea0bfb 7707 UFSHCD_REQ_SENSE_SIZE,
57d104c1
SJ		 7708 0};
7709 char *buffer;
7710 int ret;
7711
dcea0bfb 7712 buffer = kzalloc(UFSHCD_REQ_SENSE_SIZE, GFP_KERNEL);
57d104c1
SJ		 7713 if (!buffer) {
7714 ret = -ENOMEM;
7715 goto out;
7716 }
7717
fcbfffe2
CH		 7718 ret = scsi_execute(sdp, cmd, DMA_FROM_DEVICE, buffer,
7719 UFSHCD_REQ_SENSE_SIZE, NULL, NULL,
7720 msecs_to_jiffies(1000), 3, 0, RQF_PM, NULL);
57d104c1
SJ		 7721 if (ret)
7722 pr_err("%s: failed with err %d\n", __func__, ret);
7723
7724 kfree(buffer);
7725out:
7726 return ret;
7727}
7728
7729/**
7730 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
7731 * power mode
7732 * @hba: per adapter instance
7733 * @pwr_mode: device power mode to set
7734 *
7735 * Returns 0 if requested power mode is set successfully
7736 * Returns non-zero if failed to set the requested power mode
7737 */
7738static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
7739 enum ufs_dev_pwr_mode pwr_mode)
7740{
7741 unsigned char cmd[6] = { START_STOP };
7742 struct scsi_sense_hdr sshdr;
7c48bfd0
AM		 7743 struct scsi_device *sdp;
7744 unsigned long flags;
57d104c1
SJ		 7745 int ret;
7746
7c48bfd0
AM		 7747 spin_lock_irqsave(hba->host->host_lock, flags);
7748 sdp = hba->sdev_ufs_device;
7749 if (sdp) {
7750 ret = scsi_device_get(sdp);
7751 if (!ret && !scsi_device_online(sdp)) {
7752 ret = -ENODEV;
7753 scsi_device_put(sdp);
7754 }
7755 } else {
7756 ret = -ENODEV;
7757 }
7758 spin_unlock_irqrestore(hba->host->host_lock, flags);
7759
7760 if (ret)
7761 return ret;
57d104c1
SJ		 7762
7763 /*
7764 * If scsi commands fail, the scsi mid-layer schedules scsi error-
7765 * handling, which would wait for host to be resumed. Since we know
7766 * we are functional while we are here, skip host resume in error
7767 * handling context.
7768 */
7769 hba->host->eh_noresume = 1;
7770 if (hba->wlun_dev_clr_ua) {
7771 ret = ufshcd_send_request_sense(hba, sdp);
7772 if (ret)
7773 goto out;
7774 /* Unit attention condition is cleared now */
7775 hba->wlun_dev_clr_ua = false;
7776 }
7777
7778 cmd[4] = pwr_mode << 4;
7779
7780 /*
7781 * Current function would be generally called from the power management
e8064021 7782 * callbacks hence set the RQF_PM flag so that it doesn't resume the
57d104c1
SJ		 7783 * already suspended childs.
7784 */
fcbfffe2
CH		 7785 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
7786 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
57d104c1
SJ		 7787 if (ret) {
7788 sdev_printk(KERN_WARNING, sdp,
ef61329d
HR		 7789 "START_STOP failed for power mode: %d, result %x\n",
7790 pwr_mode, ret);
21045519
HR		 7791 if (driver_byte(ret) & DRIVER_SENSE)
7792 scsi_print_sense_hdr(sdp, NULL, &sshdr);
57d104c1
SJ		 7793 }
7794
7795 if (!ret)
7796 hba->curr_dev_pwr_mode = pwr_mode;
7797out:
7c48bfd0 7798 scsi_device_put(sdp);
57d104c1
SJ		 7799 hba->host->eh_noresume = 0;
7800 return ret;
7801}
7802
7803static int ufshcd_link_state_transition(struct ufs_hba *hba,
7804 enum uic_link_state req_link_state,
7805 int check_for_bkops)
7806{
7807 int ret = 0;
7808
7809 if (req_link_state == hba->uic_link_state)
7810 return 0;
7811
9c07a889 7812 if (req_link_state == UIC_LINK_HIBERN8_STATE ||
7813 req_link_state == UIC_LINK_OFF_STATE) {
5801290e 7814 ufshcd_set_link_trans_hibern8(hba);
0f7f11ff 7815 ret = ufshcd_link_hibern8_ctrl(hba, true);
57d104c1
SJ		 7816 if (!ret)
7817 ufshcd_set_link_hibern8(hba);
5801290e 7818 else {
40e137af 7819 unsigned long flags;
7820 bool saved_is_suspended = hba->clk_gating.is_suspended;
7821
7822 spin_lock_irqsave(hba->host->host_lock, flags);
7823 hba->clk_gating.state = __CLKS_ON;
7824 spin_unlock_irqrestore(hba->host->host_lock, flags);
7825
7826 hba->clk_gating.is_suspended = true;
66a35665 7827 ufshcd_host_reset_and_restore(hba);
40e137af 7828 spin_lock_irqsave(hba->host->host_lock, flags);
7829 hba->clk_gating.state = CLKS_ON;
7830 spin_unlock_irqrestore(hba->host->host_lock, flags);
7831 hba->clk_gating.is_suspended = saved_is_suspended;
7832
57d104c1 7833 goto out;
9c07a889 7834 }
7835
7836
57d104c1 7837 /*
9c07a889 7838 * If autobkops is enabled, link can't be turned off because
7839 * turning off the link would also turn off the device.
57d104c1 7840 */
9c07a889 7841 if ((req_link_state == UIC_LINK_OFF_STATE) &&
7842 (!check_for_bkops || (check_for_bkops &&
7843 !hba->auto_bkops_enabled))) {
7844 unsigned long flags;
7845
7846 /*
7847 * Change controller state to "reset state" which
7848 * should also put the link in off/reset state
7849 */
7850
2bfd4b44 7851 spin_lock_irqsave(hba->host->host_lock, flags);
7852 hba->ufshcd_state = UFSHCD_STATE_RESET;
7853 ufshcd_hba_stop(hba, true);
7854 spin_unlock_irqrestore(hba->host->host_lock, flags);
9c07a889 7855 /*
7856 * TODO: Check if we need any delay to make sure that
7857 * controller is reset
7858 */
7859 ufshcd_set_link_off(hba);
7860 }
57d104c1
SJ		 7861 }
7862
7863out:
7864 return ret;
7865}
7866
7867static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
7868{
b799fdf7
YG		 7869 /*
7870 * It seems some UFS devices may keep drawing more than sleep current
7871 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
7872 * To avoid this situation, add 2ms delay before putting these UFS
7873 * rails in LPM mode.
7874 */
7875 if (!ufshcd_is_link_active(hba) &&
7876 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
7877 usleep_range(2000, 2100);
7878
57d104c1
SJ		 7879 /*
7880 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
7881 * power.
7882 *
7883 * If UFS device and link is in OFF state, all power supplies (VCC,
7884 * VCCQ, VCCQ2) can be turned off if power on write protect is not
7885 * required. If UFS link is inactive (Hibern8 or OFF state) and device
7886 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
7887 *
7888 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
7889 * in low power state which would save some power.
7890 */
7891 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7892 !hba->dev_info.is_lu_power_on_wp) {
7893 ufshcd_setup_vreg(hba, false);
7894 } else if (!ufshcd_is_ufs_dev_active(hba)) {
7895 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7896 if (!ufshcd_is_link_active(hba)) {
7897 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7898 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
7899 }
7900 }
7901}
7902
7903static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
7904{
7905 int ret = 0;
7906
7907 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
7908 !hba->dev_info.is_lu_power_on_wp) {
7909 ret = ufshcd_setup_vreg(hba, true);
7910 } else if (!ufshcd_is_ufs_dev_active(hba)) {
57d104c1
SJ		 7911 if (!ret && !ufshcd_is_link_active(hba)) {
7912 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
7913 if (ret)
7914 goto vcc_disable;
7915 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
7916 if (ret)
7917 goto vccq_lpm;
7918 }
69d72ac8 7919 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
57d104c1
SJ		 7920 }
7921 goto out;
7922
7923vccq_lpm:
7924 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
7925vcc_disable:
7926 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
7927out:
7928 return ret;
7929}
7930
7931static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
7932{
7933 if (ufshcd_is_link_off(hba))
7934 ufshcd_setup_hba_vreg(hba, false);
7935}
7936
7937static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
7938{
7939 if (ufshcd_is_link_off(hba))
7940 ufshcd_setup_hba_vreg(hba, true);
7941}
7942
7a3e97b0 7943/**
57d104c1 7944 * ufshcd_suspend - helper function for suspend operations
3b1d0580 7945 * @hba: per adapter instance
57d104c1
SJ		 7946 * @pm_op: desired low power operation type
7947 *
7948 * This function will try to put the UFS device and link into low power
7949 * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
7950 * (System PM level).
7951 *
7952 * If this function is called during shutdown, it will make sure that
7953 * both UFS device and UFS link is powered off.
7a3e97b0 7954 *
57d104c1
SJ		 7955 * NOTE: UFS device & link must be active before we enter in this function.
7956 *
7957 * Returns 0 for success and non-zero for failure
7a3e97b0 7958 */
57d104c1 7959static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 7960{
57d104c1
SJ		 7961 int ret = 0;
7962 enum ufs_pm_level pm_lvl;
7963 enum ufs_dev_pwr_mode req_dev_pwr_mode;
7964 enum uic_link_state req_link_state;
5801290e 7965 bool gating_allowed = !ufshcd_can_fake_clkgating(hba);
57d104c1
SJ		 7966
7967 hba->pm_op_in_progress = 1;
7968 if (!ufshcd_is_shutdown_pm(pm_op)) {
7969 pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
7970 hba->rpm_lvl : hba->spm_lvl;
7971 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
7972 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
7973 } else {
7974 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
7975 req_link_state = UIC_LINK_OFF_STATE;
7976 }
7977
7a3e97b0 7978 /*
57d104c1
SJ		 7979 * If we can't transition into any of the low power modes
7980 * just gate the clocks.
7a3e97b0 7981 */
1ab27c9c
ST		 7982 ufshcd_hold(hba, false);
7983 hba->clk_gating.is_suspended = true;
7984
401f1e44
SJ		 7985 if (hba->clk_scaling.is_allowed) {
7986 cancel_work_sync(&hba->clk_scaling.suspend_work);
7987 cancel_work_sync(&hba->clk_scaling.resume_work);
7988 ufshcd_suspend_clkscaling(hba);
7989 }
d6fcf81a 7990
57d104c1
SJ		 7991 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
7992 req_link_state == UIC_LINK_ACTIVE_STATE) {
7993 goto disable_clks;
7994 }
7a3e97b0 7995
57d104c1
SJ		 7996 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
7997 (req_link_state == hba->uic_link_state))
d6fcf81a 7998 goto enable_gating;
57d104c1
SJ		 7999
8000 /* UFS device & link must be active before we enter in this function */
8001 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8002 ret = -EINVAL;
d6fcf81a 8003 goto enable_gating;
57d104c1
SJ		 8004 }
8005
8006 if (ufshcd_is_runtime_pm(pm_op)) {
374a246e
SJ		 8007 if (ufshcd_can_autobkops_during_suspend(hba)) {
8008 /*
8009 * The device is idle with no requests in the queue,
8010 * allow background operations if bkops status shows
8011 * that performance might be impacted.
8012 */
8013 ret = ufshcd_urgent_bkops(hba);
8014 if (ret)
8015 goto enable_gating;
8016 } else {
8017 /* make sure that auto bkops is disabled */
8018 ufshcd_disable_auto_bkops(hba);
8019 }
57d104c1
SJ		 8020 }
8021
ce96cf1c 8022 if (ufshcd_is_shutdown_pm(pm_op))
8023 ufs_shutdown_state = 1;
8024
57d104c1
SJ		 8025 if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
8026 ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
8027 !ufshcd_is_runtime_pm(pm_op))) {
8028 /* ensure that bkops is disabled */
8029 ufshcd_disable_auto_bkops(hba);
8030 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
8031 if (ret)
1ab27c9c 8032 goto enable_gating;
57d104c1
SJ		 8033 }
8034
8035 ret = ufshcd_link_state_transition(hba, req_link_state, 1);
8036 if (ret)
8037 goto set_dev_active;
8038
57d104c1 8039disable_clks:
0f7f11ff 8040
8041 /*
8042 * Flush pending works before clock is disabled
8043 */
8044 cancel_work_sync(&hba->eh_work);
8045 cancel_work_sync(&hba->eeh_work);
8046
57d104c1 8047 /*
8214b377 8048 * Disable the host irq as host controller as there won't be any
8049 * host controller trasanction expected till resume.
57d104c1 8050 */
8214b377 8051 ufshcd_disable_irq(hba);
8052
cf632748 8053 ufshcd_vreg_set_lpm(hba);
8054 udelay(50);
57d104c1 8055
5801290e 8056 if (gating_allowed) {
8057 if (!ufshcd_is_link_active(hba))
8058 ufshcd_setup_clocks(hba, false);
8059 else
8060 /* If link is active, device ref_clk can't be switched off */
8061 __ufshcd_setup_clocks(hba, false, true);
8062 }
57d104c1 8063
1ab27c9c 8064 hba->clk_gating.state = CLKS_OFF;
7ff5ab47 8065 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
57d104c1 8066 /*
8214b377 8067 * Call vendor specific suspend callback. As these callbacks may access
8068 * vendor specific host controller register space call them before the
8069 * host clocks are ON.
57d104c1 8070 */
8214b377 8071 ret = ufshcd_vops_suspend(hba, pm_op);
8072 if (ret)
8073 goto set_link_active;
8074
8075
57d104c1
SJ		 8076 /* Put the host controller in low power mode if possible */
8077 ufshcd_hba_vreg_set_lpm(hba);
8078 goto out;
8079
57d104c1 8080set_link_active:
401f1e44
SJ		 8081 if (hba->clk_scaling.is_allowed)
8082 ufshcd_resume_clkscaling(hba);
5801290e 8083 if (ufshcd_is_link_hibern8(hba)) {
8084 ufshcd_set_link_trans_active(hba);
8085 if (!ufshcd_link_hibern8_ctrl(hba, false))
8086 ufshcd_set_link_active(hba);
8087 else
8088 ufshcd_set_link_off(hba);
8089 } else if (ufshcd_is_link_off(hba))
57d104c1
SJ		 8090 ufshcd_host_reset_and_restore(hba);
8091set_dev_active:
8092 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
8093 ufshcd_disable_auto_bkops(hba);
1ab27c9c 8094enable_gating:
401f1e44
SJ		 8095 if (hba->clk_scaling.is_allowed)
8096 ufshcd_resume_clkscaling(hba);
1ab27c9c
ST		 8097 hba->clk_gating.is_suspended = false;
8098 ufshcd_release(hba);
57d104c1
SJ		 8099out:
8100 hba->pm_op_in_progress = 0;
9632ac5f 8101
8102 if (hba->monitor.flag & UFSHCD_MONITOR_LEVEL1)
8103 dev_info(hba->dev, "UFS suspend done\n");
8104
57d104c1 8105 return ret;
7a3e97b0
SY		 8106}
8107
8108/**
57d104c1 8109 * ufshcd_resume - helper function for resume operations
3b1d0580 8110 * @hba: per adapter instance
57d104c1 8111 * @pm_op: runtime PM or system PM
7a3e97b0 8112 *
57d104c1
SJ		 8113 * This function basically brings the UFS device, UniPro link and controller
8114 * to active state.
8115 *
8116 * Returns 0 for success and non-zero for failure
7a3e97b0 8117 */
57d104c1 8118static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
7a3e97b0 8119{
57d104c1
SJ		 8120 int ret;
8121 enum uic_link_state old_link_state;
3bc47bcc 8122 enum ufs_pm_level pm_lvl;
5801290e 8123 bool gating_allowed = !ufshcd_can_fake_clkgating(hba);
57d104c1
SJ		 8124
8125 hba->pm_op_in_progress = 1;
3bc47bcc 8126 if (ufshcd_is_system_pm(pm_op))
8127 pm_lvl = hba->spm_lvl;
8128 else
8129 pm_lvl = hba->rpm_lvl;
8130
8131 if (ufs_get_pm_lvl_to_link_pwr_state(pm_lvl) == UIC_LINK_OFF_STATE)
8132 hba->uic_link_state = UIC_LINK_OFF_STATE;
57d104c1
SJ		 8133 old_link_state = hba->uic_link_state;
8134
8135 ufshcd_hba_vreg_set_hpm(hba);
5801290e 8136
57d104c1
SJ		 8137 ret = ufshcd_vreg_set_hpm(hba);
8138 if (ret)
8139 goto disable_irq_and_vops_clks;
8140
7a3e97b0 8141 /*
57d104c1
SJ		 8142 * Call vendor specific resume callback. As these callbacks may access
8143 * vendor specific host controller register space call them when the
8144 * host clocks are ON.
7a3e97b0 8145 */
0263bcd0
YG		 8146 ret = ufshcd_vops_resume(hba, pm_op);
8147 if (ret)
8148 goto disable_vreg;
57d104c1 8149
5801290e 8150 if (gating_allowed) {
8151 /* Make sure clocks are enabled before accessing controller */
8152 ret = ufshcd_setup_clocks(hba, true);
8153 if (ret)
8154 goto disable_vreg;
8155 }
57d104c1 8156 if (ufshcd_is_link_hibern8(hba)) {
5801290e 8157 ufshcd_set_link_trans_active(hba);
0f7f11ff 8158 ret = ufshcd_link_hibern8_ctrl(hba, false);
57d104c1
SJ		 8159 if (!ret)
8160 ufshcd_set_link_active(hba);
5801290e 8161 else {
8162 ufshcd_set_link_off(hba);
57d104c1 8163 goto vendor_suspend;
5801290e 8164 }
57d104c1 8165 } else if (ufshcd_is_link_off(hba)) {
9632ac5f 8166#ifdef CONFIG_SCSI_UFS_ASYNC_RELINK
8167 hba->async_resume = true;
8168 ret = ufshcd_host_reset_and_restore(hba);
8169 goto async_resume;
8170#else
57d104c1 8171 ret = ufshcd_host_reset_and_restore(hba);
9632ac5f 8172#endif
8173
57d104c1
SJ		 8174 /*
8175 * ufshcd_host_reset_and_restore() should have already
8176 * set the link state as active
8177 */
8178 if (ret || !ufshcd_is_link_active(hba))
8179 goto vendor_suspend;
8180 }
8181
8182 if (!ufshcd_is_ufs_dev_active(hba)) {
8183 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
8184 if (ret)
8185 goto set_old_link_state;
8186 }
8187
4e768e76
SJ		 8188 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
8189 ufshcd_enable_auto_bkops(hba);
8190 else
8191 /*
8192 * If BKOPs operations are urgently needed at this moment then
8193 * keep auto-bkops enabled or else disable it.
8194 */
8195 ufshcd_urgent_bkops(hba);
9632ac5f 8196#ifdef CONFIG_SCSI_UFS_ASYNC_RELINK
8197async_resume:
8198#endif
1ab27c9c
ST		 8199 hba->clk_gating.is_suspended = false;
8200
b393aa4d 8201#if defined(CONFIG_PM_DEVFREQ)
fcb0c4b0
ST		 8202 if (hba->clk_scaling.is_allowed)
8203 ufshcd_resume_clkscaling(hba);
b393aa4d 8204#endif
856b3483 8205
1ab27c9c
ST		 8206 /* Schedule clock gating in case of no access to UFS device yet */
8207 ufshcd_release(hba);
57d104c1
SJ		 8208 goto out;
8209
8210set_old_link_state:
8211 ufshcd_link_state_transition(hba, old_link_state, 0);
8212vendor_suspend:
0263bcd0 8213 ufshcd_vops_suspend(hba, pm_op);
57d104c1
SJ		 8214disable_irq_and_vops_clks:
8215 ufshcd_disable_irq(hba);
401f1e44
SJ		 8216 if (hba->clk_scaling.is_allowed)
8217 ufshcd_suspend_clkscaling(hba);
57d104c1 8218 ufshcd_setup_clocks(hba, false);
6aecc4db 8219disable_vreg:
8220 ufshcd_vreg_set_lpm(hba);
57d104c1
SJ		 8221out:
8222 hba->pm_op_in_progress = 0;
9632ac5f 8223
8224 if (hba->monitor.flag & UFSHCD_MONITOR_LEVEL1)
8225 dev_info(hba->dev, "UFS resume done\n");
8226
57d104c1
SJ		 8227 return ret;
8228}
8229
8230/**
8231 * ufshcd_system_suspend - system suspend routine
8232 * @hba: per adapter instance
8233 * @pm_op: runtime PM or system PM
8234 *
8235 * Check the description of ufshcd_suspend() function for more details.
8236 *
8237 * Returns 0 for success and non-zero for failure
8238 */
8239int ufshcd_system_suspend(struct ufs_hba *hba)
8240{
8241 int ret = 0;
7ff5ab47 8242 ktime_t start = ktime_get();
57d104c1
SJ		 8243
8244 if (!hba || !hba->is_powered)
233b594b 8245 return 0;
57d104c1 8246
0b257734
SJ		 8247 if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
8248 hba->curr_dev_pwr_mode) &&
8249 (ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
8250 hba->uic_link_state))
8251 goto out;
57d104c1 8252
0b257734 8253 if (pm_runtime_suspended(hba->dev)) {
57d104c1
SJ		 8254 /*
8255 * UFS device and/or UFS link low power states during runtime
8256 * suspend seems to be different than what is expected during
8257 * system suspend. Hence runtime resume the devic & link and
8258 * let the system suspend low power states to take effect.
8259 * TODO: If resume takes longer time, we might have optimize
8260 * it in future by not resuming everything if possible.
8261 */
8262 ret = ufshcd_runtime_resume(hba);
8263 if (ret)
8264 goto out;
8265 }
8266
8267 ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
8268out:
7ff5ab47
SJ		 8269 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
8270 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8271 hba->curr_dev_pwr_mode, hba->uic_link_state);
e785060e
DR		 8272 if (!ret)
8273 hba->is_sys_suspended = true;
57d104c1
SJ		 8274 return ret;
8275}
8276EXPORT_SYMBOL(ufshcd_system_suspend);
8277
8278/**
8279 * ufshcd_system_resume - system resume routine
8280 * @hba: per adapter instance
8281 *
8282 * Returns 0 for success and non-zero for failure
8283 */
7a3e97b0 8284
57d104c1
SJ		 8285int ufshcd_system_resume(struct ufs_hba *hba)
8286{
7ff5ab47
SJ		 8287 int ret = 0;
8288 ktime_t start = ktime_get();
8289
e3ce73d6
YG		 8290 if (!hba)
8291 return -EINVAL;
8292
8293 if (!hba->is_powered || pm_runtime_suspended(hba->dev))
57d104c1
SJ		 8294 /*
8295 * Let the runtime resume take care of resuming
8296 * if runtime suspended.
8297 */
7ff5ab47
SJ		 8298 goto out;
8299 else
8300 ret = ufshcd_resume(hba, UFS_SYSTEM_PM);
8301out:
8302 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
8303 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8304 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8305 return ret;
7a3e97b0 8306}
57d104c1 8307EXPORT_SYMBOL(ufshcd_system_resume);
3b1d0580 8308
57d104c1
SJ		 8309/**
8310 * ufshcd_runtime_suspend - runtime suspend routine
8311 * @hba: per adapter instance
8312 *
8313 * Check the description of ufshcd_suspend() function for more details.
8314 *
8315 * Returns 0 for success and non-zero for failure
8316 */
66ec6d59
SRT		 8317int ufshcd_runtime_suspend(struct ufs_hba *hba)
8318{
7ff5ab47
SJ		 8319 int ret = 0;
8320 ktime_t start = ktime_get();
8321
e3ce73d6
YG		 8322 if (!hba)
8323 return -EINVAL;
8324
8325 if (!hba->is_powered)
7ff5ab47
SJ		 8326 goto out;
8327 else
8328 ret = ufshcd_suspend(hba, UFS_RUNTIME_PM);
8329out:
8330 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
8331 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8332 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8333 return ret;
66ec6d59
SRT		 8334}
8335EXPORT_SYMBOL(ufshcd_runtime_suspend);
8336
57d104c1
SJ		 8337/**
8338 * ufshcd_runtime_resume - runtime resume routine
8339 * @hba: per adapter instance
8340 *
8341 * This function basically brings the UFS device, UniPro link and controller
8342 * to active state. Following operations are done in this function:
8343 *
8344 * 1. Turn on all the controller related clocks
8345 * 2. Bring the UniPro link out of Hibernate state
8346 * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
8347 * to active state.
8348 * 4. If auto-bkops is enabled on the device, disable it.
8349 *
8350 * So following would be the possible power state after this function return
8351 * successfully:
8352 * S1: UFS device in Active state with VCC rail ON
8353 * UniPro link in Active state
8354 * All the UFS/UniPro controller clocks are ON
8355 *
8356 * Returns 0 for success and non-zero for failure
8357 */
66ec6d59
SRT		 8358int ufshcd_runtime_resume(struct ufs_hba *hba)
8359{
7ff5ab47
SJ		 8360 int ret = 0;
8361 ktime_t start = ktime_get();
8362
e3ce73d6
YG		 8363 if (!hba)
8364 return -EINVAL;
8365
8366 if (!hba->is_powered)
7ff5ab47
SJ		 8367 goto out;
8368 else
8369 ret = ufshcd_resume(hba, UFS_RUNTIME_PM);
8370out:
8371 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
8372 ktime_to_us(ktime_sub(ktime_get(), start)),
73eba2be 8373 hba->curr_dev_pwr_mode, hba->uic_link_state);
7ff5ab47 8374 return ret;
66ec6d59
SRT		 8375}
8376EXPORT_SYMBOL(ufshcd_runtime_resume);
8377
8378int ufshcd_runtime_idle(struct ufs_hba *hba)
8379{
8380 return 0;
8381}
8382EXPORT_SYMBOL(ufshcd_runtime_idle);
8383
09690d5a
SJ		 8384static inline ssize_t ufshcd_pm_lvl_store(struct device *dev,
8385 struct device_attribute *attr,
8386 const char *buf, size_t count,
8387 bool rpm)
8388{
8389 struct ufs_hba *hba = dev_get_drvdata(dev);
8390 unsigned long flags, value;
8391
8392 if (kstrtoul(buf, 0, &value))
8393 return -EINVAL;
8394
949d7fa1 8395 if (value >= UFS_PM_LVL_MAX)
09690d5a
SJ		 8396 return -EINVAL;
8397
8398 spin_lock_irqsave(hba->host->host_lock, flags);
8399 if (rpm)
8400 hba->rpm_lvl = value;
8401 else
8402 hba->spm_lvl = value;
8403 spin_unlock_irqrestore(hba->host->host_lock, flags);
8404 return count;
8405}
8406
8407static ssize_t ufshcd_rpm_lvl_show(struct device *dev,
8408 struct device_attribute *attr, char *buf)
8409{
8410 struct ufs_hba *hba = dev_get_drvdata(dev);
8411 int curr_len;
8412 u8 lvl;
8413
8414 curr_len = snprintf(buf, PAGE_SIZE,
8415 "\nCurrent Runtime PM level [%d] => dev_state [%s] link_state [%s]\n",
8416 hba->rpm_lvl,
8417 ufschd_ufs_dev_pwr_mode_to_string(
8418 ufs_pm_lvl_states[hba->rpm_lvl].dev_state),
8419 ufschd_uic_link_state_to_string(
8420 ufs_pm_lvl_states[hba->rpm_lvl].link_state));
8421
8422 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
8423 "\nAll available Runtime PM levels info:\n");
8424 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
8425 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
8426 "\tRuntime PM level [%d] => dev_state [%s] link_state [%s]\n",
8427 lvl,
8428 ufschd_ufs_dev_pwr_mode_to_string(
8429 ufs_pm_lvl_states[lvl].dev_state),
8430 ufschd_uic_link_state_to_string(
8431 ufs_pm_lvl_states[lvl].link_state));
8432
8433 return curr_len;
8434}
8435
8436static ssize_t ufshcd_rpm_lvl_store(struct device *dev,
8437 struct device_attribute *attr, const char *buf, size_t count)
8438{
8439 return ufshcd_pm_lvl_store(dev, attr, buf, count, true);
8440}
8441
8442static void ufshcd_add_rpm_lvl_sysfs_nodes(struct ufs_hba *hba)
8443{
8444 hba->rpm_lvl_attr.show = ufshcd_rpm_lvl_show;
8445 hba->rpm_lvl_attr.store = ufshcd_rpm_lvl_store;
8446 sysfs_attr_init(&hba->rpm_lvl_attr.attr);
8447 hba->rpm_lvl_attr.attr.name = "rpm_lvl";
8448 hba->rpm_lvl_attr.attr.mode = 0644;
8449 if (device_create_file(hba->dev, &hba->rpm_lvl_attr))
8450 dev_err(hba->dev, "Failed to create sysfs for rpm_lvl\n");
8451}
8452
8453static ssize_t ufshcd_spm_lvl_show(struct device *dev,
8454 struct device_attribute *attr, char *buf)
8455{
8456 struct ufs_hba *hba = dev_get_drvdata(dev);
8457 int curr_len;
8458 u8 lvl;
8459
8460 curr_len = snprintf(buf, PAGE_SIZE,
8461 "\nCurrent System PM level [%d] => dev_state [%s] link_state [%s]\n",
8462 hba->spm_lvl,
8463 ufschd_ufs_dev_pwr_mode_to_string(
8464 ufs_pm_lvl_states[hba->spm_lvl].dev_state),
8465 ufschd_uic_link_state_to_string(
8466 ufs_pm_lvl_states[hba->spm_lvl].link_state));
8467
8468 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
8469 "\nAll available System PM levels info:\n");
8470 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++)
8471 curr_len += snprintf((buf + curr_len), (PAGE_SIZE - curr_len),
8472 "\tSystem PM level [%d] => dev_state [%s] link_state [%s]\n",
8473 lvl,
8474 ufschd_ufs_dev_pwr_mode_to_string(
8475 ufs_pm_lvl_states[lvl].dev_state),
8476 ufschd_uic_link_state_to_string(
8477 ufs_pm_lvl_states[lvl].link_state));
8478
8479 return curr_len;
8480}
8481
8482static ssize_t ufshcd_spm_lvl_store(struct device *dev,
8483 struct device_attribute *attr, const char *buf, size_t count)
8484{
8485 return ufshcd_pm_lvl_store(dev, attr, buf, count, false);
8486}
8487
8488static void ufshcd_add_spm_lvl_sysfs_nodes(struct ufs_hba *hba)
8489{
8490 hba->spm_lvl_attr.show = ufshcd_spm_lvl_show;
8491 hba->spm_lvl_attr.store = ufshcd_spm_lvl_store;
8492 sysfs_attr_init(&hba->spm_lvl_attr.attr);
8493 hba->spm_lvl_attr.attr.name = "spm_lvl";
8494 hba->spm_lvl_attr.attr.mode = 0644;
8495 if (device_create_file(hba->dev, &hba->spm_lvl_attr))
8496 dev_err(hba->dev, "Failed to create sysfs for spm_lvl\n");
8497}
8498
8499static inline void ufshcd_add_sysfs_nodes(struct ufs_hba *hba)
8500{
8501 ufshcd_add_rpm_lvl_sysfs_nodes(hba);
8502 ufshcd_add_spm_lvl_sysfs_nodes(hba);
8503}
8504
463f620b
MP		 8505static inline void ufshcd_remove_sysfs_nodes(struct ufs_hba *hba)
8506{
8507 device_remove_file(hba->dev, &hba->rpm_lvl_attr);
8508 device_remove_file(hba->dev, &hba->spm_lvl_attr);
8509}
8510
57d104c1
SJ		 8511/**
8512 * ufshcd_shutdown - shutdown routine
8513 * @hba: per adapter instance
8514 *
8515 * This function would power off both UFS device and UFS link.
8516 *
8517 * Returns 0 always to allow force shutdown even in case of errors.
8518 */
8519int ufshcd_shutdown(struct ufs_hba *hba)
8520{
8521 int ret = 0;
8522
8523 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
8524 goto out;
8525
8526 if (pm_runtime_suspended(hba->dev)) {
8527 ret = ufshcd_runtime_resume(hba);
8528 if (ret)
8529 goto out;
8530 }
8531
8532 ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
8533out:
8534 if (ret)
8535 dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
8536 /* allow force shutdown even in case of errors */
8537 return 0;
8538}
8539EXPORT_SYMBOL(ufshcd_shutdown);
8540
7a3e97b0 8541/**
3b1d0580 8542 * ufshcd_remove - de-allocate SCSI host and host memory space
7a3e97b0 8543 * data structure memory
3b1d0580 8544 * @hba - per adapter instance
7a3e97b0 8545 */
3b1d0580 8546void ufshcd_remove(struct ufs_hba *hba)
7a3e97b0 8547{
463f620b 8548 ufshcd_remove_sysfs_nodes(hba);
cfdf9c91 8549 scsi_remove_host(hba->host);
7a3e97b0 8550 /* disable interrupts */
2fbd009b 8551 ufshcd_disable_intr(hba, hba->intr_mask);
596585a2 8552 ufshcd_hba_stop(hba, true);
7a3e97b0 8553
1ab27c9c 8554 ufshcd_exit_clk_gating(hba);
b393aa4d 8555#if defined(CONFIG_PM_DEVFREQ)
fcb0c4b0
ST		 8556 if (ufshcd_is_clkscaling_supported(hba))
8557 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
b393aa4d 8558#endif
aa497613 8559 ufshcd_hba_exit(hba);
3b1d0580
VH		 8560}
8561EXPORT_SYMBOL_GPL(ufshcd_remove);
8562
47555a5c
YG		 8563/**
8564 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
8565 * @hba: pointer to Host Bus Adapter (HBA)
8566 */
8567void ufshcd_dealloc_host(struct ufs_hba *hba)
8568{
8569 scsi_host_put(hba->host);
8570}
8571EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
8572
ca3d7bf9
AM		 8573/**
8574 * ufshcd_set_dma_mask - Set dma mask based on the controller
8575 * addressing capability
8576 * @hba: per adapter instance
8577 *
8578 * Returns 0 for success, non-zero for failure
8579 */
8580static int ufshcd_set_dma_mask(struct ufs_hba *hba)
8581{
8582 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
8583 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
8584 return 0;
8585 }
8586 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
8587}
8588
7a3e97b0 8589/**
5c0c28a8 8590 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
3b1d0580
VH		 8591 * @dev: pointer to device handle
8592 * @hba_handle: driver private handle
7a3e97b0
SY		 8593 * Returns 0 on success, non-zero value on failure
8594 */
5c0c28a8 8595int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
7a3e97b0
SY		 8596{
8597 struct Scsi_Host *host;
8598 struct ufs_hba *hba;
5c0c28a8 8599 int err = 0;
7a3e97b0 8600
3b1d0580
VH		 8601 if (!dev) {
8602 dev_err(dev,
8603 "Invalid memory reference for dev is NULL\n");
8604 err = -ENODEV;
7a3e97b0
SY		 8605 goto out_error;
8606 }
8607
7a3e97b0
SY		 8608 host = scsi_host_alloc(&ufshcd_driver_template,
8609 sizeof(struct ufs_hba));
8610 if (!host) {
3b1d0580 8611 dev_err(dev, "scsi_host_alloc failed\n");
7a3e97b0 8612 err = -ENOMEM;
3b1d0580 8613 goto out_error;
7a3e97b0
SY		 8614 }
8615 hba = shost_priv(host);
7a3e97b0 8616 hba->host = host;
3b1d0580 8617 hba->dev = dev;
5c0c28a8
SRT		 8618 *hba_handle = hba;
8619
566ec9ad
SM		 8620 INIT_LIST_HEAD(&hba->clk_list_head);
8621
5c0c28a8
SRT		 8622out_error:
8623 return err;
8624}
8625EXPORT_SYMBOL(ufshcd_alloc_host);
8626
8627/**
8628 * ufshcd_init - Driver initialization routine
8629 * @hba: per-adapter instance
8630 * @mmio_base: base register address
8631 * @irq: Interrupt line of device
8632 * Returns 0 on success, non-zero value on failure
8633 */
8634int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
8635{
8636 int err;
8637 struct Scsi_Host *host = hba->host;
8638 struct device *dev = hba->dev;
8639
8640 if (!mmio_base) {
8641 dev_err(hba->dev,
8642 "Invalid memory reference for mmio_base is NULL\n");
8643 err = -ENODEV;
8644 goto out_error;
8645 }
8646
3b1d0580
VH		 8647 hba->mmio_base = mmio_base;
8648 hba->irq = irq;
7a3e97b0 8649
a4b0e8a4
PM		 8650 /* Set descriptor lengths to specification defaults */
8651 ufshcd_def_desc_sizes(hba);
8652
aa497613 8653 err = ufshcd_hba_init(hba);
5c0c28a8
SRT		 8654 if (err)
8655 goto out_error;
8656
7a3e97b0
SY		 8657 /* Read capabilities registers */
8658 ufshcd_hba_capabilities(hba);
8659
8660 /* Get UFS version supported by the controller */
8661 hba->ufs_version = ufshcd_get_ufs_version(hba);
8662
c01848c6
YG		 8663 if ((hba->ufs_version != UFSHCI_VERSION_10) &&
8664 (hba->ufs_version != UFSHCI_VERSION_11) &&
8665 (hba->ufs_version != UFSHCI_VERSION_20) &&
8666 (hba->ufs_version != UFSHCI_VERSION_21))
8667 dev_err(hba->dev, "invalid UFS version 0x%x\n",
8668 hba->ufs_version);
8669
2fbd009b
SJ		 8670 /* Get Interrupt bit mask per version */
8671 hba->intr_mask = ufshcd_get_intr_mask(hba);
8672
ca3d7bf9
AM		 8673 err = ufshcd_set_dma_mask(hba);
8674 if (err) {
8675 dev_err(hba->dev, "set dma mask failed\n");
8676 goto out_disable;
8677 }
8678
7a3e97b0
SY		 8679 /* Allocate memory for host memory space */
8680 err = ufshcd_memory_alloc(hba);
8681 if (err) {
3b1d0580
VH		 8682 dev_err(hba->dev, "Memory allocation failed\n");
8683 goto out_disable;
7a3e97b0
SY		 8684 }
8685
8686 /* Configure LRB */
8687 ufshcd_host_memory_configure(hba);
8688
8689 host->can_queue = hba->nutrs;
8690 host->cmd_per_lun = hba->nutrs;
8691 host->max_id = UFSHCD_MAX_ID;
0ce147d4 8692 host->max_lun = UFS_MAX_LUNS;
7a3e97b0
SY		 8693 host->max_channel = UFSHCD_MAX_CHANNEL;
8694 host->unique_id = host->host_no;
8695 host->max_cmd_len = MAX_CDB_SIZE;
8696
7eb584db
DR		 8697 hba->max_pwr_info.is_valid = false;
8698
7a3e97b0 8699 /* Initailize wait queue for task management */
e2933132
SRT		 8700 init_waitqueue_head(&hba->tm_wq);
8701 init_waitqueue_head(&hba->tm_tag_wq);
7a3e97b0
SY		 8702
8703 /* Initialize work queues */
e8e7f271 8704 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
66ec6d59 8705 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
7a3e97b0 8706
6ccf44fe
SJ		 8707 /* Initialize UIC command mutex */
8708 mutex_init(&hba->uic_cmd_mutex);
8709
5a0b0cb9
SRT		 8710 /* Initialize mutex for device management commands */
8711 mutex_init(&hba->dev_cmd.lock);
8712
a3cd5ec5
SJ		 8713 init_rwsem(&hba->clk_scaling_lock);
8714
5a0b0cb9
SRT		 8715 /* Initialize device management tag acquire wait queue */
8716 init_waitqueue_head(&hba->dev_cmd.tag_wq);
8717
9632ac5f 8718 /* Initialize monitor */
8719 ufshcd_init_monitor(hba);
9087ff6a 8720
8721 err = ufshcd_init_clk_gating(hba);
8722 if (err) {
8723 dev_err(hba->dev, "init clk_gating failed\n");
8724 goto out_disable;
8725 }
199ef13c
YG		 8726
8727 /*
8728 * In order to avoid any spurious interrupt immediately after
8729 * registering UFS controller interrupt handler, clear any pending UFS
8730 * interrupt status and disable all the UFS interrupts.
8731 */
8732 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
8733 REG_INTERRUPT_STATUS);
8734 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
8735 /*
8736 * Make sure that UFS interrupts are disabled and any pending interrupt
8737 * status is cleared before registering UFS interrupt handler.
8738 */
8739 mb();
8740
7a3e97b0 8741 /* IRQ registration */
2953f850 8742 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
7a3e97b0 8743 if (err) {
3b1d0580 8744 dev_err(hba->dev, "request irq failed\n");
1ab27c9c 8745 goto exit_gating;
57d104c1
SJ		 8746 } else {
8747 hba->is_irq_enabled = true;
7a3e97b0
SY		 8748 }
8749
3b1d0580 8750 err = scsi_add_host(host, hba->dev);
7a3e97b0 8751 if (err) {
3b1d0580 8752 dev_err(hba->dev, "scsi_add_host failed\n");
1ab27c9c 8753 goto exit_gating;
7a3e97b0
SY		 8754 }
8755
b393aa4d 8756#if defined(CONFIG_PM_DEVFREQ)
fcb0c4b0 8757 if (ufshcd_is_clkscaling_supported(hba)) {
401f1e44
SJ		 8758 char wq_name[sizeof("ufs_clkscaling_00")];
8759
401f1e44
SJ		 8760 INIT_WORK(&hba->clk_scaling.suspend_work,
8761 ufshcd_clk_scaling_suspend_work);
8762 INIT_WORK(&hba->clk_scaling.resume_work,
8763 ufshcd_clk_scaling_resume_work);
8764
d985c6ea 8765 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
401f1e44
SJ		 8766 host->host_no);
8767 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
8768
fcb0c4b0 8769 ufshcd_clkscaling_init_sysfs(hba);
856b3483 8770 }
b393aa4d 8771#endif
0c8f7586
SJ		 8772 /*
8773 * Set the default power management level for runtime and system PM.
8774 * Default power saving mode is to keep UFS link in Hibern8 state
8775 * and UFS device in sleep state.
8776 */
8777 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8778 UFS_SLEEP_PWR_MODE,
8779 UIC_LINK_HIBERN8_STATE);
8780 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
8781 UFS_SLEEP_PWR_MODE,
8782 UIC_LINK_HIBERN8_STATE);
8783
62694735
SRT		 8784 /* Hold auto suspend until async scan completes */
8785 pm_runtime_get_sync(dev);
8786
57d104c1 8787 /*
7caf489b
SJ		 8788 * We are assuming that device wasn't put in sleep/power-down
8789 * state exclusively during the boot stage before kernel.
8790 * This assumption helps avoid doing link startup twice during
8791 * ufshcd_probe_hba().
57d104c1 8792 */
7caf489b 8793 ufshcd_set_ufs_dev_active(hba);
57d104c1 8794
6ccf44fe 8795 async_schedule(ufshcd_async_scan, hba);
09690d5a 8796 ufshcd_add_sysfs_nodes(hba);
6ccf44fe 8797
7a3e97b0
SY		 8798 return 0;
8799
3b1d0580
VH		 8800out_remove_scsi_host:
8801 scsi_remove_host(hba->host);
1ab27c9c
ST		 8802exit_gating:
8803 ufshcd_exit_clk_gating(hba);
3b1d0580 8804out_disable:
57d104c1 8805 hba->is_irq_enabled = false;
aa497613 8806 ufshcd_hba_exit(hba);
3b1d0580
VH		 8807out_error:
8808 return err;
8809}
8810EXPORT_SYMBOL_GPL(ufshcd_init);
8811
3b1d0580
VH		 8812MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
8813MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
e0eca63e 8814MODULE_DESCRIPTION("Generic UFS host controller driver Core");
7a3e97b0
SY		 8815MODULE_LICENSE("GPL");
8816MODULE_VERSION(UFSHCD_DRIVER_VERSION);