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1da177e4 LT |
1 | /* |
2 | * sata_sx4.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
41 | #include "scsi.h" | |
42 | #include <scsi/scsi_host.h> | |
43 | #include <linux/libata.h> | |
44 | #include <asm/io.h> | |
45 | #include "sata_promise.h" | |
46 | ||
47 | #define DRV_NAME "sata_sx4" | |
48 | #define DRV_VERSION "0.7" | |
49 | ||
50 | ||
51 | enum { | |
52 | PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */ | |
53 | ||
54 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | |
55 | PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */ | |
56 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
57 | PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */ | |
58 | ||
59 | PDC_20621_SEQCTL = 0x400, | |
60 | PDC_20621_SEQMASK = 0x480, | |
61 | PDC_20621_GENERAL_CTL = 0x484, | |
62 | PDC_20621_PAGE_SIZE = (32 * 1024), | |
63 | ||
64 | /* chosen, not constant, values; we design our own DIMM mem map */ | |
65 | PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */ | |
66 | PDC_20621_DIMM_BASE = 0x00200000, | |
67 | PDC_20621_DIMM_DATA = (64 * 1024), | |
68 | PDC_DIMM_DATA_STEP = (256 * 1024), | |
69 | PDC_DIMM_WINDOW_STEP = (8 * 1024), | |
70 | PDC_DIMM_HOST_PRD = (6 * 1024), | |
71 | PDC_DIMM_HOST_PKT = (128 * 0), | |
72 | PDC_DIMM_HPKT_PRD = (128 * 1), | |
73 | PDC_DIMM_ATA_PKT = (128 * 2), | |
74 | PDC_DIMM_APKT_PRD = (128 * 3), | |
75 | PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128, | |
76 | PDC_PAGE_WINDOW = 0x40, | |
77 | PDC_PAGE_DATA = PDC_PAGE_WINDOW + | |
78 | (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE), | |
79 | PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE, | |
80 | ||
81 | PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */ | |
82 | ||
83 | PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
84 | (1<<23), | |
85 | ||
86 | board_20621 = 0, /* FastTrak S150 SX4 */ | |
87 | ||
88 | PDC_RESET = (1 << 11), /* HDMA reset */ | |
89 | ||
90 | PDC_MAX_HDMA = 32, | |
91 | PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1), | |
92 | ||
93 | PDC_DIMM0_SPD_DEV_ADDRESS = 0x50, | |
94 | PDC_DIMM1_SPD_DEV_ADDRESS = 0x51, | |
95 | PDC_MAX_DIMM_MODULE = 0x02, | |
96 | PDC_I2C_CONTROL_OFFSET = 0x48, | |
97 | PDC_I2C_ADDR_DATA_OFFSET = 0x4C, | |
98 | PDC_DIMM0_CONTROL_OFFSET = 0x80, | |
99 | PDC_DIMM1_CONTROL_OFFSET = 0x84, | |
100 | PDC_SDRAM_CONTROL_OFFSET = 0x88, | |
101 | PDC_I2C_WRITE = 0x00000000, | |
8a60a071 | 102 | PDC_I2C_READ = 0x00000040, |
1da177e4 LT |
103 | PDC_I2C_START = 0x00000080, |
104 | PDC_I2C_MASK_INT = 0x00000020, | |
105 | PDC_I2C_COMPLETE = 0x00010000, | |
106 | PDC_I2C_NO_ACK = 0x00100000, | |
107 | PDC_DIMM_SPD_SUBADDRESS_START = 0x00, | |
108 | PDC_DIMM_SPD_SUBADDRESS_END = 0x7F, | |
109 | PDC_DIMM_SPD_ROW_NUM = 3, | |
110 | PDC_DIMM_SPD_COLUMN_NUM = 4, | |
111 | PDC_DIMM_SPD_MODULE_ROW = 5, | |
112 | PDC_DIMM_SPD_TYPE = 11, | |
8a60a071 JG |
113 | PDC_DIMM_SPD_FRESH_RATE = 12, |
114 | PDC_DIMM_SPD_BANK_NUM = 17, | |
1da177e4 | 115 | PDC_DIMM_SPD_CAS_LATENCY = 18, |
8a60a071 | 116 | PDC_DIMM_SPD_ATTRIBUTE = 21, |
1da177e4 | 117 | PDC_DIMM_SPD_ROW_PRE_CHARGE = 27, |
8a60a071 | 118 | PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28, |
1da177e4 LT |
119 | PDC_DIMM_SPD_RAS_CAS_DELAY = 29, |
120 | PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30, | |
121 | PDC_DIMM_SPD_SYSTEM_FREQ = 126, | |
8a60a071 | 122 | PDC_CTL_STATUS = 0x08, |
1da177e4 LT |
123 | PDC_DIMM_WINDOW_CTLR = 0x0C, |
124 | PDC_TIME_CONTROL = 0x3C, | |
125 | PDC_TIME_PERIOD = 0x40, | |
126 | PDC_TIME_COUNTER = 0x44, | |
127 | PDC_GENERAL_CTLR = 0x484, | |
128 | PCI_PLL_INIT = 0x8A531824, | |
129 | PCI_X_TCOUNT = 0xEE1E5CFF | |
130 | }; | |
131 | ||
132 | ||
133 | struct pdc_port_priv { | |
134 | u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512]; | |
135 | u8 *pkt; | |
136 | dma_addr_t pkt_dma; | |
137 | }; | |
138 | ||
139 | struct pdc_host_priv { | |
140 | void *dimm_mmio; | |
141 | ||
142 | unsigned int doing_hdma; | |
143 | unsigned int hdma_prod; | |
144 | unsigned int hdma_cons; | |
145 | struct { | |
146 | struct ata_queued_cmd *qc; | |
147 | unsigned int seq; | |
148 | unsigned long pkt_ofs; | |
149 | } hdma[32]; | |
150 | }; | |
151 | ||
152 | ||
153 | static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
154 | static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs); | |
155 | static void pdc_eng_timeout(struct ata_port *ap); | |
156 | static void pdc_20621_phy_reset (struct ata_port *ap); | |
157 | static int pdc_port_start(struct ata_port *ap); | |
158 | static void pdc_port_stop(struct ata_port *ap); | |
159 | static void pdc20621_qc_prep(struct ata_queued_cmd *qc); | |
160 | static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf); | |
161 | static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf); | |
162 | static void pdc20621_host_stop(struct ata_host_set *host_set); | |
163 | static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe); | |
164 | static int pdc20621_detect_dimm(struct ata_probe_ent *pe); | |
8a60a071 | 165 | static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, |
1da177e4 LT |
166 | u32 device, u32 subaddr, u32 *pdata); |
167 | static int pdc20621_prog_dimm0(struct ata_probe_ent *pe); | |
168 | static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe); | |
169 | #ifdef ATA_VERBOSE_DEBUG | |
8a60a071 | 170 | static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, |
1da177e4 LT |
171 | void *psource, u32 offset, u32 size); |
172 | #endif | |
8a60a071 | 173 | static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, |
1da177e4 LT |
174 | void *psource, u32 offset, u32 size); |
175 | static void pdc20621_irq_clear(struct ata_port *ap); | |
176 | static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc); | |
177 | ||
178 | ||
179 | static Scsi_Host_Template pdc_sata_sht = { | |
180 | .module = THIS_MODULE, | |
181 | .name = DRV_NAME, | |
182 | .ioctl = ata_scsi_ioctl, | |
183 | .queuecommand = ata_scsi_queuecmd, | |
184 | .eh_strategy_handler = ata_scsi_error, | |
185 | .can_queue = ATA_DEF_QUEUE, | |
186 | .this_id = ATA_SHT_THIS_ID, | |
187 | .sg_tablesize = LIBATA_MAX_PRD, | |
188 | .max_sectors = ATA_MAX_SECTORS, | |
189 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
190 | .emulated = ATA_SHT_EMULATED, | |
191 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
192 | .proc_name = DRV_NAME, | |
193 | .dma_boundary = ATA_DMA_BOUNDARY, | |
194 | .slave_configure = ata_scsi_slave_config, | |
195 | .bios_param = ata_std_bios_param, | |
196 | .ordered_flush = 1, | |
197 | }; | |
198 | ||
199 | static struct ata_port_operations pdc_20621_ops = { | |
200 | .port_disable = ata_port_disable, | |
201 | .tf_load = pdc_tf_load_mmio, | |
202 | .tf_read = ata_tf_read, | |
203 | .check_status = ata_check_status, | |
204 | .exec_command = pdc_exec_command_mmio, | |
205 | .dev_select = ata_std_dev_select, | |
206 | .phy_reset = pdc_20621_phy_reset, | |
207 | .qc_prep = pdc20621_qc_prep, | |
208 | .qc_issue = pdc20621_qc_issue_prot, | |
209 | .eng_timeout = pdc_eng_timeout, | |
210 | .irq_handler = pdc20621_interrupt, | |
211 | .irq_clear = pdc20621_irq_clear, | |
212 | .port_start = pdc_port_start, | |
213 | .port_stop = pdc_port_stop, | |
214 | .host_stop = pdc20621_host_stop, | |
215 | }; | |
216 | ||
217 | static struct ata_port_info pdc_port_info[] = { | |
218 | /* board_20621 */ | |
219 | { | |
220 | .sht = &pdc_sata_sht, | |
221 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
222 | ATA_FLAG_SRST | ATA_FLAG_MMIO, | |
223 | .pio_mask = 0x1f, /* pio0-4 */ | |
224 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
225 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
226 | .port_ops = &pdc_20621_ops, | |
227 | }, | |
228 | ||
229 | }; | |
230 | ||
231 | static struct pci_device_id pdc_sata_pci_tbl[] = { | |
232 | { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
233 | board_20621 }, | |
234 | { } /* terminate list */ | |
235 | }; | |
236 | ||
237 | ||
238 | static struct pci_driver pdc_sata_pci_driver = { | |
239 | .name = DRV_NAME, | |
240 | .id_table = pdc_sata_pci_tbl, | |
241 | .probe = pdc_sata_init_one, | |
242 | .remove = ata_pci_remove_one, | |
243 | }; | |
244 | ||
245 | ||
246 | static void pdc20621_host_stop(struct ata_host_set *host_set) | |
247 | { | |
248 | struct pdc_host_priv *hpriv = host_set->private_data; | |
249 | void *dimm_mmio = hpriv->dimm_mmio; | |
250 | ||
251 | iounmap(dimm_mmio); | |
252 | kfree(hpriv); | |
aa8f0dc6 JG |
253 | |
254 | ata_host_stop(host_set); | |
1da177e4 LT |
255 | } |
256 | ||
257 | static int pdc_port_start(struct ata_port *ap) | |
258 | { | |
259 | struct device *dev = ap->host_set->dev; | |
260 | struct pdc_port_priv *pp; | |
261 | int rc; | |
262 | ||
263 | rc = ata_port_start(ap); | |
264 | if (rc) | |
265 | return rc; | |
266 | ||
267 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
268 | if (!pp) { | |
269 | rc = -ENOMEM; | |
270 | goto err_out; | |
271 | } | |
272 | memset(pp, 0, sizeof(*pp)); | |
273 | ||
274 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
275 | if (!pp->pkt) { | |
276 | rc = -ENOMEM; | |
277 | goto err_out_kfree; | |
278 | } | |
279 | ||
280 | ap->private_data = pp; | |
281 | ||
282 | return 0; | |
283 | ||
284 | err_out_kfree: | |
285 | kfree(pp); | |
286 | err_out: | |
287 | ata_port_stop(ap); | |
288 | return rc; | |
289 | } | |
290 | ||
291 | ||
292 | static void pdc_port_stop(struct ata_port *ap) | |
293 | { | |
294 | struct device *dev = ap->host_set->dev; | |
295 | struct pdc_port_priv *pp = ap->private_data; | |
296 | ||
297 | ap->private_data = NULL; | |
298 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
299 | kfree(pp); | |
300 | ata_port_stop(ap); | |
301 | } | |
302 | ||
303 | ||
304 | static void pdc_20621_phy_reset (struct ata_port *ap) | |
305 | { | |
306 | VPRINTK("ENTER\n"); | |
307 | ap->cbl = ATA_CBL_SATA; | |
308 | ata_port_probe(ap); | |
309 | ata_bus_reset(ap); | |
310 | } | |
311 | ||
312 | static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf, | |
313 | unsigned int portno, | |
314 | unsigned int total_len) | |
315 | { | |
316 | u32 addr; | |
317 | unsigned int dw = PDC_DIMM_APKT_PRD >> 2; | |
318 | u32 *buf32 = (u32 *) buf; | |
319 | ||
320 | /* output ATA packet S/G table */ | |
321 | addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA + | |
322 | (PDC_DIMM_DATA_STEP * portno); | |
323 | VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr); | |
324 | buf32[dw] = cpu_to_le32(addr); | |
325 | buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT); | |
326 | ||
327 | VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n", | |
328 | PDC_20621_DIMM_BASE + | |
329 | (PDC_DIMM_WINDOW_STEP * portno) + | |
330 | PDC_DIMM_APKT_PRD, | |
331 | buf32[dw], buf32[dw + 1]); | |
332 | } | |
333 | ||
334 | static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf, | |
335 | unsigned int portno, | |
336 | unsigned int total_len) | |
337 | { | |
338 | u32 addr; | |
339 | unsigned int dw = PDC_DIMM_HPKT_PRD >> 2; | |
340 | u32 *buf32 = (u32 *) buf; | |
341 | ||
342 | /* output Host DMA packet S/G table */ | |
343 | addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA + | |
344 | (PDC_DIMM_DATA_STEP * portno); | |
345 | ||
346 | buf32[dw] = cpu_to_le32(addr); | |
347 | buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT); | |
348 | ||
349 | VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n", | |
350 | PDC_20621_DIMM_BASE + | |
351 | (PDC_DIMM_WINDOW_STEP * portno) + | |
352 | PDC_DIMM_HPKT_PRD, | |
353 | buf32[dw], buf32[dw + 1]); | |
354 | } | |
355 | ||
356 | static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf, | |
357 | unsigned int devno, u8 *buf, | |
358 | unsigned int portno) | |
359 | { | |
360 | unsigned int i, dw; | |
361 | u32 *buf32 = (u32 *) buf; | |
362 | u8 dev_reg; | |
363 | ||
364 | unsigned int dimm_sg = PDC_20621_DIMM_BASE + | |
365 | (PDC_DIMM_WINDOW_STEP * portno) + | |
366 | PDC_DIMM_APKT_PRD; | |
367 | VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg); | |
368 | ||
369 | i = PDC_DIMM_ATA_PKT; | |
370 | ||
371 | /* | |
372 | * Set up ATA packet | |
373 | */ | |
374 | if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE))) | |
375 | buf[i++] = PDC_PKT_READ; | |
376 | else if (tf->protocol == ATA_PROT_NODATA) | |
377 | buf[i++] = PDC_PKT_NODATA; | |
378 | else | |
379 | buf[i++] = 0; | |
380 | buf[i++] = 0; /* reserved */ | |
381 | buf[i++] = portno + 1; /* seq. id */ | |
382 | buf[i++] = 0xff; /* delay seq. id */ | |
383 | ||
384 | /* dimm dma S/G, and next-pkt */ | |
385 | dw = i >> 2; | |
386 | if (tf->protocol == ATA_PROT_NODATA) | |
387 | buf32[dw] = 0; | |
388 | else | |
389 | buf32[dw] = cpu_to_le32(dimm_sg); | |
390 | buf32[dw + 1] = 0; | |
391 | i += 8; | |
392 | ||
393 | if (devno == 0) | |
394 | dev_reg = ATA_DEVICE_OBS; | |
395 | else | |
396 | dev_reg = ATA_DEVICE_OBS | ATA_DEV1; | |
397 | ||
398 | /* select device */ | |
399 | buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE; | |
400 | buf[i++] = dev_reg; | |
401 | ||
402 | /* device control register */ | |
403 | buf[i++] = (1 << 5) | PDC_REG_DEVCTL; | |
404 | buf[i++] = tf->ctl; | |
405 | ||
406 | return i; | |
407 | } | |
408 | ||
409 | static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf, | |
410 | unsigned int portno) | |
411 | { | |
412 | unsigned int dw; | |
413 | u32 tmp, *buf32 = (u32 *) buf; | |
414 | ||
415 | unsigned int host_sg = PDC_20621_DIMM_BASE + | |
416 | (PDC_DIMM_WINDOW_STEP * portno) + | |
417 | PDC_DIMM_HOST_PRD; | |
418 | unsigned int dimm_sg = PDC_20621_DIMM_BASE + | |
419 | (PDC_DIMM_WINDOW_STEP * portno) + | |
420 | PDC_DIMM_HPKT_PRD; | |
421 | VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg); | |
422 | VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg); | |
423 | ||
424 | dw = PDC_DIMM_HOST_PKT >> 2; | |
425 | ||
426 | /* | |
427 | * Set up Host DMA packet | |
428 | */ | |
429 | if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE))) | |
430 | tmp = PDC_PKT_READ; | |
431 | else | |
432 | tmp = 0; | |
433 | tmp |= ((portno + 1 + 4) << 16); /* seq. id */ | |
434 | tmp |= (0xff << 24); /* delay seq. id */ | |
435 | buf32[dw + 0] = cpu_to_le32(tmp); | |
436 | buf32[dw + 1] = cpu_to_le32(host_sg); | |
437 | buf32[dw + 2] = cpu_to_le32(dimm_sg); | |
438 | buf32[dw + 3] = 0; | |
439 | ||
440 | VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n", | |
441 | PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) + | |
442 | PDC_DIMM_HOST_PKT, | |
443 | buf32[dw + 0], | |
444 | buf32[dw + 1], | |
445 | buf32[dw + 2], | |
446 | buf32[dw + 3]); | |
447 | } | |
448 | ||
449 | static void pdc20621_dma_prep(struct ata_queued_cmd *qc) | |
450 | { | |
451 | struct scatterlist *sg = qc->sg; | |
452 | struct ata_port *ap = qc->ap; | |
453 | struct pdc_port_priv *pp = ap->private_data; | |
ea6ba10b | 454 | void __iomem *mmio = ap->host_set->mmio_base; |
1da177e4 | 455 | struct pdc_host_priv *hpriv = ap->host_set->private_data; |
ea6ba10b | 456 | void __iomem *dimm_mmio = hpriv->dimm_mmio; |
1da177e4 LT |
457 | unsigned int portno = ap->port_no; |
458 | unsigned int i, last, idx, total_len = 0, sgt_len; | |
459 | u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ]; | |
460 | ||
461 | assert(qc->flags & ATA_QCFLAG_DMAMAP); | |
462 | ||
463 | VPRINTK("ata%u: ENTER\n", ap->id); | |
464 | ||
465 | /* hard-code chip #0 */ | |
466 | mmio += PDC_CHIP0_OFS; | |
467 | ||
468 | /* | |
469 | * Build S/G table | |
470 | */ | |
471 | last = qc->n_elem; | |
472 | idx = 0; | |
473 | for (i = 0; i < last; i++) { | |
474 | buf[idx++] = cpu_to_le32(sg_dma_address(&sg[i])); | |
475 | buf[idx++] = cpu_to_le32(sg_dma_len(&sg[i])); | |
fae00984 | 476 | total_len += sg_dma_len(&sg[i]); |
1da177e4 LT |
477 | } |
478 | buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT); | |
479 | sgt_len = idx * 4; | |
480 | ||
481 | /* | |
482 | * Build ATA, host DMA packets | |
483 | */ | |
484 | pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len); | |
485 | pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno); | |
486 | ||
487 | pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len); | |
488 | i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno); | |
489 | ||
490 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
491 | i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i); | |
492 | else | |
493 | i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i); | |
494 | ||
495 | pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i); | |
496 | ||
497 | /* copy three S/G tables and two packets to DIMM MMIO window */ | |
498 | memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP), | |
499 | &pp->dimm_buf, PDC_DIMM_HEADER_SZ); | |
500 | memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) + | |
501 | PDC_DIMM_HOST_PRD, | |
502 | &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len); | |
503 | ||
504 | /* force host FIFO dump */ | |
505 | writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); | |
506 | ||
507 | readl(dimm_mmio); /* MMIO PCI posting flush */ | |
508 | ||
509 | VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len); | |
510 | } | |
511 | ||
512 | static void pdc20621_nodata_prep(struct ata_queued_cmd *qc) | |
513 | { | |
514 | struct ata_port *ap = qc->ap; | |
515 | struct pdc_port_priv *pp = ap->private_data; | |
ea6ba10b | 516 | void __iomem *mmio = ap->host_set->mmio_base; |
1da177e4 | 517 | struct pdc_host_priv *hpriv = ap->host_set->private_data; |
ea6ba10b | 518 | void __iomem *dimm_mmio = hpriv->dimm_mmio; |
1da177e4 LT |
519 | unsigned int portno = ap->port_no; |
520 | unsigned int i; | |
521 | ||
522 | VPRINTK("ata%u: ENTER\n", ap->id); | |
523 | ||
524 | /* hard-code chip #0 */ | |
525 | mmio += PDC_CHIP0_OFS; | |
526 | ||
527 | i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno); | |
528 | ||
529 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
530 | i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i); | |
531 | else | |
532 | i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i); | |
533 | ||
534 | pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i); | |
535 | ||
536 | /* copy three S/G tables and two packets to DIMM MMIO window */ | |
537 | memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP), | |
538 | &pp->dimm_buf, PDC_DIMM_HEADER_SZ); | |
539 | ||
540 | /* force host FIFO dump */ | |
541 | writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); | |
542 | ||
543 | readl(dimm_mmio); /* MMIO PCI posting flush */ | |
544 | ||
545 | VPRINTK("ata pkt buf ofs %u, mmio copied\n", i); | |
546 | } | |
547 | ||
548 | static void pdc20621_qc_prep(struct ata_queued_cmd *qc) | |
549 | { | |
550 | switch (qc->tf.protocol) { | |
551 | case ATA_PROT_DMA: | |
552 | pdc20621_dma_prep(qc); | |
553 | break; | |
554 | case ATA_PROT_NODATA: | |
555 | pdc20621_nodata_prep(qc); | |
556 | break; | |
557 | default: | |
558 | break; | |
559 | } | |
560 | } | |
561 | ||
562 | static void __pdc20621_push_hdma(struct ata_queued_cmd *qc, | |
563 | unsigned int seq, | |
564 | u32 pkt_ofs) | |
565 | { | |
566 | struct ata_port *ap = qc->ap; | |
567 | struct ata_host_set *host_set = ap->host_set; | |
ea6ba10b | 568 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
569 | |
570 | /* hard-code chip #0 */ | |
571 | mmio += PDC_CHIP0_OFS; | |
572 | ||
573 | writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); | |
574 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ | |
575 | ||
576 | writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT); | |
577 | readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */ | |
578 | } | |
579 | ||
580 | static void pdc20621_push_hdma(struct ata_queued_cmd *qc, | |
581 | unsigned int seq, | |
582 | u32 pkt_ofs) | |
583 | { | |
584 | struct ata_port *ap = qc->ap; | |
585 | struct pdc_host_priv *pp = ap->host_set->private_data; | |
586 | unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK; | |
587 | ||
588 | if (!pp->doing_hdma) { | |
589 | __pdc20621_push_hdma(qc, seq, pkt_ofs); | |
590 | pp->doing_hdma = 1; | |
591 | return; | |
592 | } | |
593 | ||
594 | pp->hdma[idx].qc = qc; | |
595 | pp->hdma[idx].seq = seq; | |
596 | pp->hdma[idx].pkt_ofs = pkt_ofs; | |
597 | pp->hdma_prod++; | |
598 | } | |
599 | ||
600 | static void pdc20621_pop_hdma(struct ata_queued_cmd *qc) | |
601 | { | |
602 | struct ata_port *ap = qc->ap; | |
603 | struct pdc_host_priv *pp = ap->host_set->private_data; | |
604 | unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK; | |
605 | ||
606 | /* if nothing on queue, we're done */ | |
607 | if (pp->hdma_prod == pp->hdma_cons) { | |
608 | pp->doing_hdma = 0; | |
609 | return; | |
610 | } | |
611 | ||
612 | __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq, | |
613 | pp->hdma[idx].pkt_ofs); | |
614 | pp->hdma_cons++; | |
615 | } | |
616 | ||
617 | #ifdef ATA_VERBOSE_DEBUG | |
618 | static void pdc20621_dump_hdma(struct ata_queued_cmd *qc) | |
619 | { | |
620 | struct ata_port *ap = qc->ap; | |
621 | unsigned int port_no = ap->port_no; | |
622 | struct pdc_host_priv *hpriv = ap->host_set->private_data; | |
623 | void *dimm_mmio = hpriv->dimm_mmio; | |
624 | ||
625 | dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP); | |
626 | dimm_mmio += PDC_DIMM_HOST_PKT; | |
627 | ||
628 | printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio)); | |
629 | printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4)); | |
630 | printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8)); | |
631 | printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12)); | |
632 | } | |
633 | #else | |
634 | static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { } | |
635 | #endif /* ATA_VERBOSE_DEBUG */ | |
636 | ||
637 | static void pdc20621_packet_start(struct ata_queued_cmd *qc) | |
638 | { | |
639 | struct ata_port *ap = qc->ap; | |
640 | struct ata_host_set *host_set = ap->host_set; | |
641 | unsigned int port_no = ap->port_no; | |
ea6ba10b | 642 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
643 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); |
644 | u8 seq = (u8) (port_no + 1); | |
645 | unsigned int port_ofs; | |
646 | ||
647 | /* hard-code chip #0 */ | |
648 | mmio += PDC_CHIP0_OFS; | |
649 | ||
650 | VPRINTK("ata%u: ENTER\n", ap->id); | |
651 | ||
652 | wmb(); /* flush PRD, pkt writes */ | |
653 | ||
654 | port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no); | |
655 | ||
656 | /* if writing, we (1) DMA to DIMM, then (2) do ATA command */ | |
657 | if (rw && qc->tf.protocol == ATA_PROT_DMA) { | |
658 | seq += 4; | |
659 | ||
660 | pdc20621_dump_hdma(qc); | |
661 | pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT); | |
662 | VPRINTK("queued ofs 0x%x (%u), seq %u\n", | |
663 | port_ofs + PDC_DIMM_HOST_PKT, | |
664 | port_ofs + PDC_DIMM_HOST_PKT, | |
665 | seq); | |
666 | } else { | |
667 | writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); | |
668 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ | |
669 | ||
670 | writel(port_ofs + PDC_DIMM_ATA_PKT, | |
671 | (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | |
672 | readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | |
673 | VPRINTK("submitted ofs 0x%x (%u), seq %u\n", | |
674 | port_ofs + PDC_DIMM_ATA_PKT, | |
675 | port_ofs + PDC_DIMM_ATA_PKT, | |
676 | seq); | |
677 | } | |
678 | } | |
679 | ||
680 | static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc) | |
681 | { | |
682 | switch (qc->tf.protocol) { | |
683 | case ATA_PROT_DMA: | |
684 | case ATA_PROT_NODATA: | |
685 | pdc20621_packet_start(qc); | |
686 | return 0; | |
687 | ||
688 | case ATA_PROT_ATAPI_DMA: | |
689 | BUG(); | |
690 | break; | |
691 | ||
692 | default: | |
693 | break; | |
694 | } | |
695 | ||
696 | return ata_qc_issue_prot(qc); | |
697 | } | |
698 | ||
699 | static inline unsigned int pdc20621_host_intr( struct ata_port *ap, | |
700 | struct ata_queued_cmd *qc, | |
701 | unsigned int doing_hdma, | |
ea6ba10b | 702 | void __iomem *mmio) |
1da177e4 LT |
703 | { |
704 | unsigned int port_no = ap->port_no; | |
705 | unsigned int port_ofs = | |
706 | PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no); | |
707 | u8 status; | |
708 | unsigned int handled = 0; | |
709 | ||
710 | VPRINTK("ENTER\n"); | |
711 | ||
712 | if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */ | |
713 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
714 | ||
715 | /* step two - DMA from DIMM to host */ | |
716 | if (doing_hdma) { | |
717 | VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id, | |
718 | readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); | |
719 | /* get drive status; clear intr; complete txn */ | |
720 | ata_qc_complete(qc, ata_wait_idle(ap)); | |
721 | pdc20621_pop_hdma(qc); | |
722 | } | |
723 | ||
724 | /* step one - exec ATA command */ | |
725 | else { | |
726 | u8 seq = (u8) (port_no + 1 + 4); | |
727 | VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id, | |
728 | readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); | |
729 | ||
730 | /* submit hdma pkt */ | |
731 | pdc20621_dump_hdma(qc); | |
732 | pdc20621_push_hdma(qc, seq, | |
733 | port_ofs + PDC_DIMM_HOST_PKT); | |
734 | } | |
735 | handled = 1; | |
736 | ||
737 | } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */ | |
738 | ||
739 | /* step one - DMA from host to DIMM */ | |
740 | if (doing_hdma) { | |
741 | u8 seq = (u8) (port_no + 1); | |
742 | VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id, | |
743 | readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); | |
744 | ||
745 | /* submit ata pkt */ | |
746 | writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); | |
747 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); | |
748 | writel(port_ofs + PDC_DIMM_ATA_PKT, | |
749 | (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | |
750 | readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | |
751 | } | |
752 | ||
753 | /* step two - execute ATA command */ | |
754 | else { | |
755 | VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id, | |
756 | readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); | |
757 | /* get drive status; clear intr; complete txn */ | |
758 | ata_qc_complete(qc, ata_wait_idle(ap)); | |
759 | pdc20621_pop_hdma(qc); | |
760 | } | |
761 | handled = 1; | |
762 | ||
763 | /* command completion, but no data xfer */ | |
764 | } else if (qc->tf.protocol == ATA_PROT_NODATA) { | |
765 | ||
766 | status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
767 | DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status); | |
768 | ata_qc_complete(qc, status); | |
769 | handled = 1; | |
770 | ||
771 | } else { | |
772 | ap->stats.idle_irq++; | |
773 | } | |
774 | ||
775 | return handled; | |
776 | } | |
777 | ||
778 | static void pdc20621_irq_clear(struct ata_port *ap) | |
779 | { | |
780 | struct ata_host_set *host_set = ap->host_set; | |
ea6ba10b | 781 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
782 | |
783 | mmio += PDC_CHIP0_OFS; | |
784 | ||
785 | readl(mmio + PDC_20621_SEQMASK); | |
786 | } | |
787 | ||
788 | static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs) | |
789 | { | |
790 | struct ata_host_set *host_set = dev_instance; | |
791 | struct ata_port *ap; | |
792 | u32 mask = 0; | |
793 | unsigned int i, tmp, port_no; | |
794 | unsigned int handled = 0; | |
ea6ba10b | 795 | void __iomem *mmio_base; |
1da177e4 LT |
796 | |
797 | VPRINTK("ENTER\n"); | |
798 | ||
799 | if (!host_set || !host_set->mmio_base) { | |
800 | VPRINTK("QUICK EXIT\n"); | |
801 | return IRQ_NONE; | |
802 | } | |
803 | ||
804 | mmio_base = host_set->mmio_base; | |
805 | ||
806 | /* reading should also clear interrupts */ | |
807 | mmio_base += PDC_CHIP0_OFS; | |
808 | mask = readl(mmio_base + PDC_20621_SEQMASK); | |
809 | VPRINTK("mask == 0x%x\n", mask); | |
810 | ||
811 | if (mask == 0xffffffff) { | |
812 | VPRINTK("QUICK EXIT 2\n"); | |
813 | return IRQ_NONE; | |
814 | } | |
815 | mask &= 0xffff; /* only 16 tags possible */ | |
816 | if (!mask) { | |
817 | VPRINTK("QUICK EXIT 3\n"); | |
818 | return IRQ_NONE; | |
819 | } | |
820 | ||
821 | spin_lock(&host_set->lock); | |
822 | ||
823 | for (i = 1; i < 9; i++) { | |
824 | port_no = i - 1; | |
825 | if (port_no > 3) | |
826 | port_no -= 4; | |
827 | if (port_no >= host_set->n_ports) | |
828 | ap = NULL; | |
829 | else | |
830 | ap = host_set->ports[port_no]; | |
831 | tmp = mask & (1 << i); | |
832 | VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp); | |
c1389503 TH |
833 | if (tmp && ap && |
834 | !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) { | |
1da177e4 LT |
835 | struct ata_queued_cmd *qc; |
836 | ||
837 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
838 | if (qc && (!(qc->tf.ctl & ATA_NIEN))) | |
839 | handled += pdc20621_host_intr(ap, qc, (i > 4), | |
840 | mmio_base); | |
841 | } | |
842 | } | |
843 | ||
844 | spin_unlock(&host_set->lock); | |
845 | ||
846 | VPRINTK("mask == 0x%x\n", mask); | |
847 | ||
848 | VPRINTK("EXIT\n"); | |
849 | ||
850 | return IRQ_RETVAL(handled); | |
851 | } | |
852 | ||
853 | static void pdc_eng_timeout(struct ata_port *ap) | |
854 | { | |
855 | u8 drv_stat; | |
b8f6153e | 856 | struct ata_host_set *host_set = ap->host_set; |
1da177e4 | 857 | struct ata_queued_cmd *qc; |
b8f6153e | 858 | unsigned long flags; |
1da177e4 LT |
859 | |
860 | DPRINTK("ENTER\n"); | |
861 | ||
b8f6153e JG |
862 | spin_lock_irqsave(&host_set->lock, flags); |
863 | ||
1da177e4 LT |
864 | qc = ata_qc_from_tag(ap, ap->active_tag); |
865 | if (!qc) { | |
866 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", | |
867 | ap->id); | |
868 | goto out; | |
869 | } | |
870 | ||
871 | /* hack alert! We cannot use the supplied completion | |
872 | * function from inside the ->eh_strategy_handler() thread. | |
873 | * libata is the only user of ->eh_strategy_handler() in | |
874 | * any kernel, so the default scsi_done() assumes it is | |
875 | * not being called from the SCSI EH. | |
876 | */ | |
877 | qc->scsidone = scsi_finish_command; | |
878 | ||
879 | switch (qc->tf.protocol) { | |
880 | case ATA_PROT_DMA: | |
881 | case ATA_PROT_NODATA: | |
882 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); | |
883 | ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR); | |
884 | break; | |
885 | ||
886 | default: | |
887 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
888 | ||
889 | printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n", | |
890 | ap->id, qc->tf.command, drv_stat); | |
891 | ||
892 | ata_qc_complete(qc, drv_stat); | |
893 | break; | |
894 | } | |
895 | ||
896 | out: | |
b8f6153e | 897 | spin_unlock_irqrestore(&host_set->lock, flags); |
1da177e4 LT |
898 | DPRINTK("EXIT\n"); |
899 | } | |
900 | ||
901 | static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf) | |
902 | { | |
903 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
904 | tf->protocol == ATA_PROT_NODATA); | |
905 | ata_tf_load(ap, tf); | |
906 | } | |
907 | ||
908 | ||
909 | static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf) | |
910 | { | |
911 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
912 | tf->protocol == ATA_PROT_NODATA); | |
913 | ata_exec_command(ap, tf); | |
914 | } | |
915 | ||
916 | ||
917 | static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base) | |
918 | { | |
919 | port->cmd_addr = base; | |
920 | port->data_addr = base; | |
921 | port->feature_addr = | |
922 | port->error_addr = base + 0x4; | |
923 | port->nsect_addr = base + 0x8; | |
924 | port->lbal_addr = base + 0xc; | |
925 | port->lbam_addr = base + 0x10; | |
926 | port->lbah_addr = base + 0x14; | |
927 | port->device_addr = base + 0x18; | |
928 | port->command_addr = | |
929 | port->status_addr = base + 0x1c; | |
930 | port->altstatus_addr = | |
931 | port->ctl_addr = base + 0x38; | |
932 | } | |
933 | ||
934 | ||
935 | #ifdef ATA_VERBOSE_DEBUG | |
8a60a071 | 936 | static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource, |
1da177e4 LT |
937 | u32 offset, u32 size) |
938 | { | |
939 | u32 window_size; | |
940 | u16 idx; | |
941 | u8 page_mask; | |
942 | long dist; | |
ea6ba10b | 943 | void __iomem *mmio = pe->mmio_base; |
1da177e4 | 944 | struct pdc_host_priv *hpriv = pe->private_data; |
ea6ba10b | 945 | void __iomem *dimm_mmio = hpriv->dimm_mmio; |
1da177e4 LT |
946 | |
947 | /* hard-code chip #0 */ | |
948 | mmio += PDC_CHIP0_OFS; | |
949 | ||
8a60a071 JG |
950 | page_mask = 0x00; |
951 | window_size = 0x2000 * 4; /* 32K byte uchar size */ | |
952 | idx = (u16) (offset / window_size); | |
1da177e4 LT |
953 | |
954 | writel(0x01, mmio + PDC_GENERAL_CTLR); | |
955 | readl(mmio + PDC_GENERAL_CTLR); | |
956 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
957 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
958 | ||
959 | offset -= (idx * window_size); | |
960 | idx++; | |
8a60a071 | 961 | dist = ((long) (window_size - (offset + size))) >= 0 ? size : |
1da177e4 | 962 | (long) (window_size - offset); |
8a60a071 | 963 | memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4), |
1da177e4 LT |
964 | dist); |
965 | ||
8a60a071 | 966 | psource += dist; |
1da177e4 LT |
967 | size -= dist; |
968 | for (; (long) size >= (long) window_size ;) { | |
969 | writel(0x01, mmio + PDC_GENERAL_CTLR); | |
970 | readl(mmio + PDC_GENERAL_CTLR); | |
971 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
972 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
8a60a071 | 973 | memcpy_fromio((char *) psource, (char *) (dimm_mmio), |
1da177e4 LT |
974 | window_size / 4); |
975 | psource += window_size; | |
976 | size -= window_size; | |
977 | idx ++; | |
978 | } | |
979 | ||
980 | if (size) { | |
981 | writel(0x01, mmio + PDC_GENERAL_CTLR); | |
982 | readl(mmio + PDC_GENERAL_CTLR); | |
983 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
984 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
8a60a071 | 985 | memcpy_fromio((char *) psource, (char *) (dimm_mmio), |
1da177e4 LT |
986 | size / 4); |
987 | } | |
988 | } | |
989 | #endif | |
990 | ||
991 | ||
8a60a071 | 992 | static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource, |
1da177e4 LT |
993 | u32 offset, u32 size) |
994 | { | |
995 | u32 window_size; | |
996 | u16 idx; | |
997 | u8 page_mask; | |
998 | long dist; | |
ea6ba10b | 999 | void __iomem *mmio = pe->mmio_base; |
1da177e4 | 1000 | struct pdc_host_priv *hpriv = pe->private_data; |
ea6ba10b | 1001 | void __iomem *dimm_mmio = hpriv->dimm_mmio; |
1da177e4 | 1002 | |
8a60a071 | 1003 | /* hard-code chip #0 */ |
1da177e4 LT |
1004 | mmio += PDC_CHIP0_OFS; |
1005 | ||
8a60a071 JG |
1006 | page_mask = 0x00; |
1007 | window_size = 0x2000 * 4; /* 32K byte uchar size */ | |
1da177e4 LT |
1008 | idx = (u16) (offset / window_size); |
1009 | ||
1010 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
1011 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
8a60a071 | 1012 | offset -= (idx * window_size); |
1da177e4 LT |
1013 | idx++; |
1014 | dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size : | |
1015 | (long) (window_size - offset); | |
1016 | memcpy_toio((char *) (dimm_mmio + offset / 4), (char *) psource, dist); | |
1017 | writel(0x01, mmio + PDC_GENERAL_CTLR); | |
1018 | readl(mmio + PDC_GENERAL_CTLR); | |
1019 | ||
8a60a071 | 1020 | psource += dist; |
1da177e4 LT |
1021 | size -= dist; |
1022 | for (; (long) size >= (long) window_size ;) { | |
1023 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
1024 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
8a60a071 | 1025 | memcpy_toio((char *) (dimm_mmio), (char *) psource, |
1da177e4 LT |
1026 | window_size / 4); |
1027 | writel(0x01, mmio + PDC_GENERAL_CTLR); | |
1028 | readl(mmio + PDC_GENERAL_CTLR); | |
1029 | psource += window_size; | |
1030 | size -= window_size; | |
1031 | idx ++; | |
1032 | } | |
8a60a071 | 1033 | |
1da177e4 LT |
1034 | if (size) { |
1035 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
1036 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
1037 | memcpy_toio((char *) (dimm_mmio), (char *) psource, size / 4); | |
1038 | writel(0x01, mmio + PDC_GENERAL_CTLR); | |
1039 | readl(mmio + PDC_GENERAL_CTLR); | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | ||
8a60a071 | 1044 | static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device, |
1da177e4 LT |
1045 | u32 subaddr, u32 *pdata) |
1046 | { | |
ea6ba10b | 1047 | void __iomem *mmio = pe->mmio_base; |
1da177e4 | 1048 | u32 i2creg = 0; |
8a60a071 | 1049 | u32 status; |
1da177e4 LT |
1050 | u32 count =0; |
1051 | ||
1052 | /* hard-code chip #0 */ | |
1053 | mmio += PDC_CHIP0_OFS; | |
1054 | ||
1055 | i2creg |= device << 24; | |
1056 | i2creg |= subaddr << 16; | |
1057 | ||
1058 | /* Set the device and subaddress */ | |
1059 | writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET); | |
1060 | readl(mmio + PDC_I2C_ADDR_DATA_OFFSET); | |
1061 | ||
1062 | /* Write Control to perform read operation, mask int */ | |
8a60a071 | 1063 | writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT, |
1da177e4 LT |
1064 | mmio + PDC_I2C_CONTROL_OFFSET); |
1065 | ||
1066 | for (count = 0; count <= 1000; count ++) { | |
1067 | status = readl(mmio + PDC_I2C_CONTROL_OFFSET); | |
1068 | if (status & PDC_I2C_COMPLETE) { | |
1069 | status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET); | |
1070 | break; | |
1071 | } else if (count == 1000) | |
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | *pdata = (status >> 8) & 0x000000ff; | |
8a60a071 | 1076 | return 1; |
1da177e4 LT |
1077 | } |
1078 | ||
1079 | ||
1080 | static int pdc20621_detect_dimm(struct ata_probe_ent *pe) | |
1081 | { | |
1082 | u32 data=0 ; | |
8a60a071 | 1083 | if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, |
1da177e4 LT |
1084 | PDC_DIMM_SPD_SYSTEM_FREQ, &data)) { |
1085 | if (data == 100) | |
1086 | return 100; | |
1087 | } else | |
1088 | return 0; | |
8a60a071 | 1089 | |
1da177e4 | 1090 | if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) { |
8a60a071 | 1091 | if(data <= 0x75) |
1da177e4 LT |
1092 | return 133; |
1093 | } else | |
1094 | return 0; | |
8a60a071 | 1095 | |
1da177e4 LT |
1096 | return 0; |
1097 | } | |
1098 | ||
1099 | ||
1100 | static int pdc20621_prog_dimm0(struct ata_probe_ent *pe) | |
1101 | { | |
1102 | u32 spd0[50]; | |
1103 | u32 data = 0; | |
1104 | int size, i; | |
8a60a071 | 1105 | u8 bdimmsize; |
ea6ba10b | 1106 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
1107 | static const struct { |
1108 | unsigned int reg; | |
1109 | unsigned int ofs; | |
1110 | } pdc_i2c_read_data [] = { | |
8a60a071 | 1111 | { PDC_DIMM_SPD_TYPE, 11 }, |
1da177e4 | 1112 | { PDC_DIMM_SPD_FRESH_RATE, 12 }, |
8a60a071 | 1113 | { PDC_DIMM_SPD_COLUMN_NUM, 4 }, |
1da177e4 LT |
1114 | { PDC_DIMM_SPD_ATTRIBUTE, 21 }, |
1115 | { PDC_DIMM_SPD_ROW_NUM, 3 }, | |
1116 | { PDC_DIMM_SPD_BANK_NUM, 17 }, | |
1117 | { PDC_DIMM_SPD_MODULE_ROW, 5 }, | |
1118 | { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 }, | |
1119 | { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 }, | |
1120 | { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 }, | |
1121 | { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 }, | |
8a60a071 | 1122 | { PDC_DIMM_SPD_CAS_LATENCY, 18 }, |
1da177e4 LT |
1123 | }; |
1124 | ||
1125 | /* hard-code chip #0 */ | |
1126 | mmio += PDC_CHIP0_OFS; | |
1127 | ||
1128 | for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++) | |
1129 | pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, | |
8a60a071 | 1130 | pdc_i2c_read_data[i].reg, |
1da177e4 | 1131 | &spd0[pdc_i2c_read_data[i].ofs]); |
8a60a071 | 1132 | |
1da177e4 | 1133 | data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4); |
8a60a071 | 1134 | data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) | |
1da177e4 | 1135 | ((((spd0[27] + 9) / 10) - 1) << 8) ; |
8a60a071 JG |
1136 | data |= (((((spd0[29] > spd0[28]) |
1137 | ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10; | |
1da177e4 | 1138 | data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12; |
8a60a071 JG |
1139 | |
1140 | if (spd0[18] & 0x08) | |
1da177e4 LT |
1141 | data |= ((0x03) << 14); |
1142 | else if (spd0[18] & 0x04) | |
1143 | data |= ((0x02) << 14); | |
1144 | else if (spd0[18] & 0x01) | |
1145 | data |= ((0x01) << 14); | |
1146 | else | |
1147 | data |= (0 << 14); | |
1148 | ||
8a60a071 | 1149 | /* |
1da177e4 LT |
1150 | Calculate the size of bDIMMSize (power of 2) and |
1151 | merge the DIMM size by program start/end address. | |
1152 | */ | |
1153 | ||
1154 | bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3; | |
1155 | size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */ | |
1156 | data |= (((size / 16) - 1) << 16); | |
1157 | data |= (0 << 23); | |
1158 | data |= 8; | |
8a60a071 | 1159 | writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET); |
1da177e4 | 1160 | readl(mmio + PDC_DIMM0_CONTROL_OFFSET); |
8a60a071 | 1161 | return size; |
1da177e4 LT |
1162 | } |
1163 | ||
1164 | ||
1165 | static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe) | |
1166 | { | |
1167 | u32 data, spd0; | |
1168 | int error, i; | |
ea6ba10b | 1169 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
1170 | |
1171 | /* hard-code chip #0 */ | |
1172 | mmio += PDC_CHIP0_OFS; | |
1173 | ||
1174 | /* | |
1175 | Set To Default : DIMM Module Global Control Register (0x022259F1) | |
1176 | DIMM Arbitration Disable (bit 20) | |
1177 | DIMM Data/Control Output Driving Selection (bit12 - bit15) | |
1178 | Refresh Enable (bit 17) | |
1179 | */ | |
1180 | ||
8a60a071 | 1181 | data = 0x022259F1; |
1da177e4 LT |
1182 | writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET); |
1183 | readl(mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1184 | ||
1185 | /* Turn on for ECC */ | |
8a60a071 | 1186 | pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, |
1da177e4 LT |
1187 | PDC_DIMM_SPD_TYPE, &spd0); |
1188 | if (spd0 == 0x02) { | |
1189 | data |= (0x01 << 16); | |
1190 | writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1191 | readl(mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1192 | printk(KERN_ERR "Local DIMM ECC Enabled\n"); | |
1193 | } | |
1194 | ||
1195 | /* DIMM Initialization Select/Enable (bit 18/19) */ | |
1196 | data &= (~(1<<18)); | |
1197 | data |= (1<<19); | |
1198 | writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1199 | ||
8a60a071 | 1200 | error = 1; |
1da177e4 LT |
1201 | for (i = 1; i <= 10; i++) { /* polling ~5 secs */ |
1202 | data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1203 | if (!(data & (1<<19))) { | |
1204 | error = 0; | |
8a60a071 | 1205 | break; |
1da177e4 LT |
1206 | } |
1207 | msleep(i*100); | |
1208 | } | |
1209 | return error; | |
1210 | } | |
8a60a071 | 1211 | |
1da177e4 LT |
1212 | |
1213 | static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe) | |
1214 | { | |
8a60a071 | 1215 | int speed, size, length; |
1da177e4 LT |
1216 | u32 addr,spd0,pci_status; |
1217 | u32 tmp=0; | |
1218 | u32 time_period=0; | |
1219 | u32 tcount=0; | |
1220 | u32 ticks=0; | |
1221 | u32 clock=0; | |
1222 | u32 fparam=0; | |
ea6ba10b | 1223 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
1224 | |
1225 | /* hard-code chip #0 */ | |
1226 | mmio += PDC_CHIP0_OFS; | |
1227 | ||
1228 | /* Initialize PLL based upon PCI Bus Frequency */ | |
1229 | ||
1230 | /* Initialize Time Period Register */ | |
1231 | writel(0xffffffff, mmio + PDC_TIME_PERIOD); | |
1232 | time_period = readl(mmio + PDC_TIME_PERIOD); | |
1233 | VPRINTK("Time Period Register (0x40): 0x%x\n", time_period); | |
1234 | ||
1235 | /* Enable timer */ | |
1236 | writel(0x00001a0, mmio + PDC_TIME_CONTROL); | |
1237 | readl(mmio + PDC_TIME_CONTROL); | |
1238 | ||
1239 | /* Wait 3 seconds */ | |
1240 | msleep(3000); | |
1241 | ||
8a60a071 | 1242 | /* |
1da177e4 LT |
1243 | When timer is enabled, counter is decreased every internal |
1244 | clock cycle. | |
1245 | */ | |
1246 | ||
1247 | tcount = readl(mmio + PDC_TIME_COUNTER); | |
1248 | VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount); | |
1249 | ||
8a60a071 | 1250 | /* |
1da177e4 LT |
1251 | If SX4 is on PCI-X bus, after 3 seconds, the timer counter |
1252 | register should be >= (0xffffffff - 3x10^8). | |
1253 | */ | |
1254 | if(tcount >= PCI_X_TCOUNT) { | |
1255 | ticks = (time_period - tcount); | |
1256 | VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks); | |
8a60a071 | 1257 | |
1da177e4 LT |
1258 | clock = (ticks / 300000); |
1259 | VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock); | |
8a60a071 | 1260 | |
1da177e4 LT |
1261 | clock = (clock * 33); |
1262 | VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock); | |
1263 | ||
1264 | /* PLL F Param (bit 22:16) */ | |
1265 | fparam = (1400000 / clock) - 2; | |
1266 | VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam); | |
8a60a071 | 1267 | |
1da177e4 LT |
1268 | /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */ |
1269 | pci_status = (0x8a001824 | (fparam << 16)); | |
1270 | } else | |
1271 | pci_status = PCI_PLL_INIT; | |
1272 | ||
1273 | /* Initialize PLL. */ | |
1274 | VPRINTK("pci_status: 0x%x\n", pci_status); | |
1275 | writel(pci_status, mmio + PDC_CTL_STATUS); | |
1276 | readl(mmio + PDC_CTL_STATUS); | |
1277 | ||
8a60a071 | 1278 | /* |
1da177e4 LT |
1279 | Read SPD of DIMM by I2C interface, |
1280 | and program the DIMM Module Controller. | |
1281 | */ | |
1282 | if (!(speed = pdc20621_detect_dimm(pe))) { | |
8a60a071 | 1283 | printk(KERN_ERR "Detect Local DIMM Fail\n"); |
1da177e4 LT |
1284 | return 1; /* DIMM error */ |
1285 | } | |
1286 | VPRINTK("Local DIMM Speed = %d\n", speed); | |
1287 | ||
8a60a071 | 1288 | /* Programming DIMM0 Module Control Register (index_CID0:80h) */ |
1da177e4 LT |
1289 | size = pdc20621_prog_dimm0(pe); |
1290 | VPRINTK("Local DIMM Size = %dMB\n",size); | |
1291 | ||
8a60a071 | 1292 | /* Programming DIMM Module Global Control Register (index_CID0:88h) */ |
1da177e4 LT |
1293 | if (pdc20621_prog_dimm_global(pe)) { |
1294 | printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n"); | |
1295 | return 1; | |
1296 | } | |
1297 | ||
1298 | #ifdef ATA_VERBOSE_DEBUG | |
1299 | { | |
1300 | u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ', | |
1301 | 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ', | |
1302 | '1','.','1','0', | |
1303 | '9','8','0','3','1','6','1','2',0,0}; | |
1304 | u8 test_parttern2[40] = {0}; | |
1305 | ||
1306 | pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40); | |
1307 | pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40); | |
1308 | ||
1309 | pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40); | |
1310 | pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40); | |
8a60a071 | 1311 | printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], |
1da177e4 | 1312 | test_parttern2[1], &(test_parttern2[2])); |
8a60a071 | 1313 | pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040, |
1da177e4 | 1314 | 40); |
8a60a071 | 1315 | printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], |
1da177e4 LT |
1316 | test_parttern2[1], &(test_parttern2[2])); |
1317 | ||
1318 | pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40); | |
1319 | pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40); | |
8a60a071 | 1320 | printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], |
1da177e4 LT |
1321 | test_parttern2[1], &(test_parttern2[2])); |
1322 | } | |
1323 | #endif | |
1324 | ||
1325 | /* ECC initiliazation. */ | |
1326 | ||
8a60a071 | 1327 | pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, |
1da177e4 LT |
1328 | PDC_DIMM_SPD_TYPE, &spd0); |
1329 | if (spd0 == 0x02) { | |
1330 | VPRINTK("Start ECC initialization\n"); | |
1331 | addr = 0; | |
1332 | length = size * 1024 * 1024; | |
1333 | while (addr < length) { | |
8a60a071 | 1334 | pdc20621_put_to_dimm(pe, (void *) &tmp, addr, |
1da177e4 LT |
1335 | sizeof(u32)); |
1336 | addr += sizeof(u32); | |
1337 | } | |
1338 | VPRINTK("Finish ECC initialization\n"); | |
1339 | } | |
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | ||
1344 | static void pdc_20621_init(struct ata_probe_ent *pe) | |
1345 | { | |
1346 | u32 tmp; | |
ea6ba10b | 1347 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
1348 | |
1349 | /* hard-code chip #0 */ | |
1350 | mmio += PDC_CHIP0_OFS; | |
1351 | ||
1352 | /* | |
1353 | * Select page 0x40 for our 32k DIMM window | |
1354 | */ | |
1355 | tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000; | |
1356 | tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */ | |
1357 | writel(tmp, mmio + PDC_20621_DIMM_WINDOW); | |
1358 | ||
1359 | /* | |
1360 | * Reset Host DMA | |
1361 | */ | |
1362 | tmp = readl(mmio + PDC_HDMA_CTLSTAT); | |
1363 | tmp |= PDC_RESET; | |
1364 | writel(tmp, mmio + PDC_HDMA_CTLSTAT); | |
1365 | readl(mmio + PDC_HDMA_CTLSTAT); /* flush */ | |
1366 | ||
1367 | udelay(10); | |
1368 | ||
1369 | tmp = readl(mmio + PDC_HDMA_CTLSTAT); | |
1370 | tmp &= ~PDC_RESET; | |
1371 | writel(tmp, mmio + PDC_HDMA_CTLSTAT); | |
1372 | readl(mmio + PDC_HDMA_CTLSTAT); /* flush */ | |
1373 | } | |
1374 | ||
1375 | static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1376 | { | |
1377 | static int printed_version; | |
1378 | struct ata_probe_ent *probe_ent = NULL; | |
1379 | unsigned long base; | |
ea6ba10b JG |
1380 | void __iomem *mmio_base; |
1381 | void __iomem *dimm_mmio = NULL; | |
1da177e4 LT |
1382 | struct pdc_host_priv *hpriv = NULL; |
1383 | unsigned int board_idx = (unsigned int) ent->driver_data; | |
1384 | int pci_dev_busy = 0; | |
1385 | int rc; | |
1386 | ||
1387 | if (!printed_version++) | |
1388 | printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); | |
1389 | ||
1390 | /* | |
1391 | * If this driver happens to only be useful on Apple's K2, then | |
1392 | * we should check that here as it has a normal Serverworks ID | |
1393 | */ | |
1394 | rc = pci_enable_device(pdev); | |
1395 | if (rc) | |
1396 | return rc; | |
1397 | ||
1398 | rc = pci_request_regions(pdev, DRV_NAME); | |
1399 | if (rc) { | |
1400 | pci_dev_busy = 1; | |
1401 | goto err_out; | |
1402 | } | |
1403 | ||
1404 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
1405 | if (rc) | |
1406 | goto err_out_regions; | |
1407 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1408 | if (rc) | |
1409 | goto err_out_regions; | |
1410 | ||
1411 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
1412 | if (probe_ent == NULL) { | |
1413 | rc = -ENOMEM; | |
1414 | goto err_out_regions; | |
1415 | } | |
1416 | ||
1417 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
1418 | probe_ent->dev = pci_dev_to_dev(pdev); | |
1419 | INIT_LIST_HEAD(&probe_ent->node); | |
1420 | ||
1421 | mmio_base = ioremap(pci_resource_start(pdev, 3), | |
1422 | pci_resource_len(pdev, 3)); | |
1423 | if (mmio_base == NULL) { | |
1424 | rc = -ENOMEM; | |
1425 | goto err_out_free_ent; | |
1426 | } | |
1427 | base = (unsigned long) mmio_base; | |
1428 | ||
1429 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
1430 | if (!hpriv) { | |
1431 | rc = -ENOMEM; | |
1432 | goto err_out_iounmap; | |
1433 | } | |
1434 | memset(hpriv, 0, sizeof(*hpriv)); | |
1435 | ||
1436 | dimm_mmio = ioremap(pci_resource_start(pdev, 4), | |
1437 | pci_resource_len(pdev, 4)); | |
1438 | if (!dimm_mmio) { | |
1439 | kfree(hpriv); | |
1440 | rc = -ENOMEM; | |
1441 | goto err_out_iounmap; | |
1442 | } | |
1443 | ||
1444 | hpriv->dimm_mmio = dimm_mmio; | |
1445 | ||
1446 | probe_ent->sht = pdc_port_info[board_idx].sht; | |
1447 | probe_ent->host_flags = pdc_port_info[board_idx].host_flags; | |
1448 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; | |
1449 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
1450 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
1451 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
1452 | ||
1453 | probe_ent->irq = pdev->irq; | |
1454 | probe_ent->irq_flags = SA_SHIRQ; | |
1455 | probe_ent->mmio_base = mmio_base; | |
1456 | ||
1457 | probe_ent->private_data = hpriv; | |
1458 | base += PDC_CHIP0_OFS; | |
1459 | ||
1460 | probe_ent->n_ports = 4; | |
1461 | pdc_sata_setup_port(&probe_ent->port[0], base + 0x200); | |
1462 | pdc_sata_setup_port(&probe_ent->port[1], base + 0x280); | |
1463 | pdc_sata_setup_port(&probe_ent->port[2], base + 0x300); | |
1464 | pdc_sata_setup_port(&probe_ent->port[3], base + 0x380); | |
1465 | ||
1466 | pci_set_master(pdev); | |
1467 | ||
1468 | /* initialize adapter */ | |
1469 | /* initialize local dimm */ | |
1470 | if (pdc20621_dimm_init(probe_ent)) { | |
1471 | rc = -ENOMEM; | |
1472 | goto err_out_iounmap_dimm; | |
1473 | } | |
1474 | pdc_20621_init(probe_ent); | |
1475 | ||
1476 | /* FIXME: check ata_device_add return value */ | |
1477 | ata_device_add(probe_ent); | |
1478 | kfree(probe_ent); | |
1479 | ||
1480 | return 0; | |
1481 | ||
1482 | err_out_iounmap_dimm: /* only get to this label if 20621 */ | |
1483 | kfree(hpriv); | |
1484 | iounmap(dimm_mmio); | |
1485 | err_out_iounmap: | |
1486 | iounmap(mmio_base); | |
1487 | err_out_free_ent: | |
1488 | kfree(probe_ent); | |
1489 | err_out_regions: | |
1490 | pci_release_regions(pdev); | |
1491 | err_out: | |
1492 | if (!pci_dev_busy) | |
1493 | pci_disable_device(pdev); | |
1494 | return rc; | |
1495 | } | |
1496 | ||
1497 | ||
1498 | static int __init pdc_sata_init(void) | |
1499 | { | |
1500 | return pci_module_init(&pdc_sata_pci_driver); | |
1501 | } | |
1502 | ||
1503 | ||
1504 | static void __exit pdc_sata_exit(void) | |
1505 | { | |
1506 | pci_unregister_driver(&pdc_sata_pci_driver); | |
1507 | } | |
1508 | ||
1509 | ||
1510 | MODULE_AUTHOR("Jeff Garzik"); | |
1511 | MODULE_DESCRIPTION("Promise SATA low-level driver"); | |
1512 | MODULE_LICENSE("GPL"); | |
1513 | MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl); | |
1514 | MODULE_VERSION(DRV_VERSION); | |
1515 | ||
1516 | module_init(pdc_sata_init); | |
1517 | module_exit(pdc_sata_exit); |