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Merge /spare/repo/linux-2.6/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / sata_sx4.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
13 * by reference.
14 *
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
25 *
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/init.h>
32#include <linux/blkdev.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/sched.h>
36#include "scsi.h"
37#include <scsi/scsi_host.h>
38#include <linux/libata.h>
39#include <asm/io.h>
40#include "sata_promise.h"
41
42#define DRV_NAME "sata_sx4"
43#define DRV_VERSION "0.7"
44
45
46enum {
47 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
48
49 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
50 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
51 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
52 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
53
54 PDC_20621_SEQCTL = 0x400,
55 PDC_20621_SEQMASK = 0x480,
56 PDC_20621_GENERAL_CTL = 0x484,
57 PDC_20621_PAGE_SIZE = (32 * 1024),
58
59 /* chosen, not constant, values; we design our own DIMM mem map */
60 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
61 PDC_20621_DIMM_BASE = 0x00200000,
62 PDC_20621_DIMM_DATA = (64 * 1024),
63 PDC_DIMM_DATA_STEP = (256 * 1024),
64 PDC_DIMM_WINDOW_STEP = (8 * 1024),
65 PDC_DIMM_HOST_PRD = (6 * 1024),
66 PDC_DIMM_HOST_PKT = (128 * 0),
67 PDC_DIMM_HPKT_PRD = (128 * 1),
68 PDC_DIMM_ATA_PKT = (128 * 2),
69 PDC_DIMM_APKT_PRD = (128 * 3),
70 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
71 PDC_PAGE_WINDOW = 0x40,
72 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
73 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
74 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
75
76 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
77
78 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
79 (1<<23),
80
81 board_20621 = 0, /* FastTrak S150 SX4 */
82
83 PDC_RESET = (1 << 11), /* HDMA reset */
84
85 PDC_MAX_HDMA = 32,
86 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
87
88 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
89 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
90 PDC_MAX_DIMM_MODULE = 0x02,
91 PDC_I2C_CONTROL_OFFSET = 0x48,
92 PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
93 PDC_DIMM0_CONTROL_OFFSET = 0x80,
94 PDC_DIMM1_CONTROL_OFFSET = 0x84,
95 PDC_SDRAM_CONTROL_OFFSET = 0x88,
96 PDC_I2C_WRITE = 0x00000000,
8a60a071 97 PDC_I2C_READ = 0x00000040,
1da177e4
LT		 98 PDC_I2C_START = 0x00000080,
99 PDC_I2C_MASK_INT = 0x00000020,
100 PDC_I2C_COMPLETE = 0x00010000,
101 PDC_I2C_NO_ACK = 0x00100000,
102 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
103 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
104 PDC_DIMM_SPD_ROW_NUM = 3,
105 PDC_DIMM_SPD_COLUMN_NUM = 4,
106 PDC_DIMM_SPD_MODULE_ROW = 5,
107 PDC_DIMM_SPD_TYPE = 11,
8a60a071
JG		 108 PDC_DIMM_SPD_FRESH_RATE = 12,
109 PDC_DIMM_SPD_BANK_NUM = 17,
1da177e4 110 PDC_DIMM_SPD_CAS_LATENCY = 18,
8a60a071 111 PDC_DIMM_SPD_ATTRIBUTE = 21,
1da177e4 112 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
8a60a071 113 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
1da177e4
LT		 114 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
115 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
116 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
8a60a071 117 PDC_CTL_STATUS = 0x08,
1da177e4
LT		 118 PDC_DIMM_WINDOW_CTLR = 0x0C,
119 PDC_TIME_CONTROL = 0x3C,
120 PDC_TIME_PERIOD = 0x40,
121 PDC_TIME_COUNTER = 0x44,
122 PDC_GENERAL_CTLR = 0x484,
123 PCI_PLL_INIT = 0x8A531824,
124 PCI_X_TCOUNT = 0xEE1E5CFF
125};
126
127
128struct pdc_port_priv {
129 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
130 u8 *pkt;
131 dma_addr_t pkt_dma;
132};
133
134struct pdc_host_priv {
135 void *dimm_mmio;
136
137 unsigned int doing_hdma;
138 unsigned int hdma_prod;
139 unsigned int hdma_cons;
140 struct {
141 struct ata_queued_cmd *qc;
142 unsigned int seq;
143 unsigned long pkt_ofs;
144 } hdma[32];
145};
146
147
148static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
149static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
150static void pdc_eng_timeout(struct ata_port *ap);
151static void pdc_20621_phy_reset (struct ata_port *ap);
152static int pdc_port_start(struct ata_port *ap);
153static void pdc_port_stop(struct ata_port *ap);
154static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
155static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
156static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
157static void pdc20621_host_stop(struct ata_host_set *host_set);
158static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
159static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
8a60a071 160static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
1da177e4
LT		 161 u32 device, u32 subaddr, u32 *pdata);
162static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
163static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
164#ifdef ATA_VERBOSE_DEBUG
8a60a071 165static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
1da177e4
LT		 166 void *psource, u32 offset, u32 size);
167#endif
8a60a071 168static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
1da177e4
LT		 169 void *psource, u32 offset, u32 size);
170static void pdc20621_irq_clear(struct ata_port *ap);
171static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
172
173
174static Scsi_Host_Template pdc_sata_sht = {
175 .module = THIS_MODULE,
176 .name = DRV_NAME,
177 .ioctl = ata_scsi_ioctl,
178 .queuecommand = ata_scsi_queuecmd,
179 .eh_strategy_handler = ata_scsi_error,
180 .can_queue = ATA_DEF_QUEUE,
181 .this_id = ATA_SHT_THIS_ID,
182 .sg_tablesize = LIBATA_MAX_PRD,
183 .max_sectors = ATA_MAX_SECTORS,
184 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
185 .emulated = ATA_SHT_EMULATED,
186 .use_clustering = ATA_SHT_USE_CLUSTERING,
187 .proc_name = DRV_NAME,
188 .dma_boundary = ATA_DMA_BOUNDARY,
189 .slave_configure = ata_scsi_slave_config,
190 .bios_param = ata_std_bios_param,
191 .ordered_flush = 1,
192};
193
194static struct ata_port_operations pdc_20621_ops = {
195 .port_disable = ata_port_disable,
196 .tf_load = pdc_tf_load_mmio,
197 .tf_read = ata_tf_read,
198 .check_status = ata_check_status,
199 .exec_command = pdc_exec_command_mmio,
200 .dev_select = ata_std_dev_select,
201 .phy_reset = pdc_20621_phy_reset,
202 .qc_prep = pdc20621_qc_prep,
203 .qc_issue = pdc20621_qc_issue_prot,
204 .eng_timeout = pdc_eng_timeout,
205 .irq_handler = pdc20621_interrupt,
206 .irq_clear = pdc20621_irq_clear,
207 .port_start = pdc_port_start,
208 .port_stop = pdc_port_stop,
209 .host_stop = pdc20621_host_stop,
210};
211
212static struct ata_port_info pdc_port_info[] = {
213 /* board_20621 */
214 {
215 .sht = &pdc_sata_sht,
216 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
217 ATA_FLAG_SRST | ATA_FLAG_MMIO,
218 .pio_mask = 0x1f, /* pio0-4 */
219 .mwdma_mask = 0x07, /* mwdma0-2 */
220 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
221 .port_ops = &pdc_20621_ops,
222 },
223
224};
225
226static struct pci_device_id pdc_sata_pci_tbl[] = {
227 { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
228 board_20621 },
229 { } /* terminate list */
230};
231
232
233static struct pci_driver pdc_sata_pci_driver = {
234 .name = DRV_NAME,
235 .id_table = pdc_sata_pci_tbl,
236 .probe = pdc_sata_init_one,
237 .remove = ata_pci_remove_one,
238};
239
240
241static void pdc20621_host_stop(struct ata_host_set *host_set)
242{
243 struct pdc_host_priv *hpriv = host_set->private_data;
244 void *dimm_mmio = hpriv->dimm_mmio;
245
246 iounmap(dimm_mmio);
247 kfree(hpriv);
aa8f0dc6
JG		 248
249 ata_host_stop(host_set);
1da177e4
LT		 250}
251
252static int pdc_port_start(struct ata_port *ap)
253{
254 struct device *dev = ap->host_set->dev;
255 struct pdc_port_priv *pp;
256 int rc;
257
258 rc = ata_port_start(ap);
259 if (rc)
260 return rc;
261
262 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
263 if (!pp) {
264 rc = -ENOMEM;
265 goto err_out;
266 }
267 memset(pp, 0, sizeof(*pp));
268
269 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
270 if (!pp->pkt) {
271 rc = -ENOMEM;
272 goto err_out_kfree;
273 }
274
275 ap->private_data = pp;
276
277 return 0;
278
279err_out_kfree:
280 kfree(pp);
281err_out:
282 ata_port_stop(ap);
283 return rc;
284}
285
286
287static void pdc_port_stop(struct ata_port *ap)
288{
289 struct device *dev = ap->host_set->dev;
290 struct pdc_port_priv *pp = ap->private_data;
291
292 ap->private_data = NULL;
293 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
294 kfree(pp);
295 ata_port_stop(ap);
296}
297
298
299static void pdc_20621_phy_reset (struct ata_port *ap)
300{
301 VPRINTK("ENTER\n");
302 ap->cbl = ATA_CBL_SATA;
303 ata_port_probe(ap);
304 ata_bus_reset(ap);
305}
306
307static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
308 unsigned int portno,
309 unsigned int total_len)
310{
311 u32 addr;
312 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
313 u32 *buf32 = (u32 *) buf;
314
315 /* output ATA packet S/G table */
316 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
317 (PDC_DIMM_DATA_STEP * portno);
318 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
319 buf32[dw] = cpu_to_le32(addr);
320 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
321
322 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
323 PDC_20621_DIMM_BASE +
324 (PDC_DIMM_WINDOW_STEP * portno) +
325 PDC_DIMM_APKT_PRD,
326 buf32[dw], buf32[dw + 1]);
327}
328
329static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
330 unsigned int portno,
331 unsigned int total_len)
332{
333 u32 addr;
334 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
335 u32 *buf32 = (u32 *) buf;
336
337 /* output Host DMA packet S/G table */
338 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
339 (PDC_DIMM_DATA_STEP * portno);
340
341 buf32[dw] = cpu_to_le32(addr);
342 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
343
344 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
345 PDC_20621_DIMM_BASE +
346 (PDC_DIMM_WINDOW_STEP * portno) +
347 PDC_DIMM_HPKT_PRD,
348 buf32[dw], buf32[dw + 1]);
349}
350
351static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
352 unsigned int devno, u8 *buf,
353 unsigned int portno)
354{
355 unsigned int i, dw;
356 u32 *buf32 = (u32 *) buf;
357 u8 dev_reg;
358
359 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
360 (PDC_DIMM_WINDOW_STEP * portno) +
361 PDC_DIMM_APKT_PRD;
362 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
363
364 i = PDC_DIMM_ATA_PKT;
365
366 /*
367 * Set up ATA packet
368 */
369 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
370 buf[i++] = PDC_PKT_READ;
371 else if (tf->protocol == ATA_PROT_NODATA)
372 buf[i++] = PDC_PKT_NODATA;
373 else
374 buf[i++] = 0;
375 buf[i++] = 0; /* reserved */
376 buf[i++] = portno + 1; /* seq. id */
377 buf[i++] = 0xff; /* delay seq. id */
378
379 /* dimm dma S/G, and next-pkt */
380 dw = i >> 2;
381 if (tf->protocol == ATA_PROT_NODATA)
382 buf32[dw] = 0;
383 else
384 buf32[dw] = cpu_to_le32(dimm_sg);
385 buf32[dw + 1] = 0;
386 i += 8;
387
388 if (devno == 0)
389 dev_reg = ATA_DEVICE_OBS;
390 else
391 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
392
393 /* select device */
394 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
395 buf[i++] = dev_reg;
396
397 /* device control register */
398 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
399 buf[i++] = tf->ctl;
400
401 return i;
402}
403
404static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
405 unsigned int portno)
406{
407 unsigned int dw;
408 u32 tmp, *buf32 = (u32 *) buf;
409
410 unsigned int host_sg = PDC_20621_DIMM_BASE +
411 (PDC_DIMM_WINDOW_STEP * portno) +
412 PDC_DIMM_HOST_PRD;
413 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
414 (PDC_DIMM_WINDOW_STEP * portno) +
415 PDC_DIMM_HPKT_PRD;
416 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
417 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
418
419 dw = PDC_DIMM_HOST_PKT >> 2;
420
421 /*
422 * Set up Host DMA packet
423 */
424 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
425 tmp = PDC_PKT_READ;
426 else
427 tmp = 0;
428 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
429 tmp |= (0xff << 24); /* delay seq. id */
430 buf32[dw + 0] = cpu_to_le32(tmp);
431 buf32[dw + 1] = cpu_to_le32(host_sg);
432 buf32[dw + 2] = cpu_to_le32(dimm_sg);
433 buf32[dw + 3] = 0;
434
435 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
436 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
437 PDC_DIMM_HOST_PKT,
438 buf32[dw + 0],
439 buf32[dw + 1],
440 buf32[dw + 2],
441 buf32[dw + 3]);
442}
443
444static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
445{
446 struct scatterlist *sg = qc->sg;
447 struct ata_port *ap = qc->ap;
448 struct pdc_port_priv *pp = ap->private_data;
449 void *mmio = ap->host_set->mmio_base;
450 struct pdc_host_priv *hpriv = ap->host_set->private_data;
451 void *dimm_mmio = hpriv->dimm_mmio;
452 unsigned int portno = ap->port_no;
453 unsigned int i, last, idx, total_len = 0, sgt_len;
454 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
455
456 assert(qc->flags & ATA_QCFLAG_DMAMAP);
457
458 VPRINTK("ata%u: ENTER\n", ap->id);
459
460 /* hard-code chip #0 */
461 mmio += PDC_CHIP0_OFS;
462
463 /*
464 * Build S/G table
465 */
466 last = qc->n_elem;
467 idx = 0;
468 for (i = 0; i < last; i++) {
469 buf[idx++] = cpu_to_le32(sg_dma_address(&sg[i]));
470 buf[idx++] = cpu_to_le32(sg_dma_len(&sg[i]));
fae00984 471 total_len += sg_dma_len(&sg[i]);
1da177e4
LT		 472 }
473 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
474 sgt_len = idx * 4;
475
476 /*
477 * Build ATA, host DMA packets
478 */
479 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
480 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
481
482 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
483 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
484
485 if (qc->tf.flags & ATA_TFLAG_LBA48)
486 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
487 else
488 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
489
490 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
491
492 /* copy three S/G tables and two packets to DIMM MMIO window */
493 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
494 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
495 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
496 PDC_DIMM_HOST_PRD,
497 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
498
499 /* force host FIFO dump */
500 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
501
502 readl(dimm_mmio); /* MMIO PCI posting flush */
503
504 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
505}
506
507static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
508{
509 struct ata_port *ap = qc->ap;
510 struct pdc_port_priv *pp = ap->private_data;
511 void *mmio = ap->host_set->mmio_base;
512 struct pdc_host_priv *hpriv = ap->host_set->private_data;
513 void *dimm_mmio = hpriv->dimm_mmio;
514 unsigned int portno = ap->port_no;
515 unsigned int i;
516
517 VPRINTK("ata%u: ENTER\n", ap->id);
518
519 /* hard-code chip #0 */
520 mmio += PDC_CHIP0_OFS;
521
522 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
523
524 if (qc->tf.flags & ATA_TFLAG_LBA48)
525 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
526 else
527 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
528
529 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
530
531 /* copy three S/G tables and two packets to DIMM MMIO window */
532 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
533 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
534
535 /* force host FIFO dump */
536 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
537
538 readl(dimm_mmio); /* MMIO PCI posting flush */
539
540 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
541}
542
543static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
544{
545 switch (qc->tf.protocol) {
546 case ATA_PROT_DMA:
547 pdc20621_dma_prep(qc);
548 break;
549 case ATA_PROT_NODATA:
550 pdc20621_nodata_prep(qc);
551 break;
552 default:
553 break;
554 }
555}
556
557static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
558 unsigned int seq,
559 u32 pkt_ofs)
560{
561 struct ata_port *ap = qc->ap;
562 struct ata_host_set *host_set = ap->host_set;
563 void *mmio = host_set->mmio_base;
564
565 /* hard-code chip #0 */
566 mmio += PDC_CHIP0_OFS;
567
568 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
569 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
570
571 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
572 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
573}
574
575static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
576 unsigned int seq,
577 u32 pkt_ofs)
578{
579 struct ata_port *ap = qc->ap;
580 struct pdc_host_priv *pp = ap->host_set->private_data;
581 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
582
583 if (!pp->doing_hdma) {
584 __pdc20621_push_hdma(qc, seq, pkt_ofs);
585 pp->doing_hdma = 1;
586 return;
587 }
588
589 pp->hdma[idx].qc = qc;
590 pp->hdma[idx].seq = seq;
591 pp->hdma[idx].pkt_ofs = pkt_ofs;
592 pp->hdma_prod++;
593}
594
595static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
596{
597 struct ata_port *ap = qc->ap;
598 struct pdc_host_priv *pp = ap->host_set->private_data;
599 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
600
601 /* if nothing on queue, we're done */
602 if (pp->hdma_prod == pp->hdma_cons) {
603 pp->doing_hdma = 0;
604 return;
605 }
606
607 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
608 pp->hdma[idx].pkt_ofs);
609 pp->hdma_cons++;
610}
611
612#ifdef ATA_VERBOSE_DEBUG
613static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
614{
615 struct ata_port *ap = qc->ap;
616 unsigned int port_no = ap->port_no;
617 struct pdc_host_priv *hpriv = ap->host_set->private_data;
618 void *dimm_mmio = hpriv->dimm_mmio;
619
620 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
621 dimm_mmio += PDC_DIMM_HOST_PKT;
622
623 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
624 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
625 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
626 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
627}
628#else
629static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
630#endif /* ATA_VERBOSE_DEBUG */
631
632static void pdc20621_packet_start(struct ata_queued_cmd *qc)
633{
634 struct ata_port *ap = qc->ap;
635 struct ata_host_set *host_set = ap->host_set;
636 unsigned int port_no = ap->port_no;
637 void *mmio = host_set->mmio_base;
638 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
639 u8 seq = (u8) (port_no + 1);
640 unsigned int port_ofs;
641
642 /* hard-code chip #0 */
643 mmio += PDC_CHIP0_OFS;
644
645 VPRINTK("ata%u: ENTER\n", ap->id);
646
647 wmb(); /* flush PRD, pkt writes */
648
649 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
650
651 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
652 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
653 seq += 4;
654
655 pdc20621_dump_hdma(qc);
656 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
657 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
658 port_ofs + PDC_DIMM_HOST_PKT,
659 port_ofs + PDC_DIMM_HOST_PKT,
660 seq);
661 } else {
662 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
663 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
664
665 writel(port_ofs + PDC_DIMM_ATA_PKT,
666 (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
667 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
668 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
669 port_ofs + PDC_DIMM_ATA_PKT,
670 port_ofs + PDC_DIMM_ATA_PKT,
671 seq);
672 }
673}
674
675static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
676{
677 switch (qc->tf.protocol) {
678 case ATA_PROT_DMA:
679 case ATA_PROT_NODATA:
680 pdc20621_packet_start(qc);
681 return 0;
682
683 case ATA_PROT_ATAPI_DMA:
684 BUG();
685 break;
686
687 default:
688 break;
689 }
690
691 return ata_qc_issue_prot(qc);
692}
693
694static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
695 struct ata_queued_cmd *qc,
696 unsigned int doing_hdma,
697 void *mmio)
698{
699 unsigned int port_no = ap->port_no;
700 unsigned int port_ofs =
701 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
702 u8 status;
703 unsigned int handled = 0;
704
705 VPRINTK("ENTER\n");
706
707 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
708 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
709
710 /* step two - DMA from DIMM to host */
711 if (doing_hdma) {
712 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
713 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
714 /* get drive status; clear intr; complete txn */
715 ata_qc_complete(qc, ata_wait_idle(ap));
716 pdc20621_pop_hdma(qc);
717 }
718
719 /* step one - exec ATA command */
720 else {
721 u8 seq = (u8) (port_no + 1 + 4);
722 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
723 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
724
725 /* submit hdma pkt */
726 pdc20621_dump_hdma(qc);
727 pdc20621_push_hdma(qc, seq,
728 port_ofs + PDC_DIMM_HOST_PKT);
729 }
730 handled = 1;
731
732 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
733
734 /* step one - DMA from host to DIMM */
735 if (doing_hdma) {
736 u8 seq = (u8) (port_no + 1);
737 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
738 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
739
740 /* submit ata pkt */
741 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
742 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
743 writel(port_ofs + PDC_DIMM_ATA_PKT,
744 (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
745 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
746 }
747
748 /* step two - execute ATA command */
749 else {
750 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
751 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
752 /* get drive status; clear intr; complete txn */
753 ata_qc_complete(qc, ata_wait_idle(ap));
754 pdc20621_pop_hdma(qc);
755 }
756 handled = 1;
757
758 /* command completion, but no data xfer */
759 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
760
761 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
762 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
763 ata_qc_complete(qc, status);
764 handled = 1;
765
766 } else {
767 ap->stats.idle_irq++;
768 }
769
770 return handled;
771}
772
773static void pdc20621_irq_clear(struct ata_port *ap)
774{
775 struct ata_host_set *host_set = ap->host_set;
776 void *mmio = host_set->mmio_base;
777
778 mmio += PDC_CHIP0_OFS;
779
780 readl(mmio + PDC_20621_SEQMASK);
781}
782
783static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
784{
785 struct ata_host_set *host_set = dev_instance;
786 struct ata_port *ap;
787 u32 mask = 0;
788 unsigned int i, tmp, port_no;
789 unsigned int handled = 0;
790 void *mmio_base;
791
792 VPRINTK("ENTER\n");
793
794 if (!host_set || !host_set->mmio_base) {
795 VPRINTK("QUICK EXIT\n");
796 return IRQ_NONE;
797 }
798
799 mmio_base = host_set->mmio_base;
800
801 /* reading should also clear interrupts */
802 mmio_base += PDC_CHIP0_OFS;
803 mask = readl(mmio_base + PDC_20621_SEQMASK);
804 VPRINTK("mask == 0x%x\n", mask);
805
806 if (mask == 0xffffffff) {
807 VPRINTK("QUICK EXIT 2\n");
808 return IRQ_NONE;
809 }
810 mask &= 0xffff; /* only 16 tags possible */
811 if (!mask) {
812 VPRINTK("QUICK EXIT 3\n");
813 return IRQ_NONE;
814 }
815
816 spin_lock(&host_set->lock);
817
818 for (i = 1; i < 9; i++) {
819 port_no = i - 1;
820 if (port_no > 3)
821 port_no -= 4;
822 if (port_no >= host_set->n_ports)
823 ap = NULL;
824 else
825 ap = host_set->ports[port_no];
826 tmp = mask & (1 << i);
827 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
c1389503
TH		 828 if (tmp && ap &&
829 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 830 struct ata_queued_cmd *qc;
831
832 qc = ata_qc_from_tag(ap, ap->active_tag);
833 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
834 handled += pdc20621_host_intr(ap, qc, (i > 4),
835 mmio_base);
836 }
837 }
838
839 spin_unlock(&host_set->lock);
840
841 VPRINTK("mask == 0x%x\n", mask);
842
843 VPRINTK("EXIT\n");
844
845 return IRQ_RETVAL(handled);
846}
847
848static void pdc_eng_timeout(struct ata_port *ap)
849{
850 u8 drv_stat;
851 struct ata_queued_cmd *qc;
852
853 DPRINTK("ENTER\n");
854
855 qc = ata_qc_from_tag(ap, ap->active_tag);
856 if (!qc) {
857 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
858 ap->id);
859 goto out;
860 }
861
862 /* hack alert! We cannot use the supplied completion
863 * function from inside the ->eh_strategy_handler() thread.
864 * libata is the only user of ->eh_strategy_handler() in
865 * any kernel, so the default scsi_done() assumes it is
866 * not being called from the SCSI EH.
867 */
868 qc->scsidone = scsi_finish_command;
869
870 switch (qc->tf.protocol) {
871 case ATA_PROT_DMA:
872 case ATA_PROT_NODATA:
873 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
874 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
875 break;
876
877 default:
878 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
879
880 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
881 ap->id, qc->tf.command, drv_stat);
882
883 ata_qc_complete(qc, drv_stat);
884 break;
885 }
886
887out:
888 DPRINTK("EXIT\n");
889}
890
891static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
892{
893 WARN_ON (tf->protocol == ATA_PROT_DMA ||
894 tf->protocol == ATA_PROT_NODATA);
895 ata_tf_load(ap, tf);
896}
897
898
899static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
900{
901 WARN_ON (tf->protocol == ATA_PROT_DMA ||
902 tf->protocol == ATA_PROT_NODATA);
903 ata_exec_command(ap, tf);
904}
905
906
907static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
908{
909 port->cmd_addr = base;
910 port->data_addr = base;
911 port->feature_addr =
912 port->error_addr = base + 0x4;
913 port->nsect_addr = base + 0x8;
914 port->lbal_addr = base + 0xc;
915 port->lbam_addr = base + 0x10;
916 port->lbah_addr = base + 0x14;
917 port->device_addr = base + 0x18;
918 port->command_addr =
919 port->status_addr = base + 0x1c;
920 port->altstatus_addr =
921 port->ctl_addr = base + 0x38;
922}
923
924
925#ifdef ATA_VERBOSE_DEBUG
8a60a071 926static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
1da177e4
LT		 927 u32 offset, u32 size)
928{
929 u32 window_size;
930 u16 idx;
931 u8 page_mask;
932 long dist;
933 void *mmio = pe->mmio_base;
934 struct pdc_host_priv *hpriv = pe->private_data;
935 void *dimm_mmio = hpriv->dimm_mmio;
936
937 /* hard-code chip #0 */
938 mmio += PDC_CHIP0_OFS;
939
8a60a071
JG		 940 page_mask = 0x00;
941 window_size = 0x2000 * 4; /* 32K byte uchar size */
942 idx = (u16) (offset / window_size);
1da177e4
LT		 943
944 writel(0x01, mmio + PDC_GENERAL_CTLR);
945 readl(mmio + PDC_GENERAL_CTLR);
946 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
947 readl(mmio + PDC_DIMM_WINDOW_CTLR);
948
949 offset -= (idx * window_size);
950 idx++;
8a60a071 951 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
1da177e4 952 (long) (window_size - offset);
8a60a071 953 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
1da177e4
LT		 954 dist);
955
8a60a071 956 psource += dist;
1da177e4
LT		 957 size -= dist;
958 for (; (long) size >= (long) window_size ;) {
959 writel(0x01, mmio + PDC_GENERAL_CTLR);
960 readl(mmio + PDC_GENERAL_CTLR);
961 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
962 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 963 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1da177e4
LT		 964 window_size / 4);
965 psource += window_size;
966 size -= window_size;
967 idx ++;
968 }
969
970 if (size) {
971 writel(0x01, mmio + PDC_GENERAL_CTLR);
972 readl(mmio + PDC_GENERAL_CTLR);
973 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
974 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 975 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1da177e4
LT		 976 size / 4);
977 }
978}
979#endif
980
981
8a60a071 982static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
1da177e4
LT		 983 u32 offset, u32 size)
984{
985 u32 window_size;
986 u16 idx;
987 u8 page_mask;
988 long dist;
989 void *mmio = pe->mmio_base;
990 struct pdc_host_priv *hpriv = pe->private_data;
991 void *dimm_mmio = hpriv->dimm_mmio;
992
8a60a071 993 /* hard-code chip #0 */
1da177e4
LT		 994 mmio += PDC_CHIP0_OFS;
995
8a60a071
JG		 996 page_mask = 0x00;
997 window_size = 0x2000 * 4; /* 32K byte uchar size */
1da177e4
LT		 998 idx = (u16) (offset / window_size);
999
1000 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1001 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 1002 offset -= (idx * window_size);
1da177e4
LT		 1003 idx++;
1004 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1005 (long) (window_size - offset);
1006 memcpy_toio((char *) (dimm_mmio + offset / 4), (char *) psource, dist);
1007 writel(0x01, mmio + PDC_GENERAL_CTLR);
1008 readl(mmio + PDC_GENERAL_CTLR);
1009
8a60a071 1010 psource += dist;
1da177e4
LT		 1011 size -= dist;
1012 for (; (long) size >= (long) window_size ;) {
1013 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1014 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 1015 memcpy_toio((char *) (dimm_mmio), (char *) psource,
1da177e4
LT		 1016 window_size / 4);
1017 writel(0x01, mmio + PDC_GENERAL_CTLR);
1018 readl(mmio + PDC_GENERAL_CTLR);
1019 psource += window_size;
1020 size -= window_size;
1021 idx ++;
1022 }
8a60a071 1023
1da177e4
LT		 1024 if (size) {
1025 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1026 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1027 memcpy_toio((char *) (dimm_mmio), (char *) psource, size / 4);
1028 writel(0x01, mmio + PDC_GENERAL_CTLR);
1029 readl(mmio + PDC_GENERAL_CTLR);
1030 }
1031}
1032
1033
8a60a071 1034static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1da177e4
LT		 1035 u32 subaddr, u32 *pdata)
1036{
1037 void *mmio = pe->mmio_base;
1038 u32 i2creg = 0;
8a60a071 1039 u32 status;
1da177e4
LT		 1040 u32 count =0;
1041
1042 /* hard-code chip #0 */
1043 mmio += PDC_CHIP0_OFS;
1044
1045 i2creg |= device << 24;
1046 i2creg |= subaddr << 16;
1047
1048 /* Set the device and subaddress */
1049 writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1050 readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1051
1052 /* Write Control to perform read operation, mask int */
8a60a071 1053 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1da177e4
LT		 1054 mmio + PDC_I2C_CONTROL_OFFSET);
1055
1056 for (count = 0; count <= 1000; count ++) {
1057 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1058 if (status & PDC_I2C_COMPLETE) {
1059 status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1060 break;
1061 } else if (count == 1000)
1062 return 0;
1063 }
1064
1065 *pdata = (status >> 8) & 0x000000ff;
8a60a071 1066 return 1;
1da177e4
LT		 1067}
1068
1069
1070static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1071{
1072 u32 data=0 ;
8a60a071 1073 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4
LT		 1074 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1075 if (data == 100)
1076 return 100;
1077 } else
1078 return 0;
8a60a071 1079
1da177e4 1080 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
8a60a071 1081 if(data <= 0x75)
1da177e4
LT		 1082 return 133;
1083 } else
1084 return 0;
8a60a071 1085
1da177e4
LT		 1086 return 0;
1087}
1088
1089
1090static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1091{
1092 u32 spd0[50];
1093 u32 data = 0;
1094 int size, i;
8a60a071 1095 u8 bdimmsize;
1da177e4
LT		 1096 void *mmio = pe->mmio_base;
1097 static const struct {
1098 unsigned int reg;
1099 unsigned int ofs;
1100 } pdc_i2c_read_data [] = {
8a60a071 1101 { PDC_DIMM_SPD_TYPE, 11 },
1da177e4 1102 { PDC_DIMM_SPD_FRESH_RATE, 12 },
8a60a071 1103 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1da177e4
LT		 1104 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1105 { PDC_DIMM_SPD_ROW_NUM, 3 },
1106 { PDC_DIMM_SPD_BANK_NUM, 17 },
1107 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1108 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1109 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1110 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1111 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
8a60a071 1112 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1da177e4
LT		 1113 };
1114
1115 /* hard-code chip #0 */
1116 mmio += PDC_CHIP0_OFS;
1117
1118 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1119 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
8a60a071 1120 pdc_i2c_read_data[i].reg,
1da177e4 1121 &spd0[pdc_i2c_read_data[i].ofs]);
8a60a071 1122
1da177e4 1123 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
8a60a071 1124 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1da177e4 1125 ((((spd0[27] + 9) / 10) - 1) << 8) ;
8a60a071
JG		 1126 data |= (((((spd0[29] > spd0[28])
1127 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1da177e4 1128 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
8a60a071
JG		 1129
1130 if (spd0[18] & 0x08)
1da177e4
LT		 1131 data |= ((0x03) << 14);
1132 else if (spd0[18] & 0x04)
1133 data |= ((0x02) << 14);
1134 else if (spd0[18] & 0x01)
1135 data |= ((0x01) << 14);
1136 else
1137 data |= (0 << 14);
1138
8a60a071 1139 /*
1da177e4
LT		 1140 Calculate the size of bDIMMSize (power of 2) and
1141 merge the DIMM size by program start/end address.
1142 */
1143
1144 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1145 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1146 data |= (((size / 16) - 1) << 16);
1147 data |= (0 << 23);
1148 data |= 8;
8a60a071 1149 writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1da177e4 1150 readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
8a60a071 1151 return size;
1da177e4
LT		 1152}
1153
1154
1155static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1156{
1157 u32 data, spd0;
1158 int error, i;
1159 void *mmio = pe->mmio_base;
1160
1161 /* hard-code chip #0 */
1162 mmio += PDC_CHIP0_OFS;
1163
1164 /*
1165 Set To Default : DIMM Module Global Control Register (0x022259F1)
1166 DIMM Arbitration Disable (bit 20)
1167 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1168 Refresh Enable (bit 17)
1169 */
1170
8a60a071 1171 data = 0x022259F1;
1da177e4
LT		 1172 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1173 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1174
1175 /* Turn on for ECC */
8a60a071 1176 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4
LT		 1177 PDC_DIMM_SPD_TYPE, &spd0);
1178 if (spd0 == 0x02) {
1179 data |= (0x01 << 16);
1180 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1181 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1182 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1183 }
1184
1185 /* DIMM Initialization Select/Enable (bit 18/19) */
1186 data &= (~(1<<18));
1187 data |= (1<<19);
1188 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1189
8a60a071 1190 error = 1;
1da177e4
LT		 1191 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1192 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1193 if (!(data & (1<<19))) {
1194 error = 0;
8a60a071 1195 break;
1da177e4
LT		 1196 }
1197 msleep(i*100);
1198 }
1199 return error;
1200}
8a60a071 1201
1da177e4
LT		 1202
1203static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1204{
8a60a071 1205 int speed, size, length;
1da177e4
LT		 1206 u32 addr,spd0,pci_status;
1207 u32 tmp=0;
1208 u32 time_period=0;
1209 u32 tcount=0;
1210 u32 ticks=0;
1211 u32 clock=0;
1212 u32 fparam=0;
1213 void *mmio = pe->mmio_base;
1214
1215 /* hard-code chip #0 */
1216 mmio += PDC_CHIP0_OFS;
1217
1218 /* Initialize PLL based upon PCI Bus Frequency */
1219
1220 /* Initialize Time Period Register */
1221 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1222 time_period = readl(mmio + PDC_TIME_PERIOD);
1223 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1224
1225 /* Enable timer */
1226 writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1227 readl(mmio + PDC_TIME_CONTROL);
1228
1229 /* Wait 3 seconds */
1230 msleep(3000);
1231
8a60a071 1232 /*
1da177e4
LT		 1233 When timer is enabled, counter is decreased every internal
1234 clock cycle.
1235 */
1236
1237 tcount = readl(mmio + PDC_TIME_COUNTER);
1238 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1239
8a60a071 1240 /*
1da177e4
LT		 1241 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1242 register should be >= (0xffffffff - 3x10^8).
1243 */
1244 if(tcount >= PCI_X_TCOUNT) {
1245 ticks = (time_period - tcount);
1246 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
8a60a071 1247
1da177e4
LT		 1248 clock = (ticks / 300000);
1249 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
8a60a071 1250
1da177e4
LT		 1251 clock = (clock * 33);
1252 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1253
1254 /* PLL F Param (bit 22:16) */
1255 fparam = (1400000 / clock) - 2;
1256 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
8a60a071 1257
1da177e4
LT		 1258 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1259 pci_status = (0x8a001824 | (fparam << 16));
1260 } else
1261 pci_status = PCI_PLL_INIT;
1262
1263 /* Initialize PLL. */
1264 VPRINTK("pci_status: 0x%x\n", pci_status);
1265 writel(pci_status, mmio + PDC_CTL_STATUS);
1266 readl(mmio + PDC_CTL_STATUS);
1267
8a60a071 1268 /*
1da177e4
LT		 1269 Read SPD of DIMM by I2C interface,
1270 and program the DIMM Module Controller.
1271 */
1272 if (!(speed = pdc20621_detect_dimm(pe))) {
8a60a071 1273 printk(KERN_ERR "Detect Local DIMM Fail\n");
1da177e4
LT		 1274 return 1; /* DIMM error */
1275 }
1276 VPRINTK("Local DIMM Speed = %d\n", speed);
1277
8a60a071 1278 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1da177e4
LT		 1279 size = pdc20621_prog_dimm0(pe);
1280 VPRINTK("Local DIMM Size = %dMB\n",size);
1281
8a60a071 1282 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1da177e4
LT		 1283 if (pdc20621_prog_dimm_global(pe)) {
1284 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1285 return 1;
1286 }
1287
1288#ifdef ATA_VERBOSE_DEBUG
1289 {
1290 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1291 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1292 '1','.','1','0',
1293 '9','8','0','3','1','6','1','2',0,0};
1294 u8 test_parttern2[40] = {0};
1295
1296 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1297 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1298
1299 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1300 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
8a60a071 1301 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1da177e4 1302 test_parttern2[1], &(test_parttern2[2]));
8a60a071 1303 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1da177e4 1304 40);
8a60a071 1305 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1da177e4
LT		 1306 test_parttern2[1], &(test_parttern2[2]));
1307
1308 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1309 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
8a60a071 1310 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1da177e4
LT		 1311 test_parttern2[1], &(test_parttern2[2]));
1312 }
1313#endif
1314
1315 /* ECC initiliazation. */
1316
8a60a071 1317 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4
LT		 1318 PDC_DIMM_SPD_TYPE, &spd0);
1319 if (spd0 == 0x02) {
1320 VPRINTK("Start ECC initialization\n");
1321 addr = 0;
1322 length = size * 1024 * 1024;
1323 while (addr < length) {
8a60a071 1324 pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1da177e4
LT		 1325 sizeof(u32));
1326 addr += sizeof(u32);
1327 }
1328 VPRINTK("Finish ECC initialization\n");
1329 }
1330 return 0;
1331}
1332
1333
1334static void pdc_20621_init(struct ata_probe_ent *pe)
1335{
1336 u32 tmp;
1337 void *mmio = pe->mmio_base;
1338
1339 /* hard-code chip #0 */
1340 mmio += PDC_CHIP0_OFS;
1341
1342 /*
1343 * Select page 0x40 for our 32k DIMM window
1344 */
1345 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1346 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1347 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1348
1349 /*
1350 * Reset Host DMA
1351 */
1352 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1353 tmp |= PDC_RESET;
1354 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1355 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1356
1357 udelay(10);
1358
1359 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1360 tmp &= ~PDC_RESET;
1361 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1362 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1363}
1364
1365static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1366{
1367 static int printed_version;
1368 struct ata_probe_ent *probe_ent = NULL;
1369 unsigned long base;
1370 void *mmio_base, *dimm_mmio = NULL;
1371 struct pdc_host_priv *hpriv = NULL;
1372 unsigned int board_idx = (unsigned int) ent->driver_data;
1373 int pci_dev_busy = 0;
1374 int rc;
1375
1376 if (!printed_version++)
1377 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1378
1379 /*
1380 * If this driver happens to only be useful on Apple's K2, then
1381 * we should check that here as it has a normal Serverworks ID
1382 */
1383 rc = pci_enable_device(pdev);
1384 if (rc)
1385 return rc;
1386
1387 rc = pci_request_regions(pdev, DRV_NAME);
1388 if (rc) {
1389 pci_dev_busy = 1;
1390 goto err_out;
1391 }
1392
1393 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1394 if (rc)
1395 goto err_out_regions;
1396 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1397 if (rc)
1398 goto err_out_regions;
1399
1400 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1401 if (probe_ent == NULL) {
1402 rc = -ENOMEM;
1403 goto err_out_regions;
1404 }
1405
1406 memset(probe_ent, 0, sizeof(*probe_ent));
1407 probe_ent->dev = pci_dev_to_dev(pdev);
1408 INIT_LIST_HEAD(&probe_ent->node);
1409
1410 mmio_base = ioremap(pci_resource_start(pdev, 3),
1411 pci_resource_len(pdev, 3));
1412 if (mmio_base == NULL) {
1413 rc = -ENOMEM;
1414 goto err_out_free_ent;
1415 }
1416 base = (unsigned long) mmio_base;
1417
1418 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1419 if (!hpriv) {
1420 rc = -ENOMEM;
1421 goto err_out_iounmap;
1422 }
1423 memset(hpriv, 0, sizeof(*hpriv));
1424
1425 dimm_mmio = ioremap(pci_resource_start(pdev, 4),
1426 pci_resource_len(pdev, 4));
1427 if (!dimm_mmio) {
1428 kfree(hpriv);
1429 rc = -ENOMEM;
1430 goto err_out_iounmap;
1431 }
1432
1433 hpriv->dimm_mmio = dimm_mmio;
1434
1435 probe_ent->sht = pdc_port_info[board_idx].sht;
1436 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
1437 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1438 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1439 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1440 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1441
1442 probe_ent->irq = pdev->irq;
1443 probe_ent->irq_flags = SA_SHIRQ;
1444 probe_ent->mmio_base = mmio_base;
1445
1446 probe_ent->private_data = hpriv;
1447 base += PDC_CHIP0_OFS;
1448
1449 probe_ent->n_ports = 4;
1450 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1451 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1452 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1453 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1454
1455 pci_set_master(pdev);
1456
1457 /* initialize adapter */
1458 /* initialize local dimm */
1459 if (pdc20621_dimm_init(probe_ent)) {
1460 rc = -ENOMEM;
1461 goto err_out_iounmap_dimm;
1462 }
1463 pdc_20621_init(probe_ent);
1464
1465 /* FIXME: check ata_device_add return value */
1466 ata_device_add(probe_ent);
1467 kfree(probe_ent);
1468
1469 return 0;
1470
1471err_out_iounmap_dimm: /* only get to this label if 20621 */
1472 kfree(hpriv);
1473 iounmap(dimm_mmio);
1474err_out_iounmap:
1475 iounmap(mmio_base);
1476err_out_free_ent:
1477 kfree(probe_ent);
1478err_out_regions:
1479 pci_release_regions(pdev);
1480err_out:
1481 if (!pci_dev_busy)
1482 pci_disable_device(pdev);
1483 return rc;
1484}
1485
1486
1487static int __init pdc_sata_init(void)
1488{
1489 return pci_module_init(&pdc_sata_pci_driver);
1490}
1491
1492
1493static void __exit pdc_sata_exit(void)
1494{
1495 pci_unregister_driver(&pdc_sata_pci_driver);
1496}
1497
1498
1499MODULE_AUTHOR("Jeff Garzik");
1500MODULE_DESCRIPTION("Promise SATA low-level driver");
1501MODULE_LICENSE("GPL");
1502MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1503MODULE_VERSION(DRV_VERSION);
1504
1505module_init(pdc_sata_init);
1506module_exit(pdc_sata_exit);
kernel source for telekom puls (alcatel/mediatek)