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[PATCH] enum safety (sata_qstor)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / sata_sx4.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
af36d7f0
JG		 10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
1da177e4
LT		 30 *
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/blkdev.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/sched.h>
41#include "scsi.h"
42#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44#include <asm/io.h>
45#include "sata_promise.h"
46
47#define DRV_NAME "sata_sx4"
48#define DRV_VERSION "0.7"
49
50
51enum {
52 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
53
54 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
55 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
56 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
57 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
58
59 PDC_20621_SEQCTL = 0x400,
60 PDC_20621_SEQMASK = 0x480,
61 PDC_20621_GENERAL_CTL = 0x484,
62 PDC_20621_PAGE_SIZE = (32 * 1024),
63
64 /* chosen, not constant, values; we design our own DIMM mem map */
65 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
66 PDC_20621_DIMM_BASE = 0x00200000,
67 PDC_20621_DIMM_DATA = (64 * 1024),
68 PDC_DIMM_DATA_STEP = (256 * 1024),
69 PDC_DIMM_WINDOW_STEP = (8 * 1024),
70 PDC_DIMM_HOST_PRD = (6 * 1024),
71 PDC_DIMM_HOST_PKT = (128 * 0),
72 PDC_DIMM_HPKT_PRD = (128 * 1),
73 PDC_DIMM_ATA_PKT = (128 * 2),
74 PDC_DIMM_APKT_PRD = (128 * 3),
75 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
76 PDC_PAGE_WINDOW = 0x40,
77 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
78 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
79 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
80
81 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
82
83 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
84 (1<<23),
85
86 board_20621 = 0, /* FastTrak S150 SX4 */
87
88 PDC_RESET = (1 << 11), /* HDMA reset */
89
90 PDC_MAX_HDMA = 32,
91 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
92
93 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
94 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
95 PDC_MAX_DIMM_MODULE = 0x02,
96 PDC_I2C_CONTROL_OFFSET = 0x48,
97 PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
98 PDC_DIMM0_CONTROL_OFFSET = 0x80,
99 PDC_DIMM1_CONTROL_OFFSET = 0x84,
100 PDC_SDRAM_CONTROL_OFFSET = 0x88,
101 PDC_I2C_WRITE = 0x00000000,
8a60a071 102 PDC_I2C_READ = 0x00000040,
1da177e4
LT		 103 PDC_I2C_START = 0x00000080,
104 PDC_I2C_MASK_INT = 0x00000020,
105 PDC_I2C_COMPLETE = 0x00010000,
106 PDC_I2C_NO_ACK = 0x00100000,
107 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
108 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
109 PDC_DIMM_SPD_ROW_NUM = 3,
110 PDC_DIMM_SPD_COLUMN_NUM = 4,
111 PDC_DIMM_SPD_MODULE_ROW = 5,
112 PDC_DIMM_SPD_TYPE = 11,
8a60a071
JG		 113 PDC_DIMM_SPD_FRESH_RATE = 12,
114 PDC_DIMM_SPD_BANK_NUM = 17,
1da177e4 115 PDC_DIMM_SPD_CAS_LATENCY = 18,
8a60a071 116 PDC_DIMM_SPD_ATTRIBUTE = 21,
1da177e4 117 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
8a60a071 118 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
1da177e4
LT		 119 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
120 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
121 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
8a60a071 122 PDC_CTL_STATUS = 0x08,
1da177e4
LT		 123 PDC_DIMM_WINDOW_CTLR = 0x0C,
124 PDC_TIME_CONTROL = 0x3C,
125 PDC_TIME_PERIOD = 0x40,
126 PDC_TIME_COUNTER = 0x44,
127 PDC_GENERAL_CTLR = 0x484,
128 PCI_PLL_INIT = 0x8A531824,
129 PCI_X_TCOUNT = 0xEE1E5CFF
130};
131
132
133struct pdc_port_priv {
134 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
135 u8 *pkt;
136 dma_addr_t pkt_dma;
137};
138
139struct pdc_host_priv {
140 void *dimm_mmio;
141
142 unsigned int doing_hdma;
143 unsigned int hdma_prod;
144 unsigned int hdma_cons;
145 struct {
146 struct ata_queued_cmd *qc;
147 unsigned int seq;
148 unsigned long pkt_ofs;
149 } hdma[32];
150};
151
152
153static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
154static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
155static void pdc_eng_timeout(struct ata_port *ap);
156static void pdc_20621_phy_reset (struct ata_port *ap);
157static int pdc_port_start(struct ata_port *ap);
158static void pdc_port_stop(struct ata_port *ap);
159static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
160static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
161static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
162static void pdc20621_host_stop(struct ata_host_set *host_set);
163static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
164static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
8a60a071 165static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
1da177e4
LT		 166 u32 device, u32 subaddr, u32 *pdata);
167static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
168static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
169#ifdef ATA_VERBOSE_DEBUG
8a60a071 170static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
1da177e4
LT		 171 void *psource, u32 offset, u32 size);
172#endif
8a60a071 173static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
1da177e4
LT		 174 void *psource, u32 offset, u32 size);
175static void pdc20621_irq_clear(struct ata_port *ap);
176static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
177
178
179static Scsi_Host_Template pdc_sata_sht = {
180 .module = THIS_MODULE,
181 .name = DRV_NAME,
182 .ioctl = ata_scsi_ioctl,
183 .queuecommand = ata_scsi_queuecmd,
184 .eh_strategy_handler = ata_scsi_error,
185 .can_queue = ATA_DEF_QUEUE,
186 .this_id = ATA_SHT_THIS_ID,
187 .sg_tablesize = LIBATA_MAX_PRD,
188 .max_sectors = ATA_MAX_SECTORS,
189 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
190 .emulated = ATA_SHT_EMULATED,
191 .use_clustering = ATA_SHT_USE_CLUSTERING,
192 .proc_name = DRV_NAME,
193 .dma_boundary = ATA_DMA_BOUNDARY,
194 .slave_configure = ata_scsi_slave_config,
195 .bios_param = ata_std_bios_param,
196 .ordered_flush = 1,
197};
198
199static struct ata_port_operations pdc_20621_ops = {
200 .port_disable = ata_port_disable,
201 .tf_load = pdc_tf_load_mmio,
202 .tf_read = ata_tf_read,
203 .check_status = ata_check_status,
204 .exec_command = pdc_exec_command_mmio,
205 .dev_select = ata_std_dev_select,
206 .phy_reset = pdc_20621_phy_reset,
207 .qc_prep = pdc20621_qc_prep,
208 .qc_issue = pdc20621_qc_issue_prot,
209 .eng_timeout = pdc_eng_timeout,
210 .irq_handler = pdc20621_interrupt,
211 .irq_clear = pdc20621_irq_clear,
212 .port_start = pdc_port_start,
213 .port_stop = pdc_port_stop,
214 .host_stop = pdc20621_host_stop,
215};
216
217static struct ata_port_info pdc_port_info[] = {
218 /* board_20621 */
219 {
220 .sht = &pdc_sata_sht,
221 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
222 ATA_FLAG_SRST | ATA_FLAG_MMIO,
223 .pio_mask = 0x1f, /* pio0-4 */
224 .mwdma_mask = 0x07, /* mwdma0-2 */
225 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
226 .port_ops = &pdc_20621_ops,
227 },
228
229};
230
231static struct pci_device_id pdc_sata_pci_tbl[] = {
232 { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
233 board_20621 },
234 { } /* terminate list */
235};
236
237
238static struct pci_driver pdc_sata_pci_driver = {
239 .name = DRV_NAME,
240 .id_table = pdc_sata_pci_tbl,
241 .probe = pdc_sata_init_one,
242 .remove = ata_pci_remove_one,
243};
244
245
246static void pdc20621_host_stop(struct ata_host_set *host_set)
247{
374b1873 248 struct pci_dev *pdev = to_pci_dev(host_set->dev);
1da177e4
LT		 249 struct pdc_host_priv *hpriv = host_set->private_data;
250 void *dimm_mmio = hpriv->dimm_mmio;
251
374b1873 252 pci_iounmap(pdev, dimm_mmio);
1da177e4 253 kfree(hpriv);
aa8f0dc6 254
374b1873 255 pci_iounmap(pdev, host_set->mmio_base);
1da177e4
LT		 256}
257
258static int pdc_port_start(struct ata_port *ap)
259{
260 struct device *dev = ap->host_set->dev;
261 struct pdc_port_priv *pp;
262 int rc;
263
264 rc = ata_port_start(ap);
265 if (rc)
266 return rc;
267
268 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
269 if (!pp) {
270 rc = -ENOMEM;
271 goto err_out;
272 }
273 memset(pp, 0, sizeof(*pp));
274
275 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
276 if (!pp->pkt) {
277 rc = -ENOMEM;
278 goto err_out_kfree;
279 }
280
281 ap->private_data = pp;
282
283 return 0;
284
285err_out_kfree:
286 kfree(pp);
287err_out:
288 ata_port_stop(ap);
289 return rc;
290}
291
292
293static void pdc_port_stop(struct ata_port *ap)
294{
295 struct device *dev = ap->host_set->dev;
296 struct pdc_port_priv *pp = ap->private_data;
297
298 ap->private_data = NULL;
299 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
300 kfree(pp);
301 ata_port_stop(ap);
302}
303
304
305static void pdc_20621_phy_reset (struct ata_port *ap)
306{
307 VPRINTK("ENTER\n");
308 ap->cbl = ATA_CBL_SATA;
309 ata_port_probe(ap);
310 ata_bus_reset(ap);
311}
312
313static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
314 unsigned int portno,
315 unsigned int total_len)
316{
317 u32 addr;
318 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
319 u32 *buf32 = (u32 *) buf;
320
321 /* output ATA packet S/G table */
322 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
323 (PDC_DIMM_DATA_STEP * portno);
324 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
325 buf32[dw] = cpu_to_le32(addr);
326 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
327
328 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
329 PDC_20621_DIMM_BASE +
330 (PDC_DIMM_WINDOW_STEP * portno) +
331 PDC_DIMM_APKT_PRD,
332 buf32[dw], buf32[dw + 1]);
333}
334
335static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
336 unsigned int portno,
337 unsigned int total_len)
338{
339 u32 addr;
340 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
341 u32 *buf32 = (u32 *) buf;
342
343 /* output Host DMA packet S/G table */
344 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
345 (PDC_DIMM_DATA_STEP * portno);
346
347 buf32[dw] = cpu_to_le32(addr);
348 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
349
350 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
351 PDC_20621_DIMM_BASE +
352 (PDC_DIMM_WINDOW_STEP * portno) +
353 PDC_DIMM_HPKT_PRD,
354 buf32[dw], buf32[dw + 1]);
355}
356
357static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
358 unsigned int devno, u8 *buf,
359 unsigned int portno)
360{
361 unsigned int i, dw;
362 u32 *buf32 = (u32 *) buf;
363 u8 dev_reg;
364
365 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
366 (PDC_DIMM_WINDOW_STEP * portno) +
367 PDC_DIMM_APKT_PRD;
368 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
369
370 i = PDC_DIMM_ATA_PKT;
371
372 /*
373 * Set up ATA packet
374 */
375 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
376 buf[i++] = PDC_PKT_READ;
377 else if (tf->protocol == ATA_PROT_NODATA)
378 buf[i++] = PDC_PKT_NODATA;
379 else
380 buf[i++] = 0;
381 buf[i++] = 0; /* reserved */
382 buf[i++] = portno + 1; /* seq. id */
383 buf[i++] = 0xff; /* delay seq. id */
384
385 /* dimm dma S/G, and next-pkt */
386 dw = i >> 2;
387 if (tf->protocol == ATA_PROT_NODATA)
388 buf32[dw] = 0;
389 else
390 buf32[dw] = cpu_to_le32(dimm_sg);
391 buf32[dw + 1] = 0;
392 i += 8;
393
394 if (devno == 0)
395 dev_reg = ATA_DEVICE_OBS;
396 else
397 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
398
399 /* select device */
400 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
401 buf[i++] = dev_reg;
402
403 /* device control register */
404 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
405 buf[i++] = tf->ctl;
406
407 return i;
408}
409
410static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
411 unsigned int portno)
412{
413 unsigned int dw;
414 u32 tmp, *buf32 = (u32 *) buf;
415
416 unsigned int host_sg = PDC_20621_DIMM_BASE +
417 (PDC_DIMM_WINDOW_STEP * portno) +
418 PDC_DIMM_HOST_PRD;
419 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
420 (PDC_DIMM_WINDOW_STEP * portno) +
421 PDC_DIMM_HPKT_PRD;
422 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
423 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
424
425 dw = PDC_DIMM_HOST_PKT >> 2;
426
427 /*
428 * Set up Host DMA packet
429 */
430 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
431 tmp = PDC_PKT_READ;
432 else
433 tmp = 0;
434 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
435 tmp |= (0xff << 24); /* delay seq. id */
436 buf32[dw + 0] = cpu_to_le32(tmp);
437 buf32[dw + 1] = cpu_to_le32(host_sg);
438 buf32[dw + 2] = cpu_to_le32(dimm_sg);
439 buf32[dw + 3] = 0;
440
441 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
442 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
443 PDC_DIMM_HOST_PKT,
444 buf32[dw + 0],
445 buf32[dw + 1],
446 buf32[dw + 2],
447 buf32[dw + 3]);
448}
449
450static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
451{
452 struct scatterlist *sg = qc->sg;
453 struct ata_port *ap = qc->ap;
454 struct pdc_port_priv *pp = ap->private_data;
ea6ba10b 455 void __iomem *mmio = ap->host_set->mmio_base;
1da177e4 456 struct pdc_host_priv *hpriv = ap->host_set->private_data;
ea6ba10b 457 void __iomem *dimm_mmio = hpriv->dimm_mmio;
1da177e4
LT		 458 unsigned int portno = ap->port_no;
459 unsigned int i, last, idx, total_len = 0, sgt_len;
460 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
461
462 assert(qc->flags & ATA_QCFLAG_DMAMAP);
463
464 VPRINTK("ata%u: ENTER\n", ap->id);
465
466 /* hard-code chip #0 */
467 mmio += PDC_CHIP0_OFS;
468
469 /*
470 * Build S/G table
471 */
472 last = qc->n_elem;
473 idx = 0;
474 for (i = 0; i < last; i++) {
475 buf[idx++] = cpu_to_le32(sg_dma_address(&sg[i]));
476 buf[idx++] = cpu_to_le32(sg_dma_len(&sg[i]));
fae00984 477 total_len += sg_dma_len(&sg[i]);
1da177e4
LT		 478 }
479 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
480 sgt_len = idx * 4;
481
482 /*
483 * Build ATA, host DMA packets
484 */
485 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
486 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
487
488 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
489 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
490
491 if (qc->tf.flags & ATA_TFLAG_LBA48)
492 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
493 else
494 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
495
496 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
497
498 /* copy three S/G tables and two packets to DIMM MMIO window */
499 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
500 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
501 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
502 PDC_DIMM_HOST_PRD,
503 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
504
505 /* force host FIFO dump */
506 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
507
508 readl(dimm_mmio); /* MMIO PCI posting flush */
509
510 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
511}
512
513static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
514{
515 struct ata_port *ap = qc->ap;
516 struct pdc_port_priv *pp = ap->private_data;
ea6ba10b 517 void __iomem *mmio = ap->host_set->mmio_base;
1da177e4 518 struct pdc_host_priv *hpriv = ap->host_set->private_data;
ea6ba10b 519 void __iomem *dimm_mmio = hpriv->dimm_mmio;
1da177e4
LT		 520 unsigned int portno = ap->port_no;
521 unsigned int i;
522
523 VPRINTK("ata%u: ENTER\n", ap->id);
524
525 /* hard-code chip #0 */
526 mmio += PDC_CHIP0_OFS;
527
528 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
529
530 if (qc->tf.flags & ATA_TFLAG_LBA48)
531 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
532 else
533 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
534
535 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
536
537 /* copy three S/G tables and two packets to DIMM MMIO window */
538 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
539 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
540
541 /* force host FIFO dump */
542 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
543
544 readl(dimm_mmio); /* MMIO PCI posting flush */
545
546 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
547}
548
549static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
550{
551 switch (qc->tf.protocol) {
552 case ATA_PROT_DMA:
553 pdc20621_dma_prep(qc);
554 break;
555 case ATA_PROT_NODATA:
556 pdc20621_nodata_prep(qc);
557 break;
558 default:
559 break;
560 }
561}
562
563static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
564 unsigned int seq,
565 u32 pkt_ofs)
566{
567 struct ata_port *ap = qc->ap;
568 struct ata_host_set *host_set = ap->host_set;
ea6ba10b 569 void __iomem *mmio = host_set->mmio_base;
1da177e4
LT		 570
571 /* hard-code chip #0 */
572 mmio += PDC_CHIP0_OFS;
573
574 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
575 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
576
577 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
578 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
579}
580
581static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
582 unsigned int seq,
583 u32 pkt_ofs)
584{
585 struct ata_port *ap = qc->ap;
586 struct pdc_host_priv *pp = ap->host_set->private_data;
587 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
588
589 if (!pp->doing_hdma) {
590 __pdc20621_push_hdma(qc, seq, pkt_ofs);
591 pp->doing_hdma = 1;
592 return;
593 }
594
595 pp->hdma[idx].qc = qc;
596 pp->hdma[idx].seq = seq;
597 pp->hdma[idx].pkt_ofs = pkt_ofs;
598 pp->hdma_prod++;
599}
600
601static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
602{
603 struct ata_port *ap = qc->ap;
604 struct pdc_host_priv *pp = ap->host_set->private_data;
605 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
606
607 /* if nothing on queue, we're done */
608 if (pp->hdma_prod == pp->hdma_cons) {
609 pp->doing_hdma = 0;
610 return;
611 }
612
613 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
614 pp->hdma[idx].pkt_ofs);
615 pp->hdma_cons++;
616}
617
618#ifdef ATA_VERBOSE_DEBUG
619static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
620{
621 struct ata_port *ap = qc->ap;
622 unsigned int port_no = ap->port_no;
623 struct pdc_host_priv *hpriv = ap->host_set->private_data;
624 void *dimm_mmio = hpriv->dimm_mmio;
625
626 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
627 dimm_mmio += PDC_DIMM_HOST_PKT;
628
629 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
630 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
631 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
632 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
633}
634#else
635static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
636#endif /* ATA_VERBOSE_DEBUG */
637
638static void pdc20621_packet_start(struct ata_queued_cmd *qc)
639{
640 struct ata_port *ap = qc->ap;
641 struct ata_host_set *host_set = ap->host_set;
642 unsigned int port_no = ap->port_no;
ea6ba10b 643 void __iomem *mmio = host_set->mmio_base;
1da177e4
LT		 644 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
645 u8 seq = (u8) (port_no + 1);
646 unsigned int port_ofs;
647
648 /* hard-code chip #0 */
649 mmio += PDC_CHIP0_OFS;
650
651 VPRINTK("ata%u: ENTER\n", ap->id);
652
653 wmb(); /* flush PRD, pkt writes */
654
655 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
656
657 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
658 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
659 seq += 4;
660
661 pdc20621_dump_hdma(qc);
662 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
663 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
664 port_ofs + PDC_DIMM_HOST_PKT,
665 port_ofs + PDC_DIMM_HOST_PKT,
666 seq);
667 } else {
668 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
669 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
670
671 writel(port_ofs + PDC_DIMM_ATA_PKT,
672 (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
673 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
674 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
675 port_ofs + PDC_DIMM_ATA_PKT,
676 port_ofs + PDC_DIMM_ATA_PKT,
677 seq);
678 }
679}
680
681static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
682{
683 switch (qc->tf.protocol) {
684 case ATA_PROT_DMA:
685 case ATA_PROT_NODATA:
686 pdc20621_packet_start(qc);
687 return 0;
688
689 case ATA_PROT_ATAPI_DMA:
690 BUG();
691 break;
692
693 default:
694 break;
695 }
696
697 return ata_qc_issue_prot(qc);
698}
699
700static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
701 struct ata_queued_cmd *qc,
702 unsigned int doing_hdma,
ea6ba10b 703 void __iomem *mmio)
1da177e4
LT		 704{
705 unsigned int port_no = ap->port_no;
706 unsigned int port_ofs =
707 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
708 u8 status;
709 unsigned int handled = 0;
710
711 VPRINTK("ENTER\n");
712
713 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
714 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
715
716 /* step two - DMA from DIMM to host */
717 if (doing_hdma) {
718 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
719 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
720 /* get drive status; clear intr; complete txn */
721 ata_qc_complete(qc, ata_wait_idle(ap));
722 pdc20621_pop_hdma(qc);
723 }
724
725 /* step one - exec ATA command */
726 else {
727 u8 seq = (u8) (port_no + 1 + 4);
728 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
729 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
730
731 /* submit hdma pkt */
732 pdc20621_dump_hdma(qc);
733 pdc20621_push_hdma(qc, seq,
734 port_ofs + PDC_DIMM_HOST_PKT);
735 }
736 handled = 1;
737
738 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
739
740 /* step one - DMA from host to DIMM */
741 if (doing_hdma) {
742 u8 seq = (u8) (port_no + 1);
743 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
744 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
745
746 /* submit ata pkt */
747 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
748 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
749 writel(port_ofs + PDC_DIMM_ATA_PKT,
750 (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
751 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
752 }
753
754 /* step two - execute ATA command */
755 else {
756 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
757 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
758 /* get drive status; clear intr; complete txn */
759 ata_qc_complete(qc, ata_wait_idle(ap));
760 pdc20621_pop_hdma(qc);
761 }
762 handled = 1;
763
764 /* command completion, but no data xfer */
765 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
766
767 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
768 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
769 ata_qc_complete(qc, status);
770 handled = 1;
771
772 } else {
773 ap->stats.idle_irq++;
774 }
775
776 return handled;
777}
778
779static void pdc20621_irq_clear(struct ata_port *ap)
780{
781 struct ata_host_set *host_set = ap->host_set;
ea6ba10b 782 void __iomem *mmio = host_set->mmio_base;
1da177e4
LT		 783
784 mmio += PDC_CHIP0_OFS;
785
786 readl(mmio + PDC_20621_SEQMASK);
787}
788
789static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
790{
791 struct ata_host_set *host_set = dev_instance;
792 struct ata_port *ap;
793 u32 mask = 0;
794 unsigned int i, tmp, port_no;
795 unsigned int handled = 0;
ea6ba10b 796 void __iomem *mmio_base;
1da177e4
LT		 797
798 VPRINTK("ENTER\n");
799
800 if (!host_set || !host_set->mmio_base) {
801 VPRINTK("QUICK EXIT\n");
802 return IRQ_NONE;
803 }
804
805 mmio_base = host_set->mmio_base;
806
807 /* reading should also clear interrupts */
808 mmio_base += PDC_CHIP0_OFS;
809 mask = readl(mmio_base + PDC_20621_SEQMASK);
810 VPRINTK("mask == 0x%x\n", mask);
811
812 if (mask == 0xffffffff) {
813 VPRINTK("QUICK EXIT 2\n");
814 return IRQ_NONE;
815 }
816 mask &= 0xffff; /* only 16 tags possible */
817 if (!mask) {
818 VPRINTK("QUICK EXIT 3\n");
819 return IRQ_NONE;
820 }
821
822 spin_lock(&host_set->lock);
823
824 for (i = 1; i < 9; i++) {
825 port_no = i - 1;
826 if (port_no > 3)
827 port_no -= 4;
828 if (port_no >= host_set->n_ports)
829 ap = NULL;
830 else
831 ap = host_set->ports[port_no];
832 tmp = mask & (1 << i);
833 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
c1389503
TH		 834 if (tmp && ap &&
835 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 836 struct ata_queued_cmd *qc;
837
838 qc = ata_qc_from_tag(ap, ap->active_tag);
839 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
840 handled += pdc20621_host_intr(ap, qc, (i > 4),
841 mmio_base);
842 }
843 }
844
845 spin_unlock(&host_set->lock);
846
847 VPRINTK("mask == 0x%x\n", mask);
848
849 VPRINTK("EXIT\n");
850
851 return IRQ_RETVAL(handled);
852}
853
854static void pdc_eng_timeout(struct ata_port *ap)
855{
856 u8 drv_stat;
b8f6153e 857 struct ata_host_set *host_set = ap->host_set;
1da177e4 858 struct ata_queued_cmd *qc;
b8f6153e 859 unsigned long flags;
1da177e4
LT		 860
861 DPRINTK("ENTER\n");
862
b8f6153e
JG		 863 spin_lock_irqsave(&host_set->lock, flags);
864
1da177e4
LT		 865 qc = ata_qc_from_tag(ap, ap->active_tag);
866 if (!qc) {
867 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
868 ap->id);
869 goto out;
870 }
871
872 /* hack alert! We cannot use the supplied completion
873 * function from inside the ->eh_strategy_handler() thread.
874 * libata is the only user of ->eh_strategy_handler() in
875 * any kernel, so the default scsi_done() assumes it is
876 * not being called from the SCSI EH.
877 */
878 qc->scsidone = scsi_finish_command;
879
880 switch (qc->tf.protocol) {
881 case ATA_PROT_DMA:
882 case ATA_PROT_NODATA:
883 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
884 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
885 break;
886
887 default:
888 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
889
890 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
891 ap->id, qc->tf.command, drv_stat);
892
893 ata_qc_complete(qc, drv_stat);
894 break;
895 }
896
897out:
b8f6153e 898 spin_unlock_irqrestore(&host_set->lock, flags);
1da177e4
LT		 899 DPRINTK("EXIT\n");
900}
901
902static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
903{
904 WARN_ON (tf->protocol == ATA_PROT_DMA ||
905 tf->protocol == ATA_PROT_NODATA);
906 ata_tf_load(ap, tf);
907}
908
909
910static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
911{
912 WARN_ON (tf->protocol == ATA_PROT_DMA ||
913 tf->protocol == ATA_PROT_NODATA);
914 ata_exec_command(ap, tf);
915}
916
917
918static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
919{
920 port->cmd_addr = base;
921 port->data_addr = base;
922 port->feature_addr =
923 port->error_addr = base + 0x4;
924 port->nsect_addr = base + 0x8;
925 port->lbal_addr = base + 0xc;
926 port->lbam_addr = base + 0x10;
927 port->lbah_addr = base + 0x14;
928 port->device_addr = base + 0x18;
929 port->command_addr =
930 port->status_addr = base + 0x1c;
931 port->altstatus_addr =
932 port->ctl_addr = base + 0x38;
933}
934
935
936#ifdef ATA_VERBOSE_DEBUG
8a60a071 937static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
1da177e4
LT		 938 u32 offset, u32 size)
939{
940 u32 window_size;
941 u16 idx;
942 u8 page_mask;
943 long dist;
ea6ba10b 944 void __iomem *mmio = pe->mmio_base;
1da177e4 945 struct pdc_host_priv *hpriv = pe->private_data;
ea6ba10b 946 void __iomem *dimm_mmio = hpriv->dimm_mmio;
1da177e4
LT		 947
948 /* hard-code chip #0 */
949 mmio += PDC_CHIP0_OFS;
950
8a60a071
JG		 951 page_mask = 0x00;
952 window_size = 0x2000 * 4; /* 32K byte uchar size */
953 idx = (u16) (offset / window_size);
1da177e4
LT		 954
955 writel(0x01, mmio + PDC_GENERAL_CTLR);
956 readl(mmio + PDC_GENERAL_CTLR);
957 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
958 readl(mmio + PDC_DIMM_WINDOW_CTLR);
959
960 offset -= (idx * window_size);
961 idx++;
8a60a071 962 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
1da177e4 963 (long) (window_size - offset);
8a60a071 964 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
1da177e4
LT		 965 dist);
966
8a60a071 967 psource += dist;
1da177e4
LT		 968 size -= dist;
969 for (; (long) size >= (long) window_size ;) {
970 writel(0x01, mmio + PDC_GENERAL_CTLR);
971 readl(mmio + PDC_GENERAL_CTLR);
972 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
973 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 974 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1da177e4
LT		 975 window_size / 4);
976 psource += window_size;
977 size -= window_size;
978 idx ++;
979 }
980
981 if (size) {
982 writel(0x01, mmio + PDC_GENERAL_CTLR);
983 readl(mmio + PDC_GENERAL_CTLR);
984 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
985 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 986 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1da177e4
LT		 987 size / 4);
988 }
989}
990#endif
991
992
8a60a071 993static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
1da177e4
LT		 994 u32 offset, u32 size)
995{
996 u32 window_size;
997 u16 idx;
998 u8 page_mask;
999 long dist;
ea6ba10b 1000 void __iomem *mmio = pe->mmio_base;
1da177e4 1001 struct pdc_host_priv *hpriv = pe->private_data;
ea6ba10b 1002 void __iomem *dimm_mmio = hpriv->dimm_mmio;
1da177e4 1003
8a60a071 1004 /* hard-code chip #0 */
1da177e4
LT		 1005 mmio += PDC_CHIP0_OFS;
1006
8a60a071
JG		 1007 page_mask = 0x00;
1008 window_size = 0x2000 * 4; /* 32K byte uchar size */
1da177e4
LT		 1009 idx = (u16) (offset / window_size);
1010
1011 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1012 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 1013 offset -= (idx * window_size);
1da177e4
LT		 1014 idx++;
1015 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1016 (long) (window_size - offset);
1017 memcpy_toio((char *) (dimm_mmio + offset / 4), (char *) psource, dist);
1018 writel(0x01, mmio + PDC_GENERAL_CTLR);
1019 readl(mmio + PDC_GENERAL_CTLR);
1020
8a60a071 1021 psource += dist;
1da177e4
LT		 1022 size -= dist;
1023 for (; (long) size >= (long) window_size ;) {
1024 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1025 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 1026 memcpy_toio((char *) (dimm_mmio), (char *) psource,
1da177e4
LT		 1027 window_size / 4);
1028 writel(0x01, mmio + PDC_GENERAL_CTLR);
1029 readl(mmio + PDC_GENERAL_CTLR);
1030 psource += window_size;
1031 size -= window_size;
1032 idx ++;
1033 }
8a60a071 1034
1da177e4
LT		 1035 if (size) {
1036 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1037 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1038 memcpy_toio((char *) (dimm_mmio), (char *) psource, size / 4);
1039 writel(0x01, mmio + PDC_GENERAL_CTLR);
1040 readl(mmio + PDC_GENERAL_CTLR);
1041 }
1042}
1043
1044
8a60a071 1045static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1da177e4
LT		 1046 u32 subaddr, u32 *pdata)
1047{
ea6ba10b 1048 void __iomem *mmio = pe->mmio_base;
1da177e4 1049 u32 i2creg = 0;
8a60a071 1050 u32 status;
1da177e4
LT		 1051 u32 count =0;
1052
1053 /* hard-code chip #0 */
1054 mmio += PDC_CHIP0_OFS;
1055
1056 i2creg |= device << 24;
1057 i2creg |= subaddr << 16;
1058
1059 /* Set the device and subaddress */
1060 writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1061 readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1062
1063 /* Write Control to perform read operation, mask int */
8a60a071 1064 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1da177e4
LT		 1065 mmio + PDC_I2C_CONTROL_OFFSET);
1066
1067 for (count = 0; count <= 1000; count ++) {
1068 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1069 if (status & PDC_I2C_COMPLETE) {
1070 status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1071 break;
1072 } else if (count == 1000)
1073 return 0;
1074 }
1075
1076 *pdata = (status >> 8) & 0x000000ff;
8a60a071 1077 return 1;
1da177e4
LT		 1078}
1079
1080
1081static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1082{
1083 u32 data=0 ;
8a60a071 1084 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4
LT		 1085 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1086 if (data == 100)
1087 return 100;
1088 } else
1089 return 0;
8a60a071 1090
1da177e4 1091 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
8a60a071 1092 if(data <= 0x75)
1da177e4
LT		 1093 return 133;
1094 } else
1095 return 0;
8a60a071 1096
1da177e4
LT		 1097 return 0;
1098}
1099
1100
1101static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1102{
1103 u32 spd0[50];
1104 u32 data = 0;
1105 int size, i;
8a60a071 1106 u8 bdimmsize;
ea6ba10b 1107 void __iomem *mmio = pe->mmio_base;
1da177e4
LT		 1108 static const struct {
1109 unsigned int reg;
1110 unsigned int ofs;
1111 } pdc_i2c_read_data [] = {
8a60a071 1112 { PDC_DIMM_SPD_TYPE, 11 },
1da177e4 1113 { PDC_DIMM_SPD_FRESH_RATE, 12 },
8a60a071 1114 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1da177e4
LT		 1115 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1116 { PDC_DIMM_SPD_ROW_NUM, 3 },
1117 { PDC_DIMM_SPD_BANK_NUM, 17 },
1118 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1119 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1120 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1121 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1122 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
8a60a071 1123 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1da177e4
LT		 1124 };
1125
1126 /* hard-code chip #0 */
1127 mmio += PDC_CHIP0_OFS;
1128
1129 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1130 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
8a60a071 1131 pdc_i2c_read_data[i].reg,
1da177e4 1132 &spd0[pdc_i2c_read_data[i].ofs]);
8a60a071 1133
1da177e4 1134 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
8a60a071 1135 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1da177e4 1136 ((((spd0[27] + 9) / 10) - 1) << 8) ;
8a60a071
JG		 1137 data |= (((((spd0[29] > spd0[28])
1138 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1da177e4 1139 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
8a60a071
JG		 1140
1141 if (spd0[18] & 0x08)
1da177e4
LT		 1142 data |= ((0x03) << 14);
1143 else if (spd0[18] & 0x04)
1144 data |= ((0x02) << 14);
1145 else if (spd0[18] & 0x01)
1146 data |= ((0x01) << 14);
1147 else
1148 data |= (0 << 14);
1149
8a60a071 1150 /*
1da177e4
LT		 1151 Calculate the size of bDIMMSize (power of 2) and
1152 merge the DIMM size by program start/end address.
1153 */
1154
1155 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1156 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1157 data |= (((size / 16) - 1) << 16);
1158 data |= (0 << 23);
1159 data |= 8;
8a60a071 1160 writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1da177e4 1161 readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
8a60a071 1162 return size;
1da177e4
LT		 1163}
1164
1165
1166static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1167{
1168 u32 data, spd0;
1169 int error, i;
ea6ba10b 1170 void __iomem *mmio = pe->mmio_base;
1da177e4
LT		 1171
1172 /* hard-code chip #0 */
1173 mmio += PDC_CHIP0_OFS;
1174
1175 /*
1176 Set To Default : DIMM Module Global Control Register (0x022259F1)
1177 DIMM Arbitration Disable (bit 20)
1178 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1179 Refresh Enable (bit 17)
1180 */
1181
8a60a071 1182 data = 0x022259F1;
1da177e4
LT		 1183 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1184 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1185
1186 /* Turn on for ECC */
8a60a071 1187 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4
LT		 1188 PDC_DIMM_SPD_TYPE, &spd0);
1189 if (spd0 == 0x02) {
1190 data |= (0x01 << 16);
1191 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1192 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1193 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1194 }
1195
1196 /* DIMM Initialization Select/Enable (bit 18/19) */
1197 data &= (~(1<<18));
1198 data |= (1<<19);
1199 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1200
8a60a071 1201 error = 1;
1da177e4
LT		 1202 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1203 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1204 if (!(data & (1<<19))) {
1205 error = 0;
8a60a071 1206 break;
1da177e4
LT		 1207 }
1208 msleep(i*100);
1209 }
1210 return error;
1211}
8a60a071 1212
1da177e4
LT		 1213
1214static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1215{
8a60a071 1216 int speed, size, length;
1da177e4
LT		 1217 u32 addr,spd0,pci_status;
1218 u32 tmp=0;
1219 u32 time_period=0;
1220 u32 tcount=0;
1221 u32 ticks=0;
1222 u32 clock=0;
1223 u32 fparam=0;
ea6ba10b 1224 void __iomem *mmio = pe->mmio_base;
1da177e4
LT		 1225
1226 /* hard-code chip #0 */
1227 mmio += PDC_CHIP0_OFS;
1228
1229 /* Initialize PLL based upon PCI Bus Frequency */
1230
1231 /* Initialize Time Period Register */
1232 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1233 time_period = readl(mmio + PDC_TIME_PERIOD);
1234 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1235
1236 /* Enable timer */
1237 writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1238 readl(mmio + PDC_TIME_CONTROL);
1239
1240 /* Wait 3 seconds */
1241 msleep(3000);
1242
8a60a071 1243 /*
1da177e4
LT		 1244 When timer is enabled, counter is decreased every internal
1245 clock cycle.
1246 */
1247
1248 tcount = readl(mmio + PDC_TIME_COUNTER);
1249 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1250
8a60a071 1251 /*
1da177e4
LT		 1252 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1253 register should be >= (0xffffffff - 3x10^8).
1254 */
1255 if(tcount >= PCI_X_TCOUNT) {
1256 ticks = (time_period - tcount);
1257 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
8a60a071 1258
1da177e4
LT		 1259 clock = (ticks / 300000);
1260 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
8a60a071 1261
1da177e4
LT		 1262 clock = (clock * 33);
1263 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1264
1265 /* PLL F Param (bit 22:16) */
1266 fparam = (1400000 / clock) - 2;
1267 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
8a60a071 1268
1da177e4
LT		 1269 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1270 pci_status = (0x8a001824 | (fparam << 16));
1271 } else
1272 pci_status = PCI_PLL_INIT;
1273
1274 /* Initialize PLL. */
1275 VPRINTK("pci_status: 0x%x\n", pci_status);
1276 writel(pci_status, mmio + PDC_CTL_STATUS);
1277 readl(mmio + PDC_CTL_STATUS);
1278
8a60a071 1279 /*
1da177e4
LT		 1280 Read SPD of DIMM by I2C interface,
1281 and program the DIMM Module Controller.
1282 */
1283 if (!(speed = pdc20621_detect_dimm(pe))) {
8a60a071 1284 printk(KERN_ERR "Detect Local DIMM Fail\n");
1da177e4
LT		 1285 return 1; /* DIMM error */
1286 }
1287 VPRINTK("Local DIMM Speed = %d\n", speed);
1288
8a60a071 1289 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1da177e4
LT		 1290 size = pdc20621_prog_dimm0(pe);
1291 VPRINTK("Local DIMM Size = %dMB\n",size);
1292
8a60a071 1293 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1da177e4
LT		 1294 if (pdc20621_prog_dimm_global(pe)) {
1295 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1296 return 1;
1297 }
1298
1299#ifdef ATA_VERBOSE_DEBUG
1300 {
1301 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1302 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1303 '1','.','1','0',
1304 '9','8','0','3','1','6','1','2',0,0};
1305 u8 test_parttern2[40] = {0};
1306
1307 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1308 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1309
1310 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1311 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
8a60a071 1312 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1da177e4 1313 test_parttern2[1], &(test_parttern2[2]));
8a60a071 1314 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1da177e4 1315 40);
8a60a071 1316 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1da177e4
LT		 1317 test_parttern2[1], &(test_parttern2[2]));
1318
1319 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1320 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
8a60a071 1321 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1da177e4
LT		 1322 test_parttern2[1], &(test_parttern2[2]));
1323 }
1324#endif
1325
1326 /* ECC initiliazation. */
1327
8a60a071 1328 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4
LT		 1329 PDC_DIMM_SPD_TYPE, &spd0);
1330 if (spd0 == 0x02) {
1331 VPRINTK("Start ECC initialization\n");
1332 addr = 0;
1333 length = size * 1024 * 1024;
1334 while (addr < length) {
8a60a071 1335 pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1da177e4
LT		 1336 sizeof(u32));
1337 addr += sizeof(u32);
1338 }
1339 VPRINTK("Finish ECC initialization\n");
1340 }
1341 return 0;
1342}
1343
1344
1345static void pdc_20621_init(struct ata_probe_ent *pe)
1346{
1347 u32 tmp;
ea6ba10b 1348 void __iomem *mmio = pe->mmio_base;
1da177e4
LT		 1349
1350 /* hard-code chip #0 */
1351 mmio += PDC_CHIP0_OFS;
1352
1353 /*
1354 * Select page 0x40 for our 32k DIMM window
1355 */
1356 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1357 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1358 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1359
1360 /*
1361 * Reset Host DMA
1362 */
1363 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1364 tmp |= PDC_RESET;
1365 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1366 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1367
1368 udelay(10);
1369
1370 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1371 tmp &= ~PDC_RESET;
1372 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1373 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1374}
1375
1376static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1377{
1378 static int printed_version;
1379 struct ata_probe_ent *probe_ent = NULL;
1380 unsigned long base;
ea6ba10b
JG		 1381 void __iomem *mmio_base;
1382 void __iomem *dimm_mmio = NULL;
1da177e4
LT		 1383 struct pdc_host_priv *hpriv = NULL;
1384 unsigned int board_idx = (unsigned int) ent->driver_data;
1385 int pci_dev_busy = 0;
1386 int rc;
1387
1388 if (!printed_version++)
1389 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1390
1391 /*
1392 * If this driver happens to only be useful on Apple's K2, then
1393 * we should check that here as it has a normal Serverworks ID
1394 */
1395 rc = pci_enable_device(pdev);
1396 if (rc)
1397 return rc;
1398
1399 rc = pci_request_regions(pdev, DRV_NAME);
1400 if (rc) {
1401 pci_dev_busy = 1;
1402 goto err_out;
1403 }
1404
1405 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1406 if (rc)
1407 goto err_out_regions;
1408 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1409 if (rc)
1410 goto err_out_regions;
1411
1412 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1413 if (probe_ent == NULL) {
1414 rc = -ENOMEM;
1415 goto err_out_regions;
1416 }
1417
1418 memset(probe_ent, 0, sizeof(*probe_ent));
1419 probe_ent->dev = pci_dev_to_dev(pdev);
1420 INIT_LIST_HEAD(&probe_ent->node);
1421
374b1873 1422 mmio_base = pci_iomap(pdev, 3, 0);
1da177e4
LT		 1423 if (mmio_base == NULL) {
1424 rc = -ENOMEM;
1425 goto err_out_free_ent;
1426 }
1427 base = (unsigned long) mmio_base;
1428
1429 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1430 if (!hpriv) {
1431 rc = -ENOMEM;
1432 goto err_out_iounmap;
1433 }
1434 memset(hpriv, 0, sizeof(*hpriv));
1435
374b1873 1436 dimm_mmio = pci_iomap(pdev, 4, 0);
1da177e4
LT		 1437 if (!dimm_mmio) {
1438 kfree(hpriv);
1439 rc = -ENOMEM;
1440 goto err_out_iounmap;
1441 }
1442
1443 hpriv->dimm_mmio = dimm_mmio;
1444
1445 probe_ent->sht = pdc_port_info[board_idx].sht;
1446 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
1447 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1448 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1449 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1450 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1451
1452 probe_ent->irq = pdev->irq;
1453 probe_ent->irq_flags = SA_SHIRQ;
1454 probe_ent->mmio_base = mmio_base;
1455
1456 probe_ent->private_data = hpriv;
1457 base += PDC_CHIP0_OFS;
1458
1459 probe_ent->n_ports = 4;
1460 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1461 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1462 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1463 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1464
1465 pci_set_master(pdev);
1466
1467 /* initialize adapter */
1468 /* initialize local dimm */
1469 if (pdc20621_dimm_init(probe_ent)) {
1470 rc = -ENOMEM;
1471 goto err_out_iounmap_dimm;
1472 }
1473 pdc_20621_init(probe_ent);
1474
1475 /* FIXME: check ata_device_add return value */
1476 ata_device_add(probe_ent);
1477 kfree(probe_ent);
1478
1479 return 0;
1480
1481err_out_iounmap_dimm: /* only get to this label if 20621 */
1482 kfree(hpriv);
374b1873 1483 pci_iounmap(pdev, dimm_mmio);
1da177e4 1484err_out_iounmap:
374b1873 1485 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1486err_out_free_ent:
1487 kfree(probe_ent);
1488err_out_regions:
1489 pci_release_regions(pdev);
1490err_out:
1491 if (!pci_dev_busy)
1492 pci_disable_device(pdev);
1493 return rc;
1494}
1495
1496
1497static int __init pdc_sata_init(void)
1498{
1499 return pci_module_init(&pdc_sata_pci_driver);
1500}
1501
1502
1503static void __exit pdc_sata_exit(void)
1504{
1505 pci_unregister_driver(&pdc_sata_pci_driver);
1506}
1507
1508
1509MODULE_AUTHOR("Jeff Garzik");
1510MODULE_DESCRIPTION("Promise SATA low-level driver");
1511MODULE_LICENSE("GPL");
1512MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1513MODULE_VERSION(DRV_VERSION);
1514
1515module_init(pdc_sata_init);
1516module_exit(pdc_sata_exit);
kernel source for telekom puls (alcatel/mediatek)