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1da177e4 LT |
1 | /* |
2 | * sata_sx4.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
1da177e4 | 42 | #include <scsi/scsi_host.h> |
193515d5 | 43 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
44 | #include <linux/libata.h> |
45 | #include <asm/io.h> | |
46 | #include "sata_promise.h" | |
47 | ||
48 | #define DRV_NAME "sata_sx4" | |
7bdd7208 | 49 | #define DRV_VERSION "0.8" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */ | |
54 | ||
55 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | |
56 | PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */ | |
57 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
58 | PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */ | |
59 | ||
60 | PDC_20621_SEQCTL = 0x400, | |
61 | PDC_20621_SEQMASK = 0x480, | |
62 | PDC_20621_GENERAL_CTL = 0x484, | |
63 | PDC_20621_PAGE_SIZE = (32 * 1024), | |
64 | ||
65 | /* chosen, not constant, values; we design our own DIMM mem map */ | |
66 | PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */ | |
67 | PDC_20621_DIMM_BASE = 0x00200000, | |
68 | PDC_20621_DIMM_DATA = (64 * 1024), | |
69 | PDC_DIMM_DATA_STEP = (256 * 1024), | |
70 | PDC_DIMM_WINDOW_STEP = (8 * 1024), | |
71 | PDC_DIMM_HOST_PRD = (6 * 1024), | |
72 | PDC_DIMM_HOST_PKT = (128 * 0), | |
73 | PDC_DIMM_HPKT_PRD = (128 * 1), | |
74 | PDC_DIMM_ATA_PKT = (128 * 2), | |
75 | PDC_DIMM_APKT_PRD = (128 * 3), | |
76 | PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128, | |
77 | PDC_PAGE_WINDOW = 0x40, | |
78 | PDC_PAGE_DATA = PDC_PAGE_WINDOW + | |
79 | (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE), | |
80 | PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE, | |
81 | ||
82 | PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */ | |
83 | ||
84 | PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
85 | (1<<23), | |
86 | ||
87 | board_20621 = 0, /* FastTrak S150 SX4 */ | |
88 | ||
89 | PDC_RESET = (1 << 11), /* HDMA reset */ | |
90 | ||
91 | PDC_MAX_HDMA = 32, | |
92 | PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1), | |
93 | ||
94 | PDC_DIMM0_SPD_DEV_ADDRESS = 0x50, | |
95 | PDC_DIMM1_SPD_DEV_ADDRESS = 0x51, | |
96 | PDC_MAX_DIMM_MODULE = 0x02, | |
97 | PDC_I2C_CONTROL_OFFSET = 0x48, | |
98 | PDC_I2C_ADDR_DATA_OFFSET = 0x4C, | |
99 | PDC_DIMM0_CONTROL_OFFSET = 0x80, | |
100 | PDC_DIMM1_CONTROL_OFFSET = 0x84, | |
101 | PDC_SDRAM_CONTROL_OFFSET = 0x88, | |
102 | PDC_I2C_WRITE = 0x00000000, | |
8a60a071 | 103 | PDC_I2C_READ = 0x00000040, |
1da177e4 LT |
104 | PDC_I2C_START = 0x00000080, |
105 | PDC_I2C_MASK_INT = 0x00000020, | |
106 | PDC_I2C_COMPLETE = 0x00010000, | |
107 | PDC_I2C_NO_ACK = 0x00100000, | |
108 | PDC_DIMM_SPD_SUBADDRESS_START = 0x00, | |
109 | PDC_DIMM_SPD_SUBADDRESS_END = 0x7F, | |
110 | PDC_DIMM_SPD_ROW_NUM = 3, | |
111 | PDC_DIMM_SPD_COLUMN_NUM = 4, | |
112 | PDC_DIMM_SPD_MODULE_ROW = 5, | |
113 | PDC_DIMM_SPD_TYPE = 11, | |
8a60a071 JG |
114 | PDC_DIMM_SPD_FRESH_RATE = 12, |
115 | PDC_DIMM_SPD_BANK_NUM = 17, | |
1da177e4 | 116 | PDC_DIMM_SPD_CAS_LATENCY = 18, |
8a60a071 | 117 | PDC_DIMM_SPD_ATTRIBUTE = 21, |
1da177e4 | 118 | PDC_DIMM_SPD_ROW_PRE_CHARGE = 27, |
8a60a071 | 119 | PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28, |
1da177e4 LT |
120 | PDC_DIMM_SPD_RAS_CAS_DELAY = 29, |
121 | PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30, | |
122 | PDC_DIMM_SPD_SYSTEM_FREQ = 126, | |
8a60a071 | 123 | PDC_CTL_STATUS = 0x08, |
1da177e4 LT |
124 | PDC_DIMM_WINDOW_CTLR = 0x0C, |
125 | PDC_TIME_CONTROL = 0x3C, | |
126 | PDC_TIME_PERIOD = 0x40, | |
127 | PDC_TIME_COUNTER = 0x44, | |
128 | PDC_GENERAL_CTLR = 0x484, | |
129 | PCI_PLL_INIT = 0x8A531824, | |
130 | PCI_X_TCOUNT = 0xEE1E5CFF | |
131 | }; | |
132 | ||
133 | ||
134 | struct pdc_port_priv { | |
135 | u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512]; | |
136 | u8 *pkt; | |
137 | dma_addr_t pkt_dma; | |
138 | }; | |
139 | ||
140 | struct pdc_host_priv { | |
a9afd7cd | 141 | void __iomem *dimm_mmio; |
1da177e4 LT |
142 | |
143 | unsigned int doing_hdma; | |
144 | unsigned int hdma_prod; | |
145 | unsigned int hdma_cons; | |
146 | struct { | |
147 | struct ata_queued_cmd *qc; | |
148 | unsigned int seq; | |
149 | unsigned long pkt_ofs; | |
150 | } hdma[32]; | |
151 | }; | |
152 | ||
153 | ||
154 | static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
155 | static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs); | |
156 | static void pdc_eng_timeout(struct ata_port *ap); | |
157 | static void pdc_20621_phy_reset (struct ata_port *ap); | |
158 | static int pdc_port_start(struct ata_port *ap); | |
159 | static void pdc_port_stop(struct ata_port *ap); | |
160 | static void pdc20621_qc_prep(struct ata_queued_cmd *qc); | |
057ace5e JG |
161 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
162 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
1da177e4 LT |
163 | static void pdc20621_host_stop(struct ata_host_set *host_set); |
164 | static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe); | |
165 | static int pdc20621_detect_dimm(struct ata_probe_ent *pe); | |
8a60a071 | 166 | static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, |
1da177e4 LT |
167 | u32 device, u32 subaddr, u32 *pdata); |
168 | static int pdc20621_prog_dimm0(struct ata_probe_ent *pe); | |
169 | static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe); | |
170 | #ifdef ATA_VERBOSE_DEBUG | |
8a60a071 | 171 | static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, |
1da177e4 LT |
172 | void *psource, u32 offset, u32 size); |
173 | #endif | |
8a60a071 | 174 | static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, |
1da177e4 LT |
175 | void *psource, u32 offset, u32 size); |
176 | static void pdc20621_irq_clear(struct ata_port *ap); | |
177 | static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc); | |
178 | ||
179 | ||
193515d5 | 180 | static struct scsi_host_template pdc_sata_sht = { |
1da177e4 LT |
181 | .module = THIS_MODULE, |
182 | .name = DRV_NAME, | |
183 | .ioctl = ata_scsi_ioctl, | |
184 | .queuecommand = ata_scsi_queuecmd, | |
185 | .eh_strategy_handler = ata_scsi_error, | |
186 | .can_queue = ATA_DEF_QUEUE, | |
187 | .this_id = ATA_SHT_THIS_ID, | |
188 | .sg_tablesize = LIBATA_MAX_PRD, | |
189 | .max_sectors = ATA_MAX_SECTORS, | |
190 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
191 | .emulated = ATA_SHT_EMULATED, | |
192 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
193 | .proc_name = DRV_NAME, | |
194 | .dma_boundary = ATA_DMA_BOUNDARY, | |
195 | .slave_configure = ata_scsi_slave_config, | |
196 | .bios_param = ata_std_bios_param, | |
197 | .ordered_flush = 1, | |
198 | }; | |
199 | ||
057ace5e | 200 | static const struct ata_port_operations pdc_20621_ops = { |
1da177e4 LT |
201 | .port_disable = ata_port_disable, |
202 | .tf_load = pdc_tf_load_mmio, | |
203 | .tf_read = ata_tf_read, | |
204 | .check_status = ata_check_status, | |
205 | .exec_command = pdc_exec_command_mmio, | |
206 | .dev_select = ata_std_dev_select, | |
207 | .phy_reset = pdc_20621_phy_reset, | |
208 | .qc_prep = pdc20621_qc_prep, | |
209 | .qc_issue = pdc20621_qc_issue_prot, | |
210 | .eng_timeout = pdc_eng_timeout, | |
211 | .irq_handler = pdc20621_interrupt, | |
212 | .irq_clear = pdc20621_irq_clear, | |
213 | .port_start = pdc_port_start, | |
214 | .port_stop = pdc_port_stop, | |
215 | .host_stop = pdc20621_host_stop, | |
216 | }; | |
217 | ||
218 | static struct ata_port_info pdc_port_info[] = { | |
219 | /* board_20621 */ | |
220 | { | |
221 | .sht = &pdc_sata_sht, | |
222 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
50630195 JG |
223 | ATA_FLAG_SRST | ATA_FLAG_MMIO | |
224 | ATA_FLAG_NO_ATAPI, | |
1da177e4 LT |
225 | .pio_mask = 0x1f, /* pio0-4 */ |
226 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
227 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
228 | .port_ops = &pdc_20621_ops, | |
229 | }, | |
230 | ||
231 | }; | |
232 | ||
3b7d697d | 233 | static const struct pci_device_id pdc_sata_pci_tbl[] = { |
1da177e4 LT |
234 | { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
235 | board_20621 }, | |
236 | { } /* terminate list */ | |
237 | }; | |
238 | ||
239 | ||
240 | static struct pci_driver pdc_sata_pci_driver = { | |
241 | .name = DRV_NAME, | |
242 | .id_table = pdc_sata_pci_tbl, | |
243 | .probe = pdc_sata_init_one, | |
244 | .remove = ata_pci_remove_one, | |
245 | }; | |
246 | ||
247 | ||
248 | static void pdc20621_host_stop(struct ata_host_set *host_set) | |
249 | { | |
374b1873 | 250 | struct pci_dev *pdev = to_pci_dev(host_set->dev); |
1da177e4 | 251 | struct pdc_host_priv *hpriv = host_set->private_data; |
a9afd7cd | 252 | void __iomem *dimm_mmio = hpriv->dimm_mmio; |
1da177e4 | 253 | |
374b1873 | 254 | pci_iounmap(pdev, dimm_mmio); |
1da177e4 | 255 | kfree(hpriv); |
aa8f0dc6 | 256 | |
374b1873 | 257 | pci_iounmap(pdev, host_set->mmio_base); |
1da177e4 LT |
258 | } |
259 | ||
260 | static int pdc_port_start(struct ata_port *ap) | |
261 | { | |
262 | struct device *dev = ap->host_set->dev; | |
263 | struct pdc_port_priv *pp; | |
264 | int rc; | |
265 | ||
266 | rc = ata_port_start(ap); | |
267 | if (rc) | |
268 | return rc; | |
269 | ||
270 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
271 | if (!pp) { | |
272 | rc = -ENOMEM; | |
273 | goto err_out; | |
274 | } | |
275 | memset(pp, 0, sizeof(*pp)); | |
276 | ||
277 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
278 | if (!pp->pkt) { | |
279 | rc = -ENOMEM; | |
280 | goto err_out_kfree; | |
281 | } | |
282 | ||
283 | ap->private_data = pp; | |
284 | ||
285 | return 0; | |
286 | ||
287 | err_out_kfree: | |
288 | kfree(pp); | |
289 | err_out: | |
290 | ata_port_stop(ap); | |
291 | return rc; | |
292 | } | |
293 | ||
294 | ||
295 | static void pdc_port_stop(struct ata_port *ap) | |
296 | { | |
297 | struct device *dev = ap->host_set->dev; | |
298 | struct pdc_port_priv *pp = ap->private_data; | |
299 | ||
300 | ap->private_data = NULL; | |
301 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
302 | kfree(pp); | |
303 | ata_port_stop(ap); | |
304 | } | |
305 | ||
306 | ||
307 | static void pdc_20621_phy_reset (struct ata_port *ap) | |
308 | { | |
309 | VPRINTK("ENTER\n"); | |
310 | ap->cbl = ATA_CBL_SATA; | |
311 | ata_port_probe(ap); | |
312 | ata_bus_reset(ap); | |
313 | } | |
314 | ||
315 | static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf, | |
316 | unsigned int portno, | |
317 | unsigned int total_len) | |
318 | { | |
319 | u32 addr; | |
320 | unsigned int dw = PDC_DIMM_APKT_PRD >> 2; | |
321 | u32 *buf32 = (u32 *) buf; | |
322 | ||
323 | /* output ATA packet S/G table */ | |
324 | addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA + | |
325 | (PDC_DIMM_DATA_STEP * portno); | |
326 | VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr); | |
327 | buf32[dw] = cpu_to_le32(addr); | |
328 | buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT); | |
329 | ||
330 | VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n", | |
331 | PDC_20621_DIMM_BASE + | |
332 | (PDC_DIMM_WINDOW_STEP * portno) + | |
333 | PDC_DIMM_APKT_PRD, | |
334 | buf32[dw], buf32[dw + 1]); | |
335 | } | |
336 | ||
337 | static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf, | |
338 | unsigned int portno, | |
339 | unsigned int total_len) | |
340 | { | |
341 | u32 addr; | |
342 | unsigned int dw = PDC_DIMM_HPKT_PRD >> 2; | |
343 | u32 *buf32 = (u32 *) buf; | |
344 | ||
345 | /* output Host DMA packet S/G table */ | |
346 | addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA + | |
347 | (PDC_DIMM_DATA_STEP * portno); | |
348 | ||
349 | buf32[dw] = cpu_to_le32(addr); | |
350 | buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT); | |
351 | ||
352 | VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n", | |
353 | PDC_20621_DIMM_BASE + | |
354 | (PDC_DIMM_WINDOW_STEP * portno) + | |
355 | PDC_DIMM_HPKT_PRD, | |
356 | buf32[dw], buf32[dw + 1]); | |
357 | } | |
358 | ||
359 | static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf, | |
360 | unsigned int devno, u8 *buf, | |
361 | unsigned int portno) | |
362 | { | |
363 | unsigned int i, dw; | |
364 | u32 *buf32 = (u32 *) buf; | |
365 | u8 dev_reg; | |
366 | ||
367 | unsigned int dimm_sg = PDC_20621_DIMM_BASE + | |
368 | (PDC_DIMM_WINDOW_STEP * portno) + | |
369 | PDC_DIMM_APKT_PRD; | |
370 | VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg); | |
371 | ||
372 | i = PDC_DIMM_ATA_PKT; | |
373 | ||
374 | /* | |
375 | * Set up ATA packet | |
376 | */ | |
377 | if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE))) | |
378 | buf[i++] = PDC_PKT_READ; | |
379 | else if (tf->protocol == ATA_PROT_NODATA) | |
380 | buf[i++] = PDC_PKT_NODATA; | |
381 | else | |
382 | buf[i++] = 0; | |
383 | buf[i++] = 0; /* reserved */ | |
384 | buf[i++] = portno + 1; /* seq. id */ | |
385 | buf[i++] = 0xff; /* delay seq. id */ | |
386 | ||
387 | /* dimm dma S/G, and next-pkt */ | |
388 | dw = i >> 2; | |
389 | if (tf->protocol == ATA_PROT_NODATA) | |
390 | buf32[dw] = 0; | |
391 | else | |
392 | buf32[dw] = cpu_to_le32(dimm_sg); | |
393 | buf32[dw + 1] = 0; | |
394 | i += 8; | |
395 | ||
396 | if (devno == 0) | |
397 | dev_reg = ATA_DEVICE_OBS; | |
398 | else | |
399 | dev_reg = ATA_DEVICE_OBS | ATA_DEV1; | |
400 | ||
401 | /* select device */ | |
402 | buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE; | |
403 | buf[i++] = dev_reg; | |
404 | ||
405 | /* device control register */ | |
406 | buf[i++] = (1 << 5) | PDC_REG_DEVCTL; | |
407 | buf[i++] = tf->ctl; | |
408 | ||
409 | return i; | |
410 | } | |
411 | ||
412 | static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf, | |
413 | unsigned int portno) | |
414 | { | |
415 | unsigned int dw; | |
416 | u32 tmp, *buf32 = (u32 *) buf; | |
417 | ||
418 | unsigned int host_sg = PDC_20621_DIMM_BASE + | |
419 | (PDC_DIMM_WINDOW_STEP * portno) + | |
420 | PDC_DIMM_HOST_PRD; | |
421 | unsigned int dimm_sg = PDC_20621_DIMM_BASE + | |
422 | (PDC_DIMM_WINDOW_STEP * portno) + | |
423 | PDC_DIMM_HPKT_PRD; | |
424 | VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg); | |
425 | VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg); | |
426 | ||
427 | dw = PDC_DIMM_HOST_PKT >> 2; | |
428 | ||
429 | /* | |
430 | * Set up Host DMA packet | |
431 | */ | |
432 | if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE))) | |
433 | tmp = PDC_PKT_READ; | |
434 | else | |
435 | tmp = 0; | |
436 | tmp |= ((portno + 1 + 4) << 16); /* seq. id */ | |
437 | tmp |= (0xff << 24); /* delay seq. id */ | |
438 | buf32[dw + 0] = cpu_to_le32(tmp); | |
439 | buf32[dw + 1] = cpu_to_le32(host_sg); | |
440 | buf32[dw + 2] = cpu_to_le32(dimm_sg); | |
441 | buf32[dw + 3] = 0; | |
442 | ||
443 | VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n", | |
444 | PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) + | |
445 | PDC_DIMM_HOST_PKT, | |
446 | buf32[dw + 0], | |
447 | buf32[dw + 1], | |
448 | buf32[dw + 2], | |
449 | buf32[dw + 3]); | |
450 | } | |
451 | ||
452 | static void pdc20621_dma_prep(struct ata_queued_cmd *qc) | |
453 | { | |
cedc9a47 | 454 | struct scatterlist *sg; |
1da177e4 LT |
455 | struct ata_port *ap = qc->ap; |
456 | struct pdc_port_priv *pp = ap->private_data; | |
ea6ba10b | 457 | void __iomem *mmio = ap->host_set->mmio_base; |
1da177e4 | 458 | struct pdc_host_priv *hpriv = ap->host_set->private_data; |
ea6ba10b | 459 | void __iomem *dimm_mmio = hpriv->dimm_mmio; |
1da177e4 | 460 | unsigned int portno = ap->port_no; |
cedc9a47 | 461 | unsigned int i, idx, total_len = 0, sgt_len; |
1da177e4 LT |
462 | u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ]; |
463 | ||
464 | assert(qc->flags & ATA_QCFLAG_DMAMAP); | |
465 | ||
466 | VPRINTK("ata%u: ENTER\n", ap->id); | |
467 | ||
468 | /* hard-code chip #0 */ | |
469 | mmio += PDC_CHIP0_OFS; | |
470 | ||
471 | /* | |
472 | * Build S/G table | |
473 | */ | |
1da177e4 | 474 | idx = 0; |
cedc9a47 JG |
475 | ata_for_each_sg(sg, qc) { |
476 | buf[idx++] = cpu_to_le32(sg_dma_address(sg)); | |
477 | buf[idx++] = cpu_to_le32(sg_dma_len(sg)); | |
478 | total_len += sg_dma_len(sg); | |
1da177e4 LT |
479 | } |
480 | buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT); | |
481 | sgt_len = idx * 4; | |
482 | ||
483 | /* | |
484 | * Build ATA, host DMA packets | |
485 | */ | |
486 | pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len); | |
487 | pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno); | |
488 | ||
489 | pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len); | |
490 | i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno); | |
491 | ||
492 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
493 | i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i); | |
494 | else | |
495 | i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i); | |
496 | ||
497 | pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i); | |
498 | ||
499 | /* copy three S/G tables and two packets to DIMM MMIO window */ | |
500 | memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP), | |
501 | &pp->dimm_buf, PDC_DIMM_HEADER_SZ); | |
502 | memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) + | |
503 | PDC_DIMM_HOST_PRD, | |
504 | &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len); | |
505 | ||
506 | /* force host FIFO dump */ | |
507 | writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); | |
508 | ||
509 | readl(dimm_mmio); /* MMIO PCI posting flush */ | |
510 | ||
511 | VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len); | |
512 | } | |
513 | ||
514 | static void pdc20621_nodata_prep(struct ata_queued_cmd *qc) | |
515 | { | |
516 | struct ata_port *ap = qc->ap; | |
517 | struct pdc_port_priv *pp = ap->private_data; | |
ea6ba10b | 518 | void __iomem *mmio = ap->host_set->mmio_base; |
1da177e4 | 519 | struct pdc_host_priv *hpriv = ap->host_set->private_data; |
ea6ba10b | 520 | void __iomem *dimm_mmio = hpriv->dimm_mmio; |
1da177e4 LT |
521 | unsigned int portno = ap->port_no; |
522 | unsigned int i; | |
523 | ||
524 | VPRINTK("ata%u: ENTER\n", ap->id); | |
525 | ||
526 | /* hard-code chip #0 */ | |
527 | mmio += PDC_CHIP0_OFS; | |
528 | ||
529 | i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno); | |
530 | ||
531 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
532 | i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i); | |
533 | else | |
534 | i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i); | |
535 | ||
536 | pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i); | |
537 | ||
538 | /* copy three S/G tables and two packets to DIMM MMIO window */ | |
539 | memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP), | |
540 | &pp->dimm_buf, PDC_DIMM_HEADER_SZ); | |
541 | ||
542 | /* force host FIFO dump */ | |
543 | writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); | |
544 | ||
545 | readl(dimm_mmio); /* MMIO PCI posting flush */ | |
546 | ||
547 | VPRINTK("ata pkt buf ofs %u, mmio copied\n", i); | |
548 | } | |
549 | ||
550 | static void pdc20621_qc_prep(struct ata_queued_cmd *qc) | |
551 | { | |
552 | switch (qc->tf.protocol) { | |
553 | case ATA_PROT_DMA: | |
554 | pdc20621_dma_prep(qc); | |
555 | break; | |
556 | case ATA_PROT_NODATA: | |
557 | pdc20621_nodata_prep(qc); | |
558 | break; | |
559 | default: | |
560 | break; | |
561 | } | |
562 | } | |
563 | ||
564 | static void __pdc20621_push_hdma(struct ata_queued_cmd *qc, | |
565 | unsigned int seq, | |
566 | u32 pkt_ofs) | |
567 | { | |
568 | struct ata_port *ap = qc->ap; | |
569 | struct ata_host_set *host_set = ap->host_set; | |
ea6ba10b | 570 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
571 | |
572 | /* hard-code chip #0 */ | |
573 | mmio += PDC_CHIP0_OFS; | |
574 | ||
575 | writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); | |
576 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ | |
577 | ||
578 | writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT); | |
579 | readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */ | |
580 | } | |
581 | ||
582 | static void pdc20621_push_hdma(struct ata_queued_cmd *qc, | |
583 | unsigned int seq, | |
584 | u32 pkt_ofs) | |
585 | { | |
586 | struct ata_port *ap = qc->ap; | |
587 | struct pdc_host_priv *pp = ap->host_set->private_data; | |
588 | unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK; | |
589 | ||
590 | if (!pp->doing_hdma) { | |
591 | __pdc20621_push_hdma(qc, seq, pkt_ofs); | |
592 | pp->doing_hdma = 1; | |
593 | return; | |
594 | } | |
595 | ||
596 | pp->hdma[idx].qc = qc; | |
597 | pp->hdma[idx].seq = seq; | |
598 | pp->hdma[idx].pkt_ofs = pkt_ofs; | |
599 | pp->hdma_prod++; | |
600 | } | |
601 | ||
602 | static void pdc20621_pop_hdma(struct ata_queued_cmd *qc) | |
603 | { | |
604 | struct ata_port *ap = qc->ap; | |
605 | struct pdc_host_priv *pp = ap->host_set->private_data; | |
606 | unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK; | |
607 | ||
608 | /* if nothing on queue, we're done */ | |
609 | if (pp->hdma_prod == pp->hdma_cons) { | |
610 | pp->doing_hdma = 0; | |
611 | return; | |
612 | } | |
613 | ||
614 | __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq, | |
615 | pp->hdma[idx].pkt_ofs); | |
616 | pp->hdma_cons++; | |
617 | } | |
618 | ||
619 | #ifdef ATA_VERBOSE_DEBUG | |
620 | static void pdc20621_dump_hdma(struct ata_queued_cmd *qc) | |
621 | { | |
622 | struct ata_port *ap = qc->ap; | |
623 | unsigned int port_no = ap->port_no; | |
624 | struct pdc_host_priv *hpriv = ap->host_set->private_data; | |
625 | void *dimm_mmio = hpriv->dimm_mmio; | |
626 | ||
627 | dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP); | |
628 | dimm_mmio += PDC_DIMM_HOST_PKT; | |
629 | ||
630 | printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio)); | |
631 | printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4)); | |
632 | printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8)); | |
633 | printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12)); | |
634 | } | |
635 | #else | |
636 | static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { } | |
637 | #endif /* ATA_VERBOSE_DEBUG */ | |
638 | ||
639 | static void pdc20621_packet_start(struct ata_queued_cmd *qc) | |
640 | { | |
641 | struct ata_port *ap = qc->ap; | |
642 | struct ata_host_set *host_set = ap->host_set; | |
643 | unsigned int port_no = ap->port_no; | |
ea6ba10b | 644 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
645 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); |
646 | u8 seq = (u8) (port_no + 1); | |
647 | unsigned int port_ofs; | |
648 | ||
649 | /* hard-code chip #0 */ | |
650 | mmio += PDC_CHIP0_OFS; | |
651 | ||
652 | VPRINTK("ata%u: ENTER\n", ap->id); | |
653 | ||
654 | wmb(); /* flush PRD, pkt writes */ | |
655 | ||
656 | port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no); | |
657 | ||
658 | /* if writing, we (1) DMA to DIMM, then (2) do ATA command */ | |
659 | if (rw && qc->tf.protocol == ATA_PROT_DMA) { | |
660 | seq += 4; | |
661 | ||
662 | pdc20621_dump_hdma(qc); | |
663 | pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT); | |
664 | VPRINTK("queued ofs 0x%x (%u), seq %u\n", | |
665 | port_ofs + PDC_DIMM_HOST_PKT, | |
666 | port_ofs + PDC_DIMM_HOST_PKT, | |
667 | seq); | |
668 | } else { | |
669 | writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); | |
670 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ | |
671 | ||
672 | writel(port_ofs + PDC_DIMM_ATA_PKT, | |
a9afd7cd AV |
673 | (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
674 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | |
1da177e4 LT |
675 | VPRINTK("submitted ofs 0x%x (%u), seq %u\n", |
676 | port_ofs + PDC_DIMM_ATA_PKT, | |
677 | port_ofs + PDC_DIMM_ATA_PKT, | |
678 | seq); | |
679 | } | |
680 | } | |
681 | ||
682 | static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc) | |
683 | { | |
684 | switch (qc->tf.protocol) { | |
685 | case ATA_PROT_DMA: | |
686 | case ATA_PROT_NODATA: | |
687 | pdc20621_packet_start(qc); | |
688 | return 0; | |
689 | ||
690 | case ATA_PROT_ATAPI_DMA: | |
691 | BUG(); | |
692 | break; | |
693 | ||
694 | default: | |
695 | break; | |
696 | } | |
697 | ||
698 | return ata_qc_issue_prot(qc); | |
699 | } | |
700 | ||
701 | static inline unsigned int pdc20621_host_intr( struct ata_port *ap, | |
702 | struct ata_queued_cmd *qc, | |
703 | unsigned int doing_hdma, | |
ea6ba10b | 704 | void __iomem *mmio) |
1da177e4 LT |
705 | { |
706 | unsigned int port_no = ap->port_no; | |
707 | unsigned int port_ofs = | |
708 | PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no); | |
709 | u8 status; | |
710 | unsigned int handled = 0; | |
711 | ||
712 | VPRINTK("ENTER\n"); | |
713 | ||
714 | if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */ | |
715 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
716 | ||
717 | /* step two - DMA from DIMM to host */ | |
718 | if (doing_hdma) { | |
719 | VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id, | |
720 | readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); | |
721 | /* get drive status; clear intr; complete txn */ | |
a7dac447 | 722 | ata_qc_complete(qc, ac_err_mask(ata_wait_idle(ap))); |
1da177e4 LT |
723 | pdc20621_pop_hdma(qc); |
724 | } | |
725 | ||
726 | /* step one - exec ATA command */ | |
727 | else { | |
728 | u8 seq = (u8) (port_no + 1 + 4); | |
729 | VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id, | |
730 | readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); | |
731 | ||
732 | /* submit hdma pkt */ | |
733 | pdc20621_dump_hdma(qc); | |
734 | pdc20621_push_hdma(qc, seq, | |
735 | port_ofs + PDC_DIMM_HOST_PKT); | |
736 | } | |
737 | handled = 1; | |
738 | ||
739 | } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */ | |
740 | ||
741 | /* step one - DMA from host to DIMM */ | |
742 | if (doing_hdma) { | |
743 | u8 seq = (u8) (port_no + 1); | |
744 | VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id, | |
745 | readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); | |
746 | ||
747 | /* submit ata pkt */ | |
748 | writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); | |
749 | readl(mmio + PDC_20621_SEQCTL + (seq * 4)); | |
750 | writel(port_ofs + PDC_DIMM_ATA_PKT, | |
a9afd7cd AV |
751 | (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
752 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | |
1da177e4 LT |
753 | } |
754 | ||
755 | /* step two - execute ATA command */ | |
756 | else { | |
757 | VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id, | |
758 | readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT)); | |
759 | /* get drive status; clear intr; complete txn */ | |
a7dac447 | 760 | ata_qc_complete(qc, ac_err_mask(ata_wait_idle(ap))); |
1da177e4 LT |
761 | pdc20621_pop_hdma(qc); |
762 | } | |
763 | handled = 1; | |
764 | ||
765 | /* command completion, but no data xfer */ | |
766 | } else if (qc->tf.protocol == ATA_PROT_NODATA) { | |
767 | ||
768 | status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
769 | DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status); | |
a7dac447 | 770 | ata_qc_complete(qc, ac_err_mask(status)); |
1da177e4 LT |
771 | handled = 1; |
772 | ||
773 | } else { | |
774 | ap->stats.idle_irq++; | |
775 | } | |
776 | ||
777 | return handled; | |
778 | } | |
779 | ||
780 | static void pdc20621_irq_clear(struct ata_port *ap) | |
781 | { | |
782 | struct ata_host_set *host_set = ap->host_set; | |
ea6ba10b | 783 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
784 | |
785 | mmio += PDC_CHIP0_OFS; | |
786 | ||
787 | readl(mmio + PDC_20621_SEQMASK); | |
788 | } | |
789 | ||
790 | static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs) | |
791 | { | |
792 | struct ata_host_set *host_set = dev_instance; | |
793 | struct ata_port *ap; | |
794 | u32 mask = 0; | |
795 | unsigned int i, tmp, port_no; | |
796 | unsigned int handled = 0; | |
ea6ba10b | 797 | void __iomem *mmio_base; |
1da177e4 LT |
798 | |
799 | VPRINTK("ENTER\n"); | |
800 | ||
801 | if (!host_set || !host_set->mmio_base) { | |
802 | VPRINTK("QUICK EXIT\n"); | |
803 | return IRQ_NONE; | |
804 | } | |
805 | ||
806 | mmio_base = host_set->mmio_base; | |
807 | ||
808 | /* reading should also clear interrupts */ | |
809 | mmio_base += PDC_CHIP0_OFS; | |
810 | mask = readl(mmio_base + PDC_20621_SEQMASK); | |
811 | VPRINTK("mask == 0x%x\n", mask); | |
812 | ||
813 | if (mask == 0xffffffff) { | |
814 | VPRINTK("QUICK EXIT 2\n"); | |
815 | return IRQ_NONE; | |
816 | } | |
817 | mask &= 0xffff; /* only 16 tags possible */ | |
818 | if (!mask) { | |
819 | VPRINTK("QUICK EXIT 3\n"); | |
820 | return IRQ_NONE; | |
821 | } | |
822 | ||
823 | spin_lock(&host_set->lock); | |
824 | ||
825 | for (i = 1; i < 9; i++) { | |
826 | port_no = i - 1; | |
827 | if (port_no > 3) | |
828 | port_no -= 4; | |
829 | if (port_no >= host_set->n_ports) | |
830 | ap = NULL; | |
831 | else | |
832 | ap = host_set->ports[port_no]; | |
833 | tmp = mask & (1 << i); | |
834 | VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp); | |
c1389503 TH |
835 | if (tmp && ap && |
836 | !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) { | |
1da177e4 LT |
837 | struct ata_queued_cmd *qc; |
838 | ||
839 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
840 | if (qc && (!(qc->tf.ctl & ATA_NIEN))) | |
841 | handled += pdc20621_host_intr(ap, qc, (i > 4), | |
842 | mmio_base); | |
843 | } | |
844 | } | |
845 | ||
846 | spin_unlock(&host_set->lock); | |
847 | ||
848 | VPRINTK("mask == 0x%x\n", mask); | |
849 | ||
850 | VPRINTK("EXIT\n"); | |
851 | ||
852 | return IRQ_RETVAL(handled); | |
853 | } | |
854 | ||
855 | static void pdc_eng_timeout(struct ata_port *ap) | |
856 | { | |
857 | u8 drv_stat; | |
b8f6153e | 858 | struct ata_host_set *host_set = ap->host_set; |
1da177e4 | 859 | struct ata_queued_cmd *qc; |
b8f6153e | 860 | unsigned long flags; |
1da177e4 LT |
861 | |
862 | DPRINTK("ENTER\n"); | |
863 | ||
b8f6153e JG |
864 | spin_lock_irqsave(&host_set->lock, flags); |
865 | ||
1da177e4 LT |
866 | qc = ata_qc_from_tag(ap, ap->active_tag); |
867 | if (!qc) { | |
868 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", | |
869 | ap->id); | |
870 | goto out; | |
871 | } | |
872 | ||
873 | /* hack alert! We cannot use the supplied completion | |
874 | * function from inside the ->eh_strategy_handler() thread. | |
875 | * libata is the only user of ->eh_strategy_handler() in | |
876 | * any kernel, so the default scsi_done() assumes it is | |
877 | * not being called from the SCSI EH. | |
878 | */ | |
879 | qc->scsidone = scsi_finish_command; | |
880 | ||
881 | switch (qc->tf.protocol) { | |
882 | case ATA_PROT_DMA: | |
883 | case ATA_PROT_NODATA: | |
884 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); | |
a7dac447 | 885 | ata_qc_complete(qc, __ac_err_mask(ata_wait_idle(ap))); |
1da177e4 LT |
886 | break; |
887 | ||
888 | default: | |
889 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
890 | ||
891 | printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n", | |
892 | ap->id, qc->tf.command, drv_stat); | |
893 | ||
a7dac447 | 894 | ata_qc_complete(qc, ac_err_mask(drv_stat)); |
1da177e4 LT |
895 | break; |
896 | } | |
897 | ||
898 | out: | |
b8f6153e | 899 | spin_unlock_irqrestore(&host_set->lock, flags); |
1da177e4 LT |
900 | DPRINTK("EXIT\n"); |
901 | } | |
902 | ||
057ace5e | 903 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
904 | { |
905 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
906 | tf->protocol == ATA_PROT_NODATA); | |
907 | ata_tf_load(ap, tf); | |
908 | } | |
909 | ||
910 | ||
057ace5e | 911 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
912 | { |
913 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
914 | tf->protocol == ATA_PROT_NODATA); | |
915 | ata_exec_command(ap, tf); | |
916 | } | |
917 | ||
918 | ||
919 | static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base) | |
920 | { | |
921 | port->cmd_addr = base; | |
922 | port->data_addr = base; | |
923 | port->feature_addr = | |
924 | port->error_addr = base + 0x4; | |
925 | port->nsect_addr = base + 0x8; | |
926 | port->lbal_addr = base + 0xc; | |
927 | port->lbam_addr = base + 0x10; | |
928 | port->lbah_addr = base + 0x14; | |
929 | port->device_addr = base + 0x18; | |
930 | port->command_addr = | |
931 | port->status_addr = base + 0x1c; | |
932 | port->altstatus_addr = | |
933 | port->ctl_addr = base + 0x38; | |
934 | } | |
935 | ||
936 | ||
937 | #ifdef ATA_VERBOSE_DEBUG | |
8a60a071 | 938 | static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource, |
1da177e4 LT |
939 | u32 offset, u32 size) |
940 | { | |
941 | u32 window_size; | |
942 | u16 idx; | |
943 | u8 page_mask; | |
944 | long dist; | |
ea6ba10b | 945 | void __iomem *mmio = pe->mmio_base; |
1da177e4 | 946 | struct pdc_host_priv *hpriv = pe->private_data; |
ea6ba10b | 947 | void __iomem *dimm_mmio = hpriv->dimm_mmio; |
1da177e4 LT |
948 | |
949 | /* hard-code chip #0 */ | |
950 | mmio += PDC_CHIP0_OFS; | |
951 | ||
8a60a071 JG |
952 | page_mask = 0x00; |
953 | window_size = 0x2000 * 4; /* 32K byte uchar size */ | |
954 | idx = (u16) (offset / window_size); | |
1da177e4 LT |
955 | |
956 | writel(0x01, mmio + PDC_GENERAL_CTLR); | |
957 | readl(mmio + PDC_GENERAL_CTLR); | |
958 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
959 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
960 | ||
961 | offset -= (idx * window_size); | |
962 | idx++; | |
8a60a071 | 963 | dist = ((long) (window_size - (offset + size))) >= 0 ? size : |
1da177e4 | 964 | (long) (window_size - offset); |
8a60a071 | 965 | memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4), |
1da177e4 LT |
966 | dist); |
967 | ||
8a60a071 | 968 | psource += dist; |
1da177e4 LT |
969 | size -= dist; |
970 | for (; (long) size >= (long) window_size ;) { | |
971 | writel(0x01, mmio + PDC_GENERAL_CTLR); | |
972 | readl(mmio + PDC_GENERAL_CTLR); | |
973 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
974 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
8a60a071 | 975 | memcpy_fromio((char *) psource, (char *) (dimm_mmio), |
1da177e4 LT |
976 | window_size / 4); |
977 | psource += window_size; | |
978 | size -= window_size; | |
979 | idx ++; | |
980 | } | |
981 | ||
982 | if (size) { | |
983 | writel(0x01, mmio + PDC_GENERAL_CTLR); | |
984 | readl(mmio + PDC_GENERAL_CTLR); | |
985 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
986 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
8a60a071 | 987 | memcpy_fromio((char *) psource, (char *) (dimm_mmio), |
1da177e4 LT |
988 | size / 4); |
989 | } | |
990 | } | |
991 | #endif | |
992 | ||
993 | ||
8a60a071 | 994 | static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource, |
1da177e4 LT |
995 | u32 offset, u32 size) |
996 | { | |
997 | u32 window_size; | |
998 | u16 idx; | |
999 | u8 page_mask; | |
1000 | long dist; | |
ea6ba10b | 1001 | void __iomem *mmio = pe->mmio_base; |
1da177e4 | 1002 | struct pdc_host_priv *hpriv = pe->private_data; |
ea6ba10b | 1003 | void __iomem *dimm_mmio = hpriv->dimm_mmio; |
1da177e4 | 1004 | |
8a60a071 | 1005 | /* hard-code chip #0 */ |
1da177e4 LT |
1006 | mmio += PDC_CHIP0_OFS; |
1007 | ||
8a60a071 JG |
1008 | page_mask = 0x00; |
1009 | window_size = 0x2000 * 4; /* 32K byte uchar size */ | |
1da177e4 LT |
1010 | idx = (u16) (offset / window_size); |
1011 | ||
1012 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
1013 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
8a60a071 | 1014 | offset -= (idx * window_size); |
1da177e4 LT |
1015 | idx++; |
1016 | dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size : | |
1017 | (long) (window_size - offset); | |
a9afd7cd | 1018 | memcpy_toio(dimm_mmio + offset / 4, psource, dist); |
1da177e4 LT |
1019 | writel(0x01, mmio + PDC_GENERAL_CTLR); |
1020 | readl(mmio + PDC_GENERAL_CTLR); | |
1021 | ||
8a60a071 | 1022 | psource += dist; |
1da177e4 LT |
1023 | size -= dist; |
1024 | for (; (long) size >= (long) window_size ;) { | |
1025 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
1026 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
a9afd7cd | 1027 | memcpy_toio(dimm_mmio, psource, window_size / 4); |
1da177e4 LT |
1028 | writel(0x01, mmio + PDC_GENERAL_CTLR); |
1029 | readl(mmio + PDC_GENERAL_CTLR); | |
1030 | psource += window_size; | |
1031 | size -= window_size; | |
1032 | idx ++; | |
1033 | } | |
8a60a071 | 1034 | |
1da177e4 LT |
1035 | if (size) { |
1036 | writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR); | |
1037 | readl(mmio + PDC_DIMM_WINDOW_CTLR); | |
a9afd7cd | 1038 | memcpy_toio(dimm_mmio, psource, size / 4); |
1da177e4 LT |
1039 | writel(0x01, mmio + PDC_GENERAL_CTLR); |
1040 | readl(mmio + PDC_GENERAL_CTLR); | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | ||
8a60a071 | 1045 | static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device, |
1da177e4 LT |
1046 | u32 subaddr, u32 *pdata) |
1047 | { | |
ea6ba10b | 1048 | void __iomem *mmio = pe->mmio_base; |
1da177e4 | 1049 | u32 i2creg = 0; |
8a60a071 | 1050 | u32 status; |
1da177e4 LT |
1051 | u32 count =0; |
1052 | ||
1053 | /* hard-code chip #0 */ | |
1054 | mmio += PDC_CHIP0_OFS; | |
1055 | ||
1056 | i2creg |= device << 24; | |
1057 | i2creg |= subaddr << 16; | |
1058 | ||
1059 | /* Set the device and subaddress */ | |
1060 | writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET); | |
1061 | readl(mmio + PDC_I2C_ADDR_DATA_OFFSET); | |
1062 | ||
1063 | /* Write Control to perform read operation, mask int */ | |
8a60a071 | 1064 | writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT, |
1da177e4 LT |
1065 | mmio + PDC_I2C_CONTROL_OFFSET); |
1066 | ||
1067 | for (count = 0; count <= 1000; count ++) { | |
1068 | status = readl(mmio + PDC_I2C_CONTROL_OFFSET); | |
1069 | if (status & PDC_I2C_COMPLETE) { | |
1070 | status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET); | |
1071 | break; | |
1072 | } else if (count == 1000) | |
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | *pdata = (status >> 8) & 0x000000ff; | |
8a60a071 | 1077 | return 1; |
1da177e4 LT |
1078 | } |
1079 | ||
1080 | ||
1081 | static int pdc20621_detect_dimm(struct ata_probe_ent *pe) | |
1082 | { | |
1083 | u32 data=0 ; | |
8a60a071 | 1084 | if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, |
1da177e4 LT |
1085 | PDC_DIMM_SPD_SYSTEM_FREQ, &data)) { |
1086 | if (data == 100) | |
1087 | return 100; | |
1088 | } else | |
1089 | return 0; | |
8a60a071 | 1090 | |
1da177e4 | 1091 | if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) { |
8a60a071 | 1092 | if(data <= 0x75) |
1da177e4 LT |
1093 | return 133; |
1094 | } else | |
1095 | return 0; | |
8a60a071 | 1096 | |
1da177e4 LT |
1097 | return 0; |
1098 | } | |
1099 | ||
1100 | ||
1101 | static int pdc20621_prog_dimm0(struct ata_probe_ent *pe) | |
1102 | { | |
1103 | u32 spd0[50]; | |
1104 | u32 data = 0; | |
1105 | int size, i; | |
8a60a071 | 1106 | u8 bdimmsize; |
ea6ba10b | 1107 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
1108 | static const struct { |
1109 | unsigned int reg; | |
1110 | unsigned int ofs; | |
1111 | } pdc_i2c_read_data [] = { | |
8a60a071 | 1112 | { PDC_DIMM_SPD_TYPE, 11 }, |
1da177e4 | 1113 | { PDC_DIMM_SPD_FRESH_RATE, 12 }, |
8a60a071 | 1114 | { PDC_DIMM_SPD_COLUMN_NUM, 4 }, |
1da177e4 LT |
1115 | { PDC_DIMM_SPD_ATTRIBUTE, 21 }, |
1116 | { PDC_DIMM_SPD_ROW_NUM, 3 }, | |
1117 | { PDC_DIMM_SPD_BANK_NUM, 17 }, | |
1118 | { PDC_DIMM_SPD_MODULE_ROW, 5 }, | |
1119 | { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 }, | |
1120 | { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 }, | |
1121 | { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 }, | |
1122 | { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 }, | |
8a60a071 | 1123 | { PDC_DIMM_SPD_CAS_LATENCY, 18 }, |
1da177e4 LT |
1124 | }; |
1125 | ||
1126 | /* hard-code chip #0 */ | |
1127 | mmio += PDC_CHIP0_OFS; | |
1128 | ||
1129 | for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++) | |
1130 | pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, | |
8a60a071 | 1131 | pdc_i2c_read_data[i].reg, |
1da177e4 | 1132 | &spd0[pdc_i2c_read_data[i].ofs]); |
8a60a071 | 1133 | |
1da177e4 | 1134 | data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4); |
8a60a071 | 1135 | data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) | |
1da177e4 | 1136 | ((((spd0[27] + 9) / 10) - 1) << 8) ; |
8a60a071 JG |
1137 | data |= (((((spd0[29] > spd0[28]) |
1138 | ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10; | |
1da177e4 | 1139 | data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12; |
8a60a071 JG |
1140 | |
1141 | if (spd0[18] & 0x08) | |
1da177e4 LT |
1142 | data |= ((0x03) << 14); |
1143 | else if (spd0[18] & 0x04) | |
1144 | data |= ((0x02) << 14); | |
1145 | else if (spd0[18] & 0x01) | |
1146 | data |= ((0x01) << 14); | |
1147 | else | |
1148 | data |= (0 << 14); | |
1149 | ||
8a60a071 | 1150 | /* |
1da177e4 LT |
1151 | Calculate the size of bDIMMSize (power of 2) and |
1152 | merge the DIMM size by program start/end address. | |
1153 | */ | |
1154 | ||
1155 | bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3; | |
1156 | size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */ | |
1157 | data |= (((size / 16) - 1) << 16); | |
1158 | data |= (0 << 23); | |
1159 | data |= 8; | |
8a60a071 | 1160 | writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET); |
1da177e4 | 1161 | readl(mmio + PDC_DIMM0_CONTROL_OFFSET); |
8a60a071 | 1162 | return size; |
1da177e4 LT |
1163 | } |
1164 | ||
1165 | ||
1166 | static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe) | |
1167 | { | |
1168 | u32 data, spd0; | |
1169 | int error, i; | |
ea6ba10b | 1170 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
1171 | |
1172 | /* hard-code chip #0 */ | |
1173 | mmio += PDC_CHIP0_OFS; | |
1174 | ||
1175 | /* | |
1176 | Set To Default : DIMM Module Global Control Register (0x022259F1) | |
1177 | DIMM Arbitration Disable (bit 20) | |
1178 | DIMM Data/Control Output Driving Selection (bit12 - bit15) | |
1179 | Refresh Enable (bit 17) | |
1180 | */ | |
1181 | ||
8a60a071 | 1182 | data = 0x022259F1; |
1da177e4 LT |
1183 | writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET); |
1184 | readl(mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1185 | ||
1186 | /* Turn on for ECC */ | |
8a60a071 | 1187 | pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, |
1da177e4 LT |
1188 | PDC_DIMM_SPD_TYPE, &spd0); |
1189 | if (spd0 == 0x02) { | |
1190 | data |= (0x01 << 16); | |
1191 | writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1192 | readl(mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1193 | printk(KERN_ERR "Local DIMM ECC Enabled\n"); | |
1194 | } | |
1195 | ||
1196 | /* DIMM Initialization Select/Enable (bit 18/19) */ | |
1197 | data &= (~(1<<18)); | |
1198 | data |= (1<<19); | |
1199 | writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1200 | ||
8a60a071 | 1201 | error = 1; |
1da177e4 LT |
1202 | for (i = 1; i <= 10; i++) { /* polling ~5 secs */ |
1203 | data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET); | |
1204 | if (!(data & (1<<19))) { | |
1205 | error = 0; | |
8a60a071 | 1206 | break; |
1da177e4 LT |
1207 | } |
1208 | msleep(i*100); | |
1209 | } | |
1210 | return error; | |
1211 | } | |
8a60a071 | 1212 | |
1da177e4 LT |
1213 | |
1214 | static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe) | |
1215 | { | |
8a60a071 | 1216 | int speed, size, length; |
1da177e4 LT |
1217 | u32 addr,spd0,pci_status; |
1218 | u32 tmp=0; | |
1219 | u32 time_period=0; | |
1220 | u32 tcount=0; | |
1221 | u32 ticks=0; | |
1222 | u32 clock=0; | |
1223 | u32 fparam=0; | |
ea6ba10b | 1224 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
1225 | |
1226 | /* hard-code chip #0 */ | |
1227 | mmio += PDC_CHIP0_OFS; | |
1228 | ||
1229 | /* Initialize PLL based upon PCI Bus Frequency */ | |
1230 | ||
1231 | /* Initialize Time Period Register */ | |
1232 | writel(0xffffffff, mmio + PDC_TIME_PERIOD); | |
1233 | time_period = readl(mmio + PDC_TIME_PERIOD); | |
1234 | VPRINTK("Time Period Register (0x40): 0x%x\n", time_period); | |
1235 | ||
1236 | /* Enable timer */ | |
1237 | writel(0x00001a0, mmio + PDC_TIME_CONTROL); | |
1238 | readl(mmio + PDC_TIME_CONTROL); | |
1239 | ||
1240 | /* Wait 3 seconds */ | |
1241 | msleep(3000); | |
1242 | ||
8a60a071 | 1243 | /* |
1da177e4 LT |
1244 | When timer is enabled, counter is decreased every internal |
1245 | clock cycle. | |
1246 | */ | |
1247 | ||
1248 | tcount = readl(mmio + PDC_TIME_COUNTER); | |
1249 | VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount); | |
1250 | ||
8a60a071 | 1251 | /* |
1da177e4 LT |
1252 | If SX4 is on PCI-X bus, after 3 seconds, the timer counter |
1253 | register should be >= (0xffffffff - 3x10^8). | |
1254 | */ | |
1255 | if(tcount >= PCI_X_TCOUNT) { | |
1256 | ticks = (time_period - tcount); | |
1257 | VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks); | |
8a60a071 | 1258 | |
1da177e4 LT |
1259 | clock = (ticks / 300000); |
1260 | VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock); | |
8a60a071 | 1261 | |
1da177e4 LT |
1262 | clock = (clock * 33); |
1263 | VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock); | |
1264 | ||
1265 | /* PLL F Param (bit 22:16) */ | |
1266 | fparam = (1400000 / clock) - 2; | |
1267 | VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam); | |
8a60a071 | 1268 | |
1da177e4 LT |
1269 | /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */ |
1270 | pci_status = (0x8a001824 | (fparam << 16)); | |
1271 | } else | |
1272 | pci_status = PCI_PLL_INIT; | |
1273 | ||
1274 | /* Initialize PLL. */ | |
1275 | VPRINTK("pci_status: 0x%x\n", pci_status); | |
1276 | writel(pci_status, mmio + PDC_CTL_STATUS); | |
1277 | readl(mmio + PDC_CTL_STATUS); | |
1278 | ||
8a60a071 | 1279 | /* |
1da177e4 LT |
1280 | Read SPD of DIMM by I2C interface, |
1281 | and program the DIMM Module Controller. | |
1282 | */ | |
1283 | if (!(speed = pdc20621_detect_dimm(pe))) { | |
8a60a071 | 1284 | printk(KERN_ERR "Detect Local DIMM Fail\n"); |
1da177e4 LT |
1285 | return 1; /* DIMM error */ |
1286 | } | |
1287 | VPRINTK("Local DIMM Speed = %d\n", speed); | |
1288 | ||
8a60a071 | 1289 | /* Programming DIMM0 Module Control Register (index_CID0:80h) */ |
1da177e4 LT |
1290 | size = pdc20621_prog_dimm0(pe); |
1291 | VPRINTK("Local DIMM Size = %dMB\n",size); | |
1292 | ||
8a60a071 | 1293 | /* Programming DIMM Module Global Control Register (index_CID0:88h) */ |
1da177e4 LT |
1294 | if (pdc20621_prog_dimm_global(pe)) { |
1295 | printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n"); | |
1296 | return 1; | |
1297 | } | |
1298 | ||
1299 | #ifdef ATA_VERBOSE_DEBUG | |
1300 | { | |
1301 | u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ', | |
1302 | 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ', | |
1303 | '1','.','1','0', | |
1304 | '9','8','0','3','1','6','1','2',0,0}; | |
1305 | u8 test_parttern2[40] = {0}; | |
1306 | ||
1307 | pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40); | |
1308 | pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40); | |
1309 | ||
1310 | pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40); | |
1311 | pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40); | |
8a60a071 | 1312 | printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], |
1da177e4 | 1313 | test_parttern2[1], &(test_parttern2[2])); |
8a60a071 | 1314 | pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040, |
1da177e4 | 1315 | 40); |
8a60a071 | 1316 | printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], |
1da177e4 LT |
1317 | test_parttern2[1], &(test_parttern2[2])); |
1318 | ||
1319 | pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40); | |
1320 | pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40); | |
8a60a071 | 1321 | printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], |
1da177e4 LT |
1322 | test_parttern2[1], &(test_parttern2[2])); |
1323 | } | |
1324 | #endif | |
1325 | ||
1326 | /* ECC initiliazation. */ | |
1327 | ||
8a60a071 | 1328 | pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, |
1da177e4 LT |
1329 | PDC_DIMM_SPD_TYPE, &spd0); |
1330 | if (spd0 == 0x02) { | |
1331 | VPRINTK("Start ECC initialization\n"); | |
1332 | addr = 0; | |
1333 | length = size * 1024 * 1024; | |
1334 | while (addr < length) { | |
8a60a071 | 1335 | pdc20621_put_to_dimm(pe, (void *) &tmp, addr, |
1da177e4 LT |
1336 | sizeof(u32)); |
1337 | addr += sizeof(u32); | |
1338 | } | |
1339 | VPRINTK("Finish ECC initialization\n"); | |
1340 | } | |
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | ||
1345 | static void pdc_20621_init(struct ata_probe_ent *pe) | |
1346 | { | |
1347 | u32 tmp; | |
ea6ba10b | 1348 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
1349 | |
1350 | /* hard-code chip #0 */ | |
1351 | mmio += PDC_CHIP0_OFS; | |
1352 | ||
1353 | /* | |
1354 | * Select page 0x40 for our 32k DIMM window | |
1355 | */ | |
1356 | tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000; | |
1357 | tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */ | |
1358 | writel(tmp, mmio + PDC_20621_DIMM_WINDOW); | |
1359 | ||
1360 | /* | |
1361 | * Reset Host DMA | |
1362 | */ | |
1363 | tmp = readl(mmio + PDC_HDMA_CTLSTAT); | |
1364 | tmp |= PDC_RESET; | |
1365 | writel(tmp, mmio + PDC_HDMA_CTLSTAT); | |
1366 | readl(mmio + PDC_HDMA_CTLSTAT); /* flush */ | |
1367 | ||
1368 | udelay(10); | |
1369 | ||
1370 | tmp = readl(mmio + PDC_HDMA_CTLSTAT); | |
1371 | tmp &= ~PDC_RESET; | |
1372 | writel(tmp, mmio + PDC_HDMA_CTLSTAT); | |
1373 | readl(mmio + PDC_HDMA_CTLSTAT); /* flush */ | |
1374 | } | |
1375 | ||
1376 | static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1377 | { | |
1378 | static int printed_version; | |
1379 | struct ata_probe_ent *probe_ent = NULL; | |
1380 | unsigned long base; | |
ea6ba10b JG |
1381 | void __iomem *mmio_base; |
1382 | void __iomem *dimm_mmio = NULL; | |
1da177e4 LT |
1383 | struct pdc_host_priv *hpriv = NULL; |
1384 | unsigned int board_idx = (unsigned int) ent->driver_data; | |
1385 | int pci_dev_busy = 0; | |
1386 | int rc; | |
1387 | ||
1388 | if (!printed_version++) | |
a9524a76 | 1389 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
1390 | |
1391 | /* | |
1392 | * If this driver happens to only be useful on Apple's K2, then | |
1393 | * we should check that here as it has a normal Serverworks ID | |
1394 | */ | |
1395 | rc = pci_enable_device(pdev); | |
1396 | if (rc) | |
1397 | return rc; | |
1398 | ||
1399 | rc = pci_request_regions(pdev, DRV_NAME); | |
1400 | if (rc) { | |
1401 | pci_dev_busy = 1; | |
1402 | goto err_out; | |
1403 | } | |
1404 | ||
1405 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
1406 | if (rc) | |
1407 | goto err_out_regions; | |
1408 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1409 | if (rc) | |
1410 | goto err_out_regions; | |
1411 | ||
1412 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
1413 | if (probe_ent == NULL) { | |
1414 | rc = -ENOMEM; | |
1415 | goto err_out_regions; | |
1416 | } | |
1417 | ||
1418 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
1419 | probe_ent->dev = pci_dev_to_dev(pdev); | |
1420 | INIT_LIST_HEAD(&probe_ent->node); | |
1421 | ||
374b1873 | 1422 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
1423 | if (mmio_base == NULL) { |
1424 | rc = -ENOMEM; | |
1425 | goto err_out_free_ent; | |
1426 | } | |
1427 | base = (unsigned long) mmio_base; | |
1428 | ||
1429 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
1430 | if (!hpriv) { | |
1431 | rc = -ENOMEM; | |
1432 | goto err_out_iounmap; | |
1433 | } | |
1434 | memset(hpriv, 0, sizeof(*hpriv)); | |
1435 | ||
374b1873 | 1436 | dimm_mmio = pci_iomap(pdev, 4, 0); |
1da177e4 LT |
1437 | if (!dimm_mmio) { |
1438 | kfree(hpriv); | |
1439 | rc = -ENOMEM; | |
1440 | goto err_out_iounmap; | |
1441 | } | |
1442 | ||
1443 | hpriv->dimm_mmio = dimm_mmio; | |
1444 | ||
1445 | probe_ent->sht = pdc_port_info[board_idx].sht; | |
1446 | probe_ent->host_flags = pdc_port_info[board_idx].host_flags; | |
1447 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; | |
1448 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
1449 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
1450 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
1451 | ||
1452 | probe_ent->irq = pdev->irq; | |
1453 | probe_ent->irq_flags = SA_SHIRQ; | |
1454 | probe_ent->mmio_base = mmio_base; | |
1455 | ||
1456 | probe_ent->private_data = hpriv; | |
1457 | base += PDC_CHIP0_OFS; | |
1458 | ||
1459 | probe_ent->n_ports = 4; | |
1460 | pdc_sata_setup_port(&probe_ent->port[0], base + 0x200); | |
1461 | pdc_sata_setup_port(&probe_ent->port[1], base + 0x280); | |
1462 | pdc_sata_setup_port(&probe_ent->port[2], base + 0x300); | |
1463 | pdc_sata_setup_port(&probe_ent->port[3], base + 0x380); | |
1464 | ||
1465 | pci_set_master(pdev); | |
1466 | ||
1467 | /* initialize adapter */ | |
1468 | /* initialize local dimm */ | |
1469 | if (pdc20621_dimm_init(probe_ent)) { | |
1470 | rc = -ENOMEM; | |
1471 | goto err_out_iounmap_dimm; | |
1472 | } | |
1473 | pdc_20621_init(probe_ent); | |
1474 | ||
1475 | /* FIXME: check ata_device_add return value */ | |
1476 | ata_device_add(probe_ent); | |
1477 | kfree(probe_ent); | |
1478 | ||
1479 | return 0; | |
1480 | ||
1481 | err_out_iounmap_dimm: /* only get to this label if 20621 */ | |
1482 | kfree(hpriv); | |
374b1873 | 1483 | pci_iounmap(pdev, dimm_mmio); |
1da177e4 | 1484 | err_out_iounmap: |
374b1873 | 1485 | pci_iounmap(pdev, mmio_base); |
1da177e4 LT |
1486 | err_out_free_ent: |
1487 | kfree(probe_ent); | |
1488 | err_out_regions: | |
1489 | pci_release_regions(pdev); | |
1490 | err_out: | |
1491 | if (!pci_dev_busy) | |
1492 | pci_disable_device(pdev); | |
1493 | return rc; | |
1494 | } | |
1495 | ||
1496 | ||
1497 | static int __init pdc_sata_init(void) | |
1498 | { | |
1499 | return pci_module_init(&pdc_sata_pci_driver); | |
1500 | } | |
1501 | ||
1502 | ||
1503 | static void __exit pdc_sata_exit(void) | |
1504 | { | |
1505 | pci_unregister_driver(&pdc_sata_pci_driver); | |
1506 | } | |
1507 | ||
1508 | ||
1509 | MODULE_AUTHOR("Jeff Garzik"); | |
1510 | MODULE_DESCRIPTION("Promise SATA low-level driver"); | |
1511 | MODULE_LICENSE("GPL"); | |
1512 | MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl); | |
1513 | MODULE_VERSION(DRV_VERSION); | |
1514 | ||
1515 | module_init(pdc_sata_init); | |
1516 | module_exit(pdc_sata_exit); |