[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / sata_svw.c

/*
 *  sata_svw.c - ServerWorks / Apple K2 SATA
 *
 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
 *		   Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  This driver probably works with non-Apple versions of the
 *  Broadcom chipset...
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#ifdef CONFIG_PPC_OF
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif /* CONFIG_PPC_OF */

#define DRV_NAME	"sata_svw"
#define DRV_VERSION	"1.07"

/* Taskfile registers offsets */
#define K2_SATA_TF_CMD_OFFSET		0x00
#define K2_SATA_TF_DATA_OFFSET		0x00
#define K2_SATA_TF_ERROR_OFFSET		0x04
#define K2_SATA_TF_NSECT_OFFSET		0x08
#define K2_SATA_TF_LBAL_OFFSET		0x0c
#define K2_SATA_TF_LBAM_OFFSET		0x10
#define K2_SATA_TF_LBAH_OFFSET		0x14
#define K2_SATA_TF_DEVICE_OFFSET	0x18
#define K2_SATA_TF_CMDSTAT_OFFSET      	0x1c
#define K2_SATA_TF_CTL_OFFSET		0x20

/* DMA base */
#define K2_SATA_DMA_CMD_OFFSET		0x30

/* SCRs base */
#define K2_SATA_SCR_STATUS_OFFSET	0x40
#define K2_SATA_SCR_ERROR_OFFSET	0x44
#define K2_SATA_SCR_CONTROL_OFFSET	0x48

/* Others */
#define K2_SATA_SICR1_OFFSET		0x80
#define K2_SATA_SICR2_OFFSET		0x84
#define K2_SATA_SIM_OFFSET		0x88

/* Port stride */
#define K2_SATA_PORT_OFFSET		0x100

static u8 k2_stat_check_status(struct ata_port *ap);


static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;
	return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
			       u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;
	writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	if (tf->ctl != ap->last_ctl) {
		writeb(tf->ctl, ioaddr->ctl_addr);
		ap->last_ctl = tf->ctl;
		ata_wait_idle(ap);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = k2_stat_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
        }
}

/**
 *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host_set lock)
 */

static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	u8 dmactl;
	void *mmio = (void *) ap->ioaddr.bmdma_addr;
	/* load PRD table addr. */
	mb();	/* make sure PRD table writes are visible to controller */
	writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = readb(mmio + ATA_DMA_CMD);
	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
	if (!rw)
		dmactl |= ATA_DMA_WR;
	writeb(dmactl, mmio + ATA_DMA_CMD);

	/* issue r/w command if this is not a ATA DMA command*/
	if (qc->tf.protocol != ATA_PROT_DMA)
		ap->ops->exec_command(ap, &qc->tf);
}

/**
 *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host_set lock)
 */

static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void *mmio = (void *) ap->ioaddr.bmdma_addr;
	u8 dmactl;

	/* start host DMA transaction */
	dmactl = readb(mmio + ATA_DMA_CMD);
	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
	/* There is a race condition in certain SATA controllers that can
	   be seen when the r/w command is given to the controller before the
	   host DMA is started. On a Read command, the controller would initiate
	   the command to the drive even before it sees the DMA start. When there
	   are very fast drives connected to the controller, or when the data request
	   hits in the drive cache, there is the possibility that the drive returns a part
	   or all of the requested data to the controller before the DMA start is issued.
	   In this case, the controller would become confused as to what to do with the data.
	   In the worst case when all the data is returned back to the controller, the
	   controller could hang. In other cases it could return partial data returning
	   in data corruption. This problem has been seen in PPC systems and can also appear
	   on an system with very fast disks, where the SATA controller is sitting behind a
	   number of bridges, and hence there is significant latency between the r/w command
	   and the start command. */
	/* issue r/w command if the access is to ATA*/
	if (qc->tf.protocol == ATA_PROT_DMA)
		ap->ops->exec_command(ap, &qc->tf);
}


static u8 k2_stat_check_status(struct ata_port *ap)
{
       	return readl((void *) ap->ioaddr.status_addr);
}

#ifdef CONFIG_PPC_OF
/*
 * k2_sata_proc_info
 * inout : decides on the direction of the dataflow and the meaning of the
 *	   variables
 * buffer: If inout==FALSE data is being written to it else read from it
 * *start: If inout==FALSE start of the valid data in the buffer
 * offset: If inout==FALSE offset from the beginning of the imaginary file
 *	   from which we start writing into the buffer
 * length: If inout==FALSE max number of bytes to be written into the buffer
 *	   else number of bytes in the buffer
 */
static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
			     off_t offset, int count, int inout)
{
	struct ata_port *ap;
	struct device_node *np;
	int len, index;

	/* Find  the ata_port */
	ap = (struct ata_port *) &shost->hostdata[0];
	if (ap == NULL)
		return 0;

	/* Find the OF node for the PCI device proper */
	np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
	if (np == NULL)
		return 0;

	/* Match it to a port node */
	index = (ap == ap->host_set->ports[0]) ? 0 : 1;
	for (np = np->child; np != NULL; np = np->sibling) {
		u32 *reg = (u32 *)get_property(np, "reg", NULL);
		if (!reg)
			continue;
		if (index == *reg)
			break;
	}
	if (np == NULL)
		return 0;

	len = sprintf(page, "devspec: %s\n", np->full_name);

	return len;
}
#endif /* CONFIG_PPC_OF */


static struct scsi_host_template k2_sata_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.eh_timed_out		= ata_scsi_timed_out,
	.eh_strategy_handler	= ata_scsi_error,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
#ifdef CONFIG_PPC_OF
	.proc_info		= k2_sata_proc_info,
#endif
	.bios_param		= ata_std_bios_param,
};


static const struct ata_port_operations k2_sata_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= k2_sata_tf_load,
	.tf_read		= k2_sata_tf_read,
	.check_status		= k2_stat_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.bmdma_setup		= k2_bmdma_setup_mmio,
	.bmdma_start		= k2_bmdma_start_mmio,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= k2_sata_scr_read,
	.scr_write		= k2_sata_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_pci_host_stop,
};

static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
{
	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
	port->feature_addr	=
	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
	port->command_addr	=
	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
	port->altstatus_addr	=
	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
}


static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	void __iomem *mmio_base;
	int pci_dev_busy = 0;
	int rc;
	int i;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pci_enable_device(pdev);
	if (rc)
		return rc;
	/*
	 * Check if we have resources mapped at all (second function may
	 * have been disabled by firmware)
	 */
	if (pci_resource_len(pdev, 5) == 0)
		return -ENODEV;

	/* Request PCI regions */
	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	memset(probe_ent, 0, sizeof(*probe_ent));
	probe_ent->dev = pci_dev_to_dev(pdev);
	INIT_LIST_HEAD(&probe_ent->node);

	mmio_base = pci_iomap(pdev, 5, 0);
	if (mmio_base == NULL) {
		rc = -ENOMEM;
		goto err_out_free_ent;
	}
	base = (unsigned long) mmio_base;

	/* Clear a magic bit in SCR1 according to Darwin, those help
	 * some funky seagate drives (though so far, those were already
	 * set by the firmware on the machines I had access to)
	 */
	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	       mmio_base + K2_SATA_SICR1_OFFSET);

	/* Clear SATA error & interrupts we don't use */
	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

	probe_ent->sht = &k2_sata_sht;
	probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
				ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
	probe_ent->port_ops = &k2_sata_ops;
	probe_ent->n_ports = 4;
	probe_ent->irq = pdev->irq;
	probe_ent->irq_flags = SA_SHIRQ;
	probe_ent->mmio_base = mmio_base;

	/* We don't care much about the PIO/UDMA masks, but the core won't like us
	 * if we don't fill these
	 */
	probe_ent->pio_mask = 0x1f;
	probe_ent->mwdma_mask = 0x7;
	probe_ent->udma_mask = 0x7f;

	/* different controllers have different number of ports - currently 4 or 8 */
	/* All ports are on the same function. Multi-function device is no
	 * longer available. This should not be seen in any system. */
	for (i = 0; i < ent->driver_data; i++)
		k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);

	pci_set_master(pdev);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;
}

/* 0x240 is device ID for Apple K2 device
 * 0x241 is device ID for Serverworks Frodo4
 * 0x242 is device ID for Serverworks Frodo8
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 * controller
 * */
static const struct pci_device_id k2_sata_pci_tbl[] = {
	{ 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
	{ 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0x1166, 0x024b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ }
};


static struct pci_driver k2_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= k2_sata_pci_tbl,
	.probe			= k2_sata_init_one,
	.remove			= ata_pci_remove_one,
};


static int __init k2_sata_init(void)
{
	return pci_module_init(&k2_sata_pci_driver);
}


static void __exit k2_sata_exit(void)
{
	pci_unregister_driver(&k2_sata_pci_driver);
}


MODULE_AUTHOR("Benjamin Herrenschmidt");
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(k2_sata_init);
module_exit(k2_sata_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_svw.c - ServerWorks / Apple K2 SATA
	3	*
	4	* Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
	5	* Jeff Garzik <jgarzik@pobox.com>
	6	* Please ALWAYS copy linux-ide@vger.kernel.org
	7	* on emails.
	8	*
	9	* Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
	10	*
	11	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	12	*
	13	* This driver probably works with non-Apple versions of the
	14	* Broadcom chipset...
	15	*
af36d7f0 JG	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License as published by
	19	* the Free Software Foundation; either version 2, or (at your option)
	20	* any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; see the file COPYING. If not, write to
	29	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	30	*
	31	*
	32	* libata documentation is available via 'make {ps\|pdf}docs',
	33	* as Documentation/DocBook/libata.*
	34	*
	35	* Hardware documentation available under NDA.
1da177e4 LT	36	*
	37	*/
	38
	39	#include <linux/config.h>
	40	#include <linux/kernel.h>
	41	#include <linux/module.h>
	42	#include <linux/pci.h>
	43	#include <linux/init.h>
	44	#include <linux/blkdev.h>
	45	#include <linux/delay.h>
	46	#include <linux/interrupt.h>
a9524a76	47	#include <linux/device.h>
1da177e4 LT	48	#include <scsi/scsi_host.h>
	49	#include <linux/libata.h>
	50
	51	#ifdef CONFIG_PPC_OF
	52	#include <asm/prom.h>
	53	#include <asm/pci-bridge.h>
	54	#endif /* CONFIG_PPC_OF */
	55
	56	#define DRV_NAME "sata_svw"
7bdd7208	57	#define DRV_VERSION "1.07"
1da177e4 LT	58
	59	/* Taskfile registers offsets */
	60	#define K2_SATA_TF_CMD_OFFSET 0x00
	61	#define K2_SATA_TF_DATA_OFFSET 0x00
	62	#define K2_SATA_TF_ERROR_OFFSET 0x04
	63	#define K2_SATA_TF_NSECT_OFFSET 0x08
	64	#define K2_SATA_TF_LBAL_OFFSET 0x0c
	65	#define K2_SATA_TF_LBAM_OFFSET 0x10
	66	#define K2_SATA_TF_LBAH_OFFSET 0x14
	67	#define K2_SATA_TF_DEVICE_OFFSET 0x18
	68	#define K2_SATA_TF_CMDSTAT_OFFSET 0x1c
	69	#define K2_SATA_TF_CTL_OFFSET 0x20
	70
	71	/* DMA base */
	72	#define K2_SATA_DMA_CMD_OFFSET 0x30
	73
	74	/* SCRs base */
	75	#define K2_SATA_SCR_STATUS_OFFSET 0x40
	76	#define K2_SATA_SCR_ERROR_OFFSET 0x44
	77	#define K2_SATA_SCR_CONTROL_OFFSET 0x48
	78
	79	/* Others */
	80	#define K2_SATA_SICR1_OFFSET 0x80
	81	#define K2_SATA_SICR2_OFFSET 0x84
	82	#define K2_SATA_SIM_OFFSET 0x88
	83
	84	/* Port stride */
	85	#define K2_SATA_PORT_OFFSET 0x100
	86
ac19bff2 JG	87	static u8 k2_stat_check_status(struct ata_port *ap);
ac19bff2 JG	88
1da177e4 LT	89
	90	static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
	91	{
	92	if (sc_reg > SCR_CONTROL)
	93	return 0xffffffffU;
	94	return readl((void ) ap->ioaddr.scr_addr + (sc_reg 4));
	95	}
	96
	97
	98	static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
	99	u32 val)
	100	{
	101	if (sc_reg > SCR_CONTROL)
	102	return;
	103	writel(val, (void ) ap->ioaddr.scr_addr + (sc_reg 4));
	104	}
	105
	106
057ace5e	107	static void k2_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	108	{
	109	struct ata_ioports *ioaddr = &ap->ioaddr;
	110	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	111
	112	if (tf->ctl != ap->last_ctl) {
	113	writeb(tf->ctl, ioaddr->ctl_addr);
	114	ap->last_ctl = tf->ctl;
	115	ata_wait_idle(ap);
	116	}
	117	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
	118	writew(tf->feature \| (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
	119	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
	120	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
	121	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
	122	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
	123	} else if (is_addr) {
	124	writew(tf->feature, ioaddr->feature_addr);
	125	writew(tf->nsect, ioaddr->nsect_addr);
	126	writew(tf->lbal, ioaddr->lbal_addr);
	127	writew(tf->lbam, ioaddr->lbam_addr);
	128	writew(tf->lbah, ioaddr->lbah_addr);
	129	}
	130
	131	if (tf->flags & ATA_TFLAG_DEVICE)
	132	writeb(tf->device, ioaddr->device_addr);
	133
	134	ata_wait_idle(ap);
	135	}
	136
	137
	138	static void k2_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	139	{
	140	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	141	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	142
ac19bff2	143	tf->command = k2_stat_check_status(ap);
1da177e4	144	tf->device = readw(ioaddr->device_addr);
ac19bff2 JG	145	feature = readw(ioaddr->error_addr);
	146	nsect = readw(ioaddr->nsect_addr);
	147	lbal = readw(ioaddr->lbal_addr);
	148	lbam = readw(ioaddr->lbam_addr);
	149	lbah = readw(ioaddr->lbah_addr);
	150
	151	tf->feature = feature;
	152	tf->nsect = nsect;
	153	tf->lbal = lbal;
	154	tf->lbam = lbam;
	155	tf->lbah = lbah;
1da177e4 LT	156
1da177e4 LT	157	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	158	tf->hob_feature = feature >> 8;
1da177e4 LT	159	tf->hob_nsect = nsect >> 8;
	160	tf->hob_lbal = lbal >> 8;
	161	tf->hob_lbam = lbam >> 8;
	162	tf->hob_lbah = lbah >> 8;
	163	}
	164	}
	165
	166	/**
	167	* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
	168	* @qc: Info associated with this ATA transaction.
	169	*
	170	* LOCKING:
	171	* spin_lock_irqsave(host_set lock)
	172	*/
	173
	174	static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
	175	{
	176	struct ata_port *ap = qc->ap;
	177	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	178	u8 dmactl;
	179	void mmio = (void ) ap->ioaddr.bmdma_addr;
	180	/* load PRD table addr. */
	181	mb(); /* make sure PRD table writes are visible to controller */
	182	writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
	183
	184	/* specify data direction, triple-check start bit is clear */
	185	dmactl = readb(mmio + ATA_DMA_CMD);
	186	dmactl &= ~(ATA_DMA_WR \| ATA_DMA_START);
	187	if (!rw)
	188	dmactl \|= ATA_DMA_WR;
	189	writeb(dmactl, mmio + ATA_DMA_CMD);
	190
	191	/* issue r/w command if this is not a ATA DMA command*/
	192	if (qc->tf.protocol != ATA_PROT_DMA)
	193	ap->ops->exec_command(ap, &qc->tf);
	194	}
	195
	196	/**
	197	* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
	198	* @qc: Info associated with this ATA transaction.
	199	*
	200	* LOCKING:
	201	* spin_lock_irqsave(host_set lock)
	202	*/
	203
	204	static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
	205	{
	206	struct ata_port *ap = qc->ap;
	207	void mmio = (void ) ap->ioaddr.bmdma_addr;
	208	u8 dmactl;
	209
	210	/* start host DMA transaction */
	211	dmactl = readb(mmio + ATA_DMA_CMD);
	212	writeb(dmactl \| ATA_DMA_START, mmio + ATA_DMA_CMD);
8a60a071 JG	213	/* There is a race condition in certain SATA controllers that can
8a60a071 JG	214	be seen when the r/w command is given to the controller before the
1da177e4 LT	215	host DMA is started. On a Read command, the controller would initiate
1da177e4 LT	216	the command to the drive even before it sees the DMA start. When there
8a60a071	217	are very fast drives connected to the controller, or when the data request
1da177e4 LT	218	hits in the drive cache, there is the possibility that the drive returns a part
	219	or all of the requested data to the controller before the DMA start is issued.
	220	In this case, the controller would become confused as to what to do with the data.
	221	In the worst case when all the data is returned back to the controller, the
	222	controller could hang. In other cases it could return partial data returning
	223	in data corruption. This problem has been seen in PPC systems and can also appear
8a60a071	224	on an system with very fast disks, where the SATA controller is sitting behind a
1da177e4 LT	225	number of bridges, and hence there is significant latency between the r/w command
	226	and the start command. */
	227	/* issue r/w command if the access is to ATA*/
	228	if (qc->tf.protocol == ATA_PROT_DMA)
	229	ap->ops->exec_command(ap, &qc->tf);
	230	}
	231
8a60a071	232
1da177e4 LT	233	static u8 k2_stat_check_status(struct ata_port *ap)
	234	{
	235	return readl((void *) ap->ioaddr.status_addr);
	236	}
	237
	238	#ifdef CONFIG_PPC_OF
	239	/*
	240	* k2_sata_proc_info
	241	* inout : decides on the direction of the dataflow and the meaning of the
	242	* variables
	243	* buffer: If inout==FALSE data is being written to it else read from it
	244	* *start: If inout==FALSE start of the valid data in the buffer
	245	* offset: If inout==FALSE offset from the beginning of the imaginary file
	246	* from which we start writing into the buffer
	247	* length: If inout==FALSE max number of bytes to be written into the buffer
	248	* else number of bytes in the buffer
	249	*/
	250	static int k2_sata_proc_info(struct Scsi_Host shost, char page, char **start,
	251	off_t offset, int count, int inout)
	252	{
	253	struct ata_port *ap;
	254	struct device_node *np;
	255	int len, index;
	256
	257	/* Find the ata_port */
	258	ap = (struct ata_port *) &shost->hostdata[0];
	259	if (ap == NULL)
	260	return 0;
	261
	262	/* Find the OF node for the PCI device proper */
	263	np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
	264	if (np == NULL)
	265	return 0;
	266
	267	/* Match it to a port node */
	268	index = (ap == ap->host_set->ports[0]) ? 0 : 1;
	269	for (np = np->child; np != NULL; np = np->sibling) {
	270	u32 reg = (u32 )get_property(np, "reg", NULL);
	271	if (!reg)
	272	continue;
	273	if (index == *reg)
	274	break;
	275	}
	276	if (np == NULL)
	277	return 0;
	278
	279	len = sprintf(page, "devspec: %s\n", np->full_name);
	280
	281	return len;
	282	}
	283	#endif /* CONFIG_PPC_OF */
	284
	285
193515d5	286	static struct scsi_host_template k2_sata_sht = {
1da177e4 LT	287	.module = THIS_MODULE,
	288	.name = DRV_NAME,
	289	.ioctl = ata_scsi_ioctl,
	290	.queuecommand = ata_scsi_queuecmd,
35daeb8f	291	.eh_timed_out = ata_scsi_timed_out,
1da177e4 LT	292	.eh_strategy_handler = ata_scsi_error,
	293	.can_queue = ATA_DEF_QUEUE,
	294	.this_id = ATA_SHT_THIS_ID,
	295	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	296	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	297	.emulated = ATA_SHT_EMULATED,
	298	.use_clustering = ATA_SHT_USE_CLUSTERING,
	299	.proc_name = DRV_NAME,
	300	.dma_boundary = ATA_DMA_BOUNDARY,
	301	.slave_configure = ata_scsi_slave_config,
	302	#ifdef CONFIG_PPC_OF
	303	.proc_info = k2_sata_proc_info,
	304	#endif
	305	.bios_param = ata_std_bios_param,
1da177e4 LT	306	};
	307
	308
057ace5e	309	static const struct ata_port_operations k2_sata_ops = {
1da177e4 LT	310	.port_disable = ata_port_disable,
	311	.tf_load = k2_sata_tf_load,
	312	.tf_read = k2_sata_tf_read,
	313	.check_status = k2_stat_check_status,
	314	.exec_command = ata_exec_command,
	315	.dev_select = ata_std_dev_select,
	316	.phy_reset = sata_phy_reset,
	317	.bmdma_setup = k2_bmdma_setup_mmio,
	318	.bmdma_start = k2_bmdma_start_mmio,
	319	.bmdma_stop = ata_bmdma_stop,
	320	.bmdma_status = ata_bmdma_status,
	321	.qc_prep = ata_qc_prep,
	322	.qc_issue = ata_qc_issue_prot,
	323	.eng_timeout = ata_eng_timeout,
	324	.irq_handler = ata_interrupt,
	325	.irq_clear = ata_bmdma_irq_clear,
	326	.scr_read = k2_sata_scr_read,
	327	.scr_write = k2_sata_scr_write,
	328	.port_start = ata_port_start,
	329	.port_stop = ata_port_stop,
374b1873	330	.host_stop = ata_pci_host_stop,
1da177e4 LT	331	};
	332
	333	static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
	334	{
	335	port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
	336	port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
	337	port->feature_addr =
	338	port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
	339	port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
	340	port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
	341	port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
	342	port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
	343	port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
	344	port->command_addr =
	345	port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
	346	port->altstatus_addr =
	347	port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
	348	port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
	349	port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
	350	}
	351
	352
	353	static int k2_sata_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	354	{
	355	static int printed_version;
	356	struct ata_probe_ent *probe_ent = NULL;
	357	unsigned long base;
ea6ba10b	358	void __iomem *mmio_base;
1da177e4 LT	359	int pci_dev_busy = 0;
1da177e4 LT	360	int rc;
60bf09a3	361	int i;
1da177e4 LT	362
1da177e4 LT	363	if (!printed_version++)
a9524a76	364	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 LT	365
	366	/*
	367	* If this driver happens to only be useful on Apple's K2, then
	368	* we should check that here as it has a normal Serverworks ID
	369	*/
	370	rc = pci_enable_device(pdev);
	371	if (rc)
	372	return rc;
	373	/*
	374	* Check if we have resources mapped at all (second function may
	375	* have been disabled by firmware)
	376	*/
	377	if (pci_resource_len(pdev, 5) == 0)
	378	return -ENODEV;
	379
	380	/* Request PCI regions */
	381	rc = pci_request_regions(pdev, DRV_NAME);
	382	if (rc) {
	383	pci_dev_busy = 1;
	384	goto err_out;
	385	}
	386
	387	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	388	if (rc)
	389	goto err_out_regions;
	390	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	391	if (rc)
	392	goto err_out_regions;
	393
	394	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	395	if (probe_ent == NULL) {
	396	rc = -ENOMEM;
	397	goto err_out_regions;
	398	}
	399
	400	memset(probe_ent, 0, sizeof(*probe_ent));
	401	probe_ent->dev = pci_dev_to_dev(pdev);
	402	INIT_LIST_HEAD(&probe_ent->node);
	403
374b1873	404	mmio_base = pci_iomap(pdev, 5, 0);
1da177e4 LT	405	if (mmio_base == NULL) {
	406	rc = -ENOMEM;
	407	goto err_out_free_ent;
	408	}
	409	base = (unsigned long) mmio_base;
	410
	411	/* Clear a magic bit in SCR1 according to Darwin, those help
	412	* some funky seagate drives (though so far, those were already
104e5010	413	* set by the firmware on the machines I had access to)
1da177e4 LT	414	*/
	415	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	416	mmio_base + K2_SATA_SICR1_OFFSET);
	417
	418	/* Clear SATA error & interrupts we don't use */
	419	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	420	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
	421
	422	probe_ent->sht = &k2_sata_sht;
	423	probe_ent->host_flags = ATA_FLAG_SATA \| ATA_FLAG_SATA_RESET \|
	424	ATA_FLAG_NO_LEGACY \| ATA_FLAG_MMIO;
	425	probe_ent->port_ops = &k2_sata_ops;
	426	probe_ent->n_ports = 4;
	427	probe_ent->irq = pdev->irq;
	428	probe_ent->irq_flags = SA_SHIRQ;
	429	probe_ent->mmio_base = mmio_base;
	430
	431	/* We don't care much about the PIO/UDMA masks, but the core won't like us
	432	* if we don't fill these
	433	*/
	434	probe_ent->pio_mask = 0x1f;
	435	probe_ent->mwdma_mask = 0x7;
	436	probe_ent->udma_mask = 0x7f;
	437
60bf09a3 NS	438	/* different controllers have different number of ports - currently 4 or 8 */
	439	/* All ports are on the same function. Multi-function device is no
	440	* longer available. This should not be seen in any system. */
	441	for (i = 0; i < ent->driver_data; i++)
	442	k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);
1da177e4 LT	443
	444	pci_set_master(pdev);
	445
	446	/* FIXME: check ata_device_add return value */
	447	ata_device_add(probe_ent);
	448	kfree(probe_ent);
	449
	450	return 0;
	451
	452	err_out_free_ent:
	453	kfree(probe_ent);
	454	err_out_regions:
	455	pci_release_regions(pdev);
	456	err_out:
	457	if (!pci_dev_busy)
	458	pci_disable_device(pdev);
	459	return rc;
	460	}
	461
60bf09a3 NS	462	/* 0x240 is device ID for Apple K2 device
	463	* 0x241 is device ID for Serverworks Frodo4
	464	* 0x242 is device ID for Serverworks Frodo8
	465	* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
	466	* controller
	467	* */
3b7d697d	468	static const struct pci_device_id k2_sata_pci_tbl[] = {
60bf09a3 NS	469	{ 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	470	{ 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	471	{ 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
	472	{ 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
88b52877	473	{ 0x1166, 0x024b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
1da177e4 LT	474	{ }
	475	};
	476
	477
	478	static struct pci_driver k2_sata_pci_driver = {
	479	.name = DRV_NAME,
	480	.id_table = k2_sata_pci_tbl,
	481	.probe = k2_sata_init_one,
	482	.remove = ata_pci_remove_one,
	483	};
	484
	485
	486	static int __init k2_sata_init(void)
	487	{
	488	return pci_module_init(&k2_sata_pci_driver);
	489	}
	490
	491
	492	static void __exit k2_sata_exit(void)
	493	{
	494	pci_unregister_driver(&k2_sata_pci_driver);
	495	}
	496
	497
	498	MODULE_AUTHOR("Benjamin Herrenschmidt");
	499	MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
	500	MODULE_LICENSE("GPL");
	501	MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
	502	MODULE_VERSION(DRV_VERSION);
	503
	504	module_init(k2_sata_init);
	505	module_exit(k2_sata_exit);