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1da177e4 LT |
1 | /* |
2 | * sata_svw.c - ServerWorks / Apple K2 SATA | |
3 | * | |
4 | * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and | |
5 | * Jeff Garzik <jgarzik@pobox.com> | |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org> | |
10 | * | |
11 | * Bits from Jeff Garzik, Copyright RedHat, Inc. | |
12 | * | |
13 | * This driver probably works with non-Apple versions of the | |
14 | * Broadcom chipset... | |
15 | * | |
af36d7f0 JG |
16 | * |
17 | * This program is free software; you can redistribute it and/or modify | |
18 | * it under the terms of the GNU General Public License as published by | |
19 | * the Free Software Foundation; either version 2, or (at your option) | |
20 | * any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; see the file COPYING. If not, write to | |
29 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | * | |
32 | * libata documentation is available via 'make {ps|pdf}docs', | |
33 | * as Documentation/DocBook/libata.* | |
34 | * | |
35 | * Hardware documentation available under NDA. | |
1da177e4 LT |
36 | * |
37 | */ | |
38 | ||
39 | #include <linux/config.h> | |
40 | #include <linux/kernel.h> | |
41 | #include <linux/module.h> | |
42 | #include <linux/pci.h> | |
43 | #include <linux/init.h> | |
44 | #include <linux/blkdev.h> | |
45 | #include <linux/delay.h> | |
46 | #include <linux/interrupt.h> | |
a9524a76 | 47 | #include <linux/device.h> |
1da177e4 LT |
48 | #include <scsi/scsi_host.h> |
49 | #include <linux/libata.h> | |
50 | ||
51 | #ifdef CONFIG_PPC_OF | |
52 | #include <asm/prom.h> | |
53 | #include <asm/pci-bridge.h> | |
54 | #endif /* CONFIG_PPC_OF */ | |
55 | ||
56 | #define DRV_NAME "sata_svw" | |
af64371a | 57 | #define DRV_VERSION "1.8" |
1da177e4 | 58 | |
55cca65e JG |
59 | enum { |
60 | /* Taskfile registers offsets */ | |
61 | K2_SATA_TF_CMD_OFFSET = 0x00, | |
62 | K2_SATA_TF_DATA_OFFSET = 0x00, | |
63 | K2_SATA_TF_ERROR_OFFSET = 0x04, | |
64 | K2_SATA_TF_NSECT_OFFSET = 0x08, | |
65 | K2_SATA_TF_LBAL_OFFSET = 0x0c, | |
66 | K2_SATA_TF_LBAM_OFFSET = 0x10, | |
67 | K2_SATA_TF_LBAH_OFFSET = 0x14, | |
68 | K2_SATA_TF_DEVICE_OFFSET = 0x18, | |
69 | K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, | |
70 | K2_SATA_TF_CTL_OFFSET = 0x20, | |
1da177e4 | 71 | |
55cca65e JG |
72 | /* DMA base */ |
73 | K2_SATA_DMA_CMD_OFFSET = 0x30, | |
1da177e4 | 74 | |
55cca65e JG |
75 | /* SCRs base */ |
76 | K2_SATA_SCR_STATUS_OFFSET = 0x40, | |
77 | K2_SATA_SCR_ERROR_OFFSET = 0x44, | |
78 | K2_SATA_SCR_CONTROL_OFFSET = 0x48, | |
1da177e4 | 79 | |
55cca65e JG |
80 | /* Others */ |
81 | K2_SATA_SICR1_OFFSET = 0x80, | |
82 | K2_SATA_SICR2_OFFSET = 0x84, | |
83 | K2_SATA_SIM_OFFSET = 0x88, | |
1da177e4 | 84 | |
55cca65e JG |
85 | /* Port stride */ |
86 | K2_SATA_PORT_OFFSET = 0x100, | |
87 | }; | |
1da177e4 | 88 | |
ac19bff2 JG |
89 | static u8 k2_stat_check_status(struct ata_port *ap); |
90 | ||
1da177e4 LT |
91 | |
92 | static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
93 | { | |
94 | if (sc_reg > SCR_CONTROL) | |
95 | return 0xffffffffU; | |
96 | return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4)); | |
97 | } | |
98 | ||
99 | ||
100 | static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
101 | u32 val) | |
102 | { | |
103 | if (sc_reg > SCR_CONTROL) | |
104 | return; | |
105 | writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4)); | |
106 | } | |
107 | ||
108 | ||
057ace5e | 109 | static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
110 | { |
111 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
112 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
113 | ||
114 | if (tf->ctl != ap->last_ctl) { | |
115 | writeb(tf->ctl, ioaddr->ctl_addr); | |
116 | ap->last_ctl = tf->ctl; | |
117 | ata_wait_idle(ap); | |
118 | } | |
119 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
120 | writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr); | |
121 | writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr); | |
122 | writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr); | |
123 | writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr); | |
124 | writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr); | |
125 | } else if (is_addr) { | |
126 | writew(tf->feature, ioaddr->feature_addr); | |
127 | writew(tf->nsect, ioaddr->nsect_addr); | |
128 | writew(tf->lbal, ioaddr->lbal_addr); | |
129 | writew(tf->lbam, ioaddr->lbam_addr); | |
130 | writew(tf->lbah, ioaddr->lbah_addr); | |
131 | } | |
132 | ||
133 | if (tf->flags & ATA_TFLAG_DEVICE) | |
134 | writeb(tf->device, ioaddr->device_addr); | |
135 | ||
136 | ata_wait_idle(ap); | |
137 | } | |
138 | ||
139 | ||
140 | static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
141 | { | |
142 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
ac19bff2 | 143 | u16 nsect, lbal, lbam, lbah, feature; |
1da177e4 | 144 | |
ac19bff2 | 145 | tf->command = k2_stat_check_status(ap); |
1da177e4 | 146 | tf->device = readw(ioaddr->device_addr); |
ac19bff2 JG |
147 | feature = readw(ioaddr->error_addr); |
148 | nsect = readw(ioaddr->nsect_addr); | |
149 | lbal = readw(ioaddr->lbal_addr); | |
150 | lbam = readw(ioaddr->lbam_addr); | |
151 | lbah = readw(ioaddr->lbah_addr); | |
152 | ||
153 | tf->feature = feature; | |
154 | tf->nsect = nsect; | |
155 | tf->lbal = lbal; | |
156 | tf->lbam = lbam; | |
157 | tf->lbah = lbah; | |
1da177e4 LT |
158 | |
159 | if (tf->flags & ATA_TFLAG_LBA48) { | |
ac19bff2 | 160 | tf->hob_feature = feature >> 8; |
1da177e4 LT |
161 | tf->hob_nsect = nsect >> 8; |
162 | tf->hob_lbal = lbal >> 8; | |
163 | tf->hob_lbam = lbam >> 8; | |
164 | tf->hob_lbah = lbah >> 8; | |
165 | } | |
166 | } | |
167 | ||
168 | /** | |
169 | * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) | |
170 | * @qc: Info associated with this ATA transaction. | |
171 | * | |
172 | * LOCKING: | |
173 | * spin_lock_irqsave(host_set lock) | |
174 | */ | |
175 | ||
176 | static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc) | |
177 | { | |
178 | struct ata_port *ap = qc->ap; | |
179 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
180 | u8 dmactl; | |
181 | void *mmio = (void *) ap->ioaddr.bmdma_addr; | |
182 | /* load PRD table addr. */ | |
183 | mb(); /* make sure PRD table writes are visible to controller */ | |
184 | writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS); | |
185 | ||
186 | /* specify data direction, triple-check start bit is clear */ | |
187 | dmactl = readb(mmio + ATA_DMA_CMD); | |
188 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
189 | if (!rw) | |
190 | dmactl |= ATA_DMA_WR; | |
191 | writeb(dmactl, mmio + ATA_DMA_CMD); | |
192 | ||
193 | /* issue r/w command if this is not a ATA DMA command*/ | |
194 | if (qc->tf.protocol != ATA_PROT_DMA) | |
195 | ap->ops->exec_command(ap, &qc->tf); | |
196 | } | |
197 | ||
198 | /** | |
199 | * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) | |
200 | * @qc: Info associated with this ATA transaction. | |
201 | * | |
202 | * LOCKING: | |
203 | * spin_lock_irqsave(host_set lock) | |
204 | */ | |
205 | ||
206 | static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc) | |
207 | { | |
208 | struct ata_port *ap = qc->ap; | |
209 | void *mmio = (void *) ap->ioaddr.bmdma_addr; | |
210 | u8 dmactl; | |
211 | ||
212 | /* start host DMA transaction */ | |
213 | dmactl = readb(mmio + ATA_DMA_CMD); | |
214 | writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); | |
8a60a071 JG |
215 | /* There is a race condition in certain SATA controllers that can |
216 | be seen when the r/w command is given to the controller before the | |
1da177e4 LT |
217 | host DMA is started. On a Read command, the controller would initiate |
218 | the command to the drive even before it sees the DMA start. When there | |
8a60a071 | 219 | are very fast drives connected to the controller, or when the data request |
1da177e4 LT |
220 | hits in the drive cache, there is the possibility that the drive returns a part |
221 | or all of the requested data to the controller before the DMA start is issued. | |
222 | In this case, the controller would become confused as to what to do with the data. | |
223 | In the worst case when all the data is returned back to the controller, the | |
224 | controller could hang. In other cases it could return partial data returning | |
225 | in data corruption. This problem has been seen in PPC systems and can also appear | |
8a60a071 | 226 | on an system with very fast disks, where the SATA controller is sitting behind a |
1da177e4 LT |
227 | number of bridges, and hence there is significant latency between the r/w command |
228 | and the start command. */ | |
229 | /* issue r/w command if the access is to ATA*/ | |
230 | if (qc->tf.protocol == ATA_PROT_DMA) | |
231 | ap->ops->exec_command(ap, &qc->tf); | |
232 | } | |
233 | ||
8a60a071 | 234 | |
1da177e4 LT |
235 | static u8 k2_stat_check_status(struct ata_port *ap) |
236 | { | |
237 | return readl((void *) ap->ioaddr.status_addr); | |
238 | } | |
239 | ||
240 | #ifdef CONFIG_PPC_OF | |
241 | /* | |
242 | * k2_sata_proc_info | |
243 | * inout : decides on the direction of the dataflow and the meaning of the | |
244 | * variables | |
245 | * buffer: If inout==FALSE data is being written to it else read from it | |
246 | * *start: If inout==FALSE start of the valid data in the buffer | |
247 | * offset: If inout==FALSE offset from the beginning of the imaginary file | |
248 | * from which we start writing into the buffer | |
249 | * length: If inout==FALSE max number of bytes to be written into the buffer | |
250 | * else number of bytes in the buffer | |
251 | */ | |
252 | static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start, | |
253 | off_t offset, int count, int inout) | |
254 | { | |
255 | struct ata_port *ap; | |
256 | struct device_node *np; | |
257 | int len, index; | |
258 | ||
259 | /* Find the ata_port */ | |
260 | ap = (struct ata_port *) &shost->hostdata[0]; | |
261 | if (ap == NULL) | |
262 | return 0; | |
263 | ||
264 | /* Find the OF node for the PCI device proper */ | |
265 | np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev)); | |
266 | if (np == NULL) | |
267 | return 0; | |
268 | ||
269 | /* Match it to a port node */ | |
270 | index = (ap == ap->host_set->ports[0]) ? 0 : 1; | |
271 | for (np = np->child; np != NULL; np = np->sibling) { | |
272 | u32 *reg = (u32 *)get_property(np, "reg", NULL); | |
273 | if (!reg) | |
274 | continue; | |
275 | if (index == *reg) | |
276 | break; | |
277 | } | |
278 | if (np == NULL) | |
279 | return 0; | |
280 | ||
281 | len = sprintf(page, "devspec: %s\n", np->full_name); | |
282 | ||
283 | return len; | |
284 | } | |
285 | #endif /* CONFIG_PPC_OF */ | |
286 | ||
287 | ||
193515d5 | 288 | static struct scsi_host_template k2_sata_sht = { |
1da177e4 LT |
289 | .module = THIS_MODULE, |
290 | .name = DRV_NAME, | |
291 | .ioctl = ata_scsi_ioctl, | |
292 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
293 | .can_queue = ATA_DEF_QUEUE, |
294 | .this_id = ATA_SHT_THIS_ID, | |
295 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
296 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
297 | .emulated = ATA_SHT_EMULATED, | |
298 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
299 | .proc_name = DRV_NAME, | |
300 | .dma_boundary = ATA_DMA_BOUNDARY, | |
301 | .slave_configure = ata_scsi_slave_config, | |
302 | #ifdef CONFIG_PPC_OF | |
303 | .proc_info = k2_sata_proc_info, | |
304 | #endif | |
305 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
306 | }; |
307 | ||
308 | ||
057ace5e | 309 | static const struct ata_port_operations k2_sata_ops = { |
1da177e4 LT |
310 | .port_disable = ata_port_disable, |
311 | .tf_load = k2_sata_tf_load, | |
312 | .tf_read = k2_sata_tf_read, | |
313 | .check_status = k2_stat_check_status, | |
314 | .exec_command = ata_exec_command, | |
315 | .dev_select = ata_std_dev_select, | |
316 | .phy_reset = sata_phy_reset, | |
317 | .bmdma_setup = k2_bmdma_setup_mmio, | |
318 | .bmdma_start = k2_bmdma_start_mmio, | |
319 | .bmdma_stop = ata_bmdma_stop, | |
320 | .bmdma_status = ata_bmdma_status, | |
321 | .qc_prep = ata_qc_prep, | |
322 | .qc_issue = ata_qc_issue_prot, | |
323 | .eng_timeout = ata_eng_timeout, | |
324 | .irq_handler = ata_interrupt, | |
325 | .irq_clear = ata_bmdma_irq_clear, | |
326 | .scr_read = k2_sata_scr_read, | |
327 | .scr_write = k2_sata_scr_write, | |
328 | .port_start = ata_port_start, | |
329 | .port_stop = ata_port_stop, | |
374b1873 | 330 | .host_stop = ata_pci_host_stop, |
1da177e4 LT |
331 | }; |
332 | ||
333 | static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base) | |
334 | { | |
335 | port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; | |
336 | port->data_addr = base + K2_SATA_TF_DATA_OFFSET; | |
337 | port->feature_addr = | |
338 | port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; | |
339 | port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; | |
340 | port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; | |
341 | port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; | |
342 | port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; | |
343 | port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; | |
344 | port->command_addr = | |
345 | port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; | |
346 | port->altstatus_addr = | |
347 | port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; | |
348 | port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; | |
349 | port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; | |
350 | } | |
351 | ||
352 | ||
353 | static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
354 | { | |
355 | static int printed_version; | |
356 | struct ata_probe_ent *probe_ent = NULL; | |
357 | unsigned long base; | |
ea6ba10b | 358 | void __iomem *mmio_base; |
1da177e4 LT |
359 | int pci_dev_busy = 0; |
360 | int rc; | |
60bf09a3 | 361 | int i; |
1da177e4 LT |
362 | |
363 | if (!printed_version++) | |
a9524a76 | 364 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
365 | |
366 | /* | |
367 | * If this driver happens to only be useful on Apple's K2, then | |
368 | * we should check that here as it has a normal Serverworks ID | |
369 | */ | |
370 | rc = pci_enable_device(pdev); | |
371 | if (rc) | |
372 | return rc; | |
373 | /* | |
374 | * Check if we have resources mapped at all (second function may | |
375 | * have been disabled by firmware) | |
376 | */ | |
377 | if (pci_resource_len(pdev, 5) == 0) | |
378 | return -ENODEV; | |
379 | ||
380 | /* Request PCI regions */ | |
381 | rc = pci_request_regions(pdev, DRV_NAME); | |
382 | if (rc) { | |
383 | pci_dev_busy = 1; | |
384 | goto err_out; | |
385 | } | |
386 | ||
387 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
388 | if (rc) | |
389 | goto err_out_regions; | |
390 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
391 | if (rc) | |
392 | goto err_out_regions; | |
393 | ||
394 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
395 | if (probe_ent == NULL) { | |
396 | rc = -ENOMEM; | |
397 | goto err_out_regions; | |
398 | } | |
399 | ||
400 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
401 | probe_ent->dev = pci_dev_to_dev(pdev); | |
402 | INIT_LIST_HEAD(&probe_ent->node); | |
403 | ||
374b1873 | 404 | mmio_base = pci_iomap(pdev, 5, 0); |
1da177e4 LT |
405 | if (mmio_base == NULL) { |
406 | rc = -ENOMEM; | |
407 | goto err_out_free_ent; | |
408 | } | |
409 | base = (unsigned long) mmio_base; | |
410 | ||
411 | /* Clear a magic bit in SCR1 according to Darwin, those help | |
412 | * some funky seagate drives (though so far, those were already | |
104e5010 | 413 | * set by the firmware on the machines I had access to) |
1da177e4 LT |
414 | */ |
415 | writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, | |
416 | mmio_base + K2_SATA_SICR1_OFFSET); | |
417 | ||
418 | /* Clear SATA error & interrupts we don't use */ | |
419 | writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); | |
420 | writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); | |
421 | ||
422 | probe_ent->sht = &k2_sata_sht; | |
423 | probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET | | |
424 | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO; | |
425 | probe_ent->port_ops = &k2_sata_ops; | |
426 | probe_ent->n_ports = 4; | |
427 | probe_ent->irq = pdev->irq; | |
428 | probe_ent->irq_flags = SA_SHIRQ; | |
429 | probe_ent->mmio_base = mmio_base; | |
430 | ||
431 | /* We don't care much about the PIO/UDMA masks, but the core won't like us | |
432 | * if we don't fill these | |
433 | */ | |
434 | probe_ent->pio_mask = 0x1f; | |
435 | probe_ent->mwdma_mask = 0x7; | |
436 | probe_ent->udma_mask = 0x7f; | |
437 | ||
60bf09a3 NS |
438 | /* different controllers have different number of ports - currently 4 or 8 */ |
439 | /* All ports are on the same function. Multi-function device is no | |
440 | * longer available. This should not be seen in any system. */ | |
441 | for (i = 0; i < ent->driver_data; i++) | |
442 | k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET); | |
1da177e4 LT |
443 | |
444 | pci_set_master(pdev); | |
445 | ||
446 | /* FIXME: check ata_device_add return value */ | |
447 | ata_device_add(probe_ent); | |
448 | kfree(probe_ent); | |
449 | ||
450 | return 0; | |
451 | ||
452 | err_out_free_ent: | |
453 | kfree(probe_ent); | |
454 | err_out_regions: | |
455 | pci_release_regions(pdev); | |
456 | err_out: | |
457 | if (!pci_dev_busy) | |
458 | pci_disable_device(pdev); | |
459 | return rc; | |
460 | } | |
461 | ||
60bf09a3 NS |
462 | /* 0x240 is device ID for Apple K2 device |
463 | * 0x241 is device ID for Serverworks Frodo4 | |
464 | * 0x242 is device ID for Serverworks Frodo8 | |
465 | * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA | |
466 | * controller | |
467 | * */ | |
3b7d697d | 468 | static const struct pci_device_id k2_sata_pci_tbl[] = { |
60bf09a3 NS |
469 | { 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, |
470 | { 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, | |
471 | { 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, | |
472 | { 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, | |
88b52877 | 473 | { 0x1166, 0x024b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, |
1da177e4 LT |
474 | { } |
475 | }; | |
476 | ||
477 | ||
478 | static struct pci_driver k2_sata_pci_driver = { | |
479 | .name = DRV_NAME, | |
480 | .id_table = k2_sata_pci_tbl, | |
481 | .probe = k2_sata_init_one, | |
482 | .remove = ata_pci_remove_one, | |
483 | }; | |
484 | ||
485 | ||
486 | static int __init k2_sata_init(void) | |
487 | { | |
488 | return pci_module_init(&k2_sata_pci_driver); | |
489 | } | |
490 | ||
491 | ||
492 | static void __exit k2_sata_exit(void) | |
493 | { | |
494 | pci_unregister_driver(&k2_sata_pci_driver); | |
495 | } | |
496 | ||
497 | ||
498 | MODULE_AUTHOR("Benjamin Herrenschmidt"); | |
499 | MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); | |
500 | MODULE_LICENSE("GPL"); | |
501 | MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); | |
502 | MODULE_VERSION(DRV_VERSION); | |
503 | ||
504 | module_init(k2_sata_init); | |
505 | module_exit(k2_sata_exit); |