[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / sata_svw.c

/*
 *  sata_svw.c - ServerWorks / Apple K2 SATA
 *
 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
 *		   Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  This driver probably works with non-Apple versions of the
 *  Broadcom chipset...
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#ifdef CONFIG_PPC_OF
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif /* CONFIG_PPC_OF */

#define DRV_NAME	"sata_svw"
#define DRV_VERSION	"1.06"

/* Taskfile registers offsets */
#define K2_SATA_TF_CMD_OFFSET		0x00
#define K2_SATA_TF_DATA_OFFSET		0x00
#define K2_SATA_TF_ERROR_OFFSET		0x04
#define K2_SATA_TF_NSECT_OFFSET		0x08
#define K2_SATA_TF_LBAL_OFFSET		0x0c
#define K2_SATA_TF_LBAM_OFFSET		0x10
#define K2_SATA_TF_LBAH_OFFSET		0x14
#define K2_SATA_TF_DEVICE_OFFSET	0x18
#define K2_SATA_TF_CMDSTAT_OFFSET      	0x1c
#define K2_SATA_TF_CTL_OFFSET		0x20

/* DMA base */
#define K2_SATA_DMA_CMD_OFFSET		0x30

/* SCRs base */
#define K2_SATA_SCR_STATUS_OFFSET	0x40
#define K2_SATA_SCR_ERROR_OFFSET	0x44
#define K2_SATA_SCR_CONTROL_OFFSET	0x48

/* Others */
#define K2_SATA_SICR1_OFFSET		0x80
#define K2_SATA_SICR2_OFFSET		0x84
#define K2_SATA_SIM_OFFSET		0x88

/* Port stride */
#define K2_SATA_PORT_OFFSET		0x100

static u8 k2_stat_check_status(struct ata_port *ap);


static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;
	return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
			       u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;
	writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	if (tf->ctl != ap->last_ctl) {
		writeb(tf->ctl, ioaddr->ctl_addr);
		ap->last_ctl = tf->ctl;
		ata_wait_idle(ap);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = k2_stat_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
        }
}

/**
 *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host_set lock)
 */

static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	u8 dmactl;
	void *mmio = (void *) ap->ioaddr.bmdma_addr;
	/* load PRD table addr. */
	mb();	/* make sure PRD table writes are visible to controller */
	writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = readb(mmio + ATA_DMA_CMD);
	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
	if (!rw)
		dmactl |= ATA_DMA_WR;
	writeb(dmactl, mmio + ATA_DMA_CMD);

	/* issue r/w command if this is not a ATA DMA command*/
	if (qc->tf.protocol != ATA_PROT_DMA)
		ap->ops->exec_command(ap, &qc->tf);
}

/**
 *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host_set lock)
 */

static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void *mmio = (void *) ap->ioaddr.bmdma_addr;
	u8 dmactl;

	/* start host DMA transaction */
	dmactl = readb(mmio + ATA_DMA_CMD);
	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
	/* There is a race condition in certain SATA controllers that can
	   be seen when the r/w command is given to the controller before the
	   host DMA is started. On a Read command, the controller would initiate
	   the command to the drive even before it sees the DMA start. When there
	   are very fast drives connected to the controller, or when the data request
	   hits in the drive cache, there is the possibility that the drive returns a part
	   or all of the requested data to the controller before the DMA start is issued.
	   In this case, the controller would become confused as to what to do with the data.
	   In the worst case when all the data is returned back to the controller, the
	   controller could hang. In other cases it could return partial data returning
	   in data corruption. This problem has been seen in PPC systems and can also appear
	   on an system with very fast disks, where the SATA controller is sitting behind a
	   number of bridges, and hence there is significant latency between the r/w command
	   and the start command. */
	/* issue r/w command if the access is to ATA*/
	if (qc->tf.protocol == ATA_PROT_DMA)
		ap->ops->exec_command(ap, &qc->tf);
}


static u8 k2_stat_check_status(struct ata_port *ap)
{
       	return readl((void *) ap->ioaddr.status_addr);
}

#ifdef CONFIG_PPC_OF
/*
 * k2_sata_proc_info
 * inout : decides on the direction of the dataflow and the meaning of the
 *	   variables
 * buffer: If inout==FALSE data is being written to it else read from it
 * *start: If inout==FALSE start of the valid data in the buffer
 * offset: If inout==FALSE offset from the beginning of the imaginary file
 *	   from which we start writing into the buffer
 * length: If inout==FALSE max number of bytes to be written into the buffer
 *	   else number of bytes in the buffer
 */
static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
			     off_t offset, int count, int inout)
{
	struct ata_port *ap;
	struct device_node *np;
	int len, index;

	/* Find  the ata_port */
	ap = (struct ata_port *) &shost->hostdata[0];
	if (ap == NULL)
		return 0;

	/* Find the OF node for the PCI device proper */
	np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
	if (np == NULL)
		return 0;

	/* Match it to a port node */
	index = (ap == ap->host_set->ports[0]) ? 0 : 1;
	for (np = np->child; np != NULL; np = np->sibling) {
		u32 *reg = (u32 *)get_property(np, "reg", NULL);
		if (!reg)
			continue;
		if (index == *reg)
			break;
	}
	if (np == NULL)
		return 0;

	len = sprintf(page, "devspec: %s\n", np->full_name);

	return len;
}
#endif /* CONFIG_PPC_OF */


static Scsi_Host_Template k2_sata_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.eh_strategy_handler	= ata_scsi_error,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
#ifdef CONFIG_PPC_OF
	.proc_info		= k2_sata_proc_info,
#endif
	.bios_param		= ata_std_bios_param,
	.ordered_flush		= 1,
};


static const struct ata_port_operations k2_sata_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= k2_sata_tf_load,
	.tf_read		= k2_sata_tf_read,
	.check_status		= k2_stat_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.bmdma_setup		= k2_bmdma_setup_mmio,
	.bmdma_start		= k2_bmdma_start_mmio,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= k2_sata_scr_read,
	.scr_write		= k2_sata_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_pci_host_stop,
};

static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
{
	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
	port->feature_addr	=
	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
	port->command_addr	=
	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
	port->altstatus_addr	=
	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
}


static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	void __iomem *mmio_base;
	int pci_dev_busy = 0;
	int rc;
	int i;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pci_enable_device(pdev);
	if (rc)
		return rc;
	/*
	 * Check if we have resources mapped at all (second function may
	 * have been disabled by firmware)
	 */
	if (pci_resource_len(pdev, 5) == 0)
		return -ENODEV;

	/* Request PCI regions */
	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	memset(probe_ent, 0, sizeof(*probe_ent));
	probe_ent->dev = pci_dev_to_dev(pdev);
	INIT_LIST_HEAD(&probe_ent->node);

	mmio_base = pci_iomap(pdev, 5, 0);
	if (mmio_base == NULL) {
		rc = -ENOMEM;
		goto err_out_free_ent;
	}
	base = (unsigned long) mmio_base;

	/* Clear a magic bit in SCR1 according to Darwin, those help
	 * some funky seagate drives (though so far, those were already
	 * set by the firmware on the machines I had access to)
	 */
	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	       mmio_base + K2_SATA_SICR1_OFFSET);

	/* Clear SATA error & interrupts we don't use */
	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

	probe_ent->sht = &k2_sata_sht;
	probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
				ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
	probe_ent->port_ops = &k2_sata_ops;
	probe_ent->n_ports = 4;
	probe_ent->irq = pdev->irq;
	probe_ent->irq_flags = SA_SHIRQ;
	probe_ent->mmio_base = mmio_base;

	/* We don't care much about the PIO/UDMA masks, but the core won't like us
	 * if we don't fill these
	 */
	probe_ent->pio_mask = 0x1f;
	probe_ent->mwdma_mask = 0x7;
	probe_ent->udma_mask = 0x7f;

	/* different controllers have different number of ports - currently 4 or 8 */
	/* All ports are on the same function. Multi-function device is no
	 * longer available. This should not be seen in any system. */
	for (i = 0; i < ent->driver_data; i++)
		k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);

	pci_set_master(pdev);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;
}

/* 0x240 is device ID for Apple K2 device
 * 0x241 is device ID for Serverworks Frodo4
 * 0x242 is device ID for Serverworks Frodo8
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 * controller
 * */
static struct pci_device_id k2_sata_pci_tbl[] = {
	{ 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
	{ 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ }
};


static struct pci_driver k2_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= k2_sata_pci_tbl,
	.probe			= k2_sata_init_one,
	.remove			= ata_pci_remove_one,
};


static int __init k2_sata_init(void)
{
	return pci_module_init(&k2_sata_pci_driver);
}


static void __exit k2_sata_exit(void)
{
	pci_unregister_driver(&k2_sata_pci_driver);
}


MODULE_AUTHOR("Benjamin Herrenschmidt");
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(k2_sata_init);
module_exit(k2_sata_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_svw.c - ServerWorks / Apple K2 SATA
	3	*
	4	* Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
	5	* Jeff Garzik <jgarzik@pobox.com>
	6	* Please ALWAYS copy linux-ide@vger.kernel.org
	7	* on emails.
	8	*
	9	* Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
	10	*
	11	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	12	*
	13	* This driver probably works with non-Apple versions of the
	14	* Broadcom chipset...
	15	*
af36d7f0 JG	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License as published by
	19	* the Free Software Foundation; either version 2, or (at your option)
	20	* any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; see the file COPYING. If not, write to
	29	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	30	*
	31	*
	32	* libata documentation is available via 'make {ps\|pdf}docs',
	33	* as Documentation/DocBook/libata.*
	34	*
	35	* Hardware documentation available under NDA.
1da177e4 LT	36	*
	37	*/
	38
	39	#include <linux/config.h>
	40	#include <linux/kernel.h>
	41	#include <linux/module.h>
	42	#include <linux/pci.h>
	43	#include <linux/init.h>
	44	#include <linux/blkdev.h>
	45	#include <linux/delay.h>
	46	#include <linux/interrupt.h>
a9524a76	47	#include <linux/device.h>
1da177e4 LT	48	#include "scsi.h"
	49	#include <scsi/scsi_host.h>
	50	#include <linux/libata.h>
	51
	52	#ifdef CONFIG_PPC_OF
	53	#include <asm/prom.h>
	54	#include <asm/pci-bridge.h>
	55	#endif /* CONFIG_PPC_OF */
	56
	57	#define DRV_NAME "sata_svw"
54258a8a	58	#define DRV_VERSION "1.06"
1da177e4 LT	59
	60	/* Taskfile registers offsets */
	61	#define K2_SATA_TF_CMD_OFFSET 0x00
	62	#define K2_SATA_TF_DATA_OFFSET 0x00
	63	#define K2_SATA_TF_ERROR_OFFSET 0x04
	64	#define K2_SATA_TF_NSECT_OFFSET 0x08
	65	#define K2_SATA_TF_LBAL_OFFSET 0x0c
	66	#define K2_SATA_TF_LBAM_OFFSET 0x10
	67	#define K2_SATA_TF_LBAH_OFFSET 0x14
	68	#define K2_SATA_TF_DEVICE_OFFSET 0x18
	69	#define K2_SATA_TF_CMDSTAT_OFFSET 0x1c
	70	#define K2_SATA_TF_CTL_OFFSET 0x20
	71
	72	/* DMA base */
	73	#define K2_SATA_DMA_CMD_OFFSET 0x30
	74
	75	/* SCRs base */
	76	#define K2_SATA_SCR_STATUS_OFFSET 0x40
	77	#define K2_SATA_SCR_ERROR_OFFSET 0x44
	78	#define K2_SATA_SCR_CONTROL_OFFSET 0x48
	79
	80	/* Others */
	81	#define K2_SATA_SICR1_OFFSET 0x80
	82	#define K2_SATA_SICR2_OFFSET 0x84
	83	#define K2_SATA_SIM_OFFSET 0x88
	84
	85	/* Port stride */
	86	#define K2_SATA_PORT_OFFSET 0x100
	87
ac19bff2 JG	88	static u8 k2_stat_check_status(struct ata_port *ap);
ac19bff2 JG	89
1da177e4 LT	90
	91	static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
	92	{
	93	if (sc_reg > SCR_CONTROL)
	94	return 0xffffffffU;
	95	return readl((void ) ap->ioaddr.scr_addr + (sc_reg 4));
	96	}
	97
	98
	99	static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
	100	u32 val)
	101	{
	102	if (sc_reg > SCR_CONTROL)
	103	return;
	104	writel(val, (void ) ap->ioaddr.scr_addr + (sc_reg 4));
	105	}
	106
	107
057ace5e	108	static void k2_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	109	{
	110	struct ata_ioports *ioaddr = &ap->ioaddr;
	111	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	112
	113	if (tf->ctl != ap->last_ctl) {
	114	writeb(tf->ctl, ioaddr->ctl_addr);
	115	ap->last_ctl = tf->ctl;
	116	ata_wait_idle(ap);
	117	}
	118	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
	119	writew(tf->feature \| (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
	120	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
	121	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
	122	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
	123	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
	124	} else if (is_addr) {
	125	writew(tf->feature, ioaddr->feature_addr);
	126	writew(tf->nsect, ioaddr->nsect_addr);
	127	writew(tf->lbal, ioaddr->lbal_addr);
	128	writew(tf->lbam, ioaddr->lbam_addr);
	129	writew(tf->lbah, ioaddr->lbah_addr);
	130	}
	131
	132	if (tf->flags & ATA_TFLAG_DEVICE)
	133	writeb(tf->device, ioaddr->device_addr);
	134
	135	ata_wait_idle(ap);
	136	}
	137
	138
	139	static void k2_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	140	{
	141	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	142	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	143
ac19bff2	144	tf->command = k2_stat_check_status(ap);
1da177e4	145	tf->device = readw(ioaddr->device_addr);
ac19bff2 JG	146	feature = readw(ioaddr->error_addr);
	147	nsect = readw(ioaddr->nsect_addr);
	148	lbal = readw(ioaddr->lbal_addr);
	149	lbam = readw(ioaddr->lbam_addr);
	150	lbah = readw(ioaddr->lbah_addr);
	151
	152	tf->feature = feature;
	153	tf->nsect = nsect;
	154	tf->lbal = lbal;
	155	tf->lbam = lbam;
	156	tf->lbah = lbah;
1da177e4 LT	157
1da177e4 LT	158	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	159	tf->hob_feature = feature >> 8;
1da177e4 LT	160	tf->hob_nsect = nsect >> 8;
	161	tf->hob_lbal = lbal >> 8;
	162	tf->hob_lbam = lbam >> 8;
	163	tf->hob_lbah = lbah >> 8;
	164	}
	165	}
	166
	167	/**
	168	* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
	169	* @qc: Info associated with this ATA transaction.
	170	*
	171	* LOCKING:
	172	* spin_lock_irqsave(host_set lock)
	173	*/
	174
	175	static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
	176	{
	177	struct ata_port *ap = qc->ap;
	178	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	179	u8 dmactl;
	180	void mmio = (void ) ap->ioaddr.bmdma_addr;
	181	/* load PRD table addr. */
	182	mb(); /* make sure PRD table writes are visible to controller */
	183	writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
	184
	185	/* specify data direction, triple-check start bit is clear */
	186	dmactl = readb(mmio + ATA_DMA_CMD);
	187	dmactl &= ~(ATA_DMA_WR \| ATA_DMA_START);
	188	if (!rw)
	189	dmactl \|= ATA_DMA_WR;
	190	writeb(dmactl, mmio + ATA_DMA_CMD);
	191
	192	/* issue r/w command if this is not a ATA DMA command*/
	193	if (qc->tf.protocol != ATA_PROT_DMA)
	194	ap->ops->exec_command(ap, &qc->tf);
	195	}
	196
	197	/**
	198	* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
	199	* @qc: Info associated with this ATA transaction.
	200	*
	201	* LOCKING:
	202	* spin_lock_irqsave(host_set lock)
	203	*/
	204
	205	static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
	206	{
	207	struct ata_port *ap = qc->ap;
	208	void mmio = (void ) ap->ioaddr.bmdma_addr;
	209	u8 dmactl;
	210
	211	/* start host DMA transaction */
	212	dmactl = readb(mmio + ATA_DMA_CMD);
	213	writeb(dmactl \| ATA_DMA_START, mmio + ATA_DMA_CMD);
8a60a071 JG	214	/* There is a race condition in certain SATA controllers that can
8a60a071 JG	215	be seen when the r/w command is given to the controller before the
1da177e4 LT	216	host DMA is started. On a Read command, the controller would initiate
1da177e4 LT	217	the command to the drive even before it sees the DMA start. When there
8a60a071	218	are very fast drives connected to the controller, or when the data request
1da177e4 LT	219	hits in the drive cache, there is the possibility that the drive returns a part
	220	or all of the requested data to the controller before the DMA start is issued.
	221	In this case, the controller would become confused as to what to do with the data.
	222	In the worst case when all the data is returned back to the controller, the
	223	controller could hang. In other cases it could return partial data returning
	224	in data corruption. This problem has been seen in PPC systems and can also appear
8a60a071	225	on an system with very fast disks, where the SATA controller is sitting behind a
1da177e4 LT	226	number of bridges, and hence there is significant latency between the r/w command
	227	and the start command. */
	228	/* issue r/w command if the access is to ATA*/
	229	if (qc->tf.protocol == ATA_PROT_DMA)
	230	ap->ops->exec_command(ap, &qc->tf);
	231	}
	232
8a60a071	233
1da177e4 LT	234	static u8 k2_stat_check_status(struct ata_port *ap)
	235	{
	236	return readl((void *) ap->ioaddr.status_addr);
	237	}
	238
	239	#ifdef CONFIG_PPC_OF
	240	/*
	241	* k2_sata_proc_info
	242	* inout : decides on the direction of the dataflow and the meaning of the
	243	* variables
	244	* buffer: If inout==FALSE data is being written to it else read from it
	245	* *start: If inout==FALSE start of the valid data in the buffer
	246	* offset: If inout==FALSE offset from the beginning of the imaginary file
	247	* from which we start writing into the buffer
	248	* length: If inout==FALSE max number of bytes to be written into the buffer
	249	* else number of bytes in the buffer
	250	*/
	251	static int k2_sata_proc_info(struct Scsi_Host shost, char page, char **start,
	252	off_t offset, int count, int inout)
	253	{
	254	struct ata_port *ap;
	255	struct device_node *np;
	256	int len, index;
	257
	258	/* Find the ata_port */
	259	ap = (struct ata_port *) &shost->hostdata[0];
	260	if (ap == NULL)
	261	return 0;
	262
	263	/* Find the OF node for the PCI device proper */
	264	np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
	265	if (np == NULL)
	266	return 0;
	267
	268	/* Match it to a port node */
	269	index = (ap == ap->host_set->ports[0]) ? 0 : 1;
	270	for (np = np->child; np != NULL; np = np->sibling) {
	271	u32 reg = (u32 )get_property(np, "reg", NULL);
	272	if (!reg)
	273	continue;
	274	if (index == *reg)
	275	break;
	276	}
	277	if (np == NULL)
	278	return 0;
	279
	280	len = sprintf(page, "devspec: %s\n", np->full_name);
	281
	282	return len;
	283	}
	284	#endif /* CONFIG_PPC_OF */
	285
	286
	287	static Scsi_Host_Template k2_sata_sht = {
	288	.module = THIS_MODULE,
	289	.name = DRV_NAME,
	290	.ioctl = ata_scsi_ioctl,
	291	.queuecommand = ata_scsi_queuecmd,
	292	.eh_strategy_handler = ata_scsi_error,
	293	.can_queue = ATA_DEF_QUEUE,
	294	.this_id = ATA_SHT_THIS_ID,
	295	.sg_tablesize = LIBATA_MAX_PRD,
	296	.max_sectors = ATA_MAX_SECTORS,
	297	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
298	.emulated = ATA_SHT_EMULATED,
299	.use_clustering = ATA_SHT_USE_CLUSTERING,
300	.proc_name = DRV_NAME,
301	.dma_boundary = ATA_DMA_BOUNDARY,
302	.slave_configure = ata_scsi_slave_config,
303	#ifdef CONFIG_PPC_OF
304	.proc_info = k2_sata_proc_info,
305	#endif
306	.bios_param = ata_std_bios_param,
307	.ordered_flush = 1,
308	};
309
310
057ace5e	311	static const struct ata_port_operations k2_sata_ops = {
1da177e4 LT	312	.port_disable = ata_port_disable,
	313	.tf_load = k2_sata_tf_load,
	314	.tf_read = k2_sata_tf_read,
	315	.check_status = k2_stat_check_status,
	316	.exec_command = ata_exec_command,
	317	.dev_select = ata_std_dev_select,
	318	.phy_reset = sata_phy_reset,
	319	.bmdma_setup = k2_bmdma_setup_mmio,
	320	.bmdma_start = k2_bmdma_start_mmio,
	321	.bmdma_stop = ata_bmdma_stop,
	322	.bmdma_status = ata_bmdma_status,
	323	.qc_prep = ata_qc_prep,
	324	.qc_issue = ata_qc_issue_prot,
	325	.eng_timeout = ata_eng_timeout,
	326	.irq_handler = ata_interrupt,
	327	.irq_clear = ata_bmdma_irq_clear,
	328	.scr_read = k2_sata_scr_read,
	329	.scr_write = k2_sata_scr_write,
	330	.port_start = ata_port_start,
	331	.port_stop = ata_port_stop,
374b1873	332	.host_stop = ata_pci_host_stop,
1da177e4 LT	333	};
	334
	335	static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
	336	{
	337	port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
	338	port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
	339	port->feature_addr =
	340	port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
	341	port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
	342	port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
	343	port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
	344	port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
	345	port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
	346	port->command_addr =
	347	port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
	348	port->altstatus_addr =
	349	port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
	350	port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
	351	port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
	352	}
	353
	354
	355	static int k2_sata_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	356	{
	357	static int printed_version;
	358	struct ata_probe_ent *probe_ent = NULL;
	359	unsigned long base;
ea6ba10b	360	void __iomem *mmio_base;
1da177e4 LT	361	int pci_dev_busy = 0;
1da177e4 LT	362	int rc;
60bf09a3	363	int i;
1da177e4 LT	364
1da177e4 LT	365	if (!printed_version++)
a9524a76	366	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 LT	367
	368	/*
	369	* If this driver happens to only be useful on Apple's K2, then
	370	* we should check that here as it has a normal Serverworks ID
	371	*/
	372	rc = pci_enable_device(pdev);
	373	if (rc)
	374	return rc;
	375	/*
	376	* Check if we have resources mapped at all (second function may
	377	* have been disabled by firmware)
	378	*/
	379	if (pci_resource_len(pdev, 5) == 0)
	380	return -ENODEV;
	381
	382	/* Request PCI regions */
	383	rc = pci_request_regions(pdev, DRV_NAME);
	384	if (rc) {
	385	pci_dev_busy = 1;
	386	goto err_out;
	387	}
	388
	389	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	390	if (rc)
	391	goto err_out_regions;
	392	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	393	if (rc)
	394	goto err_out_regions;
	395
	396	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	397	if (probe_ent == NULL) {
	398	rc = -ENOMEM;
	399	goto err_out_regions;
	400	}
	401
	402	memset(probe_ent, 0, sizeof(*probe_ent));
	403	probe_ent->dev = pci_dev_to_dev(pdev);
	404	INIT_LIST_HEAD(&probe_ent->node);
	405
374b1873	406	mmio_base = pci_iomap(pdev, 5, 0);
1da177e4 LT	407	if (mmio_base == NULL) {
	408	rc = -ENOMEM;
	409	goto err_out_free_ent;
	410	}
	411	base = (unsigned long) mmio_base;
	412
	413	/* Clear a magic bit in SCR1 according to Darwin, those help
	414	* some funky seagate drives (though so far, those were already
104e5010	415	* set by the firmware on the machines I had access to)
1da177e4 LT	416	*/
	417	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	418	mmio_base + K2_SATA_SICR1_OFFSET);
	419
	420	/* Clear SATA error & interrupts we don't use */
	421	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	422	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
	423
	424	probe_ent->sht = &k2_sata_sht;
	425	probe_ent->host_flags = ATA_FLAG_SATA \| ATA_FLAG_SATA_RESET \|
	426	ATA_FLAG_NO_LEGACY \| ATA_FLAG_MMIO;
	427	probe_ent->port_ops = &k2_sata_ops;
	428	probe_ent->n_ports = 4;
	429	probe_ent->irq = pdev->irq;
	430	probe_ent->irq_flags = SA_SHIRQ;
	431	probe_ent->mmio_base = mmio_base;
	432
	433	/* We don't care much about the PIO/UDMA masks, but the core won't like us
	434	* if we don't fill these
	435	*/
	436	probe_ent->pio_mask = 0x1f;
	437	probe_ent->mwdma_mask = 0x7;
	438	probe_ent->udma_mask = 0x7f;
	439
60bf09a3 NS	440	/* different controllers have different number of ports - currently 4 or 8 */
	441	/* All ports are on the same function. Multi-function device is no
	442	* longer available. This should not be seen in any system. */
	443	for (i = 0; i < ent->driver_data; i++)
	444	k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);
1da177e4 LT	445
	446	pci_set_master(pdev);
	447
	448	/* FIXME: check ata_device_add return value */
	449	ata_device_add(probe_ent);
	450	kfree(probe_ent);
	451
	452	return 0;
	453
	454	err_out_free_ent:
	455	kfree(probe_ent);
	456	err_out_regions:
	457	pci_release_regions(pdev);
	458	err_out:
	459	if (!pci_dev_busy)
	460	pci_disable_device(pdev);
	461	return rc;
	462	}
	463
60bf09a3 NS	464	/* 0x240 is device ID for Apple K2 device
	465	* 0x241 is device ID for Serverworks Frodo4
	466	* 0x242 is device ID for Serverworks Frodo8
	467	* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
	468	* controller
	469	* */
1da177e4	470	static struct pci_device_id k2_sata_pci_tbl[] = {
60bf09a3 NS	471	{ 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	472	{ 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	473	{ 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
	474	{ 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
1da177e4 LT	475	{ }
	476	};
	477
	478
	479	static struct pci_driver k2_sata_pci_driver = {
	480	.name = DRV_NAME,
	481	.id_table = k2_sata_pci_tbl,
	482	.probe = k2_sata_init_one,
	483	.remove = ata_pci_remove_one,
	484	};
	485
	486
	487	static int __init k2_sata_init(void)
	488	{
	489	return pci_module_init(&k2_sata_pci_driver);
	490	}
	491
	492
	493	static void __exit k2_sata_exit(void)
	494	{
	495	pci_unregister_driver(&k2_sata_pci_driver);
	496	}
	497
	498
	499	MODULE_AUTHOR("Benjamin Herrenschmidt");
	500	MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
	501	MODULE_LICENSE("GPL");
	502	MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
	503	MODULE_VERSION(DRV_VERSION);
	504
	505	module_init(k2_sata_init);
	506	module_exit(k2_sata_exit);