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[PATCH] pcmcia: new suspend core
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / sata_promise.c
CommitLineData
1da177e4
LT		 1/*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
1da177e4 10 *
af36d7f0
JG		 11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
1da177e4
LT		 30 *
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/init.h>
37#include <linux/blkdev.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/sched.h>
a9524a76 41#include <linux/device.h>
1da177e4 42#include <scsi/scsi_host.h>
193515d5 43#include <scsi/scsi_cmnd.h>
1da177e4
LT		 44#include <linux/libata.h>
45#include <asm/io.h>
46#include "sata_promise.h"
47
48#define DRV_NAME "sata_promise"
7bdd7208 49#define DRV_VERSION "1.03"
1da177e4
LT		 50
51
52enum {
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
62
63 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
64 (1<<8) | (1<<9) | (1<<10),
65
66 board_2037x = 0, /* FastTrak S150 TX2plus */
67 board_20319 = 1, /* FastTrak S150 TX4 */
f497ba73 68 board_20619 = 2, /* FastTrak TX4000 */
1da177e4
LT		 69
70 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
71
72 PDC_RESET = (1 << 11), /* HDMA reset */
50630195
JG		 73
74 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
75 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI,
1da177e4
LT		 76};
77
78
79struct pdc_port_priv {
80 u8 *pkt;
81 dma_addr_t pkt_dma;
82};
83
84static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
85static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
86static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
87static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
88static void pdc_eng_timeout(struct ata_port *ap);
89static int pdc_port_start(struct ata_port *ap);
90static void pdc_port_stop(struct ata_port *ap);
2cba582a
JG		 91static void pdc_pata_phy_reset(struct ata_port *ap);
92static void pdc_sata_phy_reset(struct ata_port *ap);
1da177e4 93static void pdc_qc_prep(struct ata_queued_cmd *qc);
057ace5e
JG		 94static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
95static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
1da177e4
LT		 96static void pdc_irq_clear(struct ata_port *ap);
97static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
98
374b1873 99
193515d5 100static struct scsi_host_template pdc_ata_sht = {
1da177e4
LT		 101 .module = THIS_MODULE,
102 .name = DRV_NAME,
103 .ioctl = ata_scsi_ioctl,
104 .queuecommand = ata_scsi_queuecmd,
105 .eh_strategy_handler = ata_scsi_error,
106 .can_queue = ATA_DEF_QUEUE,
107 .this_id = ATA_SHT_THIS_ID,
108 .sg_tablesize = LIBATA_MAX_PRD,
109 .max_sectors = ATA_MAX_SECTORS,
110 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
111 .emulated = ATA_SHT_EMULATED,
112 .use_clustering = ATA_SHT_USE_CLUSTERING,
113 .proc_name = DRV_NAME,
114 .dma_boundary = ATA_DMA_BOUNDARY,
115 .slave_configure = ata_scsi_slave_config,
116 .bios_param = ata_std_bios_param,
117 .ordered_flush = 1,
118};
119
057ace5e 120static const struct ata_port_operations pdc_sata_ops = {
1da177e4
LT		 121 .port_disable = ata_port_disable,
122 .tf_load = pdc_tf_load_mmio,
123 .tf_read = ata_tf_read,
124 .check_status = ata_check_status,
125 .exec_command = pdc_exec_command_mmio,
126 .dev_select = ata_std_dev_select,
2cba582a
JG		 127
128 .phy_reset = pdc_sata_phy_reset,
129
1da177e4
LT		 130 .qc_prep = pdc_qc_prep,
131 .qc_issue = pdc_qc_issue_prot,
132 .eng_timeout = pdc_eng_timeout,
133 .irq_handler = pdc_interrupt,
134 .irq_clear = pdc_irq_clear,
2cba582a 135
1da177e4
LT		 136 .scr_read = pdc_sata_scr_read,
137 .scr_write = pdc_sata_scr_write,
138 .port_start = pdc_port_start,
139 .port_stop = pdc_port_stop,
374b1873 140 .host_stop = ata_pci_host_stop,
1da177e4
LT		 141};
142
057ace5e 143static const struct ata_port_operations pdc_pata_ops = {
2cba582a
JG		 144 .port_disable = ata_port_disable,
145 .tf_load = pdc_tf_load_mmio,
146 .tf_read = ata_tf_read,
147 .check_status = ata_check_status,
148 .exec_command = pdc_exec_command_mmio,
149 .dev_select = ata_std_dev_select,
150
151 .phy_reset = pdc_pata_phy_reset,
152
153 .qc_prep = pdc_qc_prep,
154 .qc_issue = pdc_qc_issue_prot,
155 .eng_timeout = pdc_eng_timeout,
156 .irq_handler = pdc_interrupt,
157 .irq_clear = pdc_irq_clear,
158
159 .port_start = pdc_port_start,
160 .port_stop = pdc_port_stop,
374b1873 161 .host_stop = ata_pci_host_stop,
2cba582a
JG		 162};
163
98ac62de 164static const struct ata_port_info pdc_port_info[] = {
1da177e4
LT		 165 /* board_2037x */
166 {
167 .sht = &pdc_ata_sht,
50630195 168 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
1da177e4
LT		 169 .pio_mask = 0x1f, /* pio0-4 */
170 .mwdma_mask = 0x07, /* mwdma0-2 */
171 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
2cba582a 172 .port_ops = &pdc_sata_ops,
1da177e4
LT		 173 },
174
175 /* board_20319 */
176 {
177 .sht = &pdc_ata_sht,
50630195 178 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
1da177e4
LT		 179 .pio_mask = 0x1f, /* pio0-4 */
180 .mwdma_mask = 0x07, /* mwdma0-2 */
181 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
2cba582a 182 .port_ops = &pdc_sata_ops,
1da177e4 183 },
f497ba73
TL		 184
185 /* board_20619 */
186 {
187 .sht = &pdc_ata_sht,
50630195 188 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
f497ba73
TL		 189 .pio_mask = 0x1f, /* pio0-4 */
190 .mwdma_mask = 0x07, /* mwdma0-2 */
191 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
2cba582a 192 .port_ops = &pdc_pata_ops,
f497ba73 193 },
1da177e4
LT		 194};
195
3b7d697d 196static const struct pci_device_id pdc_ata_pci_tbl[] = {
1da177e4
LT		 197 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
198 board_2037x },
07c1da23
JG		 199 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
200 board_2037x },
4c3a53d4
FJ		 201 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
202 board_2037x },
1da177e4
LT		 203 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
204 board_2037x },
205 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
206 board_2037x },
207 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
208 board_2037x },
209 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
210 board_2037x },
211 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
212 board_2037x },
c45154a3
EK		 213 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
214 board_2037x },
1da177e4
LT		 215
216 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
217 board_20319 },
218 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
219 board_20319 },
93090495
DD		 220 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
221 board_20319 },
08b791c0
OM		 222 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
223 board_20319 },
1da177e4
LT		 224 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
225 board_20319 },
226
f497ba73
TL		 227 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
228 board_20619 },
229
1da177e4
LT		 230 { } /* terminate list */
231};
232
233
234static struct pci_driver pdc_ata_pci_driver = {
235 .name = DRV_NAME,
236 .id_table = pdc_ata_pci_tbl,
237 .probe = pdc_ata_init_one,
238 .remove = ata_pci_remove_one,
239};
240
241
242static int pdc_port_start(struct ata_port *ap)
243{
244 struct device *dev = ap->host_set->dev;
245 struct pdc_port_priv *pp;
246 int rc;
247
248 rc = ata_port_start(ap);
249 if (rc)
250 return rc;
251
252 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
253 if (!pp) {
254 rc = -ENOMEM;
255 goto err_out;
256 }
257 memset(pp, 0, sizeof(*pp));
258
259 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
260 if (!pp->pkt) {
261 rc = -ENOMEM;
262 goto err_out_kfree;
263 }
264
265 ap->private_data = pp;
266
267 return 0;
268
269err_out_kfree:
270 kfree(pp);
271err_out:
272 ata_port_stop(ap);
273 return rc;
274}
275
276
277static void pdc_port_stop(struct ata_port *ap)
278{
279 struct device *dev = ap->host_set->dev;
280 struct pdc_port_priv *pp = ap->private_data;
281
282 ap->private_data = NULL;
283 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
284 kfree(pp);
285 ata_port_stop(ap);
286}
287
288
289static void pdc_reset_port(struct ata_port *ap)
290{
ea6ba10b 291 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
1da177e4
LT		 292 unsigned int i;
293 u32 tmp;
294
295 for (i = 11; i > 0; i--) {
296 tmp = readl(mmio);
297 if (tmp & PDC_RESET)
298 break;
299
300 udelay(100);
301
302 tmp |= PDC_RESET;
303 writel(tmp, mmio);
304 }
305
306 tmp &= ~PDC_RESET;
307 writel(tmp, mmio);
308 readl(mmio); /* flush */
309}
310
2cba582a 311static void pdc_sata_phy_reset(struct ata_port *ap)
1da177e4
LT		 312{
313 pdc_reset_port(ap);
314 sata_phy_reset(ap);
315}
316
2cba582a
JG		 317static void pdc_pata_phy_reset(struct ata_port *ap)
318{
319 /* FIXME: add cable detect. Don't assume 40-pin cable */
320 ap->cbl = ATA_CBL_PATA40;
321 ap->udma_mask &= ATA_UDMA_MASK_40C;
322
323 pdc_reset_port(ap);
324 ata_port_probe(ap);
325 ata_bus_reset(ap);
326}
327
1da177e4
LT		 328static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
329{
330 if (sc_reg > SCR_CONTROL)
331 return 0xffffffffU;
b181d3b0 332 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 333}
334
335
336static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
337 u32 val)
338{
339 if (sc_reg > SCR_CONTROL)
340 return;
b181d3b0 341 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 342}
343
344static void pdc_qc_prep(struct ata_queued_cmd *qc)
345{
346 struct pdc_port_priv *pp = qc->ap->private_data;
347 unsigned int i;
348
349 VPRINTK("ENTER\n");
350
351 switch (qc->tf.protocol) {
352 case ATA_PROT_DMA:
353 ata_qc_prep(qc);
354 /* fall through */
355
356 case ATA_PROT_NODATA:
357 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
358 qc->dev->devno, pp->pkt);
359
360 if (qc->tf.flags & ATA_TFLAG_LBA48)
361 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
362 else
363 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
364
365 pdc_pkt_footer(&qc->tf, pp->pkt, i);
366 break;
367
368 default:
369 break;
370 }
371}
372
373static void pdc_eng_timeout(struct ata_port *ap)
374{
b8f6153e 375 struct ata_host_set *host_set = ap->host_set;
1da177e4
LT		 376 u8 drv_stat;
377 struct ata_queued_cmd *qc;
b8f6153e 378 unsigned long flags;
1da177e4
LT		 379
380 DPRINTK("ENTER\n");
381
b8f6153e
JG		 382 spin_lock_irqsave(&host_set->lock, flags);
383
1da177e4
LT		 384 qc = ata_qc_from_tag(ap, ap->active_tag);
385 if (!qc) {
386 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
387 ap->id);
388 goto out;
389 }
390
391 /* hack alert! We cannot use the supplied completion
392 * function from inside the ->eh_strategy_handler() thread.
393 * libata is the only user of ->eh_strategy_handler() in
394 * any kernel, so the default scsi_done() assumes it is
395 * not being called from the SCSI EH.
396 */
397 qc->scsidone = scsi_finish_command;
398
399 switch (qc->tf.protocol) {
400 case ATA_PROT_DMA:
401 case ATA_PROT_NODATA:
402 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
a7dac447 403 drv_stat = ata_wait_idle(ap);
a22e2eb0
AL		 404 qc->err_mask |= __ac_err_mask(drv_stat);
405 ata_qc_complete(qc);
1da177e4
LT		 406 break;
407
408 default:
409 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
410
411 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
412 ap->id, qc->tf.command, drv_stat);
413
a22e2eb0
AL		 414 qc->err_mask |= ac_err_mask(drv_stat);
415 ata_qc_complete(qc);
1da177e4
LT		 416 break;
417 }
418
419out:
b8f6153e 420 spin_unlock_irqrestore(&host_set->lock, flags);
1da177e4
LT		 421 DPRINTK("EXIT\n");
422}
423
424static inline unsigned int pdc_host_intr( struct ata_port *ap,
425 struct ata_queued_cmd *qc)
426{
a22e2eb0 427 unsigned int handled = 0;
1da177e4 428 u32 tmp;
ea6ba10b 429 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
1da177e4
LT		 430
431 tmp = readl(mmio);
432 if (tmp & PDC_ERR_MASK) {
a22e2eb0 433 qc->err_mask |= AC_ERR_DEV;
1da177e4
LT		 434 pdc_reset_port(ap);
435 }
436
437 switch (qc->tf.protocol) {
438 case ATA_PROT_DMA:
439 case ATA_PROT_NODATA:
a22e2eb0
AL		 440 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
441 ata_qc_complete(qc);
1da177e4
LT		 442 handled = 1;
443 break;
444
445 default:
ee500aab
AL		 446 ap->stats.idle_irq++;
447 break;
1da177e4
LT		 448 }
449
ee500aab 450 return handled;
1da177e4
LT		 451}
452
453static void pdc_irq_clear(struct ata_port *ap)
454{
455 struct ata_host_set *host_set = ap->host_set;
ea6ba10b 456 void __iomem *mmio = host_set->mmio_base;
1da177e4
LT		 457
458 readl(mmio + PDC_INT_SEQMASK);
459}
460
461static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
462{
463 struct ata_host_set *host_set = dev_instance;
464 struct ata_port *ap;
465 u32 mask = 0;
466 unsigned int i, tmp;
467 unsigned int handled = 0;
ea6ba10b 468 void __iomem *mmio_base;
1da177e4
LT		 469
470 VPRINTK("ENTER\n");
471
472 if (!host_set || !host_set->mmio_base) {
473 VPRINTK("QUICK EXIT\n");
474 return IRQ_NONE;
475 }
476
477 mmio_base = host_set->mmio_base;
478
479 /* reading should also clear interrupts */
480 mask = readl(mmio_base + PDC_INT_SEQMASK);
481
482 if (mask == 0xffffffff) {
483 VPRINTK("QUICK EXIT 2\n");
484 return IRQ_NONE;
485 }
486 mask &= 0xffff; /* only 16 tags possible */
487 if (!mask) {
488 VPRINTK("QUICK EXIT 3\n");
489 return IRQ_NONE;
490 }
491
492 spin_lock(&host_set->lock);
493
494 writel(mask, mmio_base + PDC_INT_SEQMASK);
495
496 for (i = 0; i < host_set->n_ports; i++) {
497 VPRINTK("port %u\n", i);
498 ap = host_set->ports[i];
499 tmp = mask & (1 << (i + 1));
c1389503
TH		 500 if (tmp && ap &&
501 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 502 struct ata_queued_cmd *qc;
503
504 qc = ata_qc_from_tag(ap, ap->active_tag);
505 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
506 handled += pdc_host_intr(ap, qc);
507 }
508 }
509
510 spin_unlock(&host_set->lock);
511
512 VPRINTK("EXIT\n");
513
514 return IRQ_RETVAL(handled);
515}
516
517static inline void pdc_packet_start(struct ata_queued_cmd *qc)
518{
519 struct ata_port *ap = qc->ap;
520 struct pdc_port_priv *pp = ap->private_data;
521 unsigned int port_no = ap->port_no;
522 u8 seq = (u8) (port_no + 1);
523
524 VPRINTK("ENTER, ap %p\n", ap);
525
526 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
527 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
528
529 pp->pkt[2] = seq;
530 wmb(); /* flush PRD, pkt writes */
b181d3b0
AV		 531 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
532 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
1da177e4
LT		 533}
534
535static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
536{
537 switch (qc->tf.protocol) {
538 case ATA_PROT_DMA:
539 case ATA_PROT_NODATA:
540 pdc_packet_start(qc);
541 return 0;
542
543 case ATA_PROT_ATAPI_DMA:
544 BUG();
545 break;
546
547 default:
548 break;
549 }
550
551 return ata_qc_issue_prot(qc);
552}
553
057ace5e 554static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 555{
556 WARN_ON (tf->protocol == ATA_PROT_DMA ||
557 tf->protocol == ATA_PROT_NODATA);
558 ata_tf_load(ap, tf);
559}
560
561
057ace5e 562static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 563{
564 WARN_ON (tf->protocol == ATA_PROT_DMA ||
565 tf->protocol == ATA_PROT_NODATA);
566 ata_exec_command(ap, tf);
567}
568
569
570static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
571{
572 port->cmd_addr = base;
573 port->data_addr = base;
574 port->feature_addr =
575 port->error_addr = base + 0x4;
576 port->nsect_addr = base + 0x8;
577 port->lbal_addr = base + 0xc;
578 port->lbam_addr = base + 0x10;
579 port->lbah_addr = base + 0x14;
580 port->device_addr = base + 0x18;
581 port->command_addr =
582 port->status_addr = base + 0x1c;
583 port->altstatus_addr =
584 port->ctl_addr = base + 0x38;
585}
586
587
588static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
589{
ea6ba10b 590 void __iomem *mmio = pe->mmio_base;
1da177e4
LT		 591 u32 tmp;
592
593 /*
594 * Except for the hotplug stuff, this is voodoo from the
595 * Promise driver. Label this entire section
596 * "TODO: figure out why we do this"
597 */
598
599 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
600 tmp = readl(mmio + PDC_FLASH_CTL);
601 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
602 writel(tmp, mmio + PDC_FLASH_CTL);
603
604 /* clear plug/unplug flags for all ports */
605 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
606 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
607
608 /* mask plug/unplug ints */
609 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
610 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
611
612 /* reduce TBG clock to 133 Mhz. */
613 tmp = readl(mmio + PDC_TBG_MODE);
614 tmp &= ~0x30000; /* clear bit 17, 16*/
615 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
616 writel(tmp, mmio + PDC_TBG_MODE);
617
618 readl(mmio + PDC_TBG_MODE); /* flush */
619 msleep(10);
620
621 /* adjust slew rate control register. */
622 tmp = readl(mmio + PDC_SLEW_CTL);
623 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
624 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
625 writel(tmp, mmio + PDC_SLEW_CTL);
626}
627
628static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
629{
630 static int printed_version;
631 struct ata_probe_ent *probe_ent = NULL;
632 unsigned long base;
ea6ba10b 633 void __iomem *mmio_base;
1da177e4
LT		 634 unsigned int board_idx = (unsigned int) ent->driver_data;
635 int pci_dev_busy = 0;
636 int rc;
637
638 if (!printed_version++)
a9524a76 639 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4
LT		 640
641 /*
642 * If this driver happens to only be useful on Apple's K2, then
643 * we should check that here as it has a normal Serverworks ID
644 */
645 rc = pci_enable_device(pdev);
646 if (rc)
647 return rc;
648
649 rc = pci_request_regions(pdev, DRV_NAME);
650 if (rc) {
651 pci_dev_busy = 1;
652 goto err_out;
653 }
654
655 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
656 if (rc)
657 goto err_out_regions;
658 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
659 if (rc)
660 goto err_out_regions;
661
662 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
663 if (probe_ent == NULL) {
664 rc = -ENOMEM;
665 goto err_out_regions;
666 }
667
668 memset(probe_ent, 0, sizeof(*probe_ent));
669 probe_ent->dev = pci_dev_to_dev(pdev);
670 INIT_LIST_HEAD(&probe_ent->node);
671
374b1873 672 mmio_base = pci_iomap(pdev, 3, 0);
1da177e4
LT		 673 if (mmio_base == NULL) {
674 rc = -ENOMEM;
675 goto err_out_free_ent;
676 }
677 base = (unsigned long) mmio_base;
678
679 probe_ent->sht = pdc_port_info[board_idx].sht;
680 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
681 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
682 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
683 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
684 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
685
686 probe_ent->irq = pdev->irq;
687 probe_ent->irq_flags = SA_SHIRQ;
688 probe_ent->mmio_base = mmio_base;
689
690 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
691 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
692
693 probe_ent->port[0].scr_addr = base + 0x400;
694 probe_ent->port[1].scr_addr = base + 0x500;
695
696 /* notice 4-port boards */
697 switch (board_idx) {
698 case board_20319:
699 probe_ent->n_ports = 4;
700
701 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
702 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
703
704 probe_ent->port[2].scr_addr = base + 0x600;
705 probe_ent->port[3].scr_addr = base + 0x700;
706 break;
707 case board_2037x:
6c9e5eb5 708 probe_ent->n_ports = 2;
1da177e4 709 break;
f497ba73
TL		 710 case board_20619:
711 probe_ent->n_ports = 4;
712
713 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
714 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
715
716 probe_ent->port[2].scr_addr = base + 0x600;
717 probe_ent->port[3].scr_addr = base + 0x700;
6c9e5eb5 718 break;
1da177e4
LT		 719 default:
720 BUG();
721 break;
722 }
723
724 pci_set_master(pdev);
725
726 /* initialize adapter */
727 pdc_host_init(board_idx, probe_ent);
728
729 /* FIXME: check ata_device_add return value */
730 ata_device_add(probe_ent);
731 kfree(probe_ent);
732
733 return 0;
734
735err_out_free_ent:
736 kfree(probe_ent);
737err_out_regions:
738 pci_release_regions(pdev);
739err_out:
740 if (!pci_dev_busy)
741 pci_disable_device(pdev);
742 return rc;
743}
744
745
746static int __init pdc_ata_init(void)
747{
748 return pci_module_init(&pdc_ata_pci_driver);
749}
750
751
752static void __exit pdc_ata_exit(void)
753{
754 pci_unregister_driver(&pdc_ata_pci_driver);
755}
756
757
758MODULE_AUTHOR("Jeff Garzik");
f497ba73 759MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1da177e4
LT		 760MODULE_LICENSE("GPL");
761MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
762MODULE_VERSION(DRV_VERSION);
763
764module_init(pdc_ata_init);
765module_exit(pdc_ata_exit);
kernel source for telekom puls (alcatel/mediatek)