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[SCSI] qla4xxx: remove unused ddb flag DF_NO_RELOGIN
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / qla4xxx / ql4_def.h
CommitLineData
afaf5a2d
DS		 1/*
2 * QLogic iSCSI HBA Driver
7d01d069 3 * Copyright (c) 2003-2010 QLogic Corporation
afaf5a2d
DS		 4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#ifndef __QL4_DEF_H
9#define __QL4_DEF_H
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/dmapool.h>
21#include <linux/mempool.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/mutex.h>
7b3595df 27#include <linux/aer.h>
afaf5a2d
DS		 28
29#include <net/tcp.h>
30#include <scsi/scsi.h>
31#include <scsi/scsi_host.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_cmnd.h>
34#include <scsi/scsi_transport.h>
35#include <scsi/scsi_transport_iscsi.h>
36
f4f5df23
VC		 37#include "ql4_dbg.h"
38#include "ql4_nx.h"
afaf5a2d
DS		 39
40#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
41#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
42#endif
43
44#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
45#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
d915058f
DS		 46#endif
47
48#ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
49#define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
50#endif
afaf5a2d 51
f4f5df23
VC		 52#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
53#define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
54#endif
55
afaf5a2d
DS		 56#define QLA_SUCCESS 0
57#define QLA_ERROR 1
58
59/*
60 * Data bit definitions
61 */
62#define BIT_0 0x1
63#define BIT_1 0x2
64#define BIT_2 0x4
65#define BIT_3 0x8
66#define BIT_4 0x10
67#define BIT_5 0x20
68#define BIT_6 0x40
69#define BIT_7 0x80
70#define BIT_8 0x100
71#define BIT_9 0x200
72#define BIT_10 0x400
73#define BIT_11 0x800
74#define BIT_12 0x1000
75#define BIT_13 0x2000
76#define BIT_14 0x4000
77#define BIT_15 0x8000
78#define BIT_16 0x10000
79#define BIT_17 0x20000
80#define BIT_18 0x40000
81#define BIT_19 0x80000
82#define BIT_20 0x100000
83#define BIT_21 0x200000
84#define BIT_22 0x400000
85#define BIT_23 0x800000
86#define BIT_24 0x1000000
87#define BIT_25 0x2000000
88#define BIT_26 0x4000000
89#define BIT_27 0x8000000
90#define BIT_28 0x10000000
91#define BIT_29 0x20000000
92#define BIT_30 0x40000000
93#define BIT_31 0x80000000
94
f4f5df23
VC		 95/**
96 * Macros to help code, maintain, etc.
97 **/
98#define ql4_printk(level, ha, format, arg...) \
99 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
100
101
afaf5a2d
DS		 102/*
103 * Host adapter default definitions
104 ***********************************/
105#define MAX_HBAS 16
106#define MAX_BUSES 1
f4f5df23 107#define MAX_TARGETS MAX_DEV_DB_ENTRIES
afaf5a2d
DS		 108#define MAX_LUNS 0xffff
109#define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */
f4f5df23 110#define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
afaf5a2d
DS		 111#define MAX_PDU_ENTRIES 32
112#define INVALID_ENTRY 0xFFFF
113#define MAX_CMDS_TO_RISC 1024
114#define MAX_SRBS MAX_CMDS_TO_RISC
115#define MBOX_AEN_REG_COUNT 5
116#define MAX_INIT_RETRIES 5
afaf5a2d
DS		 117
118/*
119 * Buffer sizes
120 */
121#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
122#define RESPONSE_QUEUE_DEPTH 64
123#define QUEUE_SIZE 64
124#define DMA_BUFFER_SIZE 512
125
126/*
127 * Misc
128 */
129#define MAC_ADDR_LEN 6 /* in bytes */
130#define IP_ADDR_LEN 4 /* in bytes */
2a49a78e 131#define IPv6_ADDR_LEN 16 /* IPv6 address size */
afaf5a2d
DS		 132#define DRIVER_NAME "qla4xxx"
133
134#define MAX_LINKED_CMDS_PER_LUN 3
dbaf82ec 135#define MAX_REQS_SERVICED_PER_INTR 1
afaf5a2d
DS		 136
137#define ISCSI_IPADDR_SIZE 4 /* IP address size */
b1c11812 138#define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
5c8bfc94 139#define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
afaf5a2d 140
3013cea8
VC		 141#define QL4_SESS_RECOVERY_TMO 30 /* iSCSI session */
142 /* recovery timeout */
143
afaf5a2d
DS		 144#define LSDW(x) ((u32)((u64)(x)))
145#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
146
147/*
148 * Retry & Timeout Values
149 */
150#define MBOX_TOV 60
151#define SOFT_RESET_TOV 30
152#define RESET_INTR_TOV 3
153#define SEMAPHORE_TOV 10
f4f5df23 154#define ADAPTER_INIT_TOV 30
afaf5a2d
DS		 155#define ADAPTER_RESET_TOV 180
156#define EXTEND_CMD_TOV 60
157#define WAIT_CMD_TOV 30
158#define EH_WAIT_CMD_TOV 120
159#define FIRMWARE_UP_TOV 60
160#define RESET_FIRMWARE_TOV 30
161#define LOGOUT_TOV 10
162#define IOCB_TOV_MARGIN 10
163#define RELOGIN_TOV 18
164#define ISNS_DEREG_TOV 5
f581a3f7 165#define HBA_ONLINE_TOV 30
afaf5a2d
DS		 166
167#define MAX_RESET_HA_RETRIES 2
168
5369887a
VC		 169#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
170
afaf5a2d
DS		 171/*
172 * SCSI Request Block structure (srb) that is placed
173 * on cmd->SCp location of every I/O [We have 22 bytes available]
174 */
175struct srb {
176 struct list_head list; /* (8) */
177 struct scsi_qla_host *ha; /* HA the SP is queued on */
6790d4fe 178 struct ddb_entry *ddb;
afaf5a2d
DS		 179 uint16_t flags; /* (1) Status flags. */
180
181#define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
182#define SRB_GOT_SENSE BIT_4 /* sense data recieved. */
183 uint8_t state; /* (1) Status flags. */
184
185#define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
186#define SRB_FREE_STATE 1
187#define SRB_ACTIVE_STATE 3
188#define SRB_ACTIVE_TIMEOUT_STATE 4
189#define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
190
191 struct scsi_cmnd *cmd; /* (4) SCSI command block */
192 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
09a0f719 193 struct kref srb_ref; /* reference count for this srb */
afaf5a2d
DS		 194 uint8_t err_id; /* error id */
195#define SRB_ERR_PORT 1 /* Request failed because "port down" */
196#define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
197#define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
198#define SRB_ERR_OTHER 4
199
200 uint16_t reserved;
201 uint16_t iocb_tov;
202 uint16_t iocb_cnt; /* Number of used iocbs */
203 uint16_t cc_stat;
94bced3c
KH		 204
205 /* Used for extended sense / status continuation */
206 uint8_t *req_sense_ptr;
207 uint16_t req_sense_len;
208 uint16_t reserved2;
afaf5a2d
DS		 209};
210
5c8bfc94
DS		 211/*
212 * Asynchronous Event Queue structure
213 */
214struct aen {
215 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
216};
217
218struct ql4_aen_log {
219 int count;
220 struct aen entry[MAX_AEN_ENTRIES];
221};
222
223/*
224 * Device Database (DDB) structure
225 */
afaf5a2d
DS		 226struct ddb_entry {
227 struct list_head list; /* ddb list */
228 struct scsi_qla_host *ha;
229 struct iscsi_cls_session *sess;
230 struct iscsi_cls_conn *conn;
231
232 atomic_t state; /* DDB State */
233
234 unsigned long flags; /* DDB Flags */
235
afaf5a2d 236 uint16_t fw_ddb_index; /* DDB firmware index */
2a49a78e 237 uint16_t options;
afaf5a2d
DS		 238 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
239
240 uint32_t CmdSn;
241 uint16_t target_session_id;
242 uint16_t connection_id;
243 uint16_t exe_throttle; /* Max mumber of cmds outstanding
244 * simultaneously */
245 uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to
246 * complete */
247 uint16_t default_relogin_timeout; /* Max time to wait for
248 * relogin to complete */
249 uint16_t tcp_source_port_num;
250 uint32_t default_time2wait; /* Default Min time between
251 * relogins (+aens) */
252
afaf5a2d
DS		 253 atomic_t retry_relogin_timer; /* Min Time between relogins
254 * (4000 only) */
255 atomic_t relogin_timer; /* Max Time to wait for relogin to complete */
256 atomic_t relogin_retry_count; /* Num of times relogin has been
257 * retried */
258
259 uint16_t port;
260 uint32_t tpgt;
2a49a78e 261 uint8_t ip_addr[IP_ADDR_LEN];
afaf5a2d
DS		 262 uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */
263 uint8_t iscsi_alias[0x20];
41bbdbeb 264 uint8_t isid[6];
2a49a78e
VC		 265 uint16_t iscsi_max_burst_len;
266 uint16_t iscsi_max_outsnd_r2t;
267 uint16_t iscsi_first_burst_len;
268 uint16_t iscsi_max_rcv_data_seg_len;
269 uint16_t iscsi_max_snd_data_seg_len;
270
271 struct in6_addr remote_ipv6_addr;
272 struct in6_addr link_local_ipv6_addr;
afaf5a2d
DS		 273};
274
275/*
276 * DDB states.
277 */
278#define DDB_STATE_DEAD 0 /* We can no longer talk to
279 * this device */
280#define DDB_STATE_ONLINE 1 /* Device ready to accept
281 * commands */
282#define DDB_STATE_MISSING 2 /* Device logged off, trying
283 * to re-login */
284
285/*
286 * DDB flags.
287 */
288#define DF_RELOGIN 0 /* Relogin to device */
afaf5a2d
DS		 289#define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
290#define DF_FO_MASKED 3
291
afaf5a2d
DS		 292
293#include "ql4_fw.h"
294#include "ql4_nvram.h"
295
f4f5df23
VC		 296struct ql82xx_hw_data {
297 /* Offsets for flash/nvram access (set to ~0 if not used). */
298 uint32_t flash_conf_off;
299 uint32_t flash_data_off;
300
301 uint32_t fdt_wrt_disable;
302 uint32_t fdt_erase_cmd;
303 uint32_t fdt_block_size;
304 uint32_t fdt_unprotect_sec_cmd;
305 uint32_t fdt_protect_sec_cmd;
306
307 uint32_t flt_region_flt;
308 uint32_t flt_region_fdt;
309 uint32_t flt_region_boot;
310 uint32_t flt_region_bootload;
311 uint32_t flt_region_fw;
312 uint32_t reserved;
313};
314
315struct qla4_8xxx_legacy_intr_set {
316 uint32_t int_vec_bit;
317 uint32_t tgt_status_reg;
318 uint32_t tgt_mask_reg;
319 uint32_t pci_int_reg;
320};
321
322/* MSI-X Support */
323
324#define QLA_MSIX_DEFAULT 0x00
325#define QLA_MSIX_RSP_Q 0x01
326
327#define QLA_MSIX_ENTRIES 2
328#define QLA_MIDX_DEFAULT 0
329#define QLA_MIDX_RSP_Q 1
330
331struct ql4_msix_entry {
332 int have_irq;
333 uint16_t msix_vector;
334 uint16_t msix_entry;
335};
336
337/*
338 * ISP Operations
339 */
340struct isp_operations {
341 int (*iospace_config) (struct scsi_qla_host *ha);
342 void (*pci_config) (struct scsi_qla_host *);
343 void (*disable_intrs) (struct scsi_qla_host *);
344 void (*enable_intrs) (struct scsi_qla_host *);
345 int (*start_firmware) (struct scsi_qla_host *);
346 irqreturn_t (*intr_handler) (int , void *);
347 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
348 int (*reset_chip) (struct scsi_qla_host *);
349 int (*reset_firmware) (struct scsi_qla_host *);
350 void (*queue_iocb) (struct scsi_qla_host *);
351 void (*complete_iocb) (struct scsi_qla_host *);
352 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
353 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
354 int (*get_sys_info) (struct scsi_qla_host *);
355};
356
afaf5a2d
DS		 357/*
358 * Linux Host Adapter structure
359 */
360struct scsi_qla_host {
361 /* Linux adapter configuration data */
afaf5a2d
DS		 362 unsigned long flags;
363
5c8bfc94
DS		 364#define AF_ONLINE 0 /* 0x00000001 */
365#define AF_INIT_DONE 1 /* 0x00000002 */
366#define AF_MBOX_COMMAND 2 /* 0x00000004 */
367#define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
f4f5df23 368#define AF_DPC_SCHEDULED 5 /* 0x00000020 */
5c8bfc94
DS		 369#define AF_INTERRUPTS_ON 6 /* 0x00000040 */
370#define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
371#define AF_LINK_UP 8 /* 0x00000100 */
372#define AF_IRQ_ATTACHED 10 /* 0x00000400 */
373#define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
f4f5df23
VC		 374#define AF_HBA_GOING_AWAY 12 /* 0x00001000 */
375#define AF_INTx_ENABLED 15 /* 0x00008000 */
376#define AF_MSI_ENABLED 16 /* 0x00010000 */
377#define AF_MSIX_ENABLED 17 /* 0x00020000 */
378#define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
21033639 379#define AF_FW_RECOVERY 19 /* 0x00080000 */
2232be0d
LC		 380#define AF_EEH_BUSY 20 /* 0x00100000 */
381#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
afaf5a2d
DS		 382
383 unsigned long dpc_flags;
384
5c8bfc94
DS		 385#define DPC_RESET_HA 1 /* 0x00000002 */
386#define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
387#define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
f4f5df23 388#define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
5c8bfc94
DS		 389#define DPC_RESET_HA_INTR 5 /* 0x00000020 */
390#define DPC_ISNS_RESTART 7 /* 0x00000080 */
391#define DPC_AEN 9 /* 0x00000200 */
392#define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
065aa1b4 393#define DPC_LINK_CHANGED 18 /* 0x00040000 */
f4f5df23
VC		 394#define DPC_RESET_ACTIVE 20 /* 0x00040000 */
395#define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
396#define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
397
5c8bfc94
DS		 398
399 struct Scsi_Host *host; /* pointer to host data */
400 uint32_t tot_ddbs;
afaf5a2d 401
f4f5df23 402 uint16_t iocb_cnt;
afaf5a2d
DS		 403
404 /* SRB cache. */
405#define SRB_MIN_REQ 128
406 mempool_t *srb_mempool;
407
408 /* pci information */
409 struct pci_dev *pdev;
410
411 struct isp_reg __iomem *reg; /* Base I/O address */
412 unsigned long pio_address;
413 unsigned long pio_length;
414#define MIN_IOBASE_LEN 0x100
415
416 uint16_t req_q_count;
afaf5a2d
DS		 417
418 unsigned long host_no;
419
420 /* NVRAM registers */
421 struct eeprom_data *nvram;
422 spinlock_t hardware_lock ____cacheline_aligned;
f4f5df23 423 uint32_t eeprom_cmd_data;
afaf5a2d
DS		 424
425 /* Counters for general statistics */
d915058f 426 uint64_t isr_count;
afaf5a2d
DS		 427 uint64_t adapter_error_count;
428 uint64_t device_error_count;
429 uint64_t total_io_count;
430 uint64_t total_mbytes_xferred;
431 uint64_t link_failure_count;
432 uint64_t invalid_crc_count;
d915058f 433 uint32_t bytes_xfered;
afaf5a2d
DS		 434 uint32_t spurious_int_count;
435 uint32_t aborted_io_count;
436 uint32_t io_timeout_count;
437 uint32_t mailbox_timeout_count;
438 uint32_t seconds_since_last_intr;
439 uint32_t seconds_since_last_heartbeat;
440 uint32_t mac_index;
441
442 /* Info Needed for Management App */
443 /* --- From GetFwVersion --- */
444 uint32_t firmware_version[2];
445 uint32_t patch_number;
446 uint32_t build_number;
5c8bfc94 447 uint32_t board_id;
afaf5a2d
DS		 448
449 /* --- From Init_FW --- */
450 /* init_cb_t *init_cb; */
451 uint16_t firmware_options;
452 uint16_t tcp_options;
453 uint8_t ip_address[IP_ADDR_LEN];
454 uint8_t subnet_mask[IP_ADDR_LEN];
455 uint8_t gateway[IP_ADDR_LEN];
456 uint8_t alias[32];
457 uint8_t name_string[256];
458 uint8_t heartbeat_interval;
afaf5a2d
DS		 459
460 /* --- From FlashSysInfo --- */
461 uint8_t my_mac[MAC_ADDR_LEN];
462 uint8_t serial_number[16];
463
464 /* --- From GetFwState --- */
465 uint32_t firmware_state;
afaf5a2d
DS		 466 uint32_t addl_fw_state;
467
468 /* Linux kernel thread */
469 struct workqueue_struct *dpc_thread;
470 struct work_struct dpc_work;
471
472 /* Linux timer thread */
473 struct timer_list timer;
474 uint32_t timer_active;
475
476 /* Recovery Timers */
afaf5a2d
DS		 477 atomic_t check_relogin_timeouts;
478 uint32_t retry_reset_ha_cnt;
479 uint32_t isp_reset_timer; /* reset test timer */
480 uint32_t nic_reset_timer; /* simulated nic reset test timer */
481 int eh_start;
482 struct list_head free_srb_q;
483 uint16_t free_srb_q_count;
484 uint16_t num_srbs_allocated;
485
486 /* DMA Memory Block */
487 void *queues;
488 dma_addr_t queues_dma;
489 unsigned long queues_len;
490
491#define MEM_ALIGN_VALUE \
492 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
493 sizeof(struct queue_entry))
494 /* request and response queue variables */
495 dma_addr_t request_dma;
496 struct queue_entry *request_ring;
497 struct queue_entry *request_ptr;
498 dma_addr_t response_dma;
499 struct queue_entry *response_ring;
500 struct queue_entry *response_ptr;
501 dma_addr_t shadow_regs_dma;
502 struct shadow_regs *shadow_regs;
503 uint16_t request_in; /* Current indexes. */
504 uint16_t request_out;
505 uint16_t response_in;
506 uint16_t response_out;
507
508 /* aen queue variables */
509 uint16_t aen_q_count; /* Number of available aen_q entries */
510 uint16_t aen_in; /* Current indexes */
511 uint16_t aen_out;
512 struct aen aen_q[MAX_AEN_ENTRIES];
513
5c8bfc94
DS		 514 struct ql4_aen_log aen_log;/* tracks all aens */
515
afaf5a2d
DS		 516 /* This mutex protects several threads to do mailbox commands
517 * concurrently.
518 */
519 struct mutex mbox_sem;
afaf5a2d
DS		 520
521 /* temporary mailbox status registers */
522 volatile uint8_t mbox_status_count;
523 volatile uint32_t mbox_status[MBOX_REG_COUNT];
524
525 /* local device database list (contains internal ddb entries) */
526 struct list_head ddb_list;
527
528 /* Map ddb_list entry by FW ddb index */
529 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
530
94bced3c
KH		 531 /* Saved srb for status continuation entry processing */
532 struct srb *status_srb;
2a49a78e
VC		 533
534 /* IPv6 support info from InitFW */
535 uint8_t acb_version;
536 uint8_t ipv4_addr_state;
537 uint16_t ipv4_options;
538
539 uint32_t resvd2;
540 uint32_t ipv6_options;
541 uint32_t ipv6_addl_options;
542 uint8_t ipv6_link_local_state;
543 uint8_t ipv6_addr0_state;
544 uint8_t ipv6_addr1_state;
545 uint8_t ipv6_default_router_state;
546 struct in6_addr ipv6_link_local_addr;
547 struct in6_addr ipv6_addr0;
548 struct in6_addr ipv6_addr1;
549 struct in6_addr ipv6_default_router_addr;
f4f5df23
VC		 550
551 /* qla82xx specific fields */
552 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */
553 unsigned long nx_pcibase; /* Base I/O address */
554 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
555 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
556 unsigned long first_page_group_start;
557 unsigned long first_page_group_end;
558
559 uint32_t crb_win;
560 uint32_t curr_window;
561 uint32_t ddr_mn_window;
562 unsigned long mn_win_crb;
563 unsigned long ms_win_crb;
564 int qdr_sn_window;
565 rwlock_t hw_lock;
566 uint16_t func_num;
567 int link_width;
568
569 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
570 u32 nx_crb_mask;
571
572 uint8_t revision_id;
573 uint32_t fw_heartbeat_counter;
574
575 struct isp_operations *isp_ops;
576 struct ql82xx_hw_data hw;
577
578 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
579
580 uint32_t nx_dev_init_timeout;
581 uint32_t nx_reset_timeout;
582
583 struct completion mbx_intr_comp;
afaf5a2d
DS		 584};
585
2a49a78e
VC		 586static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
587{
588 return ((ha->ipv4_options & IPOPT_IPv4_PROTOCOL_ENABLE) != 0);
589}
590
591static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
592{
593 return ((ha->ipv6_options & IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
594}
595
afaf5a2d
DS		 596static inline int is_qla4010(struct scsi_qla_host *ha)
597{
598 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
599}
600
601static inline int is_qla4022(struct scsi_qla_host *ha)
602{
603 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
604}
605
d915058f
DS		 606static inline int is_qla4032(struct scsi_qla_host *ha)
607{
608 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
609}
610
f4f5df23
VC		 611static inline int is_qla8022(struct scsi_qla_host *ha)
612{
613 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
614}
615
2232be0d
LC		 616/* Note: Currently AER/EEH is now supported only for 8022 cards
617 * This function needs to be updated when AER/EEH is enabled
618 * for other cards.
619 */
620static inline int is_aer_supported(struct scsi_qla_host *ha)
621{
622 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
623}
624
afaf5a2d
DS		 625static inline int adapter_up(struct scsi_qla_host *ha)
626{
627 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
628 (test_bit(AF_LINK_UP, &ha->flags) != 0);
629}
630
631static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
632{
633 return (struct scsi_qla_host *)shost->hostdata;
634}
635
636static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
637{
d915058f
DS		 638 return (is_qla4010(ha) ?
639 &ha->reg->u1.isp4010.nvram :
640 &ha->reg->u1.isp4022.semaphore);
afaf5a2d
DS		 641}
642
643static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
644{
d915058f
DS		 645 return (is_qla4010(ha) ?
646 &ha->reg->u1.isp4010.nvram :
647 &ha->reg->u1.isp4022.nvram);
afaf5a2d
DS		 648}
649
650static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
651{
d915058f
DS		 652 return (is_qla4010(ha) ?
653 &ha->reg->u2.isp4010.ext_hw_conf :
654 &ha->reg->u2.isp4022.p0.ext_hw_conf);
afaf5a2d
DS		 655}
656
657static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
658{
d915058f
DS		 659 return (is_qla4010(ha) ?
660 &ha->reg->u2.isp4010.port_status :
661 &ha->reg->u2.isp4022.p0.port_status);
afaf5a2d
DS		 662}
663
664static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
665{
d915058f
DS		 666 return (is_qla4010(ha) ?
667 &ha->reg->u2.isp4010.port_ctrl :
668 &ha->reg->u2.isp4022.p0.port_ctrl);
afaf5a2d
DS		 669}
670
671static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
672{
d915058f
DS		 673 return (is_qla4010(ha) ?
674 &ha->reg->u2.isp4010.port_err_status :
675 &ha->reg->u2.isp4022.p0.port_err_status);
afaf5a2d
DS		 676}
677
678static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
679{
d915058f
DS		 680 return (is_qla4010(ha) ?
681 &ha->reg->u2.isp4010.gp_out :
682 &ha->reg->u2.isp4022.p0.gp_out);
afaf5a2d
DS		 683}
684
685static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
686{
d915058f
DS		 687 return (is_qla4010(ha) ?
688 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
689 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
afaf5a2d
DS		 690}
691
692int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
693void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
694int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
695
696static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
697{
d915058f
DS		 698 if (is_qla4010(a))
699 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
700 QL4010_FLASH_SEM_BITS);
701 else
afaf5a2d
DS		 702 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
703 (QL4022_RESOURCE_BITS_BASE_CODE |
704 (a->mac_index)) << 13);
afaf5a2d
DS		 705}
706
707static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
708{
d915058f 709 if (is_qla4010(a))
afaf5a2d 710 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
d915058f
DS		 711 else
712 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
afaf5a2d
DS		 713}
714
715static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
716{
d915058f
DS		 717 if (is_qla4010(a))
718 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
719 QL4010_NVRAM_SEM_BITS);
720 else
afaf5a2d
DS		 721 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
722 (QL4022_RESOURCE_BITS_BASE_CODE |
723 (a->mac_index)) << 10);
afaf5a2d
DS		 724}
725
726static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
727{
d915058f 728 if (is_qla4010(a))
afaf5a2d 729 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
d915058f
DS		 730 else
731 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
afaf5a2d
DS		 732}
733
734static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
735{
d915058f
DS		 736 if (is_qla4010(a))
737 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
738 QL4010_DRVR_SEM_BITS);
739 else
afaf5a2d
DS		 740 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
741 (QL4022_RESOURCE_BITS_BASE_CODE |
742 (a->mac_index)) << 1);
afaf5a2d
DS		 743}
744
745static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
746{
d915058f 747 if (is_qla4010(a))
afaf5a2d 748 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
d915058f
DS		 749 else
750 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
afaf5a2d
DS		 751}
752
753/*---------------------------------------------------------------------------*/
754
755/* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
756#define PRESERVE_DDB_LIST 0
757#define REBUILD_DDB_LIST 1
758
759/* Defines for process_aen() */
760#define PROCESS_ALL_AENS 0
761#define FLUSH_DDB_CHANGED_AENS 1
afaf5a2d 762
afaf5a2d 763#endif /*_QLA4XXX_H */
kernel source for telekom puls (alcatel/mediatek)