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[SCSI] qla2xxx: Handle outstanding mbx cmds on hung f/w scenarios.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / qla2xxx / qla_nx.c
CommitLineData
a9083016
GM		 1/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7#include "qla_def.h"
8#include <linux/delay.h>
9#include <linux/pci.h>
10
11#define MASK(n) ((1ULL<<(n))-1)
12#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
13 ((addr >> 25) & 0x3ff))
14#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
15 ((addr >> 25) & 0x3ff))
16#define MS_WIN(addr) (addr & 0x0ffc0000)
17#define QLA82XX_PCI_MN_2M (0)
18#define QLA82XX_PCI_MS_2M (0x80000)
19#define QLA82XX_PCI_OCM0_2M (0xc0000)
20#define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
21#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
22
23/* CRB window related */
24#define CRB_BLK(off) ((off >> 20) & 0x3f)
25#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
26#define CRB_WINDOW_2M (0x130060)
27#define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
28#define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
29 ((off) & 0xf0000))
30#define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
31#define CRB_INDIRECT_2M (0x1e0000UL)
32
a9083016
GM		 33#define MAX_CRB_XFORM 60
34static unsigned long crb_addr_xform[MAX_CRB_XFORM];
35int qla82xx_crb_table_initialized;
36
37#define qla82xx_crb_addr_transform(name) \
38 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
39 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
40
41static void qla82xx_crb_addr_transform_setup(void)
42{
43 qla82xx_crb_addr_transform(XDMA);
44 qla82xx_crb_addr_transform(TIMR);
45 qla82xx_crb_addr_transform(SRE);
46 qla82xx_crb_addr_transform(SQN3);
47 qla82xx_crb_addr_transform(SQN2);
48 qla82xx_crb_addr_transform(SQN1);
49 qla82xx_crb_addr_transform(SQN0);
50 qla82xx_crb_addr_transform(SQS3);
51 qla82xx_crb_addr_transform(SQS2);
52 qla82xx_crb_addr_transform(SQS1);
53 qla82xx_crb_addr_transform(SQS0);
54 qla82xx_crb_addr_transform(RPMX7);
55 qla82xx_crb_addr_transform(RPMX6);
56 qla82xx_crb_addr_transform(RPMX5);
57 qla82xx_crb_addr_transform(RPMX4);
58 qla82xx_crb_addr_transform(RPMX3);
59 qla82xx_crb_addr_transform(RPMX2);
60 qla82xx_crb_addr_transform(RPMX1);
61 qla82xx_crb_addr_transform(RPMX0);
62 qla82xx_crb_addr_transform(ROMUSB);
63 qla82xx_crb_addr_transform(SN);
64 qla82xx_crb_addr_transform(QMN);
65 qla82xx_crb_addr_transform(QMS);
66 qla82xx_crb_addr_transform(PGNI);
67 qla82xx_crb_addr_transform(PGND);
68 qla82xx_crb_addr_transform(PGN3);
69 qla82xx_crb_addr_transform(PGN2);
70 qla82xx_crb_addr_transform(PGN1);
71 qla82xx_crb_addr_transform(PGN0);
72 qla82xx_crb_addr_transform(PGSI);
73 qla82xx_crb_addr_transform(PGSD);
74 qla82xx_crb_addr_transform(PGS3);
75 qla82xx_crb_addr_transform(PGS2);
76 qla82xx_crb_addr_transform(PGS1);
77 qla82xx_crb_addr_transform(PGS0);
78 qla82xx_crb_addr_transform(PS);
79 qla82xx_crb_addr_transform(PH);
80 qla82xx_crb_addr_transform(NIU);
81 qla82xx_crb_addr_transform(I2Q);
82 qla82xx_crb_addr_transform(EG);
83 qla82xx_crb_addr_transform(MN);
84 qla82xx_crb_addr_transform(MS);
85 qla82xx_crb_addr_transform(CAS2);
86 qla82xx_crb_addr_transform(CAS1);
87 qla82xx_crb_addr_transform(CAS0);
88 qla82xx_crb_addr_transform(CAM);
89 qla82xx_crb_addr_transform(C2C1);
90 qla82xx_crb_addr_transform(C2C0);
91 qla82xx_crb_addr_transform(SMB);
92 qla82xx_crb_addr_transform(OCM0);
93 /*
94 * Used only in P3 just define it for P2 also.
95 */
96 qla82xx_crb_addr_transform(I2C0);
97
98 qla82xx_crb_table_initialized = 1;
99}
100
101struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
102 {{{0, 0, 0, 0} } },
103 {{{1, 0x0100000, 0x0102000, 0x120000},
104 {1, 0x0110000, 0x0120000, 0x130000},
105 {1, 0x0120000, 0x0122000, 0x124000},
106 {1, 0x0130000, 0x0132000, 0x126000},
107 {1, 0x0140000, 0x0142000, 0x128000},
108 {1, 0x0150000, 0x0152000, 0x12a000},
109 {1, 0x0160000, 0x0170000, 0x110000},
110 {1, 0x0170000, 0x0172000, 0x12e000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {1, 0x01e0000, 0x01e0800, 0x122000},
118 {0, 0x0000000, 0x0000000, 0x000000} } } ,
119 {{{1, 0x0200000, 0x0210000, 0x180000} } },
120 {{{0, 0, 0, 0} } },
121 {{{1, 0x0400000, 0x0401000, 0x169000} } },
122 {{{1, 0x0500000, 0x0510000, 0x140000} } },
123 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
124 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
125 {{{1, 0x0800000, 0x0802000, 0x170000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {1, 0x08f0000, 0x08f2000, 0x172000} } },
141 {{{1, 0x0900000, 0x0902000, 0x174000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {1, 0x09f0000, 0x09f2000, 0x176000} } },
157 {{{0, 0x0a00000, 0x0a02000, 0x178000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
173 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
189 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
190 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
191 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
192 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
193 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
194 {{{1, 0x1100000, 0x1101000, 0x160000} } },
195 {{{1, 0x1200000, 0x1201000, 0x161000} } },
196 {{{1, 0x1300000, 0x1301000, 0x162000} } },
197 {{{1, 0x1400000, 0x1401000, 0x163000} } },
198 {{{1, 0x1500000, 0x1501000, 0x165000} } },
199 {{{1, 0x1600000, 0x1601000, 0x166000} } },
200 {{{0, 0, 0, 0} } },
201 {{{0, 0, 0, 0} } },
202 {{{0, 0, 0, 0} } },
203 {{{0, 0, 0, 0} } },
204 {{{0, 0, 0, 0} } },
205 {{{0, 0, 0, 0} } },
206 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
207 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
208 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
209 {{{0} } },
210 {{{1, 0x2100000, 0x2102000, 0x120000},
211 {1, 0x2110000, 0x2120000, 0x130000},
212 {1, 0x2120000, 0x2122000, 0x124000},
213 {1, 0x2130000, 0x2132000, 0x126000},
214 {1, 0x2140000, 0x2142000, 0x128000},
215 {1, 0x2150000, 0x2152000, 0x12a000},
216 {1, 0x2160000, 0x2170000, 0x110000},
217 {1, 0x2170000, 0x2172000, 0x12e000},
218 {0, 0x0000000, 0x0000000, 0x000000},
219 {0, 0x0000000, 0x0000000, 0x000000},
220 {0, 0x0000000, 0x0000000, 0x000000},
221 {0, 0x0000000, 0x0000000, 0x000000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000} } },
226 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
227 {{{0} } },
228 {{{0} } },
229 {{{0} } },
230 {{{0} } },
231 {{{0} } },
232 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
233 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
234 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
235 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
236 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
237 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
238 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
239 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
240 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
241 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
242 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
243 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
244 {{{0} } },
245 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
246 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
247 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
248 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
249 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
250 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
251 {{{0} } },
252 {{{0} } },
253 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
254 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
255 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
256};
257
258/*
259 * top 12 bits of crb internal address (hub, agent)
260 */
261unsigned qla82xx_crb_hub_agt[64] = {
262 0,
263 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
264 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
265 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
266 0,
267 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
270 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
289 0,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
292 0,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
294 0,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
297 0,
298 0,
299 0,
300 0,
301 0,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
303 0,
304 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
305 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
307 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
314 0,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
319 0,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
323 0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
325 0,
326};
327
f1af6208
GM		 328/* Device states */
329char *qdev_state[] = {
330 "Unknown",
331 "Cold",
332 "Initializing",
333 "Ready",
334 "Need Reset",
335 "Need Quiescent",
336 "Failed",
337 "Quiescent",
338};
339
a9083016
GM		 340/*
341 * In: 'off' is offset from CRB space in 128M pci map
342 * Out: 'off' is 2M pci map addr
343 * side effect: lock crb window
344 */
345static void
346qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
347{
348 u32 win_read;
349
350 ha->crb_win = CRB_HI(*off);
351 writel(ha->crb_win,
352 (void *)(CRB_WINDOW_2M + ha->nx_pcibase));
353
354 /* Read back value to make sure write has gone through before trying
355 * to use it.
356 */
357 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase));
358 if (win_read != ha->crb_win) {
359 DEBUG2(qla_printk(KERN_INFO, ha,
360 "%s: Written crbwin (0x%x) != Read crbwin (0x%x), "
361 "off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
362 }
363 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
364}
365
366static inline unsigned long
367qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
368{
369 /* See if we are currently pointing to the region we want to use next */
370 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
371 /* No need to change window. PCIX and PCIEregs are in both
372 * regs are in both windows.
373 */
374 return off;
375 }
376
377 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
378 /* We are in first CRB window */
379 if (ha->curr_window != 0)
380 WARN_ON(1);
381 return off;
382 }
383
384 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
385 /* We are in second CRB window */
386 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
387
388 if (ha->curr_window != 1)
389 return off;
390
391 /* We are in the QM or direct access
392 * register region - do nothing
393 */
394 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
395 (off < QLA82XX_PCI_CAMQM_MAX))
396 return off;
397 }
398 /* strange address given */
399 qla_printk(KERN_WARNING, ha,
400 "%s: Warning: unm_nic_pci_set_crbwindow called with"
401 " an unknown address(%llx)\n", QLA2XXX_DRIVER_NAME, off);
402 return off;
403}
404
405int
406qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
407{
408 unsigned long flags = 0;
409 int rv;
410
411 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
412
413 BUG_ON(rv == -1);
414
415 if (rv == 1) {
416 write_lock_irqsave(&ha->hw_lock, flags);
417 qla82xx_crb_win_lock(ha);
418 qla82xx_pci_set_crbwindow_2M(ha, &off);
419 }
420
421 writel(data, (void __iomem *)off);
422
423 if (rv == 1) {
424 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
425 write_unlock_irqrestore(&ha->hw_lock, flags);
426 }
427 return 0;
428}
429
430int
431qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
432{
433 unsigned long flags = 0;
434 int rv;
435 u32 data;
436
437 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
438
439 BUG_ON(rv == -1);
440
441 if (rv == 1) {
442 write_lock_irqsave(&ha->hw_lock, flags);
443 qla82xx_crb_win_lock(ha);
444 qla82xx_pci_set_crbwindow_2M(ha, &off);
445 }
446 data = RD_REG_DWORD((void __iomem *)off);
447
448 if (rv == 1) {
449 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
450 write_unlock_irqrestore(&ha->hw_lock, flags);
451 }
452 return data;
453}
454
455#define CRB_WIN_LOCK_TIMEOUT 100000000
456int qla82xx_crb_win_lock(struct qla_hw_data *ha)
457{
458 int done = 0, timeout = 0;
459
460 while (!done) {
461 /* acquire semaphore3 from PCI HW block */
462 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
463 if (done == 1)
464 break;
465 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
466 return -1;
467 timeout++;
468 }
469 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
470 return 0;
471}
472
473#define IDC_LOCK_TIMEOUT 100000000
474int qla82xx_idc_lock(struct qla_hw_data *ha)
475{
476 int i;
477 int done = 0, timeout = 0;
478
479 while (!done) {
480 /* acquire semaphore5 from PCI HW block */
481 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
482 if (done == 1)
483 break;
484 if (timeout >= IDC_LOCK_TIMEOUT)
485 return -1;
486
487 timeout++;
488
489 /* Yield CPU */
490 if (!in_interrupt())
491 schedule();
492 else {
493 for (i = 0; i < 20; i++)
494 cpu_relax();
495 }
496 }
497
498 return 0;
499}
500
501void qla82xx_idc_unlock(struct qla_hw_data *ha)
502{
503 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
504}
505
506int
507qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
508{
509 struct crb_128M_2M_sub_block_map *m;
510
511 if (*off >= QLA82XX_CRB_MAX)
512 return -1;
513
514 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
515 *off = (*off - QLA82XX_PCI_CAMQM) +
516 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
517 return 0;
518 }
519
520 if (*off < QLA82XX_PCI_CRBSPACE)
521 return -1;
522
523 *off -= QLA82XX_PCI_CRBSPACE;
524
525 /* Try direct map */
526 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
527
528 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
529 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
530 return 0;
531 }
532 /* Not in direct map, use crb window */
533 return 1;
534}
535
536/* PCI Windowing for DDR regions. */
537#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
538 (((addr) <= (high)) && ((addr) >= (low)))
539/*
540 * check memory access boundary.
541 * used by test agent. support ddr access only for now
542 */
543static unsigned long
544qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
545 unsigned long long addr, int size)
546{
547 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
548 QLA82XX_ADDR_DDR_NET_MAX) ||
549 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET,
550 QLA82XX_ADDR_DDR_NET_MAX) ||
551 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
552 return 0;
553 else
554 return 1;
555}
556
557int qla82xx_pci_set_window_warning_count;
558
559unsigned long
560qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
561{
562 int window;
563 u32 win_read;
564
565 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
566 QLA82XX_ADDR_DDR_NET_MAX)) {
567 /* DDR network side */
568 window = MN_WIN(addr);
569 ha->ddr_mn_window = window;
570 qla82xx_wr_32(ha,
571 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
572 win_read = qla82xx_rd_32(ha,
573 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
574 if ((win_read << 17) != window) {
575 qla_printk(KERN_WARNING, ha,
576 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
577 __func__, window, win_read);
578 }
579 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
580 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
581 QLA82XX_ADDR_OCM0_MAX)) {
582 unsigned int temp1;
583 if ((addr & 0x00ff800) == 0xff800) {
584 qla_printk(KERN_WARNING, ha,
585 "%s: QM access not handled.\n", __func__);
586 addr = -1UL;
587 }
588 window = OCM_WIN(addr);
589 ha->ddr_mn_window = window;
590 qla82xx_wr_32(ha,
591 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
592 win_read = qla82xx_rd_32(ha,
593 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
594 temp1 = ((window & 0x1FF) << 7) |
595 ((window & 0x0FFFE0000) >> 17);
596 if (win_read != temp1) {
597 qla_printk(KERN_WARNING, ha,
598 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x)\n",
599 __func__, temp1, win_read);
600 }
601 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
602
603 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
604 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
605 /* QDR network side */
606 window = MS_WIN(addr);
607 ha->qdr_sn_window = window;
608 qla82xx_wr_32(ha,
609 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
610 win_read = qla82xx_rd_32(ha,
611 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
612 if (win_read != window) {
613 qla_printk(KERN_WARNING, ha,
614 "%s: Written MSwin (0x%x) != Read MSwin (0x%x)\n",
615 __func__, window, win_read);
616 }
617 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
618 } else {
619 /*
620 * peg gdb frequently accesses memory that doesn't exist,
621 * this limits the chit chat so debugging isn't slowed down.
622 */
623 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
624 (qla82xx_pci_set_window_warning_count%64 == 0)) {
625 qla_printk(KERN_WARNING, ha,
626 "%s: Warning:%s Unknown address range!\n", __func__,
627 QLA2XXX_DRIVER_NAME);
628 }
629 addr = -1UL;
630 }
631 return addr;
632}
633
634/* check if address is in the same windows as the previous access */
635static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
636 unsigned long long addr)
637{
638 int window;
639 unsigned long long qdr_max;
640
641 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
642
643 /* DDR network side */
644 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
645 QLA82XX_ADDR_DDR_NET_MAX))
646 BUG();
647 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
648 QLA82XX_ADDR_OCM0_MAX))
649 return 1;
650 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
651 QLA82XX_ADDR_OCM1_MAX))
652 return 1;
653 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
654 /* QDR network side */
655 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
656 if (ha->qdr_sn_window == window)
657 return 1;
658 }
659 return 0;
660}
661
662static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
663 u64 off, void *data, int size)
664{
665 unsigned long flags;
f1af6208 666 void *addr = NULL;
a9083016
GM		 667 int ret = 0;
668 u64 start;
669 uint8_t *mem_ptr = NULL;
670 unsigned long mem_base;
671 unsigned long mem_page;
672
673 write_lock_irqsave(&ha->hw_lock, flags);
674
675 /*
676 * If attempting to access unknown address or straddle hw windows,
677 * do not access.
678 */
679 start = qla82xx_pci_set_window(ha, off);
680 if ((start == -1UL) ||
681 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
682 write_unlock_irqrestore(&ha->hw_lock, flags);
683 qla_printk(KERN_ERR, ha,
684 "%s out of bound pci memory access. "
685 "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off);
686 return -1;
687 }
688
f1af6208
GM		 689 write_unlock_irqrestore(&ha->hw_lock, flags);
690 mem_base = pci_resource_start(ha->pdev, 0);
691 mem_page = start & PAGE_MASK;
692 /* Map two pages whenever user tries to access addresses in two
693 * consecutive pages.
694 */
695 if (mem_page != ((start + size - 1) & PAGE_MASK))
696 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
697 else
698 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
699 if (mem_ptr == 0UL) {
700 *(u8 *)data = 0;
701 return -1;
a9083016 702 }
f1af6208
GM		 703 addr = mem_ptr;
704 addr += start & (PAGE_SIZE - 1);
705 write_lock_irqsave(&ha->hw_lock, flags);
a9083016
GM		 706
707 switch (size) {
708 case 1:
709 *(u8 *)data = readb(addr);
710 break;
711 case 2:
712 *(u16 *)data = readw(addr);
713 break;
714 case 4:
715 *(u32 *)data = readl(addr);
716 break;
717 case 8:
718 *(u64 *)data = readq(addr);
719 break;
720 default:
721 ret = -1;
722 break;
723 }
724 write_unlock_irqrestore(&ha->hw_lock, flags);
725
726 if (mem_ptr)
727 iounmap(mem_ptr);
728 return ret;
729}
730
731static int
732qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
733 u64 off, void *data, int size)
734{
735 unsigned long flags;
f1af6208 736 void *addr = NULL;
a9083016
GM		 737 int ret = 0;
738 u64 start;
739 uint8_t *mem_ptr = NULL;
740 unsigned long mem_base;
741 unsigned long mem_page;
742
743 write_lock_irqsave(&ha->hw_lock, flags);
744
745 /*
746 * If attempting to access unknown address or straddle hw windows,
747 * do not access.
748 */
749 start = qla82xx_pci_set_window(ha, off);
750 if ((start == -1UL) ||
751 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
752 write_unlock_irqrestore(&ha->hw_lock, flags);
753 qla_printk(KERN_ERR, ha,
754 "%s out of bound pci memory access. "
755 "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off);
756 return -1;
757 }
758
f1af6208
GM		 759 write_unlock_irqrestore(&ha->hw_lock, flags);
760 mem_base = pci_resource_start(ha->pdev, 0);
761 mem_page = start & PAGE_MASK;
762 /* Map two pages whenever user tries to access addresses in two
763 * consecutive pages.
764 */
765 if (mem_page != ((start + size - 1) & PAGE_MASK))
766 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
767 else
768 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
769 if (mem_ptr == 0UL)
770 return -1;
a9083016 771
f1af6208
GM		 772 addr = mem_ptr;
773 addr += start & (PAGE_SIZE - 1);
774 write_lock_irqsave(&ha->hw_lock, flags);
a9083016
GM		 775
776 switch (size) {
777 case 1:
778 writeb(*(u8 *)data, addr);
779 break;
780 case 2:
781 writew(*(u16 *)data, addr);
782 break;
783 case 4:
784 writel(*(u32 *)data, addr);
785 break;
786 case 8:
787 writeq(*(u64 *)data, addr);
788 break;
789 default:
790 ret = -1;
791 break;
792 }
793 write_unlock_irqrestore(&ha->hw_lock, flags);
794 if (mem_ptr)
795 iounmap(mem_ptr);
796 return ret;
797}
798
799int
800qla82xx_wrmem(struct qla_hw_data *ha, u64 off, void *data, int size)
801{
802 int i, j, ret = 0, loop, sz[2], off0;
803 u32 temp;
804 u64 off8, mem_crb, tmpw, word[2] = {0, 0};
805#define MAX_CTL_CHECK 1000
806 /*
807 * If not MN, go check for MS or invalid.
808 */
809 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) {
810 mem_crb = QLA82XX_CRB_QDR_NET;
811 } else {
812 mem_crb = QLA82XX_CRB_DDR_NET;
813 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
814 return qla82xx_pci_mem_write_direct(ha, off,
815 data, size);
816 }
817
818 off8 = off & 0xfffffff8;
819 off0 = off & 0x7;
820 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
821 sz[1] = size - sz[0];
822 loop = ((off0 + size - 1) >> 3) + 1;
823
824 if ((size != 8) || (off0 != 0)) {
825 for (i = 0; i < loop; i++) {
826 if (qla82xx_rdmem(ha, off8 + (i << 3), &word[i], 8))
827 return -1;
828 }
829 }
830
831 switch (size) {
832 case 1:
833 tmpw = *((u8 *)data);
834 break;
835 case 2:
836 tmpw = *((u16 *)data);
837 break;
838 case 4:
839 tmpw = *((u32 *)data);
840 break;
841 case 8:
842 default:
843 tmpw = *((u64 *)data);
844 break;
845 }
846
847 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
848 word[0] |= tmpw << (off0 * 8);
849
850 if (loop == 2) {
851 word[1] &= ~(~0ULL << (sz[1] * 8));
852 word[1] |= tmpw >> (sz[0] * 8);
853 }
854
855 for (i = 0; i < loop; i++) {
856 temp = off8 + (i << 3);
857 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
858 temp = 0;
859 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
860 temp = word[i] & 0xffffffff;
861 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
862 temp = (word[i] >> 32) & 0xffffffff;
863 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
864 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
865 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
866 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
867 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
868
869 for (j = 0; j < MAX_CTL_CHECK; j++) {
870 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
871 if ((temp & MIU_TA_CTL_BUSY) == 0)
872 break;
873 }
874
875 if (j >= MAX_CTL_CHECK) {
876 qla_printk(KERN_WARNING, ha,
877 "%s: Fail to write through agent\n",
878 QLA2XXX_DRIVER_NAME);
879 ret = -1;
880 break;
881 }
882 }
883 return ret;
884}
885
886int
887qla82xx_rdmem(struct qla_hw_data *ha, u64 off, void *data, int size)
888{
889 int i, j = 0, k, start, end, loop, sz[2], off0[2];
890 u32 temp;
891 u64 off8, val, mem_crb, word[2] = {0, 0};
892#define MAX_CTL_CHECK 1000
893
894 /*
895 * If not MN, go check for MS or invalid.
896 */
897 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
898 mem_crb = QLA82XX_CRB_QDR_NET;
899 else {
900 mem_crb = QLA82XX_CRB_DDR_NET;
901 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
902 return qla82xx_pci_mem_read_direct(ha, off,
903 data, size);
904 }
905
906 off8 = off & 0xfffffff8;
907 off0[0] = off & 0x7;
908 off0[1] = 0;
909 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
910 sz[1] = size - sz[0];
911 loop = ((off0[0] + size - 1) >> 3) + 1;
912
913 for (i = 0; i < loop; i++) {
914 temp = off8 + (i << 3);
915 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
916 temp = 0;
917 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
918 temp = MIU_TA_CTL_ENABLE;
919 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
920 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
921 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
922
923 for (j = 0; j < MAX_CTL_CHECK; j++) {
924 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
925 if ((temp & MIU_TA_CTL_BUSY) == 0)
926 break;
927 }
928
929 if (j >= MAX_CTL_CHECK) {
930 qla_printk(KERN_INFO, ha,
931 "%s: Fail to read through agent\n",
932 QLA2XXX_DRIVER_NAME);
933 break;
934 }
935
936 start = off0[i] >> 2;
937 end = (off0[i] + sz[i] - 1) >> 2;
938 for (k = start; k <= end; k++) {
939 temp = qla82xx_rd_32(ha,
940 mem_crb + MIU_TEST_AGT_RDDATA(k));
941 word[i] |= ((u64)temp << (32 * k));
942 }
943 }
944
945 if (j >= MAX_CTL_CHECK)
946 return -1;
947
948 if (sz[0] == 8) {
949 val = word[0];
950 } else {
951 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
952 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
953 }
954
955 switch (size) {
956 case 1:
957 *(u8 *)data = val;
958 break;
959 case 2:
960 *(u16 *)data = val;
961 break;
962 case 4:
963 *(u32 *)data = val;
964 break;
965 case 8:
966 *(u64 *)data = val;
967 break;
968 }
969 return 0;
970}
971
972#define MTU_FUDGE_FACTOR 100
973unsigned long qla82xx_decode_crb_addr(unsigned long addr)
974{
975 int i;
976 unsigned long base_addr, offset, pci_base;
977
978 if (!qla82xx_crb_table_initialized)
979 qla82xx_crb_addr_transform_setup();
980
981 pci_base = ADDR_ERROR;
982 base_addr = addr & 0xfff00000;
983 offset = addr & 0x000fffff;
984
985 for (i = 0; i < MAX_CRB_XFORM; i++) {
986 if (crb_addr_xform[i] == base_addr) {
987 pci_base = i << 20;
988 break;
989 }
990 }
991 if (pci_base == ADDR_ERROR)
992 return pci_base;
993 return pci_base + offset;
994}
995
996static long rom_max_timeout = 100;
997static long qla82xx_rom_lock_timeout = 100;
998
999int
1000qla82xx_rom_lock(struct qla_hw_data *ha)
1001{
1002 int done = 0, timeout = 0;
1003
1004 while (!done) {
1005 /* acquire semaphore2 from PCI HW block */
1006 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
1007 if (done == 1)
1008 break;
1009 if (timeout >= qla82xx_rom_lock_timeout)
1010 return -1;
1011 timeout++;
1012 }
1013 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
1014 return 0;
1015}
1016
1017int
1018qla82xx_wait_rom_busy(struct qla_hw_data *ha)
1019{
1020 long timeout = 0;
1021 long done = 0 ;
1022
1023 while (done == 0) {
1024 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
1025 done &= 4;
1026 timeout++;
1027 if (timeout >= rom_max_timeout) {
1028 DEBUG(qla_printk(KERN_INFO, ha,
1029 "%s: Timeout reached waiting for rom busy",
1030 QLA2XXX_DRIVER_NAME));
1031 return -1;
1032 }
1033 }
1034 return 0;
1035}
1036
1037int
1038qla82xx_wait_rom_done(struct qla_hw_data *ha)
1039{
1040 long timeout = 0;
1041 long done = 0 ;
1042
1043 while (done == 0) {
1044 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
1045 done &= 2;
1046 timeout++;
1047 if (timeout >= rom_max_timeout) {
1048 DEBUG(qla_printk(KERN_INFO, ha,
1049 "%s: Timeout reached waiting for rom done",
1050 QLA2XXX_DRIVER_NAME));
1051 return -1;
1052 }
1053 }
1054 return 0;
1055}
1056
1057int
1058qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
1059{
1060 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
1061 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
1062 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1063 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
1064 qla82xx_wait_rom_busy(ha);
1065 if (qla82xx_wait_rom_done(ha)) {
1066 qla_printk(KERN_WARNING, ha,
1067 "%s: Error waiting for rom done\n",
1068 QLA2XXX_DRIVER_NAME);
1069 return -1;
1070 }
1071 /* Reset abyte_cnt and dummy_byte_cnt */
1072 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
1073 udelay(10);
1074 cond_resched();
1075 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1076 *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
1077 return 0;
1078}
1079
1080int
1081qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
1082{
1083 int ret, loops = 0;
1084
1085 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1086 udelay(100);
1087 schedule();
1088 loops++;
1089 }
1090 if (loops >= 50000) {
1091 qla_printk(KERN_INFO, ha,
1092 "%s: qla82xx_rom_lock failed\n",
1093 QLA2XXX_DRIVER_NAME);
1094 return -1;
1095 }
1096 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
1097 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
1098 return ret;
1099}
1100
1101int
1102qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
1103{
1104 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
1105 qla82xx_wait_rom_busy(ha);
1106 if (qla82xx_wait_rom_done(ha)) {
1107 qla_printk(KERN_WARNING, ha,
1108 "Error waiting for rom done\n");
1109 return -1;
1110 }
1111 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
1112 return 0;
1113}
1114
1115int
1116qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
1117{
1118 long timeout = 0;
1119 uint32_t done = 1 ;
1120 uint32_t val;
1121 int ret = 0;
1122
1123 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1124 while ((done != 0) && (ret == 0)) {
1125 ret = qla82xx_read_status_reg(ha, &val);
1126 done = val & 1;
1127 timeout++;
1128 udelay(10);
1129 cond_resched();
1130 if (timeout >= 50000) {
1131 qla_printk(KERN_WARNING, ha,
1132 "Timeout reached waiting for write finish");
1133 return -1;
1134 }
1135 }
1136 return ret;
1137}
1138
1139int
1140qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1141{
1142 uint32_t val;
1143 qla82xx_wait_rom_busy(ha);
1144 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1145 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1146 qla82xx_wait_rom_busy(ha);
1147 if (qla82xx_wait_rom_done(ha))
1148 return -1;
1149 if (qla82xx_read_status_reg(ha, &val) != 0)
1150 return -1;
1151 if ((val & 2) != 2)
1152 return -1;
1153 return 0;
1154}
1155
1156int
1157qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1158{
1159 if (qla82xx_flash_set_write_enable(ha))
1160 return -1;
1161 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1162 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1163 if (qla82xx_wait_rom_done(ha)) {
1164 qla_printk(KERN_WARNING, ha,
1165 "Error waiting for rom done\n");
1166 return -1;
1167 }
1168 return qla82xx_flash_wait_write_finish(ha);
1169}
1170
1171int
1172qla82xx_write_disable_flash(struct qla_hw_data *ha)
1173{
1174 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1175 if (qla82xx_wait_rom_done(ha)) {
1176 qla_printk(KERN_WARNING, ha,
1177 "Error waiting for rom done\n");
1178 return -1;
1179 }
1180 return 0;
1181}
1182
1183int
1184ql82xx_rom_lock_d(struct qla_hw_data *ha)
1185{
1186 int loops = 0;
1187 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1188 udelay(100);
1189 cond_resched();
1190 loops++;
1191 }
1192 if (loops >= 50000) {
1193 qla_printk(KERN_WARNING, ha, "ROM lock failed\n");
1194 return -1;
1195 }
1196 return 0;;
1197}
1198
1199int
1200qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1201 uint32_t data)
1202{
1203 int ret = 0;
1204
1205 ret = ql82xx_rom_lock_d(ha);
1206 if (ret < 0) {
1207 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
1208 return ret;
1209 }
1210
1211 if (qla82xx_flash_set_write_enable(ha))
1212 goto done_write;
1213
1214 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1215 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1216 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1217 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1218 qla82xx_wait_rom_busy(ha);
1219 if (qla82xx_wait_rom_done(ha)) {
1220 qla_printk(KERN_WARNING, ha,
1221 "Error waiting for rom done\n");
1222 ret = -1;
1223 goto done_write;
1224 }
1225
1226 ret = qla82xx_flash_wait_write_finish(ha);
1227
1228done_write:
1229 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
1230 return ret;
1231}
1232
1233/* This routine does CRB initialize sequence
1234 * to put the ISP into operational state
1235 */
1236int qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1237{
1238 int addr, val;
1239 int i ;
1240 struct crb_addr_pair *buf;
1241 unsigned long off;
1242 unsigned offset, n;
1243 struct qla_hw_data *ha = vha->hw;
1244
1245 struct crb_addr_pair {
1246 long addr;
1247 long data;
1248 };
1249
1250 /* Halt all the indiviual PEGs and other blocks of the ISP */
1251 qla82xx_rom_lock(ha);
1252 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1253 /* don't reset CAM block on reset */
1254 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1255 else
1256 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1257 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
1258
1259 /* Read the signature value from the flash.
1260 * Offset 0: Contain signature (0xcafecafe)
1261 * Offset 4: Offset and number of addr/value pairs
1262 * that present in CRB initialize sequence
1263 */
1264 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1265 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1266 qla_printk(KERN_WARNING, ha,
1267 "[ERROR] Reading crb_init area: n: %08x\n", n);
1268 return -1;
1269 }
1270
1271 /* Offset in flash = lower 16 bits
1272 * Number of enteries = upper 16 bits
1273 */
1274 offset = n & 0xffffU;
1275 n = (n >> 16) & 0xffffU;
1276
1277 /* number of addr/value pair should not exceed 1024 enteries */
1278 if (n >= 1024) {
1279 qla_printk(KERN_WARNING, ha,
1280 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1281 QLA2XXX_DRIVER_NAME, __func__, n);
1282 return -1;
1283 }
1284
1285 qla_printk(KERN_INFO, ha,
1286 "%s: %d CRB init values found in ROM.\n", QLA2XXX_DRIVER_NAME, n);
1287
1288 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1289 if (buf == NULL) {
1290 qla_printk(KERN_WARNING, ha,
1291 "%s: [ERROR] Unable to malloc memory.\n",
1292 QLA2XXX_DRIVER_NAME);
1293 return -1;
1294 }
1295
1296 for (i = 0; i < n; i++) {
1297 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1298 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1299 kfree(buf);
1300 return -1;
1301 }
1302
1303 buf[i].addr = addr;
1304 buf[i].data = val;
1305 }
1306
1307 for (i = 0; i < n; i++) {
1308 /* Translate internal CRB initialization
1309 * address to PCI bus address
1310 */
1311 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1312 QLA82XX_PCI_CRBSPACE;
1313 /* Not all CRB addr/value pair to be written,
1314 * some of them are skipped
1315 */
1316
1317 /* skipping cold reboot MAGIC */
1318 if (off == QLA82XX_CAM_RAM(0x1fc))
1319 continue;
1320
1321 /* do not reset PCI */
1322 if (off == (ROMUSB_GLB + 0xbc))
1323 continue;
1324
1325 /* skip core clock, so that firmware can increase the clock */
1326 if (off == (ROMUSB_GLB + 0xc8))
1327 continue;
1328
1329 /* skip the function enable register */
1330 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1331 continue;
1332
1333 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1334 continue;
1335
1336 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1337 continue;
1338
1339 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1340 continue;
1341
1342 if (off == ADDR_ERROR) {
1343 qla_printk(KERN_WARNING, ha,
1344 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1345 QLA2XXX_DRIVER_NAME, buf[i].addr);
1346 continue;
1347 }
1348
1349 if (off == (QLA82XX_CRB_PEG_NET_1 + 0x18)) {
1350 if (!QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision))
1351 buf[i].data = 0x1020;
1352 }
1353
1354 qla82xx_wr_32(ha, off, buf[i].data);
1355
1356 /* ISP requires much bigger delay to settle down,
1357 * else crb_window returns 0xffffffff
1358 */
1359 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1360 msleep(1000);
1361
1362 /* ISP requires millisec delay between
1363 * successive CRB register updation
1364 */
1365 msleep(1);
1366 }
1367
1368 kfree(buf);
1369
1370 /* Resetting the data and instruction cache */
1371 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1372 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1373 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1374
1375 /* Clear all protocol processing engines */
1376 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1377 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1378 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1379 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1380 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1381 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1382 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1383 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1384 return 0;
1385}
1386
1387int qla82xx_check_for_bad_spd(struct qla_hw_data *ha)
1388{
1389 u32 val = 0;
1390 val = qla82xx_rd_32(ha, BOOT_LOADER_DIMM_STATUS);
1391 val &= QLA82XX_BOOT_LOADER_MN_ISSUE;
1392 if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) {
1393 qla_printk(KERN_INFO, ha,
1394 "Memory DIMM SPD not programmed. "
1395 " Assumed valid.\n");
1396 return 1;
1397 } else if (val) {
1398 qla_printk(KERN_INFO, ha,
1399 "Memory DIMM type incorrect.Info:%08X.\n", val);
1400 return 2;
1401 }
1402 return 0;
1403}
1404
1405int
1406qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1407{
1408 int i;
1409 long size = 0;
9c2b2975
HZ		 1410 long flashaddr = ha->flt_region_bootload << 2;
1411 long memaddr = BOOTLD_START;
a9083016
GM		 1412 u64 data;
1413 u32 high, low;
1414 size = (IMAGE_START - BOOTLD_START) / 8;
1415
1416 for (i = 0; i < size; i++) {
1417 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1418 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1419 return -1;
1420 }
1421 data = ((u64)high << 32) | low ;
1422 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1423 flashaddr += 8;
1424 memaddr += 8;
1425
1426 if (i % 0x1000 == 0)
1427 msleep(1);
1428 }
1429 udelay(100);
1430 read_lock(&ha->hw_lock);
1431 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1432 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1433 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1434 } else {
1435 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d);
1436 }
1437 read_unlock(&ha->hw_lock);
1438 return 0;
1439}
1440
1441int
1442qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1443 u64 off, void *data, int size)
1444{
1445 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1446 int shift_amount;
1447 uint32_t temp;
1448 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1449
1450 /*
1451 * If not MN, go check for MS or invalid.
1452 */
1453
1454 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1455 mem_crb = QLA82XX_CRB_QDR_NET;
1456 else {
1457 mem_crb = QLA82XX_CRB_DDR_NET;
1458 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1459 return qla82xx_pci_mem_read_direct(ha,
1460 off, data, size);
1461 }
1462
1463 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1464 off8 = off & 0xfffffff0;
1465 off0[0] = off & 0xf;
1466 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1467 shift_amount = 4;
1468 } else {
1469 off8 = off & 0xfffffff8;
1470 off0[0] = off & 0x7;
1471 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1472 shift_amount = 4;
1473 }
1474 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1475 off0[1] = 0;
1476 sz[1] = size - sz[0];
1477
1478 /*
1479 * don't lock here - write_wx gets the lock if each time
1480 * write_lock_irqsave(&adapter->adapter_lock, flags);
1481 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1482 */
1483
1484 for (i = 0; i < loop; i++) {
1485 temp = off8 + (i << shift_amount);
1486 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1487 temp = 0;
1488 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1489 temp = MIU_TA_CTL_ENABLE;
1490 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1491 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1492 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1493
1494 for (j = 0; j < MAX_CTL_CHECK; j++) {
1495 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1496 if ((temp & MIU_TA_CTL_BUSY) == 0)
1497 break;
1498 }
1499
1500 if (j >= MAX_CTL_CHECK) {
1501 if (printk_ratelimit())
1502 dev_err(&ha->pdev->dev,
1503 "failed to read through agent\n");
1504 break;
1505 }
1506
1507 start = off0[i] >> 2;
1508 end = (off0[i] + sz[i] - 1) >> 2;
1509 for (k = start; k <= end; k++) {
1510 temp = qla82xx_rd_32(ha,
1511 mem_crb + MIU_TEST_AGT_RDDATA(k));
1512 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1513 }
1514 }
1515
1516 /*
1517 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1518 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1519 */
1520
1521 if (j >= MAX_CTL_CHECK)
1522 return -1;
1523
1524 if ((off0[0] & 7) == 0) {
1525 val = word[0];
1526 } else {
1527 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1528 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1529 }
1530
1531 switch (size) {
1532 case 1:
1533 *(uint8_t *)data = val;
1534 break;
1535 case 2:
1536 *(uint16_t *)data = val;
1537 break;
1538 case 4:
1539 *(uint32_t *)data = val;
1540 break;
1541 case 8:
1542 *(uint64_t *)data = val;
1543 break;
1544 }
1545 return 0;
1546}
1547
1548int
1549qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1550 u64 off, void *data, int size)
1551{
1552 int i, j, ret = 0, loop, sz[2], off0;
1553 int scale, shift_amount, p3p, startword;
1554 uint32_t temp;
1555 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1556
1557 /*
1558 * If not MN, go check for MS or invalid.
1559 */
1560 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1561 mem_crb = QLA82XX_CRB_QDR_NET;
1562 else {
1563 mem_crb = QLA82XX_CRB_DDR_NET;
1564 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1565 return qla82xx_pci_mem_write_direct(ha,
1566 off, data, size);
1567 }
1568
1569 off0 = off & 0x7;
1570 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1571 sz[1] = size - sz[0];
1572
1573 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1574 off8 = off & 0xfffffff0;
1575 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1576 shift_amount = 4;
1577 scale = 2;
1578 p3p = 1;
1579 startword = (off & 0xf)/8;
1580 } else {
1581 off8 = off & 0xfffffff8;
1582 loop = ((off0 + size - 1) >> 3) + 1;
1583 shift_amount = 3;
1584 scale = 1;
1585 p3p = 0;
1586 startword = 0;
1587 }
1588
1589 if (p3p || (size != 8) || (off0 != 0)) {
1590 for (i = 0; i < loop; i++) {
1591 if (qla82xx_pci_mem_read_2M(ha, off8 +
1592 (i << shift_amount), &word[i * scale], 8))
1593 return -1;
1594 }
1595 }
1596
1597 switch (size) {
1598 case 1:
1599 tmpw = *((uint8_t *)data);
1600 break;
1601 case 2:
1602 tmpw = *((uint16_t *)data);
1603 break;
1604 case 4:
1605 tmpw = *((uint32_t *)data);
1606 break;
1607 case 8:
1608 default:
1609 tmpw = *((uint64_t *)data);
1610 break;
1611 }
1612
1613 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1614 if (sz[0] == 8) {
1615 word[startword] = tmpw;
1616 } else {
1617 word[startword] &=
1618 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1619 word[startword] |= tmpw << (off0 * 8);
1620 }
1621 if (sz[1] != 0) {
1622 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1623 word[startword+1] |= tmpw >> (sz[0] * 8);
1624 }
1625 } else {
1626 word[startword] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1627 word[startword] |= tmpw << (off0 * 8);
1628
1629 if (loop == 2) {
1630 word[1] &= ~(~0ULL << (sz[1] * 8));
1631 word[1] |= tmpw >> (sz[0] * 8);
1632 }
1633 }
1634
1635 /*
1636 * don't lock here - write_wx gets the lock if each time
1637 * write_lock_irqsave(&adapter->adapter_lock, flags);
1638 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1639 */
1640 for (i = 0; i < loop; i++) {
1641 temp = off8 + (i << shift_amount);
1642 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1643 temp = 0;
1644 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1645 temp = word[i * scale] & 0xffffffff;
1646 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1647 temp = (word[i * scale] >> 32) & 0xffffffff;
1648 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1649 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
1650 temp = word[i*scale + 1] & 0xffffffff;
1651 qla82xx_wr_32(ha, mem_crb +
1652 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1653 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1654 qla82xx_wr_32(ha, mem_crb +
1655 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1656 }
1657
1658 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1659 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1660 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1661 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1662
1663 for (j = 0; j < MAX_CTL_CHECK; j++) {
1664 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1665 if ((temp & MIU_TA_CTL_BUSY) == 0)
1666 break;
1667 }
1668
1669 if (j >= MAX_CTL_CHECK) {
1670 if (printk_ratelimit())
1671 dev_err(&ha->pdev->dev,
1672 "failed to write through agent\n");
1673 ret = -1;
1674 break;
1675 }
1676 }
1677
1678 return ret;
1679}
1680
9c2b2975
HZ		 1681static struct qla82xx_uri_table_desc *
1682qla82xx_get_table_desc(const u8 *unirom, int section)
1683{
1684 uint32_t i;
1685 struct qla82xx_uri_table_desc *directory =
1686 (struct qla82xx_uri_table_desc *)&unirom[0];
1687 __le32 offset;
1688 __le32 tab_type;
1689 __le32 entries = cpu_to_le32(directory->num_entries);
1690
1691 for (i = 0; i < entries; i++) {
1692 offset = cpu_to_le32(directory->findex) +
1693 (i * cpu_to_le32(directory->entry_size));
1694 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1695
1696 if (tab_type == section)
1697 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1698 }
1699
1700 return NULL;
1701}
1702
1703static struct qla82xx_uri_data_desc *
1704qla82xx_get_data_desc(struct qla_hw_data *ha,
1705 u32 section, u32 idx_offset)
1706{
1707 const u8 *unirom = ha->hablob->fw->data;
1708 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1709 struct qla82xx_uri_table_desc *tab_desc = NULL;
1710 __le32 offset;
1711
1712 tab_desc = qla82xx_get_table_desc(unirom, section);
1713 if (!tab_desc)
1714 return NULL;
1715
1716 offset = cpu_to_le32(tab_desc->findex) +
1717 (cpu_to_le32(tab_desc->entry_size) * idx);
1718
1719 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1720}
1721
1722static u8 *
1723qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1724{
1725 u32 offset = BOOTLD_START;
1726 struct qla82xx_uri_data_desc *uri_desc = NULL;
1727
1728 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1729 uri_desc = qla82xx_get_data_desc(ha,
1730 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1731 if (uri_desc)
1732 offset = cpu_to_le32(uri_desc->findex);
1733 }
1734
1735 return (u8 *)&ha->hablob->fw->data[offset];
1736}
1737
1738static __le32
1739qla82xx_get_fw_size(struct qla_hw_data *ha)
1740{
1741 struct qla82xx_uri_data_desc *uri_desc = NULL;
1742
1743 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1744 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1745 QLA82XX_URI_FIRMWARE_IDX_OFF);
1746 if (uri_desc)
1747 return cpu_to_le32(uri_desc->size);
1748 }
1749
1750 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1751}
1752
1753static u8 *
1754qla82xx_get_fw_offs(struct qla_hw_data *ha)
1755{
1756 u32 offset = IMAGE_START;
1757 struct qla82xx_uri_data_desc *uri_desc = NULL;
1758
1759 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1760 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1761 QLA82XX_URI_FIRMWARE_IDX_OFF);
1762 if (uri_desc)
1763 offset = cpu_to_le32(uri_desc->findex);
1764 }
1765
1766 return (u8 *)&ha->hablob->fw->data[offset];
1767}
1768
a9083016
GM		 1769/* PCI related functions */
1770char *
1771qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str)
1772{
1773 int pcie_reg;
1774 struct qla_hw_data *ha = vha->hw;
1775 char lwstr[6];
1776 uint16_t lnk;
1777
1778 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
1779 pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk);
1780 ha->link_width = (lnk >> 4) & 0x3f;
1781
1782 strcpy(str, "PCIe (");
1783 strcat(str, "2.5Gb/s ");
1784 snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width);
1785 strcat(str, lwstr);
1786 return str;
1787}
1788
1789int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1790{
1791 unsigned long val = 0;
1792 u32 control;
1793
1794 switch (region) {
1795 case 0:
1796 val = 0;
1797 break;
1798 case 1:
1799 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1800 val = control + QLA82XX_MSIX_TBL_SPACE;
1801 break;
1802 }
1803 return val;
1804}
1805
1806int qla82xx_pci_region_len(struct pci_dev *pdev, int region)
1807{
1808 unsigned long val = 0;
1809 u32 control;
1810 switch (region) {
1811 case 0:
1812 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1813 val = control;
1814 break;
1815 case 1:
1816 val = pci_resource_len(pdev, 0) -
1817 qla82xx_pci_region_offset(pdev, 1);
1818 break;
1819 }
1820 return val;
1821}
1822
1823int
1824qla82xx_iospace_config(struct qla_hw_data *ha)
1825{
1826 uint32_t len = 0;
1827
1828 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1829 qla_printk(KERN_WARNING, ha,
1830 "Failed to reserve selected regions (%s)\n",
1831 pci_name(ha->pdev));
1832 goto iospace_error_exit;
1833 }
1834
1835 /* Use MMIO operations for all accesses. */
1836 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1837 qla_printk(KERN_ERR, ha,
1838 "region #0 not an MMIO resource (%s), aborting\n",
1839 pci_name(ha->pdev));
1840 goto iospace_error_exit;
1841 }
1842
1843 len = pci_resource_len(ha->pdev, 0);
1844 ha->nx_pcibase =
1845 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1846 if (!ha->nx_pcibase) {
1847 qla_printk(KERN_ERR, ha,
1848 "cannot remap pcibase MMIO (%s), aborting\n",
1849 pci_name(ha->pdev));
1850 pci_release_regions(ha->pdev);
1851 goto iospace_error_exit;
1852 }
1853
1854 /* Mapping of IO base pointer */
1855 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase +
1856 0xbc000 + (ha->pdev->devfn << 11));
1857
1858 if (!ql2xdbwr) {
1859 ha->nxdb_wr_ptr =
1860 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1861 (ha->pdev->devfn << 12)), 4);
1862 if (!ha->nxdb_wr_ptr) {
1863 qla_printk(KERN_ERR, ha,
1864 "cannot remap MMIO (%s), aborting\n",
1865 pci_name(ha->pdev));
1866 pci_release_regions(ha->pdev);
1867 goto iospace_error_exit;
1868 }
1869
1870 /* Mapping of IO base pointer,
1871 * door bell read and write pointer
1872 */
1873 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
1874 (ha->pdev->devfn * 8);
1875 } else {
1876 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
1877 QLA82XX_CAMRAM_DB1 :
1878 QLA82XX_CAMRAM_DB2);
1879 }
1880
1881 ha->max_req_queues = ha->max_rsp_queues = 1;
1882 ha->msix_count = ha->max_rsp_queues + 1;
1883 return 0;
1884
1885iospace_error_exit:
1886 return -ENOMEM;
1887}
1888
1889/* GS related functions */
1890
1891/* Initialization related functions */
1892
1893/**
1894 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1895 * @ha: HA context
1896 *
1897 * Returns 0 on success.
1898*/
1899int
1900qla82xx_pci_config(scsi_qla_host_t *vha)
1901{
1902 struct qla_hw_data *ha = vha->hw;
1903 int ret;
1904
1905 pci_set_master(ha->pdev);
1906 ret = pci_set_mwi(ha->pdev);
1907 ha->chip_revision = ha->pdev->revision;
1908 return 0;
1909}
1910
1911/**
1912 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1913 * @ha: HA context
1914 *
1915 * Returns 0 on success.
1916 */
1917void
1918qla82xx_reset_chip(scsi_qla_host_t *vha)
1919{
1920 struct qla_hw_data *ha = vha->hw;
1921 ha->isp_ops->disable_intrs(ha);
1922}
1923
1924void qla82xx_config_rings(struct scsi_qla_host *vha)
1925{
1926 struct qla_hw_data *ha = vha->hw;
1927 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1928 struct init_cb_81xx *icb;
1929 struct req_que *req = ha->req_q_map[0];
1930 struct rsp_que *rsp = ha->rsp_q_map[0];
1931
1932 /* Setup ring parameters in initialization control block. */
1933 icb = (struct init_cb_81xx *)ha->init_cb;
1934 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1935 icb->response_q_inpointer = __constant_cpu_to_le16(0);
1936 icb->request_q_length = cpu_to_le16(req->length);
1937 icb->response_q_length = cpu_to_le16(rsp->length);
1938 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1939 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1940 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1941 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1942
1943 icb->version = 1;
1944 icb->frame_payload_size = 2112;
1945 icb->execution_throttle = 8;
1946 icb->exchange_count = 128;
1947 icb->login_retry_count = 8;
1948
1949 WRT_REG_DWORD((unsigned long __iomem *)&reg->req_q_out[0], 0);
1950 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_in[0], 0);
1951 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_out[0], 0);
1952}
1953
f1af6208
GM		 1954void qla82xx_reset_adapter(struct scsi_qla_host *vha)
1955{
1956 struct qla_hw_data *ha = vha->hw;
1957 vha->flags.online = 0;
1958 qla2x00_try_to_stop_firmware(vha);
1959 ha->isp_ops->disable_intrs(ha);
1960}
1961
a9083016
GM		 1962int qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1963{
1964 u64 *ptr64;
1965 u32 i, flashaddr, size;
1966 __le64 data;
1967
1968 size = (IMAGE_START - BOOTLD_START) / 8;
1969
9c2b2975 1970 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
a9083016
GM		 1971 flashaddr = BOOTLD_START;
1972
1973 for (i = 0; i < size; i++) {
1974 data = cpu_to_le64(ptr64[i]);
9c2b2975
HZ		 1975 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1976 return -EIO;
a9083016
GM		 1977 flashaddr += 8;
1978 }
1979
a9083016 1980 flashaddr = FLASH_ADDR_START;
9c2b2975
HZ		 1981 size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1982 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
a9083016
GM		 1983
1984 for (i = 0; i < size; i++) {
1985 data = cpu_to_le64(ptr64[i]);
1986
1987 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1988 return -EIO;
1989 flashaddr += 8;
1990 }
9c2b2975 1991 udelay(100);
a9083016
GM		 1992
1993 /* Write a magic value to CAMRAM register
1994 * at a specified offset to indicate
1995 * that all data is written and
1996 * ready for firmware to initialize.
1997 */
9c2b2975 1998 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
a9083016 1999
9c2b2975 2000 read_lock(&ha->hw_lock);
a9083016
GM		 2001 if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) {
2002 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
2003 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
2004 } else
2005 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d);
9c2b2975
HZ		 2006 read_unlock(&ha->hw_lock);
2007 return 0;
2008}
2009
2010static int
2011qla82xx_set_product_offset(struct qla_hw_data *ha)
2012{
2013 struct qla82xx_uri_table_desc *ptab_desc = NULL;
2014 const uint8_t *unirom = ha->hablob->fw->data;
2015 uint32_t i;
2016 __le32 entries;
2017 __le32 flags, file_chiprev, offset;
2018 uint8_t chiprev = ha->chip_revision;
2019 /* Hardcoding mn_present flag for P3P */
2020 int mn_present = 0;
2021 uint32_t flagbit;
2022
2023 ptab_desc = qla82xx_get_table_desc(unirom,
2024 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
2025 if (!ptab_desc)
2026 return -1;
2027
2028 entries = cpu_to_le32(ptab_desc->num_entries);
2029
2030 for (i = 0; i < entries; i++) {
2031 offset = cpu_to_le32(ptab_desc->findex) +
2032 (i * cpu_to_le32(ptab_desc->entry_size));
2033 flags = cpu_to_le32(*((int *)&unirom[offset] +
2034 QLA82XX_URI_FLAGS_OFF));
2035 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
2036 QLA82XX_URI_CHIP_REV_OFF));
2037
2038 flagbit = mn_present ? 1 : 2;
2039
2040 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
2041 ha->file_prd_off = offset;
2042 return 0;
2043 }
2044 }
2045 return -1;
2046}
2047
2048int
2049qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
2050{
2051 __le32 val;
2052 uint32_t min_size;
2053 struct qla_hw_data *ha = vha->hw;
2054 const struct firmware *fw = ha->hablob->fw;
2055
2056 ha->fw_type = fw_type;
2057
2058 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
2059 if (qla82xx_set_product_offset(ha))
2060 return -EINVAL;
2061
2062 min_size = QLA82XX_URI_FW_MIN_SIZE;
2063 } else {
2064 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
2065 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
2066 return -EINVAL;
2067
2068 min_size = QLA82XX_FW_MIN_SIZE;
2069 }
2070
2071 if (fw->size < min_size)
2072 return -EINVAL;
a9083016
GM		 2073 return 0;
2074}
2075
2076int qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
2077{
2078 u32 val = 0;
2079 int retries = 60;
2080
2081 do {
2082 read_lock(&ha->hw_lock);
2083 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
2084 read_unlock(&ha->hw_lock);
2085
2086 switch (val) {
2087 case PHAN_INITIALIZE_COMPLETE:
2088 case PHAN_INITIALIZE_ACK:
2089 return QLA_SUCCESS;
2090 case PHAN_INITIALIZE_FAILED:
2091 break;
2092 default:
2093 break;
2094 }
2095 qla_printk(KERN_WARNING, ha,
2096 "CRB_CMDPEG_STATE: 0x%x and retries: 0x%x\n",
2097 val, retries);
2098
2099 msleep(500);
2100
2101 } while (--retries);
2102
2103 qla_printk(KERN_INFO, ha,
2104 "Cmd Peg initialization failed: 0x%x.\n", val);
2105
2106 qla82xx_check_for_bad_spd(ha);
2107 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
2108 read_lock(&ha->hw_lock);
2109 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
2110 read_unlock(&ha->hw_lock);
2111 return QLA_FUNCTION_FAILED;
2112}
2113
2114int qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
2115{
2116 u32 val = 0;
2117 int retries = 60;
2118
2119 do {
2120 read_lock(&ha->hw_lock);
2121 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
2122 read_unlock(&ha->hw_lock);
2123
2124 switch (val) {
2125 case PHAN_INITIALIZE_COMPLETE:
2126 case PHAN_INITIALIZE_ACK:
2127 return QLA_SUCCESS;
2128 case PHAN_INITIALIZE_FAILED:
2129 break;
2130 default:
2131 break;
2132 }
2133
2134 qla_printk(KERN_WARNING, ha,
2135 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x\n",
2136 val, retries);
2137
2138 msleep(500);
2139
2140 } while (--retries);
2141
2142 qla_printk(KERN_INFO, ha,
2143 "Rcv Peg initialization failed: 0x%x.\n", val);
2144 read_lock(&ha->hw_lock);
2145 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
2146 read_unlock(&ha->hw_lock);
2147 return QLA_FUNCTION_FAILED;
2148}
2149
2150/* ISR related functions */
2151uint32_t qla82xx_isr_int_target_mask_enable[8] = {
2152 ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1,
2153 ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3,
2154 ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5,
2155 ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7
2156};
2157
2158uint32_t qla82xx_isr_int_target_status[8] = {
2159 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
2160 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
2161 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
2162 ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7
2163};
2164
2165static struct qla82xx_legacy_intr_set legacy_intr[] = \
2166 QLA82XX_LEGACY_INTR_CONFIG;
2167
2168/*
2169 * qla82xx_mbx_completion() - Process mailbox command completions.
2170 * @ha: SCSI driver HA context
2171 * @mb0: Mailbox0 register
2172 */
2173void
2174qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
2175{
2176 uint16_t cnt;
2177 uint16_t __iomem *wptr;
2178 struct qla_hw_data *ha = vha->hw;
2179 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
2180 wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
2181
2182 /* Load return mailbox registers. */
2183 ha->flags.mbox_int = 1;
2184 ha->mailbox_out[0] = mb0;
2185
2186 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2187 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2188 wptr++;
2189 }
2190
2191 if (ha->mcp) {
2192 DEBUG3_11(printk(KERN_INFO "%s(%ld): "
2193 "Got mailbox completion. cmd=%x.\n",
2194 __func__, vha->host_no, ha->mcp->mb[0]));
2195 } else {
2196 qla_printk(KERN_INFO, ha,
2197 "%s(%ld): MBX pointer ERROR!\n",
2198 __func__, vha->host_no);
2199 }
2200}
2201
2202/*
2203 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2204 * @irq:
2205 * @dev_id: SCSI driver HA context
2206 * @regs:
2207 *
2208 * Called by system whenever the host adapter generates an interrupt.
2209 *
2210 * Returns handled flag.
2211 */
2212irqreturn_t
2213qla82xx_intr_handler(int irq, void *dev_id)
2214{
2215 scsi_qla_host_t *vha;
2216 struct qla_hw_data *ha;
2217 struct rsp_que *rsp;
2218 struct device_reg_82xx __iomem *reg;
2219 int status = 0, status1 = 0;
2220 unsigned long flags;
2221 unsigned long iter;
2222 uint32_t stat;
2223 uint16_t mb[4];
2224
2225 rsp = (struct rsp_que *) dev_id;
2226 if (!rsp) {
2227 printk(KERN_INFO
2228 "%s(): NULL response queue pointer\n", __func__);
2229 return IRQ_NONE;
2230 }
2231 ha = rsp->hw;
2232
2233 if (!ha->flags.msi_enabled) {
2234 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2235 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2236 return IRQ_NONE;
2237
2238 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2239 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2240 return IRQ_NONE;
2241 }
2242
2243 /* clear the interrupt */
2244 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2245
2246 /* read twice to ensure write is flushed */
2247 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2248 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2249
2250 reg = &ha->iobase->isp82;
2251
2252 spin_lock_irqsave(&ha->hardware_lock, flags);
2253 vha = pci_get_drvdata(ha->pdev);
2254 for (iter = 1; iter--; ) {
2255
2256 if (RD_REG_DWORD(&reg->host_int)) {
2257 stat = RD_REG_DWORD(&reg->host_status);
f1af6208 2258 if ((stat & HSRX_RISC_INT) == 0)
a9083016
GM		 2259 break;
2260
2261 switch (stat & 0xff) {
2262 case 0x1:
2263 case 0x2:
2264 case 0x10:
2265 case 0x11:
2266 qla82xx_mbx_completion(vha, MSW(stat));
2267 status |= MBX_INTERRUPT;
2268 break;
2269 case 0x12:
2270 mb[0] = MSW(stat);
2271 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2272 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2273 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2274 qla2x00_async_event(vha, rsp, mb);
2275 break;
2276 case 0x13:
2277 qla24xx_process_response_queue(vha, rsp);
2278 break;
2279 default:
2280 DEBUG2(printk("scsi(%ld): "
2281 " Unrecognized interrupt type (%d).\n",
2282 vha->host_no, stat & 0xff));
2283 break;
2284 }
2285 }
2286 WRT_REG_DWORD(&reg->host_int, 0);
2287 }
2288 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2289 if (!ha->flags.msi_enabled)
2290 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2291
2292#ifdef QL_DEBUG_LEVEL_17
2293 if (!irq && ha->flags.eeh_busy)
2294 qla_printk(KERN_WARNING, ha,
2295 "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n",
2296 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2297#endif
2298
2299 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2300 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2301 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2302 complete(&ha->mbx_intr_comp);
2303 }
2304 return IRQ_HANDLED;
2305}
2306
2307irqreturn_t
2308qla82xx_msix_default(int irq, void *dev_id)
2309{
2310 scsi_qla_host_t *vha;
2311 struct qla_hw_data *ha;
2312 struct rsp_que *rsp;
2313 struct device_reg_82xx __iomem *reg;
2314 int status = 0;
2315 unsigned long flags;
2316 uint32_t stat;
2317 uint16_t mb[4];
2318
2319 rsp = (struct rsp_que *) dev_id;
2320 if (!rsp) {
2321 printk(KERN_INFO
2322 "%s(): NULL response queue pointer\n", __func__);
2323 return IRQ_NONE;
2324 }
2325 ha = rsp->hw;
2326
2327 reg = &ha->iobase->isp82;
2328
2329 spin_lock_irqsave(&ha->hardware_lock, flags);
2330 vha = pci_get_drvdata(ha->pdev);
2331 do {
2332 if (RD_REG_DWORD(&reg->host_int)) {
2333 stat = RD_REG_DWORD(&reg->host_status);
f1af6208 2334 if ((stat & HSRX_RISC_INT) == 0)
a9083016
GM		 2335 break;
2336
2337 switch (stat & 0xff) {
2338 case 0x1:
2339 case 0x2:
2340 case 0x10:
2341 case 0x11:
2342 qla82xx_mbx_completion(vha, MSW(stat));
2343 status |= MBX_INTERRUPT;
2344 break;
2345 case 0x12:
2346 mb[0] = MSW(stat);
2347 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2348 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2349 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2350 qla2x00_async_event(vha, rsp, mb);
2351 break;
2352 case 0x13:
2353 qla24xx_process_response_queue(vha, rsp);
2354 break;
2355 default:
2356 DEBUG2(printk("scsi(%ld): "
2357 " Unrecognized interrupt type (%d).\n",
2358 vha->host_no, stat & 0xff));
2359 break;
2360 }
2361 }
2362 WRT_REG_DWORD(&reg->host_int, 0);
2363 } while (0);
2364
2365 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2366
2367#ifdef QL_DEBUG_LEVEL_17
2368 if (!irq && ha->flags.eeh_busy)
2369 qla_printk(KERN_WARNING, ha,
2370 "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n",
2371 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2372#endif
2373
2374 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2375 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2376 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2377 complete(&ha->mbx_intr_comp);
2378 }
2379 return IRQ_HANDLED;
2380}
2381
2382irqreturn_t
2383qla82xx_msix_rsp_q(int irq, void *dev_id)
2384{
2385 scsi_qla_host_t *vha;
2386 struct qla_hw_data *ha;
2387 struct rsp_que *rsp;
2388 struct device_reg_82xx __iomem *reg;
2389
2390 rsp = (struct rsp_que *) dev_id;
2391 if (!rsp) {
2392 printk(KERN_INFO
2393 "%s(): NULL response queue pointer\n", __func__);
2394 return IRQ_NONE;
2395 }
2396
2397 ha = rsp->hw;
2398 reg = &ha->iobase->isp82;
2399 spin_lock_irq(&ha->hardware_lock);
2400 vha = pci_get_drvdata(ha->pdev);
2401 qla24xx_process_response_queue(vha, rsp);
2402 WRT_REG_DWORD(&reg->host_int, 0);
2403 spin_unlock_irq(&ha->hardware_lock);
2404 return IRQ_HANDLED;
2405}
2406
2407void
2408qla82xx_poll(int irq, void *dev_id)
2409{
2410 scsi_qla_host_t *vha;
2411 struct qla_hw_data *ha;
2412 struct rsp_que *rsp;
2413 struct device_reg_82xx __iomem *reg;
2414 int status = 0;
2415 uint32_t stat;
2416 uint16_t mb[4];
2417 unsigned long flags;
2418
2419 rsp = (struct rsp_que *) dev_id;
2420 if (!rsp) {
2421 printk(KERN_INFO
2422 "%s(): NULL response queue pointer\n", __func__);
2423 return;
2424 }
2425 ha = rsp->hw;
2426
2427 reg = &ha->iobase->isp82;
2428 spin_lock_irqsave(&ha->hardware_lock, flags);
2429 vha = pci_get_drvdata(ha->pdev);
2430
2431 if (RD_REG_DWORD(&reg->host_int)) {
2432 stat = RD_REG_DWORD(&reg->host_status);
2433 switch (stat & 0xff) {
2434 case 0x1:
2435 case 0x2:
2436 case 0x10:
2437 case 0x11:
2438 qla82xx_mbx_completion(vha, MSW(stat));
2439 status |= MBX_INTERRUPT;
2440 break;
2441 case 0x12:
2442 mb[0] = MSW(stat);
2443 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2444 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2445 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2446 qla2x00_async_event(vha, rsp, mb);
2447 break;
2448 case 0x13:
2449 qla24xx_process_response_queue(vha, rsp);
2450 break;
2451 default:
2452 DEBUG2(printk("scsi(%ld): Unrecognized interrupt type "
2453 "(%d).\n",
2454 vha->host_no, stat & 0xff));
2455 break;
2456 }
2457 }
2458 WRT_REG_DWORD(&reg->host_int, 0);
2459 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2460}
2461
2462void
2463qla82xx_enable_intrs(struct qla_hw_data *ha)
2464{
2465 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2466 qla82xx_mbx_intr_enable(vha);
2467 spin_lock_irq(&ha->hardware_lock);
2468 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2469 spin_unlock_irq(&ha->hardware_lock);
2470 ha->interrupts_on = 1;
2471}
2472
2473void
2474qla82xx_disable_intrs(struct qla_hw_data *ha)
2475{
2476 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2477 qla82xx_mbx_intr_disable(vha);
2478 spin_lock_irq(&ha->hardware_lock);
2479 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2480 spin_unlock_irq(&ha->hardware_lock);
2481 ha->interrupts_on = 0;
2482}
2483
2484void qla82xx_init_flags(struct qla_hw_data *ha)
2485{
2486 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2487
2488 /* ISP 8021 initializations */
2489 rwlock_init(&ha->hw_lock);
2490 ha->qdr_sn_window = -1;
2491 ha->ddr_mn_window = -1;
2492 ha->curr_window = 255;
2493 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2494 nx_legacy_intr = &legacy_intr[ha->portnum];
2495 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2496 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2497 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2498 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2499}
2500
2501static inline void
2502qla82xx_set_drv_active(scsi_qla_host_t *vha)
2503{
2504 uint32_t drv_active;
2505 struct qla_hw_data *ha = vha->hw;
2506
2507 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2508
2509 /* If reset value is all FF's, initialize DRV_ACTIVE */
2510 if (drv_active == 0xffffffff) {
2511 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 0);
2512 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2513 }
2514 drv_active |= (1 << (ha->portnum * 4));
2515 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2516}
2517
2518inline void
2519qla82xx_clear_drv_active(struct qla_hw_data *ha)
2520{
2521 uint32_t drv_active;
2522
2523 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2524 drv_active &= ~(1 << (ha->portnum * 4));
2525 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2526}
2527
2528static inline int
2529qla82xx_need_reset(struct qla_hw_data *ha)
2530{
2531 uint32_t drv_state;
2532 int rval;
2533
2534 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2535 rval = drv_state & (1 << (ha->portnum * 4));
2536 return rval;
2537}
2538
2539static inline void
2540qla82xx_set_rst_ready(struct qla_hw_data *ha)
2541{
2542 uint32_t drv_state;
2543 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2544
2545 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2546
2547 /* If reset value is all FF's, initialize DRV_STATE */
2548 if (drv_state == 0xffffffff) {
2549 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
2550 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2551 }
2552 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2553 qla_printk(KERN_INFO, ha,
2554 "%s(%ld):drv_state = 0x%x\n",
2555 __func__, vha->host_no, drv_state);
2556 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2557}
2558
2559static inline void
2560qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2561{
2562 uint32_t drv_state;
2563
2564 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2565 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2566 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2567}
2568
2569static inline void
2570qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2571{
2572 uint32_t qsnt_state;
2573
2574 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2575 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2576 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2577}
2578
2579int qla82xx_load_fw(scsi_qla_host_t *vha)
2580{
2581 int rst;
2582 struct fw_blob *blob;
2583 struct qla_hw_data *ha = vha->hw;
2584
2585 /* Put both the PEG CMD and RCV PEG to default state
2586 * of 0 before resetting the hardware
2587 */
2588 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2589 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2590
2591 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2592 qla_printk(KERN_ERR, ha,
2593 "%s: Error during CRB Initialization\n", __func__);
2594 return QLA_FUNCTION_FAILED;
2595 }
2596 udelay(500);
2597
2598 /* Bring QM and CAMRAM out of reset */
2599 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2600 rst &= ~((1 << 28) | (1 << 24));
2601 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2602
2603 /*
2604 * FW Load priority:
2605 * 1) Operational firmware residing in flash.
2606 * 2) Firmware via request-firmware interface (.bin file).
2607 */
2608 if (ql2xfwloadbin == 2)
2609 goto try_blob_fw;
2610
2611 qla_printk(KERN_INFO, ha,
2612 "Attempting to load firmware from flash\n");
2613
2614 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2615 qla_printk(KERN_ERR, ha,
2616 "Firmware loaded successfully from flash\n");
2617 return QLA_SUCCESS;
2618 }
2619try_blob_fw:
2620 qla_printk(KERN_INFO, ha,
2621 "Attempting to load firmware from blob\n");
2622
2623 /* Load firmware blob. */
2624 blob = ha->hablob = qla2x00_request_firmware(vha);
2625 if (!blob) {
2626 qla_printk(KERN_ERR, ha,
2627 "Firmware image not present.\n");
2628 goto fw_load_failed;
2629 }
2630
9c2b2975
HZ		 2631 /* Validating firmware blob */
2632 if (qla82xx_validate_firmware_blob(vha,
2633 QLA82XX_FLASH_ROMIMAGE)) {
2634 /* Fallback to URI format */
2635 if (qla82xx_validate_firmware_blob(vha,
2636 QLA82XX_UNIFIED_ROMIMAGE)) {
2637 qla_printk(KERN_ERR, ha,
2638 "No valid firmware image found!!!");
2639 return QLA_FUNCTION_FAILED;
2640 }
2641 }
2642
a9083016
GM		 2643 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2644 qla_printk(KERN_ERR, ha,
2645 "%s: Firmware loaded successfully "
2646 " from binary blob\n", __func__);
2647 return QLA_SUCCESS;
2648 } else {
2649 qla_printk(KERN_ERR, ha,
2650 "Firmware load failed from binary blob\n");
2651 blob->fw = NULL;
2652 blob = NULL;
2653 goto fw_load_failed;
2654 }
2655 return QLA_SUCCESS;
2656
2657fw_load_failed:
2658 return QLA_FUNCTION_FAILED;
2659}
2660
2661static int
2662qla82xx_start_firmware(scsi_qla_host_t *vha)
2663{
2664 int pcie_cap;
2665 uint16_t lnk;
2666 struct qla_hw_data *ha = vha->hw;
2667
2668 /* scrub dma mask expansion register */
2669 qla82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
2670
2671 /* Overwrite stale initialization register values */
2672 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2673 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2674
2675 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2676 qla_printk(KERN_INFO, ha,
2677 "%s: Error trying to start fw!\n", __func__);
2678 return QLA_FUNCTION_FAILED;
2679 }
2680
2681 /* Handshake with the card before we register the devices. */
2682 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2683 qla_printk(KERN_INFO, ha,
2684 "%s: Error during card handshake!\n", __func__);
2685 return QLA_FUNCTION_FAILED;
2686 }
2687
2688 /* Negotiated Link width */
2689 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
2690 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
2691 ha->link_width = (lnk >> 4) & 0x3f;
2692
2693 /* Synchronize with Receive peg */
2694 return qla82xx_check_rcvpeg_state(ha);
2695}
2696
2697static inline int
2698qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt,
2699 uint16_t tot_dsds)
2700{
2701 uint32_t *cur_dsd = NULL;
2702 scsi_qla_host_t *vha;
2703 struct qla_hw_data *ha;
2704 struct scsi_cmnd *cmd;
2705 struct scatterlist *cur_seg;
2706 uint32_t *dsd_seg;
2707 void *next_dsd;
2708 uint8_t avail_dsds;
2709 uint8_t first_iocb = 1;
2710 uint32_t dsd_list_len;
2711 struct dsd_dma *dsd_ptr;
2712 struct ct6_dsd *ctx;
2713
2714 cmd = sp->cmd;
2715
2716 /* Update entry type to indicate Command Type 3 IOCB */
2717 *((uint32_t *)(&cmd_pkt->entry_type)) =
2718 __constant_cpu_to_le32(COMMAND_TYPE_6);
2719
2720 /* No data transfer */
2721 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
2722 cmd_pkt->byte_count = __constant_cpu_to_le32(0);
2723 return 0;
2724 }
2725
2726 vha = sp->fcport->vha;
2727 ha = vha->hw;
2728
2729 /* Set transfer direction */
2730 if (cmd->sc_data_direction == DMA_TO_DEVICE) {
2731 cmd_pkt->control_flags =
2732 __constant_cpu_to_le16(CF_WRITE_DATA);
2733 ha->qla_stats.output_bytes += scsi_bufflen(cmd);
2734 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
2735 cmd_pkt->control_flags =
2736 __constant_cpu_to_le16(CF_READ_DATA);
2737 ha->qla_stats.input_bytes += scsi_bufflen(cmd);
2738 }
2739
2740 cur_seg = scsi_sglist(cmd);
2741 ctx = sp->ctx;
2742
2743 while (tot_dsds) {
2744 avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ?
2745 QLA_DSDS_PER_IOCB : tot_dsds;
2746 tot_dsds -= avail_dsds;
2747 dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE;
2748
2749 dsd_ptr = list_first_entry(&ha->gbl_dsd_list,
2750 struct dsd_dma, list);
2751 next_dsd = dsd_ptr->dsd_addr;
2752 list_del(&dsd_ptr->list);
2753 ha->gbl_dsd_avail--;
2754 list_add_tail(&dsd_ptr->list, &ctx->dsd_list);
2755 ctx->dsd_use_cnt++;
2756 ha->gbl_dsd_inuse++;
2757
2758 if (first_iocb) {
2759 first_iocb = 0;
2760 dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address;
2761 *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma));
2762 *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma));
2763 *dsd_seg++ = dsd_list_len;
2764 } else {
2765 *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma));
2766 *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma));
2767 *cur_dsd++ = dsd_list_len;
2768 }
2769 cur_dsd = (uint32_t *)next_dsd;
2770 while (avail_dsds) {
2771 dma_addr_t sle_dma;
2772
2773 sle_dma = sg_dma_address(cur_seg);
2774 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
2775 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
2776 *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg));
2777 cur_seg++;
2778 avail_dsds--;
2779 }
2780 }
2781
2782 /* Null termination */
2783 *cur_dsd++ = 0;
2784 *cur_dsd++ = 0;
2785 *cur_dsd++ = 0;
2786 cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE;
2787 return 0;
2788}
2789
2790/*
2791 * qla82xx_calc_dsd_lists() - Determine number of DSD list required
2792 * for Command Type 6.
2793 *
2794 * @dsds: number of data segment decriptors needed
2795 *
2796 * Returns the number of dsd list needed to store @dsds.
2797 */
2798inline uint16_t
2799qla82xx_calc_dsd_lists(uint16_t dsds)
2800{
2801 uint16_t dsd_lists = 0;
2802
2803 dsd_lists = (dsds/QLA_DSDS_PER_IOCB);
2804 if (dsds % QLA_DSDS_PER_IOCB)
2805 dsd_lists++;
2806 return dsd_lists;
2807}
2808
2809/*
2810 * qla82xx_start_scsi() - Send a SCSI command to the ISP
2811 * @sp: command to send to the ISP
2812 *
2813 * Returns non-zero if a failure occured, else zero.
2814 */
2815int
2816qla82xx_start_scsi(srb_t *sp)
2817{
2818 int ret, nseg;
2819 unsigned long flags;
2820 struct scsi_cmnd *cmd;
2821 uint32_t *clr_ptr;
2822 uint32_t index;
2823 uint32_t handle;
2824 uint16_t cnt;
2825 uint16_t req_cnt;
2826 uint16_t tot_dsds;
2827 struct device_reg_82xx __iomem *reg;
2828 uint32_t dbval;
2829 uint32_t *fcp_dl;
2830 uint8_t additional_cdb_len;
2831 struct ct6_dsd *ctx;
2832 struct scsi_qla_host *vha = sp->fcport->vha;
2833 struct qla_hw_data *ha = vha->hw;
2834 struct req_que *req = NULL;
2835 struct rsp_que *rsp = NULL;
2836
2837 /* Setup device pointers. */
2838 ret = 0;
2839 reg = &ha->iobase->isp82;
2840 cmd = sp->cmd;
2841 req = vha->req;
2842 rsp = ha->rsp_q_map[0];
2843
2844 /* So we know we haven't pci_map'ed anything yet */
2845 tot_dsds = 0;
2846
2847 dbval = 0x04 | (ha->portnum << 5);
2848
2849 /* Send marker if required */
2850 if (vha->marker_needed != 0) {
2851 if (qla2x00_marker(vha, req,
2852 rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS)
2853 return QLA_FUNCTION_FAILED;
2854 vha->marker_needed = 0;
2855 }
2856
2857 /* Acquire ring specific lock */
2858 spin_lock_irqsave(&ha->hardware_lock, flags);
2859
2860 /* Check for room in outstanding command list. */
2861 handle = req->current_outstanding_cmd;
2862 for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) {
2863 handle++;
2864 if (handle == MAX_OUTSTANDING_COMMANDS)
2865 handle = 1;
2866 if (!req->outstanding_cmds[handle])
2867 break;
2868 }
2869 if (index == MAX_OUTSTANDING_COMMANDS)
2870 goto queuing_error;
2871
2872 /* Map the sg table so we have an accurate count of sg entries needed */
2873 if (scsi_sg_count(cmd)) {
2874 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
2875 scsi_sg_count(cmd), cmd->sc_data_direction);
2876 if (unlikely(!nseg))
2877 goto queuing_error;
2878 } else
2879 nseg = 0;
2880
2881 tot_dsds = nseg;
2882
2883 if (tot_dsds > ql2xshiftctondsd) {
2884 struct cmd_type_6 *cmd_pkt;
2885 uint16_t more_dsd_lists = 0;
2886 struct dsd_dma *dsd_ptr;
2887 uint16_t i;
2888
2889 more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds);
2890 if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN)
2891 goto queuing_error;
2892
2893 if (more_dsd_lists <= ha->gbl_dsd_avail)
2894 goto sufficient_dsds;
2895 else
2896 more_dsd_lists -= ha->gbl_dsd_avail;
2897
2898 for (i = 0; i < more_dsd_lists; i++) {
2899 dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC);
2900 if (!dsd_ptr)
2901 goto queuing_error;
2902
2903 dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool,
2904 GFP_ATOMIC, &dsd_ptr->dsd_list_dma);
2905 if (!dsd_ptr->dsd_addr) {
2906 kfree(dsd_ptr);
2907 goto queuing_error;
2908 }
2909 list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list);
2910 ha->gbl_dsd_avail++;
2911 }
2912
2913sufficient_dsds:
2914 req_cnt = 1;
2915
2916 ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC);
2917 if (!sp->ctx) {
2918 DEBUG(printk(KERN_INFO
2919 "%s(%ld): failed to allocate"
2920 " ctx.\n", __func__, vha->host_no));
2921 goto queuing_error;
2922 }
2923 memset(ctx, 0, sizeof(struct ct6_dsd));
2924 ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool,
2925 GFP_ATOMIC, &ctx->fcp_cmnd_dma);
2926 if (!ctx->fcp_cmnd) {
2927 DEBUG2_3(printk("%s(%ld): failed to allocate"
2928 " fcp_cmnd.\n", __func__, vha->host_no));
2929 goto queuing_error_fcp_cmnd;
2930 }
2931
2932 /* Initialize the DSD list and dma handle */
2933 INIT_LIST_HEAD(&ctx->dsd_list);
2934 ctx->dsd_use_cnt = 0;
2935
2936 if (cmd->cmd_len > 16) {
2937 additional_cdb_len = cmd->cmd_len - 16;
2938 if ((cmd->cmd_len % 4) != 0) {
2939 /* SCSI command bigger than 16 bytes must be
2940 * multiple of 4
2941 */
2942 goto queuing_error_fcp_cmnd;
2943 }
2944 ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4;
2945 } else {
2946 additional_cdb_len = 0;
2947 ctx->fcp_cmnd_len = 12 + 16 + 4;
2948 }
2949
2950 cmd_pkt = (struct cmd_type_6 *)req->ring_ptr;
2951 cmd_pkt->handle = MAKE_HANDLE(req->id, handle);
2952
2953 /* Zero out remaining portion of packet. */
2954 /* tagged queuing modifier -- default is TSK_SIMPLE (0). */
2955 clr_ptr = (uint32_t *)cmd_pkt + 2;
2956 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8);
2957 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds);
2958
2959 /* Set NPORT-ID and LUN number*/
2960 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id);
2961 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa;
2962 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area;
2963 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain;
2964 cmd_pkt->vp_index = sp->fcport->vp_idx;
2965
2966 /* Build IOCB segments */
2967 if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds))
2968 goto queuing_error_fcp_cmnd;
2969
2970 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun);
2971
2972 /* build FCP_CMND IU */
2973 memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd));
2974 int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun);
2975 ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len;
2976
2977 if (cmd->sc_data_direction == DMA_TO_DEVICE)
2978 ctx->fcp_cmnd->additional_cdb_len |= 1;
2979 else if (cmd->sc_data_direction == DMA_FROM_DEVICE)
2980 ctx->fcp_cmnd->additional_cdb_len |= 2;
2981
2982 memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len);
2983
2984 fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 +
2985 additional_cdb_len);
2986 *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd));
2987
2988 cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len);
2989 cmd_pkt->fcp_cmnd_dseg_address[0] =
2990 cpu_to_le32(LSD(ctx->fcp_cmnd_dma));
2991 cmd_pkt->fcp_cmnd_dseg_address[1] =
2992 cpu_to_le32(MSD(ctx->fcp_cmnd_dma));
2993
2994 sp->flags |= SRB_FCP_CMND_DMA_VALID;
2995 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
2996 /* Set total data segment count. */
2997 cmd_pkt->entry_count = (uint8_t)req_cnt;
2998 /* Specify response queue number where
2999 * completion should happen
3000 */
3001 cmd_pkt->entry_status = (uint8_t) rsp->id;
3002 } else {
3003 struct cmd_type_7 *cmd_pkt;
3004 req_cnt = qla24xx_calc_iocbs(tot_dsds);
3005 if (req->cnt < (req_cnt + 2)) {
3006 cnt = (uint16_t)RD_REG_DWORD_RELAXED(
3007 &reg->req_q_out[0]);
3008 if (req->ring_index < cnt)
3009 req->cnt = cnt - req->ring_index;
3010 else
3011 req->cnt = req->length -
3012 (req->ring_index - cnt);
3013 }
3014 if (req->cnt < (req_cnt + 2))
3015 goto queuing_error;
3016
3017 cmd_pkt = (struct cmd_type_7 *)req->ring_ptr;
3018 cmd_pkt->handle = MAKE_HANDLE(req->id, handle);
3019
3020 /* Zero out remaining portion of packet. */
3021 /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/
3022 clr_ptr = (uint32_t *)cmd_pkt + 2;
3023 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8);
3024 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds);
3025
3026 /* Set NPORT-ID and LUN number*/
3027 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id);
3028 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa;
3029 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area;
3030 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain;
3031 cmd_pkt->vp_index = sp->fcport->vp_idx;
3032
3033 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun);
3034 host_to_fcp_swap((uint8_t *)&cmd_pkt->lun,
3035 sizeof(cmd_pkt->lun));
3036
3037 /* Load SCSI command packet. */
3038 memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len);
3039 host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb));
3040
3041 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
3042
3043 /* Build IOCB segments */
3044 qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds);
3045
3046 /* Set total data segment count. */
3047 cmd_pkt->entry_count = (uint8_t)req_cnt;
3048 /* Specify response queue number where
3049 * completion should happen.
3050 */
3051 cmd_pkt->entry_status = (uint8_t) rsp->id;
3052
3053 }
3054 /* Build command packet. */
3055 req->current_outstanding_cmd = handle;
3056 req->outstanding_cmds[handle] = sp;
3057 sp->handle = handle;
3058 sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle;
3059 req->cnt -= req_cnt;
3060 wmb();
3061
3062 /* Adjust ring index. */
3063 req->ring_index++;
3064 if (req->ring_index == req->length) {
3065 req->ring_index = 0;
3066 req->ring_ptr = req->ring;
3067 } else
3068 req->ring_ptr++;
3069
3070 sp->flags |= SRB_DMA_VALID;
3071
3072 /* Set chip new ring index. */
3073 /* write, read and verify logic */
3074 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
3075 if (ql2xdbwr)
3076 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
3077 else {
3078 WRT_REG_DWORD(
3079 (unsigned long __iomem *)ha->nxdb_wr_ptr,
3080 dbval);
3081 wmb();
3082 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
3083 WRT_REG_DWORD(
3084 (unsigned long __iomem *)ha->nxdb_wr_ptr,
3085 dbval);
3086 wmb();
3087 }
3088 }
3089
3090 /* Manage unprocessed RIO/ZIO commands in response queue. */
3091 if (vha->flags.process_response_queue &&
3092 rsp->ring_ptr->signature != RESPONSE_PROCESSED)
3093 qla24xx_process_response_queue(vha, rsp);
3094
3095 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3096 return QLA_SUCCESS;
3097
3098queuing_error_fcp_cmnd:
3099 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma);
3100queuing_error:
3101 if (tot_dsds)
3102 scsi_dma_unmap(cmd);
3103
3104 if (sp->ctx) {
3105 mempool_free(sp->ctx, ha->ctx_mempool);
3106 sp->ctx = NULL;
3107 }
3108 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3109
3110 return QLA_FUNCTION_FAILED;
3111}
3112
3113uint32_t *
3114qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
3115 uint32_t length)
3116{
3117 uint32_t i;
3118 uint32_t val;
3119 struct qla_hw_data *ha = vha->hw;
3120
3121 /* Dword reads to flash. */
3122 for (i = 0; i < length/4; i++, faddr += 4) {
3123 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
3124 qla_printk(KERN_WARNING, ha,
3125 "Do ROM fast read failed\n");
3126 goto done_read;
3127 }
3128 dwptr[i] = __constant_cpu_to_le32(val);
3129 }
3130done_read:
3131 return dwptr;
3132}
3133
3134int
3135qla82xx_unprotect_flash(struct qla_hw_data *ha)
3136{
3137 int ret;
3138 uint32_t val;
3139
3140 ret = ql82xx_rom_lock_d(ha);
3141 if (ret < 0) {
3142 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
3143 return ret;
3144 }
3145
3146 ret = qla82xx_read_status_reg(ha, &val);
3147 if (ret < 0)
3148 goto done_unprotect;
3149
3150 val &= ~(0x7 << 2);
3151 ret = qla82xx_write_status_reg(ha, val);
3152 if (ret < 0) {
3153 val |= (0x7 << 2);
3154 qla82xx_write_status_reg(ha, val);
3155 }
3156
3157 if (qla82xx_write_disable_flash(ha) != 0)
3158 qla_printk(KERN_WARNING, ha, "Write disable failed\n");
3159
3160done_unprotect:
3161 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
3162 return ret;
3163}
3164
3165int
3166qla82xx_protect_flash(struct qla_hw_data *ha)
3167{
3168 int ret;
3169 uint32_t val;
3170
3171 ret = ql82xx_rom_lock_d(ha);
3172 if (ret < 0) {
3173 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
3174 return ret;
3175 }
3176
3177 ret = qla82xx_read_status_reg(ha, &val);
3178 if (ret < 0)
3179 goto done_protect;
3180
3181 val |= (0x7 << 2);
3182 /* LOCK all sectors */
3183 ret = qla82xx_write_status_reg(ha, val);
3184 if (ret < 0)
3185 qla_printk(KERN_WARNING, ha, "Write status register failed\n");
3186
3187 if (qla82xx_write_disable_flash(ha) != 0)
3188 qla_printk(KERN_WARNING, ha, "Write disable failed\n");
3189done_protect:
3190 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
3191 return ret;
3192}
3193
3194int
3195qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
3196{
3197 int ret = 0;
3198
3199 ret = ql82xx_rom_lock_d(ha);
3200 if (ret < 0) {
3201 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
3202 return ret;
3203 }
3204
3205 qla82xx_flash_set_write_enable(ha);
3206 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
3207 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
3208 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
3209
3210 if (qla82xx_wait_rom_done(ha)) {
3211 qla_printk(KERN_WARNING, ha,
3212 "Error waiting for rom done\n");
3213 ret = -1;
3214 goto done;
3215 }
3216 ret = qla82xx_flash_wait_write_finish(ha);
3217done:
3218 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
3219 return ret;
3220}
3221
3222/*
3223 * Address and length are byte address
3224 */
3225uint8_t *
3226qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3227 uint32_t offset, uint32_t length)
3228{
3229 scsi_block_requests(vha->host);
3230 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
3231 scsi_unblock_requests(vha->host);
3232 return buf;
3233}
3234
3235static int
3236qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
3237 uint32_t faddr, uint32_t dwords)
3238{
3239 int ret;
3240 uint32_t liter;
3241 uint32_t sec_mask, rest_addr;
3242 dma_addr_t optrom_dma;
3243 void *optrom = NULL;
3244 int page_mode = 0;
3245 struct qla_hw_data *ha = vha->hw;
3246
3247 ret = -1;
3248
3249 /* Prepare burst-capable write on supported ISPs. */
3250 if (page_mode && !(faddr & 0xfff) &&
3251 dwords > OPTROM_BURST_DWORDS) {
3252 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
3253 &optrom_dma, GFP_KERNEL);
3254 if (!optrom) {
3255 qla_printk(KERN_DEBUG, ha,
3256 "Unable to allocate memory for optrom "
3257 "burst write (%x KB).\n",
3258 OPTROM_BURST_SIZE / 1024);
3259 }
3260 }
3261
3262 rest_addr = ha->fdt_block_size - 1;
3263 sec_mask = ~rest_addr;
3264
3265 ret = qla82xx_unprotect_flash(ha);
3266 if (ret) {
3267 qla_printk(KERN_WARNING, ha,
3268 "Unable to unprotect flash for update.\n");
3269 goto write_done;
3270 }
3271
3272 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3273 /* Are we at the beginning of a sector? */
3274 if ((faddr & rest_addr) == 0) {
3275
3276 ret = qla82xx_erase_sector(ha, faddr);
3277 if (ret) {
3278 DEBUG9(qla_printk(KERN_ERR, ha,
3279 "Unable to erase sector: "
3280 "address=%x.\n", faddr));
3281 break;
3282 }
3283 }
3284
3285 /* Go with burst-write. */
3286 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
3287 /* Copy data to DMA'ble buffer. */
3288 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
3289
3290 ret = qla2x00_load_ram(vha, optrom_dma,
3291 (ha->flash_data_off | faddr),
3292 OPTROM_BURST_DWORDS);
3293 if (ret != QLA_SUCCESS) {
3294 qla_printk(KERN_WARNING, ha,
3295 "Unable to burst-write optrom segment "
3296 "(%x/%x/%llx).\n", ret,
3297 (ha->flash_data_off | faddr),
3298 (unsigned long long)optrom_dma);
3299 qla_printk(KERN_WARNING, ha,
3300 "Reverting to slow-write.\n");
3301
3302 dma_free_coherent(&ha->pdev->dev,
3303 OPTROM_BURST_SIZE, optrom, optrom_dma);
3304 optrom = NULL;
3305 } else {
3306 liter += OPTROM_BURST_DWORDS - 1;
3307 faddr += OPTROM_BURST_DWORDS - 1;
3308 dwptr += OPTROM_BURST_DWORDS - 1;
3309 continue;
3310 }
3311 }
3312
3313 ret = qla82xx_write_flash_dword(ha, faddr,
3314 cpu_to_le32(*dwptr));
3315 if (ret) {
3316 DEBUG9(printk(KERN_DEBUG "%s(%ld) Unable to program"
3317 "flash address=%x data=%x.\n", __func__,
3318 ha->host_no, faddr, *dwptr));
3319 break;
3320 }
3321 }
3322
3323 ret = qla82xx_protect_flash(ha);
3324 if (ret)
3325 qla_printk(KERN_WARNING, ha,
3326 "Unable to protect flash after update.\n");
3327write_done:
3328 if (optrom)
3329 dma_free_coherent(&ha->pdev->dev,
3330 OPTROM_BURST_SIZE, optrom, optrom_dma);
3331 return ret;
3332}
3333
3334int
3335qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3336 uint32_t offset, uint32_t length)
3337{
3338 int rval;
3339
3340 /* Suspend HBA. */
3341 scsi_block_requests(vha->host);
3342 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
3343 length >> 2);
3344 scsi_unblock_requests(vha->host);
3345
3346 /* Convert return ISP82xx to generic */
3347 if (rval)
3348 rval = QLA_FUNCTION_FAILED;
3349 else
3350 rval = QLA_SUCCESS;
3351 return rval;
3352}
3353
3354void
3355qla82xx_start_iocbs(srb_t *sp)
3356{
3357 struct qla_hw_data *ha = sp->fcport->vha->hw;
3358 struct req_que *req = ha->req_q_map[0];
3359 struct device_reg_82xx __iomem *reg;
3360 uint32_t dbval;
3361
3362 /* Adjust ring index. */
3363 req->ring_index++;
3364 if (req->ring_index == req->length) {
3365 req->ring_index = 0;
3366 req->ring_ptr = req->ring;
3367 } else
3368 req->ring_ptr++;
3369
3370 reg = &ha->iobase->isp82;
3371 dbval = 0x04 | (ha->portnum << 5);
3372
3373 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
3374 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
3375 wmb();
3376 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
3377 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
3378 wmb();
3379 }
3380}
3381
3382/*
3383 * qla82xx_device_bootstrap
3384 * Initialize device, set DEV_READY, start fw
3385 *
3386 * Note:
3387 * IDC lock must be held upon entry
3388 *
3389 * Return:
3390 * Success : 0
3391 * Failed : 1
3392 */
3393static int
3394qla82xx_device_bootstrap(scsi_qla_host_t *vha)
3395{
3396 int rval, i, timeout;
3397 uint32_t old_count, count;
3398 struct qla_hw_data *ha = vha->hw;
3399
3400 if (qla82xx_need_reset(ha))
3401 goto dev_initialize;
3402
3403 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
3404
3405 for (i = 0; i < 10; i++) {
3406 timeout = msleep_interruptible(200);
3407 if (timeout) {
3408 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3409 QLA82XX_DEV_FAILED);
3410 return QLA_FUNCTION_FAILED;
3411 }
3412
3413 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
3414 if (count != old_count)
3415 goto dev_ready;
3416 }
3417
3418dev_initialize:
3419 /* set to DEV_INITIALIZING */
3420 qla_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
3421 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
3422
3423 /* Driver that sets device state to initializating sets IDC version */
3424 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
3425
3426 qla82xx_idc_unlock(ha);
3427 rval = qla82xx_start_firmware(vha);
3428 qla82xx_idc_lock(ha);
3429
3430 if (rval != QLA_SUCCESS) {
3431 qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
3432 qla82xx_clear_drv_active(ha);
3433 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
3434 return rval;
3435 }
3436
3437dev_ready:
3438 qla_printk(KERN_INFO, ha, "HW State: READY\n");
3439 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
3440
3441 return QLA_SUCCESS;
3442}
3443
3444static void
3445qla82xx_dev_failed_handler(scsi_qla_host_t *vha)
3446{
3447 struct qla_hw_data *ha = vha->hw;
3448
3449 /* Disable the board */
3450 qla_printk(KERN_INFO, ha, "Disabling the board\n");
3451
b963752f
GM		 3452 qla82xx_idc_lock(ha);
3453 qla82xx_clear_drv_active(ha);
3454 qla82xx_idc_unlock(ha);
3455
a9083016
GM		 3456 /* Set DEV_FAILED flag to disable timer */
3457 vha->device_flags |= DFLG_DEV_FAILED;
3458 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3459 qla2x00_mark_all_devices_lost(vha, 0);
3460 vha->flags.online = 0;
3461 vha->flags.init_done = 0;
3462}
3463
3464/*
3465 * qla82xx_need_reset_handler
3466 * Code to start reset sequence
3467 *
3468 * Note:
3469 * IDC lock must be held upon entry
3470 *
3471 * Return:
3472 * Success : 0
3473 * Failed : 1
3474 */
3475static void
3476qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3477{
3478 uint32_t dev_state, drv_state, drv_active;
3479 unsigned long reset_timeout;
3480 struct qla_hw_data *ha = vha->hw;
3481 struct req_que *req = ha->req_q_map[0];
3482
3483 if (vha->flags.online) {
3484 qla82xx_idc_unlock(ha);
3485 qla2x00_abort_isp_cleanup(vha);
3486 ha->isp_ops->get_flash_version(vha, req->ring);
3487 ha->isp_ops->nvram_config(vha);
3488 qla82xx_idc_lock(ha);
3489 }
3490
3491 qla82xx_set_rst_ready(ha);
3492
3493 /* wait for 10 seconds for reset ack from all functions */
3494 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
3495
3496 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3497 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3498
3499 while (drv_state != drv_active) {
3500 if (time_after_eq(jiffies, reset_timeout)) {
3501 qla_printk(KERN_INFO, ha,
3502 "%s: RESET TIMEOUT!\n", QLA2XXX_DRIVER_NAME);
3503 break;
3504 }
3505 qla82xx_idc_unlock(ha);
3506 msleep(1000);
3507 qla82xx_idc_lock(ha);
3508 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3509 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3510 }
3511
3512 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
f1af6208
GM		 3513 qla_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state,
3514 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
3515
a9083016
GM		 3516 /* Force to DEV_COLD unless someone else is starting a reset */
3517 if (dev_state != QLA82XX_DEV_INITIALIZING) {
3518 qla_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
3519 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
3520 }
3521}
3522
3523static void
3524qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3525{
3526 uint32_t fw_heartbeat_counter, halt_status;
3527 struct qla_hw_data *ha = vha->hw;
3528
3529 fw_heartbeat_counter = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
3530 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3531 vha->seconds_since_last_heartbeat++;
3532 /* FW not alive after 2 seconds */
3533 if (vha->seconds_since_last_heartbeat == 2) {
3534 vha->seconds_since_last_heartbeat = 0;
3535 halt_status = qla82xx_rd_32(ha,
3536 QLA82XX_PEG_HALT_STATUS1);
3537 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3538 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3539 } else {
3540 qla_printk(KERN_INFO, ha,
3541 "scsi(%ld): %s - detect abort needed\n",
3542 vha->host_no, __func__);
3543 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3544 }
3545 qla2xxx_wake_dpc(vha);
cdbb0a4f
SV		 3546 if (ha->flags.mbox_busy) {
3547 ha->flags.fw_hung = 1;
3548 ha->flags.mbox_int = 1;
3549 DEBUG2(qla_printk(KERN_ERR, ha,
3550 "Due to fw hung, doing premature "
3551 "completion of mbx command\n"));
3552 complete(&ha->mbx_intr_comp);
3553 }
a9083016
GM		 3554 }
3555 }
3556 vha->fw_heartbeat_counter = fw_heartbeat_counter;
3557}
3558
3559/*
3560 * qla82xx_device_state_handler
3561 * Main state handler
3562 *
3563 * Note:
3564 * IDC lock must be held upon entry
3565 *
3566 * Return:
3567 * Success : 0
3568 * Failed : 1
3569 */
3570int
3571qla82xx_device_state_handler(scsi_qla_host_t *vha)
3572{
3573 uint32_t dev_state;
a9083016
GM		 3574 int rval = QLA_SUCCESS;
3575 unsigned long dev_init_timeout;
3576 struct qla_hw_data *ha = vha->hw;
3577
3578 qla82xx_idc_lock(ha);
3579 if (!vha->flags.init_done)
3580 qla82xx_set_drv_active(vha);
3581
f1af6208
GM		 3582 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3583 qla_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state,
3584 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
a9083016
GM		 3585
3586 /* wait for 30 seconds for device to go ready */
3587 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3588
3589 while (1) {
3590
3591 if (time_after_eq(jiffies, dev_init_timeout)) {
3592 DEBUG(qla_printk(KERN_INFO, ha,
3593 "%s: device init failed!\n",
3594 QLA2XXX_DRIVER_NAME));
3595 rval = QLA_FUNCTION_FAILED;
3596 break;
3597 }
3598 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
f1af6208
GM		 3599 qla_printk(KERN_INFO, ha,
3600 "2:Device state is 0x%x = %s\n", dev_state,
3601 dev_state < MAX_STATES ?
3602 qdev_state[dev_state] : "Unknown");
3603
a9083016
GM		 3604 switch (dev_state) {
3605 case QLA82XX_DEV_READY:
3606 goto exit;
3607 case QLA82XX_DEV_COLD:
3608 rval = qla82xx_device_bootstrap(vha);
3609 goto exit;
3610 case QLA82XX_DEV_INITIALIZING:
3611 qla82xx_idc_unlock(ha);
3612 msleep(1000);
3613 qla82xx_idc_lock(ha);
3614 break;
3615 case QLA82XX_DEV_NEED_RESET:
3616 if (!ql2xdontresethba)
3617 qla82xx_need_reset_handler(vha);
3618 break;
3619 case QLA82XX_DEV_NEED_QUIESCENT:
3620 qla82xx_set_qsnt_ready(ha);
3621 case QLA82XX_DEV_QUIESCENT:
3622 qla82xx_idc_unlock(ha);
3623 msleep(1000);
3624 qla82xx_idc_lock(ha);
3625 break;
3626 case QLA82XX_DEV_FAILED:
3627 qla82xx_dev_failed_handler(vha);
3628 rval = QLA_FUNCTION_FAILED;
3629 goto exit;
3630 default:
3631 qla82xx_idc_unlock(ha);
3632 msleep(1000);
3633 qla82xx_idc_lock(ha);
3634 }
3635 }
3636exit:
3637 qla82xx_idc_unlock(ha);
3638 return rval;
3639}
3640
3641void qla82xx_watchdog(scsi_qla_host_t *vha)
3642{
3643 uint32_t dev_state;
3644 struct qla_hw_data *ha = vha->hw;
3645
3646 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3647
3648 /* don't poll if reset is going on */
3649 if (!(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3650 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
3651 test_bit(ISP_ABORT_RETRY, &vha->dpc_flags))) {
3652 if (dev_state == QLA82XX_DEV_NEED_RESET) {
3653 qla_printk(KERN_WARNING, ha,
3654 "%s(): Adapter reset needed!\n", __func__);
3655 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3656 qla2xxx_wake_dpc(vha);
cdbb0a4f
SV		 3657 if (ha->flags.mbox_busy) {
3658 ha->flags.fw_hung = 1;
3659 ha->flags.mbox_int = 1;
3660 DEBUG2(qla_printk(KERN_ERR, ha,
3661 "Need reset, doing premature "
3662 "completion of mbx command\n"));
3663 complete(&ha->mbx_intr_comp);
3664 }
a9083016
GM		 3665 } else {
3666 qla82xx_check_fw_alive(vha);
3667 }
3668 }
3669}
3670
3671int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3672{
3673 int rval;
3674 rval = qla82xx_device_state_handler(vha);
3675 return rval;
3676}
3677
3678/*
3679 * qla82xx_abort_isp
3680 * Resets ISP and aborts all outstanding commands.
3681 *
3682 * Input:
3683 * ha = adapter block pointer.
3684 *
3685 * Returns:
3686 * 0 = success
3687 */
3688int
3689qla82xx_abort_isp(scsi_qla_host_t *vha)
3690{
3691 int rval;
3692 struct qla_hw_data *ha = vha->hw;
3693 uint32_t dev_state;
3694
3695 if (vha->device_flags & DFLG_DEV_FAILED) {
3696 qla_printk(KERN_WARNING, ha,
3697 "%s(%ld): Device in failed state, "
3698 "Exiting.\n", __func__, vha->host_no);
3699 return QLA_SUCCESS;
3700 }
3701
3702 qla82xx_idc_lock(ha);
3703 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
f1af6208 3704 if (dev_state == QLA82XX_DEV_READY) {
a9083016
GM		 3705 qla_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
3706 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3707 QLA82XX_DEV_NEED_RESET);
3708 } else
f1af6208
GM		 3709 qla_printk(KERN_INFO, ha, "HW State: %s\n",
3710 dev_state < MAX_STATES ?
3711 qdev_state[dev_state] : "Unknown");
a9083016
GM		 3712 qla82xx_idc_unlock(ha);
3713
3714 rval = qla82xx_device_state_handler(vha);
3715
3716 qla82xx_idc_lock(ha);
3717 qla82xx_clear_rst_ready(ha);
3718 qla82xx_idc_unlock(ha);
3719
cdbb0a4f
SV		 3720 if (rval == QLA_SUCCESS) {
3721 ha->flags.fw_hung = 0;
a9083016 3722 qla82xx_restart_isp(vha);
cdbb0a4f 3723 }
f1af6208
GM		 3724
3725 if (rval) {
3726 vha->flags.online = 1;
3727 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3728 if (ha->isp_abort_cnt == 0) {
3729 qla_printk(KERN_WARNING, ha,
3730 "ISP error recovery failed - "
3731 "board disabled\n");
3732 /*
3733 * The next call disables the board
3734 * completely.
3735 */
3736 ha->isp_ops->reset_adapter(vha);
3737 vha->flags.online = 0;
3738 clear_bit(ISP_ABORT_RETRY,
3739 &vha->dpc_flags);
3740 rval = QLA_SUCCESS;
3741 } else { /* schedule another ISP abort */
3742 ha->isp_abort_cnt--;
3743 DEBUG(qla_printk(KERN_INFO, ha,
3744 "qla%ld: ISP abort - retry remaining %d\n",
3745 vha->host_no, ha->isp_abort_cnt));
3746 rval = QLA_FUNCTION_FAILED;
3747 }
3748 } else {
3749 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3750 DEBUG(qla_printk(KERN_INFO, ha,
3751 "(%ld): ISP error recovery - retrying (%d) "
3752 "more times\n", vha->host_no, ha->isp_abort_cnt));
3753 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3754 rval = QLA_FUNCTION_FAILED;
3755 }
3756 }
a9083016
GM		 3757 return rval;
3758}
3759
3760/*
3761 * qla82xx_fcoe_ctx_reset
3762 * Perform a quick reset and aborts all outstanding commands.
3763 * This will only perform an FCoE context reset and avoids a full blown
3764 * chip reset.
3765 *
3766 * Input:
3767 * ha = adapter block pointer.
3768 * is_reset_path = flag for identifying the reset path.
3769 *
3770 * Returns:
3771 * 0 = success
3772 */
3773int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3774{
3775 int rval = QLA_FUNCTION_FAILED;
3776
3777 if (vha->flags.online) {
3778 /* Abort all outstanding commands, so as to be requeued later */
3779 qla2x00_abort_isp_cleanup(vha);
3780 }
3781
3782 /* Stop currently executing firmware.
3783 * This will destroy existing FCoE context at the F/W end.
3784 */
3785 qla2x00_try_to_stop_firmware(vha);
3786
3787 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3788 rval = qla82xx_restart_isp(vha);
3789
3790 return rval;
3791}
3792
3793/*
3794 * qla2x00_wait_for_fcoe_ctx_reset
3795 * Wait till the FCoE context is reset.
3796 *
3797 * Note:
3798 * Does context switching here.
3799 * Release SPIN_LOCK (if any) before calling this routine.
3800 *
3801 * Return:
3802 * Success (fcoe_ctx reset is done) : 0
3803 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3804 */
3805int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3806{
3807 int status = QLA_FUNCTION_FAILED;
3808 unsigned long wait_reset;
3809
3810 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3811 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3812 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3813 && time_before(jiffies, wait_reset)) {
3814
3815 set_current_state(TASK_UNINTERRUPTIBLE);
3816 schedule_timeout(HZ);
3817
3818 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3819 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3820 status = QLA_SUCCESS;
3821 break;
3822 }
3823 }
3824 DEBUG2(printk(KERN_INFO
3825 "%s status=%d\n", __func__, status));
3826
3827 return status;
3828}
kernel source for telekom puls (alcatel/mediatek)