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Merge branch 'bind_unbind' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / scsi / qla2xxx / qla_mbx.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
2d70c103 8#include "qla_target.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/gfp.h>
1da177e4 12
15f30a57
QT		 13static struct mb_cmd_name {
14 uint16_t cmd;
15 const char *str;
16} mb_str[] = {
17 {MBC_GET_PORT_DATABASE, "GPDB"},
18 {MBC_GET_ID_LIST, "GIDList"},
19 {MBC_GET_LINK_PRIV_STATS, "Stats"},
20};
21
22static const char *mb_to_str(uint16_t cmd)
23{
24 int i;
25 struct mb_cmd_name *e;
26
27 for (i = 0; i < ARRAY_SIZE(mb_str); i++) {
28 e = mb_str + i;
29 if (cmd == e->cmd)
30 return e->str;
31 }
32 return "unknown";
33}
34
ca825828 35static struct rom_cmd {
77ddb94a 36 uint16_t cmd;
37} rom_cmds[] = {
38 { MBC_LOAD_RAM },
39 { MBC_EXECUTE_FIRMWARE },
40 { MBC_READ_RAM_WORD },
41 { MBC_MAILBOX_REGISTER_TEST },
42 { MBC_VERIFY_CHECKSUM },
43 { MBC_GET_FIRMWARE_VERSION },
44 { MBC_LOAD_RISC_RAM },
45 { MBC_DUMP_RISC_RAM },
46 { MBC_LOAD_RISC_RAM_EXTENDED },
47 { MBC_DUMP_RISC_RAM_EXTENDED },
48 { MBC_WRITE_RAM_WORD_EXTENDED },
49 { MBC_READ_RAM_EXTENDED },
50 { MBC_GET_RESOURCE_COUNTS },
51 { MBC_SET_FIRMWARE_OPTION },
52 { MBC_MID_INITIALIZE_FIRMWARE },
53 { MBC_GET_FIRMWARE_STATE },
54 { MBC_GET_MEM_OFFLOAD_CNTRL_STAT },
55 { MBC_GET_RETRY_COUNT },
56 { MBC_TRACE_CONTROL },
57};
58
59static int is_rom_cmd(uint16_t cmd)
60{
61 int i;
62 struct rom_cmd *wc;
63
64 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) {
65 wc = rom_cmds + i;
66 if (wc->cmd == cmd)
67 return 1;
68 }
69
70 return 0;
71}
1da177e4
LT		 72
73/*
74 * qla2x00_mailbox_command
75 * Issue mailbox command and waits for completion.
76 *
77 * Input:
78 * ha = adapter block pointer.
79 * mcp = driver internal mbx struct pointer.
80 *
81 * Output:
82 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
83 *
84 * Returns:
85 * 0 : QLA_SUCCESS = cmd performed success
86 * 1 : QLA_FUNCTION_FAILED (error encountered)
87 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
88 *
89 * Context:
90 * Kernel context.
91 */
92static int
7b867cf7 93qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
1da177e4 94{
d14e72fb 95 int rval, i;
1da177e4 96 unsigned long flags = 0;
f73cb695 97 device_reg_t *reg;
1c7c6357 98 uint8_t abort_active;
2c3dfe3f 99 uint8_t io_lock_on;
cdbb0a4f 100 uint16_t command = 0;
1da177e4
LT		 101 uint16_t *iptr;
102 uint16_t __iomem *optr;
103 uint32_t cnt;
104 uint32_t mboxes;
d14e72fb 105 uint16_t __iomem *mbx_reg;
1da177e4 106 unsigned long wait_time;
7b867cf7
AC		 107 struct qla_hw_data *ha = vha->hw;
108 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 109
d14e72fb 110
5e19ed90 111 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
7c3df132
SK		 112
113 if (ha->pdev->error_state > pci_channel_io_frozen) {
5e19ed90 114 ql_log(ql_log_warn, vha, 0x1001,
7c3df132
SK		 115 "error_state is greater than pci_channel_io_frozen, "
116 "exiting.\n");
b9b12f73 117 return QLA_FUNCTION_TIMEOUT;
7c3df132 118 }
b9b12f73 119
a9083016 120 if (vha->device_flags & DFLG_DEV_FAILED) {
5e19ed90 121 ql_log(ql_log_warn, vha, 0x1002,
7c3df132 122 "Device in failed state, exiting.\n");
a9083016
GM		 123 return QLA_FUNCTION_TIMEOUT;
124 }
125
c2a5d94f
BVA		 126 /* if PCI error, then avoid mbx processing.*/
127 if (test_bit(PCI_ERR, &base_vha->dpc_flags)) {
783e0dc4
SC		 128 ql_log(ql_log_warn, vha, 0x1191,
129 "PCI error, exiting.\n");
130 return QLA_FUNCTION_TIMEOUT;
c2a5d94f 131 }
783e0dc4 132
2c3dfe3f 133 reg = ha->iobase;
7b867cf7 134 io_lock_on = base_vha->flags.init_done;
1da177e4
LT		 135
136 rval = QLA_SUCCESS;
7b867cf7 137 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1c7c6357 138
1da177e4 139
85880801 140 if (ha->flags.pci_channel_io_perm_failure) {
5e19ed90 141 ql_log(ql_log_warn, vha, 0x1003,
7c3df132 142 "Perm failure on EEH timeout MBX, exiting.\n");
85880801
AV		 143 return QLA_FUNCTION_TIMEOUT;
144 }
145
7ec0effd 146 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
862cd01e
GM		 147 /* Setting Link-Down error */
148 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
5e19ed90 149 ql_log(ql_log_warn, vha, 0x1004,
7c3df132 150 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
1806fcd5 151 return QLA_FUNCTION_TIMEOUT;
862cd01e
GM		 152 }
153
77ddb94a 154 /* check if ISP abort is active and return cmd with timeout */
155 if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
156 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
157 test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
158 !is_rom_cmd(mcp->mb[0])) {
159 ql_log(ql_log_info, vha, 0x1005,
160 "Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
161 mcp->mb[0]);
162 return QLA_FUNCTION_TIMEOUT;
163 }
164
1da177e4 165 /*
1c7c6357
AV		 166 * Wait for active mailbox commands to finish by waiting at most tov
167 * seconds. This is to serialize actual issuing of mailbox cmds during
168 * non ISP abort time.
1da177e4 169 */
8eca3f39
AV		 170 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
171 /* Timeout occurred. Return error. */
5e19ed90 172 ql_log(ql_log_warn, vha, 0x1005,
d8c0d546
CD		 173 "Cmd access timeout, cmd=0x%x, Exiting.\n",
174 mcp->mb[0]);
8eca3f39 175 return QLA_FUNCTION_TIMEOUT;
1da177e4
LT		 176 }
177
178 ha->flags.mbox_busy = 1;
179 /* Save mailbox command for debug */
180 ha->mcp = mcp;
181
5e19ed90 182 ql_dbg(ql_dbg_mbx, vha, 0x1006,
7c3df132 183 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
1da177e4
LT		 184
185 spin_lock_irqsave(&ha->hardware_lock, flags);
186
187 /* Load mailbox registers. */
7ec0effd 188 if (IS_P3P_TYPE(ha))
a9083016 189 optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
7ec0effd 190 else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
1c7c6357
AV		 191 optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
192 else
193 optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
1da177e4
LT		 194
195 iptr = mcp->mb;
196 command = mcp->mb[0];
197 mboxes = mcp->out_mb;
198
7b711623 199 ql_dbg(ql_dbg_mbx, vha, 0x1111,
0e31a2c8 200 "Mailbox registers (OUT):\n");
1da177e4
LT		 201 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
202 if (IS_QLA2200(ha) && cnt == 8)
1c7c6357
AV		 203 optr =
204 (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
0e31a2c8
JC		 205 if (mboxes & BIT_0) {
206 ql_dbg(ql_dbg_mbx, vha, 0x1112,
207 "mbox[%d]<-0x%04x\n", cnt, *iptr);
1da177e4 208 WRT_REG_WORD(optr, *iptr);
0e31a2c8 209 }
1da177e4
LT		 210
211 mboxes >>= 1;
212 optr++;
213 iptr++;
214 }
215
5e19ed90 216 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
7c3df132 217 "I/O Address = %p.\n", optr);
1da177e4
LT		 218
219 /* Issue set host interrupt command to send cmd out. */
220 ha->flags.mbox_int = 0;
221 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
222
223 /* Unlock mbx registers and wait for interrupt */
5e19ed90 224 ql_dbg(ql_dbg_mbx, vha, 0x100f,
7c3df132
SK		 225 "Going to unlock irq & waiting for interrupts. "
226 "jiffies=%lx.\n", jiffies);
1da177e4
LT		 227
228 /* Wait for mbx cmd completion until timeout */
229
124f85e6 230 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
1da177e4
LT		 231 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
232
7ec0effd 233 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 234 if (RD_REG_DWORD(&reg->isp82.hint) &
235 HINT_MBX_INT_PENDING) {
236 spin_unlock_irqrestore(&ha->hardware_lock,
237 flags);
8937f2f1 238 ha->flags.mbox_busy = 0;
5e19ed90 239 ql_dbg(ql_dbg_mbx, vha, 0x1010,
7c3df132 240 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 241 rval = QLA_FUNCTION_TIMEOUT;
242 goto premature_exit;
a9083016
GM		 243 }
244 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
245 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 246 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
247 else
248 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4
LT		 249 spin_unlock_irqrestore(&ha->hardware_lock, flags);
250
77ddb94a 251 wait_time = jiffies;
754d1243
GM		 252 if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
253 mcp->tov * HZ)) {
254 ql_dbg(ql_dbg_mbx, vha, 0x117a,
255 "cmd=%x Timeout.\n", command);
256 spin_lock_irqsave(&ha->hardware_lock, flags);
257 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
258 spin_unlock_irqrestore(&ha->hardware_lock, flags);
259 }
77ddb94a 260 if (time_after(jiffies, wait_time + 5 * HZ))
261 ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
262 command, jiffies_to_msecs(jiffies - wait_time));
1da177e4 263 } else {
5e19ed90 264 ql_dbg(ql_dbg_mbx, vha, 0x1011,
7c3df132 265 "Cmd=%x Polling Mode.\n", command);
1da177e4 266
7ec0effd 267 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 268 if (RD_REG_DWORD(&reg->isp82.hint) &
269 HINT_MBX_INT_PENDING) {
270 spin_unlock_irqrestore(&ha->hardware_lock,
271 flags);
8937f2f1 272 ha->flags.mbox_busy = 0;
5e19ed90 273 ql_dbg(ql_dbg_mbx, vha, 0x1012,
7c3df132 274 "Pending mailbox timeout, exiting.\n");
cdbb0a4f
SV		 275 rval = QLA_FUNCTION_TIMEOUT;
276 goto premature_exit;
a9083016
GM		 277 }
278 WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
279 } else if (IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 280 WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
281 else
282 WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
1da177e4 283 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4
LT		 284
285 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
286 while (!ha->flags.mbox_int) {
287 if (time_after(jiffies, wait_time))
288 break;
289
290 /* Check for pending interrupts. */
73208dfd 291 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4 292
85880801
AV		 293 if (!ha->flags.mbox_int &&
294 !(IS_QLA2200(ha) &&
295 command == MBC_LOAD_RISC_RAM_EXTENDED))
59989831 296 msleep(10);
1da177e4 297 } /* while */
5e19ed90 298 ql_dbg(ql_dbg_mbx, vha, 0x1013,
7c3df132
SK		 299 "Waited %d sec.\n",
300 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
1da177e4
LT		 301 }
302
1da177e4
LT		 303 /* Check whether we timed out */
304 if (ha->flags.mbox_int) {
305 uint16_t *iptr2;
306
5e19ed90 307 ql_dbg(ql_dbg_mbx, vha, 0x1014,
7c3df132 308 "Cmd=%x completed.\n", command);
1da177e4
LT		 309
310 /* Got interrupt. Clear the flag. */
311 ha->flags.mbox_int = 0;
312 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
313
7ec0effd 314 if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
cdbb0a4f
SV		 315 ha->flags.mbox_busy = 0;
316 /* Setting Link-Down error */
317 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
318 ha->mcp = NULL;
319 rval = QLA_FUNCTION_FAILED;
5e19ed90 320 ql_log(ql_log_warn, vha, 0x1015,
7c3df132 321 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
cdbb0a4f
SV		 322 goto premature_exit;
323 }
324
354d6b21 325 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
1da177e4 326 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 327
328 /* Load return mailbox registers. */
329 iptr2 = mcp->mb;
330 iptr = (uint16_t *)&ha->mailbox_out[0];
331 mboxes = mcp->in_mb;
0e31a2c8
JC		 332
333 ql_dbg(ql_dbg_mbx, vha, 0x1113,
334 "Mailbox registers (IN):\n");
1da177e4 335 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
0e31a2c8 336 if (mboxes & BIT_0) {
1da177e4 337 *iptr2 = *iptr;
0e31a2c8
JC		 338 ql_dbg(ql_dbg_mbx, vha, 0x1114,
339 "mbox[%d]->0x%04x\n", cnt, *iptr2);
340 }
1da177e4
LT		 341
342 mboxes >>= 1;
343 iptr2++;
344 iptr++;
345 }
346 } else {
347
8d3c9c23
QT		 348 uint16_t mb[8];
349 uint32_t ictrl, host_status, hccr;
783e0dc4 350 uint16_t w;
1c7c6357 351
e428924c 352 if (IS_FWI2_CAPABLE(ha)) {
8d3c9c23
QT		 353 mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
354 mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
355 mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
356 mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
357 mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
1c7c6357 358 ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
8d3c9c23
QT		 359 host_status = RD_REG_DWORD(&reg->isp24.host_status);
360 hccr = RD_REG_DWORD(&reg->isp24.hccr);
361
362 ql_log(ql_log_warn, vha, 0x1119,
363 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
364 "mb[0-3]=[0x%x 0x%x 0x%x 0x%x] mb7 0x%x host_status 0x%x hccr 0x%x\n",
365 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3],
366 mb[7], host_status, hccr);
367
1c7c6357 368 } else {
8d3c9c23 369 mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
1c7c6357 370 ictrl = RD_REG_WORD(&reg->isp.ictrl);
8d3c9c23
QT		 371 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
372 "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
373 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
1c7c6357 374 }
5e19ed90 375 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
1da177e4 376
783e0dc4
SC		 377 /* Capture FW dump only, if PCI device active */
378 if (!pci_channel_offline(vha->hw->pdev)) {
379 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
380 if (w == 0xffff || ictrl == 0xffffffff) {
381 /* This is special case if there is unload
382 * of driver happening and if PCI device go
383 * into bad state due to PCI error condition
384 * then only PCI ERR flag would be set.
385 * we will do premature exit for above case.
386 */
387 if (test_bit(UNLOADING, &base_vha->dpc_flags))
388 set_bit(PCI_ERR, &base_vha->dpc_flags);
389 ha->flags.mbox_busy = 0;
390 rval = QLA_FUNCTION_TIMEOUT;
391 goto premature_exit;
392 }
f55bfc88 393
783e0dc4
SC		 394 /* Attempt to capture firmware dump for further
395 * anallysis of the current formware state. we do not
396 * need to do this if we are intentionally generating
397 * a dump
398 */
399 if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
400 ha->isp_ops->fw_dump(vha, 0);
401 rval = QLA_FUNCTION_TIMEOUT;
402 }
1da177e4
LT		 403 }
404
1da177e4
LT		 405 ha->flags.mbox_busy = 0;
406
407 /* Clean up */
408 ha->mcp = NULL;
409
124f85e6 410 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
5e19ed90 411 ql_dbg(ql_dbg_mbx, vha, 0x101a,
7c3df132 412 "Checking for additional resp interrupt.\n");
1da177e4
LT		 413
414 /* polling mode for non isp_abort commands. */
73208dfd 415 qla2x00_poll(ha->rsp_q_map[0]);
1da177e4
LT		 416 }
417
1c7c6357
AV		 418 if (rval == QLA_FUNCTION_TIMEOUT &&
419 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
85880801
AV		 420 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
421 ha->flags.eeh_busy) {
1da177e4 422 /* not in dpc. schedule it for dpc to take over. */
5e19ed90 423 ql_dbg(ql_dbg_mbx, vha, 0x101b,
7c3df132 424 "Timeout, schedule isp_abort_needed.\n");
cdbb0a4f
SV		 425
426 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
427 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
428 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 429 if (IS_QLA82XX(ha)) {
430 ql_dbg(ql_dbg_mbx, vha, 0x112a,
431 "disabling pause transmit on port "
432 "0 & 1.\n");
433 qla82xx_wr_32(ha,
434 QLA82XX_CRB_NIU + 0x98,
435 CRB_NIU_XG_PAUSE_CTL_P0|
436 CRB_NIU_XG_PAUSE_CTL_P1);
437 }
7c3df132 438 ql_log(ql_log_info, base_vha, 0x101c,
24d9ee85 439 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 440 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
441 "abort.\n", command, mcp->mb[0],
442 ha->flags.eeh_busy);
cdbb0a4f
SV		 443 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
444 qla2xxx_wake_dpc(vha);
445 }
1da177e4 446 } else if (!abort_active) {
1da177e4 447 /* call abort directly since we are in the DPC thread */
5e19ed90 448 ql_dbg(ql_dbg_mbx, vha, 0x101d,
7c3df132 449 "Timeout, calling abort_isp.\n");
cdbb0a4f
SV		 450
451 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
452 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
453 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
63154916
GM		 454 if (IS_QLA82XX(ha)) {
455 ql_dbg(ql_dbg_mbx, vha, 0x112b,
456 "disabling pause transmit on port "
457 "0 & 1.\n");
458 qla82xx_wr_32(ha,
459 QLA82XX_CRB_NIU + 0x98,
460 CRB_NIU_XG_PAUSE_CTL_P0|
461 CRB_NIU_XG_PAUSE_CTL_P1);
462 }
7c3df132 463 ql_log(ql_log_info, base_vha, 0x101e,
24d9ee85 464 "Mailbox cmd timeout occurred, cmd=0x%x, "
d8c0d546
CD		 465 "mb[0]=0x%x. Scheduling ISP abort ",
466 command, mcp->mb[0]);
cdbb0a4f
SV		 467 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
468 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
d3360960
GM		 469 /* Allow next mbx cmd to come in. */
470 complete(&ha->mbx_cmd_comp);
cdbb0a4f
SV		 471 if (ha->isp_ops->abort_isp(vha)) {
472 /* Failed. retry later. */
473 set_bit(ISP_ABORT_NEEDED,
474 &vha->dpc_flags);
475 }
476 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
5e19ed90 477 ql_dbg(ql_dbg_mbx, vha, 0x101f,
7c3df132 478 "Finished abort_isp.\n");
d3360960 479 goto mbx_done;
1da177e4 480 }
1da177e4
LT		 481 }
482 }
483
cdbb0a4f 484premature_exit:
1da177e4 485 /* Allow next mbx cmd to come in. */
8eca3f39 486 complete(&ha->mbx_cmd_comp);
1da177e4 487
d3360960 488mbx_done:
1da177e4 489 if (rval) {
34c5801d 490 ql_dbg(ql_dbg_disc, base_vha, 0x1020,
6246b8a1
GM		 491 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
492 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
d14e72fb 493
75d560e0 494 ql_dbg(ql_dbg_mbx, vha, 0x1198,
d14e72fb
HM		 495 "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n",
496 RD_REG_DWORD(&reg->isp24.host_status),
497 ha->fw_dump_cap_flags,
498 RD_REG_DWORD(&reg->isp24.ictrl),
499 RD_REG_DWORD(&reg->isp24.istatus));
500
501 mbx_reg = &reg->isp24.mailbox0;
502 for (i = 0; i < 6; i++)
75d560e0 503 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1199,
d14e72fb 504 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
1da177e4 505 } else {
7c3df132 506 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
1da177e4
LT		 507 }
508
1da177e4
LT		 509 return rval;
510}
511
1da177e4 512int
7b867cf7 513qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
590f98e5 514 uint32_t risc_code_size)
1da177e4
LT		 515{
516 int rval;
7b867cf7 517 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 518 mbx_cmd_t mc;
519 mbx_cmd_t *mcp = &mc;
1da177e4 520
5f28d2d7
SK		 521 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
522 "Entered %s.\n", __func__);
1da177e4 523
e428924c 524 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
590f98e5
AV		 525 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
526 mcp->mb[8] = MSW(risc_addr);
527 mcp->out_mb = MBX_8|MBX_0;
1da177e4 528 } else {
590f98e5
AV		 529 mcp->mb[0] = MBC_LOAD_RISC_RAM;
530 mcp->out_mb = MBX_0;
1da177e4 531 }
1da177e4
LT		 532 mcp->mb[1] = LSW(risc_addr);
533 mcp->mb[2] = MSW(req_dma);
534 mcp->mb[3] = LSW(req_dma);
1da177e4
LT		 535 mcp->mb[6] = MSW(MSD(req_dma));
536 mcp->mb[7] = LSW(MSD(req_dma));
590f98e5 537 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
e428924c 538 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 539 mcp->mb[4] = MSW(risc_code_size);
540 mcp->mb[5] = LSW(risc_code_size);
541 mcp->out_mb |= MBX_5|MBX_4;
542 } else {
543 mcp->mb[4] = LSW(risc_code_size);
544 mcp->out_mb |= MBX_4;
545 }
546
1da177e4 547 mcp->in_mb = MBX_0;
b93480e3 548 mcp->tov = MBX_TOV_SECONDS;
1da177e4 549 mcp->flags = 0;
7b867cf7 550 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 551
1da177e4 552 if (rval != QLA_SUCCESS) {
7c3df132
SK		 553 ql_dbg(ql_dbg_mbx, vha, 0x1023,
554 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4 555 } else {
5f28d2d7
SK		 556 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
557 "Done %s.\n", __func__);
1da177e4
LT		 558 }
559
560 return rval;
561}
562
cad454b1 563#define EXTENDED_BB_CREDITS BIT_0
1da177e4
LT		 564/*
565 * qla2x00_execute_fw
1c7c6357 566 * Start adapter firmware.
1da177e4
LT		 567 *
568 * Input:
1c7c6357
AV		 569 * ha = adapter block pointer.
570 * TARGET_QUEUE_LOCK must be released.
571 * ADAPTER_STATE_LOCK must be released.
1da177e4
LT		 572 *
573 * Returns:
1c7c6357 574 * qla2x00 local function return status code.
1da177e4
LT		 575 *
576 * Context:
1c7c6357 577 * Kernel context.
1da177e4
LT		 578 */
579int
7b867cf7 580qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 581{
582 int rval;
7b867cf7 583 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 584 mbx_cmd_t mc;
585 mbx_cmd_t *mcp = &mc;
586
5f28d2d7
SK		 587 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
588 "Entered %s.\n", __func__);
1da177e4
LT		 589
590 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
1c7c6357
AV		 591 mcp->out_mb = MBX_0;
592 mcp->in_mb = MBX_0;
e428924c 593 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 594 mcp->mb[1] = MSW(risc_addr);
595 mcp->mb[2] = LSW(risc_addr);
596 mcp->mb[3] = 0;
f73cb695
CD		 597 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
598 IS_QLA27XX(ha)) {
cad454b1
SV		 599 struct nvram_81xx *nv = ha->nvram;
600 mcp->mb[4] = (nv->enhanced_features &
601 EXTENDED_BB_CREDITS);
602 } else
603 mcp->mb[4] = 0;
b0d6cabd
HM		 604
605 if (ha->flags.exlogins_enabled)
606 mcp->mb[4] |= ENABLE_EXTENDED_LOGIN;
607
2f56a7f1
HM		 608 if (ha->flags.exchoffld_enabled)
609 mcp->mb[4] |= ENABLE_EXCHANGE_OFFLD;
610
8b3253d1 611 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
1c7c6357
AV		 612 mcp->in_mb |= MBX_1;
613 } else {
614 mcp->mb[1] = LSW(risc_addr);
615 mcp->out_mb |= MBX_1;
616 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
617 mcp->mb[2] = 0;
618 mcp->out_mb |= MBX_2;
619 }
1da177e4
LT		 620 }
621
b93480e3 622 mcp->tov = MBX_TOV_SECONDS;
1da177e4 623 mcp->flags = 0;
7b867cf7 624 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 625
1c7c6357 626 if (rval != QLA_SUCCESS) {
7c3df132
SK		 627 ql_dbg(ql_dbg_mbx, vha, 0x1026,
628 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357 629 } else {
e428924c 630 if (IS_FWI2_CAPABLE(ha)) {
5f28d2d7 631 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
7c3df132 632 "Done exchanges=%x.\n", mcp->mb[1]);
1c7c6357 633 } else {
5f28d2d7
SK		 634 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
635 "Done %s.\n", __func__);
1c7c6357
AV		 636 }
637 }
1da177e4
LT		 638
639 return rval;
640}
641
b0d6cabd
HM		 642/*
643 * qla_get_exlogin_status
644 * Get extended login status
645 * uses the memory offload control/status Mailbox
646 *
647 * Input:
648 * ha: adapter state pointer.
649 * fwopt: firmware options
650 *
651 * Returns:
652 * qla2x00 local function status
653 *
654 * Context:
655 * Kernel context.
656 */
657#define FETCH_XLOGINS_STAT 0x8
658int
659qla_get_exlogin_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
660 uint16_t *ex_logins_cnt)
661{
662 int rval;
663 mbx_cmd_t mc;
664 mbx_cmd_t *mcp = &mc;
665
666 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118f,
667 "Entered %s\n", __func__);
668
669 memset(mcp->mb, 0 , sizeof(mcp->mb));
670 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
671 mcp->mb[1] = FETCH_XLOGINS_STAT;
672 mcp->out_mb = MBX_1|MBX_0;
673 mcp->in_mb = MBX_10|MBX_4|MBX_0;
674 mcp->tov = MBX_TOV_SECONDS;
675 mcp->flags = 0;
676
677 rval = qla2x00_mailbox_command(vha, mcp);
678 if (rval != QLA_SUCCESS) {
679 ql_dbg(ql_dbg_mbx, vha, 0x1115, "Failed=%x.\n", rval);
680 } else {
681 *buf_sz = mcp->mb[4];
682 *ex_logins_cnt = mcp->mb[10];
683
684 ql_log(ql_log_info, vha, 0x1190,
685 "buffer size 0x%x, exchange login count=%d\n",
686 mcp->mb[4], mcp->mb[10]);
687
688 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1116,
689 "Done %s.\n", __func__);
690 }
691
692 return rval;
693}
694
695/*
696 * qla_set_exlogin_mem_cfg
697 * set extended login memory configuration
698 * Mbx needs to be issues before init_cb is set
699 *
700 * Input:
701 * ha: adapter state pointer.
702 * buffer: buffer pointer
703 * phys_addr: physical address of buffer
704 * size: size of buffer
705 * TARGET_QUEUE_LOCK must be released
706 * ADAPTER_STATE_LOCK must be release
707 *
708 * Returns:
709 * qla2x00 local funxtion status code.
710 *
711 * Context:
712 * Kernel context.
713 */
714#define CONFIG_XLOGINS_MEM 0x3
715int
716qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
717{
718 int rval;
719 mbx_cmd_t mc;
720 mbx_cmd_t *mcp = &mc;
721 struct qla_hw_data *ha = vha->hw;
b0d6cabd
HM		 722
723 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111a,
724 "Entered %s.\n", __func__);
725
726 memset(mcp->mb, 0 , sizeof(mcp->mb));
727 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
728 mcp->mb[1] = CONFIG_XLOGINS_MEM;
729 mcp->mb[2] = MSW(phys_addr);
730 mcp->mb[3] = LSW(phys_addr);
731 mcp->mb[6] = MSW(MSD(phys_addr));
732 mcp->mb[7] = LSW(MSD(phys_addr));
733 mcp->mb[8] = MSW(ha->exlogin_size);
734 mcp->mb[9] = LSW(ha->exlogin_size);
735 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
736 mcp->in_mb = MBX_11|MBX_0;
737 mcp->tov = MBX_TOV_SECONDS;
738 mcp->flags = 0;
739 rval = qla2x00_mailbox_command(vha, mcp);
740 if (rval != QLA_SUCCESS) {
741 /*EMPTY*/
742 ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
743 } else {
b0d6cabd
HM		 744 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
745 "Done %s.\n", __func__);
746 }
747
748 return rval;
749}
750
2f56a7f1
HM		 751/*
752 * qla_get_exchoffld_status
753 * Get exchange offload status
754 * uses the memory offload control/status Mailbox
755 *
756 * Input:
757 * ha: adapter state pointer.
758 * fwopt: firmware options
759 *
760 * Returns:
761 * qla2x00 local function status
762 *
763 * Context:
764 * Kernel context.
765 */
766#define FETCH_XCHOFFLD_STAT 0x2
767int
768qla_get_exchoffld_status(scsi_qla_host_t *vha, uint16_t *buf_sz,
769 uint16_t *ex_logins_cnt)
770{
771 int rval;
772 mbx_cmd_t mc;
773 mbx_cmd_t *mcp = &mc;
774
775 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1019,
776 "Entered %s\n", __func__);
777
778 memset(mcp->mb, 0 , sizeof(mcp->mb));
779 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
780 mcp->mb[1] = FETCH_XCHOFFLD_STAT;
781 mcp->out_mb = MBX_1|MBX_0;
782 mcp->in_mb = MBX_10|MBX_4|MBX_0;
783 mcp->tov = MBX_TOV_SECONDS;
784 mcp->flags = 0;
785
786 rval = qla2x00_mailbox_command(vha, mcp);
787 if (rval != QLA_SUCCESS) {
788 ql_dbg(ql_dbg_mbx, vha, 0x1155, "Failed=%x.\n", rval);
789 } else {
790 *buf_sz = mcp->mb[4];
791 *ex_logins_cnt = mcp->mb[10];
792
793 ql_log(ql_log_info, vha, 0x118e,
794 "buffer size 0x%x, exchange offload count=%d\n",
795 mcp->mb[4], mcp->mb[10]);
796
797 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1156,
798 "Done %s.\n", __func__);
799 }
800
801 return rval;
802}
803
804/*
805 * qla_set_exchoffld_mem_cfg
806 * Set exchange offload memory configuration
807 * Mbx needs to be issues before init_cb is set
808 *
809 * Input:
810 * ha: adapter state pointer.
811 * buffer: buffer pointer
812 * phys_addr: physical address of buffer
813 * size: size of buffer
814 * TARGET_QUEUE_LOCK must be released
815 * ADAPTER_STATE_LOCK must be release
816 *
817 * Returns:
818 * qla2x00 local funxtion status code.
819 *
820 * Context:
821 * Kernel context.
822 */
823#define CONFIG_XCHOFFLD_MEM 0x3
824int
825qla_set_exchoffld_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
826{
827 int rval;
828 mbx_cmd_t mc;
829 mbx_cmd_t *mcp = &mc;
830 struct qla_hw_data *ha = vha->hw;
831
832 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1157,
833 "Entered %s.\n", __func__);
834
835 memset(mcp->mb, 0 , sizeof(mcp->mb));
836 mcp->mb[0] = MBC_GET_MEM_OFFLOAD_CNTRL_STAT;
837 mcp->mb[1] = CONFIG_XCHOFFLD_MEM;
838 mcp->mb[2] = MSW(phys_addr);
839 mcp->mb[3] = LSW(phys_addr);
840 mcp->mb[6] = MSW(MSD(phys_addr));
841 mcp->mb[7] = LSW(MSD(phys_addr));
842 mcp->mb[8] = MSW(ha->exlogin_size);
843 mcp->mb[9] = LSW(ha->exlogin_size);
844 mcp->out_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
845 mcp->in_mb = MBX_11|MBX_0;
846 mcp->tov = MBX_TOV_SECONDS;
847 mcp->flags = 0;
848 rval = qla2x00_mailbox_command(vha, mcp);
849 if (rval != QLA_SUCCESS) {
850 /*EMPTY*/
851 ql_dbg(ql_dbg_mbx, vha, 0x1158, "Failed=%x.\n", rval);
852 } else {
853 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
854 "Done %s.\n", __func__);
855 }
856
857 return rval;
858}
859
1da177e4
LT		 860/*
861 * qla2x00_get_fw_version
862 * Get firmware version.
863 *
864 * Input:
865 * ha: adapter state pointer.
866 * major: pointer for major number.
867 * minor: pointer for minor number.
868 * subminor: pointer for subminor number.
869 *
870 * Returns:
871 * qla2x00 local function return status code.
872 *
873 * Context:
874 * Kernel context.
875 */
ca9e9c3e 876int
6246b8a1 877qla2x00_get_fw_version(scsi_qla_host_t *vha)
1da177e4
LT		 878{
879 int rval;
880 mbx_cmd_t mc;
881 mbx_cmd_t *mcp = &mc;
6246b8a1 882 struct qla_hw_data *ha = vha->hw;
1da177e4 883
5f28d2d7
SK		 884 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
885 "Entered %s.\n", __func__);
1da177e4
LT		 886
887 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
888 mcp->out_mb = MBX_0;
889 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
7ec0effd 890 if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
55a96158 891 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
fb0effee 892 if (IS_FWI2_CAPABLE(ha))
6246b8a1 893 mcp->in_mb |= MBX_17|MBX_16|MBX_15;
f73cb695 894 if (IS_QLA27XX(ha))
ad1ef177
JC		 895 mcp->in_mb |=
896 MBX_25|MBX_24|MBX_23|MBX_22|MBX_21|MBX_20|MBX_19|MBX_18|
897 MBX_14|MBX_13|MBX_11|MBX_10|MBX_9|MBX_8;
03aa868c 898
1da177e4 899 mcp->flags = 0;
b93480e3 900 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 901 rval = qla2x00_mailbox_command(vha, mcp);
ca9e9c3e
AV		 902 if (rval != QLA_SUCCESS)
903 goto failed;
1da177e4
LT		 904
905 /* Return mailbox data. */
6246b8a1
GM		 906 ha->fw_major_version = mcp->mb[1];
907 ha->fw_minor_version = mcp->mb[2];
908 ha->fw_subminor_version = mcp->mb[3];
909 ha->fw_attributes = mcp->mb[6];
7b867cf7 910 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
6246b8a1 911 ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
1da177e4 912 else
6246b8a1 913 ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
03aa868c 914
7ec0effd 915 if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
6246b8a1
GM		 916 ha->mpi_version[0] = mcp->mb[10] & 0xff;
917 ha->mpi_version[1] = mcp->mb[11] >> 8;
918 ha->mpi_version[2] = mcp->mb[11] & 0xff;
919 ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
920 ha->phy_version[0] = mcp->mb[8] & 0xff;
921 ha->phy_version[1] = mcp->mb[9] >> 8;
922 ha->phy_version[2] = mcp->mb[9] & 0xff;
923 }
03aa868c 924
81178772
SK		 925 if (IS_FWI2_CAPABLE(ha)) {
926 ha->fw_attributes_h = mcp->mb[15];
927 ha->fw_attributes_ext[0] = mcp->mb[16];
928 ha->fw_attributes_ext[1] = mcp->mb[17];
929 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
930 "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
931 __func__, mcp->mb[15], mcp->mb[6]);
932 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
933 "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
934 __func__, mcp->mb[17], mcp->mb[16]);
2f56a7f1 935
b0d6cabd
HM		 936 if (ha->fw_attributes_h & 0x4)
937 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118d,
938 "%s: Firmware supports Extended Login 0x%x\n",
939 __func__, ha->fw_attributes_h);
2f56a7f1
HM		 940
941 if (ha->fw_attributes_h & 0x8)
942 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1191,
943 "%s: Firmware supports Exchange Offload 0x%x\n",
944 __func__, ha->fw_attributes_h);
3a03eb79 945 }
03aa868c 946
f73cb695 947 if (IS_QLA27XX(ha)) {
03aa868c
SC		 948 ha->mpi_version[0] = mcp->mb[10] & 0xff;
949 ha->mpi_version[1] = mcp->mb[11] >> 8;
950 ha->mpi_version[2] = mcp->mb[11] & 0xff;
951 ha->pep_version[0] = mcp->mb[13] & 0xff;
952 ha->pep_version[1] = mcp->mb[14] >> 8;
953 ha->pep_version[2] = mcp->mb[14] & 0xff;
f73cb695
CD		 954 ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
955 ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
ad1ef177
JC		 956 ha->fw_ddr_ram_start = (mcp->mb[23] << 16) | mcp->mb[22];
957 ha->fw_ddr_ram_end = (mcp->mb[25] << 16) | mcp->mb[24];
f73cb695 958 }
6246b8a1 959
ca9e9c3e 960failed:
1da177e4
LT		 961 if (rval != QLA_SUCCESS) {
962 /*EMPTY*/
7c3df132 963 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
1da177e4
LT		 964 } else {
965 /*EMPTY*/
5f28d2d7
SK		 966 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
967 "Done %s.\n", __func__);
1da177e4 968 }
ca9e9c3e 969 return rval;
1da177e4
LT		 970}
971
972/*
973 * qla2x00_get_fw_options
974 * Set firmware options.
975 *
976 * Input:
977 * ha = adapter block pointer.
978 * fwopt = pointer for firmware options.
979 *
980 * Returns:
981 * qla2x00 local function return status code.
982 *
983 * Context:
984 * Kernel context.
985 */
986int
7b867cf7 987qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 988{
989 int rval;
990 mbx_cmd_t mc;
991 mbx_cmd_t *mcp = &mc;
992
5f28d2d7
SK		 993 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
994 "Entered %s.\n", __func__);
1da177e4
LT		 995
996 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
997 mcp->out_mb = MBX_0;
998 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 999 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1000 mcp->flags = 0;
7b867cf7 1001 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1002
1003 if (rval != QLA_SUCCESS) {
1004 /*EMPTY*/
7c3df132 1005 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
1da177e4 1006 } else {
1c7c6357 1007 fwopts[0] = mcp->mb[0];
1da177e4
LT		 1008 fwopts[1] = mcp->mb[1];
1009 fwopts[2] = mcp->mb[2];
1010 fwopts[3] = mcp->mb[3];
1011
5f28d2d7
SK		 1012 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
1013 "Done %s.\n", __func__);
1da177e4
LT		 1014 }
1015
1016 return rval;
1017}
1018
1019
1020/*
1021 * qla2x00_set_fw_options
1022 * Set firmware options.
1023 *
1024 * Input:
1025 * ha = adapter block pointer.
1026 * fwopt = pointer for firmware options.
1027 *
1028 * Returns:
1029 * qla2x00 local function return status code.
1030 *
1031 * Context:
1032 * Kernel context.
1033 */
1034int
7b867cf7 1035qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
1da177e4
LT		 1036{
1037 int rval;
1038 mbx_cmd_t mc;
1039 mbx_cmd_t *mcp = &mc;
1040
5f28d2d7
SK		 1041 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
1042 "Entered %s.\n", __func__);
1da177e4
LT		 1043
1044 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
1045 mcp->mb[1] = fwopts[1];
1046 mcp->mb[2] = fwopts[2];
1047 mcp->mb[3] = fwopts[3];
1c7c6357 1048 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 1049 mcp->in_mb = MBX_0;
7b867cf7 1050 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 1051 mcp->in_mb |= MBX_1;
1052 } else {
1053 mcp->mb[10] = fwopts[10];
1054 mcp->mb[11] = fwopts[11];
1055 mcp->mb[12] = 0; /* Undocumented, but used */
1056 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
1057 }
b93480e3 1058 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1059 mcp->flags = 0;
7b867cf7 1060 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1061
1c7c6357
AV		 1062 fwopts[0] = mcp->mb[0];
1063
1da177e4
LT		 1064 if (rval != QLA_SUCCESS) {
1065 /*EMPTY*/
7c3df132
SK		 1066 ql_dbg(ql_dbg_mbx, vha, 0x1030,
1067 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 1068 } else {
1069 /*EMPTY*/
5f28d2d7
SK		 1070 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
1071 "Done %s.\n", __func__);
1da177e4
LT		 1072 }
1073
1074 return rval;
1075}
1076
1077/*
1078 * qla2x00_mbx_reg_test
1079 * Mailbox register wrap test.
1080 *
1081 * Input:
1082 * ha = adapter block pointer.
1083 * TARGET_QUEUE_LOCK must be released.
1084 * ADAPTER_STATE_LOCK must be released.
1085 *
1086 * Returns:
1087 * qla2x00 local function return status code.
1088 *
1089 * Context:
1090 * Kernel context.
1091 */
1092int
7b867cf7 1093qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
1da177e4
LT		 1094{
1095 int rval;
1096 mbx_cmd_t mc;
1097 mbx_cmd_t *mcp = &mc;
1098
5f28d2d7
SK		 1099 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
1100 "Entered %s.\n", __func__);
1da177e4
LT		 1101
1102 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
1103 mcp->mb[1] = 0xAAAA;
1104 mcp->mb[2] = 0x5555;
1105 mcp->mb[3] = 0xAA55;
1106 mcp->mb[4] = 0x55AA;
1107 mcp->mb[5] = 0xA5A5;
1108 mcp->mb[6] = 0x5A5A;
1109 mcp->mb[7] = 0x2525;
1110 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1111 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1112 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1113 mcp->flags = 0;
7b867cf7 1114 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1115
1116 if (rval == QLA_SUCCESS) {
1117 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
1118 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
1119 rval = QLA_FUNCTION_FAILED;
1120 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
1121 mcp->mb[7] != 0x2525)
1122 rval = QLA_FUNCTION_FAILED;
1123 }
1124
1125 if (rval != QLA_SUCCESS) {
1126 /*EMPTY*/
7c3df132 1127 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
1da177e4
LT		 1128 } else {
1129 /*EMPTY*/
5f28d2d7
SK		 1130 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
1131 "Done %s.\n", __func__);
1da177e4
LT		 1132 }
1133
1134 return rval;
1135}
1136
1137/*
1138 * qla2x00_verify_checksum
1139 * Verify firmware checksum.
1140 *
1141 * Input:
1142 * ha = adapter block pointer.
1143 * TARGET_QUEUE_LOCK must be released.
1144 * ADAPTER_STATE_LOCK must be released.
1145 *
1146 * Returns:
1147 * qla2x00 local function return status code.
1148 *
1149 * Context:
1150 * Kernel context.
1151 */
1152int
7b867cf7 1153qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
1da177e4
LT		 1154{
1155 int rval;
1156 mbx_cmd_t mc;
1157 mbx_cmd_t *mcp = &mc;
1158
5f28d2d7
SK		 1159 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
1160 "Entered %s.\n", __func__);
1da177e4
LT		 1161
1162 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
1c7c6357
AV		 1163 mcp->out_mb = MBX_0;
1164 mcp->in_mb = MBX_0;
7b867cf7 1165 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 1166 mcp->mb[1] = MSW(risc_addr);
1167 mcp->mb[2] = LSW(risc_addr);
1168 mcp->out_mb |= MBX_2|MBX_1;
1169 mcp->in_mb |= MBX_2|MBX_1;
1170 } else {
1171 mcp->mb[1] = LSW(risc_addr);
1172 mcp->out_mb |= MBX_1;
1173 mcp->in_mb |= MBX_1;
1174 }
1175
b93480e3 1176 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1177 mcp->flags = 0;
7b867cf7 1178 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1179
1180 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1181 ql_dbg(ql_dbg_mbx, vha, 0x1036,
1182 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
1183 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
1da177e4 1184 } else {
5f28d2d7
SK		 1185 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
1186 "Done %s.\n", __func__);
1da177e4
LT		 1187 }
1188
1189 return rval;
1190}
1191
1192/*
1193 * qla2x00_issue_iocb
1194 * Issue IOCB using mailbox command
1195 *
1196 * Input:
1197 * ha = adapter state pointer.
1198 * buffer = buffer pointer.
1199 * phys_addr = physical address of buffer.
1200 * size = size of buffer.
1201 * TARGET_QUEUE_LOCK must be released.
1202 * ADAPTER_STATE_LOCK must be released.
1203 *
1204 * Returns:
1205 * qla2x00 local function return status code.
1206 *
1207 * Context:
1208 * Kernel context.
1209 */
6e98016c 1210int
7b867cf7 1211qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
4d4df193 1212 dma_addr_t phys_addr, size_t size, uint32_t tov)
1da177e4
LT		 1213{
1214 int rval;
1215 mbx_cmd_t mc;
1216 mbx_cmd_t *mcp = &mc;
1217
5f28d2d7
SK		 1218 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1219 "Entered %s.\n", __func__);
7c3df132 1220
1da177e4
LT		 1221 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1222 mcp->mb[1] = 0;
1223 mcp->mb[2] = MSW(phys_addr);
1224 mcp->mb[3] = LSW(phys_addr);
1225 mcp->mb[6] = MSW(MSD(phys_addr));
1226 mcp->mb[7] = LSW(MSD(phys_addr));
1227 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1228 mcp->in_mb = MBX_2|MBX_0;
4d4df193 1229 mcp->tov = tov;
1da177e4 1230 mcp->flags = 0;
7b867cf7 1231 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1232
1233 if (rval != QLA_SUCCESS) {
1234 /*EMPTY*/
7c3df132 1235 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1da177e4 1236 } else {
8c958a99
AV		 1237 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
1238
1239 /* Mask reserved bits. */
1240 sts_entry->entry_status &=
7b867cf7 1241 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
5f28d2d7
SK		 1242 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1243 "Done %s.\n", __func__);
1da177e4
LT		 1244 }
1245
1246 return rval;
1247}
1248
4d4df193 1249int
7b867cf7 1250qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
4d4df193
HK		 1251 size_t size)
1252{
7b867cf7 1253 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
4d4df193
HK		 1254 MBX_TOV_SECONDS);
1255}
1256
1da177e4
LT		 1257/*
1258 * qla2x00_abort_command
1259 * Abort command aborts a specified IOCB.
1260 *
1261 * Input:
1262 * ha = adapter block pointer.
1263 * sp = SB structure pointer.
1264 *
1265 * Returns:
1266 * qla2x00 local function return status code.
1267 *
1268 * Context:
1269 * Kernel context.
1270 */
1271int
2afa19a9 1272qla2x00_abort_command(srb_t *sp)
1da177e4
LT		 1273{
1274 unsigned long flags = 0;
1da177e4 1275 int rval;
73208dfd 1276 uint32_t handle = 0;
1da177e4
LT		 1277 mbx_cmd_t mc;
1278 mbx_cmd_t *mcp = &mc;
2afa19a9
AC		 1279 fc_port_t *fcport = sp->fcport;
1280 scsi_qla_host_t *vha = fcport->vha;
7b867cf7 1281 struct qla_hw_data *ha = vha->hw;
d7459527 1282 struct req_que *req;
9ba56b95 1283 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1da177e4 1284
5f28d2d7
SK		 1285 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1286 "Entered %s.\n", __func__);
1da177e4 1287
d7459527
MH		 1288 if (vha->flags.qpairs_available && sp->qpair)
1289 req = sp->qpair->req;
1290 else
1291 req = vha->req;
1292
c9c5ced9 1293 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 1294 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 1295 if (req->outstanding_cmds[handle] == sp)
1da177e4
LT		 1296 break;
1297 }
c9c5ced9 1298 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1299
8d93f550 1300 if (handle == req->num_outstanding_cmds) {
1da177e4
LT		 1301 /* command not found */
1302 return QLA_FUNCTION_FAILED;
1303 }
1304
1305 mcp->mb[0] = MBC_ABORT_COMMAND;
1306 if (HAS_EXTENDED_IDS(ha))
1307 mcp->mb[1] = fcport->loop_id;
1308 else
1309 mcp->mb[1] = fcport->loop_id << 8;
1310 mcp->mb[2] = (uint16_t)handle;
1311 mcp->mb[3] = (uint16_t)(handle >> 16);
9ba56b95 1312 mcp->mb[6] = (uint16_t)cmd->device->lun;
1da177e4
LT		 1313 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1314 mcp->in_mb = MBX_0;
b93480e3 1315 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1316 mcp->flags = 0;
7b867cf7 1317 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1318
1319 if (rval != QLA_SUCCESS) {
7c3df132 1320 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
1da177e4 1321 } else {
5f28d2d7
SK		 1322 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
1323 "Done %s.\n", __func__);
1da177e4
LT		 1324 }
1325
1326 return rval;
1327}
1328
1da177e4 1329int
9cb78c16 1330qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
1da177e4 1331{
523ec773 1332 int rval, rval2;
1da177e4
LT		 1333 mbx_cmd_t mc;
1334 mbx_cmd_t *mcp = &mc;
7b867cf7 1335 scsi_qla_host_t *vha;
73208dfd
AC		 1336 struct req_que *req;
1337 struct rsp_que *rsp;
1da177e4 1338
523ec773 1339 l = l;
7b867cf7 1340 vha = fcport->vha;
7c3df132 1341
5f28d2d7
SK		 1342 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1343 "Entered %s.\n", __func__);
7c3df132 1344
7e2b895b
GM		 1345 req = vha->hw->req_q_map[0];
1346 rsp = req->rsp;
1da177e4 1347 mcp->mb[0] = MBC_ABORT_TARGET;
523ec773 1348 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
7b867cf7 1349 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1350 mcp->mb[1] = fcport->loop_id;
1351 mcp->mb[10] = 0;
1352 mcp->out_mb |= MBX_10;
1353 } else {
1354 mcp->mb[1] = fcport->loop_id << 8;
1355 }
7b867cf7
AC		 1356 mcp->mb[2] = vha->hw->loop_reset_delay;
1357 mcp->mb[9] = vha->vp_idx;
1da177e4
LT		 1358
1359 mcp->in_mb = MBX_0;
b93480e3 1360 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1361 mcp->flags = 0;
7b867cf7 1362 rval = qla2x00_mailbox_command(vha, mcp);
523ec773 1363 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 1364 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
1365 "Failed=%x.\n", rval);
523ec773
AV		 1366 }
1367
1368 /* Issue marker IOCB. */
73208dfd
AC		 1369 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
1370 MK_SYNC_ID);
523ec773 1371 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1372 ql_dbg(ql_dbg_mbx, vha, 0x1040,
1373 "Failed to issue marker IOCB (%x).\n", rval2);
523ec773 1374 } else {
5f28d2d7
SK		 1375 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
1376 "Done %s.\n", __func__);
523ec773
AV		 1377 }
1378
1379 return rval;
1380}
1381
1382int
9cb78c16 1383qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773
AV		 1384{
1385 int rval, rval2;
1386 mbx_cmd_t mc;
1387 mbx_cmd_t *mcp = &mc;
7b867cf7 1388 scsi_qla_host_t *vha;
73208dfd
AC		 1389 struct req_que *req;
1390 struct rsp_que *rsp;
523ec773 1391
7b867cf7 1392 vha = fcport->vha;
7c3df132 1393
5f28d2d7
SK		 1394 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1395 "Entered %s.\n", __func__);
7c3df132 1396
7e2b895b
GM		 1397 req = vha->hw->req_q_map[0];
1398 rsp = req->rsp;
523ec773
AV		 1399 mcp->mb[0] = MBC_LUN_RESET;
1400 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 1401 if (HAS_EXTENDED_IDS(vha->hw))
523ec773
AV		 1402 mcp->mb[1] = fcport->loop_id;
1403 else
1404 mcp->mb[1] = fcport->loop_id << 8;
9cb78c16 1405 mcp->mb[2] = (u32)l;
523ec773 1406 mcp->mb[3] = 0;
7b867cf7 1407 mcp->mb[9] = vha->vp_idx;
1da177e4 1408
523ec773 1409 mcp->in_mb = MBX_0;
b93480e3 1410 mcp->tov = MBX_TOV_SECONDS;
523ec773 1411 mcp->flags = 0;
7b867cf7 1412 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1413 if (rval != QLA_SUCCESS) {
7c3df132 1414 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
523ec773
AV		 1415 }
1416
1417 /* Issue marker IOCB. */
73208dfd
AC		 1418 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
1419 MK_SYNC_ID_LUN);
523ec773 1420 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 1421 ql_dbg(ql_dbg_mbx, vha, 0x1044,
1422 "Failed to issue marker IOCB (%x).\n", rval2);
1da177e4 1423 } else {
5f28d2d7
SK		 1424 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
1425 "Done %s.\n", __func__);
1da177e4
LT		 1426 }
1427
1428 return rval;
1429}
1da177e4 1430
1da177e4
LT		 1431/*
1432 * qla2x00_get_adapter_id
1433 * Get adapter ID and topology.
1434 *
1435 * Input:
1436 * ha = adapter block pointer.
1437 * id = pointer for loop ID.
1438 * al_pa = pointer for AL_PA.
1439 * area = pointer for area.
1440 * domain = pointer for domain.
1441 * top = pointer for topology.
1442 * TARGET_QUEUE_LOCK must be released.
1443 * ADAPTER_STATE_LOCK must be released.
1444 *
1445 * Returns:
1446 * qla2x00 local function return status code.
1447 *
1448 * Context:
1449 * Kernel context.
1450 */
1451int
7b867cf7 1452qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
2c3dfe3f 1453 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1da177e4
LT		 1454{
1455 int rval;
1456 mbx_cmd_t mc;
1457 mbx_cmd_t *mcp = &mc;
1458
5f28d2d7
SK		 1459 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
1460 "Entered %s.\n", __func__);
1da177e4
LT		 1461
1462 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
7b867cf7 1463 mcp->mb[9] = vha->vp_idx;
eb66dc60 1464 mcp->out_mb = MBX_9|MBX_0;
2c3dfe3f 1465 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6246b8a1 1466 if (IS_CNA_CAPABLE(vha->hw))
bad7001c 1467 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
7c9c4766
JC		 1468 if (IS_FWI2_CAPABLE(vha->hw))
1469 mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
969a6199
SC		 1470 if (IS_QLA27XX(vha->hw))
1471 mcp->in_mb |= MBX_15;
b93480e3 1472 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1473 mcp->flags = 0;
7b867cf7 1474 rval = qla2x00_mailbox_command(vha, mcp);
33135aa2
RA		 1475 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1476 rval = QLA_COMMAND_ERROR;
42e421b1
AV		 1477 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1478 rval = QLA_INVALID_COMMAND;
1da177e4
LT		 1479
1480 /* Return data. */
1481 *id = mcp->mb[1];
1482 *al_pa = LSB(mcp->mb[2]);
1483 *area = MSB(mcp->mb[2]);
1484 *domain = LSB(mcp->mb[3]);
1485 *top = mcp->mb[6];
2c3dfe3f 1486 *sw_cap = mcp->mb[7];
1da177e4
LT		 1487
1488 if (rval != QLA_SUCCESS) {
1489 /*EMPTY*/
7c3df132 1490 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1da177e4 1491 } else {
5f28d2d7
SK		 1492 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
1493 "Done %s.\n", __func__);
bad7001c 1494
6246b8a1 1495 if (IS_CNA_CAPABLE(vha->hw)) {
bad7001c
AV		 1496 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1497 vha->fcoe_fcf_idx = mcp->mb[10];
1498 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1499 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1500 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1501 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1502 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1503 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1504 }
7c9c4766 1505 /* If FA-WWN supported */
d6b9b42b
SK		 1506 if (IS_FAWWN_CAPABLE(vha->hw)) {
1507 if (mcp->mb[7] & BIT_14) {
1508 vha->port_name[0] = MSB(mcp->mb[16]);
1509 vha->port_name[1] = LSB(mcp->mb[16]);
1510 vha->port_name[2] = MSB(mcp->mb[17]);
1511 vha->port_name[3] = LSB(mcp->mb[17]);
1512 vha->port_name[4] = MSB(mcp->mb[18]);
1513 vha->port_name[5] = LSB(mcp->mb[18]);
1514 vha->port_name[6] = MSB(mcp->mb[19]);
1515 vha->port_name[7] = LSB(mcp->mb[19]);
1516 fc_host_port_name(vha->host) =
1517 wwn_to_u64(vha->port_name);
1518 ql_dbg(ql_dbg_mbx, vha, 0x10ca,
1519 "FA-WWN acquired %016llx\n",
1520 wwn_to_u64(vha->port_name));
1521 }
7c9c4766 1522 }
969a6199
SC		 1523
1524 if (IS_QLA27XX(vha->hw))
1525 vha->bbcr = mcp->mb[15];
1da177e4
LT		 1526 }
1527
1528 return rval;
1529}
1530
1531/*
1532 * qla2x00_get_retry_cnt
1533 * Get current firmware login retry count and delay.
1534 *
1535 * Input:
1536 * ha = adapter block pointer.
1537 * retry_cnt = pointer to login retry count.
1538 * tov = pointer to login timeout value.
1539 *
1540 * Returns:
1541 * qla2x00 local function return status code.
1542 *
1543 * Context:
1544 * Kernel context.
1545 */
1546int
7b867cf7 1547qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1da177e4
LT		 1548 uint16_t *r_a_tov)
1549{
1550 int rval;
1551 uint16_t ratov;
1552 mbx_cmd_t mc;
1553 mbx_cmd_t *mcp = &mc;
1554
5f28d2d7
SK		 1555 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
1556 "Entered %s.\n", __func__);
1da177e4
LT		 1557
1558 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1559 mcp->out_mb = MBX_0;
1560 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1561 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1562 mcp->flags = 0;
7b867cf7 1563 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1564
1565 if (rval != QLA_SUCCESS) {
1566 /*EMPTY*/
7c3df132
SK		 1567 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1568 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1da177e4
LT		 1569 } else {
1570 /* Convert returned data and check our values. */
1571 *r_a_tov = mcp->mb[3] / 2;
1572 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1573 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1574 /* Update to the larger values */
1575 *retry_cnt = (uint8_t)mcp->mb[1];
1576 *tov = ratov;
1577 }
1578
5f28d2d7 1579 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
7c3df132 1580 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1da177e4
LT		 1581 }
1582
1583 return rval;
1584}
1585
1586/*
1587 * qla2x00_init_firmware
1588 * Initialize adapter firmware.
1589 *
1590 * Input:
1591 * ha = adapter block pointer.
1592 * dptr = Initialization control block pointer.
1593 * size = size of initialization control block.
1594 * TARGET_QUEUE_LOCK must be released.
1595 * ADAPTER_STATE_LOCK must be released.
1596 *
1597 * Returns:
1598 * qla2x00 local function return status code.
1599 *
1600 * Context:
1601 * Kernel context.
1602 */
1603int
7b867cf7 1604qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1da177e4
LT		 1605{
1606 int rval;
1607 mbx_cmd_t mc;
1608 mbx_cmd_t *mcp = &mc;
7b867cf7 1609 struct qla_hw_data *ha = vha->hw;
1da177e4 1610
5f28d2d7
SK		 1611 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
1612 "Entered %s.\n", __func__);
1da177e4 1613
7ec0effd 1614 if (IS_P3P_TYPE(ha) && ql2xdbwr)
8dfa4b5a 1615 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
a9083016
GM		 1616 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1617
e6e074f1 1618 if (ha->flags.npiv_supported)
2c3dfe3f
SJ		 1619 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1620 else
1621 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1622
b64b0e8f 1623 mcp->mb[1] = 0;
1da177e4
LT		 1624 mcp->mb[2] = MSW(ha->init_cb_dma);
1625 mcp->mb[3] = LSW(ha->init_cb_dma);
1da177e4
LT		 1626 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1627 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
b64b0e8f 1628 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4ef21bd4 1629 if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
b64b0e8f
AV		 1630 mcp->mb[1] = BIT_0;
1631 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1632 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1633 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1634 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1635 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1636 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1637 }
6246b8a1
GM		 1638 /* 1 and 2 should normally be captured. */
1639 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 1640 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 1641 /* mb3 is additional info about the installed SFP. */
1642 mcp->in_mb |= MBX_3;
1da177e4
LT		 1643 mcp->buf_size = size;
1644 mcp->flags = MBX_DMA_OUT;
b93480e3 1645 mcp->tov = MBX_TOV_SECONDS;
7b867cf7 1646 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1647
1648 if (rval != QLA_SUCCESS) {
1649 /*EMPTY*/
7c3df132 1650 ql_dbg(ql_dbg_mbx, vha, 0x104d,
6246b8a1
GM		 1651 "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
1652 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
1da177e4
LT		 1653 } else {
1654 /*EMPTY*/
5f28d2d7
SK		 1655 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
1656 "Done %s.\n", __func__);
1da177e4
LT		 1657 }
1658
1659 return rval;
1660}
1661
2d70c103 1662
1da177e4
LT		 1663/*
1664 * qla2x00_get_port_database
1665 * Issue normal/enhanced get port database mailbox command
1666 * and copy device name as necessary.
1667 *
1668 * Input:
1669 * ha = adapter state pointer.
1670 * dev = structure pointer.
1671 * opt = enhanced cmd option byte.
1672 *
1673 * Returns:
1674 * qla2x00 local function return status code.
1675 *
1676 * Context:
1677 * Kernel context.
1678 */
1679int
7b867cf7 1680qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1da177e4
LT		 1681{
1682 int rval;
1683 mbx_cmd_t mc;
1684 mbx_cmd_t *mcp = &mc;
1685 port_database_t *pd;
1c7c6357 1686 struct port_database_24xx *pd24;
1da177e4 1687 dma_addr_t pd_dma;
7b867cf7 1688 struct qla_hw_data *ha = vha->hw;
1da177e4 1689
5f28d2d7
SK		 1690 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
1691 "Entered %s.\n", __func__);
1da177e4 1692
1c7c6357
AV		 1693 pd24 = NULL;
1694 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1da177e4 1695 if (pd == NULL) {
7c3df132
SK		 1696 ql_log(ql_log_warn, vha, 0x1050,
1697 "Failed to allocate port database structure.\n");
1da177e4
LT		 1698 return QLA_MEMORY_ALLOC_FAILED;
1699 }
1c7c6357 1700 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1da177e4 1701
1c7c6357 1702 mcp->mb[0] = MBC_GET_PORT_DATABASE;
e428924c 1703 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1da177e4 1704 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1da177e4
LT		 1705 mcp->mb[2] = MSW(pd_dma);
1706 mcp->mb[3] = LSW(pd_dma);
1707 mcp->mb[6] = MSW(MSD(pd_dma));
1708 mcp->mb[7] = LSW(MSD(pd_dma));
7b867cf7 1709 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1710 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1da177e4 1711 mcp->in_mb = MBX_0;
e428924c 1712 if (IS_FWI2_CAPABLE(ha)) {
1c7c6357
AV		 1713 mcp->mb[1] = fcport->loop_id;
1714 mcp->mb[10] = opt;
1715 mcp->out_mb |= MBX_10|MBX_1;
1716 mcp->in_mb |= MBX_1;
1717 } else if (HAS_EXTENDED_IDS(ha)) {
1718 mcp->mb[1] = fcport->loop_id;
1719 mcp->mb[10] = opt;
1720 mcp->out_mb |= MBX_10|MBX_1;
1721 } else {
1722 mcp->mb[1] = fcport->loop_id << 8 | opt;
1723 mcp->out_mb |= MBX_1;
1724 }
e428924c
AV		 1725 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1726 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1da177e4
LT		 1727 mcp->flags = MBX_DMA_IN;
1728 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 1729 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1730 if (rval != QLA_SUCCESS)
1731 goto gpd_error_out;
1732
e428924c 1733 if (IS_FWI2_CAPABLE(ha)) {
0eba25df 1734 uint64_t zero = 0;
1c7c6357
AV		 1735 pd24 = (struct port_database_24xx *) pd;
1736
1737 /* Check for logged in state. */
1738 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1739 pd24->last_login_state != PDS_PRLI_COMPLETE) {
7c3df132
SK		 1740 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1741 "Unable to verify login-state (%x/%x) for "
1742 "loop_id %x.\n", pd24->current_login_state,
1743 pd24->last_login_state, fcport->loop_id);
1c7c6357
AV		 1744 rval = QLA_FUNCTION_FAILED;
1745 goto gpd_error_out;
1746 }
1da177e4 1747
0eba25df
AE		 1748 if (fcport->loop_id == FC_NO_LOOP_ID ||
1749 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1750 memcmp(fcport->port_name, pd24->port_name, 8))) {
1751 /* We lost the device mid way. */
1752 rval = QLA_NOT_LOGGED_IN;
1753 goto gpd_error_out;
1754 }
1755
1c7c6357
AV		 1756 /* Names are little-endian. */
1757 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1758 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1759
1760 /* Get port_id of device. */
1761 fcport->d_id.b.domain = pd24->port_id[0];
1762 fcport->d_id.b.area = pd24->port_id[1];
1763 fcport->d_id.b.al_pa = pd24->port_id[2];
1764 fcport->d_id.b.rsvd_1 = 0;
1765
1766 /* If not target must be initiator or unknown type. */
1767 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1768 fcport->port_type = FCT_INITIATOR;
1769 else
1770 fcport->port_type = FCT_TARGET;
2d70c103
NB		 1771
1772 /* Passback COS information. */
1773 fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
1774 FC_COS_CLASS2 : FC_COS_CLASS3;
1775
1776 if (pd24->prli_svc_param_word_3[0] & BIT_7)
1777 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
1c7c6357 1778 } else {
0eba25df
AE		 1779 uint64_t zero = 0;
1780
1c7c6357
AV		 1781 /* Check for logged in state. */
1782 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1783 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
7c3df132
SK		 1784 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1785 "Unable to verify login-state (%x/%x) - "
1786 "portid=%02x%02x%02x.\n", pd->master_state,
1787 pd->slave_state, fcport->d_id.b.domain,
1788 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1c7c6357
AV		 1789 rval = QLA_FUNCTION_FAILED;
1790 goto gpd_error_out;
1791 }
1da177e4 1792
0eba25df
AE		 1793 if (fcport->loop_id == FC_NO_LOOP_ID ||
1794 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
1795 memcmp(fcport->port_name, pd->port_name, 8))) {
1796 /* We lost the device mid way. */
1797 rval = QLA_NOT_LOGGED_IN;
1798 goto gpd_error_out;
1799 }
1800
1c7c6357
AV		 1801 /* Names are little-endian. */
1802 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1803 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1804
1805 /* Get port_id of device. */
1806 fcport->d_id.b.domain = pd->port_id[0];
1807 fcport->d_id.b.area = pd->port_id[3];
1808 fcport->d_id.b.al_pa = pd->port_id[2];
1809 fcport->d_id.b.rsvd_1 = 0;
1810
1c7c6357
AV		 1811 /* If not target must be initiator or unknown type. */
1812 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1813 fcport->port_type = FCT_INITIATOR;
1814 else
1815 fcport->port_type = FCT_TARGET;
ad3e0eda
AV		 1816
1817 /* Passback COS information. */
1818 fcport->supported_classes = (pd->options & BIT_4) ?
1819 FC_COS_CLASS2: FC_COS_CLASS3;
1c7c6357 1820 }
1da177e4
LT		 1821
1822gpd_error_out:
1823 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1824
1825 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1826 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1827 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1828 mcp->mb[0], mcp->mb[1]);
1da177e4 1829 } else {
5f28d2d7
SK		 1830 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1831 "Done %s.\n", __func__);
1da177e4
LT		 1832 }
1833
1834 return rval;
1835}
1836
1837/*
1838 * qla2x00_get_firmware_state
1839 * Get adapter firmware state.
1840 *
1841 * Input:
1842 * ha = adapter block pointer.
1843 * dptr = pointer for firmware state.
1844 * TARGET_QUEUE_LOCK must be released.
1845 * ADAPTER_STATE_LOCK must be released.
1846 *
1847 * Returns:
1848 * qla2x00 local function return status code.
1849 *
1850 * Context:
1851 * Kernel context.
1852 */
1853int
7b867cf7 1854qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1da177e4
LT		 1855{
1856 int rval;
1857 mbx_cmd_t mc;
1858 mbx_cmd_t *mcp = &mc;
1859
5f28d2d7
SK		 1860 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
1861 "Entered %s.\n", __func__);
1da177e4
LT		 1862
1863 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1864 mcp->out_mb = MBX_0;
9d2683c0 1865 if (IS_FWI2_CAPABLE(vha->hw))
b5a340dd 1866 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
9d2683c0
AV		 1867 else
1868 mcp->in_mb = MBX_1|MBX_0;
b93480e3 1869 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1870 mcp->flags = 0;
7b867cf7 1871 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4 1872
4d4df193
HK		 1873 /* Return firmware states. */
1874 states[0] = mcp->mb[1];
9d2683c0
AV		 1875 if (IS_FWI2_CAPABLE(vha->hw)) {
1876 states[1] = mcp->mb[2];
ec891462 1877 states[2] = mcp->mb[3]; /* SFP info */
9d2683c0
AV		 1878 states[3] = mcp->mb[4];
1879 states[4] = mcp->mb[5];
b5a340dd 1880 states[5] = mcp->mb[6]; /* DPORT status */
9d2683c0 1881 }
1da177e4
LT		 1882
1883 if (rval != QLA_SUCCESS) {
1884 /*EMPTY*/
7c3df132 1885 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1da177e4
LT		 1886 } else {
1887 /*EMPTY*/
5f28d2d7
SK		 1888 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
1889 "Done %s.\n", __func__);
1da177e4
LT		 1890 }
1891
1892 return rval;
1893}
1894
1895/*
1896 * qla2x00_get_port_name
1897 * Issue get port name mailbox command.
1898 * Returned name is in big endian format.
1899 *
1900 * Input:
1901 * ha = adapter block pointer.
1902 * loop_id = loop ID of device.
1903 * name = pointer for name.
1904 * TARGET_QUEUE_LOCK must be released.
1905 * ADAPTER_STATE_LOCK must be released.
1906 *
1907 * Returns:
1908 * qla2x00 local function return status code.
1909 *
1910 * Context:
1911 * Kernel context.
1912 */
1913int
7b867cf7 1914qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1da177e4
LT		 1915 uint8_t opt)
1916{
1917 int rval;
1918 mbx_cmd_t mc;
1919 mbx_cmd_t *mcp = &mc;
1920
5f28d2d7
SK		 1921 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
1922 "Entered %s.\n", __func__);
1da177e4
LT		 1923
1924 mcp->mb[0] = MBC_GET_PORT_NAME;
7b867cf7 1925 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 1926 mcp->out_mb = MBX_9|MBX_1|MBX_0;
7b867cf7 1927 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 1928 mcp->mb[1] = loop_id;
1929 mcp->mb[10] = opt;
1930 mcp->out_mb |= MBX_10;
1931 } else {
1932 mcp->mb[1] = loop_id << 8 | opt;
1933 }
1934
1935 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 1936 mcp->tov = MBX_TOV_SECONDS;
1da177e4 1937 mcp->flags = 0;
7b867cf7 1938 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 1939
1940 if (rval != QLA_SUCCESS) {
1941 /*EMPTY*/
7c3df132 1942 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1da177e4
LT		 1943 } else {
1944 if (name != NULL) {
1945 /* This function returns name in big endian. */
1196ae02
RL		 1946 name[0] = MSB(mcp->mb[2]);
1947 name[1] = LSB(mcp->mb[2]);
1948 name[2] = MSB(mcp->mb[3]);
1949 name[3] = LSB(mcp->mb[3]);
1950 name[4] = MSB(mcp->mb[6]);
1951 name[5] = LSB(mcp->mb[6]);
1952 name[6] = MSB(mcp->mb[7]);
1953 name[7] = LSB(mcp->mb[7]);
1da177e4
LT		 1954 }
1955
5f28d2d7
SK		 1956 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
1957 "Done %s.\n", __func__);
1da177e4
LT		 1958 }
1959
1960 return rval;
1961}
1962
61e1b269
JC		 1963/*
1964 * qla24xx_link_initialization
1965 * Issue link initialization mailbox command.
1966 *
1967 * Input:
1968 * ha = adapter block pointer.
1969 * TARGET_QUEUE_LOCK must be released.
1970 * ADAPTER_STATE_LOCK must be released.
1971 *
1972 * Returns:
1973 * qla2x00 local function return status code.
1974 *
1975 * Context:
1976 * Kernel context.
1977 */
1978int
1979qla24xx_link_initialize(scsi_qla_host_t *vha)
1980{
1981 int rval;
1982 mbx_cmd_t mc;
1983 mbx_cmd_t *mcp = &mc;
1984
1985 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
1986 "Entered %s.\n", __func__);
1987
1988 if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
1989 return QLA_FUNCTION_FAILED;
1990
1991 mcp->mb[0] = MBC_LINK_INITIALIZATION;
5a5c27b6
JC		 1992 mcp->mb[1] = BIT_4;
1993 if (vha->hw->operating_mode == LOOP)
1994 mcp->mb[1] |= BIT_6;
1995 else
1996 mcp->mb[1] |= BIT_5;
61e1b269
JC		 1997 mcp->mb[2] = 0;
1998 mcp->mb[3] = 0;
1999 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2000 mcp->in_mb = MBX_0;
2001 mcp->tov = MBX_TOV_SECONDS;
2002 mcp->flags = 0;
2003 rval = qla2x00_mailbox_command(vha, mcp);
2004
2005 if (rval != QLA_SUCCESS) {
2006 ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
2007 } else {
2008 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
2009 "Done %s.\n", __func__);
2010 }
2011
2012 return rval;
2013}
2014
1da177e4
LT		 2015/*
2016 * qla2x00_lip_reset
2017 * Issue LIP reset mailbox command.
2018 *
2019 * Input:
2020 * ha = adapter block pointer.
2021 * TARGET_QUEUE_LOCK must be released.
2022 * ADAPTER_STATE_LOCK must be released.
2023 *
2024 * Returns:
2025 * qla2x00 local function return status code.
2026 *
2027 * Context:
2028 * Kernel context.
2029 */
2030int
7b867cf7 2031qla2x00_lip_reset(scsi_qla_host_t *vha)
1da177e4
LT		 2032{
2033 int rval;
2034 mbx_cmd_t mc;
2035 mbx_cmd_t *mcp = &mc;
2036
5f28d2d7
SK		 2037 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
2038 "Entered %s.\n", __func__);
1da177e4 2039
6246b8a1 2040 if (IS_CNA_CAPABLE(vha->hw)) {
3a03eb79
AV		 2041 /* Logout across all FCFs. */
2042 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2043 mcp->mb[1] = BIT_1;
2044 mcp->mb[2] = 0;
2045 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2046 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357 2047 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
0c8c39af
AV		 2048 mcp->mb[1] = BIT_6;
2049 mcp->mb[2] = 0;
7b867cf7 2050 mcp->mb[3] = vha->hw->loop_reset_delay;
1c7c6357 2051 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1da177e4 2052 } else {
1c7c6357
AV		 2053 mcp->mb[0] = MBC_LIP_RESET;
2054 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
7b867cf7 2055 if (HAS_EXTENDED_IDS(vha->hw)) {
1c7c6357
AV		 2056 mcp->mb[1] = 0x00ff;
2057 mcp->mb[10] = 0;
2058 mcp->out_mb |= MBX_10;
2059 } else {
2060 mcp->mb[1] = 0xff00;
2061 }
7b867cf7 2062 mcp->mb[2] = vha->hw->loop_reset_delay;
1c7c6357 2063 mcp->mb[3] = 0;
1da177e4 2064 }
1da177e4 2065 mcp->in_mb = MBX_0;
b93480e3 2066 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2067 mcp->flags = 0;
7b867cf7 2068 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2069
2070 if (rval != QLA_SUCCESS) {
2071 /*EMPTY*/
7c3df132 2072 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1da177e4
LT		 2073 } else {
2074 /*EMPTY*/
5f28d2d7
SK		 2075 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
2076 "Done %s.\n", __func__);
1da177e4
LT		 2077 }
2078
2079 return rval;
2080}
2081
2082/*
2083 * qla2x00_send_sns
2084 * Send SNS command.
2085 *
2086 * Input:
2087 * ha = adapter block pointer.
2088 * sns = pointer for command.
2089 * cmd_size = command size.
2090 * buf_size = response/command size.
2091 * TARGET_QUEUE_LOCK must be released.
2092 * ADAPTER_STATE_LOCK must be released.
2093 *
2094 * Returns:
2095 * qla2x00 local function return status code.
2096 *
2097 * Context:
2098 * Kernel context.
2099 */
2100int
7b867cf7 2101qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1da177e4
LT		 2102 uint16_t cmd_size, size_t buf_size)
2103{
2104 int rval;
2105 mbx_cmd_t mc;
2106 mbx_cmd_t *mcp = &mc;
2107
5f28d2d7
SK		 2108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
2109 "Entered %s.\n", __func__);
1da177e4 2110
5f28d2d7 2111 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
7c3df132
SK		 2112 "Retry cnt=%d ratov=%d total tov=%d.\n",
2113 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1da177e4
LT		 2114
2115 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
2116 mcp->mb[1] = cmd_size;
2117 mcp->mb[2] = MSW(sns_phys_address);
2118 mcp->mb[3] = LSW(sns_phys_address);
2119 mcp->mb[6] = MSW(MSD(sns_phys_address));
2120 mcp->mb[7] = LSW(MSD(sns_phys_address));
2121 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2122 mcp->in_mb = MBX_0|MBX_1;
2123 mcp->buf_size = buf_size;
2124 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
7b867cf7
AC		 2125 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
2126 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2127
2128 if (rval != QLA_SUCCESS) {
2129 /*EMPTY*/
7c3df132
SK		 2130 ql_dbg(ql_dbg_mbx, vha, 0x105f,
2131 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2132 rval, mcp->mb[0], mcp->mb[1]);
1da177e4
LT		 2133 } else {
2134 /*EMPTY*/
5f28d2d7
SK		 2135 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
2136 "Done %s.\n", __func__);
1da177e4
LT		 2137 }
2138
2139 return rval;
2140}
2141
1c7c6357 2142int
7b867cf7 2143qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2144 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2145{
2146 int rval;
2147
2148 struct logio_entry_24xx *lg;
2149 dma_addr_t lg_dma;
2150 uint32_t iop[2];
7b867cf7 2151 struct qla_hw_data *ha = vha->hw;
2afa19a9 2152 struct req_que *req;
1c7c6357 2153
5f28d2d7
SK		 2154 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
2155 "Entered %s.\n", __func__);
1c7c6357 2156
d7459527
MH		 2157 if (vha->vp_idx && vha->qpair)
2158 req = vha->qpair->req;
68ca949c 2159 else
d7459527 2160 req = ha->req_q_map[0];
2afa19a9 2161
1c7c6357
AV		 2162 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2163 if (lg == NULL) {
7c3df132
SK		 2164 ql_log(ql_log_warn, vha, 0x1062,
2165 "Failed to allocate login IOCB.\n");
1c7c6357
AV		 2166 return QLA_MEMORY_ALLOC_FAILED;
2167 }
2168 memset(lg, 0, sizeof(struct logio_entry_24xx));
2169
2170 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2171 lg->entry_count = 1;
2afa19a9 2172 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357 2173 lg->nport_handle = cpu_to_le16(loop_id);
ad950360 2174 lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
1c7c6357 2175 if (opt & BIT_0)
ad950360 2176 lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
8baa51a6 2177 if (opt & BIT_1)
ad950360 2178 lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
1c7c6357
AV		 2179 lg->port_id[0] = al_pa;
2180 lg->port_id[1] = area;
2181 lg->port_id[2] = domain;
7b867cf7 2182 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2183 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2184 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2185 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2186 ql_dbg(ql_dbg_mbx, vha, 0x1063,
2187 "Failed to issue login IOCB (%x).\n", rval);
1c7c6357 2188 } else if (lg->entry_status != 0) {
7c3df132
SK		 2189 ql_dbg(ql_dbg_mbx, vha, 0x1064,
2190 "Failed to complete IOCB -- error status (%x).\n",
2191 lg->entry_status);
1c7c6357 2192 rval = QLA_FUNCTION_FAILED;
ad950360 2193 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
1c7c6357
AV		 2194 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2195 iop[1] = le32_to_cpu(lg->io_parameter[1]);
2196
7c3df132
SK		 2197 ql_dbg(ql_dbg_mbx, vha, 0x1065,
2198 "Failed to complete IOCB -- completion status (%x) "
2199 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
2200 iop[0], iop[1]);
1c7c6357
AV		 2201
2202 switch (iop[0]) {
2203 case LSC_SCODE_PORTID_USED:
2204 mb[0] = MBS_PORT_ID_USED;
2205 mb[1] = LSW(iop[1]);
2206 break;
2207 case LSC_SCODE_NPORT_USED:
2208 mb[0] = MBS_LOOP_ID_USED;
2209 break;
2210 case LSC_SCODE_NOLINK:
2211 case LSC_SCODE_NOIOCB:
2212 case LSC_SCODE_NOXCB:
2213 case LSC_SCODE_CMD_FAILED:
2214 case LSC_SCODE_NOFABRIC:
2215 case LSC_SCODE_FW_NOT_READY:
2216 case LSC_SCODE_NOT_LOGGED_IN:
2217 case LSC_SCODE_NOPCB:
2218 case LSC_SCODE_ELS_REJECT:
2219 case LSC_SCODE_CMD_PARAM_ERR:
2220 case LSC_SCODE_NONPORT:
2221 case LSC_SCODE_LOGGED_IN:
2222 case LSC_SCODE_NOFLOGI_ACC:
2223 default:
2224 mb[0] = MBS_COMMAND_ERROR;
2225 break;
2226 }
2227 } else {
5f28d2d7
SK		 2228 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
2229 "Done %s.\n", __func__);
1c7c6357
AV		 2230
2231 iop[0] = le32_to_cpu(lg->io_parameter[0]);
2232
2233 mb[0] = MBS_COMMAND_COMPLETE;
2234 mb[1] = 0;
2235 if (iop[0] & BIT_4) {
2236 if (iop[0] & BIT_8)
2237 mb[1] |= BIT_1;
2238 } else
2239 mb[1] = BIT_0;
ad3e0eda
AV		 2240
2241 /* Passback COS information. */
2242 mb[10] = 0;
2243 if (lg->io_parameter[7] || lg->io_parameter[8])
2244 mb[10] |= BIT_0; /* Class 2. */
2245 if (lg->io_parameter[9] || lg->io_parameter[10])
2246 mb[10] |= BIT_1; /* Class 3. */
ad950360 2247 if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
2d70c103
NB		 2248 mb[10] |= BIT_7; /* Confirmed Completion
2249 * Allowed
2250 */
1c7c6357
AV		 2251 }
2252
2253 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2254
2255 return rval;
2256}
2257
1da177e4
LT		 2258/*
2259 * qla2x00_login_fabric
2260 * Issue login fabric port mailbox command.
2261 *
2262 * Input:
2263 * ha = adapter block pointer.
2264 * loop_id = device loop ID.
2265 * domain = device domain.
2266 * area = device area.
2267 * al_pa = device AL_PA.
2268 * status = pointer for return status.
2269 * opt = command options.
2270 * TARGET_QUEUE_LOCK must be released.
2271 * ADAPTER_STATE_LOCK must be released.
2272 *
2273 * Returns:
2274 * qla2x00 local function return status code.
2275 *
2276 * Context:
2277 * Kernel context.
2278 */
2279int
7b867cf7 2280qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1da177e4
LT		 2281 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
2282{
2283 int rval;
2284 mbx_cmd_t mc;
2285 mbx_cmd_t *mcp = &mc;
7b867cf7 2286 struct qla_hw_data *ha = vha->hw;
1da177e4 2287
5f28d2d7
SK		 2288 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
2289 "Entered %s.\n", __func__);
1da177e4
LT		 2290
2291 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
2292 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2293 if (HAS_EXTENDED_IDS(ha)) {
2294 mcp->mb[1] = loop_id;
2295 mcp->mb[10] = opt;
2296 mcp->out_mb |= MBX_10;
2297 } else {
2298 mcp->mb[1] = (loop_id << 8) | opt;
2299 }
2300 mcp->mb[2] = domain;
2301 mcp->mb[3] = area << 8 | al_pa;
2302
2303 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
2304 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2305 mcp->flags = 0;
7b867cf7 2306 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2307
2308 /* Return mailbox statuses. */
2309 if (mb != NULL) {
2310 mb[0] = mcp->mb[0];
2311 mb[1] = mcp->mb[1];
2312 mb[2] = mcp->mb[2];
2313 mb[6] = mcp->mb[6];
2314 mb[7] = mcp->mb[7];
ad3e0eda
AV		 2315 /* COS retrieved from Get-Port-Database mailbox command. */
2316 mb[10] = 0;
1da177e4
LT		 2317 }
2318
2319 if (rval != QLA_SUCCESS) {
2320 /* RLU tmp code: need to change main mailbox_command function to
2321 * return ok even when the mailbox completion value is not
2322 * SUCCESS. The caller needs to be responsible to interpret
2323 * the return values of this mailbox command if we're not
2324 * to change too much of the existing code.
2325 */
2326 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
2327 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
2328 mcp->mb[0] == 0x4006)
2329 rval = QLA_SUCCESS;
2330
2331 /*EMPTY*/
7c3df132
SK		 2332 ql_dbg(ql_dbg_mbx, vha, 0x1068,
2333 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
2334 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1da177e4
LT		 2335 } else {
2336 /*EMPTY*/
5f28d2d7
SK		 2337 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
2338 "Done %s.\n", __func__);
1da177e4
LT		 2339 }
2340
2341 return rval;
2342}
2343
2344/*
2345 * qla2x00_login_local_device
2346 * Issue login loop port mailbox command.
fa2a1ce5 2347 *
1da177e4
LT		 2348 * Input:
2349 * ha = adapter block pointer.
2350 * loop_id = device loop ID.
2351 * opt = command options.
fa2a1ce5 2352 *
1da177e4
LT		 2353 * Returns:
2354 * Return status code.
fa2a1ce5 2355 *
1da177e4
LT		 2356 * Context:
2357 * Kernel context.
fa2a1ce5 2358 *
1da177e4
LT		 2359 */
2360int
7b867cf7 2361qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 2362 uint16_t *mb_ret, uint8_t opt)
2363{
2364 int rval;
2365 mbx_cmd_t mc;
2366 mbx_cmd_t *mcp = &mc;
7b867cf7 2367 struct qla_hw_data *ha = vha->hw;
1da177e4 2368
5f28d2d7
SK		 2369 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
2370 "Entered %s.\n", __func__);
7c3df132 2371
e428924c 2372 if (IS_FWI2_CAPABLE(ha))
7b867cf7 2373 return qla24xx_login_fabric(vha, fcport->loop_id,
9a52a57c
AV		 2374 fcport->d_id.b.domain, fcport->d_id.b.area,
2375 fcport->d_id.b.al_pa, mb_ret, opt);
2376
1da177e4
LT		 2377 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
2378 if (HAS_EXTENDED_IDS(ha))
9a52a57c 2379 mcp->mb[1] = fcport->loop_id;
1da177e4 2380 else
9a52a57c 2381 mcp->mb[1] = fcport->loop_id << 8;
1da177e4
LT		 2382 mcp->mb[2] = opt;
2383 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2384 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
2385 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2386 mcp->flags = 0;
7b867cf7 2387 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2388
2389 /* Return mailbox statuses. */
2390 if (mb_ret != NULL) {
2391 mb_ret[0] = mcp->mb[0];
2392 mb_ret[1] = mcp->mb[1];
2393 mb_ret[6] = mcp->mb[6];
2394 mb_ret[7] = mcp->mb[7];
2395 }
2396
2397 if (rval != QLA_SUCCESS) {
2398 /* AV tmp code: need to change main mailbox_command function to
2399 * return ok even when the mailbox completion value is not
2400 * SUCCESS. The caller needs to be responsible to interpret
2401 * the return values of this mailbox command if we're not
2402 * to change too much of the existing code.
2403 */
2404 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
2405 rval = QLA_SUCCESS;
2406
7c3df132
SK		 2407 ql_dbg(ql_dbg_mbx, vha, 0x106b,
2408 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
2409 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1da177e4
LT		 2410 } else {
2411 /*EMPTY*/
5f28d2d7
SK		 2412 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
2413 "Done %s.\n", __func__);
1da177e4
LT		 2414 }
2415
2416 return (rval);
2417}
2418
1c7c6357 2419int
7b867cf7 2420qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357
AV		 2421 uint8_t area, uint8_t al_pa)
2422{
2423 int rval;
2424 struct logio_entry_24xx *lg;
2425 dma_addr_t lg_dma;
7b867cf7 2426 struct qla_hw_data *ha = vha->hw;
2afa19a9 2427 struct req_que *req;
1c7c6357 2428
5f28d2d7
SK		 2429 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
2430 "Entered %s.\n", __func__);
1c7c6357
AV		 2431
2432 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
2433 if (lg == NULL) {
7c3df132
SK		 2434 ql_log(ql_log_warn, vha, 0x106e,
2435 "Failed to allocate logout IOCB.\n");
1c7c6357
AV		 2436 return QLA_MEMORY_ALLOC_FAILED;
2437 }
2438 memset(lg, 0, sizeof(struct logio_entry_24xx));
2439
d7459527 2440 req = vha->req;
1c7c6357
AV		 2441 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2442 lg->entry_count = 1;
2afa19a9 2443 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1c7c6357
AV		 2444 lg->nport_handle = cpu_to_le16(loop_id);
2445 lg->control_flags =
ad950360 2446 cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
c8d6691b 2447 LCF_FREE_NPORT);
1c7c6357
AV		 2448 lg->port_id[0] = al_pa;
2449 lg->port_id[1] = area;
2450 lg->port_id[2] = domain;
7b867cf7 2451 lg->vp_index = vha->vp_idx;
7f45dd0b
AV		 2452 rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
2453 (ha->r_a_tov / 10 * 2) + 2);
1c7c6357 2454 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2455 ql_dbg(ql_dbg_mbx, vha, 0x106f,
2456 "Failed to issue logout IOCB (%x).\n", rval);
1c7c6357 2457 } else if (lg->entry_status != 0) {
7c3df132
SK		 2458 ql_dbg(ql_dbg_mbx, vha, 0x1070,
2459 "Failed to complete IOCB -- error status (%x).\n",
2460 lg->entry_status);
1c7c6357 2461 rval = QLA_FUNCTION_FAILED;
ad950360 2462 } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 2463 ql_dbg(ql_dbg_mbx, vha, 0x1071,
2464 "Failed to complete IOCB -- completion status (%x) "
2465 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1c7c6357 2466 le32_to_cpu(lg->io_parameter[0]),
7c3df132 2467 le32_to_cpu(lg->io_parameter[1]));
1c7c6357
AV		 2468 } else {
2469 /*EMPTY*/
5f28d2d7
SK		 2470 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
2471 "Done %s.\n", __func__);
1c7c6357
AV		 2472 }
2473
2474 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
2475
2476 return rval;
2477}
2478
1da177e4
LT		 2479/*
2480 * qla2x00_fabric_logout
2481 * Issue logout fabric port mailbox command.
2482 *
2483 * Input:
2484 * ha = adapter block pointer.
2485 * loop_id = device loop ID.
2486 * TARGET_QUEUE_LOCK must be released.
2487 * ADAPTER_STATE_LOCK must be released.
2488 *
2489 * Returns:
2490 * qla2x00 local function return status code.
2491 *
2492 * Context:
2493 * Kernel context.
2494 */
2495int
7b867cf7 2496qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1c7c6357 2497 uint8_t area, uint8_t al_pa)
1da177e4
LT		 2498{
2499 int rval;
2500 mbx_cmd_t mc;
2501 mbx_cmd_t *mcp = &mc;
2502
5f28d2d7
SK		 2503 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
2504 "Entered %s.\n", __func__);
1da177e4
LT		 2505
2506 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
2507 mcp->out_mb = MBX_1|MBX_0;
7b867cf7 2508 if (HAS_EXTENDED_IDS(vha->hw)) {
1da177e4
LT		 2509 mcp->mb[1] = loop_id;
2510 mcp->mb[10] = 0;
2511 mcp->out_mb |= MBX_10;
2512 } else {
2513 mcp->mb[1] = loop_id << 8;
2514 }
2515
2516 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2517 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2518 mcp->flags = 0;
7b867cf7 2519 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2520
2521 if (rval != QLA_SUCCESS) {
2522 /*EMPTY*/
7c3df132
SK		 2523 ql_dbg(ql_dbg_mbx, vha, 0x1074,
2524 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1da177e4
LT		 2525 } else {
2526 /*EMPTY*/
5f28d2d7
SK		 2527 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
2528 "Done %s.\n", __func__);
1da177e4
LT		 2529 }
2530
2531 return rval;
2532}
2533
2534/*
2535 * qla2x00_full_login_lip
2536 * Issue full login LIP mailbox command.
2537 *
2538 * Input:
2539 * ha = adapter block pointer.
2540 * TARGET_QUEUE_LOCK must be released.
2541 * ADAPTER_STATE_LOCK must be released.
2542 *
2543 * Returns:
2544 * qla2x00 local function return status code.
2545 *
2546 * Context:
2547 * Kernel context.
2548 */
2549int
7b867cf7 2550qla2x00_full_login_lip(scsi_qla_host_t *vha)
1da177e4
LT		 2551{
2552 int rval;
2553 mbx_cmd_t mc;
2554 mbx_cmd_t *mcp = &mc;
2555
5f28d2d7
SK		 2556 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
2557 "Entered %s.\n", __func__);
1da177e4
LT		 2558
2559 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
7b867cf7 2560 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
0c8c39af 2561 mcp->mb[2] = 0;
1da177e4
LT		 2562 mcp->mb[3] = 0;
2563 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
2564 mcp->in_mb = MBX_0;
b93480e3 2565 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2566 mcp->flags = 0;
7b867cf7 2567 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2568
2569 if (rval != QLA_SUCCESS) {
2570 /*EMPTY*/
7c3df132 2571 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
1da177e4
LT		 2572 } else {
2573 /*EMPTY*/
5f28d2d7
SK		 2574 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
2575 "Done %s.\n", __func__);
1da177e4
LT		 2576 }
2577
2578 return rval;
2579}
2580
2581/*
2582 * qla2x00_get_id_list
2583 *
2584 * Input:
2585 * ha = adapter block pointer.
2586 *
2587 * Returns:
2588 * qla2x00 local function return status code.
2589 *
2590 * Context:
2591 * Kernel context.
2592 */
2593int
7b867cf7 2594qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
1da177e4
LT		 2595 uint16_t *entries)
2596{
2597 int rval;
2598 mbx_cmd_t mc;
2599 mbx_cmd_t *mcp = &mc;
2600
5f28d2d7
SK		 2601 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
2602 "Entered %s.\n", __func__);
1da177e4
LT		 2603
2604 if (id_list == NULL)
2605 return QLA_FUNCTION_FAILED;
2606
2607 mcp->mb[0] = MBC_GET_ID_LIST;
1c7c6357 2608 mcp->out_mb = MBX_0;
7b867cf7 2609 if (IS_FWI2_CAPABLE(vha->hw)) {
1c7c6357
AV		 2610 mcp->mb[2] = MSW(id_list_dma);
2611 mcp->mb[3] = LSW(id_list_dma);
2612 mcp->mb[6] = MSW(MSD(id_list_dma));
2613 mcp->mb[7] = LSW(MSD(id_list_dma));
247ec457 2614 mcp->mb[8] = 0;
7b867cf7 2615 mcp->mb[9] = vha->vp_idx;
2c3dfe3f 2616 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
1c7c6357
AV		 2617 } else {
2618 mcp->mb[1] = MSW(id_list_dma);
2619 mcp->mb[2] = LSW(id_list_dma);
2620 mcp->mb[3] = MSW(MSD(id_list_dma));
2621 mcp->mb[6] = LSW(MSD(id_list_dma));
2622 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2623 }
1da177e4 2624 mcp->in_mb = MBX_1|MBX_0;
b93480e3 2625 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2626 mcp->flags = 0;
7b867cf7 2627 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2628
2629 if (rval != QLA_SUCCESS) {
2630 /*EMPTY*/
7c3df132 2631 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
1da177e4
LT		 2632 } else {
2633 *entries = mcp->mb[1];
5f28d2d7
SK		 2634 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
2635 "Done %s.\n", __func__);
1da177e4
LT		 2636 }
2637
2638 return rval;
2639}
2640
2641/*
2642 * qla2x00_get_resource_cnts
2643 * Get current firmware resource counts.
2644 *
2645 * Input:
2646 * ha = adapter block pointer.
2647 *
2648 * Returns:
2649 * qla2x00 local function return status code.
2650 *
2651 * Context:
2652 * Kernel context.
2653 */
2654int
03e8c680 2655qla2x00_get_resource_cnts(scsi_qla_host_t *vha)
1da177e4 2656{
03e8c680 2657 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2658 int rval;
2659 mbx_cmd_t mc;
2660 mbx_cmd_t *mcp = &mc;
2661
5f28d2d7
SK		 2662 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
2663 "Entered %s.\n", __func__);
1da177e4
LT		 2664
2665 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2666 mcp->out_mb = MBX_0;
4d0ea247 2667 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
f73cb695 2668 if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
f3a0a77e 2669 mcp->in_mb |= MBX_12;
b93480e3 2670 mcp->tov = MBX_TOV_SECONDS;
1da177e4 2671 mcp->flags = 0;
7b867cf7 2672 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2673
2674 if (rval != QLA_SUCCESS) {
2675 /*EMPTY*/
7c3df132
SK		 2676 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2677 "Failed mb[0]=%x.\n", mcp->mb[0]);
1da177e4 2678 } else {
5f28d2d7 2679 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
7c3df132
SK		 2680 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2681 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2682 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2683 mcp->mb[11], mcp->mb[12]);
1da177e4 2684
03e8c680
QT		 2685 ha->orig_fw_tgt_xcb_count = mcp->mb[1];
2686 ha->cur_fw_tgt_xcb_count = mcp->mb[2];
2687 ha->cur_fw_xcb_count = mcp->mb[3];
2688 ha->orig_fw_xcb_count = mcp->mb[6];
2689 ha->cur_fw_iocb_count = mcp->mb[7];
2690 ha->orig_fw_iocb_count = mcp->mb[10];
2691 if (ha->flags.npiv_supported)
2692 ha->max_npiv_vports = mcp->mb[11];
2693 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
2694 ha->fw_max_fcf_count = mcp->mb[12];
1da177e4
LT		 2695 }
2696
2697 return (rval);
2698}
2699
1da177e4
LT		 2700/*
2701 * qla2x00_get_fcal_position_map
2702 * Get FCAL (LILP) position map using mailbox command
2703 *
2704 * Input:
2705 * ha = adapter state pointer.
2706 * pos_map = buffer pointer (can be NULL).
2707 *
2708 * Returns:
2709 * qla2x00 local function return status code.
2710 *
2711 * Context:
2712 * Kernel context.
2713 */
2714int
7b867cf7 2715qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
1da177e4
LT		 2716{
2717 int rval;
2718 mbx_cmd_t mc;
2719 mbx_cmd_t *mcp = &mc;
2720 char *pmap;
2721 dma_addr_t pmap_dma;
7b867cf7 2722 struct qla_hw_data *ha = vha->hw;
1da177e4 2723
5f28d2d7
SK		 2724 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
2725 "Entered %s.\n", __func__);
7c3df132 2726
4b89258c 2727 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
1da177e4 2728 if (pmap == NULL) {
7c3df132
SK		 2729 ql_log(ql_log_warn, vha, 0x1080,
2730 "Memory alloc failed.\n");
1da177e4
LT		 2731 return QLA_MEMORY_ALLOC_FAILED;
2732 }
2733 memset(pmap, 0, FCAL_MAP_SIZE);
2734
2735 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2736 mcp->mb[2] = MSW(pmap_dma);
2737 mcp->mb[3] = LSW(pmap_dma);
2738 mcp->mb[6] = MSW(MSD(pmap_dma));
2739 mcp->mb[7] = LSW(MSD(pmap_dma));
2740 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2741 mcp->in_mb = MBX_1|MBX_0;
2742 mcp->buf_size = FCAL_MAP_SIZE;
2743 mcp->flags = MBX_DMA_IN;
2744 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
7b867cf7 2745 rval = qla2x00_mailbox_command(vha, mcp);
1da177e4
LT		 2746
2747 if (rval == QLA_SUCCESS) {
5f28d2d7 2748 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
7c3df132
SK		 2749 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2750 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2751 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2752 pmap, pmap[0] + 1);
1da177e4
LT		 2753
2754 if (pos_map)
2755 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2756 }
2757 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2758
2759 if (rval != QLA_SUCCESS) {
7c3df132 2760 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
1da177e4 2761 } else {
5f28d2d7
SK		 2762 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
2763 "Done %s.\n", __func__);
1da177e4
LT		 2764 }
2765
2766 return rval;
2767}
392e2f65
AV		 2768
2769/*
2770 * qla2x00_get_link_status
2771 *
2772 * Input:
2773 * ha = adapter block pointer.
2774 * loop_id = device loop ID.
2775 * ret_buf = pointer to link status return buffer.
2776 *
2777 * Returns:
2778 * 0 = success.
2779 * BIT_0 = mem alloc error.
2780 * BIT_1 = mailbox error.
2781 */
2782int
7b867cf7 2783qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
43ef0580 2784 struct link_statistics *stats, dma_addr_t stats_dma)
392e2f65
AV		 2785{
2786 int rval;
2787 mbx_cmd_t mc;
2788 mbx_cmd_t *mcp = &mc;
c6dc9905
JC		 2789 uint32_t *iter = (void *)stats;
2790 ushort dwords = offsetof(typeof(*stats), link_up_cnt)/sizeof(*iter);
7b867cf7 2791 struct qla_hw_data *ha = vha->hw;
392e2f65 2792
5f28d2d7
SK		 2793 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
2794 "Entered %s.\n", __func__);
392e2f65 2795
392e2f65 2796 mcp->mb[0] = MBC_GET_LINK_STATUS;
c6dc9905
JC		 2797 mcp->mb[2] = MSW(LSD(stats_dma));
2798 mcp->mb[3] = LSW(LSD(stats_dma));
43ef0580
AV		 2799 mcp->mb[6] = MSW(MSD(stats_dma));
2800 mcp->mb[7] = LSW(MSD(stats_dma));
392e2f65
AV		 2801 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2802 mcp->in_mb = MBX_0;
e428924c 2803 if (IS_FWI2_CAPABLE(ha)) {
392e2f65
AV		 2804 mcp->mb[1] = loop_id;
2805 mcp->mb[4] = 0;
2806 mcp->mb[10] = 0;
2807 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2808 mcp->in_mb |= MBX_1;
2809 } else if (HAS_EXTENDED_IDS(ha)) {
2810 mcp->mb[1] = loop_id;
2811 mcp->mb[10] = 0;
2812 mcp->out_mb |= MBX_10|MBX_1;
2813 } else {
2814 mcp->mb[1] = loop_id << 8;
2815 mcp->out_mb |= MBX_1;
2816 }
b93480e3 2817 mcp->tov = MBX_TOV_SECONDS;
392e2f65 2818 mcp->flags = IOCTL_CMD;
7b867cf7 2819 rval = qla2x00_mailbox_command(vha, mcp);
392e2f65
AV		 2820
2821 if (rval == QLA_SUCCESS) {
2822 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2823 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2824 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
43ef0580 2825 rval = QLA_FUNCTION_FAILED;
392e2f65 2826 } else {
c6dc9905 2827 /* Re-endianize - firmware data is le32. */
5f28d2d7
SK		 2828 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
2829 "Done %s.\n", __func__);
da08ef5c
JC		 2830 for ( ; dwords--; iter++)
2831 le32_to_cpus(iter);
392e2f65
AV		 2832 }
2833 } else {
2834 /* Failed. */
7c3df132 2835 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
392e2f65
AV		 2836 }
2837
392e2f65
AV		 2838 return rval;
2839}
2840
2841int
7b867cf7 2842qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
15f30a57 2843 dma_addr_t stats_dma, uint16_t options)
1c7c6357
AV		 2844{
2845 int rval;
2846 mbx_cmd_t mc;
2847 mbx_cmd_t *mcp = &mc;
da08ef5c 2848 uint32_t *iter, dwords;
1c7c6357 2849
5f28d2d7
SK		 2850 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
2851 "Entered %s.\n", __func__);
1c7c6357 2852
15f30a57
QT		 2853 memset(&mc, 0, sizeof(mc));
2854 mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
2855 mc.mb[2] = MSW(stats_dma);
2856 mc.mb[3] = LSW(stats_dma);
2857 mc.mb[6] = MSW(MSD(stats_dma));
2858 mc.mb[7] = LSW(MSD(stats_dma));
2859 mc.mb[8] = sizeof(struct link_statistics) / 4;
2860 mc.mb[9] = cpu_to_le16(vha->vp_idx);
2861 mc.mb[10] = cpu_to_le16(options);
2862
2863 rval = qla24xx_send_mb_cmd(vha, &mc);
1c7c6357
AV		 2864
2865 if (rval == QLA_SUCCESS) {
2866 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 2867 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2868 "Failed mb[0]=%x.\n", mcp->mb[0]);
43ef0580 2869 rval = QLA_FUNCTION_FAILED;
1c7c6357 2870 } else {
5f28d2d7
SK		 2871 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
2872 "Done %s.\n", __func__);
c6dc9905 2873 /* Re-endianize - firmware data is le32. */
43ef0580 2874 dwords = sizeof(struct link_statistics) / 4;
da08ef5c
JC		 2875 iter = &stats->link_fail_cnt;
2876 for ( ; dwords--; iter++)
2877 le32_to_cpus(iter);
1c7c6357
AV		 2878 }
2879 } else {
2880 /* Failed. */
7c3df132 2881 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
1c7c6357
AV		 2882 }
2883
1c7c6357
AV		 2884 return rval;
2885}
1c7c6357
AV		 2886
2887int
2afa19a9 2888qla24xx_abort_command(srb_t *sp)
1c7c6357
AV		 2889{
2890 int rval;
1c7c6357
AV		 2891 unsigned long flags = 0;
2892
2893 struct abort_entry_24xx *abt;
2894 dma_addr_t abt_dma;
2895 uint32_t handle;
2afa19a9
AC		 2896 fc_port_t *fcport = sp->fcport;
2897 struct scsi_qla_host *vha = fcport->vha;
7b867cf7 2898 struct qla_hw_data *ha = vha->hw;
67c2e93a 2899 struct req_que *req = vha->req;
1c7c6357 2900
5f28d2d7
SK		 2901 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
2902 "Entered %s.\n", __func__);
1c7c6357 2903
d7459527
MH		 2904 if (vha->flags.qpairs_available && sp->qpair)
2905 req = sp->qpair->req;
2906
4440e46d
AB		 2907 if (ql2xasynctmfenable)
2908 return qla24xx_async_abort_command(sp);
2909
7b867cf7 2910 spin_lock_irqsave(&ha->hardware_lock, flags);
8d93f550 2911 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
7b867cf7 2912 if (req->outstanding_cmds[handle] == sp)
1c7c6357
AV		 2913 break;
2914 }
7b867cf7 2915 spin_unlock_irqrestore(&ha->hardware_lock, flags);
8d93f550 2916 if (handle == req->num_outstanding_cmds) {
1c7c6357
AV		 2917 /* Command not found. */
2918 return QLA_FUNCTION_FAILED;
2919 }
2920
2921 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2922 if (abt == NULL) {
7c3df132
SK		 2923 ql_log(ql_log_warn, vha, 0x108d,
2924 "Failed to allocate abort IOCB.\n");
1c7c6357
AV		 2925 return QLA_MEMORY_ALLOC_FAILED;
2926 }
2927 memset(abt, 0, sizeof(struct abort_entry_24xx));
2928
2929 abt->entry_type = ABORT_IOCB_TYPE;
2930 abt->entry_count = 1;
2afa19a9 2931 abt->handle = MAKE_HANDLE(req->id, abt->handle);
1c7c6357 2932 abt->nport_handle = cpu_to_le16(fcport->loop_id);
a74ec14f 2933 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
1c7c6357
AV		 2934 abt->port_id[0] = fcport->d_id.b.al_pa;
2935 abt->port_id[1] = fcport->d_id.b.area;
2936 abt->port_id[2] = fcport->d_id.b.domain;
c6d39e23 2937 abt->vp_index = fcport->vha->vp_idx;
73208dfd
AC		 2938
2939 abt->req_que_no = cpu_to_le16(req->id);
2940
7b867cf7 2941 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
1c7c6357 2942 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2943 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2944 "Failed to issue IOCB (%x).\n", rval);
1c7c6357 2945 } else if (abt->entry_status != 0) {
7c3df132
SK		 2946 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2947 "Failed to complete IOCB -- error status (%x).\n",
2948 abt->entry_status);
1c7c6357 2949 rval = QLA_FUNCTION_FAILED;
ad950360 2950 } else if (abt->nport_handle != cpu_to_le16(0)) {
7c3df132
SK		 2951 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2952 "Failed to complete IOCB -- completion status (%x).\n",
2953 le16_to_cpu(abt->nport_handle));
f934c9d0
CD		 2954 if (abt->nport_handle == CS_IOCB_ERROR)
2955 rval = QLA_FUNCTION_PARAMETER_ERROR;
2956 else
2957 rval = QLA_FUNCTION_FAILED;
1c7c6357 2958 } else {
5f28d2d7
SK		 2959 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
2960 "Done %s.\n", __func__);
1c7c6357
AV		 2961 }
2962
2963 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2964
2965 return rval;
2966}
2967
2968struct tsk_mgmt_cmd {
2969 union {
2970 struct tsk_mgmt_entry tsk;
2971 struct sts_entry_24xx sts;
2972 } p;
2973};
2974
523ec773
AV		 2975static int
2976__qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
9cb78c16 2977 uint64_t l, int tag)
1c7c6357 2978{
523ec773 2979 int rval, rval2;
1c7c6357 2980 struct tsk_mgmt_cmd *tsk;
9ca1d01f 2981 struct sts_entry_24xx *sts;
1c7c6357 2982 dma_addr_t tsk_dma;
7b867cf7
AC		 2983 scsi_qla_host_t *vha;
2984 struct qla_hw_data *ha;
73208dfd
AC		 2985 struct req_que *req;
2986 struct rsp_que *rsp;
d7459527 2987 struct qla_qpair *qpair;
1c7c6357 2988
7b867cf7
AC		 2989 vha = fcport->vha;
2990 ha = vha->hw;
2afa19a9 2991 req = vha->req;
7c3df132 2992
5f28d2d7
SK		 2993 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
2994 "Entered %s.\n", __func__);
7c3df132 2995
d7459527
MH		 2996 if (vha->vp_idx && vha->qpair) {
2997 /* NPIV port */
2998 qpair = vha->qpair;
2999 rsp = qpair->rsp;
3000 req = qpair->req;
3001 } else {
68ca949c 3002 rsp = req->rsp;
d7459527
MH		 3003 }
3004
7b867cf7 3005 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
1c7c6357 3006 if (tsk == NULL) {
7c3df132
SK		 3007 ql_log(ql_log_warn, vha, 0x1093,
3008 "Failed to allocate task management IOCB.\n");
1c7c6357
AV		 3009 return QLA_MEMORY_ALLOC_FAILED;
3010 }
3011 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
3012
3013 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3014 tsk->p.tsk.entry_count = 1;
2afa19a9 3015 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
1c7c6357 3016 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
00a537b8 3017 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
523ec773 3018 tsk->p.tsk.control_flags = cpu_to_le32(type);
1c7c6357
AV		 3019 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
3020 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
3021 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
c6d39e23 3022 tsk->p.tsk.vp_index = fcport->vha->vp_idx;
523ec773
AV		 3023 if (type == TCF_LUN_RESET) {
3024 int_to_scsilun(l, &tsk->p.tsk.lun);
3025 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
3026 sizeof(tsk->p.tsk.lun));
3027 }
2c3dfe3f 3028
9ca1d01f 3029 sts = &tsk->p.sts;
7b867cf7 3030 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
1c7c6357 3031 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3032 ql_dbg(ql_dbg_mbx, vha, 0x1094,
3033 "Failed to issue %s reset IOCB (%x).\n", name, rval);
9ca1d01f 3034 } else if (sts->entry_status != 0) {
7c3df132
SK		 3035 ql_dbg(ql_dbg_mbx, vha, 0x1095,
3036 "Failed to complete IOCB -- error status (%x).\n",
3037 sts->entry_status);
1c7c6357 3038 rval = QLA_FUNCTION_FAILED;
ad950360 3039 } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3040 ql_dbg(ql_dbg_mbx, vha, 0x1096,
3041 "Failed to complete IOCB -- completion status (%x).\n",
3042 le16_to_cpu(sts->comp_status));
9ca1d01f 3043 rval = QLA_FUNCTION_FAILED;
97dec564
AV		 3044 } else if (le16_to_cpu(sts->scsi_status) &
3045 SS_RESPONSE_INFO_LEN_VALID) {
3046 if (le32_to_cpu(sts->rsp_data_len) < 4) {
5f28d2d7 3047 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
7c3df132
SK		 3048 "Ignoring inconsistent data length -- not enough "
3049 "response info (%d).\n",
3050 le32_to_cpu(sts->rsp_data_len));
97dec564 3051 } else if (sts->data[3]) {
7c3df132
SK		 3052 ql_dbg(ql_dbg_mbx, vha, 0x1098,
3053 "Failed to complete IOCB -- response (%x).\n",
3054 sts->data[3]);
97dec564
AV		 3055 rval = QLA_FUNCTION_FAILED;
3056 }
1c7c6357
AV		 3057 }
3058
3059 /* Issue marker IOCB. */
73208dfd 3060 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
523ec773
AV		 3061 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
3062 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 3063 ql_dbg(ql_dbg_mbx, vha, 0x1099,
3064 "Failed to issue marker IOCB (%x).\n", rval2);
1c7c6357 3065 } else {
5f28d2d7
SK		 3066 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
3067 "Done %s.\n", __func__);
1c7c6357
AV		 3068 }
3069
7b867cf7 3070 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
1c7c6357
AV		 3071
3072 return rval;
3073}
3074
523ec773 3075int
9cb78c16 3076qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3077{
3822263e
MI		 3078 struct qla_hw_data *ha = fcport->vha->hw;
3079
3080 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3081 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
3082
2afa19a9 3083 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
523ec773
AV		 3084}
3085
3086int
9cb78c16 3087qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
523ec773 3088{
3822263e
MI		 3089 struct qla_hw_data *ha = fcport->vha->hw;
3090
3091 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
3092 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
3093
2afa19a9 3094 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
523ec773
AV		 3095}
3096
1c7c6357 3097int
7b867cf7 3098qla2x00_system_error(scsi_qla_host_t *vha)
1c7c6357
AV		 3099{
3100 int rval;
3101 mbx_cmd_t mc;
3102 mbx_cmd_t *mcp = &mc;
7b867cf7 3103 struct qla_hw_data *ha = vha->hw;
1c7c6357 3104
68af0811 3105 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
1c7c6357
AV		 3106 return QLA_FUNCTION_FAILED;
3107
5f28d2d7
SK		 3108 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
3109 "Entered %s.\n", __func__);
1c7c6357
AV		 3110
3111 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
3112 mcp->out_mb = MBX_0;
3113 mcp->in_mb = MBX_0;
3114 mcp->tov = 5;
3115 mcp->flags = 0;
7b867cf7 3116 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3117
3118 if (rval != QLA_SUCCESS) {
7c3df132 3119 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
1c7c6357 3120 } else {
5f28d2d7
SK		 3121 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
3122 "Done %s.\n", __func__);
1c7c6357
AV		 3123 }
3124
3125 return rval;
3126}
3127
db64e930
JC		 3128int
3129qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
3130{
3131 int rval;
3132 mbx_cmd_t mc;
3133 mbx_cmd_t *mcp = &mc;
3134
f299c7c2
JC		 3135 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3136 !IS_QLA27XX(vha->hw))
db64e930
JC		 3137 return QLA_FUNCTION_FAILED;
3138
3139 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
3140 "Entered %s.\n", __func__);
3141
3142 mcp->mb[0] = MBC_WRITE_SERDES;
3143 mcp->mb[1] = addr;
064135e0
AV		 3144 if (IS_QLA2031(vha->hw))
3145 mcp->mb[2] = data & 0xff;
3146 else
3147 mcp->mb[2] = data;
3148
db64e930
JC		 3149 mcp->mb[3] = 0;
3150 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
3151 mcp->in_mb = MBX_0;
3152 mcp->tov = MBX_TOV_SECONDS;
3153 mcp->flags = 0;
3154 rval = qla2x00_mailbox_command(vha, mcp);
3155
3156 if (rval != QLA_SUCCESS) {
3157 ql_dbg(ql_dbg_mbx, vha, 0x1183,
3158 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3159 } else {
3160 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
3161 "Done %s.\n", __func__);
3162 }
3163
3164 return rval;
3165}
3166
3167int
3168qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
3169{
3170 int rval;
3171 mbx_cmd_t mc;
3172 mbx_cmd_t *mcp = &mc;
3173
f299c7c2
JC		 3174 if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3175 !IS_QLA27XX(vha->hw))
db64e930
JC		 3176 return QLA_FUNCTION_FAILED;
3177
3178 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
3179 "Entered %s.\n", __func__);
3180
3181 mcp->mb[0] = MBC_READ_SERDES;
3182 mcp->mb[1] = addr;
3183 mcp->mb[3] = 0;
3184 mcp->out_mb = MBX_3|MBX_1|MBX_0;
3185 mcp->in_mb = MBX_1|MBX_0;
3186 mcp->tov = MBX_TOV_SECONDS;
3187 mcp->flags = 0;
3188 rval = qla2x00_mailbox_command(vha, mcp);
3189
064135e0
AV		 3190 if (IS_QLA2031(vha->hw))
3191 *data = mcp->mb[1] & 0xff;
3192 else
3193 *data = mcp->mb[1];
db64e930
JC		 3194
3195 if (rval != QLA_SUCCESS) {
3196 ql_dbg(ql_dbg_mbx, vha, 0x1186,
3197 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3198 } else {
3199 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
3200 "Done %s.\n", __func__);
3201 }
3202
3203 return rval;
3204}
3205
e8887c51
JC		 3206int
3207qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
3208{
3209 int rval;
3210 mbx_cmd_t mc;
3211 mbx_cmd_t *mcp = &mc;
3212
3213 if (!IS_QLA8044(vha->hw))
3214 return QLA_FUNCTION_FAILED;
3215
3216 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186,
3217 "Entered %s.\n", __func__);
3218
3219 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3220 mcp->mb[1] = HCS_WRITE_SERDES;
3221 mcp->mb[3] = LSW(addr);
3222 mcp->mb[4] = MSW(addr);
3223 mcp->mb[5] = LSW(data);
3224 mcp->mb[6] = MSW(data);
3225 mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
3226 mcp->in_mb = MBX_0;
3227 mcp->tov = MBX_TOV_SECONDS;
3228 mcp->flags = 0;
3229 rval = qla2x00_mailbox_command(vha, mcp);
3230
3231 if (rval != QLA_SUCCESS) {
3232 ql_dbg(ql_dbg_mbx, vha, 0x1187,
3233 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3234 } else {
3235 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
3236 "Done %s.\n", __func__);
3237 }
3238
3239 return rval;
3240}
3241
3242int
3243qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
3244{
3245 int rval;
3246 mbx_cmd_t mc;
3247 mbx_cmd_t *mcp = &mc;
3248
3249 if (!IS_QLA8044(vha->hw))
3250 return QLA_FUNCTION_FAILED;
3251
3252 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
3253 "Entered %s.\n", __func__);
3254
3255 mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
3256 mcp->mb[1] = HCS_READ_SERDES;
3257 mcp->mb[3] = LSW(addr);
3258 mcp->mb[4] = MSW(addr);
3259 mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
3260 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3261 mcp->tov = MBX_TOV_SECONDS;
3262 mcp->flags = 0;
3263 rval = qla2x00_mailbox_command(vha, mcp);
3264
3265 *data = mcp->mb[2] << 16 | mcp->mb[1];
3266
3267 if (rval != QLA_SUCCESS) {
3268 ql_dbg(ql_dbg_mbx, vha, 0x118a,
3269 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3270 } else {
3271 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
3272 "Done %s.\n", __func__);
3273 }
3274
3275 return rval;
3276}
3277
1c7c6357
AV		 3278/**
3279 * qla2x00_set_serdes_params() -
3280 * @ha: HA context
3281 *
3282 * Returns
3283 */
3284int
7b867cf7 3285qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
1c7c6357
AV		 3286 uint16_t sw_em_2g, uint16_t sw_em_4g)
3287{
3288 int rval;
3289 mbx_cmd_t mc;
3290 mbx_cmd_t *mcp = &mc;
3291
5f28d2d7
SK		 3292 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
3293 "Entered %s.\n", __func__);
1c7c6357
AV		 3294
3295 mcp->mb[0] = MBC_SERDES_PARAMS;
3296 mcp->mb[1] = BIT_0;
fdbc6833
AV		 3297 mcp->mb[2] = sw_em_1g | BIT_15;
3298 mcp->mb[3] = sw_em_2g | BIT_15;
3299 mcp->mb[4] = sw_em_4g | BIT_15;
1c7c6357
AV		 3300 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3301 mcp->in_mb = MBX_0;
b93480e3 3302 mcp->tov = MBX_TOV_SECONDS;
1c7c6357 3303 mcp->flags = 0;
7b867cf7 3304 rval = qla2x00_mailbox_command(vha, mcp);
1c7c6357
AV		 3305
3306 if (rval != QLA_SUCCESS) {
3307 /*EMPTY*/
7c3df132
SK		 3308 ql_dbg(ql_dbg_mbx, vha, 0x109f,
3309 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1c7c6357
AV		 3310 } else {
3311 /*EMPTY*/
5f28d2d7
SK		 3312 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
3313 "Done %s.\n", __func__);
1c7c6357
AV		 3314 }
3315
3316 return rval;
3317}
f6ef3b18
AV		 3318
3319int
7b867cf7 3320qla2x00_stop_firmware(scsi_qla_host_t *vha)
f6ef3b18
AV		 3321{
3322 int rval;
3323 mbx_cmd_t mc;
3324 mbx_cmd_t *mcp = &mc;
3325
7b867cf7 3326 if (!IS_FWI2_CAPABLE(vha->hw))
f6ef3b18
AV		 3327 return QLA_FUNCTION_FAILED;
3328
5f28d2d7
SK		 3329 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
3330 "Entered %s.\n", __func__);
f6ef3b18
AV		 3331
3332 mcp->mb[0] = MBC_STOP_FIRMWARE;
4ba988db
AV		 3333 mcp->mb[1] = 0;
3334 mcp->out_mb = MBX_1|MBX_0;
f6ef3b18
AV		 3335 mcp->in_mb = MBX_0;
3336 mcp->tov = 5;
3337 mcp->flags = 0;
7b867cf7 3338 rval = qla2x00_mailbox_command(vha, mcp);
f6ef3b18
AV		 3339
3340 if (rval != QLA_SUCCESS) {
7c3df132 3341 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
b469a7cb
AV		 3342 if (mcp->mb[0] == MBS_INVALID_COMMAND)
3343 rval = QLA_INVALID_COMMAND;
f6ef3b18 3344 } else {
5f28d2d7
SK		 3345 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
3346 "Done %s.\n", __func__);
f6ef3b18
AV		 3347 }
3348
3349 return rval;
3350}
a7a167bf
AV		 3351
3352int
7b867cf7 3353qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
a7a167bf
AV		 3354 uint16_t buffers)
3355{
3356 int rval;
3357 mbx_cmd_t mc;
3358 mbx_cmd_t *mcp = &mc;
3359
5f28d2d7
SK		 3360 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
3361 "Entered %s.\n", __func__);
7c3df132 3362
7b867cf7 3363 if (!IS_FWI2_CAPABLE(vha->hw))
a7a167bf
AV		 3364 return QLA_FUNCTION_FAILED;
3365
85880801
AV		 3366 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3367 return QLA_FUNCTION_FAILED;
3368
a7a167bf 3369 mcp->mb[0] = MBC_TRACE_CONTROL;
00b6bd25
AV		 3370 mcp->mb[1] = TC_EFT_ENABLE;
3371 mcp->mb[2] = LSW(eft_dma);
3372 mcp->mb[3] = MSW(eft_dma);
3373 mcp->mb[4] = LSW(MSD(eft_dma));
3374 mcp->mb[5] = MSW(MSD(eft_dma));
3375 mcp->mb[6] = buffers;
3376 mcp->mb[7] = TC_AEN_DISABLE;
3377 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
a7a167bf 3378 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3379 mcp->tov = MBX_TOV_SECONDS;
a7a167bf 3380 mcp->flags = 0;
7b867cf7 3381 rval = qla2x00_mailbox_command(vha, mcp);
00b6bd25 3382 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3383 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
3384 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3385 rval, mcp->mb[0], mcp->mb[1]);
00b6bd25 3386 } else {
5f28d2d7
SK		 3387 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
3388 "Done %s.\n", __func__);
00b6bd25
AV		 3389 }
3390
3391 return rval;
3392}
a7a167bf 3393
00b6bd25 3394int
7b867cf7 3395qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
00b6bd25
AV		 3396{
3397 int rval;
3398 mbx_cmd_t mc;
3399 mbx_cmd_t *mcp = &mc;
3400
5f28d2d7
SK		 3401 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
3402 "Entered %s.\n", __func__);
7c3df132 3403
7b867cf7 3404 if (!IS_FWI2_CAPABLE(vha->hw))
00b6bd25
AV		 3405 return QLA_FUNCTION_FAILED;
3406
85880801
AV		 3407 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3408 return QLA_FUNCTION_FAILED;
3409
00b6bd25
AV		 3410 mcp->mb[0] = MBC_TRACE_CONTROL;
3411 mcp->mb[1] = TC_EFT_DISABLE;
3412 mcp->out_mb = MBX_1|MBX_0;
3413 mcp->in_mb = MBX_1|MBX_0;
b93480e3 3414 mcp->tov = MBX_TOV_SECONDS;
00b6bd25 3415 mcp->flags = 0;
7b867cf7 3416 rval = qla2x00_mailbox_command(vha, mcp);
a7a167bf 3417 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3418 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
3419 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3420 rval, mcp->mb[0], mcp->mb[1]);
a7a167bf 3421 } else {
5f28d2d7
SK		 3422 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
3423 "Done %s.\n", __func__);
a7a167bf
AV		 3424 }
3425
3426 return rval;
3427}
3428
df613b96 3429int
7b867cf7 3430qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
df613b96
AV		 3431 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
3432{
3433 int rval;
3434 mbx_cmd_t mc;
3435 mbx_cmd_t *mcp = &mc;
3436
5f28d2d7
SK		 3437 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
3438 "Entered %s.\n", __func__);
7c3df132 3439
6246b8a1 3440 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
f73cb695 3441 !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
df613b96
AV		 3442 return QLA_FUNCTION_FAILED;
3443
85880801
AV		 3444 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3445 return QLA_FUNCTION_FAILED;
3446
df613b96
AV		 3447 mcp->mb[0] = MBC_TRACE_CONTROL;
3448 mcp->mb[1] = TC_FCE_ENABLE;
3449 mcp->mb[2] = LSW(fce_dma);
3450 mcp->mb[3] = MSW(fce_dma);
3451 mcp->mb[4] = LSW(MSD(fce_dma));
3452 mcp->mb[5] = MSW(MSD(fce_dma));
3453 mcp->mb[6] = buffers;
3454 mcp->mb[7] = TC_AEN_DISABLE;
3455 mcp->mb[8] = 0;
3456 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
3457 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
3458 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3459 MBX_1|MBX_0;
3460 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
b93480e3 3461 mcp->tov = MBX_TOV_SECONDS;
df613b96 3462 mcp->flags = 0;
7b867cf7 3463 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3464 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3465 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
3466 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3467 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3468 } else {
5f28d2d7
SK		 3469 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
3470 "Done %s.\n", __func__);
df613b96
AV		 3471
3472 if (mb)
3473 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
3474 if (dwords)
fa0926df 3475 *dwords = buffers;
df613b96
AV		 3476 }
3477
3478 return rval;
3479}
3480
3481int
7b867cf7 3482qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
df613b96
AV		 3483{
3484 int rval;
3485 mbx_cmd_t mc;
3486 mbx_cmd_t *mcp = &mc;
3487
5f28d2d7
SK		 3488 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
3489 "Entered %s.\n", __func__);
7c3df132 3490
7b867cf7 3491 if (!IS_FWI2_CAPABLE(vha->hw))
df613b96
AV		 3492 return QLA_FUNCTION_FAILED;
3493
85880801
AV		 3494 if (unlikely(pci_channel_offline(vha->hw->pdev)))
3495 return QLA_FUNCTION_FAILED;
3496
df613b96
AV		 3497 mcp->mb[0] = MBC_TRACE_CONTROL;
3498 mcp->mb[1] = TC_FCE_DISABLE;
3499 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
3500 mcp->out_mb = MBX_2|MBX_1|MBX_0;
3501 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
3502 MBX_1|MBX_0;
b93480e3 3503 mcp->tov = MBX_TOV_SECONDS;
df613b96 3504 mcp->flags = 0;
7b867cf7 3505 rval = qla2x00_mailbox_command(vha, mcp);
df613b96 3506 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3507 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
3508 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3509 rval, mcp->mb[0], mcp->mb[1]);
df613b96 3510 } else {
5f28d2d7
SK		 3511 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
3512 "Done %s.\n", __func__);
df613b96
AV		 3513
3514 if (wr)
3515 *wr = (uint64_t) mcp->mb[5] << 48 |
3516 (uint64_t) mcp->mb[4] << 32 |
3517 (uint64_t) mcp->mb[3] << 16 |
3518 (uint64_t) mcp->mb[2];
3519 if (rd)
3520 *rd = (uint64_t) mcp->mb[9] << 48 |
3521 (uint64_t) mcp->mb[8] << 32 |
3522 (uint64_t) mcp->mb[7] << 16 |
3523 (uint64_t) mcp->mb[6];
3524 }
3525
3526 return rval;
3527}
3528
6e98016c
GM		 3529int
3530qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
3531 uint16_t *port_speed, uint16_t *mb)
3532{
3533 int rval;
3534 mbx_cmd_t mc;
3535 mbx_cmd_t *mcp = &mc;
3536
5f28d2d7
SK		 3537 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
3538 "Entered %s.\n", __func__);
7c3df132 3539
6e98016c
GM		 3540 if (!IS_IIDMA_CAPABLE(vha->hw))
3541 return QLA_FUNCTION_FAILED;
3542
6e98016c
GM		 3543 mcp->mb[0] = MBC_PORT_PARAMS;
3544 mcp->mb[1] = loop_id;
3545 mcp->mb[2] = mcp->mb[3] = 0;
3546 mcp->mb[9] = vha->vp_idx;
3547 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3548 mcp->in_mb = MBX_3|MBX_1|MBX_0;
3549 mcp->tov = MBX_TOV_SECONDS;
3550 mcp->flags = 0;
3551 rval = qla2x00_mailbox_command(vha, mcp);
3552
3553 /* Return mailbox statuses. */
3554 if (mb != NULL) {
3555 mb[0] = mcp->mb[0];
3556 mb[1] = mcp->mb[1];
3557 mb[3] = mcp->mb[3];
3558 }
3559
3560 if (rval != QLA_SUCCESS) {
7c3df132 3561 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
6e98016c 3562 } else {
5f28d2d7
SK		 3563 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
3564 "Done %s.\n", __func__);
6e98016c
GM		 3565 if (port_speed)
3566 *port_speed = mcp->mb[3];
3567 }
3568
3569 return rval;
3570}
3571
d8b45213 3572int
7b867cf7 3573qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
d8b45213
AV		 3574 uint16_t port_speed, uint16_t *mb)
3575{
3576 int rval;
3577 mbx_cmd_t mc;
3578 mbx_cmd_t *mcp = &mc;
3579
5f28d2d7
SK		 3580 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
3581 "Entered %s.\n", __func__);
7c3df132 3582
7b867cf7 3583 if (!IS_IIDMA_CAPABLE(vha->hw))
d8b45213
AV		 3584 return QLA_FUNCTION_FAILED;
3585
d8b45213
AV		 3586 mcp->mb[0] = MBC_PORT_PARAMS;
3587 mcp->mb[1] = loop_id;
3588 mcp->mb[2] = BIT_0;
6246b8a1 3589 if (IS_CNA_CAPABLE(vha->hw))
1bb39548
HZ		 3590 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
3591 else
3592 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3593 mcp->mb[9] = vha->vp_idx;
3594 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
3595 mcp->in_mb = MBX_3|MBX_1|MBX_0;
b93480e3 3596 mcp->tov = MBX_TOV_SECONDS;
d8b45213 3597 mcp->flags = 0;
7b867cf7 3598 rval = qla2x00_mailbox_command(vha, mcp);
d8b45213
AV		 3599
3600 /* Return mailbox statuses. */
3601 if (mb != NULL) {
3602 mb[0] = mcp->mb[0];
3603 mb[1] = mcp->mb[1];
3604 mb[3] = mcp->mb[3];
d8b45213
AV		 3605 }
3606
3607 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 3608 ql_dbg(ql_dbg_mbx, vha, 0x10b4,
3609 "Failed=%x.\n", rval);
d8b45213 3610 } else {
5f28d2d7
SK		 3611 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
3612 "Done %s.\n", __func__);
d8b45213
AV		 3613 }
3614
3615 return rval;
3616}
2c3dfe3f 3617
2c3dfe3f 3618void
7b867cf7 3619qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2c3dfe3f
SJ		 3620 struct vp_rpt_id_entry_24xx *rptid_entry)
3621{
7b867cf7 3622 struct qla_hw_data *ha = vha->hw;
41dc529a 3623 scsi_qla_host_t *vp = NULL;
feafb7b1 3624 unsigned long flags;
4ac8d4ca 3625 int found;
482c9dc7 3626 port_id_t id;
2c3dfe3f 3627
5f28d2d7
SK		 3628 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
3629 "Entered %s.\n", __func__);
7c3df132 3630
2c3dfe3f
SJ		 3631 if (rptid_entry->entry_status != 0)
3632 return;
2c3dfe3f 3633
482c9dc7
QT		 3634 id.b.domain = rptid_entry->port_id[2];
3635 id.b.area = rptid_entry->port_id[1];
3636 id.b.al_pa = rptid_entry->port_id[0];
3637 id.b.rsvd_1 = 0;
3638
2c3dfe3f 3639 if (rptid_entry->format == 0) {
41dc529a 3640 /* loop */
ec7193e2 3641 ql_dbg(ql_dbg_async, vha, 0x10b7,
7c3df132 3642 "Format 0 : Number of VPs setup %d, number of "
41dc529a
QT		 3643 "VPs acquired %d.\n", rptid_entry->vp_setup,
3644 rptid_entry->vp_acquired);
ec7193e2 3645 ql_dbg(ql_dbg_async, vha, 0x10b8,
7c3df132
SK		 3646 "Primary port id %02x%02x%02x.\n",
3647 rptid_entry->port_id[2], rptid_entry->port_id[1],
3648 rptid_entry->port_id[0]);
41dc529a 3649
482c9dc7 3650 qlt_update_host_map(vha, id);
41dc529a 3651
2c3dfe3f 3652 } else if (rptid_entry->format == 1) {
41dc529a 3653 /* fabric */
ec7193e2 3654 ql_dbg(ql_dbg_async, vha, 0x10b9,
7c3df132 3655 "Format 1: VP[%d] enabled - status %d - with "
41dc529a
QT		 3656 "port id %02x%02x%02x.\n", rptid_entry->vp_idx,
3657 rptid_entry->vp_status,
2c3dfe3f 3658 rptid_entry->port_id[2], rptid_entry->port_id[1],
7c3df132 3659 rptid_entry->port_id[0]);
531a82d1 3660
969a6199 3661 /* buffer to buffer credit flag */
41dc529a
QT		 3662 vha->flags.bbcr_enable = (rptid_entry->u.f1.bbcr & 0xf) != 0;
3663
3664 if (rptid_entry->vp_idx == 0) {
3665 if (rptid_entry->vp_status == VP_STAT_COMPL) {
3666 /* FA-WWN is only for physical port */
3667 if (qla_ini_mode_enabled(vha) &&
3668 ha->flags.fawwpn_enabled &&
3669 (rptid_entry->u.f1.flags &
3670 VP_FLAGS_NAME_VALID)) {
3671 memcpy(vha->port_name,
3672 rptid_entry->u.f1.port_name,
3673 WWN_SIZE);
3674 }
7c9c4766 3675
482c9dc7 3676 qlt_update_host_map(vha, id);
7c9c4766 3677 }
41dc529a 3678
41dc529a
QT		 3679 set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
3680 set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
3681 } else {
3682 if (rptid_entry->vp_status != VP_STAT_COMPL &&
3683 rptid_entry->vp_status != VP_STAT_ID_CHG) {
3684 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
3685 "Could not acquire ID for VP[%d].\n",
3686 rptid_entry->vp_idx);
3687 return;
4ac8d4ca 3688 }
feafb7b1 3689
41dc529a
QT		 3690 found = 0;
3691 spin_lock_irqsave(&ha->vport_slock, flags);
3692 list_for_each_entry(vp, &ha->vp_list, list) {
3693 if (rptid_entry->vp_idx == vp->vp_idx) {
3694 found = 1;
3695 break;
3696 }
3697 }
3698 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f 3699
41dc529a
QT		 3700 if (!found)
3701 return;
2c3dfe3f 3702
482c9dc7 3703 qlt_update_host_map(vp, id);
2c3dfe3f 3704
41dc529a
QT		 3705 /*
3706 * Cannot configure here as we are still sitting on the
3707 * response queue. Handle it in dpc context.
3708 */
3709 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
3710 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
3711 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
3712 }
531a82d1 3713 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
7b867cf7 3714 qla2xxx_wake_dpc(vha);
41dc529a
QT		 3715 } else if (rptid_entry->format == 2) {
3716 ql_dbg(ql_dbg_async, vha, 0xffff,
3717 "RIDA: format 2/N2N Primary port id %02x%02x%02x.\n",
3718 rptid_entry->port_id[2], rptid_entry->port_id[1],
3719 rptid_entry->port_id[0]);
3720
3721 ql_dbg(ql_dbg_async, vha, 0xffff,
3722 "N2N: Remote WWPN %8phC.\n",
3723 rptid_entry->u.f2.port_name);
3724
3725 /* N2N. direct connect */
3726 vha->d_id.b.domain = rptid_entry->port_id[2];
3727 vha->d_id.b.area = rptid_entry->port_id[1];
3728 vha->d_id.b.al_pa = rptid_entry->port_id[0];
3729
3730 spin_lock_irqsave(&ha->vport_slock, flags);
3731 qlt_update_vp_map(vha, SET_AL_PA);
3732 spin_unlock_irqrestore(&ha->vport_slock, flags);
2c3dfe3f
SJ		 3733 }
3734}
3735
3736/*
3737 * qla24xx_modify_vp_config
3738 * Change VP configuration for vha
3739 *
3740 * Input:
3741 * vha = adapter block pointer.
3742 *
3743 * Returns:
3744 * qla2xxx local function return status code.
3745 *
3746 * Context:
3747 * Kernel context.
3748 */
3749int
3750qla24xx_modify_vp_config(scsi_qla_host_t *vha)
3751{
3752 int rval;
3753 struct vp_config_entry_24xx *vpmod;
3754 dma_addr_t vpmod_dma;
7b867cf7
AC		 3755 struct qla_hw_data *ha = vha->hw;
3756 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f
SJ		 3757
3758 /* This can be called by the parent */
2c3dfe3f 3759
5f28d2d7
SK		 3760 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
3761 "Entered %s.\n", __func__);
7c3df132 3762
7b867cf7 3763 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2c3dfe3f 3764 if (!vpmod) {
7c3df132
SK		 3765 ql_log(ql_log_warn, vha, 0x10bc,
3766 "Failed to allocate modify VP IOCB.\n");
2c3dfe3f
SJ		 3767 return QLA_MEMORY_ALLOC_FAILED;
3768 }
3769
3770 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
3771 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
3772 vpmod->entry_count = 1;
3773 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
3774 vpmod->vp_count = 1;
3775 vpmod->vp_index1 = vha->vp_idx;
3776 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2d70c103
NB		 3777
3778 qlt_modify_vp_config(vha, vpmod);
3779
2c3dfe3f
SJ		 3780 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
3781 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
3782 vpmod->entry_count = 1;
3783
7b867cf7 3784 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2c3dfe3f 3785 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3786 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
3787 "Failed to issue VP config IOCB (%x).\n", rval);
2c3dfe3f 3788 } else if (vpmod->comp_status != 0) {
7c3df132
SK		 3789 ql_dbg(ql_dbg_mbx, vha, 0x10be,
3790 "Failed to complete IOCB -- error status (%x).\n",
3791 vpmod->comp_status);
2c3dfe3f 3792 rval = QLA_FUNCTION_FAILED;
ad950360 3793 } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3794 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
3795 "Failed to complete IOCB -- completion status (%x).\n",
3796 le16_to_cpu(vpmod->comp_status));
2c3dfe3f
SJ		 3797 rval = QLA_FUNCTION_FAILED;
3798 } else {
3799 /* EMPTY */
5f28d2d7
SK		 3800 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
3801 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3802 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
3803 }
7b867cf7 3804 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2c3dfe3f
SJ		 3805
3806 return rval;
3807}
3808
3809/*
3810 * qla24xx_control_vp
3811 * Enable a virtual port for given host
3812 *
3813 * Input:
3814 * ha = adapter block pointer.
3815 * vhba = virtual adapter (unused)
3816 * index = index number for enabled VP
3817 *
3818 * Returns:
3819 * qla2xxx local function return status code.
3820 *
3821 * Context:
3822 * Kernel context.
3823 */
3824int
3825qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3826{
3827 int rval;
3828 int map, pos;
3829 struct vp_ctrl_entry_24xx *vce;
3830 dma_addr_t vce_dma;
7b867cf7 3831 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 3832 int vp_index = vha->vp_idx;
7b867cf7 3833 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2c3dfe3f 3834
5f28d2d7 3835 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
7c3df132 3836 "Entered %s enabling index %d.\n", __func__, vp_index);
2c3dfe3f 3837
eb66dc60 3838 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
2c3dfe3f
SJ		 3839 return QLA_PARAMETER_ERROR;
3840
3841 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3842 if (!vce) {
7c3df132
SK		 3843 ql_log(ql_log_warn, vha, 0x10c2,
3844 "Failed to allocate VP control IOCB.\n");
2c3dfe3f
SJ		 3845 return QLA_MEMORY_ALLOC_FAILED;
3846 }
3847 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3848
3849 vce->entry_type = VP_CTRL_IOCB_TYPE;
3850 vce->entry_count = 1;
3851 vce->command = cpu_to_le16(cmd);
ad950360 3852 vce->vp_count = cpu_to_le16(1);
2c3dfe3f
SJ		 3853
3854 /* index map in firmware starts with 1; decrement index
3855 * this is ok as we never use index 0
3856 */
3857 map = (vp_index - 1) / 8;
3858 pos = (vp_index - 1) & 7;
6c2f527c 3859 mutex_lock(&ha->vport_lock);
2c3dfe3f 3860 vce->vp_idx_map[map] |= 1 << pos;
6c2f527c 3861 mutex_unlock(&ha->vport_lock);
2c3dfe3f 3862
7b867cf7 3863 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
2c3dfe3f 3864 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3865 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3866 "Failed to issue VP control IOCB (%x).\n", rval);
2c3dfe3f 3867 } else if (vce->entry_status != 0) {
7c3df132
SK		 3868 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3869 "Failed to complete IOCB -- error status (%x).\n",
2c3dfe3f
SJ		 3870 vce->entry_status);
3871 rval = QLA_FUNCTION_FAILED;
ad950360 3872 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) {
7c3df132
SK		 3873 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3874 "Failed to complet IOCB -- completion status (%x).\n",
2c3dfe3f
SJ		 3875 le16_to_cpu(vce->comp_status));
3876 rval = QLA_FUNCTION_FAILED;
3877 } else {
5f28d2d7
SK		 3878 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
3879 "Done %s.\n", __func__);
2c3dfe3f
SJ		 3880 }
3881
3882 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3883
3884 return rval;
3885}
3886
3887/*
3888 * qla2x00_send_change_request
3889 * Receive or disable RSCN request from fabric controller
3890 *
3891 * Input:
3892 * ha = adapter block pointer
3893 * format = registration format:
3894 * 0 - Reserved
3895 * 1 - Fabric detected registration
3896 * 2 - N_port detected registration
3897 * 3 - Full registration
3898 * FF - clear registration
3899 * vp_idx = Virtual port index
3900 *
3901 * Returns:
3902 * qla2x00 local function return status code.
3903 *
3904 * Context:
3905 * Kernel Context
3906 */
3907
3908int
7b867cf7 3909qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
2c3dfe3f
SJ		 3910 uint16_t vp_idx)
3911{
3912 int rval;
3913 mbx_cmd_t mc;
3914 mbx_cmd_t *mcp = &mc;
3915
5f28d2d7
SK		 3916 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
3917 "Entered %s.\n", __func__);
7c3df132 3918
2c3dfe3f
SJ		 3919 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3920 mcp->mb[1] = format;
3921 mcp->mb[9] = vp_idx;
3922 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3923 mcp->in_mb = MBX_0|MBX_1;
3924 mcp->tov = MBX_TOV_SECONDS;
3925 mcp->flags = 0;
7b867cf7 3926 rval = qla2x00_mailbox_command(vha, mcp);
2c3dfe3f
SJ		 3927
3928 if (rval == QLA_SUCCESS) {
3929 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3930 rval = BIT_1;
3931 }
3932 } else
3933 rval = BIT_1;
3934
3935 return rval;
3936}
338c9161
AV		 3937
3938int
7b867cf7 3939qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
338c9161
AV		 3940 uint32_t size)
3941{
3942 int rval;
3943 mbx_cmd_t mc;
3944 mbx_cmd_t *mcp = &mc;
3945
5f28d2d7
SK		 3946 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
3947 "Entered %s.\n", __func__);
338c9161 3948
7b867cf7 3949 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3950 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3951 mcp->mb[8] = MSW(addr);
3952 mcp->out_mb = MBX_8|MBX_0;
3953 } else {
3954 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3955 mcp->out_mb = MBX_0;
3956 }
3957 mcp->mb[1] = LSW(addr);
3958 mcp->mb[2] = MSW(req_dma);
3959 mcp->mb[3] = LSW(req_dma);
3960 mcp->mb[6] = MSW(MSD(req_dma));
3961 mcp->mb[7] = LSW(MSD(req_dma));
3962 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
7b867cf7 3963 if (IS_FWI2_CAPABLE(vha->hw)) {
338c9161
AV		 3964 mcp->mb[4] = MSW(size);
3965 mcp->mb[5] = LSW(size);
3966 mcp->out_mb |= MBX_5|MBX_4;
3967 } else {
3968 mcp->mb[4] = LSW(size);
3969 mcp->out_mb |= MBX_4;
3970 }
3971
3972 mcp->in_mb = MBX_0;
b93480e3 3973 mcp->tov = MBX_TOV_SECONDS;
338c9161 3974 mcp->flags = 0;
7b867cf7 3975 rval = qla2x00_mailbox_command(vha, mcp);
338c9161
AV		 3976
3977 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3978 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3979 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
338c9161 3980 } else {
5f28d2d7
SK		 3981 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
3982 "Done %s.\n", __func__);
338c9161
AV		 3983 }
3984
3985 return rval;
3986}
4d4df193
HK		 3987/* 84XX Support **************************************************************/
3988
3989struct cs84xx_mgmt_cmd {
3990 union {
3991 struct verify_chip_entry_84xx req;
3992 struct verify_chip_rsp_84xx rsp;
3993 } p;
3994};
3995
3996int
7b867cf7 3997qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
4d4df193
HK		 3998{
3999 int rval, retry;
4000 struct cs84xx_mgmt_cmd *mn;
4001 dma_addr_t mn_dma;
4002 uint16_t options;
4003 unsigned long flags;
7b867cf7 4004 struct qla_hw_data *ha = vha->hw;
4d4df193 4005
5f28d2d7
SK		 4006 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
4007 "Entered %s.\n", __func__);
4d4df193
HK		 4008
4009 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
4010 if (mn == NULL) {
4d4df193
HK		 4011 return QLA_MEMORY_ALLOC_FAILED;
4012 }
4013
4014 /* Force Update? */
4015 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
4016 /* Diagnostic firmware? */
4017 /* options |= MENLO_DIAG_FW; */
4018 /* We update the firmware with only one data sequence. */
4019 options |= VCO_END_OF_DATA;
4020
4d4df193 4021 do {
c1ec1f1b 4022 retry = 0;
4d4df193
HK		 4023 memset(mn, 0, sizeof(*mn));
4024 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
4025 mn->p.req.entry_count = 1;
4026 mn->p.req.options = cpu_to_le16(options);
4027
7c3df132
SK		 4028 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4029 "Dump of Verify Request.\n");
4030 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4031 (uint8_t *)mn, sizeof(*mn));
4d4df193 4032
7b867cf7 4033 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4d4df193 4034 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4035 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
4036 "Failed to issue verify IOCB (%x).\n", rval);
4d4df193
HK		 4037 goto verify_done;
4038 }
4039
7c3df132
SK		 4040 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4041 "Dump of Verify Response.\n");
4042 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4043 (uint8_t *)mn, sizeof(*mn));
4d4df193
HK		 4044
4045 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4046 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
4047 le16_to_cpu(mn->p.rsp.failure_code) : 0;
5f28d2d7 4048 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
7c3df132 4049 "cs=%x fc=%x.\n", status[0], status[1]);
4d4df193
HK		 4050
4051 if (status[0] != CS_COMPLETE) {
4052 rval = QLA_FUNCTION_FAILED;
4053 if (!(options & VCO_DONT_UPDATE_FW)) {
7c3df132
SK		 4054 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
4055 "Firmware update failed. Retrying "
4056 "without update firmware.\n");
4d4df193
HK		 4057 options |= VCO_DONT_UPDATE_FW;
4058 options &= ~VCO_FORCE_UPDATE;
4059 retry = 1;
4060 }
4061 } else {
5f28d2d7 4062 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
7c3df132
SK		 4063 "Firmware updated to %x.\n",
4064 le32_to_cpu(mn->p.rsp.fw_ver));
4d4df193
HK		 4065
4066 /* NOTE: we only update OP firmware. */
4067 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
4068 ha->cs84xx->op_fw_version =
4069 le32_to_cpu(mn->p.rsp.fw_ver);
4070 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
4071 flags);
4072 }
4073 } while (retry);
4074
4075verify_done:
4076 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
4077
4078 if (rval != QLA_SUCCESS) {
5f28d2d7
SK		 4079 ql_dbg(ql_dbg_mbx, vha, 0x10d1,
4080 "Failed=%x.\n", rval);
4d4df193 4081 } else {
5f28d2d7
SK		 4082 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
4083 "Done %s.\n", __func__);
4d4df193
HK		 4084 }
4085
4086 return rval;
4087}
73208dfd
AC		 4088
4089int
618a7523 4090qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
73208dfd
AC		 4091{
4092 int rval;
4093 unsigned long flags;
4094 mbx_cmd_t mc;
4095 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4096 struct qla_hw_data *ha = vha->hw;
4097
5f28d2d7
SK		 4098 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
4099 "Entered %s.\n", __func__);
7c3df132 4100
7c6300e3
JC		 4101 if (IS_SHADOW_REG_CAPABLE(ha))
4102 req->options |= BIT_13;
4103
73208dfd 4104 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4105 mcp->mb[1] = req->options;
73208dfd
AC		 4106 mcp->mb[2] = MSW(LSD(req->dma));
4107 mcp->mb[3] = LSW(LSD(req->dma));
4108 mcp->mb[6] = MSW(MSD(req->dma));
4109 mcp->mb[7] = LSW(MSD(req->dma));
4110 mcp->mb[5] = req->length;
4111 if (req->rsp)
4112 mcp->mb[10] = req->rsp->id;
4113 mcp->mb[12] = req->qos;
4114 mcp->mb[11] = req->vp_idx;
4115 mcp->mb[13] = req->rid;
f73cb695 4116 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4117 mcp->mb[15] = 0;
73208dfd 4118
73208dfd
AC		 4119 mcp->mb[4] = req->id;
4120 /* que in ptr index */
4121 mcp->mb[8] = 0;
4122 /* que out ptr index */
7c6300e3 4123 mcp->mb[9] = *req->out_ptr = 0;
73208dfd
AC		 4124 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
4125 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4126 mcp->in_mb = MBX_0;
4127 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4128 mcp->tov = MBX_TOV_SECONDS * 2;
4129
f73cb695 4130 if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4131 mcp->in_mb |= MBX_1;
ba4828b7 4132 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4133 mcp->out_mb |= MBX_15;
4134 /* debug q create issue in SR-IOV */
4135 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4136 }
73208dfd
AC		 4137
4138 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4139 if (!(req->options & BIT_0)) {
da9b1d5c 4140 WRT_REG_DWORD(req->req_q_in, 0);
29db41c3 4141 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4142 WRT_REG_DWORD(req->req_q_out, 0);
73208dfd
AC		 4143 }
4144 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4145
17d98630 4146 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4147 if (rval != QLA_SUCCESS) {
4148 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
4149 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4150 } else {
5f28d2d7
SK		 4151 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
4152 "Done %s.\n", __func__);
7c3df132
SK		 4153 }
4154
73208dfd
AC		 4155 return rval;
4156}
4157
4158int
618a7523 4159qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
73208dfd
AC		 4160{
4161 int rval;
4162 unsigned long flags;
4163 mbx_cmd_t mc;
4164 mbx_cmd_t *mcp = &mc;
73208dfd
AC		 4165 struct qla_hw_data *ha = vha->hw;
4166
5f28d2d7
SK		 4167 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
4168 "Entered %s.\n", __func__);
7c3df132 4169
7c6300e3
JC		 4170 if (IS_SHADOW_REG_CAPABLE(ha))
4171 rsp->options |= BIT_13;
4172
73208dfd 4173 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
618a7523 4174 mcp->mb[1] = rsp->options;
73208dfd
AC		 4175 mcp->mb[2] = MSW(LSD(rsp->dma));
4176 mcp->mb[3] = LSW(LSD(rsp->dma));
4177 mcp->mb[6] = MSW(MSD(rsp->dma));
4178 mcp->mb[7] = LSW(MSD(rsp->dma));
4179 mcp->mb[5] = rsp->length;
444786d7 4180 mcp->mb[14] = rsp->msix->entry;
73208dfd 4181 mcp->mb[13] = rsp->rid;
f73cb695 4182 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 4183 mcp->mb[15] = 0;
73208dfd 4184
73208dfd
AC		 4185 mcp->mb[4] = rsp->id;
4186 /* que in ptr index */
7c6300e3 4187 mcp->mb[8] = *rsp->in_ptr = 0;
73208dfd
AC		 4188 /* que out ptr index */
4189 mcp->mb[9] = 0;
2afa19a9 4190 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
73208dfd
AC		 4191 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4192 mcp->in_mb = MBX_0;
4193 mcp->flags = MBX_DMA_OUT;
6246b8a1
GM		 4194 mcp->tov = MBX_TOV_SECONDS * 2;
4195
4196 if (IS_QLA81XX(ha)) {
4197 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
4198 mcp->in_mb |= MBX_1;
f73cb695 4199 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 4200 mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
4201 mcp->in_mb |= MBX_1;
4202 /* debug q create issue in SR-IOV */
4203 mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
4204 }
73208dfd
AC		 4205
4206 spin_lock_irqsave(&ha->hardware_lock, flags);
618a7523 4207 if (!(rsp->options & BIT_0)) {
da9b1d5c 4208 WRT_REG_DWORD(rsp->rsp_q_out, 0);
b20f02e1 4209 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
da9b1d5c 4210 WRT_REG_DWORD(rsp->rsp_q_in, 0);
73208dfd
AC		 4211 }
4212
4213 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4214
17d98630 4215 rval = qla2x00_mailbox_command(vha, mcp);
7c3df132
SK		 4216 if (rval != QLA_SUCCESS) {
4217 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
4218 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4219 } else {
5f28d2d7
SK		 4220 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
4221 "Done %s.\n", __func__);
7c3df132
SK		 4222 }
4223
73208dfd
AC		 4224 return rval;
4225}
4226
8a659571
AV		 4227int
4228qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
4229{
4230 int rval;
4231 mbx_cmd_t mc;
4232 mbx_cmd_t *mcp = &mc;
4233
5f28d2d7
SK		 4234 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
4235 "Entered %s.\n", __func__);
8a659571
AV		 4236
4237 mcp->mb[0] = MBC_IDC_ACK;
4238 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4239 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4240 mcp->in_mb = MBX_0;
4241 mcp->tov = MBX_TOV_SECONDS;
4242 mcp->flags = 0;
4243 rval = qla2x00_mailbox_command(vha, mcp);
4244
4245 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4246 ql_dbg(ql_dbg_mbx, vha, 0x10da,
4247 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
8a659571 4248 } else {
5f28d2d7
SK		 4249 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
4250 "Done %s.\n", __func__);
8a659571
AV		 4251 }
4252
4253 return rval;
4254}
1d2874de
JC		 4255
4256int
4257qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
4258{
4259 int rval;
4260 mbx_cmd_t mc;
4261 mbx_cmd_t *mcp = &mc;
4262
5f28d2d7
SK		 4263 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
4264 "Entered %s.\n", __func__);
7c3df132 4265
f73cb695
CD		 4266 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4267 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4268 return QLA_FUNCTION_FAILED;
4269
1d2874de
JC		 4270 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4271 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
4272 mcp->out_mb = MBX_1|MBX_0;
4273 mcp->in_mb = MBX_1|MBX_0;
4274 mcp->tov = MBX_TOV_SECONDS;
4275 mcp->flags = 0;
4276 rval = qla2x00_mailbox_command(vha, mcp);
4277
4278 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4279 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
4280 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4281 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4282 } else {
5f28d2d7
SK		 4283 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
4284 "Done %s.\n", __func__);
1d2874de
JC		 4285 *sector_size = mcp->mb[1];
4286 }
4287
4288 return rval;
4289}
4290
4291int
4292qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
4293{
4294 int rval;
4295 mbx_cmd_t mc;
4296 mbx_cmd_t *mcp = &mc;
4297
f73cb695
CD		 4298 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4299 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4300 return QLA_FUNCTION_FAILED;
4301
5f28d2d7
SK		 4302 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
4303 "Entered %s.\n", __func__);
1d2874de
JC		 4304
4305 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4306 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
4307 FAC_OPT_CMD_WRITE_PROTECT;
4308 mcp->out_mb = MBX_1|MBX_0;
4309 mcp->in_mb = MBX_1|MBX_0;
4310 mcp->tov = MBX_TOV_SECONDS;
4311 mcp->flags = 0;
4312 rval = qla2x00_mailbox_command(vha, mcp);
4313
4314 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4315 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
4316 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4317 rval, mcp->mb[0], mcp->mb[1]);
1d2874de 4318 } else {
5f28d2d7
SK		 4319 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
4320 "Done %s.\n", __func__);
1d2874de
JC		 4321 }
4322
4323 return rval;
4324}
4325
4326int
4327qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
4328{
4329 int rval;
4330 mbx_cmd_t mc;
4331 mbx_cmd_t *mcp = &mc;
4332
f73cb695
CD		 4333 if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4334 !IS_QLA27XX(vha->hw))
1d2874de
JC		 4335 return QLA_FUNCTION_FAILED;
4336
5f28d2d7
SK		 4337 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
4338 "Entered %s.\n", __func__);
1d2874de
JC		 4339
4340 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
4341 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
4342 mcp->mb[2] = LSW(start);
4343 mcp->mb[3] = MSW(start);
4344 mcp->mb[4] = LSW(finish);
4345 mcp->mb[5] = MSW(finish);
4346 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4347 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4348 mcp->tov = MBX_TOV_SECONDS;
4349 mcp->flags = 0;
4350 rval = qla2x00_mailbox_command(vha, mcp);
4351
4352 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4353 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
4354 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4355 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1d2874de 4356 } else {
5f28d2d7
SK		 4357 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
4358 "Done %s.\n", __func__);
1d2874de
JC		 4359 }
4360
4361 return rval;
4362}
6e181be5
LC		 4363
4364int
4365qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
4366{
4367 int rval = 0;
4368 mbx_cmd_t mc;
4369 mbx_cmd_t *mcp = &mc;
4370
5f28d2d7
SK		 4371 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
4372 "Entered %s.\n", __func__);
6e181be5
LC		 4373
4374 mcp->mb[0] = MBC_RESTART_MPI_FW;
4375 mcp->out_mb = MBX_0;
4376 mcp->in_mb = MBX_0|MBX_1;
4377 mcp->tov = MBX_TOV_SECONDS;
4378 mcp->flags = 0;
4379 rval = qla2x00_mailbox_command(vha, mcp);
4380
4381 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4382 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
4383 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4384 rval, mcp->mb[0], mcp->mb[1]);
6e181be5 4385 } else {
5f28d2d7
SK		 4386 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
4387 "Done %s.\n", __func__);
6e181be5
LC		 4388 }
4389
4390 return rval;
4391}
ad0ecd61 4392
c46e65c7
JC		 4393int
4394qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4395{
4396 int rval;
4397 mbx_cmd_t mc;
4398 mbx_cmd_t *mcp = &mc;
4399 int i;
4400 int len;
4401 uint16_t *str;
4402 struct qla_hw_data *ha = vha->hw;
4403
4404 if (!IS_P3P_TYPE(ha))
4405 return QLA_FUNCTION_FAILED;
4406
4407 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4408 "Entered %s.\n", __func__);
4409
4410 str = (void *)version;
4411 len = strlen(version);
4412
4413 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4414 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4415 mcp->out_mb = MBX_1|MBX_0;
4416 for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4417 mcp->mb[i] = cpu_to_le16p(str);
4418 mcp->out_mb |= 1<<i;
4419 }
4420 for (; i < 16; i++) {
4421 mcp->mb[i] = 0;
4422 mcp->out_mb |= 1<<i;
4423 }
4424 mcp->in_mb = MBX_1|MBX_0;
4425 mcp->tov = MBX_TOV_SECONDS;
4426 mcp->flags = 0;
4427 rval = qla2x00_mailbox_command(vha, mcp);
4428
4429 if (rval != QLA_SUCCESS) {
4430 ql_dbg(ql_dbg_mbx, vha, 0x117c,
4431 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4432 } else {
4433 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
4434 "Done %s.\n", __func__);
4435 }
4436
4437 return rval;
4438}
4439
4440int
4441qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
4442{
4443 int rval;
4444 mbx_cmd_t mc;
4445 mbx_cmd_t *mcp = &mc;
4446 int len;
4447 uint16_t dwlen;
4448 uint8_t *str;
4449 dma_addr_t str_dma;
4450 struct qla_hw_data *ha = vha->hw;
4451
4452 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
4453 IS_P3P_TYPE(ha))
4454 return QLA_FUNCTION_FAILED;
4455
4456 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
4457 "Entered %s.\n", __func__);
4458
4459 str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
4460 if (!str) {
4461 ql_log(ql_log_warn, vha, 0x117f,
4462 "Failed to allocate driver version param.\n");
4463 return QLA_MEMORY_ALLOC_FAILED;
4464 }
4465
4466 memcpy(str, "\x7\x3\x11\x0", 4);
4467 dwlen = str[0];
4468 len = dwlen * 4 - 4;
4469 memset(str + 4, 0, len);
4470 if (len > strlen(version))
4471 len = strlen(version);
4472 memcpy(str + 4, version, len);
4473
4474 mcp->mb[0] = MBC_SET_RNID_PARAMS;
4475 mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
4476 mcp->mb[2] = MSW(LSD(str_dma));
4477 mcp->mb[3] = LSW(LSD(str_dma));
4478 mcp->mb[6] = MSW(MSD(str_dma));
4479 mcp->mb[7] = LSW(MSD(str_dma));
4480 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4481 mcp->in_mb = MBX_1|MBX_0;
4482 mcp->tov = MBX_TOV_SECONDS;
4483 mcp->flags = 0;
4484 rval = qla2x00_mailbox_command(vha, mcp);
4485
4486 if (rval != QLA_SUCCESS) {
4487 ql_dbg(ql_dbg_mbx, vha, 0x1180,
4488 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4489 } else {
4490 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
4491 "Done %s.\n", __func__);
4492 }
4493
4494 dma_pool_free(ha->s_dma_pool, str, str_dma);
4495
4496 return rval;
4497}
4498
fe52f6e1
JC		 4499static int
4500qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
4501{
4502 int rval;
4503 mbx_cmd_t mc;
4504 mbx_cmd_t *mcp = &mc;
4505
4506 if (!IS_FWI2_CAPABLE(vha->hw))
4507 return QLA_FUNCTION_FAILED;
4508
4509 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
4510 "Entered %s.\n", __func__);
4511
4512 mcp->mb[0] = MBC_GET_RNID_PARAMS;
4513 mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
4514 mcp->out_mb = MBX_1|MBX_0;
4515 mcp->in_mb = MBX_1|MBX_0;
4516 mcp->tov = MBX_TOV_SECONDS;
4517 mcp->flags = 0;
4518 rval = qla2x00_mailbox_command(vha, mcp);
4519 *temp = mcp->mb[1];
4520
4521 if (rval != QLA_SUCCESS) {
4522 ql_dbg(ql_dbg_mbx, vha, 0x115a,
4523 "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
4524 } else {
4525 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
4526 "Done %s.\n", __func__);
4527 }
4528
4529 return rval;
4530}
4531
ad0ecd61 4532int
6766df9e
JC		 4533qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4534 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4535{
4536 int rval;
4537 mbx_cmd_t mc;
4538 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4539 struct qla_hw_data *ha = vha->hw;
4540
5f28d2d7
SK		 4541 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
4542 "Entered %s.\n", __func__);
7c3df132 4543
6766df9e
JC		 4544 if (!IS_FWI2_CAPABLE(ha))
4545 return QLA_FUNCTION_FAILED;
ad0ecd61 4546
6766df9e
JC		 4547 if (len == 1)
4548 opt |= BIT_0;
4549
ad0ecd61
JC		 4550 mcp->mb[0] = MBC_READ_SFP;
4551 mcp->mb[1] = dev;
4552 mcp->mb[2] = MSW(sfp_dma);
4553 mcp->mb[3] = LSW(sfp_dma);
4554 mcp->mb[6] = MSW(MSD(sfp_dma));
4555 mcp->mb[7] = LSW(MSD(sfp_dma));
4556 mcp->mb[8] = len;
6766df9e 4557 mcp->mb[9] = off;
ad0ecd61
JC		 4558 mcp->mb[10] = opt;
4559 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1bff6cc8 4560 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4561 mcp->tov = MBX_TOV_SECONDS;
4562 mcp->flags = 0;
4563 rval = qla2x00_mailbox_command(vha, mcp);
4564
4565 if (opt & BIT_0)
6766df9e 4566 *sfp = mcp->mb[1];
ad0ecd61
JC		 4567
4568 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4569 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4570 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4571 } else {
5f28d2d7
SK		 4572 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4573 "Done %s.\n", __func__);
ad0ecd61
JC		 4574 }
4575
4576 return rval;
4577}
4578
4579int
6766df9e
JC		 4580qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
4581 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
ad0ecd61
JC		 4582{
4583 int rval;
4584 mbx_cmd_t mc;
4585 mbx_cmd_t *mcp = &mc;
6766df9e
JC		 4586 struct qla_hw_data *ha = vha->hw;
4587
5f28d2d7
SK		 4588 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
4589 "Entered %s.\n", __func__);
7c3df132 4590
6766df9e
JC		 4591 if (!IS_FWI2_CAPABLE(ha))
4592 return QLA_FUNCTION_FAILED;
ad0ecd61 4593
6766df9e
JC		 4594 if (len == 1)
4595 opt |= BIT_0;
4596
ad0ecd61 4597 if (opt & BIT_0)
6766df9e 4598 len = *sfp;
ad0ecd61
JC		 4599
4600 mcp->mb[0] = MBC_WRITE_SFP;
4601 mcp->mb[1] = dev;
4602 mcp->mb[2] = MSW(sfp_dma);
4603 mcp->mb[3] = LSW(sfp_dma);
4604 mcp->mb[6] = MSW(MSD(sfp_dma));
4605 mcp->mb[7] = LSW(MSD(sfp_dma));
4606 mcp->mb[8] = len;
6766df9e 4607 mcp->mb[9] = off;
ad0ecd61
JC		 4608 mcp->mb[10] = opt;
4609 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
6766df9e 4610 mcp->in_mb = MBX_1|MBX_0;
ad0ecd61
JC		 4611 mcp->tov = MBX_TOV_SECONDS;
4612 mcp->flags = 0;
4613 rval = qla2x00_mailbox_command(vha, mcp);
4614
4615 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4616 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
4617 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
ad0ecd61 4618 } else {
5f28d2d7
SK		 4619 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
4620 "Done %s.\n", __func__);
ad0ecd61
JC		 4621 }
4622
4623 return rval;
4624}
ce0423f4
AV		 4625
4626int
4627qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
4628 uint16_t size_in_bytes, uint16_t *actual_size)
4629{
4630 int rval;
4631 mbx_cmd_t mc;
4632 mbx_cmd_t *mcp = &mc;
4633
5f28d2d7
SK		 4634 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
4635 "Entered %s.\n", __func__);
7c3df132 4636
6246b8a1 4637 if (!IS_CNA_CAPABLE(vha->hw))
ce0423f4
AV		 4638 return QLA_FUNCTION_FAILED;
4639
ce0423f4
AV		 4640 mcp->mb[0] = MBC_GET_XGMAC_STATS;
4641 mcp->mb[2] = MSW(stats_dma);
4642 mcp->mb[3] = LSW(stats_dma);
4643 mcp->mb[6] = MSW(MSD(stats_dma));
4644 mcp->mb[7] = LSW(MSD(stats_dma));
4645 mcp->mb[8] = size_in_bytes >> 2;
4646 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
4647 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4648 mcp->tov = MBX_TOV_SECONDS;
4649 mcp->flags = 0;
4650 rval = qla2x00_mailbox_command(vha, mcp);
4651
4652 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4653 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
4654 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4655 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
ce0423f4 4656 } else {
5f28d2d7
SK		 4657 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
4658 "Done %s.\n", __func__);
7c3df132 4659
ce0423f4
AV		 4660
4661 *actual_size = mcp->mb[2] << 2;
4662 }
4663
4664 return rval;
4665}
11bbc1d8
AV		 4666
4667int
4668qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
4669 uint16_t size)
4670{
4671 int rval;
4672 mbx_cmd_t mc;
4673 mbx_cmd_t *mcp = &mc;
4674
5f28d2d7
SK		 4675 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
4676 "Entered %s.\n", __func__);
7c3df132 4677
6246b8a1 4678 if (!IS_CNA_CAPABLE(vha->hw))
11bbc1d8
AV		 4679 return QLA_FUNCTION_FAILED;
4680
11bbc1d8
AV		 4681 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
4682 mcp->mb[1] = 0;
4683 mcp->mb[2] = MSW(tlv_dma);
4684 mcp->mb[3] = LSW(tlv_dma);
4685 mcp->mb[6] = MSW(MSD(tlv_dma));
4686 mcp->mb[7] = LSW(MSD(tlv_dma));
4687 mcp->mb[8] = size;
4688 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
4689 mcp->in_mb = MBX_2|MBX_1|MBX_0;
4690 mcp->tov = MBX_TOV_SECONDS;
4691 mcp->flags = 0;
4692 rval = qla2x00_mailbox_command(vha, mcp);
4693
4694 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4695 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
4696 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
4697 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
11bbc1d8 4698 } else {
5f28d2d7
SK		 4699 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
4700 "Done %s.\n", __func__);
11bbc1d8
AV		 4701 }
4702
4703 return rval;
4704}
18e7555a
AV		 4705
4706int
4707qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
4708{
4709 int rval;
4710 mbx_cmd_t mc;
4711 mbx_cmd_t *mcp = &mc;
4712
5f28d2d7
SK		 4713 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
4714 "Entered %s.\n", __func__);
7c3df132 4715
18e7555a
AV		 4716 if (!IS_FWI2_CAPABLE(vha->hw))
4717 return QLA_FUNCTION_FAILED;
4718
18e7555a
AV		 4719 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
4720 mcp->mb[1] = LSW(risc_addr);
4721 mcp->mb[8] = MSW(risc_addr);
4722 mcp->out_mb = MBX_8|MBX_1|MBX_0;
4723 mcp->in_mb = MBX_3|MBX_2|MBX_0;
4724 mcp->tov = 30;
4725 mcp->flags = 0;
4726 rval = qla2x00_mailbox_command(vha, mcp);
4727 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4728 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
4729 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4730 } else {
5f28d2d7
SK		 4731 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
4732 "Done %s.\n", __func__);
18e7555a
AV		 4733 *data = mcp->mb[3] << 16 | mcp->mb[2];
4734 }
4735
4736 return rval;
4737}
4738
9a069e19 4739int
a9083016
GM		 4740qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4741 uint16_t *mresp)
9a069e19
GM		 4742{
4743 int rval;
4744 mbx_cmd_t mc;
4745 mbx_cmd_t *mcp = &mc;
9a069e19 4746
5f28d2d7
SK		 4747 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
4748 "Entered %s.\n", __func__);
9a069e19
GM		 4749
4750 memset(mcp->mb, 0 , sizeof(mcp->mb));
4751 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
4752 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
4753
4754 /* transfer count */
4755 mcp->mb[10] = LSW(mreq->transfer_size);
4756 mcp->mb[11] = MSW(mreq->transfer_size);
4757
4758 /* send data address */
4759 mcp->mb[14] = LSW(mreq->send_dma);
4760 mcp->mb[15] = MSW(mreq->send_dma);
4761 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4762 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4763
25985edc 4764 /* receive data address */
9a069e19
GM		 4765 mcp->mb[16] = LSW(mreq->rcv_dma);
4766 mcp->mb[17] = MSW(mreq->rcv_dma);
4767 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4768 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4769
4770 /* Iteration count */
1b98b421
JC		 4771 mcp->mb[18] = LSW(mreq->iteration_count);
4772 mcp->mb[19] = MSW(mreq->iteration_count);
9a069e19
GM		 4773
4774 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
4775 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4776 if (IS_CNA_CAPABLE(vha->hw))
9a069e19
GM		 4777 mcp->out_mb |= MBX_2;
4778 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
4779
4780 mcp->buf_size = mreq->transfer_size;
4781 mcp->tov = MBX_TOV_SECONDS;
4782 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4783
4784 rval = qla2x00_mailbox_command(vha, mcp);
4785
4786 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4787 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
4788 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
4789 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
4790 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
9a069e19 4791 } else {
5f28d2d7
SK		 4792 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
4793 "Done %s.\n", __func__);
9a069e19
GM		 4794 }
4795
4796 /* Copy mailbox information */
4797 memcpy( mresp, mcp->mb, 64);
9a069e19
GM		 4798 return rval;
4799}
4800
4801int
a9083016
GM		 4802qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
4803 uint16_t *mresp)
9a069e19
GM		 4804{
4805 int rval;
4806 mbx_cmd_t mc;
4807 mbx_cmd_t *mcp = &mc;
4808 struct qla_hw_data *ha = vha->hw;
4809
5f28d2d7
SK		 4810 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
4811 "Entered %s.\n", __func__);
9a069e19
GM		 4812
4813 memset(mcp->mb, 0 , sizeof(mcp->mb));
4814 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
1d634965
JC		 4815 /* BIT_6 specifies 64bit address */
4816 mcp->mb[1] = mreq->options | BIT_15 | BIT_6;
6246b8a1 4817 if (IS_CNA_CAPABLE(ha)) {
a9083016
GM		 4818 mcp->mb[2] = vha->fcoe_fcf_idx;
4819 }
9a069e19
GM		 4820 mcp->mb[16] = LSW(mreq->rcv_dma);
4821 mcp->mb[17] = MSW(mreq->rcv_dma);
4822 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
4823 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
4824
4825 mcp->mb[10] = LSW(mreq->transfer_size);
4826
4827 mcp->mb[14] = LSW(mreq->send_dma);
4828 mcp->mb[15] = MSW(mreq->send_dma);
4829 mcp->mb[20] = LSW(MSD(mreq->send_dma));
4830 mcp->mb[21] = MSW(MSD(mreq->send_dma));
4831
4832 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
4833 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
6246b8a1 4834 if (IS_CNA_CAPABLE(ha))
9a069e19
GM		 4835 mcp->out_mb |= MBX_2;
4836
4837 mcp->in_mb = MBX_0;
6246b8a1
GM		 4838 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
4839 IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19 4840 mcp->in_mb |= MBX_1;
6246b8a1 4841 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
9a069e19
GM		 4842 mcp->in_mb |= MBX_3;
4843
4844 mcp->tov = MBX_TOV_SECONDS;
4845 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4846 mcp->buf_size = mreq->transfer_size;
4847
4848 rval = qla2x00_mailbox_command(vha, mcp);
4849
4850 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4851 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
4852 "Failed=%x mb[0]=%x mb[1]=%x.\n",
4853 rval, mcp->mb[0], mcp->mb[1]);
9a069e19 4854 } else {
5f28d2d7
SK		 4855 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
4856 "Done %s.\n", __func__);
9a069e19
GM		 4857 }
4858
4859 /* Copy mailbox information */
6dbdda4d 4860 memcpy(mresp, mcp->mb, 64);
9a069e19
GM		 4861 return rval;
4862}
6dbdda4d 4863
9a069e19 4864int
7c3df132 4865qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
9a069e19
GM		 4866{
4867 int rval;
4868 mbx_cmd_t mc;
4869 mbx_cmd_t *mcp = &mc;
4870
5f28d2d7 4871 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
7c3df132 4872 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
9a069e19
GM		 4873
4874 mcp->mb[0] = MBC_ISP84XX_RESET;
4875 mcp->mb[1] = enable_diagnostic;
4876 mcp->out_mb = MBX_1|MBX_0;
4877 mcp->in_mb = MBX_1|MBX_0;
4878 mcp->tov = MBX_TOV_SECONDS;
4879 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
7c3df132 4880 rval = qla2x00_mailbox_command(vha, mcp);
9a069e19 4881
9a069e19 4882 if (rval != QLA_SUCCESS)
7c3df132 4883 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
9a069e19 4884 else
5f28d2d7
SK		 4885 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
4886 "Done %s.\n", __func__);
9a069e19
GM		 4887
4888 return rval;
4889}
4890
18e7555a
AV		 4891int
4892qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
4893{
4894 int rval;
4895 mbx_cmd_t mc;
4896 mbx_cmd_t *mcp = &mc;
4897
5f28d2d7
SK		 4898 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
4899 "Entered %s.\n", __func__);
7c3df132 4900
18e7555a 4901 if (!IS_FWI2_CAPABLE(vha->hw))
6c452a45 4902 return QLA_FUNCTION_FAILED;
18e7555a 4903
18e7555a
AV		 4904 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
4905 mcp->mb[1] = LSW(risc_addr);
4906 mcp->mb[2] = LSW(data);
4907 mcp->mb[3] = MSW(data);
4908 mcp->mb[8] = MSW(risc_addr);
4909 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
4910 mcp->in_mb = MBX_0;
4911 mcp->tov = 30;
4912 mcp->flags = 0;
4913 rval = qla2x00_mailbox_command(vha, mcp);
4914 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4915 ql_dbg(ql_dbg_mbx, vha, 0x1101,
4916 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
18e7555a 4917 } else {
5f28d2d7
SK		 4918 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
4919 "Done %s.\n", __func__);
18e7555a
AV		 4920 }
4921
4922 return rval;
4923}
3064ff39 4924
b1d46989
MI		 4925int
4926qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
4927{
4928 int rval;
4929 uint32_t stat, timer;
4930 uint16_t mb0 = 0;
4931 struct qla_hw_data *ha = vha->hw;
4932 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4933
4934 rval = QLA_SUCCESS;
4935
5f28d2d7
SK		 4936 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
4937 "Entered %s.\n", __func__);
b1d46989
MI		 4938
4939 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
4940
4941 /* Write the MBC data to the registers */
4942 WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
4943 WRT_REG_WORD(&reg->mailbox1, mb[0]);
4944 WRT_REG_WORD(&reg->mailbox2, mb[1]);
4945 WRT_REG_WORD(&reg->mailbox3, mb[2]);
4946 WRT_REG_WORD(&reg->mailbox4, mb[3]);
4947
4948 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
4949
4950 /* Poll for MBC interrupt */
4951 for (timer = 6000000; timer; timer--) {
4952 /* Check for pending interrupts. */
4953 stat = RD_REG_DWORD(&reg->host_status);
4954 if (stat & HSRX_RISC_INT) {
4955 stat &= 0xff;
4956
4957 if (stat == 0x1 || stat == 0x2 ||
4958 stat == 0x10 || stat == 0x11) {
4959 set_bit(MBX_INTERRUPT,
4960 &ha->mbx_cmd_flags);
4961 mb0 = RD_REG_WORD(&reg->mailbox0);
4962 WRT_REG_DWORD(&reg->hccr,
4963 HCCRX_CLR_RISC_INT);
4964 RD_REG_DWORD(&reg->hccr);
4965 break;
4966 }
4967 }
4968 udelay(5);
4969 }
4970
4971 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
4972 rval = mb0 & MBS_MASK;
4973 else
4974 rval = QLA_FUNCTION_FAILED;
4975
4976 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4977 ql_dbg(ql_dbg_mbx, vha, 0x1104,
4978 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
b1d46989 4979 } else {
5f28d2d7
SK		 4980 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
4981 "Done %s.\n", __func__);
b1d46989
MI		 4982 }
4983
4984 return rval;
4985}
6246b8a1 4986
3064ff39
MH		 4987int
4988qla2x00_get_data_rate(scsi_qla_host_t *vha)
4989{
4990 int rval;
4991 mbx_cmd_t mc;
4992 mbx_cmd_t *mcp = &mc;
4993 struct qla_hw_data *ha = vha->hw;
4994
5f28d2d7
SK		 4995 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
4996 "Entered %s.\n", __func__);
7c3df132 4997
3064ff39
MH		 4998 if (!IS_FWI2_CAPABLE(ha))
4999 return QLA_FUNCTION_FAILED;
5000
3064ff39
MH		 5001 mcp->mb[0] = MBC_DATA_RATE;
5002 mcp->mb[1] = 0;
5003 mcp->out_mb = MBX_1|MBX_0;
5004 mcp->in_mb = MBX_2|MBX_1|MBX_0;
f73cb695 5005 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1 5006 mcp->in_mb |= MBX_3;
3064ff39
MH		 5007 mcp->tov = MBX_TOV_SECONDS;
5008 mcp->flags = 0;
5009 rval = qla2x00_mailbox_command(vha, mcp);
5010 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5011 ql_dbg(ql_dbg_mbx, vha, 0x1107,
5012 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3064ff39 5013 } else {
5f28d2d7
SK		 5014 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5015 "Done %s.\n", __func__);
3064ff39
MH		 5016 if (mcp->mb[1] != 0x7)
5017 ha->link_data_rate = mcp->mb[1];
5018 }
5019
5020 return rval;
5021}
09ff701a 5022
23f2ebd1
SR		 5023int
5024qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5025{
5026 int rval;
5027 mbx_cmd_t mc;
5028 mbx_cmd_t *mcp = &mc;
5029 struct qla_hw_data *ha = vha->hw;
5030
5f28d2d7
SK		 5031 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
5032 "Entered %s.\n", __func__);
23f2ebd1 5033
f73cb695
CD		 5034 if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5035 !IS_QLA27XX(ha))
23f2ebd1
SR		 5036 return QLA_FUNCTION_FAILED;
5037 mcp->mb[0] = MBC_GET_PORT_CONFIG;
5038 mcp->out_mb = MBX_0;
5039 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5040 mcp->tov = MBX_TOV_SECONDS;
5041 mcp->flags = 0;
5042
5043 rval = qla2x00_mailbox_command(vha, mcp);
5044
5045 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5046 ql_dbg(ql_dbg_mbx, vha, 0x110a,
5047 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1
SR		 5048 } else {
5049 /* Copy all bits to preserve original value */
5050 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
5051
5f28d2d7
SK		 5052 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
5053 "Done %s.\n", __func__);
23f2ebd1
SR		 5054 }
5055 return rval;
5056}
5057
5058int
5059qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
5060{
5061 int rval;
5062 mbx_cmd_t mc;
5063 mbx_cmd_t *mcp = &mc;
5064
5f28d2d7
SK		 5065 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
5066 "Entered %s.\n", __func__);
23f2ebd1
SR		 5067
5068 mcp->mb[0] = MBC_SET_PORT_CONFIG;
5069 /* Copy all bits to preserve original setting */
5070 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
5071 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5072 mcp->in_mb = MBX_0;
5073 mcp->tov = MBX_TOV_SECONDS;
5074 mcp->flags = 0;
5075 rval = qla2x00_mailbox_command(vha, mcp);
5076
5077 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5078 ql_dbg(ql_dbg_mbx, vha, 0x110d,
5079 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
23f2ebd1 5080 } else
5f28d2d7
SK		 5081 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
5082 "Done %s.\n", __func__);
23f2ebd1
SR		 5083
5084 return rval;
5085}
5086
5087
09ff701a
SR		 5088int
5089qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
5090 uint16_t *mb)
5091{
5092 int rval;
5093 mbx_cmd_t mc;
5094 mbx_cmd_t *mcp = &mc;
5095 struct qla_hw_data *ha = vha->hw;
5096
5f28d2d7
SK		 5097 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
5098 "Entered %s.\n", __func__);
7c3df132 5099
09ff701a
SR		 5100 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
5101 return QLA_FUNCTION_FAILED;
5102
09ff701a
SR		 5103 mcp->mb[0] = MBC_PORT_PARAMS;
5104 mcp->mb[1] = loop_id;
5105 if (ha->flags.fcp_prio_enabled)
5106 mcp->mb[2] = BIT_1;
5107 else
5108 mcp->mb[2] = BIT_2;
5109 mcp->mb[4] = priority & 0xf;
5110 mcp->mb[9] = vha->vp_idx;
5111 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5112 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5113 mcp->tov = 30;
5114 mcp->flags = 0;
5115 rval = qla2x00_mailbox_command(vha, mcp);
5116 if (mb != NULL) {
5117 mb[0] = mcp->mb[0];
5118 mb[1] = mcp->mb[1];
5119 mb[3] = mcp->mb[3];
5120 mb[4] = mcp->mb[4];
5121 }
5122
5123 if (rval != QLA_SUCCESS) {
7c3df132 5124 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
09ff701a 5125 } else {
5f28d2d7
SK		 5126 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
5127 "Done %s.\n", __func__);
09ff701a
SR		 5128 }
5129
5130 return rval;
5131}
a9083016 5132
794a5691 5133int
fe52f6e1 5134qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
794a5691 5135{
fe52f6e1 5136 int rval = QLA_FUNCTION_FAILED;
794a5691 5137 struct qla_hw_data *ha = vha->hw;
fe52f6e1 5138 uint8_t byte;
794a5691 5139
1ae47cf3
JC		 5140 if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
5141 ql_dbg(ql_dbg_mbx, vha, 0x1150,
5142 "Thermal not supported by this card.\n");
5143 return rval;
5144 }
5145
5146 if (IS_QLA25XX(ha)) {
5147 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
5148 ha->pdev->subsystem_device == 0x0175) {
5149 rval = qla2x00_read_sfp(vha, 0, &byte,
5150 0x98, 0x1, 1, BIT_13|BIT_0);
5151 *temp = byte;
5152 return rval;
5153 }
5154 if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
5155 ha->pdev->subsystem_device == 0x338e) {
5156 rval = qla2x00_read_sfp(vha, 0, &byte,
5157 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
5158 *temp = byte;
5159 return rval;
5160 }
5161 ql_dbg(ql_dbg_mbx, vha, 0x10c9,
5162 "Thermal not supported by this card.\n");
5163 return rval;
794a5691 5164 }
794a5691 5165
1ae47cf3
JC		 5166 if (IS_QLA82XX(ha)) {
5167 *temp = qla82xx_read_temperature(vha);
5168 rval = QLA_SUCCESS;
5169 return rval;
5170 } else if (IS_QLA8044(ha)) {
5171 *temp = qla8044_read_temperature(vha);
5172 rval = QLA_SUCCESS;
5173 return rval;
794a5691 5174 }
794a5691 5175
1ae47cf3 5176 rval = qla2x00_read_asic_temperature(vha, temp);
794a5691
AV		 5177 return rval;
5178}
5179
a9083016
GM		 5180int
5181qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
5182{
5183 int rval;
5184 struct qla_hw_data *ha = vha->hw;
5185 mbx_cmd_t mc;
5186 mbx_cmd_t *mcp = &mc;
5187
5f28d2d7
SK		 5188 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
5189 "Entered %s.\n", __func__);
7c3df132 5190
a9083016
GM		 5191 if (!IS_FWI2_CAPABLE(ha))
5192 return QLA_FUNCTION_FAILED;
5193
a9083016 5194 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5195 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5196 mcp->mb[1] = 1;
5197
5198 mcp->out_mb = MBX_1|MBX_0;
5199 mcp->in_mb = MBX_0;
5200 mcp->tov = 30;
5201 mcp->flags = 0;
5202
5203 rval = qla2x00_mailbox_command(vha, mcp);
5204 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5205 ql_dbg(ql_dbg_mbx, vha, 0x1016,
5206 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5207 } else {
5f28d2d7
SK		 5208 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
5209 "Done %s.\n", __func__);
a9083016
GM		 5210 }
5211
5212 return rval;
5213}
5214
5215int
5216qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
5217{
5218 int rval;
5219 struct qla_hw_data *ha = vha->hw;
5220 mbx_cmd_t mc;
5221 mbx_cmd_t *mcp = &mc;
5222
5f28d2d7
SK		 5223 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
5224 "Entered %s.\n", __func__);
7c3df132 5225
7ec0effd 5226 if (!IS_P3P_TYPE(ha))
a9083016
GM		 5227 return QLA_FUNCTION_FAILED;
5228
a9083016 5229 memset(mcp, 0, sizeof(mbx_cmd_t));
3711333d 5230 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
a9083016
GM		 5231 mcp->mb[1] = 0;
5232
5233 mcp->out_mb = MBX_1|MBX_0;
5234 mcp->in_mb = MBX_0;
5235 mcp->tov = 30;
5236 mcp->flags = 0;
5237
5238 rval = qla2x00_mailbox_command(vha, mcp);
5239 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5240 ql_dbg(ql_dbg_mbx, vha, 0x100c,
5241 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
a9083016 5242 } else {
5f28d2d7
SK		 5243 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
5244 "Done %s.\n", __func__);
a9083016
GM		 5245 }
5246
5247 return rval;
5248}
08de2844
GM		 5249
5250int
5251qla82xx_md_get_template_size(scsi_qla_host_t *vha)
5252{
5253 struct qla_hw_data *ha = vha->hw;
5254 mbx_cmd_t mc;
5255 mbx_cmd_t *mcp = &mc;
5256 int rval = QLA_FUNCTION_FAILED;
5257
5f28d2d7
SK		 5258 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
5259 "Entered %s.\n", __func__);
08de2844
GM		 5260
5261 memset(mcp->mb, 0 , sizeof(mcp->mb));
5262 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5263 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5264 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
5265 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
5266
5267 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5268 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
5269 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5270
5271 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5272 mcp->tov = MBX_TOV_SECONDS;
5273 rval = qla2x00_mailbox_command(vha, mcp);
5274
5275 /* Always copy back return mailbox values. */
5276 if (rval != QLA_SUCCESS) {
5277 ql_dbg(ql_dbg_mbx, vha, 0x1120,
5278 "mailbox command FAILED=0x%x, subcode=%x.\n",
5279 (mcp->mb[1] << 16) | mcp->mb[0],
5280 (mcp->mb[3] << 16) | mcp->mb[2]);
5281 } else {
5f28d2d7
SK		 5282 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
5283 "Done %s.\n", __func__);
08de2844
GM		 5284 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
5285 if (!ha->md_template_size) {
5286 ql_dbg(ql_dbg_mbx, vha, 0x1122,
5287 "Null template size obtained.\n");
5288 rval = QLA_FUNCTION_FAILED;
5289 }
5290 }
5291 return rval;
5292}
5293
5294int
5295qla82xx_md_get_template(scsi_qla_host_t *vha)
5296{
5297 struct qla_hw_data *ha = vha->hw;
5298 mbx_cmd_t mc;
5299 mbx_cmd_t *mcp = &mc;
5300 int rval = QLA_FUNCTION_FAILED;
5301
5f28d2d7
SK		 5302 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
5303 "Entered %s.\n", __func__);
08de2844
GM		 5304
5305 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5306 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5307 if (!ha->md_tmplt_hdr) {
5308 ql_log(ql_log_warn, vha, 0x1124,
5309 "Unable to allocate memory for Minidump template.\n");
5310 return rval;
5311 }
5312
5313 memset(mcp->mb, 0 , sizeof(mcp->mb));
5314 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5315 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5316 mcp->mb[2] = LSW(RQST_TMPLT);
5317 mcp->mb[3] = MSW(RQST_TMPLT);
5318 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
5319 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
5320 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
5321 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
5322 mcp->mb[8] = LSW(ha->md_template_size);
5323 mcp->mb[9] = MSW(ha->md_template_size);
5324
5325 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5326 mcp->tov = MBX_TOV_SECONDS;
5327 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5328 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5329 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5330 rval = qla2x00_mailbox_command(vha, mcp);
5331
5332 if (rval != QLA_SUCCESS) {
5333 ql_dbg(ql_dbg_mbx, vha, 0x1125,
5334 "mailbox command FAILED=0x%x, subcode=%x.\n",
5335 ((mcp->mb[1] << 16) | mcp->mb[0]),
5336 ((mcp->mb[3] << 16) | mcp->mb[2]));
5337 } else
5f28d2d7
SK		 5338 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
5339 "Done %s.\n", __func__);
08de2844
GM		 5340 return rval;
5341}
999916dc 5342
7ec0effd
AD		 5343int
5344qla8044_md_get_template(scsi_qla_host_t *vha)
5345{
5346 struct qla_hw_data *ha = vha->hw;
5347 mbx_cmd_t mc;
5348 mbx_cmd_t *mcp = &mc;
5349 int rval = QLA_FUNCTION_FAILED;
5350 int offset = 0, size = MINIDUMP_SIZE_36K;
5351 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5352 "Entered %s.\n", __func__);
5353
5354 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
5355 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
5356 if (!ha->md_tmplt_hdr) {
5357 ql_log(ql_log_warn, vha, 0xb11b,
5358 "Unable to allocate memory for Minidump template.\n");
5359 return rval;
5360 }
5361
5362 memset(mcp->mb, 0 , sizeof(mcp->mb));
5363 while (offset < ha->md_template_size) {
5364 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5365 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
5366 mcp->mb[2] = LSW(RQST_TMPLT);
5367 mcp->mb[3] = MSW(RQST_TMPLT);
5368 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
5369 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
5370 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
5371 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
5372 mcp->mb[8] = LSW(size);
5373 mcp->mb[9] = MSW(size);
5374 mcp->mb[10] = offset & 0x0000FFFF;
5375 mcp->mb[11] = offset & 0xFFFF0000;
5376 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
5377 mcp->tov = MBX_TOV_SECONDS;
5378 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
5379 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5380 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5381 rval = qla2x00_mailbox_command(vha, mcp);
5382
5383 if (rval != QLA_SUCCESS) {
5384 ql_dbg(ql_dbg_mbx, vha, 0xb11c,
5385 "mailbox command FAILED=0x%x, subcode=%x.\n",
5386 ((mcp->mb[1] << 16) | mcp->mb[0]),
5387 ((mcp->mb[3] << 16) | mcp->mb[2]));
5388 return rval;
5389 } else
5390 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
5391 "Done %s.\n", __func__);
5392 offset = offset + size;
5393 }
5394 return rval;
5395}
5396
6246b8a1
GM		 5397int
5398qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5399{
5400 int rval;
5401 struct qla_hw_data *ha = vha->hw;
5402 mbx_cmd_t mc;
5403 mbx_cmd_t *mcp = &mc;
5404
5405 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5406 return QLA_FUNCTION_FAILED;
5407
5f28d2d7
SK		 5408 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
5409 "Entered %s.\n", __func__);
6246b8a1
GM		 5410
5411 memset(mcp, 0, sizeof(mbx_cmd_t));
5412 mcp->mb[0] = MBC_SET_LED_CONFIG;
5413 mcp->mb[1] = led_cfg[0];
5414 mcp->mb[2] = led_cfg[1];
5415 if (IS_QLA8031(ha)) {
5416 mcp->mb[3] = led_cfg[2];
5417 mcp->mb[4] = led_cfg[3];
5418 mcp->mb[5] = led_cfg[4];
5419 mcp->mb[6] = led_cfg[5];
5420 }
5421
5422 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5423 if (IS_QLA8031(ha))
5424 mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5425 mcp->in_mb = MBX_0;
5426 mcp->tov = 30;
5427 mcp->flags = 0;
5428
5429 rval = qla2x00_mailbox_command(vha, mcp);
5430 if (rval != QLA_SUCCESS) {
5431 ql_dbg(ql_dbg_mbx, vha, 0x1134,
5432 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5433 } else {
5f28d2d7
SK		 5434 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
5435 "Done %s.\n", __func__);
6246b8a1
GM		 5436 }
5437
5438 return rval;
5439}
5440
5441int
5442qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
5443{
5444 int rval;
5445 struct qla_hw_data *ha = vha->hw;
5446 mbx_cmd_t mc;
5447 mbx_cmd_t *mcp = &mc;
5448
5449 if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
5450 return QLA_FUNCTION_FAILED;
5451
5f28d2d7
SK		 5452 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
5453 "Entered %s.\n", __func__);
6246b8a1
GM		 5454
5455 memset(mcp, 0, sizeof(mbx_cmd_t));
5456 mcp->mb[0] = MBC_GET_LED_CONFIG;
5457
5458 mcp->out_mb = MBX_0;
5459 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5460 if (IS_QLA8031(ha))
5461 mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
5462 mcp->tov = 30;
5463 mcp->flags = 0;
5464
5465 rval = qla2x00_mailbox_command(vha, mcp);
5466 if (rval != QLA_SUCCESS) {
5467 ql_dbg(ql_dbg_mbx, vha, 0x1137,
5468 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5469 } else {
5470 led_cfg[0] = mcp->mb[1];
5471 led_cfg[1] = mcp->mb[2];
5472 if (IS_QLA8031(ha)) {
5473 led_cfg[2] = mcp->mb[3];
5474 led_cfg[3] = mcp->mb[4];
5475 led_cfg[4] = mcp->mb[5];
5476 led_cfg[5] = mcp->mb[6];
5477 }
5f28d2d7
SK		 5478 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
5479 "Done %s.\n", __func__);
6246b8a1
GM		 5480 }
5481
5482 return rval;
5483}
5484
999916dc
SK		 5485int
5486qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
5487{
5488 int rval;
5489 struct qla_hw_data *ha = vha->hw;
5490 mbx_cmd_t mc;
5491 mbx_cmd_t *mcp = &mc;
5492
7ec0effd 5493 if (!IS_P3P_TYPE(ha))
999916dc
SK		 5494 return QLA_FUNCTION_FAILED;
5495
5f28d2d7 5496 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
999916dc
SK		 5497 "Entered %s.\n", __func__);
5498
5499 memset(mcp, 0, sizeof(mbx_cmd_t));
5500 mcp->mb[0] = MBC_SET_LED_CONFIG;
5501 if (enable)
5502 mcp->mb[7] = 0xE;
5503 else
5504 mcp->mb[7] = 0xD;
5505
5506 mcp->out_mb = MBX_7|MBX_0;
5507 mcp->in_mb = MBX_0;
6246b8a1 5508 mcp->tov = MBX_TOV_SECONDS;
999916dc
SK		 5509 mcp->flags = 0;
5510
5511 rval = qla2x00_mailbox_command(vha, mcp);
5512 if (rval != QLA_SUCCESS) {
5513 ql_dbg(ql_dbg_mbx, vha, 0x1128,
5514 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5515 } else {
5f28d2d7 5516 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
999916dc
SK		 5517 "Done %s.\n", __func__);
5518 }
5519
5520 return rval;
5521}
6246b8a1
GM		 5522
5523int
7d613ac6 5524qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
6246b8a1
GM		 5525{
5526 int rval;
5527 struct qla_hw_data *ha = vha->hw;
5528 mbx_cmd_t mc;
5529 mbx_cmd_t *mcp = &mc;
5530
f73cb695 5531 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1
GM		 5532 return QLA_FUNCTION_FAILED;
5533
5f28d2d7
SK		 5534 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
5535 "Entered %s.\n", __func__);
6246b8a1
GM		 5536
5537 mcp->mb[0] = MBC_WRITE_REMOTE_REG;
5538 mcp->mb[1] = LSW(reg);
5539 mcp->mb[2] = MSW(reg);
5540 mcp->mb[3] = LSW(data);
5541 mcp->mb[4] = MSW(data);
5542 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
5543
5544 mcp->in_mb = MBX_1|MBX_0;
5545 mcp->tov = MBX_TOV_SECONDS;
5546 mcp->flags = 0;
5547 rval = qla2x00_mailbox_command(vha, mcp);
5548
5549 if (rval != QLA_SUCCESS) {
5550 ql_dbg(ql_dbg_mbx, vha, 0x1131,
5551 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5552 } else {
5f28d2d7 5553 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
6246b8a1
GM		 5554 "Done %s.\n", __func__);
5555 }
af11f64d 5556
6246b8a1
GM		 5557 return rval;
5558}
af11f64d
AV		 5559
5560int
5561qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
5562{
5563 int rval;
5564 struct qla_hw_data *ha = vha->hw;
5565 mbx_cmd_t mc;
5566 mbx_cmd_t *mcp = &mc;
5567
5568 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
5f28d2d7 5569 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
af11f64d
AV		 5570 "Implicit LOGO Unsupported.\n");
5571 return QLA_FUNCTION_FAILED;
5572 }
5573
5574
5f28d2d7
SK		 5575 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
5576 "Entering %s.\n", __func__);
af11f64d
AV		 5577
5578 /* Perform Implicit LOGO. */
5579 mcp->mb[0] = MBC_PORT_LOGOUT;
5580 mcp->mb[1] = fcport->loop_id;
5581 mcp->mb[10] = BIT_15;
5582 mcp->out_mb = MBX_10|MBX_1|MBX_0;
5583 mcp->in_mb = MBX_0;
5584 mcp->tov = MBX_TOV_SECONDS;
5585 mcp->flags = 0;
5586 rval = qla2x00_mailbox_command(vha, mcp);
5587 if (rval != QLA_SUCCESS)
5588 ql_dbg(ql_dbg_mbx, vha, 0x113d,
5589 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5590 else
5f28d2d7
SK		 5591 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
5592 "Done %s.\n", __func__);
af11f64d
AV		 5593
5594 return rval;
5595}
5596
7d613ac6
SV		 5597int
5598qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
5599{
5600 int rval;
5601 mbx_cmd_t mc;
5602 mbx_cmd_t *mcp = &mc;
5603 struct qla_hw_data *ha = vha->hw;
5604 unsigned long retry_max_time = jiffies + (2 * HZ);
5605
f73cb695 5606 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5607 return QLA_FUNCTION_FAILED;
5608
5609 ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
5610
5611retry_rd_reg:
5612 mcp->mb[0] = MBC_READ_REMOTE_REG;
5613 mcp->mb[1] = LSW(reg);
5614 mcp->mb[2] = MSW(reg);
5615 mcp->out_mb = MBX_2|MBX_1|MBX_0;
5616 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
5617 mcp->tov = MBX_TOV_SECONDS;
5618 mcp->flags = 0;
5619 rval = qla2x00_mailbox_command(vha, mcp);
5620
5621 if (rval != QLA_SUCCESS) {
5622 ql_dbg(ql_dbg_mbx, vha, 0x114c,
5623 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5624 rval, mcp->mb[0], mcp->mb[1]);
5625 } else {
5626 *data = (mcp->mb[3] | (mcp->mb[4] << 16));
5627 if (*data == QLA8XXX_BAD_VALUE) {
5628 /*
5629 * During soft-reset CAMRAM register reads might
5630 * return 0xbad0bad0. So retry for MAX of 2 sec
5631 * while reading camram registers.
5632 */
5633 if (time_after(jiffies, retry_max_time)) {
5634 ql_dbg(ql_dbg_mbx, vha, 0x1141,
5635 "Failure to read CAMRAM register. "
5636 "data=0x%x.\n", *data);
5637 return QLA_FUNCTION_FAILED;
5638 }
5639 msleep(100);
5640 goto retry_rd_reg;
5641 }
5642 ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
5643 }
5644
5645 return rval;
5646}
5647
5648int
5649qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
5650{
5651 int rval;
5652 mbx_cmd_t mc;
5653 mbx_cmd_t *mcp = &mc;
5654 struct qla_hw_data *ha = vha->hw;
5655
b20f02e1 5656 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
7d613ac6
SV		 5657 return QLA_FUNCTION_FAILED;
5658
5659 ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
5660
5661 mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
5662 mcp->out_mb = MBX_0;
5663 mcp->in_mb = MBX_1|MBX_0;
5664 mcp->tov = MBX_TOV_SECONDS;
5665 mcp->flags = 0;
5666 rval = qla2x00_mailbox_command(vha, mcp);
5667
5668 if (rval != QLA_SUCCESS) {
5669 ql_dbg(ql_dbg_mbx, vha, 0x1144,
5670 "Failed=%x mb[0]=%x mb[1]=%x.\n",
5671 rval, mcp->mb[0], mcp->mb[1]);
5672 ha->isp_ops->fw_dump(vha, 0);
5673 } else {
5674 ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5675 }
5676
5677 return rval;
5678}
5679
5680int
5681qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
5682 uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
5683{
5684 int rval;
5685 mbx_cmd_t mc;
5686 mbx_cmd_t *mcp = &mc;
5687 uint8_t subcode = (uint8_t)options;
5688 struct qla_hw_data *ha = vha->hw;
5689
5690 if (!IS_QLA8031(ha))
5691 return QLA_FUNCTION_FAILED;
5692
5693 ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
5694
5695 mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
5696 mcp->mb[1] = options;
5697 mcp->out_mb = MBX_1|MBX_0;
5698 if (subcode & BIT_2) {
5699 mcp->mb[2] = LSW(start_addr);
5700 mcp->mb[3] = MSW(start_addr);
5701 mcp->mb[4] = LSW(end_addr);
5702 mcp->mb[5] = MSW(end_addr);
5703 mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
5704 }
5705 mcp->in_mb = MBX_2|MBX_1|MBX_0;
5706 if (!(subcode & (BIT_2 | BIT_5)))
5707 mcp->in_mb |= MBX_4|MBX_3;
5708 mcp->tov = MBX_TOV_SECONDS;
5709 mcp->flags = 0;
5710 rval = qla2x00_mailbox_command(vha, mcp);
5711
5712 if (rval != QLA_SUCCESS) {
5713 ql_dbg(ql_dbg_mbx, vha, 0x1147,
5714 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5715 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5716 mcp->mb[4]);
5717 ha->isp_ops->fw_dump(vha, 0);
5718 } else {
5719 if (subcode & BIT_5)
5720 *sector_size = mcp->mb[1];
5721 else if (subcode & (BIT_6 | BIT_7)) {
5722 ql_dbg(ql_dbg_mbx, vha, 0x1148,
5723 "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5724 } else if (subcode & (BIT_3 | BIT_4)) {
5725 ql_dbg(ql_dbg_mbx, vha, 0x1149,
5726 "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
5727 }
5728 ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
5729 }
5730
5731 return rval;
5732}
81178772
SK		 5733
5734int
5735qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
5736 uint32_t size)
5737{
5738 int rval;
5739 mbx_cmd_t mc;
5740 mbx_cmd_t *mcp = &mc;
5741
5742 if (!IS_MCTP_CAPABLE(vha->hw))
5743 return QLA_FUNCTION_FAILED;
5744
5745 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
5746 "Entered %s.\n", __func__);
5747
5748 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
5749 mcp->mb[1] = LSW(addr);
5750 mcp->mb[2] = MSW(req_dma);
5751 mcp->mb[3] = LSW(req_dma);
5752 mcp->mb[4] = MSW(size);
5753 mcp->mb[5] = LSW(size);
5754 mcp->mb[6] = MSW(MSD(req_dma));
5755 mcp->mb[7] = LSW(MSD(req_dma));
5756 mcp->mb[8] = MSW(addr);
5757 /* Setting RAM ID to valid */
5758 mcp->mb[10] |= BIT_7;
5759 /* For MCTP RAM ID is 0x40 */
5760 mcp->mb[10] |= 0x40;
5761
5762 mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
5763 MBX_0;
5764
5765 mcp->in_mb = MBX_0;
5766 mcp->tov = MBX_TOV_SECONDS;
5767 mcp->flags = 0;
5768 rval = qla2x00_mailbox_command(vha, mcp);
5769
5770 if (rval != QLA_SUCCESS) {
5771 ql_dbg(ql_dbg_mbx, vha, 0x114e,
5772 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5773 } else {
5774 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
5775 "Done %s.\n", __func__);
5776 }
5777
5778 return rval;
5779}
ec891462
JC		 5780
5781int
5782qla26xx_dport_diagnostics(scsi_qla_host_t *vha,
5783 void *dd_buf, uint size, uint options)
5784{
5785 int rval;
5786 mbx_cmd_t mc;
5787 mbx_cmd_t *mcp = &mc;
5788 dma_addr_t dd_dma;
5789
5790 if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
5791 return QLA_FUNCTION_FAILED;
5792
5793 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1192,
5794 "Entered %s.\n", __func__);
5795
ec891462
JC		 5796 dd_dma = dma_map_single(&vha->hw->pdev->dev,
5797 dd_buf, size, DMA_FROM_DEVICE);
5798 if (!dd_dma) {
5799 ql_log(ql_log_warn, vha, 0x1194, "Failed to map dma buffer.\n");
5800 return QLA_MEMORY_ALLOC_FAILED;
5801 }
5802
5803 memset(dd_buf, 0, size);
5804
5805 mcp->mb[0] = MBC_DPORT_DIAGNOSTICS;
5806 mcp->mb[1] = options;
5807 mcp->mb[2] = MSW(LSD(dd_dma));
5808 mcp->mb[3] = LSW(LSD(dd_dma));
5809 mcp->mb[6] = MSW(MSD(dd_dma));
5810 mcp->mb[7] = LSW(MSD(dd_dma));
5811 mcp->mb[8] = size;
5812 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
5813 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
5814 mcp->buf_size = size;
5815 mcp->flags = MBX_DMA_IN;
5816 mcp->tov = MBX_TOV_SECONDS * 4;
5817 rval = qla2x00_mailbox_command(vha, mcp);
5818
5819 if (rval != QLA_SUCCESS) {
5820 ql_dbg(ql_dbg_mbx, vha, 0x1195, "Failed=%x.\n", rval);
5821 } else {
5822 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1196,
5823 "Done %s.\n", __func__);
5824 }
5825
5826 dma_unmap_single(&vha->hw->pdev->dev, dd_dma,
5827 size, DMA_FROM_DEVICE);
5828
5829 return rval;
5830}
15f30a57
QT		 5831
5832static void qla2x00_async_mb_sp_done(void *s, int res)
5833{
5834 struct srb *sp = s;
5835
5836 sp->u.iocb_cmd.u.mbx.rc = res;
5837
5838 complete(&sp->u.iocb_cmd.u.mbx.comp);
5839 /* don't free sp here. Let the caller do the free */
5840}
5841
5842/*
5843 * This mailbox uses the iocb interface to send MB command.
5844 * This allows non-critial (non chip setup) command to go
5845 * out in parrallel.
5846 */
5847int qla24xx_send_mb_cmd(struct scsi_qla_host *vha, mbx_cmd_t *mcp)
5848{
5849 int rval = QLA_FUNCTION_FAILED;
5850 srb_t *sp;
5851 struct srb_iocb *c;
5852
5853 if (!vha->hw->flags.fw_started)
5854 goto done;
5855
5856 sp = qla2x00_get_sp(vha, NULL, GFP_KERNEL);
5857 if (!sp)
5858 goto done;
5859
5860 sp->type = SRB_MB_IOCB;
5861 sp->name = mb_to_str(mcp->mb[0]);
5862
5863 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
5864
5865 memcpy(sp->u.iocb_cmd.u.mbx.out_mb, mcp->mb, SIZEOF_IOCB_MB_REG);
5866
5867 c = &sp->u.iocb_cmd;
5868 c->timeout = qla2x00_async_iocb_timeout;
5869 init_completion(&c->u.mbx.comp);
5870
5871 sp->done = qla2x00_async_mb_sp_done;
5872
5873 rval = qla2x00_start_sp(sp);
5874 if (rval != QLA_SUCCESS) {
5875 ql_dbg(ql_dbg_mbx, vha, 0xffff,
5876 "%s: %s Failed submission. %x.\n",
5877 __func__, sp->name, rval);
5878 goto done_free_sp;
5879 }
5880
5881 ql_dbg(ql_dbg_mbx, vha, 0xffff, "MB:%s hndl %x submitted\n",
5882 sp->name, sp->handle);
5883
5884 wait_for_completion(&c->u.mbx.comp);
5885 memcpy(mcp->mb, sp->u.iocb_cmd.u.mbx.in_mb, SIZEOF_IOCB_MB_REG);
5886
5887 rval = c->u.mbx.rc;
5888 switch (rval) {
5889 case QLA_FUNCTION_TIMEOUT:
5890 ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s: %s Timeout. %x.\n",
5891 __func__, sp->name, rval);
5892 break;
5893 case QLA_SUCCESS:
5894 ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s: %s done.\n",
5895 __func__, sp->name);
5896 sp->free(sp);
5897 break;
5898 default:
5899 ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s: %s Failed. %x.\n",
5900 __func__, sp->name, rval);
5901 sp->free(sp);
5902 break;
5903 }
5904
5905 return rval;
5906
5907done_free_sp:
5908 sp->free(sp);
5909done:
5910 return rval;
5911}
5912
5913/*
5914 * qla24xx_gpdb_wait
5915 * NOTE: Do not call this routine from DPC thread
5916 */
5917int qla24xx_gpdb_wait(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
5918{
5919 int rval = QLA_FUNCTION_FAILED;
5920 dma_addr_t pd_dma;
5921 struct port_database_24xx *pd;
5922 struct qla_hw_data *ha = vha->hw;
5923 mbx_cmd_t mc;
5924
5925 if (!vha->hw->flags.fw_started)
5926 goto done;
5927
5928 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
5929 if (pd == NULL) {
5930 ql_log(ql_log_warn, vha, 0xffff,
5931 "Failed to allocate port database structure.\n");
5932 goto done_free_sp;
5933 }
5934 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
5935
5936 memset(&mc, 0, sizeof(mc));
5937 mc.mb[0] = MBC_GET_PORT_DATABASE;
5938 mc.mb[1] = cpu_to_le16(fcport->loop_id);
5939 mc.mb[2] = MSW(pd_dma);
5940 mc.mb[3] = LSW(pd_dma);
5941 mc.mb[6] = MSW(MSD(pd_dma));
5942 mc.mb[7] = LSW(MSD(pd_dma));
5943 mc.mb[9] = cpu_to_le16(vha->vp_idx);
5944 mc.mb[10] = cpu_to_le16((uint16_t)opt);
5945
5946 rval = qla24xx_send_mb_cmd(vha, &mc);
5947 if (rval != QLA_SUCCESS) {
5948 ql_dbg(ql_dbg_mbx, vha, 0xffff,
5949 "%s: %8phC fail\n", __func__, fcport->port_name);
5950 goto done_free_sp;
5951 }
5952
5953 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
5954
5955 ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s: %8phC done\n",
5956 __func__, fcport->port_name);
5957
5958done_free_sp:
5959 if (pd)
5960 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
5961done:
5962 return rval;
5963}
5964
5965int __qla24xx_parse_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport,
5966 struct port_database_24xx *pd)
5967{
5968 int rval = QLA_SUCCESS;
5969 uint64_t zero = 0;
5970
5971 /* Check for logged in state. */
5972 if (pd->current_login_state != PDS_PRLI_COMPLETE &&
5973 pd->last_login_state != PDS_PRLI_COMPLETE) {
5974 ql_dbg(ql_dbg_mbx, vha, 0xffff,
5975 "Unable to verify login-state (%x/%x) for "
5976 "loop_id %x.\n", pd->current_login_state,
5977 pd->last_login_state, fcport->loop_id);
5978 rval = QLA_FUNCTION_FAILED;
5979 goto gpd_error_out;
5980 }
5981
5982 if (fcport->loop_id == FC_NO_LOOP_ID ||
5983 (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
5984 memcmp(fcport->port_name, pd->port_name, 8))) {
5985 /* We lost the device mid way. */
5986 rval = QLA_NOT_LOGGED_IN;
5987 goto gpd_error_out;
5988 }
5989
5990 /* Names are little-endian. */
5991 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
5992 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
5993
5994 /* Get port_id of device. */
5995 fcport->d_id.b.domain = pd->port_id[0];
5996 fcport->d_id.b.area = pd->port_id[1];
5997 fcport->d_id.b.al_pa = pd->port_id[2];
5998 fcport->d_id.b.rsvd_1 = 0;
5999
6000 /* If not target must be initiator or unknown type. */
6001 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
6002 fcport->port_type = FCT_INITIATOR;
6003 else
6004 fcport->port_type = FCT_TARGET;
6005
6006 /* Passback COS information. */
6007 fcport->supported_classes = (pd->flags & PDF_CLASS_2) ?
6008 FC_COS_CLASS2 : FC_COS_CLASS3;
6009
6010 if (pd->prli_svc_param_word_3[0] & BIT_7) {
6011 fcport->flags |= FCF_CONF_COMP_SUPPORTED;
6012 fcport->conf_compl_supported = 1;
6013 }
6014
6015gpd_error_out:
6016 return rval;
6017}
6018
6019/*
6020 * qla24xx_gidlist__wait
6021 * NOTE: don't call this routine from DPC thread.
6022 */
6023int qla24xx_gidlist_wait(struct scsi_qla_host *vha,
6024 void *id_list, dma_addr_t id_list_dma, uint16_t *entries)
6025{
6026 int rval = QLA_FUNCTION_FAILED;
6027 mbx_cmd_t mc;
6028
6029 if (!vha->hw->flags.fw_started)
6030 goto done;
6031
6032 memset(&mc, 0, sizeof(mc));
6033 mc.mb[0] = MBC_GET_ID_LIST;
6034 mc.mb[2] = MSW(id_list_dma);
6035 mc.mb[3] = LSW(id_list_dma);
6036 mc.mb[6] = MSW(MSD(id_list_dma));
6037 mc.mb[7] = LSW(MSD(id_list_dma));
6038 mc.mb[8] = 0;
6039 mc.mb[9] = cpu_to_le16(vha->vp_idx);
6040
6041 rval = qla24xx_send_mb_cmd(vha, &mc);
6042 if (rval != QLA_SUCCESS) {
6043 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6044 "%s: fail\n", __func__);
6045 } else {
6046 *entries = mc.mb[1];
6047 ql_dbg(ql_dbg_mbx, vha, 0xffff,
6048 "%s: done\n", __func__);
6049 }
6050done:
6051 return rval;
6052}