projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] qla2xxx: Set Maximum Read Request Size to 4K.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_init_rings(scsi_qla_host_t *);
29static int qla2x00_fw_ready(scsi_qla_host_t *);
30static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 31static int qla2x00_configure_loop(scsi_qla_host_t *);
32static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4
LT		 33static int qla2x00_configure_fabric(scsi_qla_host_t *);
34static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
1da177e4
LT		 35static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
1da177e4
LT		 37
38static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 39
4d4df193
HK		 40static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 42static int qla25xx_init_queues(struct qla_hw_data *);
4d4df193 43
ac280b67
AV		 44/* SRB Extensions ---------------------------------------------------------- */
45
9ba56b95
GM		 46void
47qla2x00_sp_timeout(unsigned long __data)
ac280b67
AV		 48{
49 srb_t *sp = (srb_t *)__data;
4916392b 50 struct srb_iocb *iocb;
ac280b67
AV		 51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
9ba56b95 61 sp->free(fcport->vha, sp);
6ac52608 62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95
GM		 65void
66qla2x00_sp_free(void *data, void *ptr)
ac280b67 67{
9ba56b95
GM		 68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
ac280b67 71
4d97cc53 72 del_timer(&iocb->timer);
9ba56b95 73 mempool_free(sp, vha->hw->srb_mempool);
feafb7b1
AE		 74
75 QLA_VHA_MARK_NOT_BUSY(vha);
ac280b67
AV		 76}
77
ac280b67
AV		 78/* Asynchronous Login/Logout Routines -------------------------------------- */
79
a9b6f722 80unsigned long
5b91490e
AV		 81qla2x00_get_async_timeout(struct scsi_qla_host *vha)
82{
83 unsigned long tmo;
84 struct qla_hw_data *ha = vha->hw;
85
86 /* Firmware should use switch negotiated r_a_tov for timeout. */
87 tmo = ha->r_a_tov / 10 * 2;
88 if (!IS_FWI2_CAPABLE(ha)) {
89 /*
90 * Except for earlier ISPs where the timeout is seeded from the
91 * initialization control block.
92 */
93 tmo = ha->login_timeout;
94 }
95 return tmo;
96}
ac280b67
AV		 97
98static void
9ba56b95 99qla2x00_async_iocb_timeout(void *data)
ac280b67 100{
9ba56b95 101 srb_t *sp = (srb_t *)data;
ac280b67 102 fc_port_t *fcport = sp->fcport;
ac280b67 103
7c3df132 104 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
cfb0919c 105 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
9ba56b95 106 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
7c3df132 107 fcport->d_id.b.al_pa);
ac280b67 108
5ff1d584 109 fcport->flags &= ~FCF_ASYNC_SENT;
9ba56b95
GM		 110 if (sp->type == SRB_LOGIN_CMD) {
111 struct srb_iocb *lio = &sp->u.iocb_cmd;
ac280b67 112 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
6ac52608
AV		 113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
117 qla2x00_post_async_login_done_work(fcport->vha, fcport,
118 lio->u.logio.data);
119 }
ac280b67
AV		 120}
121
99b0bec7 122static void
9ba56b95 123qla2x00_async_login_sp_done(void *data, void *ptr, int res)
99b0bec7 124{
9ba56b95
GM		 125 srb_t *sp = (srb_t *)ptr;
126 struct srb_iocb *lio = &sp->u.iocb_cmd;
127 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
128
129 if (!test_bit(UNLOADING, &vha->dpc_flags))
130 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
131 lio->u.logio.data);
132 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 133}
134
ac280b67
AV		 135int
136qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
137 uint16_t *data)
138{
ac280b67 139 srb_t *sp;
4916392b 140 struct srb_iocb *lio;
ac280b67
AV		 141 int rval;
142
143 rval = QLA_FUNCTION_FAILED;
9ba56b95 144 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 145 if (!sp)
146 goto done;
147
9ba56b95
GM		 148 sp->type = SRB_LOGIN_CMD;
149 sp->name = "login";
150 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
151
152 lio = &sp->u.iocb_cmd;
3822263e 153 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 154 sp->done = qla2x00_async_login_sp_done;
4916392b 155 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
ac280b67 156 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 157 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67
AV		 158 rval = qla2x00_start_sp(sp);
159 if (rval != QLA_SUCCESS)
160 goto done_free_sp;
161
7c3df132 162 ql_dbg(ql_dbg_disc, vha, 0x2072,
cfb0919c
CD		 163 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
164 "retries=%d.\n", sp->handle, fcport->loop_id,
165 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
166 fcport->login_retry);
ac280b67
AV		 167 return rval;
168
169done_free_sp:
9ba56b95 170 sp->free(fcport->vha, sp);
ac280b67
AV		 171done:
172 return rval;
173}
174
99b0bec7 175static void
9ba56b95 176qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
99b0bec7 177{
9ba56b95
GM		 178 srb_t *sp = (srb_t *)ptr;
179 struct srb_iocb *lio = &sp->u.iocb_cmd;
180 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
181
182 if (!test_bit(UNLOADING, &vha->dpc_flags))
183 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
184 lio->u.logio.data);
185 sp->free(sp->fcport->vha, sp);
99b0bec7
AV		 186}
187
ac280b67
AV		 188int
189qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
190{
ac280b67 191 srb_t *sp;
4916392b 192 struct srb_iocb *lio;
ac280b67
AV		 193 int rval;
194
195 rval = QLA_FUNCTION_FAILED;
9ba56b95 196 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 197 if (!sp)
198 goto done;
199
9ba56b95
GM		 200 sp->type = SRB_LOGOUT_CMD;
201 sp->name = "logout";
202 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
203
204 lio = &sp->u.iocb_cmd;
3822263e 205 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 206 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 207 rval = qla2x00_start_sp(sp);
208 if (rval != QLA_SUCCESS)
209 goto done_free_sp;
210
7c3df132 211 ql_dbg(ql_dbg_disc, vha, 0x2070,
cfb0919c
CD		 212 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
213 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
214 fcport->d_id.b.area, fcport->d_id.b.al_pa);
ac280b67
AV		 215 return rval;
216
217done_free_sp:
9ba56b95 218 sp->free(fcport->vha, sp);
ac280b67
AV		 219done:
220 return rval;
221}
222
5ff1d584 223static void
9ba56b95 224qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
5ff1d584 225{
9ba56b95
GM		 226 srb_t *sp = (srb_t *)ptr;
227 struct srb_iocb *lio = &sp->u.iocb_cmd;
228 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
229
230 if (!test_bit(UNLOADING, &vha->dpc_flags))
231 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
232 lio->u.logio.data);
233 sp->free(sp->fcport->vha, sp);
5ff1d584
AV		 234}
235
236int
237qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
238 uint16_t *data)
239{
5ff1d584 240 srb_t *sp;
4916392b 241 struct srb_iocb *lio;
5ff1d584
AV		 242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
9ba56b95 245 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 246 if (!sp)
247 goto done;
248
9ba56b95
GM		 249 sp->type = SRB_ADISC_CMD;
250 sp->name = "adisc";
251 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
252
253 lio = &sp->u.iocb_cmd;
3822263e 254 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 255 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 256 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 257 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 258 rval = qla2x00_start_sp(sp);
259 if (rval != QLA_SUCCESS)
260 goto done_free_sp;
261
7c3df132 262 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 263 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
264 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
265 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 266 return rval;
267
268done_free_sp:
9ba56b95 269 sp->free(fcport->vha, sp);
5ff1d584
AV		 270done:
271 return rval;
272}
273
3822263e 274static void
9ba56b95 275qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
3822263e 276{
9ba56b95
GM		 277 srb_t *sp = (srb_t *)ptr;
278 struct srb_iocb *iocb = &sp->u.iocb_cmd;
279 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
280 uint32_t flags;
281 uint16_t lun;
282 int rval;
3822263e 283
9ba56b95
GM		 284 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
285 flags = iocb->u.tmf.flags;
286 lun = (uint16_t)iocb->u.tmf.lun;
287
288 /* Issue Marker IOCB */
289 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
290 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
291 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
292
293 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
294 ql_dbg(ql_dbg_taskm, vha, 0x8030,
295 "TM IOCB failed (%x).\n", rval);
296 }
297 }
298 sp->free(sp->fcport->vha, sp);
3822263e
MI		 299}
300
301int
9ba56b95 302qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
3822263e
MI		 303 uint32_t tag)
304{
305 struct scsi_qla_host *vha = fcport->vha;
3822263e 306 srb_t *sp;
3822263e
MI		 307 struct srb_iocb *tcf;
308 int rval;
309
310 rval = QLA_FUNCTION_FAILED;
9ba56b95 311 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 312 if (!sp)
313 goto done;
314
9ba56b95
GM		 315 sp->type = SRB_TM_CMD;
316 sp->name = "tmf";
317 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
318
319 tcf = &sp->u.iocb_cmd;
320 tcf->u.tmf.flags = tm_flags;
3822263e
MI		 321 tcf->u.tmf.lun = lun;
322 tcf->u.tmf.data = tag;
323 tcf->timeout = qla2x00_async_iocb_timeout;
9ba56b95 324 sp->done = qla2x00_async_tm_cmd_done;
3822263e
MI		 325
326 rval = qla2x00_start_sp(sp);
327 if (rval != QLA_SUCCESS)
328 goto done_free_sp;
329
7c3df132 330 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 331 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
332 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
333 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3822263e
MI		 334 return rval;
335
336done_free_sp:
9ba56b95 337 sp->free(fcport->vha, sp);
3822263e
MI		 338done:
339 return rval;
340}
341
4916392b 342void
ac280b67
AV		 343qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
344 uint16_t *data)
345{
346 int rval;
ac280b67
AV		 347
348 switch (data[0]) {
349 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 350 /*
351 * Driver must validate login state - If PRLI not complete,
352 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
353 * requests.
354 */
355 rval = qla2x00_get_port_database(vha, fcport, 0);
0eba25df
AE		 356 if (rval == QLA_NOT_LOGGED_IN) {
357 fcport->flags &= ~FCF_ASYNC_SENT;
358 fcport->flags |= FCF_LOGIN_NEEDED;
359 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
360 break;
361 }
362
a4f92a32
AV		 363 if (rval != QLA_SUCCESS) {
364 qla2x00_post_async_logout_work(vha, fcport, NULL);
365 qla2x00_post_async_login_work(vha, fcport, NULL);
366 break;
367 }
99b0bec7 368 if (fcport->flags & FCF_FCP2_DEVICE) {
5ff1d584
AV		 369 qla2x00_post_async_adisc_work(vha, fcport, data);
370 break;
99b0bec7
AV		 371 }
372 qla2x00_update_fcport(vha, fcport);
ac280b67
AV		 373 break;
374 case MBS_COMMAND_ERROR:
5ff1d584 375 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 376 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
377 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
378 else
80d79440 379 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 380 break;
381 case MBS_PORT_ID_USED:
382 fcport->loop_id = data[1];
6ac52608 383 qla2x00_post_async_logout_work(vha, fcport, NULL);
ac280b67
AV		 384 qla2x00_post_async_login_work(vha, fcport, NULL);
385 break;
386 case MBS_LOOP_ID_USED:
387 fcport->loop_id++;
388 rval = qla2x00_find_new_loop_id(vha, fcport);
389 if (rval != QLA_SUCCESS) {
5ff1d584 390 fcport->flags &= ~FCF_ASYNC_SENT;
80d79440 391 qla2x00_mark_device_lost(vha, fcport, 1, 0);
ac280b67
AV		 392 break;
393 }
394 qla2x00_post_async_login_work(vha, fcport, NULL);
395 break;
396 }
4916392b 397 return;
ac280b67
AV		 398}
399
4916392b 400void
ac280b67
AV		 401qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
402 uint16_t *data)
403{
404 qla2x00_mark_device_lost(vha, fcport, 1, 0);
4916392b 405 return;
ac280b67
AV		 406}
407
4916392b 408void
5ff1d584
AV		 409qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
410 uint16_t *data)
411{
412 if (data[0] == MBS_COMMAND_COMPLETE) {
413 qla2x00_update_fcport(vha, fcport);
414
4916392b 415 return;
5ff1d584
AV		 416 }
417
418 /* Retry login. */
419 fcport->flags &= ~FCF_ASYNC_SENT;
420 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
421 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
422 else
80d79440 423 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 424
4916392b 425 return;
5ff1d584
AV		 426}
427
1da177e4
LT		 428/****************************************************************************/
429/* QLogic ISP2x00 Hardware Support Functions. */
430/****************************************************************************/
431
7d613ac6
SV		 432int
433qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
434{
435 int rval = QLA_SUCCESS;
436 struct qla_hw_data *ha = vha->hw;
437 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 438 uint16_t config[4];
7d613ac6
SV		 439
440 qla83xx_idc_lock(vha, 0);
441
442 /* SV: TODO: Assign initialization timeout from
443 * flash-info / other param
444 */
445 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
446 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
447
448 /* Set our fcoe function presence */
449 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
450 ql_dbg(ql_dbg_p3p, vha, 0xb077,
451 "Error while setting DRV-Presence.\n");
452 rval = QLA_FUNCTION_FAILED;
453 goto exit;
454 }
455
456 /* Decide the reset ownership */
457 qla83xx_reset_ownership(vha);
458
459 /*
460 * On first protocol driver load:
461 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
462 * register.
463 * Others: Check compatibility with current IDC Major version.
464 */
465 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
466 if (ha->flags.nic_core_reset_owner) {
467 /* Set IDC Major version */
468 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
469 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
470
471 /* Clearing IDC-Lock-Recovery register */
472 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
473 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
474 /*
475 * Clear further IDC participation if we are not compatible with
476 * the current IDC Major Version.
477 */
478 ql_log(ql_log_warn, vha, 0xb07d,
479 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
480 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
481 __qla83xx_clear_drv_presence(vha);
482 rval = QLA_FUNCTION_FAILED;
483 goto exit;
484 }
485 /* Each function sets its supported Minor version. */
486 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
487 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
488 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
489
711aa7f7
SK		 490 if (ha->flags.nic_core_reset_owner) {
491 memset(config, 0, sizeof(config));
492 if (!qla81xx_get_port_config(vha, config))
493 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
494 QLA8XXX_DEV_READY);
495 }
496
7d613ac6
SV		 497 rval = qla83xx_idc_state_handler(vha);
498
499exit:
500 qla83xx_idc_unlock(vha, 0);
501
502 return rval;
503}
504
1da177e4
LT		 505/*
506* qla2x00_initialize_adapter
507* Initialize board.
508*
509* Input:
510* ha = adapter block pointer.
511*
512* Returns:
513* 0 = success
514*/
515int
e315cd28 516qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 517{
518 int rval;
e315cd28 519 struct qla_hw_data *ha = vha->hw;
73208dfd 520 struct req_que *req = ha->req_q_map[0];
2533cf67 521
1da177e4 522 /* Clear adapter flags. */
e315cd28 523 vha->flags.online = 0;
2533cf67 524 ha->flags.chip_reset_done = 0;
e315cd28 525 vha->flags.reset_active = 0;
85880801
AV		 526 ha->flags.pci_channel_io_perm_failure = 0;
527 ha->flags.eeh_busy = 0;
794a5691 528 ha->flags.thermal_supported = 1;
e315cd28
AC		 529 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
530 atomic_set(&vha->loop_state, LOOP_DOWN);
531 vha->device_flags = DFLG_NO_CABLE;
532 vha->dpc_flags = 0;
533 vha->flags.management_server_logged_in = 0;
534 vha->marker_needed = 0;
1da177e4
LT		 535 ha->isp_abort_cnt = 0;
536 ha->beacon_blink_led = 0;
537
73208dfd
AC		 538 set_bit(0, ha->req_qid_map);
539 set_bit(0, ha->rsp_qid_map);
540
cfb0919c 541 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 542 "Configuring PCI space...\n");
e315cd28 543 rval = ha->isp_ops->pci_config(vha);
1da177e4 544 if (rval) {
7c3df132
SK		 545 ql_log(ql_log_warn, vha, 0x0044,
546 "Unable to configure PCI space.\n");
1da177e4
LT		 547 return (rval);
548 }
549
e315cd28 550 ha->isp_ops->reset_chip(vha);
1da177e4 551
e315cd28 552 rval = qla2xxx_get_flash_info(vha);
c00d8994 553 if (rval) {
7c3df132
SK		 554 ql_log(ql_log_fatal, vha, 0x004f,
555 "Unable to validate FLASH data.\n");
c00d8994
AV		 556 return (rval);
557 }
558
73208dfd 559 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 560 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 561 "Configure NVRAM parameters...\n");
0107109e 562
e315cd28 563 ha->isp_ops->nvram_config(vha);
1da177e4 564
d4c760c2
AV		 565 if (ha->flags.disable_serdes) {
566 /* Mask HBA via NVRAM settings? */
7c3df132
SK		 567 ql_log(ql_log_info, vha, 0x0077,
568 "Masking HBA WWPN "
d4c760c2 569 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
e315cd28
AC		 570 vha->port_name[0], vha->port_name[1],
571 vha->port_name[2], vha->port_name[3],
572 vha->port_name[4], vha->port_name[5],
573 vha->port_name[6], vha->port_name[7]);
d4c760c2
AV		 574 return QLA_FUNCTION_FAILED;
575 }
576
cfb0919c 577 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 578 "Verifying loaded RISC code...\n");
1da177e4 579
e315cd28
AC		 580 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
581 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 582 if (rval)
583 return (rval);
e315cd28 584 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 585 if (rval)
586 return (rval);
1da177e4 587 }
a9083016 588
4d4df193 589 if (IS_QLA84XX(ha)) {
e315cd28 590 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 591 if (!ha->cs84xx) {
7c3df132 592 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 593 "Unable to configure ISP84XX.\n");
594 return QLA_FUNCTION_FAILED;
595 }
596 }
2d70c103
NB		 597
598 if (qla_ini_mode_enabled(vha))
599 rval = qla2x00_init_rings(vha);
600
2533cf67 601 ha->flags.chip_reset_done = 1;
1da177e4 602
9a069e19 603 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 604 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 605 rval = qla84xx_init_chip(vha);
606 if (rval != QLA_SUCCESS) {
7c3df132
SK		 607 ql_log(ql_log_warn, vha, 0x00d4,
608 "Unable to initialize ISP84XX.\n");
9a069e19
GM		 609 qla84xx_put_chip(vha);
610 }
611 }
612
7d613ac6
SV		 613 /* Load the NIC Core f/w if we are the first protocol driver. */
614 if (IS_QLA8031(ha)) {
615 rval = qla83xx_nic_core_fw_load(vha);
616 if (rval)
617 ql_log(ql_log_warn, vha, 0x0124,
618 "Error in initializing NIC Core f/w.\n");
619 }
620
2f0f3f4f
MI		 621 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
622 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 623
1da177e4
LT		 624 return (rval);
625}
626
627/**
abbd8870 628 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 629 * @ha: HA context
630 *
631 * Returns 0 on success.
632 */
abbd8870 633int
e315cd28 634qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 635{
a157b101 636 uint16_t w;
abbd8870 637 unsigned long flags;
e315cd28 638 struct qla_hw_data *ha = vha->hw;
3d71644c 639 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 640
1da177e4 641 pci_set_master(ha->pdev);
af6177d8 642 pci_try_set_mwi(ha->pdev);
1da177e4 643
1da177e4 644 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 645 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 646 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
647
737faece 648 pci_disable_rom(ha->pdev);
1da177e4
LT		 649
650 /* Get PCI bus information. */
651 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 652 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 653 spin_unlock_irqrestore(&ha->hardware_lock, flags);
654
abbd8870
AV		 655 return QLA_SUCCESS;
656}
1da177e4 657
abbd8870
AV		 658/**
659 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
660 * @ha: HA context
661 *
662 * Returns 0 on success.
663 */
664int
e315cd28 665qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 666{
a157b101 667 uint16_t w;
abbd8870
AV		 668 unsigned long flags = 0;
669 uint32_t cnt;
e315cd28 670 struct qla_hw_data *ha = vha->hw;
3d71644c 671 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 672
abbd8870 673 pci_set_master(ha->pdev);
af6177d8 674 pci_try_set_mwi(ha->pdev);
1da177e4 675
abbd8870 676 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 677 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 678
abbd8870
AV		 679 if (IS_QLA2322(ha) || IS_QLA6322(ha))
680 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 681 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 682
abbd8870
AV		 683 /*
684 * If this is a 2300 card and not 2312, reset the
685 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
686 * the 2310 also reports itself as a 2300 so we need to get the
687 * fb revision level -- a 6 indicates it really is a 2300 and
688 * not a 2310.
689 */
690 if (IS_QLA2300(ha)) {
691 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 692
abbd8870 693 /* Pause RISC. */
3d71644c 694 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 695 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 696 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 697 break;
1da177e4 698
abbd8870
AV		 699 udelay(10);
700 }
1da177e4 701
abbd8870 702 /* Select FPM registers. */
3d71644c
AV		 703 WRT_REG_WORD(&reg->ctrl_status, 0x20);
704 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 705
706 /* Get the fb rev level */
3d71644c 707 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 708
709 if (ha->fb_rev == FPM_2300)
a157b101 710 pci_clear_mwi(ha->pdev);
abbd8870
AV		 711
712 /* Deselect FPM registers. */
3d71644c
AV		 713 WRT_REG_WORD(&reg->ctrl_status, 0x0);
714 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 715
716 /* Release RISC module. */
3d71644c 717 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 718 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 719 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 720 break;
721
722 udelay(10);
1da177e4 723 }
1da177e4 724
abbd8870
AV		 725 spin_unlock_irqrestore(&ha->hardware_lock, flags);
726 }
1da177e4 727
abbd8870
AV		 728 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
729
737faece 730 pci_disable_rom(ha->pdev);
1da177e4 731
abbd8870
AV		 732 /* Get PCI bus information. */
733 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 734 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 735 spin_unlock_irqrestore(&ha->hardware_lock, flags);
736
737 return QLA_SUCCESS;
1da177e4
LT		 738}
739
0107109e
AV		 740/**
741 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
742 * @ha: HA context
743 *
744 * Returns 0 on success.
745 */
746int
e315cd28 747qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 748{
a157b101 749 uint16_t w;
0107109e 750 unsigned long flags = 0;
e315cd28 751 struct qla_hw_data *ha = vha->hw;
0107109e 752 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 753
754 pci_set_master(ha->pdev);
af6177d8 755 pci_try_set_mwi(ha->pdev);
0107109e
AV		 756
757 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 758 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 759 w &= ~PCI_COMMAND_INTX_DISABLE;
760 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
761
762 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
763
764 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 765 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
766 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 767
768 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 769 if (pci_is_pcie(ha->pdev))
5ffd3a52 770 pcie_set_readrq(ha->pdev, 4096);
0107109e 771
737faece 772 pci_disable_rom(ha->pdev);
0107109e 773
44c10138 774 ha->chip_revision = ha->pdev->revision;
a8488abe 775
0107109e
AV		 776 /* Get PCI bus information. */
777 spin_lock_irqsave(&ha->hardware_lock, flags);
778 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
780
781 return QLA_SUCCESS;
782}
783
c3a2f0df
AV		 784/**
785 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
786 * @ha: HA context
787 *
788 * Returns 0 on success.
789 */
790int
e315cd28 791qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 792{
793 uint16_t w;
e315cd28 794 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 795
796 pci_set_master(ha->pdev);
797 pci_try_set_mwi(ha->pdev);
798
799 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
800 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
801 w &= ~PCI_COMMAND_INTX_DISABLE;
802 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
803
804 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 805 if (pci_is_pcie(ha->pdev))
5ffd3a52 806 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 807
737faece 808 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 809
810 ha->chip_revision = ha->pdev->revision;
811
812 return QLA_SUCCESS;
813}
814
1da177e4
LT		 815/**
816 * qla2x00_isp_firmware() - Choose firmware image.
817 * @ha: HA context
818 *
819 * Returns 0 on success.
820 */
821static int
e315cd28 822qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 823{
824 int rval;
42e421b1
AV		 825 uint16_t loop_id, topo, sw_cap;
826 uint8_t domain, area, al_pa;
e315cd28 827 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 828
829 /* Assume loading risc code */
fa2a1ce5 830 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 831
832 if (ha->flags.disable_risc_code_load) {
7c3df132 833 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 834
835 /* Verify checksum of loaded RISC code. */
e315cd28 836 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 837 if (rval == QLA_SUCCESS) {
838 /* And, verify we are not in ROM code. */
e315cd28 839 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 840 &area, &domain, &topo, &sw_cap);
841 }
1da177e4
LT		 842 }
843
7c3df132
SK		 844 if (rval)
845 ql_dbg(ql_dbg_init, vha, 0x007a,
846 "**** Load RISC code ****.\n");
1da177e4
LT		 847
848 return (rval);
849}
850
851/**
852 * qla2x00_reset_chip() - Reset ISP chip.
853 * @ha: HA context
854 *
855 * Returns 0 on success.
856 */
abbd8870 857void
e315cd28 858qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 859{
860 unsigned long flags = 0;
e315cd28 861 struct qla_hw_data *ha = vha->hw;
3d71644c 862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 863 uint32_t cnt;
1da177e4
LT		 864 uint16_t cmd;
865
85880801
AV		 866 if (unlikely(pci_channel_offline(ha->pdev)))
867 return;
868
fd34f556 869 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 870
871 spin_lock_irqsave(&ha->hardware_lock, flags);
872
873 /* Turn off master enable */
874 cmd = 0;
875 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
876 cmd &= ~PCI_COMMAND_MASTER;
877 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
878
879 if (!IS_QLA2100(ha)) {
880 /* Pause RISC. */
881 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
882 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
883 for (cnt = 0; cnt < 30000; cnt++) {
884 if ((RD_REG_WORD(&reg->hccr) &
885 HCCR_RISC_PAUSE) != 0)
886 break;
887 udelay(100);
888 }
889 } else {
890 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
891 udelay(10);
892 }
893
894 /* Select FPM registers. */
895 WRT_REG_WORD(&reg->ctrl_status, 0x20);
896 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
897
898 /* FPM Soft Reset. */
899 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
900 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
901
902 /* Toggle Fpm Reset. */
903 if (!IS_QLA2200(ha)) {
904 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
905 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
906 }
907
908 /* Select frame buffer registers. */
909 WRT_REG_WORD(&reg->ctrl_status, 0x10);
910 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
911
912 /* Reset frame buffer FIFOs. */
913 if (IS_QLA2200(ha)) {
914 WRT_FB_CMD_REG(ha, reg, 0xa000);
915 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
916 } else {
917 WRT_FB_CMD_REG(ha, reg, 0x00fc);
918
919 /* Read back fb_cmd until zero or 3 seconds max */
920 for (cnt = 0; cnt < 3000; cnt++) {
921 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
922 break;
923 udelay(100);
924 }
925 }
926
927 /* Select RISC module registers. */
928 WRT_REG_WORD(&reg->ctrl_status, 0);
929 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
930
931 /* Reset RISC processor. */
932 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
933 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
934
935 /* Release RISC processor. */
936 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
937 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
938 }
939
940 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
941 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
942
943 /* Reset ISP chip. */
944 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
945
946 /* Wait for RISC to recover from reset. */
947 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
948 /*
949 * It is necessary to for a delay here since the card doesn't
950 * respond to PCI reads during a reset. On some architectures
951 * this will result in an MCA.
952 */
953 udelay(20);
954 for (cnt = 30000; cnt; cnt--) {
955 if ((RD_REG_WORD(&reg->ctrl_status) &
956 CSR_ISP_SOFT_RESET) == 0)
957 break;
958 udelay(100);
959 }
960 } else
961 udelay(10);
962
963 /* Reset RISC processor. */
964 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
965
966 WRT_REG_WORD(&reg->semaphore, 0);
967
968 /* Release RISC processor. */
969 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
970 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
971
972 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
973 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 974 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 975 break;
1da177e4
LT		 976
977 udelay(100);
978 }
979 } else
980 udelay(100);
981
982 /* Turn on master enable */
983 cmd |= PCI_COMMAND_MASTER;
984 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
985
986 /* Disable RISC pause on FPM parity error. */
987 if (!IS_QLA2100(ha)) {
988 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
989 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
990 }
991
992 spin_unlock_irqrestore(&ha->hardware_lock, flags);
993}
994
b1d46989
MI		 995/**
996 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
997 *
998 * Returns 0 on success.
999 */
1000int
1001qla81xx_reset_mpi(scsi_qla_host_t *vha)
1002{
1003 uint16_t mb[4] = {0x1010, 0, 1, 0};
1004
6246b8a1
GM		 1005 if (!IS_QLA81XX(vha->hw))
1006 return QLA_SUCCESS;
1007
b1d46989
MI		 1008 return qla81xx_write_mpi_register(vha, mb);
1009}
1010
0107109e 1011/**
88c26663 1012 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 1013 * @ha: HA context
1014 *
1015 * Returns 0 on success.
1016 */
88c26663 1017static inline void
e315cd28 1018qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 1019{
1020 unsigned long flags = 0;
e315cd28 1021 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 1022 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1023 uint32_t cnt, d2;
335a1cc9 1024 uint16_t wd;
b1d46989 1025 static int abts_cnt; /* ISP abort retry counts */
0107109e 1026
0107109e
AV		 1027 spin_lock_irqsave(&ha->hardware_lock, flags);
1028
1029 /* Reset RISC. */
1030 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1031 for (cnt = 0; cnt < 30000; cnt++) {
1032 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
1033 break;
1034
1035 udelay(10);
1036 }
1037
1038 WRT_REG_DWORD(&reg->ctrl_status,
1039 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 1040 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 1041
335a1cc9 1042 udelay(100);
88c26663 1043 /* Wait for firmware to complete NVRAM accesses. */
88c26663
AV		 1044 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1045 for (cnt = 10000 ; cnt && d2; cnt--) {
1046 udelay(5);
1047 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1048 barrier();
1049 }
1050
335a1cc9 1051 /* Wait for soft-reset to complete. */
0107109e
AV		 1052 d2 = RD_REG_DWORD(&reg->ctrl_status);
1053 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
1054 udelay(5);
1055 d2 = RD_REG_DWORD(&reg->ctrl_status);
1056 barrier();
1057 }
1058
b1d46989
MI		 1059 /* If required, do an MPI FW reset now */
1060 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
1061 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
1062 if (++abts_cnt < 5) {
1063 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1064 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
1065 } else {
1066 /*
1067 * We exhausted the ISP abort retries. We have to
1068 * set the board offline.
1069 */
1070 abts_cnt = 0;
1071 vha->flags.online = 0;
1072 }
1073 }
1074 }
1075
0107109e
AV		 1076 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
1077 RD_REG_DWORD(&reg->hccr);
1078
1079 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
1080 RD_REG_DWORD(&reg->hccr);
1081
1082 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1083 RD_REG_DWORD(&reg->hccr);
1084
1085 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1086 for (cnt = 6000000 ; cnt && d2; cnt--) {
1087 udelay(5);
1088 d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1089 barrier();
1090 }
1091
1092 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6
AV		 1093
1094 if (IS_NOPOLLING_TYPE(ha))
1095 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 1096}
1097
88c26663
AV		 1098/**
1099 * qla24xx_reset_chip() - Reset ISP24xx chip.
1100 * @ha: HA context
1101 *
1102 * Returns 0 on success.
1103 */
1104void
e315cd28 1105qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 1106{
e315cd28 1107 struct qla_hw_data *ha = vha->hw;
85880801
AV		 1108
1109 if (pci_channel_offline(ha->pdev) &&
1110 ha->flags.pci_channel_io_perm_failure) {
1111 return;
1112 }
1113
fd34f556 1114 ha->isp_ops->disable_intrs(ha);
88c26663
AV		 1115
1116 /* Perform RISC reset. */
e315cd28 1117 qla24xx_reset_risc(vha);
88c26663
AV		 1118}
1119
1da177e4
LT		 1120/**
1121 * qla2x00_chip_diag() - Test chip for proper operation.
1122 * @ha: HA context
1123 *
1124 * Returns 0 on success.
1125 */
abbd8870 1126int
e315cd28 1127qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 1128{
1129 int rval;
e315cd28 1130 struct qla_hw_data *ha = vha->hw;
3d71644c 1131 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1132 unsigned long flags = 0;
1133 uint16_t data;
1134 uint32_t cnt;
1135 uint16_t mb[5];
73208dfd 1136 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 1137
1138 /* Assume a failed state */
1139 rval = QLA_FUNCTION_FAILED;
1140
7c3df132
SK		 1141 ql_dbg(ql_dbg_init, vha, 0x007b,
1142 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 1143
1144 spin_lock_irqsave(&ha->hardware_lock, flags);
1145
1146 /* Reset ISP chip. */
1147 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1148
1149 /*
1150 * We need to have a delay here since the card will not respond while
1151 * in reset causing an MCA on some architectures.
1152 */
1153 udelay(20);
1154 data = qla2x00_debounce_register(&reg->ctrl_status);
1155 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1156 udelay(5);
1157 data = RD_REG_WORD(&reg->ctrl_status);
1158 barrier();
1159 }
1160
1161 if (!cnt)
1162 goto chip_diag_failed;
1163
7c3df132
SK		 1164 ql_dbg(ql_dbg_init, vha, 0x007c,
1165 "Reset register cleared by chip reset.\n");
1da177e4
LT		 1166
1167 /* Reset RISC processor. */
1168 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
1169 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
1170
1171 /* Workaround for QLA2312 PCI parity error */
1172 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1173 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1174 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1175 udelay(5);
1176 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 1177 barrier();
1da177e4
LT		 1178 }
1179 } else
1180 udelay(10);
1181
1182 if (!cnt)
1183 goto chip_diag_failed;
1184
1185 /* Check product ID of chip */
7c3df132 1186 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1da177e4
LT		 1187
1188 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1189 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1190 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1191 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1192 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1193 mb[3] != PROD_ID_3) {
7c3df132
SK		 1194 ql_log(ql_log_warn, vha, 0x0062,
1195 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1196 mb[1], mb[2], mb[3]);
1da177e4
LT		 1197
1198 goto chip_diag_failed;
1199 }
1200 ha->product_id[0] = mb[1];
1201 ha->product_id[1] = mb[2];
1202 ha->product_id[2] = mb[3];
1203 ha->product_id[3] = mb[4];
1204
1205 /* Adjust fw RISC transfer size */
73208dfd 1206 if (req->length > 1024)
1da177e4
LT		 1207 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1208 else
1209 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 1210 req->length;
1da177e4
LT		 1211
1212 if (IS_QLA2200(ha) &&
1213 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1214 /* Limit firmware transfer size with a 2200A */
7c3df132 1215 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 1216
ea5b6382 1217 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 1218 ha->fw_transfer_size = 128;
1219 }
1220
1221 /* Wrap Incoming Mailboxes Test. */
1222 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1223
7c3df132 1224 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 1225 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 1226 if (rval)
1227 ql_log(ql_log_warn, vha, 0x0080,
1228 "Failed mailbox send register test.\n");
1229 else
1da177e4
LT		 1230 /* Flag a successful rval */
1231 rval = QLA_SUCCESS;
1da177e4
LT		 1232 spin_lock_irqsave(&ha->hardware_lock, flags);
1233
1234chip_diag_failed:
1235 if (rval)
7c3df132
SK		 1236 ql_log(ql_log_info, vha, 0x0081,
1237 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 1238
1239 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1240
1241 return (rval);
1242}
1243
0107109e
AV		 1244/**
1245 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
1246 * @ha: HA context
1247 *
1248 * Returns 0 on success.
1249 */
1250int
e315cd28 1251qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 1252{
1253 int rval;
e315cd28 1254 struct qla_hw_data *ha = vha->hw;
73208dfd 1255 struct req_que *req = ha->req_q_map[0];
0107109e 1256
a9083016
GM		 1257 if (IS_QLA82XX(ha))
1258 return QLA_SUCCESS;
1259
73208dfd 1260 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 1261
e315cd28 1262 rval = qla2x00_mbx_reg_test(vha);
0107109e 1263 if (rval) {
7c3df132
SK		 1264 ql_log(ql_log_warn, vha, 0x0082,
1265 "Failed mailbox send register test.\n");
0107109e
AV		 1266 } else {
1267 /* Flag a successful rval */
1268 rval = QLA_SUCCESS;
1269 }
1270
1271 return rval;
1272}
1273
a7a167bf 1274void
e315cd28 1275qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 1276{
a7a167bf
AV		 1277 int rval;
1278 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 1279 eft_size, fce_size, mq_size;
df613b96
AV		 1280 dma_addr_t tc_dma;
1281 void *tc;
e315cd28 1282 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1283 struct req_que *req = ha->req_q_map[0];
1284 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 1285
1286 if (ha->fw_dump) {
7c3df132
SK		 1287 ql_dbg(ql_dbg_init, vha, 0x00bd,
1288 "Firmware dump already allocated.\n");
a7a167bf
AV		 1289 return;
1290 }
d4e3e04d 1291
0107109e 1292 ha->fw_dumped = 0;
73208dfd 1293 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
d4e3e04d 1294 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 1295 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 1296 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 1297 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1298 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1299 sizeof(uint16_t);
e428924c 1300 } else if (IS_FWI2_CAPABLE(ha)) {
6246b8a1
GM		 1301 if (IS_QLA83XX(ha))
1302 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1303 else if (IS_QLA81XX(ha))
3a03eb79
AV		 1304 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1305 else if (IS_QLA25XX(ha))
1306 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1307 else
1308 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
a7a167bf
AV		 1309 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1310 sizeof(uint32_t);
050c9bb1 1311 if (ha->mqenable) {
6246b8a1
GM		 1312 if (!IS_QLA83XX(ha))
1313 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 1314 /*
1315 * Allocate maximum buffer size for all queues.
1316 * Resizing must be done at end-of-dump processing.
1317 */
1318 mq_size += ha->max_req_queues *
1319 (req->length * sizeof(request_t));
1320 mq_size += ha->max_rsp_queues *
1321 (rsp->length * sizeof(response_t));
1322 }
2d70c103
NB		 1323 if (ha->tgt.atio_q_length)
1324 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 1325 /* Allocate memory for Fibre Channel Event Buffer. */
6246b8a1 1326 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
436a7b11 1327 goto try_eft;
df613b96
AV		 1328
1329 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1330 GFP_KERNEL);
1331 if (!tc) {
7c3df132
SK		 1332 ql_log(ql_log_warn, vha, 0x00be,
1333 "Unable to allocate (%d KB) for FCE.\n",
1334 FCE_SIZE / 1024);
17d98630 1335 goto try_eft;
df613b96
AV		 1336 }
1337
1338 memset(tc, 0, FCE_SIZE);
e315cd28 1339 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 1340 ha->fce_mb, &ha->fce_bufs);
1341 if (rval) {
7c3df132
SK		 1342 ql_log(ql_log_warn, vha, 0x00bf,
1343 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 1344 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1345 tc_dma);
1346 ha->flags.fce_enabled = 0;
17d98630 1347 goto try_eft;
df613b96 1348 }
cfb0919c 1349 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 1350 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 1351
7d9dade3 1352 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 1353 ha->flags.fce_enabled = 1;
1354 ha->fce_dma = tc_dma;
1355 ha->fce = tc;
436a7b11
AV		 1356try_eft:
1357 /* Allocate memory for Extended Trace Buffer. */
1358 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1359 GFP_KERNEL);
1360 if (!tc) {
7c3df132
SK		 1361 ql_log(ql_log_warn, vha, 0x00c1,
1362 "Unable to allocate (%d KB) for EFT.\n",
1363 EFT_SIZE / 1024);
436a7b11
AV		 1364 goto cont_alloc;
1365 }
1366
1367 memset(tc, 0, EFT_SIZE);
e315cd28 1368 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 1369 if (rval) {
7c3df132
SK		 1370 ql_log(ql_log_warn, vha, 0x00c2,
1371 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 1372 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1373 tc_dma);
1374 goto cont_alloc;
1375 }
cfb0919c 1376 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 1377 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 1378
1379 eft_size = EFT_SIZE;
1380 ha->eft_dma = tc_dma;
1381 ha->eft = tc;
d4e3e04d 1382 }
a7a167bf 1383cont_alloc:
73208dfd
AC		 1384 req_q_size = req->length * sizeof(request_t);
1385 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf
AV		 1386
1387 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 1388 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 1389 ha->chain_offset = dump_size;
1390 dump_size += mq_size + fce_size;
d4e3e04d
AV		 1391
1392 ha->fw_dump = vmalloc(dump_size);
a7a167bf 1393 if (!ha->fw_dump) {
7c3df132
SK		 1394 ql_log(ql_log_warn, vha, 0x00c4,
1395 "Unable to allocate (%d KB) for firmware dump.\n",
1396 dump_size / 1024);
a7a167bf 1397
e30d1756
MI		 1398 if (ha->fce) {
1399 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1400 ha->fce_dma);
1401 ha->fce = NULL;
1402 ha->fce_dma = 0;
1403 }
1404
a7a167bf
AV		 1405 if (ha->eft) {
1406 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1407 ha->eft_dma);
1408 ha->eft = NULL;
1409 ha->eft_dma = 0;
1410 }
1411 return;
1412 }
cfb0919c 1413 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 1414 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf
AV		 1415
1416 ha->fw_dump_len = dump_size;
1417 ha->fw_dump->signature[0] = 'Q';
1418 ha->fw_dump->signature[1] = 'L';
1419 ha->fw_dump->signature[2] = 'G';
1420 ha->fw_dump->signature[3] = 'C';
1421 ha->fw_dump->version = __constant_htonl(1);
1422
1423 ha->fw_dump->fixed_size = htonl(fixed_size);
1424 ha->fw_dump->mem_size = htonl(mem_size);
1425 ha->fw_dump->req_q_size = htonl(req_q_size);
1426 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1427
1428 ha->fw_dump->eft_size = htonl(eft_size);
1429 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1430 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1431
1432 ha->fw_dump->header_size =
1433 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 1434}
1435
18e7555a
AV		 1436static int
1437qla81xx_mpi_sync(scsi_qla_host_t *vha)
1438{
1439#define MPS_MASK 0xe0
1440 int rval;
1441 uint16_t dc;
1442 uint32_t dw;
18e7555a
AV		 1443
1444 if (!IS_QLA81XX(vha->hw))
1445 return QLA_SUCCESS;
1446
1447 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1448 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1449 ql_log(ql_log_warn, vha, 0x0105,
1450 "Unable to acquire semaphore.\n");
18e7555a
AV		 1451 goto done;
1452 }
1453
1454 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1455 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1456 if (rval != QLA_SUCCESS) {
7c3df132 1457 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 1458 goto done_release;
1459 }
1460
1461 dc &= MPS_MASK;
1462 if (dc == (dw & MPS_MASK))
1463 goto done_release;
1464
1465 dw &= ~MPS_MASK;
1466 dw |= dc;
1467 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1468 if (rval != QLA_SUCCESS) {
7c3df132 1469 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 1470 }
1471
1472done_release:
1473 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1474 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1475 ql_log(ql_log_warn, vha, 0x006d,
1476 "Unable to release semaphore.\n");
18e7555a
AV		 1477 }
1478
1479done:
1480 return rval;
1481}
1482
1da177e4
LT		 1483/**
1484 * qla2x00_setup_chip() - Load and start RISC firmware.
1485 * @ha: HA context
1486 *
1487 * Returns 0 on success.
1488 */
1489static int
e315cd28 1490qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 1491{
0107109e
AV		 1492 int rval;
1493 uint32_t srisc_address = 0;
e315cd28 1494 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 1495 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1496 unsigned long flags;
dda772e8 1497 uint16_t fw_major_version;
3db0652e 1498
a9083016
GM		 1499 if (IS_QLA82XX(ha)) {
1500 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 1501 if (rval == QLA_SUCCESS) {
1502 qla2x00_stop_firmware(vha);
a9083016 1503 goto enable_82xx_npiv;
14e303d9 1504 } else
b963752f 1505 goto failed;
a9083016
GM		 1506 }
1507
3db0652e
AV		 1508 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1509 /* Disable SRAM, Instruction RAM and GP RAM parity. */
1510 spin_lock_irqsave(&ha->hardware_lock, flags);
1511 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
1512 RD_REG_WORD(&reg->hccr);
1513 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1514 }
1da177e4 1515
18e7555a
AV		 1516 qla81xx_mpi_sync(vha);
1517
1da177e4 1518 /* Load firmware sequences */
e315cd28 1519 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 1520 if (rval == QLA_SUCCESS) {
7c3df132
SK		 1521 ql_dbg(ql_dbg_init, vha, 0x00c9,
1522 "Verifying Checksum of loaded RISC code.\n");
1da177e4 1523
e315cd28 1524 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 1525 if (rval == QLA_SUCCESS) {
1526 /* Start firmware execution. */
7c3df132
SK		 1527 ql_dbg(ql_dbg_init, vha, 0x00ca,
1528 "Starting firmware.\n");
1da177e4 1529
e315cd28 1530 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 1531 /* Retrieve firmware information. */
dda772e8 1532 if (rval == QLA_SUCCESS) {
a9083016 1533enable_82xx_npiv:
dda772e8 1534 fw_major_version = ha->fw_major_version;
3173167f
GM		 1535 if (IS_QLA82XX(ha))
1536 qla82xx_check_md_needed(vha);
6246b8a1
GM		 1537 else
1538 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 1539 if (rval != QLA_SUCCESS)
1540 goto failed;
2c3dfe3f 1541 ha->flags.npiv_supported = 0;
e315cd28 1542 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 1543 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 1544 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 1545 if ((!ha->max_npiv_vports) ||
1546 ((ha->max_npiv_vports + 1) %
eb66dc60 1547 MIN_MULTI_ID_FABRIC))
4d0ea247 1548 ha->max_npiv_vports =
eb66dc60 1549 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 1550 }
24a08138
AV		 1551 qla2x00_get_resource_cnts(vha, NULL,
1552 &ha->fw_xcb_count, NULL, NULL,
f3a0a77e 1553 &ha->max_npiv_vports, NULL);
d743de66 1554
be5ea3cf
SK		 1555 if (!fw_major_version && ql2xallocfwdump
1556 && !IS_QLA82XX(ha))
08de2844 1557 qla2x00_alloc_fw_dump(vha);
1da177e4
LT		 1558 }
1559 } else {
7c3df132
SK		 1560 ql_log(ql_log_fatal, vha, 0x00cd,
1561 "ISP Firmware failed checksum.\n");
1562 goto failed;
1da177e4 1563 }
c74d88a4
AV		 1564 } else
1565 goto failed;
1da177e4 1566
3db0652e
AV		 1567 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1568 /* Enable proper parity. */
1569 spin_lock_irqsave(&ha->hardware_lock, flags);
1570 if (IS_QLA2300(ha))
1571 /* SRAM parity */
1572 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
1573 else
1574 /* SRAM, Instruction RAM and GP RAM parity */
1575 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
1576 RD_REG_WORD(&reg->hccr);
1577 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1578 }
1579
6246b8a1
GM		 1580 if (IS_QLA83XX(ha))
1581 goto skip_fac_check;
1582
1d2874de
JC		 1583 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1584 uint32_t size;
1585
1586 rval = qla81xx_fac_get_sector_size(vha, &size);
1587 if (rval == QLA_SUCCESS) {
1588 ha->flags.fac_supported = 1;
1589 ha->fdt_block_size = size << 2;
1590 } else {
7c3df132 1591 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 1592 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1593 ha->fw_major_version, ha->fw_minor_version,
1594 ha->fw_subminor_version);
6246b8a1
GM		 1595skip_fac_check:
1596 if (IS_QLA83XX(ha)) {
1597 ha->flags.fac_supported = 0;
1598 rval = QLA_SUCCESS;
1599 }
1d2874de
JC		 1600 }
1601 }
ca9e9c3e 1602failed:
1da177e4 1603 if (rval) {
7c3df132
SK		 1604 ql_log(ql_log_fatal, vha, 0x00cf,
1605 "Setup chip ****FAILED****.\n");
1da177e4
LT		 1606 }
1607
1608 return (rval);
1609}
1610
1611/**
1612 * qla2x00_init_response_q_entries() - Initializes response queue entries.
1613 * @ha: HA context
1614 *
1615 * Beginning of request ring has initialization control block already built
1616 * by nvram config routine.
1617 *
1618 * Returns 0 on success.
1619 */
73208dfd
AC		 1620void
1621qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 1622{
1623 uint16_t cnt;
1624 response_t *pkt;
1625
2afa19a9
AC		 1626 rsp->ring_ptr = rsp->ring;
1627 rsp->ring_index = 0;
1628 rsp->status_srb = NULL;
e315cd28
AC		 1629 pkt = rsp->ring_ptr;
1630 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 1631 pkt->signature = RESPONSE_PROCESSED;
1632 pkt++;
1633 }
1da177e4
LT		 1634}
1635
1636/**
1637 * qla2x00_update_fw_options() - Read and process firmware options.
1638 * @ha: HA context
1639 *
1640 * Returns 0 on success.
1641 */
abbd8870 1642void
e315cd28 1643qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 1644{
1645 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 1646 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1647
1648 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 1649 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 1650
1651 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1652 return;
1653
1654 /* Serial Link options. */
7c3df132
SK		 1655 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1656 "Serial link options.\n");
1657 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1658 (uint8_t *)&ha->fw_seriallink_options,
1659 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 1660
1661 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1662 if (ha->fw_seriallink_options[3] & BIT_2) {
1663 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1664
1665 /* 1G settings */
1666 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1667 emphasis = (ha->fw_seriallink_options[2] &
1668 (BIT_4 | BIT_3)) >> 3;
1669 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 1670 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1671 rx_sens = (ha->fw_seriallink_options[0] &
1672 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1673 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1674 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1675 if (rx_sens == 0x0)
1676 rx_sens = 0x3;
1677 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1678 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1679 ha->fw_options[10] |= BIT_5 |
1680 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1681 (tx_sens & (BIT_1 | BIT_0));
1682
1683 /* 2G settings */
1684 swing = (ha->fw_seriallink_options[2] &
1685 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1686 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1687 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 1688 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 1689 rx_sens = (ha->fw_seriallink_options[1] &
1690 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1691 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1692 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1693 if (rx_sens == 0x0)
1694 rx_sens = 0x3;
1695 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1696 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1697 ha->fw_options[11] |= BIT_5 |
1698 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1699 (tx_sens & (BIT_1 | BIT_0));
1700 }
1701
1702 /* FCP2 options. */
1703 /* Return command IOCBs without waiting for an ABTS to complete. */
1704 ha->fw_options[3] |= BIT_13;
1705
1706 /* LED scheme. */
1707 if (ha->flags.enable_led_scheme)
1708 ha->fw_options[2] |= BIT_12;
1709
48c02fde
AV		 1710 /* Detect ISP6312. */
1711 if (IS_QLA6312(ha))
1712 ha->fw_options[2] |= BIT_13;
1713
1da177e4 1714 /* Update firmware options. */
e315cd28 1715 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 1716}
1717
0107109e 1718void
e315cd28 1719qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 1720{
1721 int rval;
e315cd28 1722 struct qla_hw_data *ha = vha->hw;
0107109e 1723
a9083016
GM		 1724 if (IS_QLA82XX(ha))
1725 return;
1726
0107109e 1727 /* Update Serial Link options. */
f94097ed 1728 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 1729 return;
1730
e315cd28 1731 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 1732 le16_to_cpu(ha->fw_seriallink_options24[1]),
1733 le16_to_cpu(ha->fw_seriallink_options24[2]),
1734 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 1735 if (rval != QLA_SUCCESS) {
7c3df132 1736 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 1737 "Unable to update Serial Link options (%x).\n", rval);
1738 }
1739}
1740
abbd8870 1741void
e315cd28 1742qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 1743{
e315cd28 1744 struct qla_hw_data *ha = vha->hw;
3d71644c 1745 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 1746 struct req_que *req = ha->req_q_map[0];
1747 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 1748
1749 /* Setup ring parameters in initialization control block. */
1750 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1751 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1752 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1753 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1754 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1755 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1756 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1757 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 1758
1759 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1760 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1761 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1762 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1763 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
1764}
1765
0107109e 1766void
e315cd28 1767qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 1768{
e315cd28 1769 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 1770 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1771 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1772 struct qla_msix_entry *msix;
0107109e 1773 struct init_cb_24xx *icb;
73208dfd
AC		 1774 uint16_t rid = 0;
1775 struct req_que *req = ha->req_q_map[0];
1776 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 1777
6246b8a1 1778 /* Setup ring parameters in initialization control block. */
0107109e
AV		 1779 icb = (struct init_cb_24xx *)ha->init_cb;
1780 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1781 icb->response_q_inpointer = __constant_cpu_to_le16(0);
e315cd28
AC		 1782 icb->request_q_length = cpu_to_le16(req->length);
1783 icb->response_q_length = cpu_to_le16(rsp->length);
1784 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1785 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1786 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1787 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 1788
2d70c103
NB		 1789 /* Setup ATIO queue dma pointers for target mode */
1790 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1791 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1792 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1793 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1794
6246b8a1 1795 if (ha->mqenable || IS_QLA83XX(ha)) {
73208dfd
AC		 1796 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1797 icb->rid = __constant_cpu_to_le16(rid);
1798 if (ha->flags.msix_enabled) {
1799 msix = &ha->msix_entries[1];
7c3df132
SK		 1800 ql_dbg(ql_dbg_init, vha, 0x00fd,
1801 "Registering vector 0x%x for base que.\n",
1802 msix->entry);
73208dfd
AC		 1803 icb->msix = cpu_to_le16(msix->entry);
1804 }
1805 /* Use alternate PCI bus number */
1806 if (MSB(rid))
1807 icb->firmware_options_2 |=
1808 __constant_cpu_to_le32(BIT_19);
1809 /* Use alternate PCI devfn */
1810 if (LSB(rid))
1811 icb->firmware_options_2 |=
1812 __constant_cpu_to_le32(BIT_18);
1813
3155754a 1814 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 1815 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1816 (ha->flags.msix_enabled)) {
3155754a
AC		 1817 icb->firmware_options_2 &=
1818 __constant_cpu_to_le32(~BIT_22);
1819 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 1820 ql_dbg(ql_dbg_init, vha, 0x00fe,
1821 "MSIX Handshake Disable Mode turned on.\n");
3155754a
AC		 1822 } else {
1823 icb->firmware_options_2 |=
1824 __constant_cpu_to_le32(BIT_22);
1825 }
73208dfd 1826 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
73208dfd
AC		 1827
1828 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
1829 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
1830 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
1831 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
1832 } else {
1833 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
1834 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
1835 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
1836 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
1837 }
2d70c103
NB		 1838 qlt_24xx_config_rings(vha, reg);
1839
73208dfd
AC		 1840 /* PCI posting */
1841 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 1842}
1843
1da177e4
LT		 1844/**
1845 * qla2x00_init_rings() - Initializes firmware.
1846 * @ha: HA context
1847 *
1848 * Beginning of request ring has initialization control block already built
1849 * by nvram config routine.
1850 *
1851 * Returns 0 on success.
1852 */
1853static int
e315cd28 1854qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 1855{
1856 int rval;
1857 unsigned long flags = 0;
29bdccbe 1858 int cnt, que;
e315cd28 1859 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 1860 struct req_que *req;
1861 struct rsp_que *rsp;
2c3dfe3f
SJ		 1862 struct mid_init_cb_24xx *mid_init_cb =
1863 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 1864
1865 spin_lock_irqsave(&ha->hardware_lock, flags);
1866
1867 /* Clear outstanding commands array. */
2afa19a9 1868 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe
AC		 1869 req = ha->req_q_map[que];
1870 if (!req)
1871 continue;
2afa19a9 1872 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
29bdccbe 1873 req->outstanding_cmds[cnt] = NULL;
1da177e4 1874
2afa19a9 1875 req->current_outstanding_cmd = 1;
1da177e4 1876
29bdccbe
AC		 1877 /* Initialize firmware. */
1878 req->ring_ptr = req->ring;
1879 req->ring_index = 0;
1880 req->cnt = req->length;
1881 }
1da177e4 1882
2afa19a9 1883 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe
AC		 1884 rsp = ha->rsp_q_map[que];
1885 if (!rsp)
1886 continue;
29bdccbe
AC		 1887 /* Initialize response queue entries */
1888 qla2x00_init_response_q_entries(rsp);
1889 }
1da177e4 1890
542bce1f 1891 spin_lock(&ha->vport_slock);
feafb7b1 1892
542bce1f 1893 spin_unlock(&ha->vport_slock);
feafb7b1 1894
2d70c103
NB		 1895 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
1896 ha->tgt.atio_ring_index = 0;
1897 /* Initialize ATIO queue entries */
1898 qlt_init_atio_q_entries(vha);
1899
e315cd28 1900 ha->isp_ops->config_rings(vha);
1da177e4
LT		 1901
1902 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1903
1904 /* Update any ISP specific firmware options before initialization. */
e315cd28 1905 ha->isp_ops->update_fw_options(vha);
1da177e4 1906
7c3df132 1907 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
2c3dfe3f 1908
605aa2bc 1909 if (ha->flags.npiv_supported) {
45980cc2 1910 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 1911 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 1912 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 1913 }
1914
24a08138
AV		 1915 if (IS_FWI2_CAPABLE(ha)) {
1916 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
1917 mid_init_cb->init_cb.execution_throttle =
1918 cpu_to_le16(ha->fw_xcb_count);
1919 }
2c3dfe3f 1920
e315cd28 1921 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
1da177e4 1922 if (rval) {
7c3df132
SK		 1923 ql_log(ql_log_fatal, vha, 0x00d2,
1924 "Init Firmware **** FAILED ****.\n");
1da177e4 1925 } else {
7c3df132
SK		 1926 ql_dbg(ql_dbg_init, vha, 0x00d3,
1927 "Init Firmware -- success.\n");
1da177e4
LT		 1928 }
1929
1930 return (rval);
1931}
1932
1933/**
1934 * qla2x00_fw_ready() - Waits for firmware ready.
1935 * @ha: HA context
1936 *
1937 * Returns 0 on success.
1938 */
1939static int
e315cd28 1940qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 1941{
1942 int rval;
4d4df193 1943 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 1944 uint16_t min_wait; /* Minimum wait time if loop is down */
1945 uint16_t wait_time; /* Wait time if loop is coming ready */
656e8912 1946 uint16_t state[5];
e315cd28 1947 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1948
1949 rval = QLA_SUCCESS;
1950
1951 /* 20 seconds for loop down. */
fa2a1ce5 1952 min_wait = 20;
1da177e4
LT		 1953
1954 /*
1955 * Firmware should take at most one RATOV to login, plus 5 seconds for
1956 * our own processing.
1957 */
1958 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
1959 wait_time = min_wait;
1960 }
1961
1962 /* Min wait time if loop down */
1963 mtime = jiffies + (min_wait * HZ);
1964
1965 /* wait time before firmware ready */
1966 wtime = jiffies + (wait_time * HZ);
1967
1968 /* Wait for ISP to finish LIP */
e315cd28 1969 if (!vha->flags.init_done)
7c3df132
SK		 1970 ql_log(ql_log_info, vha, 0x801e,
1971 "Waiting for LIP to complete.\n");
1da177e4
LT		 1972
1973 do {
e315cd28 1974 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 1975 if (rval == QLA_SUCCESS) {
4d4df193 1976 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 1977 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 1978 }
4d4df193 1979 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 1980 ql_dbg(ql_dbg_taskm, vha, 0x801f,
1981 "fw_state=%x 84xx=%x.\n", state[0],
1982 state[2]);
4d4df193
HK		 1983 if ((state[2] & FSTATE_LOGGED_IN) &&
1984 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 1985 ql_dbg(ql_dbg_taskm, vha, 0x8028,
1986 "Sending verify iocb.\n");
4d4df193
HK		 1987
1988 cs84xx_time = jiffies;
e315cd28 1989 rval = qla84xx_init_chip(vha);
7c3df132
SK		 1990 if (rval != QLA_SUCCESS) {
1991 ql_log(ql_log_warn,
cfb0919c 1992 vha, 0x8007,
7c3df132 1993 "Init chip failed.\n");
4d4df193 1994 break;
7c3df132 1995 }
4d4df193
HK		 1996
1997 /* Add time taken to initialize. */
1998 cs84xx_time = jiffies - cs84xx_time;
1999 wtime += cs84xx_time;
2000 mtime += cs84xx_time;
cfb0919c 2001 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 2002 "Increasing wait time by %ld. "
2003 "New time %ld.\n", cs84xx_time,
2004 wtime);
4d4df193
HK		 2005 }
2006 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 2007 ql_dbg(ql_dbg_taskm, vha, 0x8037,
2008 "F/W Ready - OK.\n");
1da177e4 2009
e315cd28 2010 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 2011 &ha->login_timeout, &ha->r_a_tov);
2012
2013 rval = QLA_SUCCESS;
2014 break;
2015 }
2016
2017 rval = QLA_FUNCTION_FAILED;
2018
e315cd28 2019 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 2020 state[0] != FSTATE_READY) {
1da177e4 2021 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 2022 * other than Wait for Login.
2023 */
1da177e4 2024 if (time_after_eq(jiffies, mtime)) {
7c3df132 2025 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 2026 "Cable is unplugged...\n");
2027
e315cd28 2028 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 2029 break;
2030 }
2031 }
2032 } else {
2033 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 2034 if (time_after_eq(jiffies, mtime) ||
7190575f 2035 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 2036 break;
2037 }
2038
2039 if (time_after_eq(jiffies, wtime))
2040 break;
2041
2042 /* Delay for a while */
2043 msleep(500);
1da177e4
LT		 2044 } while (1);
2045
7c3df132
SK		 2046 ql_dbg(ql_dbg_taskm, vha, 0x803a,
2047 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
2048 state[1], state[2], state[3], state[4], jiffies);
1da177e4 2049
cfb0919c 2050 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 2051 ql_log(ql_log_warn, vha, 0x803b,
2052 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 2053 }
2054
2055 return (rval);
2056}
2057
2058/*
2059* qla2x00_configure_hba
2060* Setup adapter context.
2061*
2062* Input:
2063* ha = adapter state pointer.
2064*
2065* Returns:
2066* 0 = success
2067*
2068* Context:
2069* Kernel context.
2070*/
2071static int
e315cd28 2072qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 2073{
2074 int rval;
2075 uint16_t loop_id;
2076 uint16_t topo;
2c3dfe3f 2077 uint16_t sw_cap;
1da177e4
LT		 2078 uint8_t al_pa;
2079 uint8_t area;
2080 uint8_t domain;
2081 char connect_type[22];
e315cd28 2082 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2083
2084 /* Get host addresses. */
e315cd28 2085 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 2086 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 2087 if (rval != QLA_SUCCESS) {
e315cd28 2088 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 2089 IS_CNA_CAPABLE(ha) ||
33135aa2 2090 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 2091 ql_dbg(ql_dbg_disc, vha, 0x2008,
2092 "Loop is in a transition state.\n");
33135aa2 2093 } else {
7c3df132
SK		 2094 ql_log(ql_log_warn, vha, 0x2009,
2095 "Unable to get host loop ID.\n");
e315cd28 2096 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 2097 }
1da177e4
LT		 2098 return (rval);
2099 }
2100
2101 if (topo == 4) {
7c3df132
SK		 2102 ql_log(ql_log_info, vha, 0x200a,
2103 "Cannot get topology - retrying.\n");
1da177e4
LT		 2104 return (QLA_FUNCTION_FAILED);
2105 }
2106
e315cd28 2107 vha->loop_id = loop_id;
1da177e4
LT		 2108
2109 /* initialize */
2110 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2111 ha->operating_mode = LOOP;
2c3dfe3f 2112 ha->switch_cap = 0;
1da177e4
LT		 2113
2114 switch (topo) {
2115 case 0:
7c3df132 2116 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 2117 ha->current_topology = ISP_CFG_NL;
2118 strcpy(connect_type, "(Loop)");
2119 break;
2120
2121 case 1:
7c3df132 2122 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 2123 ha->switch_cap = sw_cap;
1da177e4
LT		 2124 ha->current_topology = ISP_CFG_FL;
2125 strcpy(connect_type, "(FL_Port)");
2126 break;
2127
2128 case 2:
7c3df132 2129 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 2130 ha->operating_mode = P2P;
2131 ha->current_topology = ISP_CFG_N;
2132 strcpy(connect_type, "(N_Port-to-N_Port)");
2133 break;
2134
2135 case 3:
7c3df132 2136 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 2137 ha->switch_cap = sw_cap;
1da177e4
LT		 2138 ha->operating_mode = P2P;
2139 ha->current_topology = ISP_CFG_F;
2140 strcpy(connect_type, "(F_Port)");
2141 break;
2142
2143 default:
7c3df132
SK		 2144 ql_dbg(ql_dbg_disc, vha, 0x200f,
2145 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 2146 ha->current_topology = ISP_CFG_NL;
2147 strcpy(connect_type, "(Loop)");
2148 break;
2149 }
2150
2151 /* Save Host port and loop ID. */
2152 /* byte order - Big Endian */
e315cd28
AC		 2153 vha->d_id.b.domain = domain;
2154 vha->d_id.b.area = area;
2155 vha->d_id.b.al_pa = al_pa;
1da177e4 2156
2d70c103
NB		 2157 spin_lock(&ha->vport_slock);
2158 qlt_update_vp_map(vha, SET_AL_PA);
2159 spin_unlock(&ha->vport_slock);
2160
e315cd28 2161 if (!vha->flags.init_done)
7c3df132
SK		 2162 ql_log(ql_log_info, vha, 0x2010,
2163 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 2164 connect_type, vha->loop_id);
1da177e4
LT		 2165
2166 if (rval) {
7c3df132
SK		 2167 ql_log(ql_log_warn, vha, 0x2011,
2168 "%s FAILED\n", __func__);
1da177e4 2169 } else {
7c3df132
SK		 2170 ql_dbg(ql_dbg_disc, vha, 0x2012,
2171 "%s success\n", __func__);
1da177e4
LT		 2172 }
2173
2174 return(rval);
2175}
2176
a9083016 2177inline void
e315cd28
AC		 2178qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2179 char *def)
9bb9fcf2
AV		 2180{
2181 char *st, *en;
2182 uint16_t index;
e315cd28 2183 struct qla_hw_data *ha = vha->hw;
ab671149 2184 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 2185 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 2186
2187 if (memcmp(model, BINZERO, len) != 0) {
2188 strncpy(ha->model_number, model, len);
2189 st = en = ha->model_number;
2190 en += len - 1;
2191 while (en > st) {
2192 if (*en != 0x20 && *en != 0x00)
2193 break;
2194 *en-- = '\0';
2195 }
2196
2197 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2198 if (use_tbl &&
2199 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 2200 index < QLA_MODEL_NAMES)
1ee27146
JC		 2201 strncpy(ha->model_desc,
2202 qla2x00_model_name[index * 2 + 1],
2203 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2204 } else {
2205 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 2206 if (use_tbl &&
2207 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 2208 index < QLA_MODEL_NAMES) {
2209 strcpy(ha->model_number,
2210 qla2x00_model_name[index * 2]);
1ee27146
JC		 2211 strncpy(ha->model_desc,
2212 qla2x00_model_name[index * 2 + 1],
2213 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 2214 } else {
2215 strcpy(ha->model_number, def);
2216 }
2217 }
1ee27146 2218 if (IS_FWI2_CAPABLE(ha))
e315cd28 2219 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 2220 sizeof(ha->model_desc));
9bb9fcf2
AV		 2221}
2222
4e08df3f
DM		 2223/* On sparc systems, obtain port and node WWN from firmware
2224 * properties.
2225 */
e315cd28 2226static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 2227{
2228#ifdef CONFIG_SPARC
e315cd28 2229 struct qla_hw_data *ha = vha->hw;
4e08df3f 2230 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 2231 struct device_node *dp = pci_device_to_OF_node(pdev);
2232 const u8 *val;
4e08df3f
DM		 2233 int len;
2234
2235 val = of_get_property(dp, "port-wwn", &len);
2236 if (val && len >= WWN_SIZE)
2237 memcpy(nv->port_name, val, WWN_SIZE);
2238
2239 val = of_get_property(dp, "node-wwn", &len);
2240 if (val && len >= WWN_SIZE)
2241 memcpy(nv->node_name, val, WWN_SIZE);
2242#endif
2243}
2244
1da177e4
LT		 2245/*
2246* NVRAM configuration for ISP 2xxx
2247*
2248* Input:
2249* ha = adapter block pointer.
2250*
2251* Output:
2252* initialization control block in response_ring
2253* host adapters parameters in host adapter block
2254*
2255* Returns:
2256* 0 = success.
2257*/
abbd8870 2258int
e315cd28 2259qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 2260{
4e08df3f 2261 int rval;
0107109e
AV		 2262 uint8_t chksum = 0;
2263 uint16_t cnt;
2264 uint8_t *dptr1, *dptr2;
e315cd28 2265 struct qla_hw_data *ha = vha->hw;
0107109e 2266 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 2267 nvram_t *nv = ha->nvram;
2268 uint8_t *ptr = ha->nvram;
3d71644c 2269 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 2270
4e08df3f
DM		 2271 rval = QLA_SUCCESS;
2272
1da177e4 2273 /* Determine NVRAM starting address. */
0107109e 2274 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 2275 ha->nvram_base = 0;
2276 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2277 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
2278 ha->nvram_base = 0x80;
2279
2280 /* Get NVRAM data and calculate checksum. */
e315cd28 2281 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 2282 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2283 chksum += *ptr++;
1da177e4 2284
7c3df132
SK		 2285 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2286 "Contents of NVRAM.\n");
2287 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2288 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 2289
2290 /* Bad NVRAM data, set defaults parameters. */
2291 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2292 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2293 /* Reset NVRAM data. */
7c3df132 2294 ql_log(ql_log_warn, vha, 0x0064,
9e336520 2295 "Inconsistent NVRAM "
7c3df132
SK		 2296 "detected: checksum=0x%x id=%c version=0x%x.\n",
2297 chksum, nv->id[0], nv->nvram_version);
2298 ql_log(ql_log_warn, vha, 0x0065,
2299 "Falling back to "
2300 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 2301
2302 /*
2303 * Set default initialization control block.
2304 */
2305 memset(nv, 0, ha->nvram_size);
2306 nv->parameter_block_version = ICB_VERSION;
2307
2308 if (IS_QLA23XX(ha)) {
2309 nv->firmware_options[0] = BIT_2 | BIT_1;
2310 nv->firmware_options[1] = BIT_7 | BIT_5;
2311 nv->add_firmware_options[0] = BIT_5;
2312 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2313 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2314 nv->special_options[1] = BIT_7;
2315 } else if (IS_QLA2200(ha)) {
2316 nv->firmware_options[0] = BIT_2 | BIT_1;
2317 nv->firmware_options[1] = BIT_7 | BIT_5;
2318 nv->add_firmware_options[0] = BIT_5;
2319 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2320 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2321 } else if (IS_QLA2100(ha)) {
2322 nv->firmware_options[0] = BIT_3 | BIT_1;
2323 nv->firmware_options[1] = BIT_5;
2324 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2325 }
2326
2327 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2328 nv->execution_throttle = __constant_cpu_to_le16(16);
2329 nv->retry_count = 8;
2330 nv->retry_delay = 1;
2331
2332 nv->port_name[0] = 33;
2333 nv->port_name[3] = 224;
2334 nv->port_name[4] = 139;
2335
e315cd28 2336 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 2337
2338 nv->login_timeout = 4;
2339
2340 /*
2341 * Set default host adapter parameters
2342 */
2343 nv->host_p[1] = BIT_2;
2344 nv->reset_delay = 5;
2345 nv->port_down_retry_count = 8;
2346 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2347 nv->link_down_timeout = 60;
2348
2349 rval = 1;
1da177e4
LT		 2350 }
2351
2352#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2353 /*
2354 * The SN2 does not provide BIOS emulation which means you can't change
2355 * potentially bogus BIOS settings. Force the use of default settings
2356 * for link rate and frame size. Hope that the rest of the settings
2357 * are valid.
2358 */
2359 if (ia64_platform_is("sn2")) {
2360 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2361 if (IS_QLA23XX(ha))
2362 nv->special_options[1] = BIT_7;
2363 }
2364#endif
2365
2366 /* Reset Initialization control block */
0107109e 2367 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 2368
2369 /*
2370 * Setup driver NVRAM options.
2371 */
2372 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2373 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2374 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2375 nv->firmware_options[1] &= ~BIT_4;
2376
2377 if (IS_QLA23XX(ha)) {
2378 nv->firmware_options[0] |= BIT_2;
2379 nv->firmware_options[0] &= ~BIT_3;
2d70c103 2380 nv->special_options[0] &= ~BIT_6;
0107109e 2381 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 2382
2383 if (IS_QLA2300(ha)) {
2384 if (ha->fb_rev == FPM_2310) {
2385 strcpy(ha->model_number, "QLA2310");
2386 } else {
2387 strcpy(ha->model_number, "QLA2300");
2388 }
2389 } else {
e315cd28 2390 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 2391 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 2392 }
2393 } else if (IS_QLA2200(ha)) {
2394 nv->firmware_options[0] |= BIT_2;
2395 /*
2396 * 'Point-to-point preferred, else loop' is not a safe
2397 * connection mode setting.
2398 */
2399 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2400 (BIT_5 | BIT_4)) {
2401 /* Force 'loop preferred, else point-to-point'. */
2402 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2403 nv->add_firmware_options[0] |= BIT_5;
2404 }
2405 strcpy(ha->model_number, "QLA22xx");
2406 } else /*if (IS_QLA2100(ha))*/ {
2407 strcpy(ha->model_number, "QLA2100");
2408 }
2409
2410 /*
2411 * Copy over NVRAM RISC parameter block to initialization control block.
2412 */
2413 dptr1 = (uint8_t *)icb;
2414 dptr2 = (uint8_t *)&nv->parameter_block_version;
2415 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2416 while (cnt--)
2417 *dptr1++ = *dptr2++;
2418
2419 /* Copy 2nd half. */
2420 dptr1 = (uint8_t *)icb->add_firmware_options;
2421 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2422 while (cnt--)
2423 *dptr1++ = *dptr2++;
2424
5341e868
AV		 2425 /* Use alternate WWN? */
2426 if (nv->host_p[1] & BIT_7) {
2427 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2428 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2429 }
2430
1da177e4
LT		 2431 /* Prepare nodename */
2432 if ((icb->firmware_options[1] & BIT_6) == 0) {
2433 /*
2434 * Firmware will apply the following mask if the nodename was
2435 * not provided.
2436 */
2437 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2438 icb->node_name[0] &= 0xF0;
2439 }
2440
2441 /*
2442 * Set host adapter parameters.
2443 */
3ce8866c
SK		 2444
2445 /*
2446 * BIT_7 in the host-parameters section allows for modification to
2447 * internal driver logging.
2448 */
0181944f 2449 if (nv->host_p[0] & BIT_7)
cfb0919c 2450 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 2451 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2452 /* Always load RISC code on non ISP2[12]00 chips. */
2453 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2454 ha->flags.disable_risc_code_load = 0;
2455 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2456 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2457 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 2458 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 2459 ha->flags.disable_serdes = 0;
1da177e4
LT		 2460
2461 ha->operating_mode =
2462 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2463
2464 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2465 sizeof(ha->fw_seriallink_options));
2466
2467 /* save HBA serial number */
2468 ha->serial0 = icb->port_name[5];
2469 ha->serial1 = icb->port_name[6];
2470 ha->serial2 = icb->port_name[7];
e315cd28
AC		 2471 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2472 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4
LT		 2473
2474 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2475
2476 ha->retry_count = nv->retry_count;
2477
2478 /* Set minimum login_timeout to 4 seconds. */
5b91490e 2479 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 2480 nv->login_timeout = ql2xlogintimeout;
2481 if (nv->login_timeout < 4)
2482 nv->login_timeout = 4;
2483 ha->login_timeout = nv->login_timeout;
2484 icb->login_timeout = nv->login_timeout;
2485
00a537b8
AV		 2486 /* Set minimum RATOV to 100 tenths of a second. */
2487 ha->r_a_tov = 100;
1da177e4 2488
1da177e4
LT		 2489 ha->loop_reset_delay = nv->reset_delay;
2490
1da177e4
LT		 2491 /* Link Down Timeout = 0:
2492 *
2493 * When Port Down timer expires we will start returning
2494 * I/O's to OS with "DID_NO_CONNECT".
2495 *
2496 * Link Down Timeout != 0:
2497 *
2498 * The driver waits for the link to come up after link down
2499 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 2500 */
1da177e4
LT		 2501 if (nv->link_down_timeout == 0) {
2502 ha->loop_down_abort_time =
354d6b21 2503 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 2504 } else {
2505 ha->link_down_timeout = nv->link_down_timeout;
2506 ha->loop_down_abort_time =
2507 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 2508 }
1da177e4 2509
1da177e4
LT		 2510 /*
2511 * Need enough time to try and get the port back.
2512 */
2513 ha->port_down_retry_count = nv->port_down_retry_count;
2514 if (qlport_down_retry)
2515 ha->port_down_retry_count = qlport_down_retry;
2516 /* Set login_retry_count */
2517 ha->login_retry_count = nv->retry_count;
2518 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2519 ha->port_down_retry_count > 3)
2520 ha->login_retry_count = ha->port_down_retry_count;
2521 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2522 ha->login_retry_count = ha->port_down_retry_count;
2523 if (ql2xloginretrycount)
2524 ha->login_retry_count = ql2xloginretrycount;
2525
1da177e4
LT		 2526 icb->lun_enables = __constant_cpu_to_le16(0);
2527 icb->command_resource_count = 0;
2528 icb->immediate_notify_resource_count = 0;
2529 icb->timeout = __constant_cpu_to_le16(0);
2530
2531 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2532 /* Enable RIO */
2533 icb->firmware_options[0] &= ~BIT_3;
2534 icb->add_firmware_options[0] &=
2535 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2536 icb->add_firmware_options[0] |= BIT_2;
2537 icb->response_accumulation_timer = 3;
2538 icb->interrupt_delay_timer = 5;
2539
e315cd28 2540 vha->flags.process_response_queue = 1;
1da177e4 2541 } else {
4fdfefe5 2542 /* Enable ZIO. */
e315cd28 2543 if (!vha->flags.init_done) {
4fdfefe5
AV		 2544 ha->zio_mode = icb->add_firmware_options[0] &
2545 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2546 ha->zio_timer = icb->interrupt_delay_timer ?
2547 icb->interrupt_delay_timer: 2;
2548 }
1da177e4
LT		 2549 icb->add_firmware_options[0] &=
2550 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 2551 vha->flags.process_response_queue = 0;
4fdfefe5 2552 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 2553 ha->zio_mode = QLA_ZIO_MODE_6;
2554
7c3df132 2555 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 2556 "ZIO mode %d enabled; timer delay (%d us).\n",
2557 ha->zio_mode, ha->zio_timer * 100);
1da177e4 2558
4fdfefe5
AV		 2559 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2560 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 2561 vha->flags.process_response_queue = 1;
1da177e4
LT		 2562 }
2563 }
2564
4e08df3f 2565 if (rval) {
7c3df132
SK		 2566 ql_log(ql_log_warn, vha, 0x0069,
2567 "NVRAM configuration failed.\n");
4e08df3f
DM		 2568 }
2569 return (rval);
1da177e4
LT		 2570}
2571
19a7b4ae
JSEC		 2572static void
2573qla2x00_rport_del(void *data)
2574{
2575 fc_port_t *fcport = data;
d97994dc 2576 struct fc_rport *rport;
2d70c103 2577 scsi_qla_host_t *vha = fcport->vha;
044d78e1 2578 unsigned long flags;
d97994dc 2579
044d78e1 2580 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 2581 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 2582 fcport->drport = NULL;
044d78e1 2583 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2d70c103 2584 if (rport) {
d97994dc 2585 fc_remote_port_delete(rport);
2d70c103
NB		 2586 /*
2587 * Release the target mode FC NEXUS in qla_target.c code
2588 * if target mod is enabled.
2589 */
2590 qlt_fc_port_deleted(vha, fcport);
2591 }
19a7b4ae
JSEC		 2592}
2593
1da177e4
LT		 2594/**
2595 * qla2x00_alloc_fcport() - Allocate a generic fcport.
2596 * @ha: HA context
2597 * @flags: allocation flags
2598 *
2599 * Returns a pointer to the allocated fcport, or NULL, if none available.
2600 */
9a069e19 2601fc_port_t *
e315cd28 2602qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 2603{
2604 fc_port_t *fcport;
2605
bbfbbbc1
MK		 2606 fcport = kzalloc(sizeof(fc_port_t), flags);
2607 if (!fcport)
2608 return NULL;
1da177e4
LT		 2609
2610 /* Setup fcport template structure. */
e315cd28 2611 fcport->vha = vha;
1da177e4
LT		 2612 fcport->port_type = FCT_UNKNOWN;
2613 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 2614 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 2615 fcport->supported_classes = FC_COS_UNSPECIFIED;
c0822b63 2616 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 2617
bbfbbbc1 2618 return fcport;
1da177e4
LT		 2619}
2620
2621/*
2622 * qla2x00_configure_loop
2623 * Updates Fibre Channel Device Database with what is actually on loop.
2624 *
2625 * Input:
2626 * ha = adapter block pointer.
2627 *
2628 * Returns:
2629 * 0 = success.
2630 * 1 = error.
2631 * 2 = database was full and device was not configured.
2632 */
2633static int
e315cd28 2634qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2635{
2636 int rval;
2637 unsigned long flags, save_flags;
e315cd28 2638 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2639 rval = QLA_SUCCESS;
2640
2641 /* Get Initiator ID */
e315cd28
AC		 2642 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2643 rval = qla2x00_configure_hba(vha);
1da177e4 2644 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2645 ql_dbg(ql_dbg_disc, vha, 0x2013,
2646 "Unable to configure HBA.\n");
1da177e4
LT		 2647 return (rval);
2648 }
2649 }
2650
e315cd28 2651 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 2652 ql_dbg(ql_dbg_disc, vha, 0x2014,
2653 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 2654
2655 /*
2656 * If we have both an RSCN and PORT UPDATE pending then handle them
2657 * both at the same time.
2658 */
e315cd28
AC		 2659 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2660 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 2661
3064ff39
MH		 2662 qla2x00_get_data_rate(vha);
2663
1da177e4
LT		 2664 /* Determine what we need to do */
2665 if (ha->current_topology == ISP_CFG_FL &&
2666 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2667
1da177e4
LT		 2668 set_bit(RSCN_UPDATE, &flags);
2669
2670 } else if (ha->current_topology == ISP_CFG_F &&
2671 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2672
1da177e4
LT		 2673 set_bit(RSCN_UPDATE, &flags);
2674 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 2675
2676 } else if (ha->current_topology == ISP_CFG_N) {
2677 clear_bit(RSCN_UPDATE, &flags);
1da177e4 2678
e315cd28 2679 } else if (!vha->flags.online ||
1da177e4
LT		 2680 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2681
1da177e4
LT		 2682 set_bit(RSCN_UPDATE, &flags);
2683 set_bit(LOCAL_LOOP_UPDATE, &flags);
2684 }
2685
2686 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 2687 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2688 ql_dbg(ql_dbg_disc, vha, 0x2015,
2689 "Loop resync needed, failing.\n");
1da177e4 2690 rval = QLA_FUNCTION_FAILED;
642ef983 2691 } else
e315cd28 2692 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 2693 }
2694
2695 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132
SK		 2696 if (LOOP_TRANSITION(vha)) {
2697 ql_dbg(ql_dbg_disc, vha, 0x201e,
2698 "Needs RSCN update and loop transition.\n");
1da177e4 2699 rval = QLA_FUNCTION_FAILED;
7c3df132 2700 }
e315cd28
AC		 2701 else
2702 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 2703 }
2704
2705 if (rval == QLA_SUCCESS) {
e315cd28
AC		 2706 if (atomic_read(&vha->loop_down_timer) ||
2707 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 2708 rval = QLA_FUNCTION_FAILED;
2709 } else {
e315cd28 2710 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 2711 ql_dbg(ql_dbg_disc, vha, 0x2069,
2712 "LOOP READY.\n");
1da177e4
LT		 2713 }
2714 }
2715
2716 if (rval) {
7c3df132
SK		 2717 ql_dbg(ql_dbg_disc, vha, 0x206a,
2718 "%s *** FAILED ***.\n", __func__);
1da177e4 2719 } else {
7c3df132
SK		 2720 ql_dbg(ql_dbg_disc, vha, 0x206b,
2721 "%s: exiting normally.\n", __func__);
1da177e4
LT		 2722 }
2723
cc3ef7bc 2724 /* Restore state if a resync event occurred during processing */
e315cd28 2725 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 2726 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 2727 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 2728 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 2729 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 2730 }
1da177e4
LT		 2731 }
2732
2733 return (rval);
2734}
2735
2736
2737
2738/*
2739 * qla2x00_configure_local_loop
2740 * Updates Fibre Channel Device Database with local loop devices.
2741 *
2742 * Input:
2743 * ha = adapter block pointer.
2744 *
2745 * Returns:
2746 * 0 = success.
2747 */
2748static int
e315cd28 2749qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 2750{
2751 int rval, rval2;
2752 int found_devs;
2753 int found;
2754 fc_port_t *fcport, *new_fcport;
2755
2756 uint16_t index;
2757 uint16_t entries;
2758 char *id_iter;
2759 uint16_t loop_id;
2760 uint8_t domain, area, al_pa;
e315cd28 2761 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 2762
2763 found_devs = 0;
2764 new_fcport = NULL;
642ef983 2765 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 2766
7c3df132
SK		 2767 ql_dbg(ql_dbg_disc, vha, 0x2016,
2768 "Getting FCAL position map.\n");
2769 if (ql2xextended_error_logging & ql_dbg_disc)
2770 qla2x00_get_fcal_position_map(vha, NULL);
1da177e4
LT		 2771
2772 /* Get list of logged in devices. */
642ef983 2773 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 2774 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 2775 &entries);
2776 if (rval != QLA_SUCCESS)
2777 goto cleanup_allocation;
2778
7c3df132
SK		 2779 ql_dbg(ql_dbg_disc, vha, 0x2017,
2780 "Entries in ID list (%d).\n", entries);
2781 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2782 (uint8_t *)ha->gid_list,
2783 entries * sizeof(struct gid_list_info));
1da177e4
LT		 2784
2785 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 2786 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2787 if (new_fcport == NULL) {
7c3df132
SK		 2788 ql_log(ql_log_warn, vha, 0x2018,
2789 "Memory allocation failed for fcport.\n");
1da177e4
LT		 2790 rval = QLA_MEMORY_ALLOC_FAILED;
2791 goto cleanup_allocation;
2792 }
2793 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2794
2795 /*
2796 * Mark local devices that were present with FCF_DEVICE_LOST for now.
2797 */
e315cd28 2798 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2799 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2800 fcport->port_type != FCT_BROADCAST &&
2801 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2802
7c3df132
SK		 2803 ql_dbg(ql_dbg_disc, vha, 0x2019,
2804 "Marking port lost loop_id=0x%04x.\n",
2805 fcport->loop_id);
1da177e4 2806
ec426e10 2807 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2808 }
2809 }
2810
2811 /* Add devices to port list. */
2812 id_iter = (char *)ha->gid_list;
2813 for (index = 0; index < entries; index++) {
2814 domain = ((struct gid_list_info *)id_iter)->domain;
2815 area = ((struct gid_list_info *)id_iter)->area;
2816 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 2817 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 2818 loop_id = (uint16_t)
2819 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 2820 else
1da177e4
LT		 2821 loop_id = le16_to_cpu(
2822 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 2823 id_iter += ha->gid_list_info_size;
1da177e4
LT		 2824
2825 /* Bypass reserved domain fields. */
2826 if ((domain & 0xf0) == 0xf0)
2827 continue;
2828
2829 /* Bypass if not same domain and area of adapter. */
f7d289f6 2830 if (area && domain &&
e315cd28 2831 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 2832 continue;
2833
2834 /* Bypass invalid local loop ID. */
2835 if (loop_id > LAST_LOCAL_LOOP_ID)
2836 continue;
2837
370d550e
AE		 2838 memset(new_fcport, 0, sizeof(fc_port_t));
2839
1da177e4
LT		 2840 /* Fill in member data. */
2841 new_fcport->d_id.b.domain = domain;
2842 new_fcport->d_id.b.area = area;
2843 new_fcport->d_id.b.al_pa = al_pa;
2844 new_fcport->loop_id = loop_id;
e315cd28 2845 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 2846 if (rval2 != QLA_SUCCESS) {
7c3df132
SK		 2847 ql_dbg(ql_dbg_disc, vha, 0x201a,
2848 "Failed to retrieve fcport information "
2849 "-- get_port_database=%x, loop_id=0x%04x.\n",
2850 rval2, new_fcport->loop_id);
2851 ql_dbg(ql_dbg_disc, vha, 0x201b,
2852 "Scheduling resync.\n");
e315cd28 2853 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 2854 continue;
2855 }
2856
2857 /* Check for matching device in port list. */
2858 found = 0;
2859 fcport = NULL;
e315cd28 2860 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 2861 if (memcmp(new_fcport->port_name, fcport->port_name,
2862 WWN_SIZE))
2863 continue;
2864
ddb9b126 2865 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 2866 fcport->loop_id = new_fcport->loop_id;
2867 fcport->port_type = new_fcport->port_type;
2868 fcport->d_id.b24 = new_fcport->d_id.b24;
2869 memcpy(fcport->node_name, new_fcport->node_name,
2870 WWN_SIZE);
2871
2872 found++;
2873 break;
2874 }
2875
2876 if (!found) {
2877 /* New device, add to fcports list. */
e315cd28 2878 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 2879
2880 /* Allocate a new replacement fcport. */
2881 fcport = new_fcport;
e315cd28 2882 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 2883 if (new_fcport == NULL) {
7c3df132
SK		 2884 ql_log(ql_log_warn, vha, 0x201c,
2885 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 2886 rval = QLA_MEMORY_ALLOC_FAILED;
2887 goto cleanup_allocation;
2888 }
2889 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2890 }
2891
d8b45213 2892 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 2893 fcport->fp_speed = ha->link_data_rate;
d8b45213 2894
e315cd28 2895 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 2896
2897 found_devs++;
2898 }
2899
2900cleanup_allocation:
c9475cb0 2901 kfree(new_fcport);
1da177e4
LT		 2902
2903 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2904 ql_dbg(ql_dbg_disc, vha, 0x201d,
2905 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 2906 }
2907
1da177e4
LT		 2908 return (rval);
2909}
2910
d8b45213 2911static void
e315cd28 2912qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 2913{
9f8fddee 2914 char *link_speed;
d8b45213 2915 int rval;
1bb39548 2916 uint16_t mb[4];
e315cd28 2917 struct qla_hw_data *ha = vha->hw;
d8b45213 2918
c76f2c01 2919 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 2920 return;
2921
c9afb9a2
GM		 2922 if (atomic_read(&fcport->state) != FCS_ONLINE)
2923 return;
2924
39bd9622
AV		 2925 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
2926 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 2927 return;
2928
e315cd28 2929 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 2930 mb);
d8b45213 2931 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2932 ql_dbg(ql_dbg_disc, vha, 0x2004,
2933 "Unable to adjust iIDMA "
2934 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
2935 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
d8b45213
AV		 2936 fcport->port_name[2], fcport->port_name[3],
2937 fcport->port_name[4], fcport->port_name[5],
2938 fcport->port_name[6], fcport->port_name[7], rval,
7c3df132 2939 fcport->fp_speed, mb[0], mb[1]);
d8b45213 2940 } else {
daae62a3 2941 link_speed = qla2x00_get_link_speed_str(ha);
7c3df132
SK		 2942 ql_dbg(ql_dbg_disc, vha, 0x2005,
2943 "iIDMA adjusted to %s GB/s "
2944 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
2945 fcport->port_name[0], fcport->port_name[1],
2946 fcport->port_name[2], fcport->port_name[3],
2947 fcport->port_name[4], fcport->port_name[5],
2948 fcport->port_name[6], fcport->port_name[7]);
d8b45213
AV		 2949 }
2950}
2951
23be331d 2952static void
e315cd28 2953qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 2954{
2955 struct fc_rport_identifiers rport_ids;
bdf79621 2956 struct fc_rport *rport;
044d78e1 2957 unsigned long flags;
8482e118 2958
ac280b67 2959 qla2x00_rport_del(fcport);
8482e118 2960
f8b02a85
AV		 2961 rport_ids.node_name = wwn_to_u64(fcport->node_name);
2962 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 2963 rport_ids.port_id = fcport->d_id.b.domain << 16 |
2964 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 2965 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 2966 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 2967 if (!rport) {
7c3df132
SK		 2968 ql_log(ql_log_warn, vha, 0x2006,
2969 "Unable to allocate fc remote port.\n");
77d74143
AV		 2970 return;
2971 }
2d70c103
NB		 2972 /*
2973 * Create target mode FC NEXUS in qla_target.c if target mode is
2974 * enabled..
2975 */
2976 qlt_fc_port_added(vha, fcport);
2977
044d78e1 2978 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 2979 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 2980 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 2981
ad3e0eda 2982 rport->supported_classes = fcport->supported_classes;
77d74143 2983
8482e118
AV		 2984 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
2985 if (fcport->port_type == FCT_INITIATOR)
2986 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
2987 if (fcport->port_type == FCT_TARGET)
2988 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
77d74143 2989 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 2990}
2991
23be331d
AB		 2992/*
2993 * qla2x00_update_fcport
2994 * Updates device on list.
2995 *
2996 * Input:
2997 * ha = adapter block pointer.
2998 * fcport = port structure pointer.
2999 *
3000 * Return:
3001 * 0 - Success
3002 * BIT_0 - error
3003 *
3004 * Context:
3005 * Kernel context.
3006 */
3007void
e315cd28 3008qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 3009{
e315cd28 3010 fcport->vha = vha;
23be331d 3011 fcport->login_retry = 0;
5ff1d584 3012 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
23be331d 3013
e315cd28 3014 qla2x00_iidma_fcport(vha, fcport);
21090cbe 3015 qla24xx_update_fcport_fcp_prio(vha, fcport);
e315cd28 3016 qla2x00_reg_remote_port(vha, fcport);
ec426e10 3017 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
23be331d
AB		 3018}
3019
1da177e4
LT		 3020/*
3021 * qla2x00_configure_fabric
3022 * Setup SNS devices with loop ID's.
3023 *
3024 * Input:
3025 * ha = adapter block pointer.
3026 *
3027 * Returns:
3028 * 0 = success.
3029 * BIT_0 = error
3030 */
3031static int
e315cd28 3032qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 3033{
b3b02e6e 3034 int rval;
4dc77c36 3035 fc_port_t *fcport;
1da177e4
LT		 3036 uint16_t next_loopid;
3037 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 3038 uint16_t loop_id;
1da177e4 3039 LIST_HEAD(new_fcports);
e315cd28
AC		 3040 struct qla_hw_data *ha = vha->hw;
3041 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 3042
3043 /* If FL port exists, then SNS is present */
e428924c 3044 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3045 loop_id = NPH_F_PORT;
3046 else
3047 loop_id = SNS_FL_PORT;
e315cd28 3048 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 3049 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3050 ql_dbg(ql_dbg_disc, vha, 0x201f,
3051 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 3052
e315cd28 3053 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 3054 return (QLA_SUCCESS);
3055 }
e315cd28 3056 vha->device_flags |= SWITCH_FOUND;
1da177e4 3057
1da177e4 3058 do {
cca5335c
AV		 3059 /* FDMI support. */
3060 if (ql2xfdmienable &&
e315cd28
AC		 3061 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
3062 qla2x00_fdmi_register(vha);
cca5335c 3063
1da177e4 3064 /* Ensure we are logged into the SNS. */
e428924c 3065 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 3066 loop_id = NPH_SNS;
3067 else
3068 loop_id = SIMPLE_NAME_SERVER;
0b91d116
CD		 3069 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
3070 0xfc, mb, BIT_1|BIT_0);
3071 if (rval != QLA_SUCCESS) {
3072 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4dc77c36 3073 break;
0b91d116 3074 }
1da177e4 3075 if (mb[0] != MBS_COMMAND_COMPLETE) {
7c3df132
SK		 3076 ql_dbg(ql_dbg_disc, vha, 0x2042,
3077 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
3078 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
3079 mb[2], mb[6], mb[7]);
1da177e4
LT		 3080 return (QLA_SUCCESS);
3081 }
3082
e315cd28
AC		 3083 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3084 if (qla2x00_rft_id(vha)) {
1da177e4 3085 /* EMPTY */
7c3df132
SK		 3086 ql_dbg(ql_dbg_disc, vha, 0x2045,
3087 "Register FC-4 TYPE failed.\n");
1da177e4 3088 }
e315cd28 3089 if (qla2x00_rff_id(vha)) {
1da177e4 3090 /* EMPTY */
7c3df132
SK		 3091 ql_dbg(ql_dbg_disc, vha, 0x2049,
3092 "Register FC-4 Features failed.\n");
1da177e4 3093 }
e315cd28 3094 if (qla2x00_rnn_id(vha)) {
1da177e4 3095 /* EMPTY */
7c3df132
SK		 3096 ql_dbg(ql_dbg_disc, vha, 0x204f,
3097 "Register Node Name failed.\n");
e315cd28 3098 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 3099 /* EMPTY */
7c3df132
SK		 3100 ql_dbg(ql_dbg_disc, vha, 0x2053,
3101 "Register Symobilic Node Name failed.\n");
1da177e4
LT		 3102 }
3103 }
3104
e315cd28 3105 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
1da177e4
LT		 3106 if (rval != QLA_SUCCESS)
3107 break;
3108
4dc77c36
JC		 3109 /* Add new ports to existing port list */
3110 list_splice_tail_init(&new_fcports, &vha->vp_fcports);
3111
3112 /* Starting free loop ID. */
3113 next_loopid = ha->min_external_loopid;
3114
e315cd28
AC		 3115 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3116 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1da177e4
LT		 3117 break;
3118
3119 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3120 continue;
3121
4dc77c36 3122 /* Logout lost/gone fabric devices (non-FCP2) */
c0822b63 3123 if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND &&
b3b02e6e 3124 atomic_read(&fcport->state) == FCS_ONLINE) {
e315cd28 3125 qla2x00_mark_device_lost(vha, fcport,
d97994dc 3126 ql2xplogiabsentdevice, 0);
1da177e4 3127 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3128 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
1da177e4
LT		 3129 fcport->port_type != FCT_INITIATOR &&
3130 fcport->port_type != FCT_BROADCAST) {
e315cd28 3131 ha->isp_ops->fabric_logout(vha,
1c7c6357
AV		 3132 fcport->loop_id,
3133 fcport->d_id.b.domain,
3134 fcport->d_id.b.area,
3135 fcport->d_id.b.al_pa);
1da177e4 3136 }
c0822b63 3137 continue;
1da177e4 3138 }
c0822b63 3139 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
1da177e4 3140
4dc77c36
JC		 3141 /* Login fabric devices that need a login */
3142 if ((fcport->flags & FCF_LOGIN_NEEDED) != 0 &&
3143 atomic_read(&vha->loop_down_timer) == 0) {
3144 if (fcport->loop_id == FC_NO_LOOP_ID) {
3145 fcport->loop_id = next_loopid;
3146 rval = qla2x00_find_new_loop_id(
3147 base_vha, fcport);
3148 if (rval != QLA_SUCCESS) {
3149 /* Ran out of IDs to use */
3150 continue;
3151 }
1da177e4
LT		 3152 }
3153 }
1da177e4 3154
bdf79621 3155 /* Login and update database */
e315cd28 3156 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
1da177e4
LT		 3157 }
3158 } while (0);
3159
1da177e4 3160 if (rval) {
7c3df132
SK		 3161 ql_dbg(ql_dbg_disc, vha, 0x2068,
3162 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 3163 }
3164
3165 return (rval);
3166}
3167
1da177e4
LT		 3168/*
3169 * qla2x00_find_all_fabric_devs
3170 *
3171 * Input:
3172 * ha = adapter block pointer.
3173 * dev = database device entry pointer.
3174 *
3175 * Returns:
3176 * 0 = success.
3177 *
3178 * Context:
3179 * Kernel context.
3180 */
3181static int
e315cd28
AC		 3182qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3183 struct list_head *new_fcports)
1da177e4
LT		 3184{
3185 int rval;
3186 uint16_t loop_id;
3187 fc_port_t *fcport, *new_fcport, *fcptemp;
3188 int found;
3189
3190 sw_info_t *swl;
3191 int swl_idx;
3192 int first_dev, last_dev;
1516ef44 3193 port_id_t wrap = {}, nxt_d_id;
e315cd28
AC		 3194 struct qla_hw_data *ha = vha->hw;
3195 struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
ee546b6e 3196 struct scsi_qla_host *tvp;
1da177e4
LT		 3197
3198 rval = QLA_SUCCESS;
3199
3200 /* Try GID_PT to get device list, else GAN. */
7a67735b 3201 if (!ha->swl)
642ef983 3202 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 3203 GFP_KERNEL);
3204 swl = ha->swl;
bbfbbbc1 3205 if (!swl) {
1da177e4 3206 /*EMPTY*/
7c3df132
SK		 3207 ql_dbg(ql_dbg_disc, vha, 0x2054,
3208 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 3209 } else {
642ef983 3210 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 3211 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 3212 swl = NULL;
e315cd28 3213 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3214 swl = NULL;
e315cd28 3215 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 3216 swl = NULL;
e5896bd5 3217 } else if (ql2xiidmaenable &&
e315cd28
AC		 3218 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3219 qla2x00_gpsc(vha, swl);
1da177e4 3220 }
e8c72ba5
CD		 3221
3222 /* If other queries succeeded probe for FC-4 type */
3223 if (swl)
3224 qla2x00_gff_id(vha, swl);
1da177e4
LT		 3225 }
3226 swl_idx = 0;
3227
3228 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 3229 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3230 if (new_fcport == NULL) {
7c3df132
SK		 3231 ql_log(ql_log_warn, vha, 0x205e,
3232 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 3233 return (QLA_MEMORY_ALLOC_FAILED);
3234 }
3235 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 3236 /* Set start port ID scan at adapter ID. */
3237 first_dev = 1;
3238 last_dev = 0;
3239
3240 /* Starting free loop ID. */
e315cd28
AC		 3241 loop_id = ha->min_external_loopid;
3242 for (; loop_id <= ha->max_loop_id; loop_id++) {
3243 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 3244 continue;
3245
3a6478df
GM		 3246 if (ha->current_topology == ISP_CFG_FL &&
3247 (atomic_read(&vha->loop_down_timer) ||
3248 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 3249 atomic_set(&vha->loop_down_timer, 0);
3250 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3251 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 3252 break;
bb2d52b2 3253 }
1da177e4
LT		 3254
3255 if (swl != NULL) {
3256 if (last_dev) {
3257 wrap.b24 = new_fcport->d_id.b24;
3258 } else {
3259 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3260 memcpy(new_fcport->node_name,
3261 swl[swl_idx].node_name, WWN_SIZE);
3262 memcpy(new_fcport->port_name,
3263 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 3264 memcpy(new_fcport->fabric_port_name,
3265 swl[swl_idx].fabric_port_name, WWN_SIZE);
3266 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 3267 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4
LT		 3268
3269 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3270 last_dev = 1;
3271 }
3272 swl_idx++;
3273 }
3274 } else {
3275 /* Send GA_NXT to the switch */
e315cd28 3276 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 3277 if (rval != QLA_SUCCESS) {
7c3df132
SK		 3278 ql_log(ql_log_warn, vha, 0x2064,
3279 "SNS scan failed -- assuming "
3280 "zero-entry result.\n");
1da177e4
LT		 3281 list_for_each_entry_safe(fcport, fcptemp,
3282 new_fcports, list) {
3283 list_del(&fcport->list);
3284 kfree(fcport);
3285 }
3286 rval = QLA_SUCCESS;
3287 break;
3288 }
3289 }
3290
3291 /* If wrap on switch device list, exit. */
3292 if (first_dev) {
3293 wrap.b24 = new_fcport->d_id.b24;
3294 first_dev = 0;
3295 } else if (new_fcport->d_id.b24 == wrap.b24) {
7c3df132
SK		 3296 ql_dbg(ql_dbg_disc, vha, 0x2065,
3297 "Device wrap (%02x%02x%02x).\n",
3298 new_fcport->d_id.b.domain,
3299 new_fcport->d_id.b.area,
3300 new_fcport->d_id.b.al_pa);
1da177e4
LT		 3301 break;
3302 }
3303
2c3dfe3f 3304 /* Bypass if same physical adapter. */
e315cd28 3305 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 3306 continue;
3307
2c3dfe3f 3308 /* Bypass virtual ports of the same host. */
e315cd28
AC		 3309 found = 0;
3310 if (ha->num_vhosts) {
feafb7b1
AE		 3311 unsigned long flags;
3312
3313 spin_lock_irqsave(&ha->vport_slock, flags);
ee546b6e 3314 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
e315cd28
AC		 3315 if (new_fcport->d_id.b24 == vp->d_id.b24) {
3316 found = 1;
2c3dfe3f 3317 break;
e315cd28 3318 }
2c3dfe3f 3319 }
feafb7b1
AE		 3320 spin_unlock_irqrestore(&ha->vport_slock, flags);
3321
e315cd28 3322 if (found)
2c3dfe3f
SJ		 3323 continue;
3324 }
3325
f7d289f6
AV		 3326 /* Bypass if same domain and area of adapter. */
3327 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 3328 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 3329 ISP_CFG_FL)
3330 continue;
3331
1da177e4
LT		 3332 /* Bypass reserved domain fields. */
3333 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3334 continue;
3335
e8c72ba5 3336 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 3337 if (ql2xgffidenable &&
3338 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3339 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 3340 continue;
3341
1da177e4
LT		 3342 /* Locate matching device in database. */
3343 found = 0;
e315cd28 3344 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 3345 if (memcmp(new_fcport->port_name, fcport->port_name,
3346 WWN_SIZE))
3347 continue;
3348
c0822b63 3349 fcport->scan_state = QLA_FCPORT_SCAN_FOUND;
b3b02e6e 3350
1da177e4
LT		 3351 found++;
3352
d8b45213
AV		 3353 /* Update port state. */
3354 memcpy(fcport->fabric_port_name,
3355 new_fcport->fabric_port_name, WWN_SIZE);
3356 fcport->fp_speed = new_fcport->fp_speed;
3357
1da177e4
LT		 3358 /*
3359 * If address the same and state FCS_ONLINE, nothing
3360 * changed.
3361 */
3362 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3363 atomic_read(&fcport->state) == FCS_ONLINE) {
3364 break;
3365 }
3366
3367 /*
3368 * If device was not a fabric device before.
3369 */
3370 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3371 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 3372 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3373 fcport->flags |= (FCF_FABRIC_DEVICE |
3374 FCF_LOGIN_NEEDED);
1da177e4
LT		 3375 break;
3376 }
3377
3378 /*
3379 * Port ID changed or device was marked to be updated;
3380 * Log it out if still logged in and mark it for
3381 * relogin later.
3382 */
3383 fcport->d_id.b24 = new_fcport->d_id.b24;
3384 fcport->flags |= FCF_LOGIN_NEEDED;
3385 if (fcport->loop_id != FC_NO_LOOP_ID &&
f08b7251 3386 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
0eba25df 3387 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
1da177e4
LT		 3388 fcport->port_type != FCT_INITIATOR &&
3389 fcport->port_type != FCT_BROADCAST) {
e315cd28 3390 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3391 fcport->d_id.b.domain, fcport->d_id.b.area,
3392 fcport->d_id.b.al_pa);
5f16b331 3393 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 3394 }
3395
3396 break;
3397 }
3398
3399 if (found)
3400 continue;
1da177e4
LT		 3401 /* If device was not in our fcports list, then add it. */
3402 list_add_tail(&new_fcport->list, new_fcports);
3403
3404 /* Allocate a new replacement fcport. */
3405 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 3406 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 3407 if (new_fcport == NULL) {
7c3df132
SK		 3408 ql_log(ql_log_warn, vha, 0x2066,
3409 "Memory allocation failed for fcport.\n");
1da177e4
LT		 3410 return (QLA_MEMORY_ALLOC_FAILED);
3411 }
3412 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3413 new_fcport->d_id.b24 = nxt_d_id.b24;
3414 }
3415
c9475cb0 3416 kfree(new_fcport);
1da177e4 3417
1da177e4
LT		 3418 return (rval);
3419}
3420
3421/*
3422 * qla2x00_find_new_loop_id
3423 * Scan through our port list and find a new usable loop ID.
3424 *
3425 * Input:
3426 * ha: adapter state pointer.
3427 * dev: port structure pointer.
3428 *
3429 * Returns:
3430 * qla2x00 local function return status code.
3431 *
3432 * Context:
3433 * Kernel context.
3434 */
03bcfb57 3435int
e315cd28 3436qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 3437{
3438 int rval;
e315cd28 3439 struct qla_hw_data *ha = vha->hw;
feafb7b1 3440 unsigned long flags = 0;
1da177e4
LT		 3441
3442 rval = QLA_SUCCESS;
3443
5f16b331 3444 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 3445
5f16b331
CD		 3446 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
3447 LOOPID_MAP_SIZE);
3448 if (dev->loop_id >= LOOPID_MAP_SIZE ||
3449 qla2x00_is_reserved_id(vha, dev->loop_id)) {
3450 dev->loop_id = FC_NO_LOOP_ID;
3451 rval = QLA_FUNCTION_FAILED;
3452 } else
3453 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 3454
5f16b331 3455 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 3456
5f16b331
CD		 3457 if (rval == QLA_SUCCESS)
3458 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3459 "Assigning new loopid=%x, portid=%x.\n",
3460 dev->loop_id, dev->d_id.b24);
3461 else
3462 ql_log(ql_log_warn, dev->vha, 0x2087,
3463 "No loop_id's available, portid=%x.\n",
3464 dev->d_id.b24);
1da177e4
LT		 3465
3466 return (rval);
3467}
3468
1da177e4
LT		 3469/*
3470 * qla2x00_fabric_dev_login
3471 * Login fabric target device and update FC port database.
3472 *
3473 * Input:
3474 * ha: adapter state pointer.
3475 * fcport: port structure list pointer.
3476 * next_loopid: contains value of a new loop ID that can be used
3477 * by the next login attempt.
3478 *
3479 * Returns:
3480 * qla2x00 local function return status code.
3481 *
3482 * Context:
3483 * Kernel context.
3484 */
3485static int
e315cd28 3486qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3487 uint16_t *next_loopid)
3488{
3489 int rval;
3490 int retry;
0107109e 3491 uint8_t opts;
e315cd28 3492 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3493
3494 rval = QLA_SUCCESS;
3495 retry = 0;
3496
ac280b67 3497 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584
AV		 3498 if (fcport->flags & FCF_ASYNC_SENT)
3499 return rval;
3500 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3501 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3502 if (!rval)
3503 return rval;
3504 }
3505
5ff1d584 3506 fcport->flags &= ~FCF_ASYNC_SENT;
e315cd28 3507 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
1da177e4 3508 if (rval == QLA_SUCCESS) {
f08b7251 3509 /* Send an ADISC to FCP2 devices.*/
0107109e 3510 opts = 0;
f08b7251 3511 if (fcport->flags & FCF_FCP2_DEVICE)
0107109e 3512 opts |= BIT_1;
e315cd28 3513 rval = qla2x00_get_port_database(vha, fcport, opts);
1da177e4 3514 if (rval != QLA_SUCCESS) {
e315cd28 3515 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3516 fcport->d_id.b.domain, fcport->d_id.b.area,
3517 fcport->d_id.b.al_pa);
e315cd28 3518 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4 3519 } else {
e315cd28 3520 qla2x00_update_fcport(vha, fcport);
1da177e4 3521 }
0b91d116
CD		 3522 } else {
3523 /* Retry Login. */
3524 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3525 }
3526
3527 return (rval);
3528}
3529
3530/*
3531 * qla2x00_fabric_login
3532 * Issue fabric login command.
3533 *
3534 * Input:
3535 * ha = adapter block pointer.
3536 * device = pointer to FC device type structure.
3537 *
3538 * Returns:
3539 * 0 - Login successfully
3540 * 1 - Login failed
3541 * 2 - Initiator device
3542 * 3 - Fatal error
3543 */
3544int
e315cd28 3545qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 3546 uint16_t *next_loopid)
3547{
3548 int rval;
3549 int retry;
3550 uint16_t tmp_loopid;
3551 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 3552 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3553
3554 retry = 0;
3555 tmp_loopid = 0;
3556
3557 for (;;) {
7c3df132
SK		 3558 ql_dbg(ql_dbg_disc, vha, 0x2000,
3559 "Trying Fabric Login w/loop id 0x%04x for port "
3560 "%02x%02x%02x.\n",
3561 fcport->loop_id, fcport->d_id.b.domain,
3562 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3563
3564 /* Login fcport on switch. */
0b91d116 3565 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 3566 fcport->d_id.b.domain, fcport->d_id.b.area,
3567 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 3568 if (rval != QLA_SUCCESS) {
3569 return rval;
3570 }
1da177e4
LT		 3571 if (mb[0] == MBS_PORT_ID_USED) {
3572 /*
3573 * Device has another loop ID. The firmware team
0107109e
AV		 3574 * recommends the driver perform an implicit login with
3575 * the specified ID again. The ID we just used is save
3576 * here so we return with an ID that can be tried by
3577 * the next login.
1da177e4
LT		 3578 */
3579 retry++;
3580 tmp_loopid = fcport->loop_id;
3581 fcport->loop_id = mb[1];
3582
7c3df132
SK		 3583 ql_dbg(ql_dbg_disc, vha, 0x2001,
3584 "Fabric Login: port in use - next loop "
3585 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 3586 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 3587 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 3588
3589 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3590 /*
3591 * Login succeeded.
3592 */
3593 if (retry) {
3594 /* A retry occurred before. */
3595 *next_loopid = tmp_loopid;
3596 } else {
3597 /*
3598 * No retry occurred before. Just increment the
3599 * ID value for next login.
3600 */
3601 *next_loopid = (fcport->loop_id + 1);
3602 }
3603
3604 if (mb[1] & BIT_0) {
3605 fcport->port_type = FCT_INITIATOR;
3606 } else {
3607 fcport->port_type = FCT_TARGET;
3608 if (mb[1] & BIT_1) {
8474f3a0 3609 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 3610 }
3611 }
3612
ad3e0eda
AV		 3613 if (mb[10] & BIT_0)
3614 fcport->supported_classes |= FC_COS_CLASS2;
3615 if (mb[10] & BIT_1)
3616 fcport->supported_classes |= FC_COS_CLASS3;
3617
2d70c103
NB		 3618 if (IS_FWI2_CAPABLE(ha)) {
3619 if (mb[10] & BIT_7)
3620 fcport->flags |=
3621 FCF_CONF_COMP_SUPPORTED;
3622 }
3623
1da177e4
LT		 3624 rval = QLA_SUCCESS;
3625 break;
3626 } else if (mb[0] == MBS_LOOP_ID_USED) {
3627 /*
3628 * Loop ID already used, try next loop ID.
3629 */
3630 fcport->loop_id++;
e315cd28 3631 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 3632 if (rval != QLA_SUCCESS) {
3633 /* Ran out of loop IDs to use */
3634 break;
3635 }
3636 } else if (mb[0] == MBS_COMMAND_ERROR) {
3637 /*
3638 * Firmware possibly timed out during login. If NO
3639 * retries are left to do then the device is declared
3640 * dead.
3641 */
3642 *next_loopid = fcport->loop_id;
e315cd28 3643 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3644 fcport->d_id.b.domain, fcport->d_id.b.area,
3645 fcport->d_id.b.al_pa);
e315cd28 3646 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 3647
3648 rval = 1;
3649 break;
3650 } else {
3651 /*
3652 * unrecoverable / not handled error
3653 */
7c3df132
SK		 3654 ql_dbg(ql_dbg_disc, vha, 0x2002,
3655 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3656 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3657 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3658 fcport->loop_id, jiffies);
1da177e4
LT		 3659
3660 *next_loopid = fcport->loop_id;
e315cd28 3661 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 3662 fcport->d_id.b.domain, fcport->d_id.b.area,
3663 fcport->d_id.b.al_pa);
5f16b331 3664 qla2x00_clear_loop_id(fcport);
0eedfcf0 3665 fcport->login_retry = 0;
1da177e4
LT		 3666
3667 rval = 3;
3668 break;
3669 }
3670 }
3671
3672 return (rval);
3673}
3674
3675/*
3676 * qla2x00_local_device_login
3677 * Issue local device login command.
3678 *
3679 * Input:
3680 * ha = adapter block pointer.
3681 * loop_id = loop id of device to login to.
3682 *
3683 * Returns (Where's the #define!!!!):
3684 * 0 - Login successfully
3685 * 1 - Login failed
3686 * 3 - Fatal error
3687 */
3688int
e315cd28 3689qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 3690{
3691 int rval;
3692 uint16_t mb[MAILBOX_REGISTER_COUNT];
3693
3694 memset(mb, 0, sizeof(mb));
e315cd28 3695 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 3696 if (rval == QLA_SUCCESS) {
3697 /* Interrogate mailbox registers for any errors */
3698 if (mb[0] == MBS_COMMAND_ERROR)
3699 rval = 1;
3700 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3701 /* device not in PCB table */
3702 rval = 3;
3703 }
3704
3705 return (rval);
3706}
3707
3708/*
3709 * qla2x00_loop_resync
3710 * Resync with fibre channel devices.
3711 *
3712 * Input:
3713 * ha = adapter block pointer.
3714 *
3715 * Returns:
3716 * 0 = success
3717 */
3718int
e315cd28 3719qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 3720{
73208dfd 3721 int rval = QLA_SUCCESS;
1da177e4 3722 uint32_t wait_time;
67c2e93a
AC		 3723 struct req_que *req;
3724 struct rsp_que *rsp;
3725
7163ea81 3726 if (vha->hw->flags.cpu_affinity_enabled)
67c2e93a
AC		 3727 req = vha->hw->req_q_map[0];
3728 else
3729 req = vha->req;
3730 rsp = req->rsp;
1da177e4 3731
e315cd28
AC		 3732 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3733 if (vha->flags.online) {
3734 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 3735 /* Wait at most MAX_TARGET RSCNs for a stable link. */
3736 wait_time = 256;
3737 do {
0107109e 3738 /* Issue a marker after FW becomes ready. */
73208dfd
AC		 3739 qla2x00_marker(vha, req, rsp, 0, 0,
3740 MK_SYNC_ALL);
e315cd28 3741 vha->marker_needed = 0;
1da177e4
LT		 3742
3743 /* Remap devices on Loop. */
e315cd28 3744 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 3745
e315cd28 3746 qla2x00_configure_loop(vha);
1da177e4 3747 wait_time--;
e315cd28
AC		 3748 } while (!atomic_read(&vha->loop_down_timer) &&
3749 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3750 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3751 &vha->dpc_flags)));
1da177e4 3752 }
1da177e4
LT		 3753 }
3754
e315cd28 3755 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 3756 return (QLA_FUNCTION_FAILED);
1da177e4 3757
e315cd28 3758 if (rval)
7c3df132
SK		 3759 ql_dbg(ql_dbg_disc, vha, 0x206c,
3760 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 3761
3762 return (rval);
3763}
3764
579d12b5
SK		 3765/*
3766* qla2x00_perform_loop_resync
3767* Description: This function will set the appropriate flags and call
3768* qla2x00_loop_resync. If successful loop will be resynced
3769* Arguments : scsi_qla_host_t pointer
3770* returm : Success or Failure
3771*/
3772
3773int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3774{
3775 int32_t rval = 0;
3776
3777 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3778 /*Configure the flags so that resync happens properly*/
3779 atomic_set(&ha->loop_down_timer, 0);
3780 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3781 atomic_set(&ha->loop_state, LOOP_UP);
3782 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3783 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3784 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3785
3786 rval = qla2x00_loop_resync(ha);
3787 } else
3788 atomic_set(&ha->loop_state, LOOP_DEAD);
3789
3790 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3791 }
3792
3793 return rval;
3794}
3795
d97994dc 3796void
67becc00 3797qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 3798{
3799 fc_port_t *fcport;
feafb7b1
AE		 3800 struct scsi_qla_host *vha;
3801 struct qla_hw_data *ha = base_vha->hw;
3802 unsigned long flags;
d97994dc 3803
feafb7b1 3804 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 3805 /* Go with deferred removal of rport references. */
feafb7b1
AE		 3806 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3807 atomic_inc(&vha->vref_count);
3808 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 3809 if (fcport->drport &&
feafb7b1
AE		 3810 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3811 spin_unlock_irqrestore(&ha->vport_slock, flags);
3812
67becc00 3813 qla2x00_rport_del(fcport);
feafb7b1
AE		 3814
3815 spin_lock_irqsave(&ha->vport_slock, flags);
3816 }
3817 }
3818 atomic_dec(&vha->vref_count);
3819 }
3820 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 3821}
3822
7d613ac6
SV		 3823/* Assumes idc_lock always held on entry */
3824void
3825qla83xx_reset_ownership(scsi_qla_host_t *vha)
3826{
3827 struct qla_hw_data *ha = vha->hw;
3828 uint32_t drv_presence, drv_presence_mask;
3829 uint32_t dev_part_info1, dev_part_info2, class_type;
3830 uint32_t class_type_mask = 0x3;
3831 uint16_t fcoe_other_function = 0xffff, i;
3832
3833 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
3834
3835 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
3836 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
3837 for (i = 0; i < 8; i++) {
3838 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
3839 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3840 (i != ha->portnum)) {
3841 fcoe_other_function = i;
3842 break;
3843 }
3844 }
3845 if (fcoe_other_function == 0xffff) {
3846 for (i = 0; i < 8; i++) {
3847 class_type = ((dev_part_info2 >> (i * 4)) &
3848 class_type_mask);
3849 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
3850 ((i + 8) != ha->portnum)) {
3851 fcoe_other_function = i + 8;
3852 break;
3853 }
3854 }
3855 }
3856 /*
3857 * Prepare drv-presence mask based on fcoe functions present.
3858 * However consider only valid physical fcoe function numbers (0-15).
3859 */
3860 drv_presence_mask = ~((1 << (ha->portnum)) |
3861 ((fcoe_other_function == 0xffff) ?
3862 0 : (1 << (fcoe_other_function))));
3863
3864 /* We are the reset owner iff:
3865 * - No other protocol drivers present.
3866 * - This is the lowest among fcoe functions. */
3867 if (!(drv_presence & drv_presence_mask) &&
3868 (ha->portnum < fcoe_other_function)) {
3869 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
3870 "This host is Reset owner.\n");
3871 ha->flags.nic_core_reset_owner = 1;
3872 }
3873}
3874
3875int
3876__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
3877{
3878 int rval = QLA_SUCCESS;
3879 struct qla_hw_data *ha = vha->hw;
3880 uint32_t drv_ack;
3881
3882 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3883 if (rval == QLA_SUCCESS) {
3884 drv_ack |= (1 << ha->portnum);
3885 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3886 }
3887
3888 return rval;
3889}
3890
3891int
3892qla83xx_set_drv_ack(scsi_qla_host_t *vha)
3893{
3894 int rval = QLA_SUCCESS;
3895
3896 qla83xx_idc_lock(vha, 0);
3897 rval = __qla83xx_set_drv_ack(vha);
3898 qla83xx_idc_unlock(vha, 0);
3899
3900 return rval;
3901}
3902
3903int
3904__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
3905{
3906 int rval = QLA_SUCCESS;
3907 struct qla_hw_data *ha = vha->hw;
3908 uint32_t drv_ack;
3909
3910 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
3911 if (rval == QLA_SUCCESS) {
3912 drv_ack &= ~(1 << ha->portnum);
3913 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
3914 }
3915
3916 return rval;
3917}
3918
3919int
3920qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
3921{
3922 int rval = QLA_SUCCESS;
3923
3924 qla83xx_idc_lock(vha, 0);
3925 rval = __qla83xx_clear_drv_ack(vha);
3926 qla83xx_idc_unlock(vha, 0);
3927
3928 return rval;
3929}
3930
3931const char *
3932qla83xx_dev_state_to_string(uint32_t dev_state)
3933{
3934 switch (dev_state) {
3935 case QLA8XXX_DEV_COLD:
3936 return "COLD/RE-INIT";
3937 case QLA8XXX_DEV_INITIALIZING:
3938 return "INITIALIZING";
3939 case QLA8XXX_DEV_READY:
3940 return "READY";
3941 case QLA8XXX_DEV_NEED_RESET:
3942 return "NEED RESET";
3943 case QLA8XXX_DEV_NEED_QUIESCENT:
3944 return "NEED QUIESCENT";
3945 case QLA8XXX_DEV_FAILED:
3946 return "FAILED";
3947 case QLA8XXX_DEV_QUIESCENT:
3948 return "QUIESCENT";
3949 default:
3950 return "Unknown";
3951 }
3952}
3953
3954/* Assumes idc-lock always held on entry */
3955void
3956qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
3957{
3958 struct qla_hw_data *ha = vha->hw;
3959 uint32_t idc_audit_reg = 0, duration_secs = 0;
3960
3961 switch (audit_type) {
3962 case IDC_AUDIT_TIMESTAMP:
3963 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
3964 idc_audit_reg = (ha->portnum) |
3965 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
3966 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
3967 break;
3968
3969 case IDC_AUDIT_COMPLETION:
3970 duration_secs = ((jiffies_to_msecs(jiffies) -
3971 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
3972 idc_audit_reg = (ha->portnum) |
3973 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
3974 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
3975 break;
3976
3977 default:
3978 ql_log(ql_log_warn, vha, 0xb078,
3979 "Invalid audit type specified.\n");
3980 break;
3981 }
3982}
3983
3984/* Assumes idc_lock always held on entry */
3985int
3986qla83xx_initiating_reset(scsi_qla_host_t *vha)
3987{
3988 struct qla_hw_data *ha = vha->hw;
3989 uint32_t idc_control, dev_state;
3990
3991 __qla83xx_get_idc_control(vha, &idc_control);
3992 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
3993 ql_log(ql_log_info, vha, 0xb080,
3994 "NIC Core reset has been disabled. idc-control=0x%x\n",
3995 idc_control);
3996 return QLA_FUNCTION_FAILED;
3997 }
3998
3999 /* Set NEED-RESET iff in READY state and we are the reset-owner */
4000 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4001 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
4002 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
4003 QLA8XXX_DEV_NEED_RESET);
4004 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
4005 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
4006 } else {
4007 const char *state = qla83xx_dev_state_to_string(dev_state);
4008 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
4009
4010 /* SV: XXX: Is timeout required here? */
4011 /* Wait for IDC state change READY -> NEED_RESET */
4012 while (dev_state == QLA8XXX_DEV_READY) {
4013 qla83xx_idc_unlock(vha, 0);
4014 msleep(200);
4015 qla83xx_idc_lock(vha, 0);
4016 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4017 }
4018 }
4019
4020 /* Send IDC ack by writing to drv-ack register */
4021 __qla83xx_set_drv_ack(vha);
4022
4023 return QLA_SUCCESS;
4024}
4025
4026int
4027__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4028{
4029 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4030}
4031
4032int
4033qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
4034{
4035 int rval = QLA_SUCCESS;
4036
4037 qla83xx_idc_lock(vha, 0);
4038 rval = __qla83xx_set_idc_control(vha, idc_control);
4039 qla83xx_idc_unlock(vha, 0);
4040
4041 return rval;
4042}
4043
4044int
4045__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4046{
4047 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
4048}
4049
4050int
4051qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
4052{
4053 int rval = QLA_SUCCESS;
4054
4055 qla83xx_idc_lock(vha, 0);
4056 rval = __qla83xx_get_idc_control(vha, idc_control);
4057 qla83xx_idc_unlock(vha, 0);
4058
4059 return rval;
4060}
4061
4062int
4063qla83xx_check_driver_presence(scsi_qla_host_t *vha)
4064{
4065 uint32_t drv_presence = 0;
4066 struct qla_hw_data *ha = vha->hw;
4067
4068 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4069 if (drv_presence & (1 << ha->portnum))
4070 return QLA_SUCCESS;
4071 else
4072 return QLA_TEST_FAILED;
4073}
4074
4075int
4076qla83xx_nic_core_reset(scsi_qla_host_t *vha)
4077{
4078 int rval = QLA_SUCCESS;
4079 struct qla_hw_data *ha = vha->hw;
4080
4081 ql_dbg(ql_dbg_p3p, vha, 0xb058,
4082 "Entered %s().\n", __func__);
4083
4084 if (vha->device_flags & DFLG_DEV_FAILED) {
4085 ql_log(ql_log_warn, vha, 0xb059,
4086 "Device in unrecoverable FAILED state.\n");
4087 return QLA_FUNCTION_FAILED;
4088 }
4089
4090 qla83xx_idc_lock(vha, 0);
4091
4092 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
4093 ql_log(ql_log_warn, vha, 0xb05a,
4094 "Function=0x%x has been removed from IDC participation.\n",
4095 ha->portnum);
4096 rval = QLA_FUNCTION_FAILED;
4097 goto exit;
4098 }
4099
4100 qla83xx_reset_ownership(vha);
4101
4102 rval = qla83xx_initiating_reset(vha);
4103
4104 /*
4105 * Perform reset if we are the reset-owner,
4106 * else wait till IDC state changes to READY/FAILED.
4107 */
4108 if (rval == QLA_SUCCESS) {
4109 rval = qla83xx_idc_state_handler(vha);
4110
4111 if (rval == QLA_SUCCESS)
4112 ha->flags.nic_core_hung = 0;
4113 __qla83xx_clear_drv_ack(vha);
4114 }
4115
4116exit:
4117 qla83xx_idc_unlock(vha, 0);
4118
4119 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
4120
4121 return rval;
4122}
4123
81178772
SK		 4124int
4125qla2xxx_mctp_dump(scsi_qla_host_t *vha)
4126{
4127 struct qla_hw_data *ha = vha->hw;
4128 int rval = QLA_FUNCTION_FAILED;
4129
4130 if (!IS_MCTP_CAPABLE(ha)) {
4131 /* This message can be removed from the final version */
4132 ql_log(ql_log_info, vha, 0x506d,
4133 "This board is not MCTP capable\n");
4134 return rval;
4135 }
4136
4137 if (!ha->mctp_dump) {
4138 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
4139 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
4140
4141 if (!ha->mctp_dump) {
4142 ql_log(ql_log_warn, vha, 0x506e,
4143 "Failed to allocate memory for mctp dump\n");
4144 return rval;
4145 }
4146 }
4147
4148#define MCTP_DUMP_STR_ADDR 0x00000000
4149 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
4150 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
4151 if (rval != QLA_SUCCESS) {
4152 ql_log(ql_log_warn, vha, 0x506f,
4153 "Failed to capture mctp dump\n");
4154 } else {
4155 ql_log(ql_log_info, vha, 0x5070,
4156 "Mctp dump capture for host (%ld/%p).\n",
4157 vha->host_no, ha->mctp_dump);
4158 ha->mctp_dumped = 1;
4159 }
4160
4161 if (!ha->flags.nic_core_reset_hdlr_active) {
4162 ha->flags.nic_core_reset_hdlr_active = 1;
4163 rval = qla83xx_restart_nic_firmware(vha);
4164 if (rval)
4165 /* NIC Core reset failed. */
4166 ql_log(ql_log_warn, vha, 0x5071,
4167 "Failed to restart nic firmware\n");
4168 else
4169 ql_dbg(ql_dbg_p3p, vha, 0xb084,
4170 "Restarted NIC firmware successfully.\n");
4171 ha->flags.nic_core_reset_hdlr_active = 0;
4172 }
4173
4174 return rval;
4175
4176}
4177
579d12b5 4178/*
8fcd6b8b 4179* qla2x00_quiesce_io
579d12b5
SK		 4180* Description: This function will block the new I/Os
4181* Its not aborting any I/Os as context
4182* is not destroyed during quiescence
4183* Arguments: scsi_qla_host_t
4184* return : void
4185*/
4186void
8fcd6b8b 4187qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 4188{
4189 struct qla_hw_data *ha = vha->hw;
4190 struct scsi_qla_host *vp;
4191
8fcd6b8b
CD		 4192 ql_dbg(ql_dbg_dpc, vha, 0x401d,
4193 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 4194
4195 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
4196 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4197 atomic_set(&vha->loop_state, LOOP_DOWN);
4198 qla2x00_mark_all_devices_lost(vha, 0);
4199 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 4200 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 4201 } else {
4202 if (!atomic_read(&vha->loop_down_timer))
4203 atomic_set(&vha->loop_down_timer,
4204 LOOP_DOWN_TIME);
4205 }
4206 /* Wait for pending cmds to complete */
4207 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
4208}
4209
a9083016
GM		 4210void
4211qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
4212{
4213 struct qla_hw_data *ha = vha->hw;
579d12b5 4214 struct scsi_qla_host *vp;
feafb7b1 4215 unsigned long flags;
6aef87be 4216 fc_port_t *fcport;
a9083016 4217
e46ef004
SK		 4218 /* For ISP82XX, driver waits for completion of the commands.
4219 * online flag should be set.
4220 */
4221 if (!IS_QLA82XX(ha))
4222 vha->flags.online = 0;
a9083016
GM		 4223 ha->flags.chip_reset_done = 0;
4224 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 4225 vha->qla_stats.total_isp_aborts++;
a9083016 4226
7c3df132
SK		 4227 ql_log(ql_log_info, vha, 0x00af,
4228 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 4229
e46ef004
SK		 4230 /* For ISP82XX, reset_chip is just disabling interrupts.
4231 * Driver waits for the completion of the commands.
4232 * the interrupts need to be enabled.
4233 */
a9083016
GM		 4234 if (!IS_QLA82XX(ha))
4235 ha->isp_ops->reset_chip(vha);
4236
4237 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
4238 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
4239 atomic_set(&vha->loop_state, LOOP_DOWN);
4240 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 4241
4242 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 4243 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 4244 atomic_inc(&vp->vref_count);
4245 spin_unlock_irqrestore(&ha->vport_slock, flags);
4246
a9083016 4247 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 4248
4249 spin_lock_irqsave(&ha->vport_slock, flags);
4250 atomic_dec(&vp->vref_count);
4251 }
4252 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 4253 } else {
4254 if (!atomic_read(&vha->loop_down_timer))
4255 atomic_set(&vha->loop_down_timer,
4256 LOOP_DOWN_TIME);
4257 }
4258
6aef87be
AV		 4259 /* Clear all async request states across all VPs. */
4260 list_for_each_entry(fcport, &vha->vp_fcports, list)
4261 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4262 spin_lock_irqsave(&ha->vport_slock, flags);
4263 list_for_each_entry(vp, &ha->vp_list, list) {
4264 atomic_inc(&vp->vref_count);
4265 spin_unlock_irqrestore(&ha->vport_slock, flags);
4266
4267 list_for_each_entry(fcport, &vp->vp_fcports, list)
4268 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
4269
4270 spin_lock_irqsave(&ha->vport_slock, flags);
4271 atomic_dec(&vp->vref_count);
4272 }
4273 spin_unlock_irqrestore(&ha->vport_slock, flags);
4274
bddd2d65
LC		 4275 if (!ha->flags.eeh_busy) {
4276 /* Make sure for ISP 82XX IO DMA is complete */
4277 if (IS_QLA82XX(ha)) {
7190575f 4278 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 4279 ql_log(ql_log_info, vha, 0x00b4,
4280 "Done chip reset cleanup.\n");
a9083016 4281
e46ef004
SK		 4282 /* Done waiting for pending commands.
4283 * Reset the online flag.
4284 */
4285 vha->flags.online = 0;
4d78c973 4286 }
a9083016 4287
bddd2d65
LC		 4288 /* Requeue all commands in outstanding command list. */
4289 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
4290 }
a9083016
GM		 4291}
4292
1da177e4
LT		 4293/*
4294* qla2x00_abort_isp
4295* Resets ISP and aborts all outstanding commands.
4296*
4297* Input:
4298* ha = adapter block pointer.
4299*
4300* Returns:
4301* 0 = success
4302*/
4303int
e315cd28 4304qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 4305{
476e8978 4306 int rval;
1da177e4 4307 uint8_t status = 0;
e315cd28
AC		 4308 struct qla_hw_data *ha = vha->hw;
4309 struct scsi_qla_host *vp;
73208dfd 4310 struct req_que *req = ha->req_q_map[0];
feafb7b1 4311 unsigned long flags;
1da177e4 4312
e315cd28 4313 if (vha->flags.online) {
a9083016 4314 qla2x00_abort_isp_cleanup(vha);
1da177e4 4315
a6171297
SV		 4316 if (IS_QLA8031(ha)) {
4317 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
4318 "Clearing fcoe driver presence.\n");
4319 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
4320 ql_dbg(ql_dbg_p3p, vha, 0xb073,
4321 "Error while clearing DRV-Presence.\n");
4322 }
4323
85880801
AV		 4324 if (unlikely(pci_channel_offline(ha->pdev) &&
4325 ha->flags.pci_channel_io_perm_failure)) {
4326 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4327 status = 0;
4328 return status;
4329 }
4330
73208dfd 4331 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 4332
e315cd28 4333 ha->isp_ops->nvram_config(vha);
1da177e4 4334
e315cd28
AC		 4335 if (!qla2x00_restart_isp(vha)) {
4336 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 4337
e315cd28 4338 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 4339 /*
4340 * Issue marker command only when we are going
4341 * to start the I/O .
4342 */
e315cd28 4343 vha->marker_needed = 1;
1da177e4
LT		 4344 }
4345
e315cd28 4346 vha->flags.online = 1;
1da177e4 4347
fd34f556 4348 ha->isp_ops->enable_intrs(ha);
1da177e4 4349
fa2a1ce5 4350 ha->isp_abort_cnt = 0;
e315cd28 4351 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 4352
6246b8a1
GM		 4353 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
4354 qla2x00_get_fw_version(vha);
df613b96
AV		 4355 if (ha->fce) {
4356 ha->flags.fce_enabled = 1;
4357 memset(ha->fce, 0,
4358 fce_calc_size(ha->fce_bufs));
e315cd28 4359 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 4360 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
4361 &ha->fce_bufs);
4362 if (rval) {
7c3df132 4363 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 4364 "Unable to reinitialize FCE "
4365 "(%d).\n", rval);
4366 ha->flags.fce_enabled = 0;
4367 }
4368 }
436a7b11
AV		 4369
4370 if (ha->eft) {
4371 memset(ha->eft, 0, EFT_SIZE);
e315cd28 4372 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 4373 ha->eft_dma, EFT_NUM_BUFFERS);
4374 if (rval) {
7c3df132 4375 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 4376 "Unable to reinitialize EFT "
4377 "(%d).\n", rval);
4378 }
4379 }
1da177e4 4380 } else { /* failed the ISP abort */
e315cd28
AC		 4381 vha->flags.online = 1;
4382 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 4383 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 4384 ql_log(ql_log_fatal, vha, 0x8035,
4385 "ISP error recover failed - "
4386 "board disabled.\n");
fa2a1ce5 4387 /*
1da177e4
LT		 4388 * The next call disables the board
4389 * completely.
4390 */
e315cd28
AC		 4391 ha->isp_ops->reset_adapter(vha);
4392 vha->flags.online = 0;
1da177e4 4393 clear_bit(ISP_ABORT_RETRY,
e315cd28 4394 &vha->dpc_flags);
1da177e4
LT		 4395 status = 0;
4396 } else { /* schedule another ISP abort */
4397 ha->isp_abort_cnt--;
7c3df132
SK		 4398 ql_dbg(ql_dbg_taskm, vha, 0x8020,
4399 "ISP abort - retry remaining %d.\n",
4400 ha->isp_abort_cnt);
1da177e4
LT		 4401 status = 1;
4402 }
4403 } else {
4404 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 4405 ql_dbg(ql_dbg_taskm, vha, 0x8021,
4406 "ISP error recovery - retrying (%d) "
4407 "more times.\n", ha->isp_abort_cnt);
e315cd28 4408 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 4409 status = 1;
4410 }
4411 }
fa2a1ce5 4412
1da177e4
LT		 4413 }
4414
e315cd28 4415 if (!status) {
7c3df132 4416 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
feafb7b1
AE		 4417
4418 spin_lock_irqsave(&ha->vport_slock, flags);
4419 list_for_each_entry(vp, &ha->vp_list, list) {
4420 if (vp->vp_idx) {
4421 atomic_inc(&vp->vref_count);
4422 spin_unlock_irqrestore(&ha->vport_slock, flags);
4423
e315cd28 4424 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 4425
4426 spin_lock_irqsave(&ha->vport_slock, flags);
4427 atomic_dec(&vp->vref_count);
4428 }
e315cd28 4429 }
feafb7b1
AE		 4430 spin_unlock_irqrestore(&ha->vport_slock, flags);
4431
7d613ac6
SV		 4432 if (IS_QLA8031(ha)) {
4433 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
4434 "Setting back fcoe driver presence.\n");
4435 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
4436 ql_dbg(ql_dbg_p3p, vha, 0xb074,
4437 "Error while setting DRV-Presence.\n");
4438 }
e315cd28 4439 } else {
d8424f68
JP		 4440 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4441 __func__);
1da177e4
LT		 4442 }
4443
4444 return(status);
4445}
4446
4447/*
4448* qla2x00_restart_isp
4449* restarts the ISP after a reset
4450*
4451* Input:
4452* ha = adapter block pointer.
4453*
4454* Returns:
4455* 0 = success
4456*/
4457static int
e315cd28 4458qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 4459{
c6b2fca8 4460 int status = 0;
1da177e4 4461 uint32_t wait_time;
e315cd28 4462 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 4463 struct req_que *req = ha->req_q_map[0];
4464 struct rsp_que *rsp = ha->rsp_q_map[0];
2d70c103 4465 unsigned long flags;
1da177e4
LT		 4466
4467 /* If firmware needs to be loaded */
e315cd28
AC		 4468 if (qla2x00_isp_firmware(vha)) {
4469 vha->flags.online = 0;
4470 status = ha->isp_ops->chip_diag(vha);
4471 if (!status)
4472 status = qla2x00_setup_chip(vha);
1da177e4
LT		 4473 }
4474
e315cd28
AC		 4475 if (!status && !(status = qla2x00_init_rings(vha))) {
4476 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 4477 ha->flags.chip_reset_done = 1;
73208dfd
AC		 4478 /* Initialize the queues in use */
4479 qla25xx_init_queues(ha);
4480
e315cd28
AC		 4481 status = qla2x00_fw_ready(vha);
4482 if (!status) {
7c3df132
SK		 4483 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4484 "Start configure loop status = %d.\n", status);
0107109e
AV		 4485
4486 /* Issue a marker after FW becomes ready. */
73208dfd 4487 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
0107109e 4488
e315cd28 4489 vha->flags.online = 1;
2d70c103
NB		 4490
4491 /*
4492 * Process any ATIO queue entries that came in
4493 * while we weren't online.
4494 */
4495 spin_lock_irqsave(&ha->hardware_lock, flags);
4496 if (qla_tgt_mode_enabled(vha))
4497 qlt_24xx_process_atio_queue(vha);
4498 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4499
1da177e4
LT		 4500 /* Wait at most MAX_TARGET RSCNs for a stable link. */
4501 wait_time = 256;
4502 do {
e315cd28
AC		 4503 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4504 qla2x00_configure_loop(vha);
1da177e4 4505 wait_time--;
e315cd28
AC		 4506 } while (!atomic_read(&vha->loop_down_timer) &&
4507 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4508 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4509 &vha->dpc_flags)));
1da177e4
LT		 4510 }
4511
4512 /* if no cable then assume it's good */
e315cd28 4513 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4
LT		 4514 status = 0;
4515
7c3df132
SK		 4516 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4517 "Configure loop done, status = 0x%x.\n", status);
1da177e4
LT		 4518 }
4519 return (status);
4520}
4521
73208dfd
AC		 4522static int
4523qla25xx_init_queues(struct qla_hw_data *ha)
4524{
4525 struct rsp_que *rsp = NULL;
4526 struct req_que *req = NULL;
4527 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4528 int ret = -1;
4529 int i;
4530
2afa19a9 4531 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd
AC		 4532 rsp = ha->rsp_q_map[i];
4533 if (rsp) {
4534 rsp->options &= ~BIT_0;
618a7523 4535 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 4536 if (ret != QLA_SUCCESS)
7c3df132
SK		 4537 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4538 "%s Rsp que: %d init failed.\n",
4539 __func__, rsp->id);
73208dfd 4540 else
7c3df132
SK		 4541 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4542 "%s Rsp que: %d inited.\n",
4543 __func__, rsp->id);
73208dfd 4544 }
2afa19a9
AC		 4545 }
4546 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd
AC		 4547 req = ha->req_q_map[i];
4548 if (req) {
29bdccbe 4549 /* Clear outstanding commands array. */
73208dfd 4550 req->options &= ~BIT_0;
618a7523 4551 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 4552 if (ret != QLA_SUCCESS)
7c3df132
SK		 4553 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4554 "%s Req que: %d init failed.\n",
4555 __func__, req->id);
73208dfd 4556 else
7c3df132
SK		 4557 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4558 "%s Req que: %d inited.\n",
4559 __func__, req->id);
73208dfd
AC		 4560 }
4561 }
4562 return ret;
4563}
4564
1da177e4
LT		 4565/*
4566* qla2x00_reset_adapter
4567* Reset adapter.
4568*
4569* Input:
4570* ha = adapter block pointer.
4571*/
abbd8870 4572void
e315cd28 4573qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 4574{
4575 unsigned long flags = 0;
e315cd28 4576 struct qla_hw_data *ha = vha->hw;
3d71644c 4577 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 4578
e315cd28 4579 vha->flags.online = 0;
fd34f556 4580 ha->isp_ops->disable_intrs(ha);
1da177e4 4581
1da177e4
LT		 4582 spin_lock_irqsave(&ha->hardware_lock, flags);
4583 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
4584 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4585 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
4586 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
4587 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4588}
0107109e
AV		 4589
4590void
e315cd28 4591qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 4592{
4593 unsigned long flags = 0;
e315cd28 4594 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 4595 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4596
a9083016
GM		 4597 if (IS_QLA82XX(ha))
4598 return;
4599
e315cd28 4600 vha->flags.online = 0;
fd34f556 4601 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 4602
4603 spin_lock_irqsave(&ha->hardware_lock, flags);
4604 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
4605 RD_REG_DWORD(&reg->hccr);
4606 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
4607 RD_REG_DWORD(&reg->hccr);
4608 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 4609
4610 if (IS_NOPOLLING_TYPE(ha))
4611 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 4612}
4613
4e08df3f
DM		 4614/* On sparc systems, obtain port and node WWN from firmware
4615 * properties.
4616 */
e315cd28
AC		 4617static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4618 struct nvram_24xx *nv)
4e08df3f
DM		 4619{
4620#ifdef CONFIG_SPARC
e315cd28 4621 struct qla_hw_data *ha = vha->hw;
4e08df3f 4622 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 4623 struct device_node *dp = pci_device_to_OF_node(pdev);
4624 const u8 *val;
4e08df3f
DM		 4625 int len;
4626
4627 val = of_get_property(dp, "port-wwn", &len);
4628 if (val && len >= WWN_SIZE)
4629 memcpy(nv->port_name, val, WWN_SIZE);
4630
4631 val = of_get_property(dp, "node-wwn", &len);
4632 if (val && len >= WWN_SIZE)
4633 memcpy(nv->node_name, val, WWN_SIZE);
4634#endif
4635}
4636
0107109e 4637int
e315cd28 4638qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 4639{
4e08df3f 4640 int rval;
0107109e
AV		 4641 struct init_cb_24xx *icb;
4642 struct nvram_24xx *nv;
4643 uint32_t *dptr;
4644 uint8_t *dptr1, *dptr2;
4645 uint32_t chksum;
4646 uint16_t cnt;
e315cd28 4647 struct qla_hw_data *ha = vha->hw;
0107109e 4648
4e08df3f 4649 rval = QLA_SUCCESS;
0107109e 4650 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 4651 nv = ha->nvram;
0107109e
AV		 4652
4653 /* Determine NVRAM starting address. */
e5b68a61
AC		 4654 if (ha->flags.port0) {
4655 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4656 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4657 } else {
0107109e 4658 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 4659 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4660 }
e5b68a61
AC		 4661 ha->nvram_size = sizeof(struct nvram_24xx);
4662 ha->vpd_size = FA_NVRAM_VPD_SIZE;
a9083016
GM		 4663 if (IS_QLA82XX(ha))
4664 ha->vpd_size = FA_VPD_SIZE_82XX;
0107109e 4665
281afe19
SJ		 4666 /* Get VPD data into cache */
4667 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 4668 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 4669 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4670
4671 /* Get NVRAM data into cache and calculate checksum. */
0107109e 4672 dptr = (uint32_t *)nv;
e315cd28 4673 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e
AV		 4674 ha->nvram_size);
4675 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4676 chksum += le32_to_cpu(*dptr++);
4677
7c3df132
SK		 4678 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4679 "Contents of NVRAM\n");
4680 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4681 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 4682
4683 /* Bad NVRAM data, set defaults parameters. */
4684 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4685 || nv->id[3] != ' ' ||
4686 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4687 /* Reset NVRAM data. */
7c3df132 4688 ql_log(ql_log_warn, vha, 0x006b,
9e336520 4689 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 4690 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4691 ql_log(ql_log_warn, vha, 0x006c,
4692 "Falling back to functioning (yet invalid -- WWPN) "
4693 "defaults.\n");
4e08df3f
DM		 4694
4695 /*
4696 * Set default initialization control block.
4697 */
4698 memset(nv, 0, ha->nvram_size);
4699 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4700 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4701 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4702 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4703 nv->exchange_count = __constant_cpu_to_le16(0);
4704 nv->hard_address = __constant_cpu_to_le16(124);
4705 nv->port_name[0] = 0x21;
e5b68a61 4706 nv->port_name[1] = 0x00 + ha->port_no;
4e08df3f
DM		 4707 nv->port_name[2] = 0x00;
4708 nv->port_name[3] = 0xe0;
4709 nv->port_name[4] = 0x8b;
4710 nv->port_name[5] = 0x1c;
4711 nv->port_name[6] = 0x55;
4712 nv->port_name[7] = 0x86;
4713 nv->node_name[0] = 0x20;
4714 nv->node_name[1] = 0x00;
4715 nv->node_name[2] = 0x00;
4716 nv->node_name[3] = 0xe0;
4717 nv->node_name[4] = 0x8b;
4718 nv->node_name[5] = 0x1c;
4719 nv->node_name[6] = 0x55;
4720 nv->node_name[7] = 0x86;
e315cd28 4721 qla24xx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 4722 nv->login_retry_count = __constant_cpu_to_le16(8);
4723 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4724 nv->login_timeout = __constant_cpu_to_le16(0);
4725 nv->firmware_options_1 =
4726 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4727 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4728 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4729 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4730 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4731 nv->efi_parameters = __constant_cpu_to_le32(0);
4732 nv->reset_delay = 5;
4733 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4734 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4735 nv->link_down_timeout = __constant_cpu_to_le16(30);
4736
4737 rval = 1;
0107109e
AV		 4738 }
4739
2d70c103
NB		 4740 if (!qla_ini_mode_enabled(vha)) {
4741 /* Don't enable full login after initial LIP */
4742 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4743 /* Don't enable LIP full login for initiator */
4744 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4745 }
4746
4747 qlt_24xx_config_nvram_stage1(vha, nv);
4748
0107109e 4749 /* Reset Initialization control block */
e315cd28 4750 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 4751
4752 /* Copy 1st segment. */
4753 dptr1 = (uint8_t *)icb;
4754 dptr2 = (uint8_t *)&nv->version;
4755 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4756 while (cnt--)
4757 *dptr1++ = *dptr2++;
4758
4759 icb->login_retry_count = nv->login_retry_count;
3ea66e28 4760 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 4761
4762 /* Copy 2nd segment. */
4763 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4764 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4765 cnt = (uint8_t *)&icb->reserved_3 -
4766 (uint8_t *)&icb->interrupt_delay_timer;
4767 while (cnt--)
4768 *dptr1++ = *dptr2++;
4769
4770 /*
4771 * Setup driver NVRAM options.
4772 */
e315cd28 4773 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 4774 "QLA2462");
0107109e 4775
2d70c103
NB		 4776 qlt_24xx_config_nvram_stage2(vha, icb);
4777
5341e868 4778 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
2d70c103 4779 /* Use alternate WWN? */
5341e868
AV		 4780 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4781 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4782 }
4783
0107109e 4784 /* Prepare nodename */
fd0e7e4d 4785 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 4786 /*
4787 * Firmware will apply the following mask if the nodename was
4788 * not provided.
4789 */
4790 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4791 icb->node_name[0] &= 0xF0;
4792 }
4793
4794 /* Set host adapter parameters. */
4795 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 4796 ha->flags.enable_lip_reset = 0;
4797 ha->flags.enable_lip_full_login =
4798 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4799 ha->flags.enable_target_reset =
4800 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 4801 ha->flags.enable_led_scheme = 0;
d4c760c2 4802 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 4803
fd0e7e4d
AV		 4804 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4805 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 4806
4807 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4808 sizeof(ha->fw_seriallink_options24));
4809
4810 /* save HBA serial number */
4811 ha->serial0 = icb->port_name[5];
4812 ha->serial1 = icb->port_name[6];
4813 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4814 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4815 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 4816
bc8fb3cb
AV		 4817 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4818
0107109e
AV		 4819 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4820
4821 /* Set minimum login_timeout to 4 seconds. */
4822 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4823 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4824 if (le16_to_cpu(nv->login_timeout) < 4)
4825 nv->login_timeout = __constant_cpu_to_le16(4);
4826 ha->login_timeout = le16_to_cpu(nv->login_timeout);
c6852c4c 4827 icb->login_timeout = nv->login_timeout;
0107109e 4828
00a537b8
AV		 4829 /* Set minimum RATOV to 100 tenths of a second. */
4830 ha->r_a_tov = 100;
0107109e
AV		 4831
4832 ha->loop_reset_delay = nv->reset_delay;
4833
4834 /* Link Down Timeout = 0:
4835 *
4836 * When Port Down timer expires we will start returning
4837 * I/O's to OS with "DID_NO_CONNECT".
4838 *
4839 * Link Down Timeout != 0:
4840 *
4841 * The driver waits for the link to come up after link down
4842 * before returning I/Os to OS with "DID_NO_CONNECT".
4843 */
4844 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4845 ha->loop_down_abort_time =
4846 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4847 } else {
4848 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4849 ha->loop_down_abort_time =
4850 (LOOP_DOWN_TIME - ha->link_down_timeout);
4851 }
4852
4853 /* Need enough time to try and get the port back. */
4854 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4855 if (qlport_down_retry)
4856 ha->port_down_retry_count = qlport_down_retry;
4857
4858 /* Set login_retry_count */
4859 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4860 if (ha->port_down_retry_count ==
4861 le16_to_cpu(nv->port_down_retry_count) &&
4862 ha->port_down_retry_count > 3)
4863 ha->login_retry_count = ha->port_down_retry_count;
4864 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4865 ha->login_retry_count = ha->port_down_retry_count;
4866 if (ql2xloginretrycount)
4867 ha->login_retry_count = ql2xloginretrycount;
4868
4fdfefe5 4869 /* Enable ZIO. */
e315cd28 4870 if (!vha->flags.init_done) {
4fdfefe5
AV		 4871 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4872 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4873 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4874 le16_to_cpu(icb->interrupt_delay_timer): 2;
4875 }
4876 icb->firmware_options_2 &= __constant_cpu_to_le32(
4877 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 4878 vha->flags.process_response_queue = 0;
4fdfefe5 4879 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 4880 ha->zio_mode = QLA_ZIO_MODE_6;
4881
7c3df132 4882 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 4883 "ZIO mode %d enabled; timer delay (%d us).\n",
4884 ha->zio_mode, ha->zio_timer * 100);
4885
4886 icb->firmware_options_2 |= cpu_to_le32(
4887 (uint32_t)ha->zio_mode);
4888 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 4889 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 4890 }
4891
4e08df3f 4892 if (rval) {
7c3df132
SK		 4893 ql_log(ql_log_warn, vha, 0x0070,
4894 "NVRAM configuration failed.\n");
4e08df3f
DM		 4895 }
4896 return (rval);
0107109e
AV		 4897}
4898
413975a0 4899static int
cbc8eb67
AV		 4900qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
4901 uint32_t faddr)
d1c61909 4902{
73208dfd 4903 int rval = QLA_SUCCESS;
d1c61909 4904 int segments, fragment;
d1c61909
AV		 4905 uint32_t *dcode, dlen;
4906 uint32_t risc_addr;
4907 uint32_t risc_size;
4908 uint32_t i;
e315cd28 4909 struct qla_hw_data *ha = vha->hw;
73208dfd 4910 struct req_que *req = ha->req_q_map[0];
eaac30be 4911
7c3df132 4912 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 4913 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 4914
d1c61909
AV		 4915 rval = QLA_SUCCESS;
4916
4917 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 4918 dcode = (uint32_t *)req->ring;
d1c61909
AV		 4919 *srisc_addr = 0;
4920
4921 /* Validate firmware image by checking version. */
e315cd28 4922 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 4923 for (i = 0; i < 4; i++)
4924 dcode[i] = be32_to_cpu(dcode[i]);
4925 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
4926 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
4927 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
4928 dcode[3] == 0)) {
7c3df132
SK		 4929 ql_log(ql_log_fatal, vha, 0x008c,
4930 "Unable to verify the integrity of flash firmware "
4931 "image.\n");
4932 ql_log(ql_log_fatal, vha, 0x008d,
4933 "Firmware data: %08x %08x %08x %08x.\n",
4934 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 4935
4936 return QLA_FUNCTION_FAILED;
4937 }
4938
4939 while (segments && rval == QLA_SUCCESS) {
4940 /* Read segment's load information. */
e315cd28 4941 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 4942
4943 risc_addr = be32_to_cpu(dcode[2]);
4944 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
4945 risc_size = be32_to_cpu(dcode[3]);
4946
4947 fragment = 0;
4948 while (risc_size > 0 && rval == QLA_SUCCESS) {
4949 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
4950 if (dlen > risc_size)
4951 dlen = risc_size;
4952
7c3df132
SK		 4953 ql_dbg(ql_dbg_init, vha, 0x008e,
4954 "Loading risc segment@ risc addr %x "
4955 "number of dwords 0x%x offset 0x%x.\n",
4956 risc_addr, dlen, faddr);
d1c61909 4957
e315cd28 4958 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 4959 for (i = 0; i < dlen; i++)
4960 dcode[i] = swab32(dcode[i]);
4961
73208dfd 4962 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 4963 dlen);
4964 if (rval) {
7c3df132
SK		 4965 ql_log(ql_log_fatal, vha, 0x008f,
4966 "Failed to load segment %d of firmware.\n",
4967 fragment);
d1c61909
AV		 4968 break;
4969 }
4970
4971 faddr += dlen;
4972 risc_addr += dlen;
4973 risc_size -= dlen;
4974 fragment++;
4975 }
4976
4977 /* Next segment. */
4978 segments--;
4979 }
4980
4981 return rval;
4982}
4983
d1c61909
AV		 4984#define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
4985
0107109e 4986int
e315cd28 4987qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 4988{
4989 int rval;
4990 int i, fragment;
4991 uint16_t *wcode, *fwcode;
4992 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
4993 struct fw_blob *blob;
e315cd28 4994 struct qla_hw_data *ha = vha->hw;
73208dfd 4995 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 4996
4997 /* Load firmware blob. */
e315cd28 4998 blob = qla2x00_request_firmware(vha);
5433383e 4999 if (!blob) {
7c3df132
SK		 5000 ql_log(ql_log_info, vha, 0x0083,
5001 "Fimware image unavailable.\n");
5002 ql_log(ql_log_info, vha, 0x0084,
5003 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 5004 return QLA_FUNCTION_FAILED;
5005 }
5006
5007 rval = QLA_SUCCESS;
5008
73208dfd 5009 wcode = (uint16_t *)req->ring;
5433383e
AV		 5010 *srisc_addr = 0;
5011 fwcode = (uint16_t *)blob->fw->data;
5012 fwclen = 0;
5013
5014 /* Validate firmware image by checking version. */
5015 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132
SK		 5016 ql_log(ql_log_fatal, vha, 0x0085,
5017 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e
AV		 5018 blob->fw->size);
5019 goto fail_fw_integrity;
5020 }
5021 for (i = 0; i < 4; i++)
5022 wcode[i] = be16_to_cpu(fwcode[i + 4]);
5023 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
5024 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
5025 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 5026 ql_log(ql_log_fatal, vha, 0x0086,
5027 "Unable to verify integrity of firmware image.\n");
5028 ql_log(ql_log_fatal, vha, 0x0087,
5029 "Firmware data: %04x %04x %04x %04x.\n",
5030 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 5031 goto fail_fw_integrity;
5032 }
5033
5034 seg = blob->segs;
5035 while (*seg && rval == QLA_SUCCESS) {
5036 risc_addr = *seg;
5037 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
5038 risc_size = be16_to_cpu(fwcode[3]);
5039
5040 /* Validate firmware image size. */
5041 fwclen += risc_size * sizeof(uint16_t);
5042 if (blob->fw->size < fwclen) {
7c3df132 5043 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 5044 "Unable to verify integrity of firmware image "
7c3df132 5045 "(%Zd).\n", blob->fw->size);
5433383e
AV		 5046 goto fail_fw_integrity;
5047 }
5048
5049 fragment = 0;
5050 while (risc_size > 0 && rval == QLA_SUCCESS) {
5051 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
5052 if (wlen > risc_size)
5053 wlen = risc_size;
7c3df132
SK		 5054 ql_dbg(ql_dbg_init, vha, 0x0089,
5055 "Loading risc segment@ risc addr %x number of "
5056 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 5057
5058 for (i = 0; i < wlen; i++)
5059 wcode[i] = swab16(fwcode[i]);
5060
73208dfd 5061 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 5062 wlen);
5063 if (rval) {
7c3df132
SK		 5064 ql_log(ql_log_fatal, vha, 0x008a,
5065 "Failed to load segment %d of firmware.\n",
5066 fragment);
5433383e
AV		 5067 break;
5068 }
5069
5070 fwcode += wlen;
5071 risc_addr += wlen;
5072 risc_size -= wlen;
5073 fragment++;
5074 }
5075
5076 /* Next segment. */
5077 seg++;
5078 }
5079 return rval;
5080
5081fail_fw_integrity:
5082 return QLA_FUNCTION_FAILED;
5083}
5084
eaac30be
AV		 5085static int
5086qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 5087{
5088 int rval;
5089 int segments, fragment;
5090 uint32_t *dcode, dlen;
5091 uint32_t risc_addr;
5092 uint32_t risc_size;
5093 uint32_t i;
5433383e 5094 struct fw_blob *blob;
0107109e 5095 uint32_t *fwcode, fwclen;
e315cd28 5096 struct qla_hw_data *ha = vha->hw;
73208dfd 5097 struct req_que *req = ha->req_q_map[0];
0107109e 5098
5433383e 5099 /* Load firmware blob. */
e315cd28 5100 blob = qla2x00_request_firmware(vha);
5433383e 5101 if (!blob) {
7c3df132
SK		 5102 ql_log(ql_log_warn, vha, 0x0090,
5103 "Fimware image unavailable.\n");
5104 ql_log(ql_log_warn, vha, 0x0091,
5105 "Firmware images can be retrieved from: "
5106 QLA_FW_URL ".\n");
d1c61909 5107
eaac30be 5108 return QLA_FUNCTION_FAILED;
0107109e
AV		 5109 }
5110
cfb0919c
CD		 5111 ql_dbg(ql_dbg_init, vha, 0x0092,
5112 "FW: Loading via request-firmware.\n");
eaac30be 5113
0107109e
AV		 5114 rval = QLA_SUCCESS;
5115
5116 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 5117 dcode = (uint32_t *)req->ring;
0107109e 5118 *srisc_addr = 0;
5433383e 5119 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 5120 fwclen = 0;
5121
5122 /* Validate firmware image by checking version. */
5433383e 5123 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132
SK		 5124 ql_log(ql_log_fatal, vha, 0x0093,
5125 "Unable to verify integrity of firmware image (%Zd).\n",
5433383e 5126 blob->fw->size);
0107109e
AV		 5127 goto fail_fw_integrity;
5128 }
5129 for (i = 0; i < 4; i++)
5130 dcode[i] = be32_to_cpu(fwcode[i + 4]);
5131 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
5132 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
5133 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
5134 dcode[3] == 0)) {
7c3df132
SK		 5135 ql_log(ql_log_fatal, vha, 0x0094,
5136 "Unable to verify integrity of firmware image (%Zd).\n",
5137 blob->fw->size);
5138 ql_log(ql_log_fatal, vha, 0x0095,
5139 "Firmware data: %08x %08x %08x %08x.\n",
5140 dcode[0], dcode[1], dcode[2], dcode[3]);
0107109e
AV		 5141 goto fail_fw_integrity;
5142 }
5143
5144 while (segments && rval == QLA_SUCCESS) {
5145 risc_addr = be32_to_cpu(fwcode[2]);
5146 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
5147 risc_size = be32_to_cpu(fwcode[3]);
5148
5149 /* Validate firmware image size. */
5150 fwclen += risc_size * sizeof(uint32_t);
5433383e 5151 if (blob->fw->size < fwclen) {
7c3df132 5152 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 5153 "Unable to verify integrity of firmware image "
7c3df132 5154 "(%Zd).\n", blob->fw->size);
5433383e 5155
0107109e
AV		 5156 goto fail_fw_integrity;
5157 }
5158
5159 fragment = 0;
5160 while (risc_size > 0 && rval == QLA_SUCCESS) {
5161 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
5162 if (dlen > risc_size)
5163 dlen = risc_size;
5164
7c3df132
SK		 5165 ql_dbg(ql_dbg_init, vha, 0x0097,
5166 "Loading risc segment@ risc addr %x "
5167 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 5168
5169 for (i = 0; i < dlen; i++)
5170 dcode[i] = swab32(fwcode[i]);
5171
73208dfd 5172 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 5173 dlen);
0107109e 5174 if (rval) {
7c3df132
SK		 5175 ql_log(ql_log_fatal, vha, 0x0098,
5176 "Failed to load segment %d of firmware.\n",
5177 fragment);
0107109e
AV		 5178 break;
5179 }
5180
5181 fwcode += dlen;
5182 risc_addr += dlen;
5183 risc_size -= dlen;
5184 fragment++;
5185 }
5186
5187 /* Next segment. */
5188 segments--;
5189 }
0107109e
AV		 5190 return rval;
5191
5192fail_fw_integrity:
0107109e 5193 return QLA_FUNCTION_FAILED;
0107109e 5194}
18c6c127 5195
eaac30be
AV		 5196int
5197qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5198{
5199 int rval;
5200
e337d907
AV		 5201 if (ql2xfwloadbin == 1)
5202 return qla81xx_load_risc(vha, srisc_addr);
5203
eaac30be
AV		 5204 /*
5205 * FW Load priority:
5206 * 1) Firmware via request-firmware interface (.bin file).
5207 * 2) Firmware residing in flash.
5208 */
5209 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5210 if (rval == QLA_SUCCESS)
5211 return rval;
5212
cbc8eb67
AV		 5213 return qla24xx_load_risc_flash(vha, srisc_addr,
5214 vha->hw->flt_region_fw);
eaac30be
AV		 5215}
5216
5217int
5218qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5219{
5220 int rval;
cbc8eb67 5221 struct qla_hw_data *ha = vha->hw;
eaac30be 5222
e337d907 5223 if (ql2xfwloadbin == 2)
cbc8eb67 5224 goto try_blob_fw;
e337d907 5225
eaac30be
AV		 5226 /*
5227 * FW Load priority:
5228 * 1) Firmware residing in flash.
5229 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 5230 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 5231 */
cbc8eb67 5232 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 5233 if (rval == QLA_SUCCESS)
5234 return rval;
5235
cbc8eb67
AV		 5236try_blob_fw:
5237 rval = qla24xx_load_risc_blob(vha, srisc_addr);
5238 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
5239 return rval;
5240
7c3df132
SK		 5241 ql_log(ql_log_info, vha, 0x0099,
5242 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 5243 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
5244 if (rval != QLA_SUCCESS)
5245 return rval;
5246
7c3df132 5247 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 5248 ha->flags.running_gold_fw = 1;
cbc8eb67 5249 return rval;
eaac30be
AV		 5250}
5251
18c6c127 5252void
e315cd28 5253qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 5254{
5255 int ret, retries;
e315cd28 5256 struct qla_hw_data *ha = vha->hw;
18c6c127 5257
85880801
AV		 5258 if (ha->flags.pci_channel_io_perm_failure)
5259 return;
e428924c 5260 if (!IS_FWI2_CAPABLE(ha))
18c6c127 5261 return;
75edf81d
AV		 5262 if (!ha->fw_major_version)
5263 return;
18c6c127 5264
e315cd28 5265 ret = qla2x00_stop_firmware(vha);
7c7f1f29 5266 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 5267 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 5268 ha->isp_ops->reset_chip(vha);
5269 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 5270 continue;
e315cd28 5271 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 5272 continue;
7c3df132
SK		 5273 ql_log(ql_log_info, vha, 0x8015,
5274 "Attempting retry of stop-firmware command.\n");
e315cd28 5275 ret = qla2x00_stop_firmware(vha);
18c6c127
AV		 5276 }
5277}
2c3dfe3f
SJ		 5278
5279int
e315cd28 5280qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 5281{
5282 int rval = QLA_SUCCESS;
0b91d116 5283 int rval2;
2c3dfe3f 5284 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 5285 struct qla_hw_data *ha = vha->hw;
5286 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 5287 struct req_que *req;
5288 struct rsp_que *rsp;
2c3dfe3f 5289
e315cd28 5290 if (!vha->vp_idx)
2c3dfe3f
SJ		 5291 return -EINVAL;
5292
e315cd28 5293 rval = qla2x00_fw_ready(base_vha);
7163ea81 5294 if (ha->flags.cpu_affinity_enabled)
67c2e93a
AC		 5295 req = ha->req_q_map[0];
5296 else
5297 req = vha->req;
5298 rsp = req->rsp;
5299
2c3dfe3f 5300 if (rval == QLA_SUCCESS) {
e315cd28 5301 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 5302 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 5303 }
5304
e315cd28 5305 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 5306
5307 /* Login to SNS first */
0b91d116
CD		 5308 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
5309 BIT_1);
5310 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5311 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
5312 ql_dbg(ql_dbg_init, vha, 0x0120,
5313 "Failed SNS login: loop_id=%x, rval2=%d\n",
5314 NPH_SNS, rval2);
5315 else
5316 ql_dbg(ql_dbg_init, vha, 0x0103,
5317 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
5318 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
5319 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 5320 return (QLA_FUNCTION_FAILED);
5321 }
5322
e315cd28
AC		 5323 atomic_set(&vha->loop_down_timer, 0);
5324 atomic_set(&vha->loop_state, LOOP_UP);
5325 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5326 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5327 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 5328
5329 return rval;
5330}
4d4df193
HK		 5331
5332/* 84XX Support **************************************************************/
5333
5334static LIST_HEAD(qla_cs84xx_list);
5335static DEFINE_MUTEX(qla_cs84xx_mutex);
5336
5337static struct qla_chip_state_84xx *
e315cd28 5338qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 5339{
5340 struct qla_chip_state_84xx *cs84xx;
e315cd28 5341 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5342
5343 mutex_lock(&qla_cs84xx_mutex);
5344
5345 /* Find any shared 84xx chip. */
5346 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
5347 if (cs84xx->bus == ha->pdev->bus) {
5348 kref_get(&cs84xx->kref);
5349 goto done;
5350 }
5351 }
5352
5353 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
5354 if (!cs84xx)
5355 goto done;
5356
5357 kref_init(&cs84xx->kref);
5358 spin_lock_init(&cs84xx->access_lock);
5359 mutex_init(&cs84xx->fw_update_mutex);
5360 cs84xx->bus = ha->pdev->bus;
5361
5362 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
5363done:
5364 mutex_unlock(&qla_cs84xx_mutex);
5365 return cs84xx;
5366}
5367
5368static void
5369__qla84xx_chip_release(struct kref *kref)
5370{
5371 struct qla_chip_state_84xx *cs84xx =
5372 container_of(kref, struct qla_chip_state_84xx, kref);
5373
5374 mutex_lock(&qla_cs84xx_mutex);
5375 list_del(&cs84xx->list);
5376 mutex_unlock(&qla_cs84xx_mutex);
5377 kfree(cs84xx);
5378}
5379
5380void
e315cd28 5381qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 5382{
e315cd28 5383 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5384 if (ha->cs84xx)
5385 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
5386}
5387
5388static int
e315cd28 5389qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 5390{
5391 int rval;
5392 uint16_t status[2];
e315cd28 5393 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 5394
5395 mutex_lock(&ha->cs84xx->fw_update_mutex);
5396
e315cd28 5397 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 5398
5399 mutex_unlock(&ha->cs84xx->fw_update_mutex);
5400
5401 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
5402 QLA_SUCCESS;
5403}
3a03eb79
AV		 5404
5405/* 81XX Support **************************************************************/
5406
5407int
5408qla81xx_nvram_config(scsi_qla_host_t *vha)
5409{
5410 int rval;
5411 struct init_cb_81xx *icb;
5412 struct nvram_81xx *nv;
5413 uint32_t *dptr;
5414 uint8_t *dptr1, *dptr2;
5415 uint32_t chksum;
5416 uint16_t cnt;
5417 struct qla_hw_data *ha = vha->hw;
5418
5419 rval = QLA_SUCCESS;
5420 icb = (struct init_cb_81xx *)ha->init_cb;
5421 nv = ha->nvram;
5422
5423 /* Determine NVRAM starting address. */
5424 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 5425 ha->vpd_size = FA_NVRAM_VPD_SIZE;
3a03eb79
AV		 5426
5427 /* Get VPD data into cache */
5428 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 5429 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5430 ha->vpd_size);
3a03eb79
AV		 5431
5432 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 5433 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 5434 ha->nvram_size);
3d79038f 5435 dptr = (uint32_t *)nv;
3a03eb79
AV		 5436 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5437 chksum += le32_to_cpu(*dptr++);
5438
7c3df132
SK		 5439 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5440 "Contents of NVRAM:\n");
5441 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5442 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 5443
5444 /* Bad NVRAM data, set defaults parameters. */
5445 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5446 || nv->id[3] != ' ' ||
5447 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5448 /* Reset NVRAM data. */
7c3df132 5449 ql_log(ql_log_info, vha, 0x0073,
9e336520 5450 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 5451 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 5452 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 5453 ql_log(ql_log_info, vha, 0x0074,
5454 "Falling back to functioning (yet invalid -- WWPN) "
5455 "defaults.\n");
3a03eb79
AV		 5456
5457 /*
5458 * Set default initialization control block.
5459 */
5460 memset(nv, 0, ha->nvram_size);
5461 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5462 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5463 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5464 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5465 nv->exchange_count = __constant_cpu_to_le16(0);
5466 nv->port_name[0] = 0x21;
e5b68a61 5467 nv->port_name[1] = 0x00 + ha->port_no;
3a03eb79
AV		 5468 nv->port_name[2] = 0x00;
5469 nv->port_name[3] = 0xe0;
5470 nv->port_name[4] = 0x8b;
5471 nv->port_name[5] = 0x1c;
5472 nv->port_name[6] = 0x55;
5473 nv->port_name[7] = 0x86;
5474 nv->node_name[0] = 0x20;
5475 nv->node_name[1] = 0x00;
5476 nv->node_name[2] = 0x00;
5477 nv->node_name[3] = 0xe0;
5478 nv->node_name[4] = 0x8b;
5479 nv->node_name[5] = 0x1c;
5480 nv->node_name[6] = 0x55;
5481 nv->node_name[7] = 0x86;
5482 nv->login_retry_count = __constant_cpu_to_le16(8);
5483 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5484 nv->login_timeout = __constant_cpu_to_le16(0);
5485 nv->firmware_options_1 =
5486 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5487 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5488 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5489 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5490 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5491 nv->efi_parameters = __constant_cpu_to_le32(0);
5492 nv->reset_delay = 5;
5493 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5494 nv->port_down_retry_count = __constant_cpu_to_le16(30);
6246b8a1 5495 nv->link_down_timeout = __constant_cpu_to_le16(180);
eeebcc92 5496 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 5497 nv->enode_mac[1] = 0xC0;
5498 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 5499 nv->enode_mac[3] = 0x04;
5500 nv->enode_mac[4] = 0x05;
e5b68a61 5501 nv->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5502
5503 rval = 1;
5504 }
5505
5506 /* Reset Initialization control block */
773120e4 5507 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 5508
5509 /* Copy 1st segment. */
5510 dptr1 = (uint8_t *)icb;
5511 dptr2 = (uint8_t *)&nv->version;
5512 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5513 while (cnt--)
5514 *dptr1++ = *dptr2++;
5515
5516 icb->login_retry_count = nv->login_retry_count;
5517
5518 /* Copy 2nd segment. */
5519 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5520 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5521 cnt = (uint8_t *)&icb->reserved_5 -
5522 (uint8_t *)&icb->interrupt_delay_timer;
5523 while (cnt--)
5524 *dptr1++ = *dptr2++;
5525
5526 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5527 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
5528 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 5529 icb->enode_mac[0] = 0x00;
5530 icb->enode_mac[1] = 0xC0;
5531 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 5532 icb->enode_mac[3] = 0x04;
5533 icb->enode_mac[4] = 0x05;
e5b68a61 5534 icb->enode_mac[5] = 0x06 + ha->port_no;
3a03eb79
AV		 5535 }
5536
b64b0e8f
AV		 5537 /* Use extended-initialization control block. */
5538 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5539
3a03eb79
AV		 5540 /*
5541 * Setup driver NVRAM options.
5542 */
5543 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 5544 "QLE8XXX");
3a03eb79
AV		 5545
5546 /* Use alternate WWN? */
5547 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5548 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5549 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5550 }
5551
5552 /* Prepare nodename */
5553 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5554 /*
5555 * Firmware will apply the following mask if the nodename was
5556 * not provided.
5557 */
5558 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5559 icb->node_name[0] &= 0xF0;
5560 }
5561
5562 /* Set host adapter parameters. */
5563 ha->flags.disable_risc_code_load = 0;
5564 ha->flags.enable_lip_reset = 0;
5565 ha->flags.enable_lip_full_login =
5566 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5567 ha->flags.enable_target_reset =
5568 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5569 ha->flags.enable_led_scheme = 0;
5570 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5571
5572 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5573 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5574
5575 /* save HBA serial number */
5576 ha->serial0 = icb->port_name[5];
5577 ha->serial1 = icb->port_name[6];
5578 ha->serial2 = icb->port_name[7];
5579 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5580 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5581
5582 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5583
5584 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5585
5586 /* Set minimum login_timeout to 4 seconds. */
5587 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5588 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5589 if (le16_to_cpu(nv->login_timeout) < 4)
5590 nv->login_timeout = __constant_cpu_to_le16(4);
5591 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5592 icb->login_timeout = nv->login_timeout;
5593
5594 /* Set minimum RATOV to 100 tenths of a second. */
5595 ha->r_a_tov = 100;
5596
5597 ha->loop_reset_delay = nv->reset_delay;
5598
5599 /* Link Down Timeout = 0:
5600 *
5601 * When Port Down timer expires we will start returning
5602 * I/O's to OS with "DID_NO_CONNECT".
5603 *
5604 * Link Down Timeout != 0:
5605 *
5606 * The driver waits for the link to come up after link down
5607 * before returning I/Os to OS with "DID_NO_CONNECT".
5608 */
5609 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5610 ha->loop_down_abort_time =
5611 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5612 } else {
5613 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5614 ha->loop_down_abort_time =
5615 (LOOP_DOWN_TIME - ha->link_down_timeout);
5616 }
5617
5618 /* Need enough time to try and get the port back. */
5619 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5620 if (qlport_down_retry)
5621 ha->port_down_retry_count = qlport_down_retry;
5622
5623 /* Set login_retry_count */
5624 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5625 if (ha->port_down_retry_count ==
5626 le16_to_cpu(nv->port_down_retry_count) &&
5627 ha->port_down_retry_count > 3)
5628 ha->login_retry_count = ha->port_down_retry_count;
5629 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5630 ha->login_retry_count = ha->port_down_retry_count;
5631 if (ql2xloginretrycount)
5632 ha->login_retry_count = ql2xloginretrycount;
5633
6246b8a1
GM		 5634 /* if not running MSI-X we need handshaking on interrupts */
5635 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5636 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5637
3a03eb79
AV		 5638 /* Enable ZIO. */
5639 if (!vha->flags.init_done) {
5640 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5641 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5642 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5643 le16_to_cpu(icb->interrupt_delay_timer): 2;
5644 }
5645 icb->firmware_options_2 &= __constant_cpu_to_le32(
5646 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5647 vha->flags.process_response_queue = 0;
5648 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5649 ha->zio_mode = QLA_ZIO_MODE_6;
5650
7c3df132 5651 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 5652 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 5653 ha->zio_mode,
5654 ha->zio_timer * 100);
3a03eb79
AV		 5655
5656 icb->firmware_options_2 |= cpu_to_le32(
5657 (uint32_t)ha->zio_mode);
5658 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5659 vha->flags.process_response_queue = 1;
5660 }
5661
5662 if (rval) {
7c3df132
SK		 5663 ql_log(ql_log_warn, vha, 0x0076,
5664 "NVRAM configuration failed.\n");
3a03eb79
AV		 5665 }
5666 return (rval);
5667}
5668
a9083016
GM		 5669int
5670qla82xx_restart_isp(scsi_qla_host_t *vha)
5671{
5672 int status, rval;
5673 uint32_t wait_time;
5674 struct qla_hw_data *ha = vha->hw;
5675 struct req_que *req = ha->req_q_map[0];
5676 struct rsp_que *rsp = ha->rsp_q_map[0];
5677 struct scsi_qla_host *vp;
feafb7b1 5678 unsigned long flags;
a9083016
GM		 5679
5680 status = qla2x00_init_rings(vha);
5681 if (!status) {
5682 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5683 ha->flags.chip_reset_done = 1;
5684
5685 status = qla2x00_fw_ready(vha);
5686 if (!status) {
7c3df132
SK		 5687 ql_log(ql_log_info, vha, 0x803c,
5688 "Start configure loop, status =%d.\n", status);
a9083016
GM		 5689
5690 /* Issue a marker after FW becomes ready. */
5691 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5692
5693 vha->flags.online = 1;
5694 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5695 wait_time = 256;
5696 do {
5697 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5698 qla2x00_configure_loop(vha);
5699 wait_time--;
5700 } while (!atomic_read(&vha->loop_down_timer) &&
5701 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5702 wait_time &&
5703 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5704 }
5705
5706 /* if no cable then assume it's good */
5707 if ((vha->device_flags & DFLG_NO_CABLE))
5708 status = 0;
5709
cfb0919c 5710 ql_log(ql_log_info, vha, 0x8000,
7c3df132 5711 "Configure loop done, status = 0x%x.\n", status);
a9083016
GM		 5712 }
5713
5714 if (!status) {
5715 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5716
5717 if (!atomic_read(&vha->loop_down_timer)) {
5718 /*
5719 * Issue marker command only when we are going
5720 * to start the I/O .
5721 */
5722 vha->marker_needed = 1;
5723 }
5724
5725 vha->flags.online = 1;
5726
5727 ha->isp_ops->enable_intrs(ha);
5728
5729 ha->isp_abort_cnt = 0;
5730 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5731
53296788 5732 /* Update the firmware version */
3173167f 5733 status = qla82xx_check_md_needed(vha);
53296788 5734
a9083016
GM		 5735 if (ha->fce) {
5736 ha->flags.fce_enabled = 1;
5737 memset(ha->fce, 0,
5738 fce_calc_size(ha->fce_bufs));
5739 rval = qla2x00_enable_fce_trace(vha,
5740 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5741 &ha->fce_bufs);
5742 if (rval) {
cfb0919c 5743 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 5744 "Unable to reinitialize FCE (%d).\n",
5745 rval);
a9083016
GM		 5746 ha->flags.fce_enabled = 0;
5747 }
5748 }
5749
5750 if (ha->eft) {
5751 memset(ha->eft, 0, EFT_SIZE);
5752 rval = qla2x00_enable_eft_trace(vha,
5753 ha->eft_dma, EFT_NUM_BUFFERS);
5754 if (rval) {
cfb0919c 5755 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 5756 "Unable to reinitialize EFT (%d).\n",
5757 rval);
a9083016
GM		 5758 }
5759 }
a9083016
GM		 5760 }
5761
5762 if (!status) {
cfb0919c 5763 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 5764 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 5765
5766 spin_lock_irqsave(&ha->vport_slock, flags);
5767 list_for_each_entry(vp, &ha->vp_list, list) {
5768 if (vp->vp_idx) {
5769 atomic_inc(&vp->vref_count);
5770 spin_unlock_irqrestore(&ha->vport_slock, flags);
5771
a9083016 5772 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 5773
5774 spin_lock_irqsave(&ha->vport_slock, flags);
5775 atomic_dec(&vp->vref_count);
5776 }
a9083016 5777 }
feafb7b1
AE		 5778 spin_unlock_irqrestore(&ha->vport_slock, flags);
5779
a9083016 5780 } else {
cfb0919c 5781 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 5782 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 5783 }
5784
5785 return status;
5786}
5787
3a03eb79 5788void
ae97c91e 5789qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 5790{
ae97c91e
AV		 5791 struct qla_hw_data *ha = vha->hw;
5792
5793 if (!ql2xetsenable)
5794 return;
5795
5796 /* Enable ETS Burst. */
5797 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5798 ha->fw_options[2] |= BIT_9;
5799 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 5800}
09ff701a
SR		 5801
5802/*
5803 * qla24xx_get_fcp_prio
5804 * Gets the fcp cmd priority value for the logged in port.
5805 * Looks for a match of the port descriptors within
5806 * each of the fcp prio config entries. If a match is found,
5807 * the tag (priority) value is returned.
5808 *
5809 * Input:
21090cbe 5810 * vha = scsi host structure pointer.
09ff701a
SR		 5811 * fcport = port structure pointer.
5812 *
5813 * Return:
6c452a45 5814 * non-zero (if found)
f28a0a96 5815 * -1 (if not found)
09ff701a
SR		 5816 *
5817 * Context:
5818 * Kernel context
5819 */
f28a0a96 5820static int
09ff701a
SR		 5821qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5822{
5823 int i, entries;
5824 uint8_t pid_match, wwn_match;
f28a0a96 5825 int priority;
09ff701a
SR		 5826 uint32_t pid1, pid2;
5827 uint64_t wwn1, wwn2;
5828 struct qla_fcp_prio_entry *pri_entry;
5829 struct qla_hw_data *ha = vha->hw;
5830
5831 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 5832 return -1;
09ff701a 5833
f28a0a96 5834 priority = -1;
09ff701a
SR		 5835 entries = ha->fcp_prio_cfg->num_entries;
5836 pri_entry = &ha->fcp_prio_cfg->entry[0];
5837
5838 for (i = 0; i < entries; i++) {
5839 pid_match = wwn_match = 0;
5840
5841 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5842 pri_entry++;
5843 continue;
5844 }
5845
5846 /* check source pid for a match */
5847 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5848 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5849 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5850 if (pid1 == INVALID_PORT_ID)
5851 pid_match++;
5852 else if (pid1 == pid2)
5853 pid_match++;
5854 }
5855
5856 /* check destination pid for a match */
5857 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5858 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5859 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5860 if (pid1 == INVALID_PORT_ID)
5861 pid_match++;
5862 else if (pid1 == pid2)
5863 pid_match++;
5864 }
5865
5866 /* check source WWN for a match */
5867 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5868 wwn1 = wwn_to_u64(vha->port_name);
5869 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5870 if (wwn2 == (uint64_t)-1)
5871 wwn_match++;
5872 else if (wwn1 == wwn2)
5873 wwn_match++;
5874 }
5875
5876 /* check destination WWN for a match */
5877 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5878 wwn1 = wwn_to_u64(fcport->port_name);
5879 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
5880 if (wwn2 == (uint64_t)-1)
5881 wwn_match++;
5882 else if (wwn1 == wwn2)
5883 wwn_match++;
5884 }
5885
5886 if (pid_match == 2 || wwn_match == 2) {
5887 /* Found a matching entry */
5888 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
5889 priority = pri_entry->tag;
5890 break;
5891 }
5892
5893 pri_entry++;
5894 }
5895
5896 return priority;
5897}
5898
5899/*
5900 * qla24xx_update_fcport_fcp_prio
5901 * Activates fcp priority for the logged in fc port
5902 *
5903 * Input:
21090cbe 5904 * vha = scsi host structure pointer.
09ff701a
SR		 5905 * fcp = port structure pointer.
5906 *
5907 * Return:
5908 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5909 *
5910 * Context:
5911 * Kernel context.
5912 */
5913int
21090cbe 5914qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 5915{
5916 int ret;
f28a0a96 5917 int priority;
09ff701a
SR		 5918 uint16_t mb[5];
5919
21090cbe
MI		 5920 if (fcport->port_type != FCT_TARGET ||
5921 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 5922 return QLA_FUNCTION_FAILED;
5923
21090cbe 5924 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 5925 if (priority < 0)
5926 return QLA_FUNCTION_FAILED;
5927
a00f6296
SK		 5928 if (IS_QLA82XX(vha->hw)) {
5929 fcport->fcp_prio = priority & 0xf;
5930 return QLA_SUCCESS;
5931 }
5932
21090cbe 5933 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 5934 if (ret == QLA_SUCCESS) {
5935 if (fcport->fcp_prio != priority)
5936 ql_dbg(ql_dbg_user, vha, 0x709e,
5937 "Updated FCP_CMND priority - value=%d loop_id=%d "
5938 "port_id=%02x%02x%02x.\n", priority,
5939 fcport->loop_id, fcport->d_id.b.domain,
5940 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 5941 fcport->fcp_prio = priority & 0xf;
cfb0919c 5942 } else
7c3df132 5943 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 5944 "Unable to update FCP_CMND priority - ret=0x%x for "
5945 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
5946 fcport->d_id.b.domain, fcport->d_id.b.area,
5947 fcport->d_id.b.al_pa);
09ff701a
SR		 5948 return ret;
5949}
5950
5951/*
5952 * qla24xx_update_all_fcp_prio
5953 * Activates fcp priority for all the logged in ports
5954 *
5955 * Input:
5956 * ha = adapter block pointer.
5957 *
5958 * Return:
5959 * QLA_SUCCESS or QLA_FUNCTION_FAILED
5960 *
5961 * Context:
5962 * Kernel context.
5963 */
5964int
5965qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
5966{
5967 int ret;
5968 fc_port_t *fcport;
5969
5970 ret = QLA_FUNCTION_FAILED;
5971 /* We need to set priority for all logged in ports */
5972 list_for_each_entry(fcport, &vha->vp_fcports, list)
5973 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
5974
5975 return ret;
5976}
kernel source for telekom puls (alcatel/mediatek)