[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / qla2xxx / qla_dbg.h

/*
 * QLogic Fibre Channel HBA Driver
 * Copyright (c)  2003-2005 QLogic Corporation
 *
 * See LICENSE.qla2xxx for copyright and licensing details.
 */
/*
 * Driver debug definitions.
 */
/* #define QL_DEBUG_LEVEL_1  */ /* Output register accesses to COM1 */
/* #define QL_DEBUG_LEVEL_2  */ /* Output error msgs to COM1 */
/* #define QL_DEBUG_LEVEL_3  */ /* Output function trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_4  */ /* Output NVRAM trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_5  */ /* Output ring trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_6  */ /* Output WATCHDOG timer trace to COM1 */
/* #define QL_DEBUG_LEVEL_7  */ /* Output RISC load trace msgs to COM1 */
/* #define QL_DEBUG_LEVEL_8  */ /* Output ring saturation msgs to COM1 */
/* #define QL_DEBUG_LEVEL_9  */ /* Output IOCTL trace msgs */
/* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */
/* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */
/* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */
/* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */
/* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */
/* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */
/*
 *  Local Macro Definitions.
 */
#if defined(QL_DEBUG_LEVEL_1)  || defined(QL_DEBUG_LEVEL_2) || \
    defined(QL_DEBUG_LEVEL_3)  || defined(QL_DEBUG_LEVEL_4) || \
    defined(QL_DEBUG_LEVEL_5)  || defined(QL_DEBUG_LEVEL_6) || \
    defined(QL_DEBUG_LEVEL_7)  || defined(QL_DEBUG_LEVEL_8) || \
    defined(QL_DEBUG_LEVEL_9)  || defined(QL_DEBUG_LEVEL_10) || \
    defined(QL_DEBUG_LEVEL_11) || defined(QL_DEBUG_LEVEL_12) || \
    defined(QL_DEBUG_LEVEL_13) || defined(QL_DEBUG_LEVEL_14) || \
    defined(QL_DEBUG_LEVEL_15)
    #define QL_DEBUG_ROUTINES
#endif

/*
* Macros use for debugging the driver.
*/

#define DEBUG(x)	do { if (ql2xextended_error_logging) { x; } } while (0)

#if defined(QL_DEBUG_LEVEL_1)
#define DEBUG1(x)	do {x;} while (0)
#else
#define DEBUG1(x)	do {} while (0)
#endif

#define DEBUG2(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_3(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_3_11(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_9_10(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_11(x)	do { if (ql2xextended_error_logging) { x; } } while (0)
#define DEBUG2_13(x)	do { if (ql2xextended_error_logging) { x; } } while (0)

#if defined(QL_DEBUG_LEVEL_3)
#define DEBUG3(x)	do {x;} while (0)
#define DEBUG3_11(x)	do {x;} while (0)
#else
#define DEBUG3(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_4)
#define DEBUG4(x)	do {x;} while (0)
#else
#define DEBUG4(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_5)
#define DEBUG5(x)          do {x;} while (0)
#else
#define DEBUG5(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_7)
#define DEBUG7(x)          do {x;} while (0)
#else
#define DEBUG7(x)	   do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_9)
#define DEBUG9(x)       do {x;} while (0)
#define DEBUG9_10(x)    do {x;} while (0)
#else
#define DEBUG9(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_10)
#define DEBUG10(x)      do {x;} while (0)
#define DEBUG9_10(x)	do {x;} while (0)
#else
#define DEBUG10(x)	do {} while (0)
  #if !defined(DEBUG9_10)
  #define DEBUG9_10(x)	do {} while (0)
  #endif
#endif

#if defined(QL_DEBUG_LEVEL_11)
#define DEBUG11(x)      do{x;} while(0)
#if !defined(DEBUG3_11)
#define DEBUG3_11(x)    do{x;} while(0)
#endif
#else
#define DEBUG11(x)	do{} while(0)
  #if !defined(QL_DEBUG_LEVEL_3)
  #define DEBUG3_11(x)	do{} while(0)
  #endif
#endif

#if defined(QL_DEBUG_LEVEL_12)
#define DEBUG12(x)      do {x;} while (0)
#else
#define DEBUG12(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_13)
#define DEBUG13(x)      do {x;} while (0)
#else
#define DEBUG13(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_14)
#define DEBUG14(x)      do {x;} while (0)
#else
#define DEBUG14(x)	do {} while (0)
#endif

#if defined(QL_DEBUG_LEVEL_15)
#define DEBUG15(x)      do {x;} while (0)
#else
#define DEBUG15(x)	do {} while (0)
#endif

/*
 * Firmware Dump structure definition
 */

struct qla2300_fw_dump {
	uint16_t hccr;
	uint16_t pbiu_reg[8];
	uint16_t risc_host_reg[8];
	uint16_t mailbox_reg[32];
	uint16_t resp_dma_reg[32];
	uint16_t dma_reg[48];
	uint16_t risc_hdw_reg[16];
	uint16_t risc_gp0_reg[16];
	uint16_t risc_gp1_reg[16];
	uint16_t risc_gp2_reg[16];
	uint16_t risc_gp3_reg[16];
	uint16_t risc_gp4_reg[16];
	uint16_t risc_gp5_reg[16];
	uint16_t risc_gp6_reg[16];
	uint16_t risc_gp7_reg[16];
	uint16_t frame_buf_hdw_reg[64];
	uint16_t fpm_b0_reg[64];
	uint16_t fpm_b1_reg[64];
	uint16_t risc_ram[0xf800];
	uint16_t stack_ram[0x1000];
	uint16_t data_ram[1];
};

struct qla2100_fw_dump {
	uint16_t hccr;
	uint16_t pbiu_reg[8];
	uint16_t mailbox_reg[32];
	uint16_t dma_reg[48];
	uint16_t risc_hdw_reg[16];
	uint16_t risc_gp0_reg[16];
	uint16_t risc_gp1_reg[16];
	uint16_t risc_gp2_reg[16];
	uint16_t risc_gp3_reg[16];
	uint16_t risc_gp4_reg[16];
	uint16_t risc_gp5_reg[16];
	uint16_t risc_gp6_reg[16];
	uint16_t risc_gp7_reg[16];
	uint16_t frame_buf_hdw_reg[16];
	uint16_t fpm_b0_reg[64];
	uint16_t fpm_b1_reg[64];
	uint16_t risc_ram[0xf000];
};

struct qla24xx_fw_dump {
	uint32_t host_status;
	uint32_t host_reg[32];
	uint32_t shadow_reg[7];
	uint16_t mailbox_reg[32];
	uint32_t xseq_gp_reg[128];
	uint32_t xseq_0_reg[16];
	uint32_t xseq_1_reg[16];
	uint32_t rseq_gp_reg[128];
	uint32_t rseq_0_reg[16];
	uint32_t rseq_1_reg[16];
	uint32_t rseq_2_reg[16];
	uint32_t cmd_dma_reg[16];
	uint32_t req0_dma_reg[15];
	uint32_t resp0_dma_reg[15];
	uint32_t req1_dma_reg[15];
	uint32_t xmt0_dma_reg[32];
	uint32_t xmt1_dma_reg[32];
	uint32_t xmt2_dma_reg[32];
	uint32_t xmt3_dma_reg[32];
	uint32_t xmt4_dma_reg[32];
	uint32_t xmt_data_dma_reg[16];
	uint32_t rcvt0_data_dma_reg[32];
	uint32_t rcvt1_data_dma_reg[32];
	uint32_t risc_gp_reg[128];
	uint32_t lmc_reg[112];
	uint32_t fpm_hdw_reg[192];
	uint32_t fb_hdw_reg[176];
	uint32_t code_ram[0x2000];
	uint32_t ext_mem[1];
};

#define EFT_NUM_BUFFERS		4
#define EFT_BYTES_PER_BUFFER	0x4000
#define EFT_SIZE		((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))

struct qla2xxx_fw_dump {
	uint8_t signature[4];
	uint32_t version;

	uint32_t fw_major_version;
	uint32_t fw_minor_version;
	uint32_t fw_subminor_version;
	uint32_t fw_attributes;

	uint32_t vendor;
	uint32_t device;
	uint32_t subsystem_vendor;
	uint32_t subsystem_device;

	uint32_t fixed_size;
	uint32_t mem_size;
	uint32_t req_q_size;
	uint32_t rsp_q_size;

	uint32_t eft_size;
	uint32_t eft_addr_l;
	uint32_t eft_addr_h;

	uint32_t header_size;

	union {
		struct qla2100_fw_dump isp21;
		struct qla2300_fw_dump isp23;
		struct qla24xx_fw_dump isp24;
	} isp;
};
Commit	Line	Data
fa90c54f AV	1	/*
	2	* QLogic Fibre Channel HBA Driver
	3	* Copyright (c) 2003-2005 QLogic Corporation
1da177e4	4	*
fa90c54f AV	5	* See LICENSE.qla2xxx for copyright and licensing details.
fa90c54f AV	6	*/
1da177e4 LT	7	/*
	8	* Driver debug definitions.
	9	*/
	10	/* #define QL_DEBUG_LEVEL_1 / / Output register accesses to COM1 */
	11	/* #define QL_DEBUG_LEVEL_2 / / Output error msgs to COM1 */
	12	/* #define QL_DEBUG_LEVEL_3 / / Output function trace msgs to COM1 */
	13	/* #define QL_DEBUG_LEVEL_4 / / Output NVRAM trace msgs to COM1 */
	14	/* #define QL_DEBUG_LEVEL_5 / / Output ring trace msgs to COM1 */
	15	/* #define QL_DEBUG_LEVEL_6 / / Output WATCHDOG timer trace to COM1 */
	16	/* #define QL_DEBUG_LEVEL_7 / / Output RISC load trace msgs to COM1 */
	17	/* #define QL_DEBUG_LEVEL_8 / / Output ring saturation msgs to COM1 */
	18	/* #define QL_DEBUG_LEVEL_9 / / Output IOCTL trace msgs */
	19	/* #define QL_DEBUG_LEVEL_10 / / Output IOCTL error msgs */
	20	/* #define QL_DEBUG_LEVEL_11 / / Output Mbx Cmd trace msgs */
	21	/* #define QL_DEBUG_LEVEL_12 / / Output IP trace msgs */
	22	/* #define QL_DEBUG_LEVEL_13 / / Output fdmi function trace msgs */
	23	/* #define QL_DEBUG_LEVEL_14 / / Output RSCN trace msgs */
2c3dfe3f	24	/* #define QL_DEBUG_LEVEL_15 / / Output NPIV trace msgs */
1da177e4 LT	25	/*
	26	* Local Macro Definitions.
	27	*/
	28	#if defined(QL_DEBUG_LEVEL_1) \|\| defined(QL_DEBUG_LEVEL_2) \|\| \
	29	defined(QL_DEBUG_LEVEL_3) \|\| defined(QL_DEBUG_LEVEL_4) \|\| \
	30	defined(QL_DEBUG_LEVEL_5) \|\| defined(QL_DEBUG_LEVEL_6) \|\| \
	31	defined(QL_DEBUG_LEVEL_7) \|\| defined(QL_DEBUG_LEVEL_8) \|\| \
	32	defined(QL_DEBUG_LEVEL_9) \|\| defined(QL_DEBUG_LEVEL_10) \|\| \
	33	defined(QL_DEBUG_LEVEL_11) \|\| defined(QL_DEBUG_LEVEL_12) \|\| \
2c3dfe3f SJ	34	defined(QL_DEBUG_LEVEL_13) \|\| defined(QL_DEBUG_LEVEL_14) \|\| \
2c3dfe3f SJ	35	defined(QL_DEBUG_LEVEL_15)
1da177e4 LT	36	#define QL_DEBUG_ROUTINES
	37	#endif
	38
	39	/*
	40	* Macros use for debugging the driver.
	41	*/
1da177e4	42
11010fec	43	#define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0)
1da177e4 LT	44
1da177e4 LT	45	#if defined(QL_DEBUG_LEVEL_1)
744f11fd	46	#define DEBUG1(x) do {x;} while (0)
1da177e4	47	#else
744f11fd	48	#define DEBUG1(x) do {} while (0)
1da177e4 LT	49	#endif
1da177e4 LT	50
11010fec AV	51	#define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	52	#define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	53	#define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	54	#define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	55	#define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0)
	56	#define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0)
1da177e4 LT	57
1da177e4 LT	58	#if defined(QL_DEBUG_LEVEL_3)
744f11fd	59	#define DEBUG3(x) do {x;} while (0)
744f11fd	60	#define DEBUG3_11(x) do {x;} while (0)
1da177e4	61	#else
744f11fd	62	#define DEBUG3(x) do {} while (0)
1da177e4 LT	63	#endif
	64
	65	#if defined(QL_DEBUG_LEVEL_4)
744f11fd	66	#define DEBUG4(x) do {x;} while (0)
1da177e4	67	#else
744f11fd	68	#define DEBUG4(x) do {} while (0)
1da177e4 LT	69	#endif
	70
	71	#if defined(QL_DEBUG_LEVEL_5)
744f11fd	72	#define DEBUG5(x) do {x;} while (0)
1da177e4	73	#else
744f11fd	74	#define DEBUG5(x) do {} while (0)
1da177e4 LT	75	#endif
	76
	77	#if defined(QL_DEBUG_LEVEL_7)
744f11fd	78	#define DEBUG7(x) do {x;} while (0)
1da177e4	79	#else
744f11fd	80	#define DEBUG7(x) do {} while (0)
1da177e4 LT	81	#endif
	82
	83	#if defined(QL_DEBUG_LEVEL_9)
744f11fd AV	84	#define DEBUG9(x) do {x;} while (0)
744f11fd AV	85	#define DEBUG9_10(x) do {x;} while (0)
1da177e4	86	#else
744f11fd	87	#define DEBUG9(x) do {} while (0)
1da177e4 LT	88	#endif
	89
	90	#if defined(QL_DEBUG_LEVEL_10)
744f11fd	91	#define DEBUG10(x) do {x;} while (0)
744f11fd	92	#define DEBUG9_10(x) do {x;} while (0)
1da177e4	93	#else
744f11fd	94	#define DEBUG10(x) do {} while (0)
1da177e4	95	#if !defined(DEBUG9_10)
744f11fd	96	#define DEBUG9_10(x) do {} while (0)
1da177e4 LT	97	#endif
	98	#endif
	99
	100	#if defined(QL_DEBUG_LEVEL_11)
744f11fd	101	#define DEBUG11(x) do{x;} while(0)
1da177e4	102	#if !defined(DEBUG3_11)
744f11fd	103	#define DEBUG3_11(x) do{x;} while(0)
1da177e4 LT	104	#endif
1da177e4 LT	105	#else
744f11fd	106	#define DEBUG11(x) do{} while(0)
1da177e4	107	#if !defined(QL_DEBUG_LEVEL_3)
744f11fd	108	#define DEBUG3_11(x) do{} while(0)
1da177e4 LT	109	#endif
	110	#endif
	111
	112	#if defined(QL_DEBUG_LEVEL_12)
744f11fd	113	#define DEBUG12(x) do {x;} while (0)
1da177e4	114	#else
744f11fd	115	#define DEBUG12(x) do {} while (0)
1da177e4 LT	116	#endif
	117
	118	#if defined(QL_DEBUG_LEVEL_13)
	119	#define DEBUG13(x) do {x;} while (0)
	120	#else
	121	#define DEBUG13(x) do {} while (0)
	122	#endif
	123
	124	#if defined(QL_DEBUG_LEVEL_14)
	125	#define DEBUG14(x) do {x;} while (0)
	126	#else
	127	#define DEBUG14(x) do {} while (0)
	128	#endif
	129
2c3dfe3f SJ	130	#if defined(QL_DEBUG_LEVEL_15)
	131	#define DEBUG15(x) do {x;} while (0)
	132	#else
	133	#define DEBUG15(x) do {} while (0)
	134	#endif
	135
1da177e4 LT	136	/*
	137	* Firmware Dump structure definition
	138	*/
1da177e4 LT	139
	140	struct qla2300_fw_dump {
	141	uint16_t hccr;
	142	uint16_t pbiu_reg[8];
	143	uint16_t risc_host_reg[8];
	144	uint16_t mailbox_reg[32];
	145	uint16_t resp_dma_reg[32];
	146	uint16_t dma_reg[48];
	147	uint16_t risc_hdw_reg[16];
	148	uint16_t risc_gp0_reg[16];
	149	uint16_t risc_gp1_reg[16];
	150	uint16_t risc_gp2_reg[16];
	151	uint16_t risc_gp3_reg[16];
	152	uint16_t risc_gp4_reg[16];
	153	uint16_t risc_gp5_reg[16];
	154	uint16_t risc_gp6_reg[16];
	155	uint16_t risc_gp7_reg[16];
	156	uint16_t frame_buf_hdw_reg[64];
	157	uint16_t fpm_b0_reg[64];
	158	uint16_t fpm_b1_reg[64];
	159	uint16_t risc_ram[0xf800];
	160	uint16_t stack_ram[0x1000];
	161	uint16_t data_ram[1];
	162	};
	163
	164	struct qla2100_fw_dump {
	165	uint16_t hccr;
	166	uint16_t pbiu_reg[8];
	167	uint16_t mailbox_reg[32];
	168	uint16_t dma_reg[48];
	169	uint16_t risc_hdw_reg[16];
	170	uint16_t risc_gp0_reg[16];
	171	uint16_t risc_gp1_reg[16];
	172	uint16_t risc_gp2_reg[16];
	173	uint16_t risc_gp3_reg[16];
	174	uint16_t risc_gp4_reg[16];
	175	uint16_t risc_gp5_reg[16];
	176	uint16_t risc_gp6_reg[16];
	177	uint16_t risc_gp7_reg[16];
	178	uint16_t frame_buf_hdw_reg[16];
	179	uint16_t fpm_b0_reg[64];
	180	uint16_t fpm_b1_reg[64];
	181	uint16_t risc_ram[0xf000];
	182	};
	183
6d9b61ed	184	struct qla24xx_fw_dump {
210d5350	185	uint32_t host_status;
6d9b61ed	186	uint32_t host_reg[32];
210d5350	187	uint32_t shadow_reg[7];
6d9b61ed AV	188	uint16_t mailbox_reg[32];
	189	uint32_t xseq_gp_reg[128];
	190	uint32_t xseq_0_reg[16];
	191	uint32_t xseq_1_reg[16];
	192	uint32_t rseq_gp_reg[128];
	193	uint32_t rseq_0_reg[16];
	194	uint32_t rseq_1_reg[16];
	195	uint32_t rseq_2_reg[16];
	196	uint32_t cmd_dma_reg[16];
	197	uint32_t req0_dma_reg[15];
	198	uint32_t resp0_dma_reg[15];
	199	uint32_t req1_dma_reg[15];
	200	uint32_t xmt0_dma_reg[32];
	201	uint32_t xmt1_dma_reg[32];
	202	uint32_t xmt2_dma_reg[32];
	203	uint32_t xmt3_dma_reg[32];
	204	uint32_t xmt4_dma_reg[32];
	205	uint32_t xmt_data_dma_reg[16];
	206	uint32_t rcvt0_data_dma_reg[32];
	207	uint32_t rcvt1_data_dma_reg[32];
	208	uint32_t risc_gp_reg[128];
6d9b61ed AV	209	uint32_t lmc_reg[112];
	210	uint32_t fpm_hdw_reg[192];
	211	uint32_t fb_hdw_reg[176];
	212	uint32_t code_ram[0x2000];
	213	uint32_t ext_mem[1];
	214	};
a7a167bf AV	215
	216	#define EFT_NUM_BUFFERS 4
	217	#define EFT_BYTES_PER_BUFFER 0x4000
	218	#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
	219
	220	struct qla2xxx_fw_dump {
	221	uint8_t signature[4];
	222	uint32_t version;
	223
	224	uint32_t fw_major_version;
	225	uint32_t fw_minor_version;
	226	uint32_t fw_subminor_version;
	227	uint32_t fw_attributes;
	228
	229	uint32_t vendor;
	230	uint32_t device;
	231	uint32_t subsystem_vendor;
	232	uint32_t subsystem_device;
	233
	234	uint32_t fixed_size;
	235	uint32_t mem_size;
	236	uint32_t req_q_size;
	237	uint32_t rsp_q_size;
	238
	239	uint32_t eft_size;
	240	uint32_t eft_addr_l;
	241	uint32_t eft_addr_h;
	242
	243	uint32_t header_size;
	244
	245	union {
	246	struct qla2100_fw_dump isp21;
	247	struct qla2300_fw_dump isp23;
	248	struct qla24xx_fw_dump isp24;
	249	} isp;
	250	};