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6e98016c GM |
1 | /* |
2 | * QLogic Fibre Channel HBA Driver | |
bd21eaf9 | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
6e98016c GM |
4 | * |
5 | * See LICENSE.qla2xxx for copyright and licensing details. | |
6 | */ | |
7 | #ifndef __QLA_BSG_H | |
8 | #define __QLA_BSG_H | |
9 | ||
10 | /* BSG Vendor specific commands */ | |
11 | #define QL_VND_LOOPBACK 0x01 | |
12 | #define QL_VND_A84_RESET 0x02 | |
13 | #define QL_VND_A84_UPDATE_FW 0x03 | |
14 | #define QL_VND_A84_MGMT_CMD 0x04 | |
15 | #define QL_VND_IIDMA 0x05 | |
16 | #define QL_VND_FCP_PRIO_CFG_CMD 0x06 | |
f19af163 HZ |
17 | #define QL_VND_READ_FLASH 0x07 |
18 | #define QL_VND_UPDATE_FLASH 0x08 | |
697a4bc6 JC |
19 | #define QL_VND_SET_FRU_VERSION 0x0B |
20 | #define QL_VND_READ_FRU_STATUS 0x0C | |
21 | #define QL_VND_WRITE_FRU_STATUS 0x0D | |
a9b6f722 | 22 | #define QL_VND_DIAG_IO_CMD 0x0A |
9ebb5d9c JC |
23 | #define QL_VND_WRITE_I2C 0x10 |
24 | #define QL_VND_READ_I2C 0x11 | |
8ae6d9c7 | 25 | #define QL_VND_FX00_MGMT_CMD 0x12 |
db64e930 | 26 | #define QL_VND_SERDES_OP 0x13 |
e8887c51 | 27 | #define QL_VND_SERDES_OP_EX 0x14 |
4243c115 SC |
28 | #define QL_VND_GET_FLASH_UPDATE_CAPS 0x15 |
29 | #define QL_VND_SET_FLASH_UPDATE_CAPS 0x16 | |
969a6199 | 30 | #define QL_VND_GET_BBCR_DATA 0x17 |
243de676 | 31 | #define QL_VND_GET_PRIV_STATS 0x18 |
ec891462 | 32 | #define QL_VND_DPORT_DIAGNOSTICS 0x19 |
8437dda0 | 33 | #define QL_VND_GET_PRIV_STATS_EX 0x1A |
697a4bc6 JC |
34 | |
35 | /* BSG Vendor specific subcode returns */ | |
36 | #define EXT_STATUS_OK 0 | |
37 | #define EXT_STATUS_ERR 1 | |
a9b6f722 | 38 | #define EXT_STATUS_BUSY 2 |
697a4bc6 | 39 | #define EXT_STATUS_INVALID_PARAM 6 |
a9b6f722 SK |
40 | #define EXT_STATUS_DATA_OVERRUN 7 |
41 | #define EXT_STATUS_DATA_UNDERRUN 8 | |
697a4bc6 JC |
42 | #define EXT_STATUS_MAILBOX 11 |
43 | #define EXT_STATUS_NO_MEMORY 17 | |
a9b6f722 SK |
44 | #define EXT_STATUS_DEVICE_OFFLINE 22 |
45 | ||
46 | /* | |
47 | * To support bidirectional iocb | |
48 | * BSG Vendor specific returns | |
49 | */ | |
50 | #define EXT_STATUS_NOT_SUPPORTED 27 | |
51 | #define EXT_STATUS_INVALID_CFG 28 | |
52 | #define EXT_STATUS_DMA_ERR 29 | |
53 | #define EXT_STATUS_TIMEOUT 30 | |
54 | #define EXT_STATUS_THREAD_FAILED 31 | |
55 | #define EXT_STATUS_DATA_CMP_FAILED 32 | |
6e98016c GM |
56 | |
57 | /* BSG definations for interpreting CommandSent field */ | |
58 | #define INT_DEF_LB_LOOPBACK_CMD 0 | |
59 | #define INT_DEF_LB_ECHO_CMD 1 | |
60 | ||
23f2ebd1 | 61 | /* Loopback related definations */ |
8fcd6b8b | 62 | #define INTERNAL_LOOPBACK 0xF1 |
23f2ebd1 SR |
63 | #define EXTERNAL_LOOPBACK 0xF2 |
64 | #define ENABLE_INTERNAL_LOOPBACK 0x02 | |
8fcd6b8b | 65 | #define ENABLE_EXTERNAL_LOOPBACK 0x04 |
23f2ebd1 SR |
66 | #define INTERNAL_LOOPBACK_MASK 0x000E |
67 | #define MAX_ELS_FRAME_PAYLOAD 252 | |
68 | #define ELS_OPCODE_BYTE 0x10 | |
69 | ||
6e98016c GM |
70 | /* BSG Vendor specific definations */ |
71 | #define A84_ISSUE_WRITE_TYPE_CMD 0 | |
72 | #define A84_ISSUE_READ_TYPE_CMD 1 | |
73 | #define A84_CLEANUP_CMD 2 | |
74 | #define A84_ISSUE_RESET_OP_FW 3 | |
75 | #define A84_ISSUE_RESET_DIAG_FW 4 | |
76 | #define A84_ISSUE_UPDATE_OPFW_CMD 5 | |
77 | #define A84_ISSUE_UPDATE_DIAGFW_CMD 6 | |
78 | ||
79 | struct qla84_mgmt_param { | |
80 | union { | |
81 | struct { | |
82 | uint32_t start_addr; | |
83 | } mem; /* for QLA84_MGMT_READ/WRITE_MEM */ | |
84 | struct { | |
85 | uint32_t id; | |
86 | #define QLA84_MGMT_CONFIG_ID_UIF 1 | |
87 | #define QLA84_MGMT_CONFIG_ID_FCOE_COS 2 | |
88 | #define QLA84_MGMT_CONFIG_ID_PAUSE 3 | |
89 | #define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4 | |
90 | ||
91 | uint32_t param0; | |
92 | uint32_t param1; | |
93 | } config; /* for QLA84_MGMT_CHNG_CONFIG */ | |
94 | ||
95 | struct { | |
96 | uint32_t type; | |
97 | #define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */ | |
98 | #define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */ | |
99 | #define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */ | |
100 | #define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */ | |
101 | #define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */ | |
102 | #define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */ | |
103 | #define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */ | |
104 | ||
105 | uint32_t context; | |
106 | /* | |
107 | * context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA | |
108 | */ | |
109 | #define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0 | |
110 | #define IC_LOG_DATA_LOG_ID_LEARN_LOG 1 | |
111 | #define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2 | |
112 | #define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3 | |
113 | #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4 | |
114 | #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5 | |
115 | #define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6 | |
116 | #define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7 | |
117 | #define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8 | |
118 | #define IC_LOG_DATA_LOG_ID_DCX_LOG 9 | |
119 | ||
120 | /* | |
121 | * context definitions for QLA84_MGMT_INFO_PORT_STAT | |
122 | */ | |
123 | #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0 | |
124 | #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1 | |
125 | #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2 | |
126 | #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3 | |
127 | #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4 | |
128 | #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5 | |
129 | ||
130 | ||
131 | /* | |
132 | * context definitions for QLA84_MGMT_INFO_LIF_STAT | |
133 | */ | |
134 | #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0 | |
135 | #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1 | |
136 | #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2 | |
137 | #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3 | |
138 | #define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6 | |
139 | ||
140 | } info; /* for QLA84_MGMT_GET_INFO */ | |
141 | } u; | |
142 | }; | |
143 | ||
144 | struct qla84_msg_mgmt { | |
145 | uint16_t cmd; | |
146 | #define QLA84_MGMT_READ_MEM 0x00 | |
147 | #define QLA84_MGMT_WRITE_MEM 0x01 | |
148 | #define QLA84_MGMT_CHNG_CONFIG 0x02 | |
149 | #define QLA84_MGMT_GET_INFO 0x03 | |
150 | uint16_t rsrvd; | |
151 | struct qla84_mgmt_param mgmtp;/* parameters for cmd */ | |
152 | uint32_t len; /* bytes in payload following this struct */ | |
153 | uint8_t payload[0]; /* payload for cmd */ | |
154 | }; | |
155 | ||
156 | struct qla_bsg_a84_mgmt { | |
157 | struct qla84_msg_mgmt mgmt; | |
158 | } __attribute__ ((packed)); | |
159 | ||
160 | struct qla_scsi_addr { | |
161 | uint16_t bus; | |
162 | uint16_t target; | |
163 | } __attribute__ ((packed)); | |
164 | ||
165 | struct qla_ext_dest_addr { | |
166 | union { | |
167 | uint8_t wwnn[8]; | |
168 | uint8_t wwpn[8]; | |
169 | uint8_t id[4]; | |
170 | struct qla_scsi_addr scsi_addr; | |
171 | } dest_addr; | |
172 | uint16_t dest_type; | |
173 | #define EXT_DEF_TYPE_WWPN 2 | |
174 | uint16_t lun; | |
175 | uint16_t padding[2]; | |
176 | } __attribute__ ((packed)); | |
177 | ||
178 | struct qla_port_param { | |
179 | struct qla_ext_dest_addr fc_scsi_addr; | |
180 | uint16_t mode; | |
181 | uint16_t speed; | |
182 | } __attribute__ ((packed)); | |
697a4bc6 JC |
183 | |
184 | ||
185 | /* FRU VPD */ | |
186 | ||
187 | #define MAX_FRU_SIZE 36 | |
188 | ||
189 | struct qla_field_address { | |
190 | uint16_t offset; | |
191 | uint16_t device; | |
192 | uint16_t option; | |
193 | } __packed; | |
194 | ||
195 | struct qla_field_info { | |
196 | uint8_t version[MAX_FRU_SIZE]; | |
197 | } __packed; | |
198 | ||
199 | struct qla_image_version { | |
200 | struct qla_field_address field_address; | |
201 | struct qla_field_info field_info; | |
202 | } __packed; | |
203 | ||
204 | struct qla_image_version_list { | |
205 | uint32_t count; | |
206 | struct qla_image_version version[0]; | |
207 | } __packed; | |
208 | ||
209 | struct qla_status_reg { | |
210 | struct qla_field_address field_address; | |
211 | uint8_t status_reg; | |
212 | uint8_t reserved[7]; | |
213 | } __packed; | |
214 | ||
9ebb5d9c JC |
215 | struct qla_i2c_access { |
216 | uint16_t device; | |
217 | uint16_t offset; | |
218 | uint16_t option; | |
219 | uint16_t length; | |
220 | uint8_t buffer[0x40]; | |
221 | } __packed; | |
222 | ||
db64e930 JC |
223 | /* 26xx serdes register interface */ |
224 | ||
225 | /* serdes reg commands */ | |
226 | #define INT_SC_SERDES_READ_REG 1 | |
227 | #define INT_SC_SERDES_WRITE_REG 2 | |
228 | ||
229 | struct qla_serdes_reg { | |
230 | uint16_t cmd; | |
231 | uint16_t addr; | |
232 | uint16_t val; | |
233 | } __packed; | |
234 | ||
e8887c51 JC |
235 | struct qla_serdes_reg_ex { |
236 | uint16_t cmd; | |
237 | uint32_t addr; | |
238 | uint32_t val; | |
239 | } __packed; | |
240 | ||
4243c115 SC |
241 | struct qla_flash_update_caps { |
242 | uint64_t capabilities; | |
243 | uint32_t outage_duration; | |
244 | uint8_t reserved[20]; | |
245 | } __packed; | |
969a6199 SC |
246 | |
247 | /* BB_CR Status */ | |
248 | #define QLA_BBCR_STATUS_DISABLED 0 | |
249 | #define QLA_BBCR_STATUS_ENABLED 1 | |
c73191b8 | 250 | #define QLA_BBCR_STATUS_UNKNOWN 2 |
969a6199 SC |
251 | |
252 | /* BB_CR State */ | |
253 | #define QLA_BBCR_STATE_OFFLINE 0 | |
254 | #define QLA_BBCR_STATE_ONLINE 1 | |
255 | ||
256 | /* BB_CR Offline Reason Code */ | |
257 | #define QLA_BBCR_REASON_PORT_SPEED 1 | |
258 | #define QLA_BBCR_REASON_PEER_PORT 2 | |
259 | #define QLA_BBCR_REASON_SWITCH 3 | |
260 | #define QLA_BBCR_REASON_LOGIN_REJECT 4 | |
261 | ||
262 | struct qla_bbcr_data { | |
263 | uint8_t status; /* 1 - enabled, 0 - Disabled */ | |
264 | uint8_t state; /* 1 - online, 0 - offline */ | |
265 | uint8_t configured_bbscn; /* 0-15 */ | |
266 | uint8_t negotiated_bbscn; /* 0-15 */ | |
267 | uint8_t offline_reason_code; | |
c73191b8 HZ |
268 | uint16_t mbx1; /* Port state */ |
269 | uint8_t reserved[9]; | |
969a6199 | 270 | } __packed; |
ec891462 JC |
271 | |
272 | struct qla_dport_diag { | |
273 | uint16_t options; | |
274 | uint32_t buf[16]; | |
275 | uint8_t unused[62]; | |
276 | } __packed; | |
277 | ||
278 | /* D_Port options */ | |
279 | #define QLA_DPORT_RESULT 0x0 | |
280 | #define QLA_DPORT_START 0x2 | |
281 | ||
6e98016c | 282 | #endif |