Commit | Line | Data |
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dd4969a8 | 1 | /* |
20b09c29 AY |
2 | * Marvell 88SE64xx/88SE94xx pci init |
3 | * | |
4 | * Copyright 2007 Red Hat, Inc. | |
5 | * Copyright 2008 Marvell. <kewei@marvell.com> | |
0b15fb1f | 6 | * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> |
20b09c29 AY |
7 | * |
8 | * This file is licensed under GPLv2. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; version 2 of the | |
13 | * License. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
23 | * USA | |
24 | */ | |
dd4969a8 | 25 | |
dd4969a8 JG |
26 | |
27 | #include "mv_sas.h" | |
dd4969a8 | 28 | |
0b15fb1f XY |
29 | static int lldd_max_execute_num = 1; |
30 | module_param_named(collector, lldd_max_execute_num, int, S_IRUGO); | |
31 | MODULE_PARM_DESC(collector, "\n" | |
32 | "\tIf greater than one, tells the SAS Layer to run in Task Collector\n" | |
33 | "\tMode. If 1 or 0, tells the SAS Layer to run in Direct Mode.\n" | |
34 | "\tThe mvsas SAS LLDD supports both modes.\n" | |
35 | "\tDefault: 1 (Direct Mode).\n"); | |
36 | ||
83c7b61c XY |
37 | int interrupt_coalescing = 0x80; |
38 | ||
dd4969a8 | 39 | static struct scsi_transport_template *mvs_stt; |
0b15fb1f | 40 | struct kmem_cache *mvs_task_list_cache; |
dd4969a8 | 41 | static const struct mvs_chip_info mvs_chips[] = { |
a4632aae XY |
42 | [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, |
43 | [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, | |
44 | [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, }, | |
45 | [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, | |
46 | [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, | |
47 | [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, | |
48 | [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, }, | |
49 | [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, }, | |
50 | [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, }, | |
dd4969a8 JG |
51 | }; |
52 | ||
83c7b61c XY |
53 | struct device_attribute *mvst_host_attrs[]; |
54 | ||
20b09c29 AY |
55 | #define SOC_SAS_NUM 2 |
56 | ||
dd4969a8 JG |
57 | static struct scsi_host_template mvs_sht = { |
58 | .module = THIS_MODULE, | |
59 | .name = DRV_NAME, | |
60 | .queuecommand = sas_queuecommand, | |
61 | .target_alloc = sas_target_alloc, | |
62 | .slave_configure = mvs_slave_configure, | |
63 | .slave_destroy = sas_slave_destroy, | |
64 | .scan_finished = mvs_scan_finished, | |
65 | .scan_start = mvs_scan_start, | |
66 | .change_queue_depth = sas_change_queue_depth, | |
67 | .change_queue_type = sas_change_queue_type, | |
68 | .bios_param = sas_bios_param, | |
69 | .can_queue = 1, | |
70 | .cmd_per_lun = 1, | |
71 | .this_id = -1, | |
b89e8f53 | 72 | .sg_tablesize = SG_ALL, |
dd4969a8 JG |
73 | .max_sectors = SCSI_DEFAULT_MAX_SECTORS, |
74 | .use_clustering = ENABLE_CLUSTERING, | |
9dc9fd94 | 75 | .eh_device_reset_handler = sas_eh_device_reset_handler, |
dd4969a8 | 76 | .eh_bus_reset_handler = sas_eh_bus_reset_handler, |
20b09c29 | 77 | .slave_alloc = mvs_slave_alloc, |
dd4969a8 JG |
78 | .target_destroy = sas_target_destroy, |
79 | .ioctl = sas_ioctl, | |
83c7b61c | 80 | .shost_attrs = mvst_host_attrs, |
dd4969a8 JG |
81 | }; |
82 | ||
83 | static struct sas_domain_function_template mvs_transport_ops = { | |
20b09c29 | 84 | .lldd_dev_found = mvs_dev_found, |
9dc9fd94 | 85 | .lldd_dev_gone = mvs_dev_gone, |
20b09c29 | 86 | .lldd_execute_task = mvs_queue_command, |
dd4969a8 | 87 | .lldd_control_phy = mvs_phy_control, |
20b09c29 AY |
88 | |
89 | .lldd_abort_task = mvs_abort_task, | |
90 | .lldd_abort_task_set = mvs_abort_task_set, | |
91 | .lldd_clear_aca = mvs_clear_aca, | |
9dc9fd94 | 92 | .lldd_clear_task_set = mvs_clear_task_set, |
dd4969a8 | 93 | .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset, |
20b09c29 AY |
94 | .lldd_lu_reset = mvs_lu_reset, |
95 | .lldd_query_task = mvs_query_task, | |
20b09c29 AY |
96 | .lldd_port_formed = mvs_port_formed, |
97 | .lldd_port_deformed = mvs_port_deformed, | |
98 | ||
dd4969a8 JG |
99 | }; |
100 | ||
101 | static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id) | |
102 | { | |
103 | struct mvs_phy *phy = &mvi->phy[phy_id]; | |
104 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
105 | ||
20b09c29 | 106 | phy->mvi = mvi; |
84fbd0ce | 107 | phy->port = NULL; |
20b09c29 | 108 | init_timer(&phy->timer); |
dd4969a8 JG |
109 | sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0; |
110 | sas_phy->class = SAS; | |
111 | sas_phy->iproto = SAS_PROTOCOL_ALL; | |
112 | sas_phy->tproto = 0; | |
113 | sas_phy->type = PHY_TYPE_PHYSICAL; | |
114 | sas_phy->role = PHY_ROLE_INITIATOR; | |
115 | sas_phy->oob_mode = OOB_NOT_CONNECTED; | |
116 | sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; | |
117 | ||
118 | sas_phy->id = phy_id; | |
119 | sas_phy->sas_addr = &mvi->sas_addr[0]; | |
120 | sas_phy->frame_rcvd = &phy->frame_rcvd[0]; | |
20b09c29 | 121 | sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata; |
dd4969a8 JG |
122 | sas_phy->lldd_phy = phy; |
123 | } | |
124 | ||
125 | static void mvs_free(struct mvs_info *mvi) | |
126 | { | |
20b09c29 AY |
127 | struct mvs_wq *mwq; |
128 | int slot_nr; | |
dd4969a8 JG |
129 | |
130 | if (!mvi) | |
131 | return; | |
132 | ||
20b09c29 AY |
133 | if (mvi->flags & MVF_FLAG_SOC) |
134 | slot_nr = MVS_SOC_SLOTS; | |
135 | else | |
b89e8f53 | 136 | slot_nr = MVS_CHIP_SLOT_SZ; |
dd4969a8 | 137 | |
0b15fb1f XY |
138 | if (mvi->dma_pool) |
139 | pci_pool_destroy(mvi->dma_pool); | |
dd4969a8 JG |
140 | |
141 | if (mvi->tx) | |
20b09c29 | 142 | dma_free_coherent(mvi->dev, |
dd4969a8 JG |
143 | sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, |
144 | mvi->tx, mvi->tx_dma); | |
145 | if (mvi->rx_fis) | |
20b09c29 | 146 | dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ, |
dd4969a8 JG |
147 | mvi->rx_fis, mvi->rx_fis_dma); |
148 | if (mvi->rx) | |
20b09c29 | 149 | dma_free_coherent(mvi->dev, |
dd4969a8 JG |
150 | sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), |
151 | mvi->rx, mvi->rx_dma); | |
152 | if (mvi->slot) | |
20b09c29 AY |
153 | dma_free_coherent(mvi->dev, |
154 | sizeof(*mvi->slot) * slot_nr, | |
dd4969a8 | 155 | mvi->slot, mvi->slot_dma); |
8882f081 | 156 | |
20b09c29 AY |
157 | if (mvi->bulk_buffer) |
158 | dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, | |
159 | mvi->bulk_buffer, mvi->bulk_buffer_dma); | |
8882f081 XY |
160 | if (mvi->bulk_buffer1) |
161 | dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE, | |
162 | mvi->bulk_buffer1, mvi->bulk_buffer_dma1); | |
20b09c29 AY |
163 | |
164 | MVS_CHIP_DISP->chip_iounmap(mvi); | |
dd4969a8 JG |
165 | if (mvi->shost) |
166 | scsi_host_put(mvi->shost); | |
20b09c29 AY |
167 | list_for_each_entry(mwq, &mvi->wq_list, entry) |
168 | cancel_delayed_work(&mwq->work_q); | |
b89e8f53 | 169 | kfree(mvi->tags); |
dd4969a8 JG |
170 | kfree(mvi); |
171 | } | |
172 | ||
6f8ac161 | 173 | #ifdef CONFIG_SCSI_MVSAS_TASKLET |
20b09c29 | 174 | static void mvs_tasklet(unsigned long opaque) |
dd4969a8 | 175 | { |
20b09c29 AY |
176 | u32 stat; |
177 | u16 core_nr, i = 0; | |
dd4969a8 | 178 | |
20b09c29 AY |
179 | struct mvs_info *mvi; |
180 | struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque; | |
181 | ||
182 | core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; | |
183 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; | |
184 | ||
185 | if (unlikely(!mvi)) | |
186 | BUG_ON(1); | |
187 | ||
6f8ac161 XY |
188 | stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq); |
189 | if (!stat) | |
190 | goto out; | |
191 | ||
20b09c29 AY |
192 | for (i = 0; i < core_nr; i++) { |
193 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; | |
6f8ac161 | 194 | MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat); |
20b09c29 | 195 | } |
6f8ac161 XY |
196 | out: |
197 | MVS_CHIP_DISP->interrupt_enable(mvi); | |
dd4969a8 | 198 | |
dd4969a8 JG |
199 | } |
200 | #endif | |
201 | ||
202 | static irqreturn_t mvs_interrupt(int irq, void *opaque) | |
203 | { | |
6f8ac161 | 204 | u32 core_nr; |
dd4969a8 | 205 | u32 stat; |
20b09c29 AY |
206 | struct mvs_info *mvi; |
207 | struct sas_ha_struct *sha = opaque; | |
6f8ac161 XY |
208 | #ifndef CONFIG_SCSI_MVSAS_TASKLET |
209 | u32 i; | |
210 | #endif | |
dd4969a8 | 211 | |
20b09c29 AY |
212 | core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; |
213 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; | |
dd4969a8 | 214 | |
20b09c29 | 215 | if (unlikely(!mvi)) |
dd4969a8 | 216 | return IRQ_NONE; |
6f8ac161 XY |
217 | #ifdef CONFIG_SCSI_MVSAS_TASKLET |
218 | MVS_CHIP_DISP->interrupt_disable(mvi); | |
219 | #endif | |
dd4969a8 | 220 | |
20b09c29 | 221 | stat = MVS_CHIP_DISP->isr_status(mvi, irq); |
6f8ac161 XY |
222 | if (!stat) { |
223 | #ifdef CONFIG_SCSI_MVSAS_TASKLET | |
224 | MVS_CHIP_DISP->interrupt_enable(mvi); | |
225 | #endif | |
20b09c29 | 226 | return IRQ_NONE; |
6f8ac161 | 227 | } |
dd4969a8 | 228 | |
6f8ac161 XY |
229 | #ifdef CONFIG_SCSI_MVSAS_TASKLET |
230 | tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); | |
dd4969a8 | 231 | #else |
20b09c29 AY |
232 | for (i = 0; i < core_nr; i++) { |
233 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; | |
234 | MVS_CHIP_DISP->isr(mvi, irq, stat); | |
235 | } | |
dd4969a8 JG |
236 | #endif |
237 | return IRQ_HANDLED; | |
238 | } | |
239 | ||
20b09c29 | 240 | static int __devinit mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost) |
dd4969a8 | 241 | { |
9dc9fd94 | 242 | int i = 0, slot_nr; |
0b15fb1f | 243 | char pool_name[32]; |
dd4969a8 | 244 | |
20b09c29 AY |
245 | if (mvi->flags & MVF_FLAG_SOC) |
246 | slot_nr = MVS_SOC_SLOTS; | |
247 | else | |
b89e8f53 | 248 | slot_nr = MVS_CHIP_SLOT_SZ; |
dd4969a8 JG |
249 | |
250 | spin_lock_init(&mvi->lock); | |
20b09c29 | 251 | for (i = 0; i < mvi->chip->n_phy; i++) { |
dd4969a8 | 252 | mvs_phy_init(mvi, i); |
dd4969a8 JG |
253 | mvi->port[i].wide_port_phymap = 0; |
254 | mvi->port[i].port_attached = 0; | |
255 | INIT_LIST_HEAD(&mvi->port[i].list); | |
256 | } | |
20b09c29 AY |
257 | for (i = 0; i < MVS_MAX_DEVICES; i++) { |
258 | mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED; | |
259 | mvi->devices[i].dev_type = NO_DEVICE; | |
260 | mvi->devices[i].device_id = i; | |
261 | mvi->devices[i].dev_status = MVS_DEV_NORMAL; | |
9dc9fd94 | 262 | init_timer(&mvi->devices[i].timer); |
20b09c29 | 263 | } |
dd4969a8 JG |
264 | |
265 | /* | |
266 | * alloc and init our DMA areas | |
267 | */ | |
20b09c29 | 268 | mvi->tx = dma_alloc_coherent(mvi->dev, |
dd4969a8 JG |
269 | sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ, |
270 | &mvi->tx_dma, GFP_KERNEL); | |
271 | if (!mvi->tx) | |
272 | goto err_out; | |
273 | memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ); | |
20b09c29 | 274 | mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ, |
dd4969a8 JG |
275 | &mvi->rx_fis_dma, GFP_KERNEL); |
276 | if (!mvi->rx_fis) | |
277 | goto err_out; | |
278 | memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ); | |
279 | ||
20b09c29 | 280 | mvi->rx = dma_alloc_coherent(mvi->dev, |
dd4969a8 JG |
281 | sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1), |
282 | &mvi->rx_dma, GFP_KERNEL); | |
283 | if (!mvi->rx) | |
284 | goto err_out; | |
285 | memset(mvi->rx, 0, sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1)); | |
dd4969a8 JG |
286 | mvi->rx[0] = cpu_to_le32(0xfff); |
287 | mvi->rx_cons = 0xfff; | |
288 | ||
20b09c29 AY |
289 | mvi->slot = dma_alloc_coherent(mvi->dev, |
290 | sizeof(*mvi->slot) * slot_nr, | |
dd4969a8 JG |
291 | &mvi->slot_dma, GFP_KERNEL); |
292 | if (!mvi->slot) | |
293 | goto err_out; | |
20b09c29 | 294 | memset(mvi->slot, 0, sizeof(*mvi->slot) * slot_nr); |
dd4969a8 | 295 | |
20b09c29 AY |
296 | mvi->bulk_buffer = dma_alloc_coherent(mvi->dev, |
297 | TRASH_BUCKET_SIZE, | |
298 | &mvi->bulk_buffer_dma, GFP_KERNEL); | |
299 | if (!mvi->bulk_buffer) | |
300 | goto err_out; | |
8882f081 XY |
301 | |
302 | mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev, | |
303 | TRASH_BUCKET_SIZE, | |
304 | &mvi->bulk_buffer_dma1, GFP_KERNEL); | |
305 | if (!mvi->bulk_buffer1) | |
306 | goto err_out; | |
307 | ||
0b15fb1f XY |
308 | sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id); |
309 | mvi->dma_pool = pci_pool_create(pool_name, mvi->pdev, MVS_SLOT_BUF_SZ, 16, 0); | |
310 | if (!mvi->dma_pool) { | |
311 | printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name); | |
dd4969a8 | 312 | goto err_out; |
dd4969a8 | 313 | } |
0b15fb1f XY |
314 | mvi->tags_num = slot_nr; |
315 | ||
20b09c29 AY |
316 | /* Initialize tags */ |
317 | mvs_tag_init(mvi); | |
318 | return 0; | |
319 | err_out: | |
320 | return 1; | |
321 | } | |
322 | ||
dd4969a8 | 323 | |
20b09c29 AY |
324 | int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex) |
325 | { | |
326 | unsigned long res_start, res_len, res_flag, res_flag_ex = 0; | |
327 | struct pci_dev *pdev = mvi->pdev; | |
328 | if (bar_ex != -1) { | |
329 | /* | |
330 | * ioremap main and peripheral registers | |
331 | */ | |
332 | res_start = pci_resource_start(pdev, bar_ex); | |
333 | res_len = pci_resource_len(pdev, bar_ex); | |
334 | if (!res_start || !res_len) | |
335 | goto err_out; | |
336 | ||
337 | res_flag_ex = pci_resource_flags(pdev, bar_ex); | |
338 | if (res_flag_ex & IORESOURCE_MEM) { | |
339 | if (res_flag_ex & IORESOURCE_CACHEABLE) | |
340 | mvi->regs_ex = ioremap(res_start, res_len); | |
341 | else | |
342 | mvi->regs_ex = ioremap_nocache(res_start, | |
343 | res_len); | |
344 | } else | |
345 | mvi->regs_ex = (void *)res_start; | |
346 | if (!mvi->regs_ex) | |
347 | goto err_out; | |
348 | } | |
349 | ||
350 | res_start = pci_resource_start(pdev, bar); | |
351 | res_len = pci_resource_len(pdev, bar); | |
352 | if (!res_start || !res_len) | |
353 | goto err_out; | |
354 | ||
355 | res_flag = pci_resource_flags(pdev, bar); | |
356 | if (res_flag & IORESOURCE_CACHEABLE) | |
357 | mvi->regs = ioremap(res_start, res_len); | |
358 | else | |
359 | mvi->regs = ioremap_nocache(res_start, res_len); | |
360 | ||
361 | if (!mvi->regs) { | |
362 | if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM)) | |
363 | iounmap(mvi->regs_ex); | |
364 | mvi->regs_ex = NULL; | |
dd4969a8 | 365 | goto err_out; |
20b09c29 AY |
366 | } |
367 | ||
368 | return 0; | |
369 | err_out: | |
370 | return -1; | |
371 | } | |
372 | ||
373 | void mvs_iounmap(void __iomem *regs) | |
374 | { | |
375 | iounmap(regs); | |
376 | } | |
377 | ||
378 | static struct mvs_info *__devinit mvs_pci_alloc(struct pci_dev *pdev, | |
379 | const struct pci_device_id *ent, | |
380 | struct Scsi_Host *shost, unsigned int id) | |
381 | { | |
84fbd0ce | 382 | struct mvs_info *mvi = NULL; |
20b09c29 AY |
383 | struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); |
384 | ||
b89e8f53 XY |
385 | mvi = kzalloc(sizeof(*mvi) + |
386 | (1L << mvs_chips[ent->driver_data].slot_width) * | |
387 | sizeof(struct mvs_slot_info), GFP_KERNEL); | |
20b09c29 AY |
388 | if (!mvi) |
389 | return NULL; | |
dd4969a8 | 390 | |
20b09c29 AY |
391 | mvi->pdev = pdev; |
392 | mvi->dev = &pdev->dev; | |
393 | mvi->chip_id = ent->driver_data; | |
394 | mvi->chip = &mvs_chips[mvi->chip_id]; | |
395 | INIT_LIST_HEAD(&mvi->wq_list); | |
20b09c29 AY |
396 | |
397 | ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi; | |
398 | ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy; | |
399 | ||
400 | mvi->id = id; | |
401 | mvi->sas = sha; | |
402 | mvi->shost = shost; | |
20b09c29 | 403 | |
b89e8f53 XY |
404 | mvi->tags = kzalloc(MVS_CHIP_SLOT_SZ>>3, GFP_KERNEL); |
405 | if (!mvi->tags) | |
406 | goto err_out; | |
407 | ||
20b09c29 AY |
408 | if (MVS_CHIP_DISP->chip_ioremap(mvi)) |
409 | goto err_out; | |
410 | if (!mvs_alloc(mvi, shost)) | |
411 | return mvi; | |
dd4969a8 JG |
412 | err_out: |
413 | mvs_free(mvi); | |
414 | return NULL; | |
415 | } | |
416 | ||
dd4969a8 JG |
417 | static int pci_go_64(struct pci_dev *pdev) |
418 | { | |
419 | int rc; | |
420 | ||
421 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { | |
422 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
423 | if (rc) { | |
424 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
425 | if (rc) { | |
426 | dev_printk(KERN_ERR, &pdev->dev, | |
427 | "64-bit DMA enable failed\n"); | |
428 | return rc; | |
429 | } | |
430 | } | |
431 | } else { | |
432 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
433 | if (rc) { | |
434 | dev_printk(KERN_ERR, &pdev->dev, | |
435 | "32-bit DMA enable failed\n"); | |
436 | return rc; | |
437 | } | |
438 | rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
439 | if (rc) { | |
440 | dev_printk(KERN_ERR, &pdev->dev, | |
441 | "32-bit consistent DMA enable failed\n"); | |
442 | return rc; | |
443 | } | |
444 | } | |
445 | ||
446 | return rc; | |
447 | } | |
448 | ||
20b09c29 AY |
449 | static int __devinit mvs_prep_sas_ha_init(struct Scsi_Host *shost, |
450 | const struct mvs_chip_info *chip_info) | |
451 | { | |
452 | int phy_nr, port_nr; unsigned short core_nr; | |
453 | struct asd_sas_phy **arr_phy; | |
454 | struct asd_sas_port **arr_port; | |
455 | struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); | |
456 | ||
457 | core_nr = chip_info->n_host; | |
458 | phy_nr = core_nr * chip_info->n_phy; | |
459 | port_nr = phy_nr; | |
460 | ||
461 | memset(sha, 0x00, sizeof(struct sas_ha_struct)); | |
462 | arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL); | |
463 | arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL); | |
464 | if (!arr_phy || !arr_port) | |
465 | goto exit_free; | |
466 | ||
467 | sha->sas_phy = arr_phy; | |
468 | sha->sas_port = arr_port; | |
9dc9fd94 | 469 | sha->core.shost = shost; |
20b09c29 AY |
470 | |
471 | sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL); | |
472 | if (!sha->lldd_ha) | |
473 | goto exit_free; | |
474 | ||
475 | ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr; | |
476 | ||
477 | shost->transportt = mvs_stt; | |
a4632aae | 478 | shost->max_id = MVS_MAX_DEVICES; |
20b09c29 AY |
479 | shost->max_lun = ~0; |
480 | shost->max_channel = 1; | |
481 | shost->max_cmd_len = 16; | |
482 | ||
483 | return 0; | |
484 | exit_free: | |
485 | kfree(arr_phy); | |
486 | kfree(arr_port); | |
487 | return -1; | |
488 | ||
489 | } | |
490 | ||
491 | static void __devinit mvs_post_sas_ha_init(struct Scsi_Host *shost, | |
492 | const struct mvs_chip_info *chip_info) | |
493 | { | |
494 | int can_queue, i = 0, j = 0; | |
495 | struct mvs_info *mvi = NULL; | |
496 | struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); | |
497 | unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; | |
498 | ||
499 | for (j = 0; j < nr_core; j++) { | |
500 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j]; | |
501 | for (i = 0; i < chip_info->n_phy; i++) { | |
502 | sha->sas_phy[j * chip_info->n_phy + i] = | |
503 | &mvi->phy[i].sas_phy; | |
504 | sha->sas_port[j * chip_info->n_phy + i] = | |
505 | &mvi->port[i].sas_port; | |
506 | } | |
507 | } | |
508 | ||
509 | sha->sas_ha_name = DRV_NAME; | |
510 | sha->dev = mvi->dev; | |
511 | sha->lldd_module = THIS_MODULE; | |
512 | sha->sas_addr = &mvi->sas_addr[0]; | |
513 | ||
514 | sha->num_phys = nr_core * chip_info->n_phy; | |
515 | ||
0b15fb1f | 516 | sha->lldd_max_execute_num = lldd_max_execute_num; |
20b09c29 AY |
517 | |
518 | if (mvi->flags & MVF_FLAG_SOC) | |
519 | can_queue = MVS_SOC_CAN_QUEUE; | |
520 | else | |
b89e8f53 | 521 | can_queue = MVS_CHIP_SLOT_SZ; |
20b09c29 AY |
522 | |
523 | sha->lldd_queue_size = can_queue; | |
a4632aae | 524 | shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG); |
20b09c29 | 525 | shost->can_queue = can_queue; |
b89e8f53 | 526 | mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE; |
20b09c29 AY |
527 | sha->core.shost = mvi->shost; |
528 | } | |
529 | ||
530 | static void mvs_init_sas_add(struct mvs_info *mvi) | |
531 | { | |
532 | u8 i; | |
533 | for (i = 0; i < mvi->chip->n_phy; i++) { | |
534 | mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL; | |
535 | mvi->phy[i].dev_sas_addr = | |
536 | cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr)); | |
537 | } | |
538 | ||
539 | memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE); | |
540 | } | |
541 | ||
dd4969a8 JG |
542 | static int __devinit mvs_pci_init(struct pci_dev *pdev, |
543 | const struct pci_device_id *ent) | |
544 | { | |
20b09c29 | 545 | unsigned int rc, nhost = 0; |
dd4969a8 | 546 | struct mvs_info *mvi; |
6f8ac161 | 547 | struct mvs_prv_info *mpi; |
dd4969a8 | 548 | irq_handler_t irq_handler = mvs_interrupt; |
20b09c29 AY |
549 | struct Scsi_Host *shost = NULL; |
550 | const struct mvs_chip_info *chip; | |
dd4969a8 | 551 | |
20b09c29 AY |
552 | dev_printk(KERN_INFO, &pdev->dev, |
553 | "mvsas: driver version %s\n", DRV_VERSION); | |
dd4969a8 JG |
554 | rc = pci_enable_device(pdev); |
555 | if (rc) | |
20b09c29 | 556 | goto err_out_enable; |
dd4969a8 JG |
557 | |
558 | pci_set_master(pdev); | |
559 | ||
560 | rc = pci_request_regions(pdev, DRV_NAME); | |
561 | if (rc) | |
562 | goto err_out_disable; | |
563 | ||
564 | rc = pci_go_64(pdev); | |
565 | if (rc) | |
566 | goto err_out_regions; | |
567 | ||
20b09c29 AY |
568 | shost = scsi_host_alloc(&mvs_sht, sizeof(void *)); |
569 | if (!shost) { | |
dd4969a8 JG |
570 | rc = -ENOMEM; |
571 | goto err_out_regions; | |
572 | } | |
573 | ||
20b09c29 AY |
574 | chip = &mvs_chips[ent->driver_data]; |
575 | SHOST_TO_SAS_HA(shost) = | |
576 | kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL); | |
577 | if (!SHOST_TO_SAS_HA(shost)) { | |
578 | kfree(shost); | |
579 | rc = -ENOMEM; | |
580 | goto err_out_regions; | |
dd4969a8 | 581 | } |
dd4969a8 | 582 | |
20b09c29 AY |
583 | rc = mvs_prep_sas_ha_init(shost, chip); |
584 | if (rc) { | |
585 | kfree(shost); | |
586 | rc = -ENOMEM; | |
587 | goto err_out_regions; | |
588 | } | |
dd4969a8 | 589 | |
20b09c29 | 590 | pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost)); |
dd4969a8 | 591 | |
20b09c29 AY |
592 | do { |
593 | mvi = mvs_pci_alloc(pdev, ent, shost, nhost); | |
594 | if (!mvi) { | |
595 | rc = -ENOMEM; | |
596 | goto err_out_regions; | |
597 | } | |
598 | ||
f1f82a91 XY |
599 | memset(&mvi->hba_info_param, 0xFF, |
600 | sizeof(struct hba_info_page)); | |
601 | ||
20b09c29 AY |
602 | mvs_init_sas_add(mvi); |
603 | ||
604 | mvi->instance = nhost; | |
605 | rc = MVS_CHIP_DISP->chip_init(mvi); | |
606 | if (rc) { | |
607 | mvs_free(mvi); | |
608 | goto err_out_regions; | |
609 | } | |
610 | nhost++; | |
611 | } while (nhost < chip->n_host); | |
6f8ac161 XY |
612 | mpi = (struct mvs_prv_info *)(SHOST_TO_SAS_HA(shost)->lldd_ha); |
613 | #ifdef CONFIG_SCSI_MVSAS_TASKLET | |
614 | tasklet_init(&(mpi->mv_tasklet), mvs_tasklet, | |
9dc9fd94 S |
615 | (unsigned long)SHOST_TO_SAS_HA(shost)); |
616 | #endif | |
20b09c29 AY |
617 | |
618 | mvs_post_sas_ha_init(shost, chip); | |
619 | ||
620 | rc = scsi_add_host(shost, &pdev->dev); | |
dd4969a8 JG |
621 | if (rc) |
622 | goto err_out_shost; | |
623 | ||
20b09c29 AY |
624 | rc = sas_register_ha(SHOST_TO_SAS_HA(shost)); |
625 | if (rc) | |
626 | goto err_out_shost; | |
627 | rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, | |
628 | DRV_NAME, SHOST_TO_SAS_HA(shost)); | |
629 | if (rc) | |
630 | goto err_not_sas; | |
dd4969a8 | 631 | |
20b09c29 | 632 | MVS_CHIP_DISP->interrupt_enable(mvi); |
dd4969a8 JG |
633 | |
634 | scsi_scan_host(mvi->shost); | |
635 | ||
636 | return 0; | |
637 | ||
20b09c29 AY |
638 | err_not_sas: |
639 | sas_unregister_ha(SHOST_TO_SAS_HA(shost)); | |
dd4969a8 JG |
640 | err_out_shost: |
641 | scsi_remove_host(mvi->shost); | |
dd4969a8 JG |
642 | err_out_regions: |
643 | pci_release_regions(pdev); | |
644 | err_out_disable: | |
645 | pci_disable_device(pdev); | |
20b09c29 | 646 | err_out_enable: |
dd4969a8 JG |
647 | return rc; |
648 | } | |
649 | ||
650 | static void __devexit mvs_pci_remove(struct pci_dev *pdev) | |
651 | { | |
20b09c29 AY |
652 | unsigned short core_nr, i = 0; |
653 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
654 | struct mvs_info *mvi = NULL; | |
dd4969a8 | 655 | |
20b09c29 AY |
656 | core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; |
657 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; | |
dd4969a8 | 658 | |
6f8ac161 XY |
659 | #ifdef CONFIG_SCSI_MVSAS_TASKLET |
660 | tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet); | |
20b09c29 | 661 | #endif |
dd4969a8 | 662 | |
20b09c29 AY |
663 | pci_set_drvdata(pdev, NULL); |
664 | sas_unregister_ha(sha); | |
665 | sas_remove_host(mvi->shost); | |
666 | scsi_remove_host(mvi->shost); | |
667 | ||
668 | MVS_CHIP_DISP->interrupt_disable(mvi); | |
b89e8f53 | 669 | free_irq(mvi->pdev->irq, sha); |
20b09c29 AY |
670 | for (i = 0; i < core_nr; i++) { |
671 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; | |
dd4969a8 | 672 | mvs_free(mvi); |
dd4969a8 | 673 | } |
20b09c29 AY |
674 | kfree(sha->sas_phy); |
675 | kfree(sha->sas_port); | |
676 | kfree(sha); | |
677 | pci_release_regions(pdev); | |
dd4969a8 | 678 | pci_disable_device(pdev); |
20b09c29 | 679 | return; |
dd4969a8 JG |
680 | } |
681 | ||
682 | static struct pci_device_id __devinitdata mvs_pci_table[] = { | |
683 | { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 }, | |
684 | { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 }, | |
685 | { | |
686 | .vendor = PCI_VENDOR_ID_MARVELL, | |
687 | .device = 0x6440, | |
688 | .subvendor = PCI_ANY_ID, | |
689 | .subdevice = 0x6480, | |
690 | .class = 0, | |
691 | .class_mask = 0, | |
20b09c29 | 692 | .driver_data = chip_6485, |
dd4969a8 JG |
693 | }, |
694 | { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 }, | |
20b09c29 AY |
695 | { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 }, |
696 | { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 }, | |
697 | { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 }, | |
f31491dc NC |
698 | { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 }, |
699 | { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 }, | |
7ec4ad01 | 700 | { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 }, |
463b8977 HLT |
701 | { PCI_VDEVICE(TTI, 0x2710), chip_9480 }, |
702 | { PCI_VDEVICE(TTI, 0x2720), chip_9480 }, | |
703 | { PCI_VDEVICE(TTI, 0x2721), chip_9480 }, | |
704 | { PCI_VDEVICE(TTI, 0x2722), chip_9480 }, | |
705 | { PCI_VDEVICE(TTI, 0x2740), chip_9480 }, | |
706 | { PCI_VDEVICE(TTI, 0x2744), chip_9480 }, | |
707 | { PCI_VDEVICE(TTI, 0x2760), chip_9480 }, | |
82140283 XY |
708 | { |
709 | .vendor = 0x1b4b, | |
710 | .device = 0x9445, | |
711 | .subvendor = PCI_ANY_ID, | |
712 | .subdevice = 0x9480, | |
713 | .class = 0, | |
714 | .class_mask = 0, | |
715 | .driver_data = chip_9445, | |
716 | }, | |
717 | { | |
718 | .vendor = 0x1b4b, | |
719 | .device = 0x9485, | |
720 | .subvendor = PCI_ANY_ID, | |
721 | .subdevice = 0x9480, | |
722 | .class = 0, | |
723 | .class_mask = 0, | |
724 | .driver_data = chip_9485, | |
725 | }, | |
dd4969a8 JG |
726 | |
727 | { } /* terminate list */ | |
728 | }; | |
729 | ||
730 | static struct pci_driver mvs_pci_driver = { | |
731 | .name = DRV_NAME, | |
732 | .id_table = mvs_pci_table, | |
733 | .probe = mvs_pci_init, | |
734 | .remove = __devexit_p(mvs_pci_remove), | |
735 | }; | |
736 | ||
83c7b61c XY |
737 | static ssize_t |
738 | mvs_show_driver_version(struct device *cdev, | |
739 | struct device_attribute *attr, char *buffer) | |
740 | { | |
741 | return snprintf(buffer, PAGE_SIZE, "%s\n", DRV_VERSION); | |
742 | } | |
743 | ||
744 | static DEVICE_ATTR(driver_version, | |
745 | S_IRUGO, | |
746 | mvs_show_driver_version, | |
747 | NULL); | |
748 | ||
749 | static ssize_t | |
750 | mvs_store_interrupt_coalescing(struct device *cdev, | |
751 | struct device_attribute *attr, | |
752 | const char *buffer, size_t size) | |
753 | { | |
754 | int val = 0; | |
755 | struct mvs_info *mvi = NULL; | |
756 | struct Scsi_Host *shost = class_to_shost(cdev); | |
757 | struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost); | |
758 | u8 i, core_nr; | |
759 | if (buffer == NULL) | |
760 | return size; | |
761 | ||
762 | if (sscanf(buffer, "%d", &val) != 1) | |
763 | return -EINVAL; | |
764 | ||
765 | if (val >= 0x10000) { | |
766 | mv_dprintk("interrupt coalescing timer %d us is" | |
767 | "too long\n", val); | |
768 | return strlen(buffer); | |
769 | } | |
770 | ||
771 | interrupt_coalescing = val; | |
772 | ||
773 | core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host; | |
774 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0]; | |
775 | ||
776 | if (unlikely(!mvi)) | |
777 | return -EINVAL; | |
778 | ||
779 | for (i = 0; i < core_nr; i++) { | |
780 | mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i]; | |
781 | if (MVS_CHIP_DISP->tune_interrupt) | |
782 | MVS_CHIP_DISP->tune_interrupt(mvi, | |
783 | interrupt_coalescing); | |
784 | } | |
785 | mv_dprintk("set interrupt coalescing time to %d us\n", | |
786 | interrupt_coalescing); | |
787 | return strlen(buffer); | |
788 | } | |
789 | ||
790 | static ssize_t mvs_show_interrupt_coalescing(struct device *cdev, | |
791 | struct device_attribute *attr, char *buffer) | |
792 | { | |
793 | return snprintf(buffer, PAGE_SIZE, "%d\n", interrupt_coalescing); | |
794 | } | |
795 | ||
796 | static DEVICE_ATTR(interrupt_coalescing, | |
797 | S_IRUGO|S_IWUSR, | |
798 | mvs_show_interrupt_coalescing, | |
799 | mvs_store_interrupt_coalescing); | |
800 | ||
20b09c29 AY |
801 | /* task handler */ |
802 | struct task_struct *mvs_th; | |
dd4969a8 JG |
803 | static int __init mvs_init(void) |
804 | { | |
805 | int rc; | |
dd4969a8 JG |
806 | mvs_stt = sas_domain_attach_transport(&mvs_transport_ops); |
807 | if (!mvs_stt) | |
808 | return -ENOMEM; | |
809 | ||
0b15fb1f XY |
810 | mvs_task_list_cache = kmem_cache_create("mvs_task_list", sizeof(struct mvs_task_list), |
811 | 0, SLAB_HWCACHE_ALIGN, NULL); | |
812 | if (!mvs_task_list_cache) { | |
813 | rc = -ENOMEM; | |
814 | mv_printk("%s: mvs_task_list_cache alloc failed! \n", __func__); | |
815 | goto err_out; | |
816 | } | |
817 | ||
dd4969a8 | 818 | rc = pci_register_driver(&mvs_pci_driver); |
20b09c29 | 819 | |
dd4969a8 JG |
820 | if (rc) |
821 | goto err_out; | |
822 | ||
823 | return 0; | |
824 | ||
825 | err_out: | |
826 | sas_release_transport(mvs_stt); | |
827 | return rc; | |
828 | } | |
829 | ||
830 | static void __exit mvs_exit(void) | |
831 | { | |
832 | pci_unregister_driver(&mvs_pci_driver); | |
833 | sas_release_transport(mvs_stt); | |
0b15fb1f | 834 | kmem_cache_destroy(mvs_task_list_cache); |
dd4969a8 JG |
835 | } |
836 | ||
83c7b61c XY |
837 | struct device_attribute *mvst_host_attrs[] = { |
838 | &dev_attr_driver_version, | |
839 | &dev_attr_interrupt_coalescing, | |
840 | NULL, | |
841 | }; | |
842 | ||
dd4969a8 JG |
843 | module_init(mvs_init); |
844 | module_exit(mvs_exit); | |
845 | ||
846 | MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); | |
847 | MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver"); | |
848 | MODULE_VERSION(DRV_VERSION); | |
849 | MODULE_LICENSE("GPL"); | |
20b09c29 | 850 | #ifdef CONFIG_PCI |
dd4969a8 | 851 | MODULE_DEVICE_TABLE(pci, mvs_pci_table); |
20b09c29 | 852 | #endif |