[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / mvsas / mv_chips.h

/*
 * Marvell 88SE64xx/88SE94xx register IO interface
 *
 * Copyright 2007 Red Hat, Inc.
 * Copyright 2008 Marvell. <kewei@marvell.com>
 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
 *
 * This file is licensed under GPLv2.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; version 2 of the
 * License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 * USA
*/


#ifndef _MV_CHIPS_H_
#define _MV_CHIPS_H_

#define mr32(reg)	readl(regs + reg)
#define mw32(reg, val)	writel((val), regs + reg)
#define mw32_f(reg, val)	do {			\
				mw32(reg, val);	\
				mr32(reg);	\
			} while (0)

#define iow32(reg, val) 	outl(val, (unsigned long)(regs + reg))
#define ior32(reg) 		inl((unsigned long)(regs + reg))
#define iow16(reg, val) 	outw((unsigned long)(val, regs + reg))
#define ior16(reg) 		inw((unsigned long)(regs + reg))
#define iow8(reg, val) 		outb((unsigned long)(val, regs + reg))
#define ior8(reg) 		inb((unsigned long)(regs + reg))

static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
{
	void __iomem *regs = mvi->regs;
	mw32(MVS_CMD_ADDR, addr);
	return mr32(MVS_CMD_DATA);
}

static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
{
	void __iomem *regs = mvi->regs;
	mw32(MVS_CMD_ADDR, addr);
	mw32(MVS_CMD_DATA, val);
}

static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
{
	void __iomem *regs = mvi->regs;
	return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
		mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
}

static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
{
	void __iomem *regs = mvi->regs;
	if (port < 4)
		mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
	else
		mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
}

static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
				u32 off2, u32 port)
{
	void __iomem *regs = mvi->regs + off;
	void __iomem *regs2 = mvi->regs + off2;
	return (port < 4) ? readl(regs + port * 8) :
		readl(regs2 + (port - 4) * 8);
}

static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
				u32 port, u32 val)
{
	void __iomem *regs = mvi->regs + off;
	void __iomem *regs2 = mvi->regs + off2;
	if (port < 4)
		writel(val, regs + port * 8);
	else
		writel(val, regs2 + (port - 4) * 8);
}

static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
{
	return mvs_read_port(mvi, MVS_P0_CFG_DATA,
			MVS_P4_CFG_DATA, port);
}

static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
						u32 port, u32 val)
{
	mvs_write_port(mvi, MVS_P0_CFG_DATA,
			MVS_P4_CFG_DATA, port, val);
}

static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
						u32 port, u32 addr)
{
	mvs_write_port(mvi, MVS_P0_CFG_ADDR,
			MVS_P4_CFG_ADDR, port, addr);
	mdelay(10);
}

static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
{
	return mvs_read_port(mvi, MVS_P0_VSR_DATA,
			MVS_P4_VSR_DATA, port);
}

static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
						u32 port, u32 val)
{
	mvs_write_port(mvi, MVS_P0_VSR_DATA,
			MVS_P4_VSR_DATA, port, val);
}

static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
						u32 port, u32 addr)
{
	mvs_write_port(mvi, MVS_P0_VSR_ADDR,
			MVS_P4_VSR_ADDR, port, addr);
	mdelay(10);
}

static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
{
	return mvs_read_port(mvi, MVS_P0_INT_STAT,
			MVS_P4_INT_STAT, port);
}

static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
						u32 port, u32 val)
{
	mvs_write_port(mvi, MVS_P0_INT_STAT,
			MVS_P4_INT_STAT, port, val);
}

static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
{
	return mvs_read_port(mvi, MVS_P0_INT_MASK,
			MVS_P4_INT_MASK, port);

}

static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
						u32 port, u32 val)
{
	mvs_write_port(mvi, MVS_P0_INT_MASK,
			MVS_P4_INT_MASK, port, val);
}

static inline void mvs_phy_hacks(struct mvs_info *mvi)
{
	u32 tmp;

	tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
	tmp &= ~(1 << 9);
	tmp |= (1 << 10);
	mvs_cw32(mvi, CMD_PHY_TIMER, tmp);

	/* enable retry 127 times */
	mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);

	/* extend open frame timeout to max */
	tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
	tmp &= ~0xffff;
	tmp |= 0x3fff;
	mvs_cw32(mvi, CMD_SAS_CTL0, tmp);

	mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);

	/* not to halt for different port op during wideport link change */
	mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
}

static inline void mvs_int_sata(struct mvs_info *mvi)
{
	u32 tmp;
	void __iomem *regs = mvi->regs;
	tmp = mr32(MVS_INT_STAT_SRS_0);
	if (tmp)
		mw32(MVS_INT_STAT_SRS_0, tmp);
	MVS_CHIP_DISP->clear_active_cmds(mvi);
}

static inline void mvs_int_full(struct mvs_info *mvi)
{
	void __iomem *regs = mvi->regs;
	u32 tmp, stat;
	int i;

	stat = mr32(MVS_INT_STAT);
	mvs_int_rx(mvi, false);

	for (i = 0; i < mvi->chip->n_phy; i++) {
		tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
		if (tmp)
			mvs_int_port(mvi, i, tmp);
	}

	if (stat & CINT_NON_SPEC_NCQ_ERROR)
		MVS_CHIP_DISP->non_spec_ncq_error(mvi);

	if (stat & CINT_SRS)
		mvs_int_sata(mvi);

	mw32(MVS_INT_STAT, stat);
}

static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
{
	void __iomem *regs = mvi->regs;
	mw32(MVS_TX_PROD_IDX, tx);
}

static inline u32 mvs_rx_update(struct mvs_info *mvi)
{
	void __iomem *regs = mvi->regs;
	return mr32(MVS_RX_CONS_IDX);
}

static inline u32 mvs_get_prd_size(void)
{
	return sizeof(struct mvs_prd);
}

static inline u32 mvs_get_prd_count(void)
{
	return MAX_SG_ENTRY;
}

static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
{
	u16 link_stat, link_spd;
	const char *spd[] = {
		"UnKnown",
		"2.5",
		"5.0",
	};
	if (mvi->flags & MVF_FLAG_SOC || mvi->id > 0)
		return;

	pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
	link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS;
	if (link_spd >= 3)
		link_spd = 0;
	dev_printk(KERN_INFO, mvi->dev,
		"mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n",
	       (link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS,
	       spd[link_spd]);
}

static inline u32 mvs_hw_max_link_rate(void)
{
	return MAX_LINK_RATE;
}

#endif  /* _MV_CHIPS_H_ */
Commit	Line	Data
20b09c29 AY	1	/*
	2	* Marvell 88SE64xx/88SE94xx register IO interface
	3	*
	4	* Copyright 2007 Red Hat, Inc.
	5	* Copyright 2008 Marvell. <kewei@marvell.com>
0b15fb1f	6	* Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
20b09c29 AY	7	*
	8	* This file is licensed under GPLv2.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; version 2 of the
	13	* License.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	18	* General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
	23	* USA
	24	*/
	25
	26
dd4969a8 JG	27	#ifndef _MV_CHIPS_H_
	28	#define _MV_CHIPS_H_
	29
20b09c29 AY	30	#define mr32(reg) readl(regs + reg)
	31	#define mw32(reg, val) writel((val), regs + reg)
	32	#define mw32_f(reg, val) do { \
	33	mw32(reg, val); \
	34	mr32(reg); \
	35	} while (0)
dd4969a8	36
20b09c29 AY	37	#define iow32(reg, val) outl(val, (unsigned long)(regs + reg))
	38	#define ior32(reg) inl((unsigned long)(regs + reg))
	39	#define iow16(reg, val) outw((unsigned long)(val, regs + reg))
	40	#define ior16(reg) inw((unsigned long)(regs + reg))
	41	#define iow8(reg, val) outb((unsigned long)(val, regs + reg))
	42	#define ior8(reg) inb((unsigned long)(regs + reg))
	43
	44	static inline u32 mvs_cr32(struct mvs_info *mvi, u32 addr)
dd4969a8	45	{
20b09c29 AY	46	void __iomem *regs = mvi->regs;
	47	mw32(MVS_CMD_ADDR, addr);
	48	return mr32(MVS_CMD_DATA);
dd4969a8 JG	49	}
dd4969a8 JG	50
20b09c29	51	static inline void mvs_cw32(struct mvs_info *mvi, u32 addr, u32 val)
dd4969a8	52	{
20b09c29 AY	53	void __iomem *regs = mvi->regs;
	54	mw32(MVS_CMD_ADDR, addr);
	55	mw32(MVS_CMD_DATA, val);
dd4969a8 JG	56	}
	57
	58	static inline u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
	59	{
	60	void __iomem *regs = mvi->regs;
20b09c29 AY	61	return (port < 4) ? mr32(MVS_P0_SER_CTLSTAT + port * 4) :
20b09c29 AY	62	mr32(MVS_P4_SER_CTLSTAT + (port - 4) * 4);
dd4969a8 JG	63	}
	64
	65	static inline void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
	66	{
	67	void __iomem *regs = mvi->regs;
	68	if (port < 4)
20b09c29	69	mw32(MVS_P0_SER_CTLSTAT + port * 4, val);
dd4969a8	70	else
20b09c29	71	mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val);
dd4969a8 JG	72	}
dd4969a8 JG	73
20b09c29 AY	74	static inline u32 mvs_read_port(struct mvs_info *mvi, u32 off,
20b09c29 AY	75	u32 off2, u32 port)
dd4969a8 JG	76	{
	77	void __iomem *regs = mvi->regs + off;
	78	void __iomem *regs2 = mvi->regs + off2;
20b09c29	79	return (port < 4) ? readl(regs + port * 8) :
dd4969a8 JG	80	readl(regs2 + (port - 4) * 8);
	81	}
	82
	83	static inline void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
	84	u32 port, u32 val)
	85	{
	86	void __iomem *regs = mvi->regs + off;
	87	void __iomem *regs2 = mvi->regs + off2;
	88	if (port < 4)
	89	writel(val, regs + port * 8);
	90	else
	91	writel(val, regs2 + (port - 4) * 8);
	92	}
	93
	94	static inline u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
	95	{
	96	return mvs_read_port(mvi, MVS_P0_CFG_DATA,
	97	MVS_P4_CFG_DATA, port);
	98	}
	99
20b09c29 AY	100	static inline void mvs_write_port_cfg_data(struct mvs_info *mvi,
20b09c29 AY	101	u32 port, u32 val)
dd4969a8 JG	102	{
	103	mvs_write_port(mvi, MVS_P0_CFG_DATA,
	104	MVS_P4_CFG_DATA, port, val);
	105	}
	106
20b09c29 AY	107	static inline void mvs_write_port_cfg_addr(struct mvs_info *mvi,
20b09c29 AY	108	u32 port, u32 addr)
dd4969a8 JG	109	{
	110	mvs_write_port(mvi, MVS_P0_CFG_ADDR,
	111	MVS_P4_CFG_ADDR, port, addr);
20b09c29	112	mdelay(10);
dd4969a8 JG	113	}
	114
	115	static inline u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
	116	{
	117	return mvs_read_port(mvi, MVS_P0_VSR_DATA,
	118	MVS_P4_VSR_DATA, port);
	119	}
	120
20b09c29 AY	121	static inline void mvs_write_port_vsr_data(struct mvs_info *mvi,
20b09c29 AY	122	u32 port, u32 val)
dd4969a8 JG	123	{
	124	mvs_write_port(mvi, MVS_P0_VSR_DATA,
	125	MVS_P4_VSR_DATA, port, val);
	126	}
	127
20b09c29 AY	128	static inline void mvs_write_port_vsr_addr(struct mvs_info *mvi,
20b09c29 AY	129	u32 port, u32 addr)
dd4969a8 JG	130	{
	131	mvs_write_port(mvi, MVS_P0_VSR_ADDR,
	132	MVS_P4_VSR_ADDR, port, addr);
20b09c29	133	mdelay(10);
dd4969a8 JG	134	}
	135
	136	static inline u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
	137	{
	138	return mvs_read_port(mvi, MVS_P0_INT_STAT,
	139	MVS_P4_INT_STAT, port);
	140	}
	141
20b09c29 AY	142	static inline void mvs_write_port_irq_stat(struct mvs_info *mvi,
20b09c29 AY	143	u32 port, u32 val)
dd4969a8 JG	144	{
	145	mvs_write_port(mvi, MVS_P0_INT_STAT,
	146	MVS_P4_INT_STAT, port, val);
	147	}
	148
	149	static inline u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
	150	{
	151	return mvs_read_port(mvi, MVS_P0_INT_MASK,
	152	MVS_P4_INT_MASK, port);
20b09c29	153
dd4969a8 JG	154	}
dd4969a8 JG	155
20b09c29 AY	156	static inline void mvs_write_port_irq_mask(struct mvs_info *mvi,
20b09c29 AY	157	u32 port, u32 val)
dd4969a8 JG	158	{
	159	mvs_write_port(mvi, MVS_P0_INT_MASK,
	160	MVS_P4_INT_MASK, port, val);
	161	}
	162
6f039790	163	static inline void mvs_phy_hacks(struct mvs_info *mvi)
20b09c29 AY	164	{
	165	u32 tmp;
	166
20b09c29 AY	167	tmp = mvs_cr32(mvi, CMD_PHY_TIMER);
	168	tmp &= ~(1 << 9);
	169	tmp \|= (1 << 10);
	170	mvs_cw32(mvi, CMD_PHY_TIMER, tmp);
	171
	172	/* enable retry 127 times */
	173	mvs_cw32(mvi, CMD_SAS_CTL1, 0x7f7f);
	174
	175	/* extend open frame timeout to max */
	176	tmp = mvs_cr32(mvi, CMD_SAS_CTL0);
	177	tmp &= ~0xffff;
	178	tmp \|= 0x3fff;
	179	mvs_cw32(mvi, CMD_SAS_CTL0, tmp);
	180
20b09c29 AY	181	mvs_cw32(mvi, CMD_WD_TIMER, 0x7a0000);
	182
	183	/* not to halt for different port op during wideport link change */
	184	mvs_cw32(mvi, CMD_APP_ERR_CONFIG, 0xffefbf7d);
20b09c29 AY	185	}
	186
	187	static inline void mvs_int_sata(struct mvs_info *mvi)
	188	{
	189	u32 tmp;
	190	void __iomem *regs = mvi->regs;
	191	tmp = mr32(MVS_INT_STAT_SRS_0);
	192	if (tmp)
	193	mw32(MVS_INT_STAT_SRS_0, tmp);
	194	MVS_CHIP_DISP->clear_active_cmds(mvi);
	195	}
	196
	197	static inline void mvs_int_full(struct mvs_info *mvi)
	198	{
	199	void __iomem *regs = mvi->regs;
	200	u32 tmp, stat;
	201	int i;
	202
	203	stat = mr32(MVS_INT_STAT);
	204	mvs_int_rx(mvi, false);
	205
	206	for (i = 0; i < mvi->chip->n_phy; i++) {
	207	tmp = (stat >> i) & (CINT_PORT \| CINT_PORT_STOPPED);
	208	if (tmp)
	209	mvs_int_port(mvi, i, tmp);
	210	}
	211
534ff101 XY	212	if (stat & CINT_NON_SPEC_NCQ_ERROR)
	213	MVS_CHIP_DISP->non_spec_ncq_error(mvi);
	214
20b09c29 AY	215	if (stat & CINT_SRS)
	216	mvs_int_sata(mvi);
	217
	218	mw32(MVS_INT_STAT, stat);
	219	}
	220
	221	static inline void mvs_start_delivery(struct mvs_info *mvi, u32 tx)
	222	{
	223	void __iomem *regs = mvi->regs;
	224	mw32(MVS_TX_PROD_IDX, tx);
	225	}
	226
	227	static inline u32 mvs_rx_update(struct mvs_info *mvi)
	228	{
	229	void __iomem *regs = mvi->regs;
	230	return mr32(MVS_RX_CONS_IDX);
	231	}
	232
	233	static inline u32 mvs_get_prd_size(void)
	234	{
	235	return sizeof(struct mvs_prd);
	236	}
	237
	238	static inline u32 mvs_get_prd_count(void)
	239	{
	240	return MAX_SG_ENTRY;
	241	}
	242
	243	static inline void mvs_show_pcie_usage(struct mvs_info *mvi)
	244	{
	245	u16 link_stat, link_spd;
	246	const char *spd[] = {
	247	"UnKnown",
	248	"2.5",
	249	"5.0",
	250	};
	251	if (mvi->flags & MVF_FLAG_SOC \|\| mvi->id > 0)
	252	return;
	253
	254	pci_read_config_word(mvi->pdev, PCR_LINK_STAT, &link_stat);
	255	link_spd = (link_stat & PLS_LINK_SPD) >> PLS_LINK_SPD_OFFS;
	256	if (link_spd >= 3)
	257	link_spd = 0;
	258	dev_printk(KERN_INFO, mvi->dev,
	259	"mvsas: PCI-E x%u, Bandwidth Usage: %s Gbps\n",
	260	(link_stat & PLS_NEG_LINK_WD) >> PLS_NEG_LINK_WD_OFFS,
	261	spd[link_spd]);
	262	}
	263
	264	static inline u32 mvs_hw_max_link_rate(void)
	265	{
	266	return MAX_LINK_RATE;
	267	}
	268
	269	#endif /* _MV_CHIPS_H_ */
	270