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Merge remote-tracking branch 'spi/fix/pxa' into spi-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / lpfc / lpfc.h
CommitLineData
dea3101e
JB		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
d4379acd 4 * Copyright (C) 2004-2012 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e 6 * www.emulex.com *
c44ce173 7 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e
JB		 8 * *
9 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 10 * modify it under the terms of version 2 of the GNU General *
11 * Public License as published by the Free Software Foundation. *
12 * This program is distributed in the hope that it will be useful. *
13 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
14 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
15 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
16 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
17 * TO BE LEGALLY INVALID. See the GNU General Public License for *
18 * more details, a copy of which can be found in the file COPYING *
19 * included with this package. *
dea3101e
JB		 20 *******************************************************************/
21
2e0fef85 22#include <scsi/scsi_host.h>
88a2cfbb
JS		 23
24#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
25#define CONFIG_SCSI_LPFC_DEBUG_FS
26#endif
27
dea3101e
JB		 28struct lpfc_sli2_slim;
29
5402a315
JS		 30#define ELX_MODEL_NAME_SIZE 80
31
3772a991
JS		 32#define LPFC_PCI_DEV_LP 0x1
33#define LPFC_PCI_DEV_OC 0x2
34
35#define LPFC_SLI_REV2 2
36#define LPFC_SLI_REV3 3
37#define LPFC_SLI_REV4 4
38
97eab634 39#define LPFC_MAX_TARGET 4096 /* max number of targets supported */
e17da18e
JS		 40#define LPFC_MAX_DISC_THREADS 64 /* max outstanding discovery els
41 requests */
42#define LPFC_MAX_NS_RETRY 3 /* Number of retry attempts to contact
43 the NameServer before giving up. */
445cf4f4 44#define LPFC_CMD_PER_LUN 3 /* max outstanding cmds per lun */
81301a9b 45#define LPFC_DEFAULT_SG_SEG_CNT 64 /* sg element count per scsi cmnd */
e2aed29f
JS		 46#define LPFC_DEFAULT_MENLO_SG_SEG_CNT 128 /* sg element count per scsi
47 cmnd for menlo needs nearly twice as for firmware
48 downloads using bsg */
96f7077f
JS		 49
50#define LPFC_MIN_SG_SLI4_BUF_SZ 0x800 /* based on LPFC_DEFAULT_SG_SEG_CNT */
51#define LPFC_MAX_SG_SLI4_SEG_CNT_DIF 128 /* sg element count per scsi cmnd */
52#define LPFC_MAX_SG_SEG_CNT_DIF 512 /* sg element count per scsi cmnd */
81301a9b 53#define LPFC_MAX_SG_SEG_CNT 4096 /* sg element count per scsi cmnd */
09294d46
JS		 54#define LPFC_MAX_SGL_SEG_CNT 512 /* SGL element count per scsi cmnd */
55#define LPFC_MAX_BPL_SEG_CNT 4096 /* BPL element count per scsi cmnd */
56
0558056c 57#define LPFC_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
dea3101e 58#define LPFC_IOCB_LIST_CNT 2250 /* list of IOCBs for fast-path usage. */
445cf4f4 59#define LPFC_Q_RAMP_UP_INTERVAL 120 /* lun q_depth ramp up interval */
495a714c 60#define LPFC_VNAME_LEN 100 /* vport symbolic name length */
977b5a0a
JS		 61#define LPFC_TGTQ_INTERVAL 40000 /* Min amount of time between tgt
62 queue depth change in millisecs */
63#define LPFC_TGTQ_RAMPUP_PCENT 5 /* Target queue rampup in percentage */
7dc517df 64#define LPFC_MIN_TGT_QDEPTH 10
977b5a0a 65#define LPFC_MAX_TGT_QDEPTH 0xFFFF
dea3101e 66
ea2151b4
JS		 67#define LPFC_MAX_BUCKET_COUNT 20 /* Maximum no. of buckets for stat data
68 collection. */
92d7f7b0
JS		 69/*
70 * Following time intervals are used of adjusting SCSI device
71 * queue depths when there are driver resource error or Firmware
72 * resource error.
73 */
256ec0d0
JS		 74/* 1 Second */
75#define QUEUE_RAMP_DOWN_INTERVAL (msecs_to_jiffies(1000 * 1))
76/* 5 minutes */
77#define QUEUE_RAMP_UP_INTERVAL (msecs_to_jiffies(1000 * 300))
92d7f7b0
JS		 78
79/* Number of exchanges reserved for discovery to complete */
80#define LPFC_DISC_IOCB_BUFF_COUNT 20
81
858c9f6c 82#define LPFC_HB_MBOX_INTERVAL 5 /* Heart beat interval in seconds. */
311464ec 83#define LPFC_HB_MBOX_TIMEOUT 30 /* Heart beat timeout in seconds. */
858c9f6c 84
ba20c853
JS		 85#define LPFC_LOOK_AHEAD_OFF 0 /* Look ahead logic is turned off */
86
9399627f
JS		 87/* Error Attention event polling interval */
88#define LPFC_ERATT_POLL_INTERVAL 5 /* EATT poll interval in seconds */
89
dea3101e
JB		 90/* Define macros for 64 bit support */
91#define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))
92#define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))
93#define getPaddr(high, low) ((dma_addr_t)( \
94 (( (u64)(high)<<16 ) << 16)|( (u64)(low))))
95/* Provide maximum configuration definitions. */
96#define LPFC_DRVR_TIMEOUT 16 /* driver iocb timeout value in sec */
dea3101e
JB		 97#define FC_MAX_ADPTMSG 64
98
99#define MAX_HBAEVT 32
100
9399627f
JS		 101/* Number of MSI-X vectors the driver uses */
102#define LPFC_MSIX_VECTORS 2
103
5e9d9b82
JS		 104/* lpfc wait event data ready flag */
105#define LPFC_DATA_READY (1<<0)
106
809c7536
JS		 107/* queue dump line buffer size */
108#define LPFC_LBUF_SZ 128
109
618a5230
JS		 110/* mailbox system shutdown options */
111#define LPFC_MBX_NO_WAIT 0
112#define LPFC_MBX_WAIT 1
113
875fbdfe
JSEC		 114enum lpfc_polling_flags {
115 ENABLE_FCP_RING_POLLING = 0x1,
116 DISABLE_FCP_RING_INT = 0x2
117};
118
dea3101e
JB		 119/* Provide DMA memory definitions the driver uses per port instance. */
120struct lpfc_dmabuf {
121 struct list_head list;
122 void *virt; /* virtual address ptr */
123 dma_addr_t phys; /* mapped address */
76bb24ef 124 uint32_t buffer_tag; /* used for tagged queue ring */
dea3101e
JB		 125};
126
127struct lpfc_dma_pool {
128 struct lpfc_dmabuf *elements;
129 uint32_t max_count;
130 uint32_t current_count;
131};
132
ed957684 133struct hbq_dmabuf {
da0436e9 134 struct lpfc_dmabuf hbuf;
ed957684 135 struct lpfc_dmabuf dbuf;
51ef4c26 136 uint32_t size;
ed957684 137 uint32_t tag;
4d9ab994 138 struct lpfc_cq_event cq_event;
45ed1190 139 unsigned long time_stamp;
ed957684
JS		 140};
141
dea3101e
JB		 142/* Priority bit. Set value to exceed low water mark in lpfc_mem. */
143#define MEM_PRI 0x100
144
145
146/****************************************************************************/
147/* Device VPD save area */
148/****************************************************************************/
149typedef struct lpfc_vpd {
150 uint32_t status; /* vpd status value */
151 uint32_t length; /* number of bytes actually returned */
152 struct {
153 uint32_t rsvd1; /* Revision numbers */
154 uint32_t biuRev;
155 uint32_t smRev;
156 uint32_t smFwRev;
157 uint32_t endecRev;
158 uint16_t rBit;
159 uint8_t fcphHigh;
160 uint8_t fcphLow;
161 uint8_t feaLevelHigh;
162 uint8_t feaLevelLow;
163 uint32_t postKernRev;
164 uint32_t opFwRev;
165 uint8_t opFwName[16];
166 uint32_t sli1FwRev;
167 uint8_t sli1FwName[16];
168 uint32_t sli2FwRev;
169 uint8_t sli2FwName[16];
170 } rev;
92d7f7b0
JS		 171 struct {
172#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 173 uint32_t rsvd3 :19; /* Reserved */
174 uint32_t cdss : 1; /* Configure Data Security SLI */
175 uint32_t rsvd2 : 3; /* Reserved */
176 uint32_t cbg : 1; /* Configure BlockGuard */
92d7f7b0
JS		 177 uint32_t cmv : 1; /* Configure Max VPIs */
178 uint32_t ccrp : 1; /* Config Command Ring Polling */
179 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
180 uint32_t chbs : 1; /* Cofigure Host Backing store */
181 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
182 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
183 uint32_t cmx : 1; /* Configure Max XRIs */
184 uint32_t cmr : 1; /* Configure Max RPIs */
185#else /* __LITTLE_ENDIAN */
186 uint32_t cmr : 1; /* Configure Max RPIs */
187 uint32_t cmx : 1; /* Configure Max XRIs */
188 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
189 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
190 uint32_t chbs : 1; /* Cofigure Host Backing store */
191 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
192 uint32_t ccrp : 1; /* Config Command Ring Polling */
193 uint32_t cmv : 1; /* Configure Max VPIs */
da0436e9
JS		 194 uint32_t cbg : 1; /* Configure BlockGuard */
195 uint32_t rsvd2 : 3; /* Reserved */
196 uint32_t cdss : 1; /* Configure Data Security SLI */
197 uint32_t rsvd3 :19; /* Reserved */
92d7f7b0
JS		 198#endif
199 } sli3Feat;
dea3101e
JB		 200} lpfc_vpd_t;
201
202struct lpfc_scsi_buf;
203
204
205/*
206 * lpfc stat counters
207 */
208struct lpfc_stats {
209 /* Statistics for ELS commands */
210 uint32_t elsLogiCol;
211 uint32_t elsRetryExceeded;
212 uint32_t elsXmitRetry;
213 uint32_t elsDelayRetry;
214 uint32_t elsRcvDrop;
215 uint32_t elsRcvFrame;
216 uint32_t elsRcvRSCN;
217 uint32_t elsRcvRNID;
218 uint32_t elsRcvFARP;
219 uint32_t elsRcvFARPR;
220 uint32_t elsRcvFLOGI;
221 uint32_t elsRcvPLOGI;
222 uint32_t elsRcvADISC;
223 uint32_t elsRcvPDISC;
224 uint32_t elsRcvFAN;
225 uint32_t elsRcvLOGO;
226 uint32_t elsRcvPRLO;
227 uint32_t elsRcvPRLI;
7bb3b137 228 uint32_t elsRcvLIRR;
12265f68 229 uint32_t elsRcvRLS;
7bb3b137
JW		 230 uint32_t elsRcvRPS;
231 uint32_t elsRcvRPL;
5ffc266e 232 uint32_t elsRcvRRQ;
12265f68
JS		 233 uint32_t elsRcvRTV;
234 uint32_t elsRcvECHO;
dea3101e 235 uint32_t elsXmitFLOGI;
92d7f7b0 236 uint32_t elsXmitFDISC;
dea3101e
JB		 237 uint32_t elsXmitPLOGI;
238 uint32_t elsXmitPRLI;
239 uint32_t elsXmitADISC;
240 uint32_t elsXmitLOGO;
241 uint32_t elsXmitSCR;
242 uint32_t elsXmitRNID;
243 uint32_t elsXmitFARP;
244 uint32_t elsXmitFARPR;
245 uint32_t elsXmitACC;
246 uint32_t elsXmitLSRJT;
247
248 uint32_t frameRcvBcast;
249 uint32_t frameRcvMulti;
250 uint32_t strayXmitCmpl;
251 uint32_t frameXmitDelay;
252 uint32_t xriCmdCmpl;
253 uint32_t xriStatErr;
254 uint32_t LinkUp;
255 uint32_t LinkDown;
256 uint32_t LinkMultiEvent;
257 uint32_t NoRcvBuf;
258 uint32_t fcpCmd;
259 uint32_t fcpCmpl;
260 uint32_t fcpRspErr;
261 uint32_t fcpRemoteStop;
262 uint32_t fcpPortRjt;
263 uint32_t fcpPortBusy;
264 uint32_t fcpError;
265 uint32_t fcpLocalErr;
266};
267
2e0fef85
JS		 268struct lpfc_hba;
269
92d7f7b0 270
2e0fef85 271enum discovery_state {
92d7f7b0
JS		 272 LPFC_VPORT_UNKNOWN = 0, /* vport state is unknown */
273 LPFC_VPORT_FAILED = 1, /* vport has failed */
274 LPFC_LOCAL_CFG_LINK = 6, /* local NPORT Id configured */
275 LPFC_FLOGI = 7, /* FLOGI sent to Fabric */
276 LPFC_FDISC = 8, /* FDISC sent for vport */
277 LPFC_FABRIC_CFG_LINK = 9, /* Fabric assigned NPORT Id
278 * configured */
279 LPFC_NS_REG = 10, /* Register with NameServer */
280 LPFC_NS_QRY = 11, /* Query NameServer for NPort ID list */
281 LPFC_BUILD_DISC_LIST = 12, /* Build ADISC and PLOGI lists for
282 * device authentication / discovery */
283 LPFC_DISC_AUTH = 13, /* Processing ADISC list */
284 LPFC_VPORT_READY = 32,
2e0fef85
JS		 285};
286
287enum hba_state {
288 LPFC_LINK_UNKNOWN = 0, /* HBA state is unknown */
289 LPFC_WARM_START = 1, /* HBA state after selective reset */
290 LPFC_INIT_START = 2, /* Initial state after board reset */
291 LPFC_INIT_MBX_CMDS = 3, /* Initialize HBA with mbox commands */
292 LPFC_LINK_DOWN = 4, /* HBA initialized, link is down */
293 LPFC_LINK_UP = 5, /* Link is up - issue READ_LA */
92d7f7b0 294 LPFC_CLEAR_LA = 6, /* authentication cmplt - issue
2e0fef85 295 * CLEAR_LA */
92d7f7b0 296 LPFC_HBA_READY = 32,
2e0fef85
JS		 297 LPFC_HBA_ERROR = -1
298};
299
300struct lpfc_vport {
2e0fef85 301 struct lpfc_hba *phba;
3772a991 302 struct list_head listentry;
2e0fef85
JS		 303 uint8_t port_type;
304#define LPFC_PHYSICAL_PORT 1
305#define LPFC_NPIV_PORT 2
306#define LPFC_FABRIC_PORT 3
307 enum discovery_state port_state;
308
92d7f7b0 309 uint16_t vpi;
da0436e9 310 uint16_t vfi;
c868595d
JS		 311 uint8_t vpi_state;
312#define LPFC_VPI_REGISTERED 0x1
2e0fef85
JS		 313
314 uint32_t fc_flag; /* FC flags */
315/* Several of these flags are HBA centric and should be moved to
316 * phba->link_flag (e.g. FC_PTP, FC_PUBLIC_LOOP)
317 */
92d7f7b0
JS		 318#define FC_PT2PT 0x1 /* pt2pt with no fabric */
319#define FC_PT2PT_PLOGI 0x2 /* pt2pt initiate PLOGI */
320#define FC_DISC_TMO 0x4 /* Discovery timer running */
321#define FC_PUBLIC_LOOP 0x8 /* Public loop */
322#define FC_LBIT 0x10 /* LOGIN bit in loopinit set */
323#define FC_RSCN_MODE 0x20 /* RSCN cmd rcv'ed */
324#define FC_NLP_MORE 0x40 /* More node to process in node tbl */
325#define FC_OFFLINE_MODE 0x80 /* Interface is offline for diag */
326#define FC_FABRIC 0x100 /* We are fabric attached */
4b40c59e 327#define FC_VPORT_LOGO_RCVD 0x200 /* LOGO received on vport */
92d7f7b0 328#define FC_RSCN_DISCOVERY 0x400 /* Auth all devices after RSCN */
4b40c59e 329#define FC_LOGO_RCVD_DID_CHNG 0x800 /* FDISC on phys port detect DID chng*/
92d7f7b0
JS		 330#define FC_SCSI_SCAN_TMO 0x4000 /* scsi scan timer running */
331#define FC_ABORT_DISCOVERY 0x8000 /* we want to abort discovery */
332#define FC_NDISC_ACTIVE 0x10000 /* NPort discovery active */
333#define FC_BYPASSED_MODE 0x20000 /* NPort is in bypassed mode */
92d7f7b0
JS		 334#define FC_VPORT_NEEDS_REG_VPI 0x80000 /* Needs to have its vpi registered */
335#define FC_RSCN_DEFERRED 0x100000 /* A deferred RSCN being processed */
1c6834a7 336#define FC_VPORT_NEEDS_INIT_VPI 0x200000 /* Need to INIT_VPI before FDISC */
695a814e
JS		 337#define FC_VPORT_CVL_RCVD 0x400000 /* VLink failed due to CVL */
338#define FC_VFI_REGISTERED 0x800000 /* VFI is registered */
339#define FC_FDISC_COMPLETED 0x1000000/* FDISC completed */
92494144 340#define FC_DISC_DELAYED 0x2000000/* Delay NPort discovery */
2e0fef85 341
7ee5d43e
JS		 342 uint32_t ct_flags;
343#define FC_CT_RFF_ID 0x1 /* RFF_ID accepted by switch */
344#define FC_CT_RNN_ID 0x2 /* RNN_ID accepted by switch */
345#define FC_CT_RSNN_NN 0x4 /* RSNN_NN accepted by switch */
346#define FC_CT_RSPN_ID 0x8 /* RSPN_ID accepted by switch */
347#define FC_CT_RFT_ID 0x10 /* RFT_ID accepted by switch */
348
2e0fef85
JS		 349 struct list_head fc_nodes;
350
351 /* Keep counters for the number of entries in each list. */
352 uint16_t fc_plogi_cnt;
353 uint16_t fc_adisc_cnt;
354 uint16_t fc_reglogin_cnt;
355 uint16_t fc_prli_cnt;
356 uint16_t fc_unmap_cnt;
357 uint16_t fc_map_cnt;
358 uint16_t fc_npr_cnt;
359 uint16_t fc_unused_cnt;
360 struct serv_parm fc_sparam; /* buffer for our service parameters */
361
362 uint32_t fc_myDID; /* fibre channel S_ID */
363 uint32_t fc_prevDID; /* previous fibre channel S_ID */
92494144
JS		 364 struct lpfc_name fabric_portname;
365 struct lpfc_name fabric_nodename;
2e0fef85
JS		 366
367 int32_t stopped; /* HBA has not been restarted since last ERATT */
368 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
369
370 uint32_t num_disc_nodes; /*in addition to hba_state */
371
372 uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */
373 uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */
7f5f3d0d 374 uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */
2e0fef85
JS		 375 struct lpfc_dmabuf *fc_rscn_id_list[FC_MAX_HOLD_RSCN];
376 struct lpfc_name fc_nodename; /* fc nodename */
377 struct lpfc_name fc_portname; /* fc portname */
378
379 struct lpfc_work_evt disc_timeout_evt;
380
381 struct timer_list fc_disctmo; /* Discovery rescue timer */
382 uint8_t fc_ns_retry; /* retries for fabric nameserver */
383 uint32_t fc_prli_sent; /* cntr for outstanding PRLIs */
384
385 spinlock_t work_port_lock;
386 uint32_t work_port_events; /* Timeout to be handled */
858c9f6c
JS		 387#define WORKER_DISC_TMO 0x1 /* vport: Discovery timeout */
388#define WORKER_ELS_TMO 0x2 /* vport: ELS timeout */
389#define WORKER_FDMI_TMO 0x4 /* vport: FDMI timeout */
92494144 390#define WORKER_DELAYED_DISC_TMO 0x8 /* vport: delayed discovery */
858c9f6c
JS		 391
392#define WORKER_MBOX_TMO 0x100 /* hba: MBOX timeout */
393#define WORKER_HB_TMO 0x200 /* hba: Heart beat timeout */
b1c11812 394#define WORKER_FABRIC_BLOCK_TMO 0x400 /* hba: fabric block timeout */
858c9f6c
JS		 395#define WORKER_RAMP_DOWN_QUEUE 0x800 /* hba: Decrease Q depth */
396#define WORKER_RAMP_UP_QUEUE 0x1000 /* hba: Increase Q depth */
2a9bf3d0 397#define WORKER_SERVICE_TXQ 0x2000 /* hba: IOCBs on the txq */
2e0fef85
JS		 398
399 struct timer_list fc_fdmitmo;
400 struct timer_list els_tmofunc;
92494144 401 struct timer_list delayed_disc_tmo;
2e0fef85
JS		 402
403 int unreg_vpi_cmpl;
404
405 uint8_t load_flag;
406#define FC_LOADING 0x1 /* HBA in process of loading drvr */
407#define FC_UNLOADING 0x2 /* HBA in process of unloading drvr */
3de2a653
JS		 408 /* Vport Config Parameters */
409 uint32_t cfg_scan_down;
410 uint32_t cfg_lun_queue_depth;
411 uint32_t cfg_nodev_tmo;
412 uint32_t cfg_devloss_tmo;
413 uint32_t cfg_restrict_login;
414 uint32_t cfg_peer_port_login;
415 uint32_t cfg_fcp_class;
416 uint32_t cfg_use_adisc;
417 uint32_t cfg_fdmi_on;
418 uint32_t cfg_discovery_threads;
e8b62011 419 uint32_t cfg_log_verbose;
3de2a653 420 uint32_t cfg_max_luns;
7ee5d43e 421 uint32_t cfg_enable_da_id;
977b5a0a 422 uint32_t cfg_max_scsicmpl_time;
7dc517df 423 uint32_t cfg_tgt_queue_depth;
3de2a653
JS		 424
425 uint32_t dev_loss_tmo_changed;
51ef4c26
JS		 426
427 struct fc_vport *fc_vport;
428
923e4b6a 429#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
51ef4c26
JS		 430 struct dentry *debug_disc_trc;
431 struct dentry *debug_nodelist;
432 struct dentry *vport_debugfs_root;
433 struct lpfc_debugfs_trc *disc_trc;
434 atomic_t disc_trc_cnt;
435#endif
ea2151b4
JS		 436 uint8_t stat_data_enabled;
437 uint8_t stat_data_blocked;
da0436e9 438 struct list_head rcv_buffer_list;
45ed1190 439 unsigned long rcv_buffer_time_stamp;
da0436e9
JS		 440 uint32_t vport_flag;
441#define STATIC_VPORT 1
2e0fef85
JS		 442};
443
ed957684
JS		 444struct hbq_s {
445 uint16_t entry_count; /* Current number of HBQ slots */
a8adb832 446 uint16_t buffer_count; /* Current number of buffers posted */
ed957684
JS		 447 uint32_t next_hbqPutIdx; /* Index to next HBQ slot to use */
448 uint32_t hbqPutIdx; /* HBQ slot to use */
449 uint32_t local_hbqGetIdx; /* Local copy of Get index from Port */
51ef4c26
JS		 450 void *hbq_virt; /* Virtual ptr to this hbq */
451 struct list_head hbq_buffer_list; /* buffers assigned to this HBQ */
452 /* Callback for HBQ buffer allocation */
453 struct hbq_dmabuf *(*hbq_alloc_buffer) (struct lpfc_hba *);
454 /* Callback for HBQ buffer free */
455 void (*hbq_free_buffer) (struct lpfc_hba *,
456 struct hbq_dmabuf *);
ed957684
JS		 457};
458
51ef4c26
JS		 459#define LPFC_MAX_HBQS 4
460/* this matches the position in the lpfc_hbq_defs array */
92d7f7b0 461#define LPFC_ELS_HBQ 0
51ef4c26 462#define LPFC_EXTRA_HBQ 1
ed957684 463
7af67051
JS		 464enum hba_temp_state {
465 HBA_NORMAL_TEMP,
466 HBA_OVER_TEMP
467};
468
db2378e0
JS		 469enum intr_type_t {
470 NONE = 0,
471 INTx,
472 MSI,
473 MSIX,
474};
475
6dd9e31c 476#define LPFC_CT_CTX_MAX 64
f1c3b0fc
JS		 477struct unsol_rcv_ct_ctx {
478 uint32_t ctxt_id;
479 uint32_t SID;
6dd9e31c
JS		 480 uint32_t valid;
481#define UNSOL_INVALID 0
482#define UNSOL_VALID 1
7851fe2c
JS		 483 uint16_t oxid;
484 uint16_t rxid;
f1c3b0fc
JS		 485};
486
76a95d75
JS		 487#define LPFC_USER_LINK_SPEED_AUTO 0 /* auto select (default)*/
488#define LPFC_USER_LINK_SPEED_1G 1 /* 1 Gigabaud */
489#define LPFC_USER_LINK_SPEED_2G 2 /* 2 Gigabaud */
490#define LPFC_USER_LINK_SPEED_4G 4 /* 4 Gigabaud */
491#define LPFC_USER_LINK_SPEED_8G 8 /* 8 Gigabaud */
492#define LPFC_USER_LINK_SPEED_10G 10 /* 10 Gigabaud */
493#define LPFC_USER_LINK_SPEED_16G 16 /* 16 Gigabaud */
494#define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_16G
495#define LPFC_USER_LINK_SPEED_BITMAP ((1 << LPFC_USER_LINK_SPEED_16G) | \
496 (1 << LPFC_USER_LINK_SPEED_10G) | \
497 (1 << LPFC_USER_LINK_SPEED_8G) | \
498 (1 << LPFC_USER_LINK_SPEED_4G) | \
499 (1 << LPFC_USER_LINK_SPEED_2G) | \
500 (1 << LPFC_USER_LINK_SPEED_1G) | \
501 (1 << LPFC_USER_LINK_SPEED_AUTO))
502#define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16"
503
7ad20aa9
JS		 504enum nemb_type {
505 nemb_mse = 1,
506 nemb_hbd
507};
508
509enum mbox_type {
510 mbox_rd = 1,
511 mbox_wr
512};
513
514enum dma_type {
515 dma_mbox = 1,
516 dma_ebuf
517};
518
519enum sta_type {
520 sta_pre_addr = 1,
521 sta_pos_addr
522};
523
524struct lpfc_mbox_ext_buf_ctx {
525 uint32_t state;
526#define LPFC_BSG_MBOX_IDLE 0
527#define LPFC_BSG_MBOX_HOST 1
528#define LPFC_BSG_MBOX_PORT 2
529#define LPFC_BSG_MBOX_DONE 3
530#define LPFC_BSG_MBOX_ABTS 4
531 enum nemb_type nembType;
532 enum mbox_type mboxType;
533 uint32_t numBuf;
534 uint32_t mbxTag;
535 uint32_t seqNum;
536 struct lpfc_dmabuf *mbx_dmabuf;
537 struct list_head ext_dmabuf_list;
538};
539
dea3101e 540struct lpfc_hba {
3772a991
JS		 541 /* SCSI interface function jump table entries */
542 int (*lpfc_new_scsi_buf)
543 (struct lpfc_vport *, int);
544 struct lpfc_scsi_buf * (*lpfc_get_scsi_buf)
19ca7609 545 (struct lpfc_hba *, struct lpfc_nodelist *);
3772a991
JS		 546 int (*lpfc_scsi_prep_dma_buf)
547 (struct lpfc_hba *, struct lpfc_scsi_buf *);
548 void (*lpfc_scsi_unprep_dma_buf)
549 (struct lpfc_hba *, struct lpfc_scsi_buf *);
550 void (*lpfc_release_scsi_buf)
551 (struct lpfc_hba *, struct lpfc_scsi_buf *);
552 void (*lpfc_rampdown_queue_depth)
553 (struct lpfc_hba *);
554 void (*lpfc_scsi_prep_cmnd)
555 (struct lpfc_vport *, struct lpfc_scsi_buf *,
556 struct lpfc_nodelist *);
acd6859b 557
3772a991
JS		 558 /* IOCB interface function jump table entries */
559 int (*__lpfc_sli_issue_iocb)
560 (struct lpfc_hba *, uint32_t,
561 struct lpfc_iocbq *, uint32_t);
562 void (*__lpfc_sli_release_iocbq)(struct lpfc_hba *,
563 struct lpfc_iocbq *);
564 int (*lpfc_hba_down_post)(struct lpfc_hba *phba);
3772a991
JS		 565 IOCB_t * (*lpfc_get_iocb_from_iocbq)
566 (struct lpfc_iocbq *);
567 void (*lpfc_scsi_cmd_iocb_cmpl)
568 (struct lpfc_hba *, struct lpfc_iocbq *, struct lpfc_iocbq *);
569
570 /* MBOX interface function jump table entries */
571 int (*lpfc_sli_issue_mbox)
572 (struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t);
acd6859b 573
3772a991
JS		 574 /* Slow-path IOCB process function jump table entries */
575 void (*lpfc_sli_handle_slow_ring_event)
576 (struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
577 uint32_t mask);
acd6859b 578
3772a991
JS		 579 /* INIT device interface function jump table entries */
580 int (*lpfc_sli_hbq_to_firmware)
581 (struct lpfc_hba *, uint32_t, struct hbq_dmabuf *);
582 int (*lpfc_sli_brdrestart)
583 (struct lpfc_hba *);
584 int (*lpfc_sli_brdready)
585 (struct lpfc_hba *, uint32_t);
586 void (*lpfc_handle_eratt)
587 (struct lpfc_hba *);
588 void (*lpfc_stop_port)
589 (struct lpfc_hba *);
84d1b006 590 int (*lpfc_hba_init_link)
6e7288d9 591 (struct lpfc_hba *, uint32_t);
84d1b006 592 int (*lpfc_hba_down_link)
6e7288d9 593 (struct lpfc_hba *, uint32_t);
7f86059a
JS		 594 int (*lpfc_selective_reset)
595 (struct lpfc_hba *);
3772a991 596
acd6859b
JS		 597 int (*lpfc_bg_scsi_prep_dma_buf)
598 (struct lpfc_hba *, struct lpfc_scsi_buf *);
599 /* Add new entries here */
600
3772a991
JS		 601 /* SLI4 specific HBA data structure */
602 struct lpfc_sli4_hba sli4_hba;
603
dea3101e 604 struct lpfc_sli sli;
3772a991
JS		 605 uint8_t pci_dev_grp; /* lpfc PCI dev group: 0x0, 0x1, 0x2,... */
606 uint32_t sli_rev; /* SLI2, SLI3, or SLI4 */
ed957684 607 uint32_t sli3_options; /* Mask of enabled SLI3 options */
34b02dcd
JS		 608#define LPFC_SLI3_HBQ_ENABLED 0x01
609#define LPFC_SLI3_NPIV_ENABLED 0x02
610#define LPFC_SLI3_VPORT_TEARDOWN 0x04
611#define LPFC_SLI3_CRP_ENABLED 0x08
81301a9b 612#define LPFC_SLI3_BG_ENABLED 0x20
da0436e9 613#define LPFC_SLI3_DSS_ENABLED 0x40
fedd3b7b
JS		 614#define LPFC_SLI4_PERFH_ENABLED 0x80
615#define LPFC_SLI4_PHWQ_ENABLED 0x100
ed957684
JS		 616 uint32_t iocb_cmd_size;
617 uint32_t iocb_rsp_size;
2e0fef85
JS		 618
619 enum hba_state link_state;
620 uint32_t link_flag; /* link state flags */
311464ec 621#define LS_LOOPBACK_MODE 0x1 /* NPort is in Loopback mode */
2e0fef85
JS		 622 /* This flag is set while issuing */
623 /* INIT_LINK mailbox command */
92d7f7b0 624#define LS_NPIV_FAB_SUPPORTED 0x2 /* Fabric supports NPIV */
1b32f6aa 625#define LS_IGNORE_ERATT 0x4 /* intr handler should ignore ERATT */
2e0fef85 626
9399627f
JS		 627 uint32_t hba_flag; /* hba generic flags */
628#define HBA_ERATT_HANDLED 0x1 /* This flag is set when eratt handled */
da0436e9 629#define DEFER_ERATT 0x2 /* Deferred error attention in progress */
76a95d75 630#define HBA_FCOE_MODE 0x4 /* HBA function in FCoE Mode */
45ed1190 631#define HBA_SP_QUEUE_EVT 0x8 /* Slow-path qevt posted to worker thread*/
da0436e9
JS		 632#define HBA_POST_RECEIVE_BUFFER 0x10 /* Rcv buffers need to be posted */
633#define FCP_XRI_ABORT_EVENT 0x20
634#define ELS_XRI_ABORT_EVENT 0x40
635#define ASYNC_EVENT 0x80
a0c87cbd 636#define LINK_DISABLED 0x100 /* Link disabled by user */
a93ff37a
JS		 637#define FCF_TS_INPROG 0x200 /* FCF table scan in progress */
638#define FCF_RR_INPROG 0x400 /* FCF roundrobin flogi in progress */
639#define HBA_FIP_SUPPORT 0x800 /* FIP support in HBA */
640#define HBA_AER_ENABLED 0x1000 /* AER enabled with HBA */
641#define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */
19ca7609 642#define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */
4f2e66c6 643#define HBA_FCP_IOQ_FLUSH 0x8000 /* FCP I/O queues being flushed */
45ed1190 644 uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
34b02dcd
JS		 645 struct lpfc_dmabuf slim2p;
646
647 MAILBOX_t *mbox;
7a470277 648 uint32_t *mbox_ext;
7ad20aa9 649 struct lpfc_mbox_ext_buf_ctx mbox_ext_buf_ctx;
9399627f 650 uint32_t ha_copy;
34b02dcd
JS		 651 struct _PCB *pcb;
652 struct _IOCB *IOCBs;
2e0fef85 653
34b02dcd 654 struct lpfc_dmabuf hbqslimp;
2e0fef85 655
dea3101e
JB		 656 uint16_t pci_cfg_value;
657
dea3101e
JB		 658 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
659
660 uint32_t fc_eventTag; /* event tag for link attention */
4d9ab994 661 uint32_t link_events;
dea3101e 662
dea3101e 663 /* These fields used to be binfo */
dea3101e 664 uint32_t fc_pref_DID; /* preferred D_ID */
92d7f7b0 665 uint8_t fc_pref_ALPA; /* preferred AL_PA */
12265f68 666 uint32_t fc_edtovResol; /* E_D_TOV timer resolution */
dea3101e
JB		 667 uint32_t fc_edtov; /* E_D_TOV timer value */
668 uint32_t fc_arbtov; /* ARB_TOV timer value */
669 uint32_t fc_ratov; /* R_A_TOV timer value */
670 uint32_t fc_rttov; /* R_T_TOV timer value */
671 uint32_t fc_altov; /* AL_TOV timer value */
672 uint32_t fc_crtov; /* C_R_TOV timer value */
673 uint32_t fc_citov; /* C_I_TOV timer value */
dea3101e 674
dea3101e
JB		 675 struct serv_parm fc_fabparam; /* fabric service parameters buffer */
676 uint8_t alpa_map[128]; /* AL_PA map from READ_LA */
677
dea3101e 678 uint32_t lmt;
dea3101e
JB		 679
680 uint32_t fc_topology; /* link topology, from LINK INIT */
e74c03c8 681 uint32_t fc_topology_changed; /* link topology, from LINK INIT */
dea3101e
JB		 682
683 struct lpfc_stats fc_stat;
684
dea3101e
JB		 685 struct lpfc_nodelist fc_fcpnodev; /* nodelist entry for no device */
686 uint32_t nport_event_cnt; /* timestamp for nlplist entry */
687
2e0fef85
JS		 688 uint8_t wwnn[8];
689 uint8_t wwpn[8];
dea3101e
JB		 690 uint32_t RandomData[7];
691
3de2a653 692 /* HBA Config Parameters */
dea3101e 693 uint32_t cfg_ack0;
78b2d852 694 uint32_t cfg_enable_npiv;
19ca7609 695 uint32_t cfg_enable_rrq;
dea3101e 696 uint32_t cfg_topology;
dea3101e 697 uint32_t cfg_link_speed;
7d791df7
JS		 698#define LPFC_FCF_FOV 1 /* Fast fcf failover */
699#define LPFC_FCF_PRIORITY 2 /* Priority fcf failover */
700 uint32_t cfg_fcf_failover_policy;
49aa143d 701 uint32_t cfg_fcp_io_sched;
a6571c6e 702 uint32_t cfg_fcp2_no_tgt_reset;
dea3101e
JB		 703 uint32_t cfg_cr_delay;
704 uint32_t cfg_cr_count;
cf5bf97e 705 uint32_t cfg_multi_ring_support;
a4bc3379
JS		 706 uint32_t cfg_multi_ring_rctl;
707 uint32_t cfg_multi_ring_type;
875fbdfe
JSEC		 708 uint32_t cfg_poll;
709 uint32_t cfg_poll_tmo;
4ff43246 710 uint32_t cfg_use_msi;
da0436e9 711 uint32_t cfg_fcp_imax;
7bb03bbf 712 uint32_t cfg_fcp_cpu_map;
da0436e9
JS		 713 uint32_t cfg_fcp_wq_count;
714 uint32_t cfg_fcp_eq_count;
67d12733 715 uint32_t cfg_fcp_io_channel;
96f7077f 716 uint32_t cfg_total_seg_cnt;
dea3101e 717 uint32_t cfg_sg_seg_cnt;
81301a9b 718 uint32_t cfg_prot_sg_seg_cnt;
dea3101e 719 uint32_t cfg_sg_dma_buf_size;
a12e07bc 720 uint64_t cfg_soft_wwnn;
c3f28afa 721 uint64_t cfg_soft_wwpn;
3de2a653 722 uint32_t cfg_hba_queue_depth;
13815c83
JS		 723 uint32_t cfg_enable_hba_reset;
724 uint32_t cfg_enable_hba_heartbeat;
81301a9b 725 uint32_t cfg_enable_bg;
7a470277 726 uint32_t cfg_hostmem_hgp;
da0436e9 727 uint32_t cfg_log_verbose;
0d878419 728 uint32_t cfg_aer_support;
912e3acd 729 uint32_t cfg_sriov_nr_virtfn;
c71ab861 730 uint32_t cfg_request_firmware_upgrade;
2a9bf3d0 731 uint32_t cfg_iocb_cnt;
84d1b006 732 uint32_t cfg_suppress_link_up;
e40a02c1
JS		 733#define LPFC_INITIALIZE_LINK 0 /* do normal init_link mbox */
734#define LPFC_DELAY_INIT_LINK 1 /* layered driver hold off */
735#define LPFC_DELAY_INIT_LINK_INDEFINITELY 2 /* wait, manual intervention */
ab56dc2e 736 uint32_t cfg_enable_dss;
dea3101e
JB		 737 lpfc_vpd_t vpd; /* vital product data */
738
dea3101e
JB		 739 struct pci_dev *pcidev;
740 struct list_head work_list;
741 uint32_t work_ha; /* Host Attention Bits for WT */
742 uint32_t work_ha_mask; /* HA Bits owned by WT */
743 uint32_t work_hs; /* HS stored in case of ERRAT */
744 uint32_t work_status[2]; /* Extra status from SLIM */
dea3101e 745
5e9d9b82 746 wait_queue_head_t work_waitq;
dea3101e 747 struct task_struct *worker_thread;
d7c255b2 748 unsigned long data_flags;
dea3101e 749
3163f725 750 uint32_t hbq_in_use; /* HBQs in use flag */
3772a991 751 struct list_head rb_pend_list; /* Received buffers to be processed */
ed957684 752 uint32_t hbq_count; /* Count of configured HBQs */
92d7f7b0 753 struct hbq_s hbqs[LPFC_MAX_HBQS]; /* local copy of hbq indicies */
ed957684 754
2a76a283 755 atomic_t fcp_qidx; /* next work queue to post work to */
8fa38513 756
dea3101e 757 unsigned long pci_bar0_map; /* Physical address for PCI BAR0 */
3772a991 758 unsigned long pci_bar1_map; /* Physical address for PCI BAR1 */
dea3101e
JB		 759 unsigned long pci_bar2_map; /* Physical address for PCI BAR2 */
760 void __iomem *slim_memmap_p; /* Kernel memory mapped address for
761 PCI BAR0 */
762 void __iomem *ctrl_regs_memmap_p;/* Kernel memory mapped address for
763 PCI BAR2 */
764
962bc51b
JS		 765 void __iomem *pci_bar0_memmap_p; /* Kernel memory mapped address for
766 PCI BAR0 with dual-ULP support */
767 void __iomem *pci_bar2_memmap_p; /* Kernel memory mapped address for
768 PCI BAR2 with dual-ULP support */
769 void __iomem *pci_bar4_memmap_p; /* Kernel memory mapped address for
770 PCI BAR4 with dual-ULP support */
771#define PCI_64BIT_BAR0 0
772#define PCI_64BIT_BAR2 2
773#define PCI_64BIT_BAR4 4
dea3101e
JB		 774 void __iomem *MBslimaddr; /* virtual address for mbox cmds */
775 void __iomem *HAregaddr; /* virtual address for host attn reg */
776 void __iomem *CAregaddr; /* virtual address for chip attn reg */
777 void __iomem *HSregaddr; /* virtual address for host status
778 reg */
779 void __iomem *HCregaddr; /* virtual address for host ctl reg */
780
ed957684 781 struct lpfc_hgp __iomem *host_gp; /* Host side get/put pointers */
34b02dcd 782 struct lpfc_pgp *port_gp;
ed957684 783 uint32_t __iomem *hbq_put; /* Address in SLIM to HBQ put ptrs */
92d7f7b0 784 uint32_t *hbq_get; /* Host mem address of HBQ get ptrs */
ed957684 785
dea3101e 786 int brd_no; /* FC board number */
dea3101e
JB		 787 char SerialNumber[32]; /* adapter Serial Number */
788 char OptionROMVersion[32]; /* adapter BIOS / Fcode version */
789 char ModelDesc[256]; /* Model Description */
790 char ModelName[80]; /* Model Name */
791 char ProgramType[256]; /* Program Type */
792 char Port[20]; /* Port No */
793 uint8_t vpd_flag; /* VPD data flag */
794
795#define VPD_MODEL_DESC 0x1 /* valid vpd model description */
796#define VPD_MODEL_NAME 0x2 /* valid vpd model name */
797#define VPD_PROGRAM_TYPE 0x4 /* valid vpd program type */
798#define VPD_PORT 0x8 /* valid vpd port data */
799#define VPD_MASK 0xf /* mask for any vpd data */
800
a12e07bc 801 uint8_t soft_wwn_enable;
c3f28afa 802
875fbdfe 803 struct timer_list fcp_poll_timer;
9399627f 804 struct timer_list eratt_poll;
875fbdfe 805
dea3101e
JB		 806 /*
807 * stat counters
808 */
809 uint64_t fc4InputRequests;
810 uint64_t fc4OutputRequests;
811 uint64_t fc4ControlRequests;
81301a9b
JS		 812 uint64_t bg_guard_err_cnt;
813 uint64_t bg_apptag_err_cnt;
814 uint64_t bg_reftag_err_cnt;
dea3101e 815
dea3101e 816 /* fastpath list. */
a40fc5f0
JS		 817 spinlock_t scsi_buf_list_get_lock; /* SCSI buf alloc list lock */
818 spinlock_t scsi_buf_list_put_lock; /* SCSI buf free list lock */
819 struct list_head lpfc_scsi_buf_list_get;
820 struct list_head lpfc_scsi_buf_list_put;
dea3101e
JB		 821 uint32_t total_scsi_bufs;
822 struct list_head lpfc_iocb_list;
823 uint32_t total_iocbq_bufs;
19ca7609 824 struct list_head active_rrq_list;
2e0fef85 825 spinlock_t hbalock;
dea3101e
JB		 826
827 /* pci_mem_pools */
828 struct pci_pool *lpfc_scsi_dma_buf_pool;
829 struct pci_pool *lpfc_mbuf_pool;
da0436e9
JS		 830 struct pci_pool *lpfc_hrb_pool; /* header receive buffer pool */
831 struct pci_pool *lpfc_drb_pool; /* data receive buffer pool */
8568a4d2 832 struct pci_pool *lpfc_hbq_pool; /* SLI3 hbq buffer pool */
dea3101e
JB		 833 struct lpfc_dma_pool lpfc_mbuf_safety_pool;
834
835 mempool_t *mbox_mem_pool;
836 mempool_t *nlp_mem_pool;
19ca7609 837 mempool_t *rrq_pool;
f888ba3c
JSEC		 838
839 struct fc_host_statistics link_stats;
db2378e0 840 enum intr_type_t intr_type;
5b75da2f
JS		 841 uint32_t intr_mode;
842#define LPFC_INTR_ERROR 0xFFFFFFFF
9399627f 843 struct msix_entry msix_entries[LPFC_MSIX_VECTORS];
858c9f6c 844
2e0fef85 845 struct list_head port_list;
549e55cd
JS		 846 struct lpfc_vport *pport; /* physical lpfc_vport pointer */
847 uint16_t max_vpi; /* Maximum virtual nports */
09372820 848#define LPFC_MAX_VPI 0xFFFF /* Max number of VPI supported */
da0436e9
JS		 849 uint16_t max_vports; /*
850 * For IOV HBAs max_vpi can change
851 * after a reset. max_vports is max
852 * number of vports present. This can
853 * be greater than max_vpi.
854 */
855 uint16_t vpi_base;
856 uint16_t vfi_base;
549e55cd 857 unsigned long *vpi_bmask; /* vpi allocation table */
6d368e53
JS		 858 uint16_t *vpi_ids;
859 uint16_t vpi_count;
860 struct list_head lpfc_vpi_blk_list;
92d7f7b0
JS		 861
862 /* Data structure used by fabric iocb scheduler */
863 struct list_head fabric_iocb_list;
864 atomic_t fabric_iocb_count;
865 struct timer_list fabric_block_timer;
866 unsigned long bit_flags;
867#define FABRIC_COMANDS_BLOCKED 0
868 atomic_t num_rsrc_err;
869 atomic_t num_cmd_success;
870 unsigned long last_rsrc_error_time;
871 unsigned long last_ramp_down_time;
872 unsigned long last_ramp_up_time;
923e4b6a 873#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
858c9f6c
JS		 874 struct dentry *hba_debugfs_root;
875 atomic_t debugfs_vport_count;
78b2d852 876 struct dentry *debug_hbqinfo;
c95d6c6c
JS		 877 struct dentry *debug_dumpHostSlim;
878 struct dentry *debug_dumpHBASlim;
f9bb2da1
JS		 879 struct dentry *debug_dumpData; /* BlockGuard BPL */
880 struct dentry *debug_dumpDif; /* BlockGuard BPL */
881 struct dentry *debug_InjErrLBA; /* LBA to inject errors at */
4ac9b226
JS		 882 struct dentry *debug_InjErrNPortID; /* NPortID to inject errors at */
883 struct dentry *debug_InjErrWWPN; /* WWPN to inject errors at */
f9bb2da1
JS		 884 struct dentry *debug_writeGuard; /* inject write guard_tag errors */
885 struct dentry *debug_writeApp; /* inject write app_tag errors */
886 struct dentry *debug_writeRef; /* inject write ref_tag errors */
acd6859b 887 struct dentry *debug_readGuard; /* inject read guard_tag errors */
f9bb2da1
JS		 888 struct dentry *debug_readApp; /* inject read app_tag errors */
889 struct dentry *debug_readRef; /* inject read ref_tag errors */
890
891 /* T10 DIF error injection */
892 uint32_t lpfc_injerr_wgrd_cnt;
893 uint32_t lpfc_injerr_wapp_cnt;
894 uint32_t lpfc_injerr_wref_cnt;
acd6859b 895 uint32_t lpfc_injerr_rgrd_cnt;
f9bb2da1
JS		 896 uint32_t lpfc_injerr_rapp_cnt;
897 uint32_t lpfc_injerr_rref_cnt;
4ac9b226
JS		 898 uint32_t lpfc_injerr_nportid;
899 struct lpfc_name lpfc_injerr_wwpn;
f9bb2da1 900 sector_t lpfc_injerr_lba;
acd6859b 901#define LPFC_INJERR_LBA_OFF (sector_t)(-1)
f9bb2da1 902
a58cbd52
JS		 903 struct dentry *debug_slow_ring_trc;
904 struct lpfc_debugfs_trc *slow_ring_trc;
905 atomic_t slow_ring_trc_cnt;
2a622bfb
JS		 906 /* iDiag debugfs sub-directory */
907 struct dentry *idiag_root;
908 struct dentry *idiag_pci_cfg;
b76f2dc9 909 struct dentry *idiag_bar_acc;
2a622bfb 910 struct dentry *idiag_que_info;
86a80846
JS		 911 struct dentry *idiag_que_acc;
912 struct dentry *idiag_drb_acc;
b76f2dc9
JS		 913 struct dentry *idiag_ctl_acc;
914 struct dentry *idiag_mbx_acc;
915 struct dentry *idiag_ext_acc;
858c9f6c
JS		 916#endif
917
0ff10d46
JS		 918 /* Used for deferred freeing of ELS data buffers */
919 struct list_head elsbuf;
920 int elsbuf_cnt;
921 int elsbuf_prev_cnt;
922
57127f15 923 uint8_t temp_sensor_support;
858c9f6c
JS		 924 /* Fields used for heart beat. */
925 unsigned long last_completion_time;
bc73905a 926 unsigned long skipped_hb;
858c9f6c
JS		 927 struct timer_list hb_tmofunc;
928 uint8_t hb_outstanding;
19ca7609 929 struct timer_list rrq_tmr;
84774a4d 930 enum hba_temp_state over_temp_state;
e47c9093
JS		 931 /* ndlp reference management */
932 spinlock_t ndlp_lock;
76bb24ef
JS		 933 /*
934 * Following bit will be set for all buffer tags which are not
935 * associated with any HBQ.
936 */
937#define QUE_BUFTAG_BIT (1<<31)
938 uint32_t buffer_tag_count;
84774a4d
JS		 939 int wait_4_mlo_maint_flg;
940 wait_queue_head_t wait_4_mlo_m_q;
ea2151b4
JS		 941 /* data structure used for latency data collection */
942#define LPFC_NO_BUCKET 0
943#define LPFC_LINEAR_BUCKET 1
944#define LPFC_POWER2_BUCKET 2
945 uint8_t bucket_type;
946 uint32_t bucket_base;
947 uint32_t bucket_step;
948
949/* Maximum number of events that can be outstanding at any time*/
950#define LPFC_MAX_EVT_COUNT 512
951 atomic_t fast_event_count;
32b9793f
JS		 952 uint32_t fcoe_eventtag;
953 uint32_t fcoe_eventtag_at_fcf_scan;
80c17849
JS		 954 uint32_t fcoe_cvl_eventtag;
955 uint32_t fcoe_cvl_eventtag_attn;
da0436e9
JS		 956 struct lpfc_fcf fcf;
957 uint8_t fc_map[3];
958 uint8_t valid_vlan;
959 uint16_t vlan_id;
960 struct list_head fcf_conn_rec_list;
f1c3b0fc 961
4fede78f 962 spinlock_t ct_ev_lock; /* synchronize access to ct_ev_waiters */
f1c3b0fc 963 struct list_head ct_ev_waiters;
6dd9e31c 964 struct unsol_rcv_ct_ctx ct_ctx[LPFC_CT_CTX_MAX];
f1c3b0fc 965 uint32_t ctx_idx;
e2aed29f
JS		 966
967 uint8_t menlo_flag; /* menlo generic flags */
968#define HBA_MENLO_SUPPORT 0x1 /* HBA supports menlo commands */
2a9bf3d0
JS		 969 uint32_t iocb_cnt;
970 uint32_t iocb_max;
d7c47992 971 atomic_t sdev_cnt;
bc73905a
JS		 972 uint8_t fips_spec_rev;
973 uint8_t fips_level;
dea3101e
JB		 974};
975
2e0fef85
JS		 976static inline struct Scsi_Host *
977lpfc_shost_from_vport(struct lpfc_vport *vport)
978{
979 return container_of((void *) vport, struct Scsi_Host, hostdata[0]);
980}
981
5b8bd0c9 982static inline void
2e0fef85
JS		 983lpfc_set_loopback_flag(struct lpfc_hba *phba)
984{
5b8bd0c9 985 if (phba->cfg_topology == FLAGS_LOCAL_LB)
2e0fef85 986 phba->link_flag |= LS_LOOPBACK_MODE;
5b8bd0c9 987 else
2e0fef85
JS		 988 phba->link_flag &= ~LS_LOOPBACK_MODE;
989}
990
991static inline int
992lpfc_is_link_up(struct lpfc_hba *phba)
993{
994 return phba->link_state == LPFC_LINK_UP ||
92d7f7b0
JS		 995 phba->link_state == LPFC_CLEAR_LA ||
996 phba->link_state == LPFC_HBA_READY;
5b8bd0c9 997}
dea3101e 998
5e9d9b82
JS		 999static inline void
1000lpfc_worker_wake_up(struct lpfc_hba *phba)
1001{
1002 /* Set the lpfc data pending flag */
1003 set_bit(LPFC_DATA_READY, &phba->data_flags);
1004
1005 /* Wake up worker thread */
1006 wake_up(&phba->work_waitq);
1007 return;
1008}
1009
9940b97b
JS		 1010static inline int
1011lpfc_readl(void __iomem *addr, uint32_t *data)
1012{
1013 uint32_t temp;
1014 temp = readl(addr);
1015 if (temp == 0xffffffff)
1016 return -EIO;
1017 *data = temp;
1018 return 0;
1019}
1020
1021static inline int
9399627f
JS		 1022lpfc_sli_read_hs(struct lpfc_hba *phba)
1023{
1024 /*
1025 * There was a link/board error. Read the status register to retrieve
1026 * the error event and process it.
1027 */
1028 phba->sli.slistat.err_attn_event++;
1029
9940b97b
JS		 1030 /* Save status info and check for unplug error */
1031 if (lpfc_readl(phba->HSregaddr, &phba->work_hs) ||
1032 lpfc_readl(phba->MBslimaddr + 0xa8, &phba->work_status[0]) ||
1033 lpfc_readl(phba->MBslimaddr + 0xac, &phba->work_status[1])) {
1034 return -EIO;
1035 }
9399627f
JS		 1036
1037 /* Clear chip Host Attention error bit */
1038 writel(HA_ERATT, phba->HAregaddr);
1039 readl(phba->HAregaddr); /* flush */
1040 phba->pport->stopped = 1;
1041
9940b97b 1042 return 0;
9399627f 1043}
kernel source for telekom puls (alcatel/mediatek)