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[PATCH] pcmcia: new suspend core
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / libata-core.c
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1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
64static unsigned int ata_busy_sleep (struct ata_port *ap,
65 unsigned long tmout_pat,
66 unsigned long tmout);
59a10b17 67static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 68static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT		 69static void ata_set_mode(struct ata_port *ap);
70static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 71static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 72static int fgb(u32 bitmap);
057ace5e 73static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 74 u8 *xfer_mode_out,
75 unsigned int *xfer_shift_out);
1da177e4
LT		 76static void __ata_qc_complete(struct ata_queued_cmd *qc);
77
78static unsigned int ata_unique_id = 1;
79static struct workqueue_struct *ata_wq;
80
1623c81e
JG		 81int atapi_enabled = 0;
82module_param(atapi_enabled, int, 0444);
83MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
84
1da177e4
LT		 85MODULE_AUTHOR("Jeff Garzik");
86MODULE_DESCRIPTION("Library module for ATA devices");
87MODULE_LICENSE("GPL");
88MODULE_VERSION(DRV_VERSION);
89
90/**
6f0ef4fa 91 * ata_tf_load_pio - send taskfile registers to host controller
1da177e4
LT		 92 * @ap: Port to which output is sent
93 * @tf: ATA taskfile register set
94 *
95 * Outputs ATA taskfile to standard ATA host controller.
96 *
97 * LOCKING:
98 * Inherited from caller.
99 */
100
057ace5e 101static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 102{
103 struct ata_ioports *ioaddr = &ap->ioaddr;
104 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
105
106 if (tf->ctl != ap->last_ctl) {
107 outb(tf->ctl, ioaddr->ctl_addr);
108 ap->last_ctl = tf->ctl;
109 ata_wait_idle(ap);
110 }
111
112 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
113 outb(tf->hob_feature, ioaddr->feature_addr);
114 outb(tf->hob_nsect, ioaddr->nsect_addr);
115 outb(tf->hob_lbal, ioaddr->lbal_addr);
116 outb(tf->hob_lbam, ioaddr->lbam_addr);
117 outb(tf->hob_lbah, ioaddr->lbah_addr);
118 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
119 tf->hob_feature,
120 tf->hob_nsect,
121 tf->hob_lbal,
122 tf->hob_lbam,
123 tf->hob_lbah);
124 }
125
126 if (is_addr) {
127 outb(tf->feature, ioaddr->feature_addr);
128 outb(tf->nsect, ioaddr->nsect_addr);
129 outb(tf->lbal, ioaddr->lbal_addr);
130 outb(tf->lbam, ioaddr->lbam_addr);
131 outb(tf->lbah, ioaddr->lbah_addr);
132 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
133 tf->feature,
134 tf->nsect,
135 tf->lbal,
136 tf->lbam,
137 tf->lbah);
138 }
139
140 if (tf->flags & ATA_TFLAG_DEVICE) {
141 outb(tf->device, ioaddr->device_addr);
142 VPRINTK("device 0x%X\n", tf->device);
143 }
144
145 ata_wait_idle(ap);
146}
147
148/**
149 * ata_tf_load_mmio - send taskfile registers to host controller
150 * @ap: Port to which output is sent
151 * @tf: ATA taskfile register set
152 *
153 * Outputs ATA taskfile to standard ATA host controller using MMIO.
154 *
155 * LOCKING:
156 * Inherited from caller.
157 */
158
057ace5e 159static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 160{
161 struct ata_ioports *ioaddr = &ap->ioaddr;
162 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
163
164 if (tf->ctl != ap->last_ctl) {
165 writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
166 ap->last_ctl = tf->ctl;
167 ata_wait_idle(ap);
168 }
169
170 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
171 writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr);
172 writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr);
173 writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr);
174 writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr);
175 writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr);
176 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
177 tf->hob_feature,
178 tf->hob_nsect,
179 tf->hob_lbal,
180 tf->hob_lbam,
181 tf->hob_lbah);
182 }
183
184 if (is_addr) {
185 writeb(tf->feature, (void __iomem *) ioaddr->feature_addr);
186 writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
187 writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
188 writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
189 writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
190 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
191 tf->feature,
192 tf->nsect,
193 tf->lbal,
194 tf->lbam,
195 tf->lbah);
196 }
197
198 if (tf->flags & ATA_TFLAG_DEVICE) {
199 writeb(tf->device, (void __iomem *) ioaddr->device_addr);
200 VPRINTK("device 0x%X\n", tf->device);
201 }
202
203 ata_wait_idle(ap);
204}
205
0baab86b
EF		 206
207/**
208 * ata_tf_load - send taskfile registers to host controller
209 * @ap: Port to which output is sent
210 * @tf: ATA taskfile register set
211 *
212 * Outputs ATA taskfile to standard ATA host controller using MMIO
213 * or PIO as indicated by the ATA_FLAG_MMIO flag.
214 * Writes the control, feature, nsect, lbal, lbam, and lbah registers.
215 * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect,
216 * hob_lbal, hob_lbam, and hob_lbah.
217 *
218 * This function waits for idle (!BUSY and !DRQ) after writing
219 * registers. If the control register has a new value, this
220 * function also waits for idle after writing control and before
221 * writing the remaining registers.
222 *
223 * May be used as the tf_load() entry in ata_port_operations.
224 *
225 * LOCKING:
226 * Inherited from caller.
227 */
057ace5e 228void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 229{
230 if (ap->flags & ATA_FLAG_MMIO)
231 ata_tf_load_mmio(ap, tf);
232 else
233 ata_tf_load_pio(ap, tf);
234}
235
236/**
0baab86b 237 * ata_exec_command_pio - issue ATA command to host controller
1da177e4
LT		 238 * @ap: port to which command is being issued
239 * @tf: ATA taskfile register set
240 *
0baab86b 241 * Issues PIO write to ATA command register, with proper
1da177e4
LT		 242 * synchronization with interrupt handler / other threads.
243 *
244 * LOCKING:
245 * spin_lock_irqsave(host_set lock)
246 */
247
057ace5e 248static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 249{
250 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
251
252 outb(tf->command, ap->ioaddr.command_addr);
253 ata_pause(ap);
254}
255
256
257/**
258 * ata_exec_command_mmio - issue ATA command to host controller
259 * @ap: port to which command is being issued
260 * @tf: ATA taskfile register set
261 *
262 * Issues MMIO write to ATA command register, with proper
263 * synchronization with interrupt handler / other threads.
264 *
265 * LOCKING:
266 * spin_lock_irqsave(host_set lock)
267 */
268
057ace5e 269static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 270{
271 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
272
273 writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr);
274 ata_pause(ap);
275}
276
0baab86b
EF		 277
278/**
279 * ata_exec_command - issue ATA command to host controller
280 * @ap: port to which command is being issued
281 * @tf: ATA taskfile register set
282 *
283 * Issues PIO/MMIO write to ATA command register, with proper
284 * synchronization with interrupt handler / other threads.
285 *
286 * LOCKING:
287 * spin_lock_irqsave(host_set lock)
288 */
057ace5e 289void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 290{
291 if (ap->flags & ATA_FLAG_MMIO)
292 ata_exec_command_mmio(ap, tf);
293 else
294 ata_exec_command_pio(ap, tf);
295}
296
1da177e4
LT		 297/**
298 * ata_tf_to_host - issue ATA taskfile to host controller
299 * @ap: port to which command is being issued
300 * @tf: ATA taskfile register set
301 *
302 * Issues ATA taskfile register set to ATA host controller,
303 * with proper synchronization with interrupt handler and
304 * other threads.
305 *
306 * LOCKING:
1da177e4
LT		 307 * spin_lock_irqsave(host_set lock)
308 */
309
e5338254
JG		 310static inline void ata_tf_to_host(struct ata_port *ap,
311 const struct ata_taskfile *tf)
1da177e4
LT		 312{
313 ap->ops->tf_load(ap, tf);
314 ap->ops->exec_command(ap, tf);
315}
316
317/**
0baab86b 318 * ata_tf_read_pio - input device's ATA taskfile shadow registers
1da177e4
LT		 319 * @ap: Port from which input is read
320 * @tf: ATA taskfile register set for storing input
321 *
322 * Reads ATA taskfile registers for currently-selected device
323 * into @tf.
324 *
325 * LOCKING:
326 * Inherited from caller.
327 */
328
329static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf)
330{
331 struct ata_ioports *ioaddr = &ap->ioaddr;
332
ac19bff2 333 tf->command = ata_check_status(ap);
0169e284 334 tf->feature = inb(ioaddr->error_addr);
1da177e4
LT		 335 tf->nsect = inb(ioaddr->nsect_addr);
336 tf->lbal = inb(ioaddr->lbal_addr);
337 tf->lbam = inb(ioaddr->lbam_addr);
338 tf->lbah = inb(ioaddr->lbah_addr);
339 tf->device = inb(ioaddr->device_addr);
340
341 if (tf->flags & ATA_TFLAG_LBA48) {
342 outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
343 tf->hob_feature = inb(ioaddr->error_addr);
344 tf->hob_nsect = inb(ioaddr->nsect_addr);
345 tf->hob_lbal = inb(ioaddr->lbal_addr);
346 tf->hob_lbam = inb(ioaddr->lbam_addr);
347 tf->hob_lbah = inb(ioaddr->lbah_addr);
348 }
349}
350
351/**
352 * ata_tf_read_mmio - input device's ATA taskfile shadow registers
353 * @ap: Port from which input is read
354 * @tf: ATA taskfile register set for storing input
355 *
356 * Reads ATA taskfile registers for currently-selected device
357 * into @tf via MMIO.
358 *
359 * LOCKING:
360 * Inherited from caller.
361 */
362
363static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf)
364{
365 struct ata_ioports *ioaddr = &ap->ioaddr;
366
ac19bff2 367 tf->command = ata_check_status(ap);
0169e284 368 tf->feature = readb((void __iomem *)ioaddr->error_addr);
1da177e4
LT		 369 tf->nsect = readb((void __iomem *)ioaddr->nsect_addr);
370 tf->lbal = readb((void __iomem *)ioaddr->lbal_addr);
371 tf->lbam = readb((void __iomem *)ioaddr->lbam_addr);
372 tf->lbah = readb((void __iomem *)ioaddr->lbah_addr);
373 tf->device = readb((void __iomem *)ioaddr->device_addr);
374
375 if (tf->flags & ATA_TFLAG_LBA48) {
376 writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr);
377 tf->hob_feature = readb((void __iomem *)ioaddr->error_addr);
378 tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr);
379 tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr);
380 tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr);
381 tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr);
382 }
383}
384
0baab86b
EF		 385
386/**
387 * ata_tf_read - input device's ATA taskfile shadow registers
388 * @ap: Port from which input is read
389 * @tf: ATA taskfile register set for storing input
390 *
391 * Reads ATA taskfile registers for currently-selected device
392 * into @tf.
393 *
394 * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48
395 * is set, also reads the hob registers.
396 *
397 * May be used as the tf_read() entry in ata_port_operations.
398 *
399 * LOCKING:
400 * Inherited from caller.
401 */
1da177e4
LT		 402void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
403{
404 if (ap->flags & ATA_FLAG_MMIO)
405 ata_tf_read_mmio(ap, tf);
406 else
407 ata_tf_read_pio(ap, tf);
408}
409
410/**
411 * ata_check_status_pio - Read device status reg & clear interrupt
412 * @ap: port where the device is
413 *
414 * Reads ATA taskfile status register for currently-selected device
0baab86b 415 * and return its value. This also clears pending interrupts
1da177e4
LT		 416 * from this device
417 *
418 * LOCKING:
419 * Inherited from caller.
420 */
421static u8 ata_check_status_pio(struct ata_port *ap)
422{
423 return inb(ap->ioaddr.status_addr);
424}
425
426/**
427 * ata_check_status_mmio - Read device status reg & clear interrupt
428 * @ap: port where the device is
429 *
430 * Reads ATA taskfile status register for currently-selected device
0baab86b 431 * via MMIO and return its value. This also clears pending interrupts
1da177e4
LT		 432 * from this device
433 *
434 * LOCKING:
435 * Inherited from caller.
436 */
437static u8 ata_check_status_mmio(struct ata_port *ap)
438{
439 return readb((void __iomem *) ap->ioaddr.status_addr);
440}
441
0baab86b
EF		 442
443/**
444 * ata_check_status - Read device status reg & clear interrupt
445 * @ap: port where the device is
446 *
447 * Reads ATA taskfile status register for currently-selected device
448 * and return its value. This also clears pending interrupts
449 * from this device
450 *
451 * May be used as the check_status() entry in ata_port_operations.
452 *
453 * LOCKING:
454 * Inherited from caller.
455 */
1da177e4
LT		 456u8 ata_check_status(struct ata_port *ap)
457{
458 if (ap->flags & ATA_FLAG_MMIO)
459 return ata_check_status_mmio(ap);
460 return ata_check_status_pio(ap);
461}
462
0baab86b
EF		 463
464/**
465 * ata_altstatus - Read device alternate status reg
466 * @ap: port where the device is
467 *
468 * Reads ATA taskfile alternate status register for
469 * currently-selected device and return its value.
470 *
471 * Note: may NOT be used as the check_altstatus() entry in
472 * ata_port_operations.
473 *
474 * LOCKING:
475 * Inherited from caller.
476 */
1da177e4
LT		 477u8 ata_altstatus(struct ata_port *ap)
478{
479 if (ap->ops->check_altstatus)
480 return ap->ops->check_altstatus(ap);
481
482 if (ap->flags & ATA_FLAG_MMIO)
483 return readb((void __iomem *)ap->ioaddr.altstatus_addr);
484 return inb(ap->ioaddr.altstatus_addr);
485}
486
0baab86b 487
1da177e4
LT		 488/**
489 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
490 * @tf: Taskfile to convert
491 * @fis: Buffer into which data will output
492 * @pmp: Port multiplier port
493 *
494 * Converts a standard ATA taskfile to a Serial ATA
495 * FIS structure (Register - Host to Device).
496 *
497 * LOCKING:
498 * Inherited from caller.
499 */
500
057ace5e 501void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 502{
503 fis[0] = 0x27; /* Register - Host to Device FIS */
504 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
505 bit 7 indicates Command FIS */
506 fis[2] = tf->command;
507 fis[3] = tf->feature;
508
509 fis[4] = tf->lbal;
510 fis[5] = tf->lbam;
511 fis[6] = tf->lbah;
512 fis[7] = tf->device;
513
514 fis[8] = tf->hob_lbal;
515 fis[9] = tf->hob_lbam;
516 fis[10] = tf->hob_lbah;
517 fis[11] = tf->hob_feature;
518
519 fis[12] = tf->nsect;
520 fis[13] = tf->hob_nsect;
521 fis[14] = 0;
522 fis[15] = tf->ctl;
523
524 fis[16] = 0;
525 fis[17] = 0;
526 fis[18] = 0;
527 fis[19] = 0;
528}
529
530/**
531 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
532 * @fis: Buffer from which data will be input
533 * @tf: Taskfile to output
534 *
e12a1be6 535 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 536 *
537 * LOCKING:
538 * Inherited from caller.
539 */
540
057ace5e 541void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 542{
543 tf->command = fis[2]; /* status */
544 tf->feature = fis[3]; /* error */
545
546 tf->lbal = fis[4];
547 tf->lbam = fis[5];
548 tf->lbah = fis[6];
549 tf->device = fis[7];
550
551 tf->hob_lbal = fis[8];
552 tf->hob_lbam = fis[9];
553 tf->hob_lbah = fis[10];
554
555 tf->nsect = fis[12];
556 tf->hob_nsect = fis[13];
557}
558
8cbd6df1
AL		 559static const u8 ata_rw_cmds[] = {
560 /* pio multi */
561 ATA_CMD_READ_MULTI,
562 ATA_CMD_WRITE_MULTI,
563 ATA_CMD_READ_MULTI_EXT,
564 ATA_CMD_WRITE_MULTI_EXT,
565 /* pio */
566 ATA_CMD_PIO_READ,
567 ATA_CMD_PIO_WRITE,
568 ATA_CMD_PIO_READ_EXT,
569 ATA_CMD_PIO_WRITE_EXT,
570 /* dma */
571 ATA_CMD_READ,
572 ATA_CMD_WRITE,
573 ATA_CMD_READ_EXT,
574 ATA_CMD_WRITE_EXT
575};
1da177e4
LT		 576
577/**
8cbd6df1
AL		 578 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
579 * @qc: command to examine and configure
1da177e4 580 *
8cbd6df1
AL		 581 * Examine the device configuration and tf->flags to calculate
582 * the proper read/write commands and protocol to use.
1da177e4
LT		 583 *
584 * LOCKING:
585 * caller.
586 */
8cbd6df1 587void ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 588{
8cbd6df1
AL		 589 struct ata_taskfile *tf = &qc->tf;
590 struct ata_device *dev = qc->dev;
1da177e4 591
8cbd6df1
AL		 592 int index, lba48, write;
593
594 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
595 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 596
8cbd6df1
AL		 597 if (dev->flags & ATA_DFLAG_PIO) {
598 tf->protocol = ATA_PROT_PIO;
599 index = dev->multi_count ? 0 : 4;
600 } else {
601 tf->protocol = ATA_PROT_DMA;
602 index = 8;
603 }
1da177e4 604
8cbd6df1 605 tf->command = ata_rw_cmds[index + lba48 + write];
1da177e4
LT		 606}
607
98ac62de 608static const char * const xfer_mode_str[] = {
1da177e4
LT		 609 "UDMA/16",
610 "UDMA/25",
611 "UDMA/33",
612 "UDMA/44",
613 "UDMA/66",
614 "UDMA/100",
615 "UDMA/133",
616 "UDMA7",
617 "MWDMA0",
618 "MWDMA1",
619 "MWDMA2",
620 "PIO0",
621 "PIO1",
622 "PIO2",
623 "PIO3",
624 "PIO4",
625};
626
627/**
628 * ata_udma_string - convert UDMA bit offset to string
629 * @mask: mask of bits supported; only highest bit counts.
630 *
631 * Determine string which represents the highest speed
632 * (highest bit in @udma_mask).
633 *
634 * LOCKING:
635 * None.
636 *
637 * RETURNS:
638 * Constant C string representing highest speed listed in
639 * @udma_mask, or the constant C string "<n/a>".
640 */
641
642static const char *ata_mode_string(unsigned int mask)
643{
644 int i;
645
646 for (i = 7; i >= 0; i--)
647 if (mask & (1 << i))
648 goto out;
649 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
650 if (mask & (1 << i))
651 goto out;
652 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
653 if (mask & (1 << i))
654 goto out;
655
656 return "<n/a>";
657
658out:
659 return xfer_mode_str[i];
660}
661
662/**
663 * ata_pio_devchk - PATA device presence detection
664 * @ap: ATA channel to examine
665 * @device: Device to examine (starting at zero)
666 *
667 * This technique was originally described in
668 * Hale Landis's ATADRVR (www.ata-atapi.com), and
669 * later found its way into the ATA/ATAPI spec.
670 *
671 * Write a pattern to the ATA shadow registers,
672 * and if a device is present, it will respond by
673 * correctly storing and echoing back the
674 * ATA shadow register contents.
675 *
676 * LOCKING:
677 * caller.
678 */
679
680static unsigned int ata_pio_devchk(struct ata_port *ap,
681 unsigned int device)
682{
683 struct ata_ioports *ioaddr = &ap->ioaddr;
684 u8 nsect, lbal;
685
686 ap->ops->dev_select(ap, device);
687
688 outb(0x55, ioaddr->nsect_addr);
689 outb(0xaa, ioaddr->lbal_addr);
690
691 outb(0xaa, ioaddr->nsect_addr);
692 outb(0x55, ioaddr->lbal_addr);
693
694 outb(0x55, ioaddr->nsect_addr);
695 outb(0xaa, ioaddr->lbal_addr);
696
697 nsect = inb(ioaddr->nsect_addr);
698 lbal = inb(ioaddr->lbal_addr);
699
700 if ((nsect == 0x55) && (lbal == 0xaa))
701 return 1; /* we found a device */
702
703 return 0; /* nothing found */
704}
705
706/**
707 * ata_mmio_devchk - PATA device presence detection
708 * @ap: ATA channel to examine
709 * @device: Device to examine (starting at zero)
710 *
711 * This technique was originally described in
712 * Hale Landis's ATADRVR (www.ata-atapi.com), and
713 * later found its way into the ATA/ATAPI spec.
714 *
715 * Write a pattern to the ATA shadow registers,
716 * and if a device is present, it will respond by
717 * correctly storing and echoing back the
718 * ATA shadow register contents.
719 *
720 * LOCKING:
721 * caller.
722 */
723
724static unsigned int ata_mmio_devchk(struct ata_port *ap,
725 unsigned int device)
726{
727 struct ata_ioports *ioaddr = &ap->ioaddr;
728 u8 nsect, lbal;
729
730 ap->ops->dev_select(ap, device);
731
732 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
733 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
734
735 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
736 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
737
738 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
739 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
740
741 nsect = readb((void __iomem *) ioaddr->nsect_addr);
742 lbal = readb((void __iomem *) ioaddr->lbal_addr);
743
744 if ((nsect == 0x55) && (lbal == 0xaa))
745 return 1; /* we found a device */
746
747 return 0; /* nothing found */
748}
749
750/**
751 * ata_devchk - PATA device presence detection
752 * @ap: ATA channel to examine
753 * @device: Device to examine (starting at zero)
754 *
755 * Dispatch ATA device presence detection, depending
756 * on whether we are using PIO or MMIO to talk to the
757 * ATA shadow registers.
758 *
759 * LOCKING:
760 * caller.
761 */
762
763static unsigned int ata_devchk(struct ata_port *ap,
764 unsigned int device)
765{
766 if (ap->flags & ATA_FLAG_MMIO)
767 return ata_mmio_devchk(ap, device);
768 return ata_pio_devchk(ap, device);
769}
770
771/**
772 * ata_dev_classify - determine device type based on ATA-spec signature
773 * @tf: ATA taskfile register set for device to be identified
774 *
775 * Determine from taskfile register contents whether a device is
776 * ATA or ATAPI, as per "Signature and persistence" section
777 * of ATA/PI spec (volume 1, sect 5.14).
778 *
779 * LOCKING:
780 * None.
781 *
782 * RETURNS:
783 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
784 * the event of failure.
785 */
786
057ace5e 787unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 788{
789 /* Apple's open source Darwin code hints that some devices only
790 * put a proper signature into the LBA mid/high registers,
791 * So, we only check those. It's sufficient for uniqueness.
792 */
793
794 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
795 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
796 DPRINTK("found ATA device by sig\n");
797 return ATA_DEV_ATA;
798 }
799
800 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
801 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
802 DPRINTK("found ATAPI device by sig\n");
803 return ATA_DEV_ATAPI;
804 }
805
806 DPRINTK("unknown device\n");
807 return ATA_DEV_UNKNOWN;
808}
809
810/**
811 * ata_dev_try_classify - Parse returned ATA device signature
812 * @ap: ATA channel to examine
813 * @device: Device to examine (starting at zero)
814 *
815 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
816 * an ATA/ATAPI-defined set of values is placed in the ATA
817 * shadow registers, indicating the results of device detection
818 * and diagnostics.
819 *
820 * Select the ATA device, and read the values from the ATA shadow
821 * registers. Then parse according to the Error register value,
822 * and the spec-defined values examined by ata_dev_classify().
823 *
824 * LOCKING:
825 * caller.
826 */
827
828static u8 ata_dev_try_classify(struct ata_port *ap, unsigned int device)
829{
830 struct ata_device *dev = &ap->device[device];
831 struct ata_taskfile tf;
832 unsigned int class;
833 u8 err;
834
835 ap->ops->dev_select(ap, device);
836
837 memset(&tf, 0, sizeof(tf));
838
1da177e4 839 ap->ops->tf_read(ap, &tf);
0169e284 840 err = tf.feature;
1da177e4
LT		 841
842 dev->class = ATA_DEV_NONE;
843
844 /* see if device passed diags */
845 if (err == 1)
846 /* do nothing */ ;
847 else if ((device == 0) && (err == 0x81))
848 /* do nothing */ ;
849 else
850 return err;
851
852 /* determine if device if ATA or ATAPI */
853 class = ata_dev_classify(&tf);
854 if (class == ATA_DEV_UNKNOWN)
855 return err;
856 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
857 return err;
858
859 dev->class = class;
860
861 return err;
862}
863
864/**
865 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
866 * @id: IDENTIFY DEVICE results we will examine
867 * @s: string into which data is output
868 * @ofs: offset into identify device page
869 * @len: length of string to return. must be an even number.
870 *
871 * The strings in the IDENTIFY DEVICE page are broken up into
872 * 16-bit chunks. Run through the string, and output each
873 * 8-bit chunk linearly, regardless of platform.
874 *
875 * LOCKING:
876 * caller.
877 */
878
057ace5e 879void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT		 880 unsigned int ofs, unsigned int len)
881{
882 unsigned int c;
883
884 while (len > 0) {
885 c = id[ofs] >> 8;
886 *s = c;
887 s++;
888
889 c = id[ofs] & 0xff;
890 *s = c;
891 s++;
892
893 ofs++;
894 len -= 2;
895 }
896}
897
0baab86b
EF		 898
899/**
900 * ata_noop_dev_select - Select device 0/1 on ATA bus
901 * @ap: ATA channel to manipulate
902 * @device: ATA device (numbered from zero) to select
903 *
904 * This function performs no actual function.
905 *
906 * May be used as the dev_select() entry in ata_port_operations.
907 *
908 * LOCKING:
909 * caller.
910 */
1da177e4
LT		 911void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
912{
913}
914
0baab86b 915
1da177e4
LT		 916/**
917 * ata_std_dev_select - Select device 0/1 on ATA bus
918 * @ap: ATA channel to manipulate
919 * @device: ATA device (numbered from zero) to select
920 *
921 * Use the method defined in the ATA specification to
922 * make either device 0, or device 1, active on the
0baab86b
EF		 923 * ATA channel. Works with both PIO and MMIO.
924 *
925 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 926 *
927 * LOCKING:
928 * caller.
929 */
930
931void ata_std_dev_select (struct ata_port *ap, unsigned int device)
932{
933 u8 tmp;
934
935 if (device == 0)
936 tmp = ATA_DEVICE_OBS;
937 else
938 tmp = ATA_DEVICE_OBS | ATA_DEV1;
939
940 if (ap->flags & ATA_FLAG_MMIO) {
941 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
942 } else {
943 outb(tmp, ap->ioaddr.device_addr);
944 }
945 ata_pause(ap); /* needed; also flushes, for mmio */
946}
947
948/**
949 * ata_dev_select - Select device 0/1 on ATA bus
950 * @ap: ATA channel to manipulate
951 * @device: ATA device (numbered from zero) to select
952 * @wait: non-zero to wait for Status register BSY bit to clear
953 * @can_sleep: non-zero if context allows sleeping
954 *
955 * Use the method defined in the ATA specification to
956 * make either device 0, or device 1, active on the
957 * ATA channel.
958 *
959 * This is a high-level version of ata_std_dev_select(),
960 * which additionally provides the services of inserting
961 * the proper pauses and status polling, where needed.
962 *
963 * LOCKING:
964 * caller.
965 */
966
967void ata_dev_select(struct ata_port *ap, unsigned int device,
968 unsigned int wait, unsigned int can_sleep)
969{
970 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
971 ap->id, device, wait);
972
973 if (wait)
974 ata_wait_idle(ap);
975
976 ap->ops->dev_select(ap, device);
977
978 if (wait) {
979 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
980 msleep(150);
981 ata_wait_idle(ap);
982 }
983}
984
985/**
986 * ata_dump_id - IDENTIFY DEVICE info debugging output
987 * @dev: Device whose IDENTIFY DEVICE page we will dump
988 *
989 * Dump selected 16-bit words from a detected device's
990 * IDENTIFY PAGE page.
991 *
992 * LOCKING:
993 * caller.
994 */
995
057ace5e 996static inline void ata_dump_id(const struct ata_device *dev)
1da177e4
LT		 997{
998 DPRINTK("49==0x%04x "
999 "53==0x%04x "
1000 "63==0x%04x "
1001 "64==0x%04x "
1002 "75==0x%04x \n",
1003 dev->id[49],
1004 dev->id[53],
1005 dev->id[63],
1006 dev->id[64],
1007 dev->id[75]);
1008 DPRINTK("80==0x%04x "
1009 "81==0x%04x "
1010 "82==0x%04x "
1011 "83==0x%04x "
1012 "84==0x%04x \n",
1013 dev->id[80],
1014 dev->id[81],
1015 dev->id[82],
1016 dev->id[83],
1017 dev->id[84]);
1018 DPRINTK("88==0x%04x "
1019 "93==0x%04x\n",
1020 dev->id[88],
1021 dev->id[93]);
1022}
1023
11e29e21
AC		 1024/*
1025 * Compute the PIO modes available for this device. This is not as
1026 * trivial as it seems if we must consider early devices correctly.
1027 *
1028 * FIXME: pre IDE drive timing (do we care ?).
1029 */
1030
057ace5e 1031static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC		 1032{
1033 u16 modes;
1034
1035 /* Usual case. Word 53 indicates word 88 is valid */
1036 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 2)) {
1037 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
1038 modes <<= 3;
1039 modes |= 0x7;
1040 return modes;
1041 }
1042
1043 /* If word 88 isn't valid then Word 51 holds the PIO timing number
1044 for the maximum. Turn it into a mask and return it */
1045 modes = (2 << (adev->id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ;
1046 return modes;
1047}
1048
a2a7a662
TH		 1049struct ata_exec_internal_arg {
1050 unsigned int err_mask;
1051 struct ata_taskfile *tf;
1052 struct completion *waiting;
1053};
1054
1055int ata_qc_complete_internal(struct ata_queued_cmd *qc)
1056{
1057 struct ata_exec_internal_arg *arg = qc->private_data;
1058 struct completion *waiting = arg->waiting;
1059
1060 if (!(qc->err_mask & ~AC_ERR_DEV))
1061 qc->ap->ops->tf_read(qc->ap, arg->tf);
1062 arg->err_mask = qc->err_mask;
1063 arg->waiting = NULL;
1064 complete(waiting);
1065
1066 return 0;
1067}
1068
1069/**
1070 * ata_exec_internal - execute libata internal command
1071 * @ap: Port to which the command is sent
1072 * @dev: Device to which the command is sent
1073 * @tf: Taskfile registers for the command and the result
1074 * @dma_dir: Data tranfer direction of the command
1075 * @buf: Data buffer of the command
1076 * @buflen: Length of data buffer
1077 *
1078 * Executes libata internal command with timeout. @tf contains
1079 * command on entry and result on return. Timeout and error
1080 * conditions are reported via return value. No recovery action
1081 * is taken after a command times out. It's caller's duty to
1082 * clean up after timeout.
1083 *
1084 * LOCKING:
1085 * None. Should be called with kernel context, might sleep.
1086 */
1087
1088static unsigned
1089ata_exec_internal(struct ata_port *ap, struct ata_device *dev,
1090 struct ata_taskfile *tf,
1091 int dma_dir, void *buf, unsigned int buflen)
1092{
1093 u8 command = tf->command;
1094 struct ata_queued_cmd *qc;
1095 DECLARE_COMPLETION(wait);
1096 unsigned long flags;
1097 struct ata_exec_internal_arg arg;
1098
1099 spin_lock_irqsave(&ap->host_set->lock, flags);
1100
1101 qc = ata_qc_new_init(ap, dev);
1102 BUG_ON(qc == NULL);
1103
1104 qc->tf = *tf;
1105 qc->dma_dir = dma_dir;
1106 if (dma_dir != DMA_NONE) {
1107 ata_sg_init_one(qc, buf, buflen);
1108 qc->nsect = buflen / ATA_SECT_SIZE;
1109 }
1110
1111 arg.waiting = &wait;
1112 arg.tf = tf;
1113 qc->private_data = &arg;
1114 qc->complete_fn = ata_qc_complete_internal;
1115
1116 if (ata_qc_issue(qc))
1117 goto issue_fail;
1118
1119 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1120
1121 if (!wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL)) {
1122 spin_lock_irqsave(&ap->host_set->lock, flags);
1123
1124 /* We're racing with irq here. If we lose, the
1125 * following test prevents us from completing the qc
1126 * again. If completion irq occurs after here but
1127 * before the caller cleans up, it will result in a
1128 * spurious interrupt. We can live with that.
1129 */
1130 if (arg.waiting) {
1131 qc->err_mask = AC_ERR_OTHER;
1132 ata_qc_complete(qc);
1133 printk(KERN_WARNING "ata%u: qc timeout (cmd 0x%x)\n",
1134 ap->id, command);
1135 }
1136
1137 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1138 }
1139
1140 return arg.err_mask;
1141
1142 issue_fail:
1143 ata_qc_free(qc);
1144 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1145 return AC_ERR_OTHER;
1146}
1147
1da177e4
LT		 1148/**
1149 * ata_dev_identify - obtain IDENTIFY x DEVICE page
1150 * @ap: port on which device we wish to probe resides
1151 * @device: device bus address, starting at zero
1152 *
1153 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
1154 * command, and read back the 512-byte device information page.
1155 * The device information page is fed to us via the standard
1156 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
1157 * using standard PIO-IN paths)
1158 *
1159 * After reading the device information page, we use several
1160 * bits of information from it to initialize data structures
1161 * that will be used during the lifetime of the ata_device.
1162 * Other data from the info page is used to disqualify certain
1163 * older ATA devices we do not wish to support.
1164 *
1165 * LOCKING:
1166 * Inherited from caller. Some functions called by this function
1167 * obtain the host_set lock.
1168 */
1169
1170static void ata_dev_identify(struct ata_port *ap, unsigned int device)
1171{
1172 struct ata_device *dev = &ap->device[device];
8bf62ece 1173 unsigned int major_version;
1da177e4
LT		 1174 u16 tmp;
1175 unsigned long xfer_modes;
1da177e4 1176 unsigned int using_edd;
a0123703
TH		 1177 struct ata_taskfile tf;
1178 unsigned int err_mask;
1da177e4
LT		 1179 int rc;
1180
1181 if (!ata_dev_present(dev)) {
1182 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
1183 ap->id, device);
1184 return;
1185 }
1186
1187 if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
1188 using_edd = 0;
1189 else
1190 using_edd = 1;
1191
1192 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
1193
1194 assert (dev->class == ATA_DEV_ATA || dev->class == ATA_DEV_ATAPI ||
1195 dev->class == ATA_DEV_NONE);
1196
1197 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
1198
1da177e4 1199retry:
a0123703
TH		 1200 ata_tf_init(ap, &tf, device);
1201
1da177e4 1202 if (dev->class == ATA_DEV_ATA) {
a0123703 1203 tf.command = ATA_CMD_ID_ATA;
1da177e4
LT		 1204 DPRINTK("do ATA identify\n");
1205 } else {
a0123703 1206 tf.command = ATA_CMD_ID_ATAPI;
1da177e4
LT		 1207 DPRINTK("do ATAPI identify\n");
1208 }
1209
a0123703 1210 tf.protocol = ATA_PROT_PIO;
1da177e4 1211
a0123703
TH		 1212 err_mask = ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
1213 dev->id, sizeof(dev->id));
1da177e4 1214
a0123703
TH		 1215 if (err_mask) {
1216 if (err_mask & ~AC_ERR_DEV)
1217 goto err_out;
0169e284 1218
1da177e4
LT		 1219 /*
1220 * arg! EDD works for all test cases, but seems to return
1221 * the ATA signature for some ATAPI devices. Until the
1222 * reason for this is found and fixed, we fix up the mess
1223 * here. If IDENTIFY DEVICE returns command aborted
1224 * (as ATAPI devices do), then we issue an
1225 * IDENTIFY PACKET DEVICE.
1226 *
1227 * ATA software reset (SRST, the default) does not appear
1228 * to have this problem.
1229 */
7c398335 1230 if ((using_edd) && (dev->class == ATA_DEV_ATA)) {
a0123703 1231 u8 err = tf.feature;
1da177e4
LT		 1232 if (err & ATA_ABORTED) {
1233 dev->class = ATA_DEV_ATAPI;
1da177e4
LT		 1234 goto retry;
1235 }
1236 }
1237 goto err_out;
1238 }
1239
1240 swap_buf_le16(dev->id, ATA_ID_WORDS);
1241
1242 /* print device capabilities */
1243 printk(KERN_DEBUG "ata%u: dev %u cfg "
1244 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
1245 ap->id, device, dev->id[49],
1246 dev->id[82], dev->id[83], dev->id[84],
1247 dev->id[85], dev->id[86], dev->id[87],
1248 dev->id[88]);
1249
1250 /*
1251 * common ATA, ATAPI feature tests
1252 */
1253
8bf62ece
AL		 1254 /* we require DMA support (bits 8 of word 49) */
1255 if (!ata_id_has_dma(dev->id)) {
1256 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT		 1257 goto err_out_nosup;
1258 }
1259
1260 /* quick-n-dirty find max transfer mode; for printk only */
1261 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
1262 if (!xfer_modes)
1263 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC		 1264 if (!xfer_modes)
1265 xfer_modes = ata_pio_modes(dev);
1da177e4
LT		 1266
1267 ata_dump_id(dev);
1268
1269 /* ATA-specific feature tests */
1270 if (dev->class == ATA_DEV_ATA) {
1271 if (!ata_id_is_ata(dev->id)) /* sanity check */
1272 goto err_out_nosup;
1273
8bf62ece 1274 /* get major version */
1da177e4 1275 tmp = dev->id[ATA_ID_MAJOR_VER];
8bf62ece
AL		 1276 for (major_version = 14; major_version >= 1; major_version--)
1277 if (tmp & (1 << major_version))
1da177e4
LT		 1278 break;
1279
8bf62ece
AL		 1280 /*
1281 * The exact sequence expected by certain pre-ATA4 drives is:
1282 * SRST RESET
1283 * IDENTIFY
1284 * INITIALIZE DEVICE PARAMETERS
1285 * anything else..
1286 * Some drives were very specific about that exact sequence.
1287 */
59a10b17 1288 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL		 1289 ata_dev_init_params(ap, dev);
1290
59a10b17
AL		 1291 /* current CHS translation info (id[53-58]) might be
1292 * changed. reread the identify device info.
1293 */
1294 ata_dev_reread_id(ap, dev);
1295 }
1296
8bf62ece
AL		 1297 if (ata_id_has_lba(dev->id)) {
1298 dev->flags |= ATA_DFLAG_LBA;
1299
1300 if (ata_id_has_lba48(dev->id)) {
1301 dev->flags |= ATA_DFLAG_LBA48;
1302 dev->n_sectors = ata_id_u64(dev->id, 100);
1303 } else {
1304 dev->n_sectors = ata_id_u32(dev->id, 60);
1305 }
1306
1307 /* print device info to dmesg */
1308 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1309 ap->id, device,
1310 major_version,
1311 ata_mode_string(xfer_modes),
1312 (unsigned long long)dev->n_sectors,
1313 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1314 } else {
1315 /* CHS */
1316
1317 /* Default translation */
1318 dev->cylinders = dev->id[1];
1319 dev->heads = dev->id[3];
1320 dev->sectors = dev->id[6];
1321 dev->n_sectors = dev->cylinders * dev->heads * dev->sectors;
1322
1323 if (ata_id_current_chs_valid(dev->id)) {
1324 /* Current CHS translation is valid. */
1325 dev->cylinders = dev->id[54];
1326 dev->heads = dev->id[55];
1327 dev->sectors = dev->id[56];
1328
1329 dev->n_sectors = ata_id_u32(dev->id, 57);
1330 }
1331
1332 /* print device info to dmesg */
1333 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1334 ap->id, device,
1335 major_version,
1336 ata_mode_string(xfer_modes),
1337 (unsigned long long)dev->n_sectors,
1338 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1339
1da177e4
LT		 1340 }
1341
1342 ap->host->max_cmd_len = 16;
1da177e4
LT		 1343 }
1344
1345 /* ATAPI-specific feature tests */
2c13b7ce 1346 else if (dev->class == ATA_DEV_ATAPI) {
1da177e4
LT		 1347 if (ata_id_is_ata(dev->id)) /* sanity check */
1348 goto err_out_nosup;
1349
1350 rc = atapi_cdb_len(dev->id);
1351 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1352 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1353 goto err_out_nosup;
1354 }
1355 ap->cdb_len = (unsigned int) rc;
1356 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1357
1358 /* print device info to dmesg */
1359 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1360 ap->id, device,
1361 ata_mode_string(xfer_modes));
1362 }
1363
1364 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1365 return;
1366
1367err_out_nosup:
1368 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1369 ap->id, device);
1370err_out:
1371 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1372 DPRINTK("EXIT, err\n");
1373}
1374
6f2f3812 1375
057ace5e 1376static inline u8 ata_dev_knobble(const struct ata_port *ap)
6f2f3812
BC		 1377{
1378 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id)));
1379}
1380
1381/**
1382 * ata_dev_config - Run device specific handlers and check for
1383 * SATA->PATA bridges
8a60a071 1384 * @ap: Bus
6f2f3812
BC		 1385 * @i: Device
1386 *
1387 * LOCKING:
1388 */
8a60a071 1389
6f2f3812
BC		 1390void ata_dev_config(struct ata_port *ap, unsigned int i)
1391{
1392 /* limit bridge transfers to udma5, 200 sectors */
1393 if (ata_dev_knobble(ap)) {
1394 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1395 ap->id, ap->device->devno);
1396 ap->udma_mask &= ATA_UDMA5;
1397 ap->host->max_sectors = ATA_MAX_SECTORS;
1398 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
1399 ap->device->flags |= ATA_DFLAG_LOCK_SECTORS;
1400 }
1401
1402 if (ap->ops->dev_config)
1403 ap->ops->dev_config(ap, &ap->device[i]);
1404}
1405
1da177e4
LT		 1406/**
1407 * ata_bus_probe - Reset and probe ATA bus
1408 * @ap: Bus to probe
1409 *
0cba632b
JG		 1410 * Master ATA bus probing function. Initiates a hardware-dependent
1411 * bus reset, then attempts to identify any devices found on
1412 * the bus.
1413 *
1da177e4 1414 * LOCKING:
0cba632b 1415 * PCI/etc. bus probe sem.
1da177e4
LT		 1416 *
1417 * RETURNS:
1418 * Zero on success, non-zero on error.
1419 */
1420
1421static int ata_bus_probe(struct ata_port *ap)
1422{
1423 unsigned int i, found = 0;
1424
1425 ap->ops->phy_reset(ap);
1426 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1427 goto err_out;
1428
1429 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1430 ata_dev_identify(ap, i);
1431 if (ata_dev_present(&ap->device[i])) {
1432 found = 1;
6f2f3812 1433 ata_dev_config(ap,i);
1da177e4
LT		 1434 }
1435 }
1436
1437 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1438 goto err_out_disable;
1439
1440 ata_set_mode(ap);
1441 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1442 goto err_out_disable;
1443
1444 return 0;
1445
1446err_out_disable:
1447 ap->ops->port_disable(ap);
1448err_out:
1449 return -1;
1450}
1451
1452/**
0cba632b
JG		 1453 * ata_port_probe - Mark port as enabled
1454 * @ap: Port for which we indicate enablement
1da177e4 1455 *
0cba632b
JG		 1456 * Modify @ap data structure such that the system
1457 * thinks that the entire port is enabled.
1458 *
1459 * LOCKING: host_set lock, or some other form of
1460 * serialization.
1da177e4
LT		 1461 */
1462
1463void ata_port_probe(struct ata_port *ap)
1464{
1465 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1466}
1467
1468/**
780a87f7
JG		 1469 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1470 * @ap: SATA port associated with target SATA PHY.
1da177e4 1471 *
780a87f7
JG		 1472 * This function issues commands to standard SATA Sxxx
1473 * PHY registers, to wake up the phy (and device), and
1474 * clear any reset condition.
1da177e4
LT		 1475 *
1476 * LOCKING:
0cba632b 1477 * PCI/etc. bus probe sem.
1da177e4
LT		 1478 *
1479 */
1480void __sata_phy_reset(struct ata_port *ap)
1481{
1482 u32 sstatus;
1483 unsigned long timeout = jiffies + (HZ * 5);
1484
1485 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1486 /* issue phy wake/reset */
1487 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1488 /* Couldn't find anything in SATA I/II specs, but
1489 * AHCI-1.1 10.4.2 says at least 1 ms. */
1490 mdelay(1);
1da177e4 1491 }
cdcca89e 1492 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1493
1494 /* wait for phy to become ready, if necessary */
1495 do {
1496 msleep(200);
1497 sstatus = scr_read(ap, SCR_STATUS);
1498 if ((sstatus & 0xf) != 1)
1499 break;
1500 } while (time_before(jiffies, timeout));
1501
1502 /* TODO: phy layer with polling, timeouts, etc. */
656563e3
JG		 1503 sstatus = scr_read(ap, SCR_STATUS);
1504 if (sata_dev_present(ap)) {
1505 const char *speed;
1506 u32 tmp;
1507
1508 tmp = (sstatus >> 4) & 0xf;
1509 if (tmp & (1 << 0))
1510 speed = "1.5";
1511 else if (tmp & (1 << 1))
1512 speed = "3.0";
1513 else
1514 speed = "<unknown>";
1515 printk(KERN_INFO "ata%u: SATA link up %s Gbps (SStatus %X)\n",
1516 ap->id, speed, sstatus);
1da177e4 1517 ata_port_probe(ap);
656563e3
JG		 1518 } else {
1519 printk(KERN_INFO "ata%u: SATA link down (SStatus %X)\n",
1da177e4
LT		 1520 ap->id, sstatus);
1521 ata_port_disable(ap);
1522 }
1523
1524 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1525 return;
1526
1527 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1528 ata_port_disable(ap);
1529 return;
1530 }
1531
1532 ap->cbl = ATA_CBL_SATA;
1533}
1534
1535/**
780a87f7
JG		 1536 * sata_phy_reset - Reset SATA bus.
1537 * @ap: SATA port associated with target SATA PHY.
1da177e4 1538 *
780a87f7
JG		 1539 * This function resets the SATA bus, and then probes
1540 * the bus for devices.
1da177e4
LT		 1541 *
1542 * LOCKING:
0cba632b 1543 * PCI/etc. bus probe sem.
1da177e4
LT		 1544 *
1545 */
1546void sata_phy_reset(struct ata_port *ap)
1547{
1548 __sata_phy_reset(ap);
1549 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1550 return;
1551 ata_bus_reset(ap);
1552}
1553
1554/**
780a87f7
JG		 1555 * ata_port_disable - Disable port.
1556 * @ap: Port to be disabled.
1da177e4 1557 *
780a87f7
JG		 1558 * Modify @ap data structure such that the system
1559 * thinks that the entire port is disabled, and should
1560 * never attempt to probe or communicate with devices
1561 * on this port.
1562 *
1563 * LOCKING: host_set lock, or some other form of
1564 * serialization.
1da177e4
LT		 1565 */
1566
1567void ata_port_disable(struct ata_port *ap)
1568{
1569 ap->device[0].class = ATA_DEV_NONE;
1570 ap->device[1].class = ATA_DEV_NONE;
1571 ap->flags |= ATA_FLAG_PORT_DISABLED;
1572}
1573
452503f9
AC		 1574/*
1575 * This mode timing computation functionality is ported over from
1576 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1577 */
1578/*
1579 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1580 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1581 * for PIO 5, which is a nonstandard extension and UDMA6, which
1582 * is currently supported only by Maxtor drives.
1583 */
1584
1585static const struct ata_timing ata_timing[] = {
1586
1587 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1588 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1589 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1590 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1591
1592 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1593 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1594 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1595
1596/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1597
1598 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1599 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1600 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1601
1602 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1603 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1604 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1605
1606/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1607 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1608 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1609
1610 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1611 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1612 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1613
1614/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1615
1616 { 0xFF }
1617};
1618
1619#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1620#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1621
1622static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1623{
1624 q->setup = EZ(t->setup * 1000, T);
1625 q->act8b = EZ(t->act8b * 1000, T);
1626 q->rec8b = EZ(t->rec8b * 1000, T);
1627 q->cyc8b = EZ(t->cyc8b * 1000, T);
1628 q->active = EZ(t->active * 1000, T);
1629 q->recover = EZ(t->recover * 1000, T);
1630 q->cycle = EZ(t->cycle * 1000, T);
1631 q->udma = EZ(t->udma * 1000, UT);
1632}
1633
1634void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1635 struct ata_timing *m, unsigned int what)
1636{
1637 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1638 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1639 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1640 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1641 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1642 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1643 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1644 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1645}
1646
1647static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1648{
1649 const struct ata_timing *t;
1650
1651 for (t = ata_timing; t->mode != speed; t++)
91190758 1652 if (t->mode == 0xFF)
452503f9
AC		 1653 return NULL;
1654 return t;
1655}
1656
1657int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1658 struct ata_timing *t, int T, int UT)
1659{
1660 const struct ata_timing *s;
1661 struct ata_timing p;
1662
1663 /*
1664 * Find the mode.
75b1f2f8 1665 */
452503f9
AC		 1666
1667 if (!(s = ata_timing_find_mode(speed)))
1668 return -EINVAL;
1669
75b1f2f8
AL		 1670 memcpy(t, s, sizeof(*s));
1671
452503f9
AC		 1672 /*
1673 * If the drive is an EIDE drive, it can tell us it needs extended
1674 * PIO/MW_DMA cycle timing.
1675 */
1676
1677 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1678 memset(&p, 0, sizeof(p));
1679 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1680 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1681 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1682 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1683 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1684 }
1685 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1686 }
1687
1688 /*
1689 * Convert the timing to bus clock counts.
1690 */
1691
75b1f2f8 1692 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1693
1694 /*
1695 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
1696 * and some other commands. We have to ensure that the DMA cycle timing is
1697 * slower/equal than the fastest PIO timing.
1698 */
1699
1700 if (speed > XFER_PIO_4) {
1701 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1702 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1703 }
1704
1705 /*
1706 * Lenghten active & recovery time so that cycle time is correct.
1707 */
1708
1709 if (t->act8b + t->rec8b < t->cyc8b) {
1710 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1711 t->rec8b = t->cyc8b - t->act8b;
1712 }
1713
1714 if (t->active + t->recover < t->cycle) {
1715 t->active += (t->cycle - (t->active + t->recover)) / 2;
1716 t->recover = t->cycle - t->active;
1717 }
1718
1719 return 0;
1720}
1721
057ace5e 1722static const struct {
1da177e4
LT		 1723 unsigned int shift;
1724 u8 base;
1725} xfer_mode_classes[] = {
1726 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1727 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1728 { ATA_SHIFT_PIO, XFER_PIO_0 },
1729};
1730
1731static inline u8 base_from_shift(unsigned int shift)
1732{
1733 int i;
1734
1735 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1736 if (xfer_mode_classes[i].shift == shift)
1737 return xfer_mode_classes[i].base;
1738
1739 return 0xff;
1740}
1741
1742static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1743{
1744 int ofs, idx;
1745 u8 base;
1746
1747 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1748 return;
1749
1750 if (dev->xfer_shift == ATA_SHIFT_PIO)
1751 dev->flags |= ATA_DFLAG_PIO;
1752
1753 ata_dev_set_xfermode(ap, dev);
1754
1755 base = base_from_shift(dev->xfer_shift);
1756 ofs = dev->xfer_mode - base;
1757 idx = ofs + dev->xfer_shift;
1758 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1759
1760 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1761 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1762
1763 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1764 ap->id, dev->devno, xfer_mode_str[idx]);
1765}
1766
1767static int ata_host_set_pio(struct ata_port *ap)
1768{
1769 unsigned int mask;
1770 int x, i;
1771 u8 base, xfer_mode;
1772
1773 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1774 x = fgb(mask);
1775 if (x < 0) {
1776 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1777 return -1;
1778 }
1779
1780 base = base_from_shift(ATA_SHIFT_PIO);
1781 xfer_mode = base + x;
1782
1783 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1784 (int)base, (int)xfer_mode, mask, x);
1785
1786 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1787 struct ata_device *dev = &ap->device[i];
1788 if (ata_dev_present(dev)) {
1789 dev->pio_mode = xfer_mode;
1790 dev->xfer_mode = xfer_mode;
1791 dev->xfer_shift = ATA_SHIFT_PIO;
1792 if (ap->ops->set_piomode)
1793 ap->ops->set_piomode(ap, dev);
1794 }
1795 }
1796
1797 return 0;
1798}
1799
1800static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1801 unsigned int xfer_shift)
1802{
1803 int i;
1804
1805 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1806 struct ata_device *dev = &ap->device[i];
1807 if (ata_dev_present(dev)) {
1808 dev->dma_mode = xfer_mode;
1809 dev->xfer_mode = xfer_mode;
1810 dev->xfer_shift = xfer_shift;
1811 if (ap->ops->set_dmamode)
1812 ap->ops->set_dmamode(ap, dev);
1813 }
1814 }
1815}
1816
1817/**
1818 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1819 * @ap: port on which timings will be programmed
1820 *
780a87f7
JG		 1821 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1822 *
1da177e4 1823 * LOCKING:
0cba632b 1824 * PCI/etc. bus probe sem.
1da177e4
LT		 1825 *
1826 */
1827static void ata_set_mode(struct ata_port *ap)
1828{
8cbd6df1 1829 unsigned int xfer_shift;
1da177e4
LT		 1830 u8 xfer_mode;
1831 int rc;
1832
1833 /* step 1: always set host PIO timings */
1834 rc = ata_host_set_pio(ap);
1835 if (rc)
1836 goto err_out;
1837
1838 /* step 2: choose the best data xfer mode */
1839 xfer_mode = xfer_shift = 0;
1840 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1841 if (rc)
1842 goto err_out;
1843
1844 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1845 if (xfer_shift != ATA_SHIFT_PIO)
1846 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1847
1848 /* step 4: update devices' xfer mode */
1849 ata_dev_set_mode(ap, &ap->device[0]);
1850 ata_dev_set_mode(ap, &ap->device[1]);
1851
1852 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1853 return;
1854
1855 if (ap->ops->post_set_mode)
1856 ap->ops->post_set_mode(ap);
1857
1da177e4
LT		 1858 return;
1859
1860err_out:
1861 ata_port_disable(ap);
1862}
1863
1864/**
1865 * ata_busy_sleep - sleep until BSY clears, or timeout
1866 * @ap: port containing status register to be polled
1867 * @tmout_pat: impatience timeout
1868 * @tmout: overall timeout
1869 *
780a87f7
JG		 1870 * Sleep until ATA Status register bit BSY clears,
1871 * or a timeout occurs.
1872 *
1873 * LOCKING: None.
1da177e4
LT		 1874 *
1875 */
1876
1877static unsigned int ata_busy_sleep (struct ata_port *ap,
1878 unsigned long tmout_pat,
1879 unsigned long tmout)
1880{
1881 unsigned long timer_start, timeout;
1882 u8 status;
1883
1884 status = ata_busy_wait(ap, ATA_BUSY, 300);
1885 timer_start = jiffies;
1886 timeout = timer_start + tmout_pat;
1887 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1888 msleep(50);
1889 status = ata_busy_wait(ap, ATA_BUSY, 3);
1890 }
1891
1892 if (status & ATA_BUSY)
1893 printk(KERN_WARNING "ata%u is slow to respond, "
1894 "please be patient\n", ap->id);
1895
1896 timeout = timer_start + tmout;
1897 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1898 msleep(50);
1899 status = ata_chk_status(ap);
1900 }
1901
1902 if (status & ATA_BUSY) {
1903 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1904 ap->id, tmout / HZ);
1905 return 1;
1906 }
1907
1908 return 0;
1909}
1910
1911static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1912{
1913 struct ata_ioports *ioaddr = &ap->ioaddr;
1914 unsigned int dev0 = devmask & (1 << 0);
1915 unsigned int dev1 = devmask & (1 << 1);
1916 unsigned long timeout;
1917
1918 /* if device 0 was found in ata_devchk, wait for its
1919 * BSY bit to clear
1920 */
1921 if (dev0)
1922 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1923
1924 /* if device 1 was found in ata_devchk, wait for
1925 * register access, then wait for BSY to clear
1926 */
1927 timeout = jiffies + ATA_TMOUT_BOOT;
1928 while (dev1) {
1929 u8 nsect, lbal;
1930
1931 ap->ops->dev_select(ap, 1);
1932 if (ap->flags & ATA_FLAG_MMIO) {
1933 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1934 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1935 } else {
1936 nsect = inb(ioaddr->nsect_addr);
1937 lbal = inb(ioaddr->lbal_addr);
1938 }
1939 if ((nsect == 1) && (lbal == 1))
1940 break;
1941 if (time_after(jiffies, timeout)) {
1942 dev1 = 0;
1943 break;
1944 }
1945 msleep(50); /* give drive a breather */
1946 }
1947 if (dev1)
1948 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1949
1950 /* is all this really necessary? */
1951 ap->ops->dev_select(ap, 0);
1952 if (dev1)
1953 ap->ops->dev_select(ap, 1);
1954 if (dev0)
1955 ap->ops->dev_select(ap, 0);
1956}
1957
1958/**
0cba632b
JG		 1959 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1960 * @ap: Port to reset and probe
1961 *
1962 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1963 * probe the bus. Not often used these days.
1da177e4
LT		 1964 *
1965 * LOCKING:
0cba632b 1966 * PCI/etc. bus probe sem.
e5338254 1967 * Obtains host_set lock.
1da177e4
LT		 1968 *
1969 */
1970
1971static unsigned int ata_bus_edd(struct ata_port *ap)
1972{
1973 struct ata_taskfile tf;
e5338254 1974 unsigned long flags;
1da177e4
LT		 1975
1976 /* set up execute-device-diag (bus reset) taskfile */
1977 /* also, take interrupts to a known state (disabled) */
1978 DPRINTK("execute-device-diag\n");
1979 ata_tf_init(ap, &tf, 0);
1980 tf.ctl |= ATA_NIEN;
1981 tf.command = ATA_CMD_EDD;
1982 tf.protocol = ATA_PROT_NODATA;
1983
1984 /* do bus reset */
e5338254 1985 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 1986 ata_tf_to_host(ap, &tf);
e5338254 1987 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 1988
1989 /* spec says at least 2ms. but who knows with those
1990 * crazy ATAPI devices...
1991 */
1992 msleep(150);
1993
1994 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1995}
1996
1997static unsigned int ata_bus_softreset(struct ata_port *ap,
1998 unsigned int devmask)
1999{
2000 struct ata_ioports *ioaddr = &ap->ioaddr;
2001
2002 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
2003
2004 /* software reset. causes dev0 to be selected */
2005 if (ap->flags & ATA_FLAG_MMIO) {
2006 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2007 udelay(20); /* FIXME: flush */
2008 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
2009 udelay(20); /* FIXME: flush */
2010 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2011 } else {
2012 outb(ap->ctl, ioaddr->ctl_addr);
2013 udelay(10);
2014 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2015 udelay(10);
2016 outb(ap->ctl, ioaddr->ctl_addr);
2017 }
2018
2019 /* spec mandates ">= 2ms" before checking status.
2020 * We wait 150ms, because that was the magic delay used for
2021 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
2022 * between when the ATA command register is written, and then
2023 * status is checked. Because waiting for "a while" before
2024 * checking status is fine, post SRST, we perform this magic
2025 * delay here as well.
2026 */
2027 msleep(150);
2028
2029 ata_bus_post_reset(ap, devmask);
2030
2031 return 0;
2032}
2033
2034/**
2035 * ata_bus_reset - reset host port and associated ATA channel
2036 * @ap: port to reset
2037 *
2038 * This is typically the first time we actually start issuing
2039 * commands to the ATA channel. We wait for BSY to clear, then
2040 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2041 * result. Determine what devices, if any, are on the channel
2042 * by looking at the device 0/1 error register. Look at the signature
2043 * stored in each device's taskfile registers, to determine if
2044 * the device is ATA or ATAPI.
2045 *
2046 * LOCKING:
0cba632b
JG		 2047 * PCI/etc. bus probe sem.
2048 * Obtains host_set lock.
1da177e4
LT		 2049 *
2050 * SIDE EFFECTS:
2051 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
2052 */
2053
2054void ata_bus_reset(struct ata_port *ap)
2055{
2056 struct ata_ioports *ioaddr = &ap->ioaddr;
2057 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2058 u8 err;
2059 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
2060
2061 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2062
2063 /* determine if device 0/1 are present */
2064 if (ap->flags & ATA_FLAG_SATA_RESET)
2065 dev0 = 1;
2066 else {
2067 dev0 = ata_devchk(ap, 0);
2068 if (slave_possible)
2069 dev1 = ata_devchk(ap, 1);
2070 }
2071
2072 if (dev0)
2073 devmask |= (1 << 0);
2074 if (dev1)
2075 devmask |= (1 << 1);
2076
2077 /* select device 0 again */
2078 ap->ops->dev_select(ap, 0);
2079
2080 /* issue bus reset */
2081 if (ap->flags & ATA_FLAG_SRST)
2082 rc = ata_bus_softreset(ap, devmask);
2083 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
2084 /* set up device control */
2085 if (ap->flags & ATA_FLAG_MMIO)
2086 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2087 else
2088 outb(ap->ctl, ioaddr->ctl_addr);
2089 rc = ata_bus_edd(ap);
2090 }
2091
2092 if (rc)
2093 goto err_out;
2094
2095 /*
2096 * determine by signature whether we have ATA or ATAPI devices
2097 */
2098 err = ata_dev_try_classify(ap, 0);
2099 if ((slave_possible) && (err != 0x81))
2100 ata_dev_try_classify(ap, 1);
2101
2102 /* re-enable interrupts */
2103 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2104 ata_irq_on(ap);
2105
2106 /* is double-select really necessary? */
2107 if (ap->device[1].class != ATA_DEV_NONE)
2108 ap->ops->dev_select(ap, 1);
2109 if (ap->device[0].class != ATA_DEV_NONE)
2110 ap->ops->dev_select(ap, 0);
2111
2112 /* if no devices were detected, disable this port */
2113 if ((ap->device[0].class == ATA_DEV_NONE) &&
2114 (ap->device[1].class == ATA_DEV_NONE))
2115 goto err_out;
2116
2117 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2118 /* set up device control for ATA_FLAG_SATA_RESET */
2119 if (ap->flags & ATA_FLAG_MMIO)
2120 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2121 else
2122 outb(ap->ctl, ioaddr->ctl_addr);
2123 }
2124
2125 DPRINTK("EXIT\n");
2126 return;
2127
2128err_out:
2129 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
2130 ap->ops->port_disable(ap);
2131
2132 DPRINTK("EXIT\n");
2133}
2134
057ace5e
JG		 2135static void ata_pr_blacklisted(const struct ata_port *ap,
2136 const struct ata_device *dev)
1da177e4
LT		 2137{
2138 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2139 ap->id, dev->devno);
2140}
2141
98ac62de 2142static const char * const ata_dma_blacklist [] = {
1da177e4
LT		 2143 "WDC AC11000H",
2144 "WDC AC22100H",
2145 "WDC AC32500H",
2146 "WDC AC33100H",
2147 "WDC AC31600H",
2148 "WDC AC32100H",
2149 "WDC AC23200L",
2150 "Compaq CRD-8241B",
2151 "CRD-8400B",
2152 "CRD-8480B",
2153 "CRD-8482B",
2154 "CRD-84",
2155 "SanDisk SDP3B",
2156 "SanDisk SDP3B-64",
2157 "SANYO CD-ROM CRD",
2158 "HITACHI CDR-8",
2159 "HITACHI CDR-8335",
2160 "HITACHI CDR-8435",
2161 "Toshiba CD-ROM XM-6202B",
e922256a 2162 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2163 "CD-532E-A",
2164 "E-IDE CD-ROM CR-840",
2165 "CD-ROM Drive/F5A",
2166 "WPI CDD-820",
2167 "SAMSUNG CD-ROM SC-148C",
2168 "SAMSUNG CD-ROM SC",
2169 "SanDisk SDP3B-64",
1da177e4
LT		 2170 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2171 "_NEC DV5800A",
2172};
2173
057ace5e 2174static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4
LT		 2175{
2176 unsigned char model_num[40];
2177 char *s;
2178 unsigned int len;
2179 int i;
2180
2181 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2182 sizeof(model_num));
2183 s = &model_num[0];
2184 len = strnlen(s, sizeof(model_num));
2185
2186 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2187 while ((len > 0) && (s[len - 1] == ' ')) {
2188 len--;
2189 s[len] = 0;
2190 }
2191
2192 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2193 if (!strncmp(ata_dma_blacklist[i], s, len))
2194 return 1;
2195
2196 return 0;
2197}
2198
057ace5e 2199static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2200{
057ace5e 2201 const struct ata_device *master, *slave;
1da177e4
LT		 2202 unsigned int mask;
2203
2204 master = &ap->device[0];
2205 slave = &ap->device[1];
2206
2207 assert (ata_dev_present(master) || ata_dev_present(slave));
2208
2209 if (shift == ATA_SHIFT_UDMA) {
2210 mask = ap->udma_mask;
2211 if (ata_dev_present(master)) {
2212 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2213 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2214 mask = 0;
2215 ata_pr_blacklisted(ap, master);
2216 }
2217 }
2218 if (ata_dev_present(slave)) {
2219 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2220 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2221 mask = 0;
2222 ata_pr_blacklisted(ap, slave);
2223 }
2224 }
2225 }
2226 else if (shift == ATA_SHIFT_MWDMA) {
2227 mask = ap->mwdma_mask;
2228 if (ata_dev_present(master)) {
2229 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2230 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2231 mask = 0;
2232 ata_pr_blacklisted(ap, master);
2233 }
2234 }
2235 if (ata_dev_present(slave)) {
2236 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2237 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2238 mask = 0;
2239 ata_pr_blacklisted(ap, slave);
2240 }
2241 }
2242 }
2243 else if (shift == ATA_SHIFT_PIO) {
2244 mask = ap->pio_mask;
2245 if (ata_dev_present(master)) {
2246 /* spec doesn't return explicit support for
2247 * PIO0-2, so we fake it
2248 */
2249 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2250 tmp_mode <<= 3;
2251 tmp_mode |= 0x7;
2252 mask &= tmp_mode;
2253 }
2254 if (ata_dev_present(slave)) {
2255 /* spec doesn't return explicit support for
2256 * PIO0-2, so we fake it
2257 */
2258 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2259 tmp_mode <<= 3;
2260 tmp_mode |= 0x7;
2261 mask &= tmp_mode;
2262 }
2263 }
2264 else {
2265 mask = 0xffffffff; /* shut up compiler warning */
2266 BUG();
2267 }
2268
2269 return mask;
2270}
2271
2272/* find greatest bit */
2273static int fgb(u32 bitmap)
2274{
2275 unsigned int i;
2276 int x = -1;
2277
2278 for (i = 0; i < 32; i++)
2279 if (bitmap & (1 << i))
2280 x = i;
2281
2282 return x;
2283}
2284
2285/**
2286 * ata_choose_xfer_mode - attempt to find best transfer mode
2287 * @ap: Port for which an xfer mode will be selected
2288 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2289 * @xfer_shift_out: (output) bit shift that selects this mode
2290 *
0cba632b
JG		 2291 * Based on host and device capabilities, determine the
2292 * maximum transfer mode that is amenable to all.
2293 *
1da177e4 2294 * LOCKING:
0cba632b 2295 * PCI/etc. bus probe sem.
1da177e4
LT		 2296 *
2297 * RETURNS:
2298 * Zero on success, negative on error.
2299 */
2300
057ace5e 2301static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 2302 u8 *xfer_mode_out,
2303 unsigned int *xfer_shift_out)
2304{
2305 unsigned int mask, shift;
2306 int x, i;
2307
2308 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2309 shift = xfer_mode_classes[i].shift;
2310 mask = ata_get_mode_mask(ap, shift);
2311
2312 x = fgb(mask);
2313 if (x >= 0) {
2314 *xfer_mode_out = xfer_mode_classes[i].base + x;
2315 *xfer_shift_out = shift;
2316 return 0;
2317 }
2318 }
2319
2320 return -1;
2321}
2322
2323/**
2324 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2325 * @ap: Port associated with device @dev
2326 * @dev: Device to which command will be sent
2327 *
780a87f7
JG		 2328 * Issue SET FEATURES - XFER MODE command to device @dev
2329 * on port @ap.
2330 *
1da177e4 2331 * LOCKING:
0cba632b 2332 * PCI/etc. bus probe sem.
1da177e4
LT		 2333 */
2334
2335static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2336{
a0123703 2337 struct ata_taskfile tf;
1da177e4
LT		 2338
2339 /* set up set-features taskfile */
2340 DPRINTK("set features - xfer mode\n");
2341
a0123703
TH		 2342 ata_tf_init(ap, &tf, dev->devno);
2343 tf.command = ATA_CMD_SET_FEATURES;
2344 tf.feature = SETFEATURES_XFER;
2345 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2346 tf.protocol = ATA_PROT_NODATA;
2347 tf.nsect = dev->xfer_mode;
1da177e4 2348
a0123703
TH		 2349 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2350 printk(KERN_ERR "ata%u: failed to set xfermode, disabled\n",
2351 ap->id);
1da177e4 2352 ata_port_disable(ap);
a0123703 2353 }
1da177e4
LT		 2354
2355 DPRINTK("EXIT\n");
2356}
2357
59a10b17
AL		 2358/**
2359 * ata_dev_reread_id - Reread the device identify device info
2360 * @ap: port where the device is
2361 * @dev: device to reread the identify device info
2362 *
2363 * LOCKING:
2364 */
2365
2366static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2367{
a0123703 2368 struct ata_taskfile tf;
59a10b17 2369
a0123703 2370 ata_tf_init(ap, &tf, dev->devno);
59a10b17
AL		 2371
2372 if (dev->class == ATA_DEV_ATA) {
a0123703 2373 tf.command = ATA_CMD_ID_ATA;
59a10b17
AL		 2374 DPRINTK("do ATA identify\n");
2375 } else {
a0123703 2376 tf.command = ATA_CMD_ID_ATAPI;
59a10b17
AL		 2377 DPRINTK("do ATAPI identify\n");
2378 }
2379
a0123703
TH		 2380 tf.flags |= ATA_TFLAG_DEVICE;
2381 tf.protocol = ATA_PROT_PIO;
59a10b17 2382
a0123703
TH		 2383 if (ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
2384 dev->id, sizeof(dev->id)))
59a10b17
AL		 2385 goto err_out;
2386
59a10b17
AL		 2387 swap_buf_le16(dev->id, ATA_ID_WORDS);
2388
2389 ata_dump_id(dev);
2390
2391 DPRINTK("EXIT\n");
2392
2393 return;
2394err_out:
a0123703 2395 printk(KERN_ERR "ata%u: failed to reread ID, disabled\n", ap->id);
59a10b17
AL		 2396 ata_port_disable(ap);
2397}
2398
8bf62ece
AL		 2399/**
2400 * ata_dev_init_params - Issue INIT DEV PARAMS command
2401 * @ap: Port associated with device @dev
2402 * @dev: Device to which command will be sent
2403 *
2404 * LOCKING:
2405 */
2406
2407static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2408{
a0123703 2409 struct ata_taskfile tf;
8bf62ece
AL		 2410 u16 sectors = dev->id[6];
2411 u16 heads = dev->id[3];
2412
2413 /* Number of sectors per track 1-255. Number of heads 1-16 */
2414 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2415 return;
2416
2417 /* set up init dev params taskfile */
2418 DPRINTK("init dev params \n");
2419
a0123703
TH		 2420 ata_tf_init(ap, &tf, dev->devno);
2421 tf.command = ATA_CMD_INIT_DEV_PARAMS;
2422 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2423 tf.protocol = ATA_PROT_NODATA;
2424 tf.nsect = sectors;
2425 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 2426
a0123703
TH		 2427 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2428 printk(KERN_ERR "ata%u: failed to init parameters, disabled\n",
2429 ap->id);
8bf62ece 2430 ata_port_disable(ap);
a0123703 2431 }
8bf62ece
AL		 2432
2433 DPRINTK("EXIT\n");
2434}
2435
1da177e4 2436/**
0cba632b
JG		 2437 * ata_sg_clean - Unmap DMA memory associated with command
2438 * @qc: Command containing DMA memory to be released
2439 *
2440 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2441 *
2442 * LOCKING:
0cba632b 2443 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2444 */
2445
2446static void ata_sg_clean(struct ata_queued_cmd *qc)
2447{
2448 struct ata_port *ap = qc->ap;
cedc9a47 2449 struct scatterlist *sg = qc->__sg;
1da177e4 2450 int dir = qc->dma_dir;
cedc9a47 2451 void *pad_buf = NULL;
1da177e4
LT		 2452
2453 assert(qc->flags & ATA_QCFLAG_DMAMAP);
2454 assert(sg != NULL);
2455
2456 if (qc->flags & ATA_QCFLAG_SINGLE)
2457 assert(qc->n_elem == 1);
2458
2c13b7ce 2459 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 2460
cedc9a47
JG		 2461 /* if we padded the buffer out to 32-bit bound, and data
2462 * xfer direction is from-device, we must copy from the
2463 * pad buffer back into the supplied buffer
2464 */
2465 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2466 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2467
2468 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d
JG		 2469 if (qc->n_elem)
2470 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2471 /* restore last sg */
2472 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2473 if (pad_buf) {
2474 struct scatterlist *psg = &qc->pad_sgent;
2475 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2476 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 2477 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2478 }
2479 } else {
e1410f2d
JG		 2480 if (sg_dma_len(&sg[0]) > 0)
2481 dma_unmap_single(ap->host_set->dev,
2482 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
2483 dir);
cedc9a47
JG		 2484 /* restore sg */
2485 sg->length += qc->pad_len;
2486 if (pad_buf)
2487 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2488 pad_buf, qc->pad_len);
2489 }
1da177e4
LT		 2490
2491 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2492 qc->__sg = NULL;
1da177e4
LT		 2493}
2494
2495/**
2496 * ata_fill_sg - Fill PCI IDE PRD table
2497 * @qc: Metadata associated with taskfile to be transferred
2498 *
780a87f7
JG		 2499 * Fill PCI IDE PRD (scatter-gather) table with segments
2500 * associated with the current disk command.
2501 *
1da177e4 2502 * LOCKING:
780a87f7 2503 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2504 *
2505 */
2506static void ata_fill_sg(struct ata_queued_cmd *qc)
2507{
1da177e4 2508 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2509 struct scatterlist *sg;
2510 unsigned int idx;
1da177e4 2511
cedc9a47 2512 assert(qc->__sg != NULL);
1da177e4
LT		 2513 assert(qc->n_elem > 0);
2514
2515 idx = 0;
cedc9a47 2516 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2517 u32 addr, offset;
2518 u32 sg_len, len;
2519
2520 /* determine if physical DMA addr spans 64K boundary.
2521 * Note h/w doesn't support 64-bit, so we unconditionally
2522 * truncate dma_addr_t to u32.
2523 */
2524 addr = (u32) sg_dma_address(sg);
2525 sg_len = sg_dma_len(sg);
2526
2527 while (sg_len) {
2528 offset = addr & 0xffff;
2529 len = sg_len;
2530 if ((offset + sg_len) > 0x10000)
2531 len = 0x10000 - offset;
2532
2533 ap->prd[idx].addr = cpu_to_le32(addr);
2534 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2535 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2536
2537 idx++;
2538 sg_len -= len;
2539 addr += len;
2540 }
2541 }
2542
2543 if (idx)
2544 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2545}
2546/**
2547 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2548 * @qc: Metadata associated with taskfile to check
2549 *
780a87f7
JG		 2550 * Allow low-level driver to filter ATA PACKET commands, returning
2551 * a status indicating whether or not it is OK to use DMA for the
2552 * supplied PACKET command.
2553 *
1da177e4 2554 * LOCKING:
0cba632b
JG		 2555 * spin_lock_irqsave(host_set lock)
2556 *
1da177e4
LT		 2557 * RETURNS: 0 when ATAPI DMA can be used
2558 * nonzero otherwise
2559 */
2560int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2561{
2562 struct ata_port *ap = qc->ap;
2563 int rc = 0; /* Assume ATAPI DMA is OK by default */
2564
2565 if (ap->ops->check_atapi_dma)
2566 rc = ap->ops->check_atapi_dma(qc);
2567
2568 return rc;
2569}
2570/**
2571 * ata_qc_prep - Prepare taskfile for submission
2572 * @qc: Metadata associated with taskfile to be prepared
2573 *
780a87f7
JG		 2574 * Prepare ATA taskfile for submission.
2575 *
1da177e4
LT		 2576 * LOCKING:
2577 * spin_lock_irqsave(host_set lock)
2578 */
2579void ata_qc_prep(struct ata_queued_cmd *qc)
2580{
2581 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2582 return;
2583
2584 ata_fill_sg(qc);
2585}
2586
0cba632b
JG		 2587/**
2588 * ata_sg_init_one - Associate command with memory buffer
2589 * @qc: Command to be associated
2590 * @buf: Memory buffer
2591 * @buflen: Length of memory buffer, in bytes.
2592 *
2593 * Initialize the data-related elements of queued_cmd @qc
2594 * to point to a single memory buffer, @buf of byte length @buflen.
2595 *
2596 * LOCKING:
2597 * spin_lock_irqsave(host_set lock)
2598 */
2599
1da177e4
LT		 2600void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2601{
2602 struct scatterlist *sg;
2603
2604 qc->flags |= ATA_QCFLAG_SINGLE;
2605
2606 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2607 qc->__sg = &qc->sgent;
1da177e4 2608 qc->n_elem = 1;
cedc9a47 2609 qc->orig_n_elem = 1;
1da177e4
LT		 2610 qc->buf_virt = buf;
2611
cedc9a47 2612 sg = qc->__sg;
f0612bbc 2613 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2614}
2615
0cba632b
JG		 2616/**
2617 * ata_sg_init - Associate command with scatter-gather table.
2618 * @qc: Command to be associated
2619 * @sg: Scatter-gather table.
2620 * @n_elem: Number of elements in s/g table.
2621 *
2622 * Initialize the data-related elements of queued_cmd @qc
2623 * to point to a scatter-gather table @sg, containing @n_elem
2624 * elements.
2625 *
2626 * LOCKING:
2627 * spin_lock_irqsave(host_set lock)
2628 */
2629
1da177e4
LT		 2630void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2631 unsigned int n_elem)
2632{
2633 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2634 qc->__sg = sg;
1da177e4 2635 qc->n_elem = n_elem;
cedc9a47 2636 qc->orig_n_elem = n_elem;
1da177e4
LT		 2637}
2638
2639/**
0cba632b
JG		 2640 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2641 * @qc: Command with memory buffer to be mapped.
2642 *
2643 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2644 *
2645 * LOCKING:
2646 * spin_lock_irqsave(host_set lock)
2647 *
2648 * RETURNS:
0cba632b 2649 * Zero on success, negative on error.
1da177e4
LT		 2650 */
2651
2652static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2653{
2654 struct ata_port *ap = qc->ap;
2655 int dir = qc->dma_dir;
cedc9a47 2656 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2657 dma_addr_t dma_address;
2658
cedc9a47
JG		 2659 /* we must lengthen transfers to end on a 32-bit boundary */
2660 qc->pad_len = sg->length & 3;
2661 if (qc->pad_len) {
2662 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2663 struct scatterlist *psg = &qc->pad_sgent;
2664
2665 assert(qc->dev->class == ATA_DEV_ATAPI);
2666
2667 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2668
2669 if (qc->tf.flags & ATA_TFLAG_WRITE)
2670 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2671 qc->pad_len);
2672
2673 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2674 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2675 /* trim sg */
2676 sg->length -= qc->pad_len;
2677
2678 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2679 sg->length, qc->pad_len);
2680 }
2681
e1410f2d
JG		 2682 if (!sg->length) {
2683 sg_dma_address(sg) = 0;
2684 goto skip_map;
2685 }
2686
1da177e4 2687 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2688 sg->length, dir);
537a95d9
TH		 2689 if (dma_mapping_error(dma_address)) {
2690 /* restore sg */
2691 sg->length += qc->pad_len;
1da177e4 2692 return -1;
537a95d9 2693 }
1da177e4
LT		 2694
2695 sg_dma_address(sg) = dma_address;
e1410f2d 2696skip_map:
32529e01 2697 sg_dma_len(sg) = sg->length;
1da177e4
LT		 2698
2699 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2700 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2701
2702 return 0;
2703}
2704
2705/**
0cba632b
JG		 2706 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2707 * @qc: Command with scatter-gather table to be mapped.
2708 *
2709 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2710 *
2711 * LOCKING:
2712 * spin_lock_irqsave(host_set lock)
2713 *
2714 * RETURNS:
0cba632b 2715 * Zero on success, negative on error.
1da177e4
LT		 2716 *
2717 */
2718
2719static int ata_sg_setup(struct ata_queued_cmd *qc)
2720{
2721 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2722 struct scatterlist *sg = qc->__sg;
2723 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 2724 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 2725
2726 VPRINTK("ENTER, ata%u\n", ap->id);
2727 assert(qc->flags & ATA_QCFLAG_SG);
2728
cedc9a47
JG		 2729 /* we must lengthen transfers to end on a 32-bit boundary */
2730 qc->pad_len = lsg->length & 3;
2731 if (qc->pad_len) {
2732 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2733 struct scatterlist *psg = &qc->pad_sgent;
2734 unsigned int offset;
2735
2736 assert(qc->dev->class == ATA_DEV_ATAPI);
2737
2738 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2739
2740 /*
2741 * psg->page/offset are used to copy to-be-written
2742 * data in this function or read data in ata_sg_clean.
2743 */
2744 offset = lsg->offset + lsg->length - qc->pad_len;
2745 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
2746 psg->offset = offset_in_page(offset);
2747
2748 if (qc->tf.flags & ATA_TFLAG_WRITE) {
2749 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2750 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 2751 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2752 }
2753
2754 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2755 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2756 /* trim last sg */
2757 lsg->length -= qc->pad_len;
e1410f2d
JG		 2758 if (lsg->length == 0)
2759 trim_sg = 1;
cedc9a47
JG		 2760
2761 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
2762 qc->n_elem - 1, lsg->length, qc->pad_len);
2763 }
2764
e1410f2d
JG		 2765 pre_n_elem = qc->n_elem;
2766 if (trim_sg && pre_n_elem)
2767 pre_n_elem--;
2768
2769 if (!pre_n_elem) {
2770 n_elem = 0;
2771 goto skip_map;
2772 }
2773
1da177e4 2774 dir = qc->dma_dir;
e1410f2d 2775 n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir);
537a95d9
TH		 2776 if (n_elem < 1) {
2777 /* restore last sg */
2778 lsg->length += qc->pad_len;
1da177e4 2779 return -1;
537a95d9 2780 }
1da177e4
LT		 2781
2782 DPRINTK("%d sg elements mapped\n", n_elem);
2783
e1410f2d 2784skip_map:
1da177e4
LT		 2785 qc->n_elem = n_elem;
2786
2787 return 0;
2788}
2789
40e8c82c
TH		 2790/**
2791 * ata_poll_qc_complete - turn irq back on and finish qc
2792 * @qc: Command to complete
8e8b77dd 2793 * @err_mask: ATA status register content
40e8c82c
TH		 2794 *
2795 * LOCKING:
2796 * None. (grabs host lock)
2797 */
2798
a22e2eb0 2799void ata_poll_qc_complete(struct ata_queued_cmd *qc)
40e8c82c
TH		 2800{
2801 struct ata_port *ap = qc->ap;
b8f6153e 2802 unsigned long flags;
40e8c82c 2803
b8f6153e 2804 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH		 2805 ap->flags &= ~ATA_FLAG_NOINTR;
2806 ata_irq_on(ap);
a22e2eb0 2807 ata_qc_complete(qc);
b8f6153e 2808 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 2809}
2810
1da177e4
LT		 2811/**
2812 * ata_pio_poll -
6f0ef4fa 2813 * @ap: the target ata_port
1da177e4
LT		 2814 *
2815 * LOCKING:
0cba632b 2816 * None. (executing in kernel thread context)
1da177e4
LT		 2817 *
2818 * RETURNS:
6f0ef4fa 2819 * timeout value to use
1da177e4
LT		 2820 */
2821
2822static unsigned long ata_pio_poll(struct ata_port *ap)
2823{
c14b8331 2824 struct ata_queued_cmd *qc;
1da177e4 2825 u8 status;
14be71f4
AL		 2826 unsigned int poll_state = HSM_ST_UNKNOWN;
2827 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4 2828
c14b8331
AL		 2829 qc = ata_qc_from_tag(ap, ap->active_tag);
2830 assert(qc != NULL);
2831
14be71f4
AL		 2832 switch (ap->hsm_task_state) {
2833 case HSM_ST:
2834 case HSM_ST_POLL:
2835 poll_state = HSM_ST_POLL;
2836 reg_state = HSM_ST;
1da177e4 2837 break;
14be71f4
AL		 2838 case HSM_ST_LAST:
2839 case HSM_ST_LAST_POLL:
2840 poll_state = HSM_ST_LAST_POLL;
2841 reg_state = HSM_ST_LAST;
1da177e4
LT		 2842 break;
2843 default:
2844 BUG();
2845 break;
2846 }
2847
2848 status = ata_chk_status(ap);
2849 if (status & ATA_BUSY) {
2850 if (time_after(jiffies, ap->pio_task_timeout)) {
1c848984 2851 qc->err_mask |= AC_ERR_ATA_BUS;
7c398335 2852 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT		 2853 return 0;
2854 }
14be71f4 2855 ap->hsm_task_state = poll_state;
1da177e4
LT		 2856 return ATA_SHORT_PAUSE;
2857 }
2858
14be71f4 2859 ap->hsm_task_state = reg_state;
1da177e4
LT		 2860 return 0;
2861}
2862
2863/**
6f0ef4fa
RD		 2864 * ata_pio_complete - check if drive is busy or idle
2865 * @ap: the target ata_port
1da177e4
LT		 2866 *
2867 * LOCKING:
0cba632b 2868 * None. (executing in kernel thread context)
7fb6ec28
JG		 2869 *
2870 * RETURNS:
2871 * Non-zero if qc completed, zero otherwise.
1da177e4
LT		 2872 */
2873
7fb6ec28 2874static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 2875{
2876 struct ata_queued_cmd *qc;
2877 u8 drv_stat;
2878
2879 /*
31433ea3
AC		 2880 * This is purely heuristic. This is a fast path. Sometimes when
2881 * we enter, BSY will be cleared in a chk-status or two. If not,
2882 * the drive is probably seeking or something. Snooze for a couple
2883 * msecs, then chk-status again. If still busy, fall back to
14be71f4 2884 * HSM_ST_POLL state.
1da177e4 2885 */
fe79e683
AL		 2886 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2887 if (drv_stat & ATA_BUSY) {
1da177e4 2888 msleep(2);
fe79e683
AL		 2889 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2890 if (drv_stat & ATA_BUSY) {
14be71f4 2891 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 2892 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 2893 return 0;
1da177e4
LT		 2894 }
2895 }
2896
c14b8331
AL		 2897 qc = ata_qc_from_tag(ap, ap->active_tag);
2898 assert(qc != NULL);
2899
1da177e4
LT		 2900 drv_stat = ata_wait_idle(ap);
2901 if (!ata_ok(drv_stat)) {
1c848984 2902 qc->err_mask |= __ac_err_mask(drv_stat);
14be71f4 2903 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 2904 return 0;
1da177e4
LT		 2905 }
2906
14be71f4 2907 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 2908
a22e2eb0
AL		 2909 assert(qc->err_mask == 0);
2910 ata_poll_qc_complete(qc);
7fb6ec28
JG		 2911
2912 /* another command may start at this point */
2913
2914 return 1;
1da177e4
LT		 2915}
2916
0baab86b
EF		 2917
2918/**
6f0ef4fa 2919 * swap_buf_le16 - swap halves of 16-words in place
0baab86b
EF		 2920 * @buf: Buffer to swap
2921 * @buf_words: Number of 16-bit words in buffer.
2922 *
2923 * Swap halves of 16-bit words if needed to convert from
2924 * little-endian byte order to native cpu byte order, or
2925 * vice-versa.
2926 *
2927 * LOCKING:
6f0ef4fa 2928 * Inherited from caller.
0baab86b 2929 */
1da177e4
LT		 2930void swap_buf_le16(u16 *buf, unsigned int buf_words)
2931{
2932#ifdef __BIG_ENDIAN
2933 unsigned int i;
2934
2935 for (i = 0; i < buf_words; i++)
2936 buf[i] = le16_to_cpu(buf[i]);
2937#endif /* __BIG_ENDIAN */
2938}
2939
6ae4cfb5
AL		 2940/**
2941 * ata_mmio_data_xfer - Transfer data by MMIO
2942 * @ap: port to read/write
2943 * @buf: data buffer
2944 * @buflen: buffer length
344babaa 2945 * @write_data: read/write
6ae4cfb5
AL		 2946 *
2947 * Transfer data from/to the device data register by MMIO.
2948 *
2949 * LOCKING:
2950 * Inherited from caller.
6ae4cfb5
AL		 2951 */
2952
1da177e4
LT		 2953static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
2954 unsigned int buflen, int write_data)
2955{
2956 unsigned int i;
2957 unsigned int words = buflen >> 1;
2958 u16 *buf16 = (u16 *) buf;
2959 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
2960
6ae4cfb5 2961 /* Transfer multiple of 2 bytes */
1da177e4
LT		 2962 if (write_data) {
2963 for (i = 0; i < words; i++)
2964 writew(le16_to_cpu(buf16[i]), mmio);
2965 } else {
2966 for (i = 0; i < words; i++)
2967 buf16[i] = cpu_to_le16(readw(mmio));
2968 }
6ae4cfb5
AL		 2969
2970 /* Transfer trailing 1 byte, if any. */
2971 if (unlikely(buflen & 0x01)) {
2972 u16 align_buf[1] = { 0 };
2973 unsigned char *trailing_buf = buf + buflen - 1;
2974
2975 if (write_data) {
2976 memcpy(align_buf, trailing_buf, 1);
2977 writew(le16_to_cpu(align_buf[0]), mmio);
2978 } else {
2979 align_buf[0] = cpu_to_le16(readw(mmio));
2980 memcpy(trailing_buf, align_buf, 1);
2981 }
2982 }
1da177e4
LT		 2983}
2984
6ae4cfb5
AL		 2985/**
2986 * ata_pio_data_xfer - Transfer data by PIO
2987 * @ap: port to read/write
2988 * @buf: data buffer
2989 * @buflen: buffer length
344babaa 2990 * @write_data: read/write
6ae4cfb5
AL		 2991 *
2992 * Transfer data from/to the device data register by PIO.
2993 *
2994 * LOCKING:
2995 * Inherited from caller.
6ae4cfb5
AL		 2996 */
2997
1da177e4
LT		 2998static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
2999 unsigned int buflen, int write_data)
3000{
6ae4cfb5 3001 unsigned int words = buflen >> 1;
1da177e4 3002
6ae4cfb5 3003 /* Transfer multiple of 2 bytes */
1da177e4 3004 if (write_data)
6ae4cfb5 3005 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3006 else
6ae4cfb5
AL		 3007 insw(ap->ioaddr.data_addr, buf, words);
3008
3009 /* Transfer trailing 1 byte, if any. */
3010 if (unlikely(buflen & 0x01)) {
3011 u16 align_buf[1] = { 0 };
3012 unsigned char *trailing_buf = buf + buflen - 1;
3013
3014 if (write_data) {
3015 memcpy(align_buf, trailing_buf, 1);
3016 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3017 } else {
3018 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3019 memcpy(trailing_buf, align_buf, 1);
3020 }
3021 }
1da177e4
LT		 3022}
3023
6ae4cfb5
AL		 3024/**
3025 * ata_data_xfer - Transfer data from/to the data register.
3026 * @ap: port to read/write
3027 * @buf: data buffer
3028 * @buflen: buffer length
3029 * @do_write: read/write
3030 *
3031 * Transfer data from/to the device data register.
3032 *
3033 * LOCKING:
3034 * Inherited from caller.
6ae4cfb5
AL		 3035 */
3036
1da177e4
LT		 3037static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3038 unsigned int buflen, int do_write)
3039{
3040 if (ap->flags & ATA_FLAG_MMIO)
3041 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3042 else
3043 ata_pio_data_xfer(ap, buf, buflen, do_write);
3044}
3045
6ae4cfb5
AL		 3046/**
3047 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3048 * @qc: Command on going
3049 *
3050 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3051 *
3052 * LOCKING:
3053 * Inherited from caller.
3054 */
3055
1da177e4
LT		 3056static void ata_pio_sector(struct ata_queued_cmd *qc)
3057{
3058 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3059 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3060 struct ata_port *ap = qc->ap;
3061 struct page *page;
3062 unsigned int offset;
3063 unsigned char *buf;
3064
3065 if (qc->cursect == (qc->nsect - 1))
14be71f4 3066 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3067
3068 page = sg[qc->cursg].page;
3069 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3070
3071 /* get the current page and offset */
3072 page = nth_page(page, (offset >> PAGE_SHIFT));
3073 offset %= PAGE_SIZE;
3074
3075 buf = kmap(page) + offset;
3076
3077 qc->cursect++;
3078 qc->cursg_ofs++;
3079
32529e01 3080 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3081 qc->cursg++;
3082 qc->cursg_ofs = 0;
3083 }
3084
3085 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3086
3087 /* do the actual data transfer */
3088 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3089 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3090
3091 kunmap(page);
3092}
3093
6ae4cfb5
AL		 3094/**
3095 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3096 * @qc: Command on going
3097 * @bytes: number of bytes
3098 *
3099 * Transfer Transfer data from/to the ATAPI device.
3100 *
3101 * LOCKING:
3102 * Inherited from caller.
3103 *
3104 */
3105
1da177e4
LT		 3106static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3107{
3108 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3109 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3110 struct ata_port *ap = qc->ap;
3111 struct page *page;
3112 unsigned char *buf;
3113 unsigned int offset, count;
3114
563a6e1f 3115 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3116 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3117
3118next_sg:
563a6e1f 3119 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3120 /*
563a6e1f
AL		 3121 * The end of qc->sg is reached and the device expects
3122 * more data to transfer. In order not to overrun qc->sg
3123 * and fulfill length specified in the byte count register,
3124 * - for read case, discard trailing data from the device
3125 * - for write case, padding zero data to the device
3126 */
3127 u16 pad_buf[1] = { 0 };
3128 unsigned int words = bytes >> 1;
3129 unsigned int i;
3130
3131 if (words) /* warning if bytes > 1 */
7fb6ec28 3132 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3133 ap->id, bytes);
3134
3135 for (i = 0; i < words; i++)
3136 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3137
14be71f4 3138 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3139 return;
3140 }
3141
cedc9a47 3142 sg = &qc->__sg[qc->cursg];
1da177e4 3143
1da177e4
LT		 3144 page = sg->page;
3145 offset = sg->offset + qc->cursg_ofs;
3146
3147 /* get the current page and offset */
3148 page = nth_page(page, (offset >> PAGE_SHIFT));
3149 offset %= PAGE_SIZE;
3150
6952df03 3151 /* don't overrun current sg */
32529e01 3152 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3153
3154 /* don't cross page boundaries */
3155 count = min(count, (unsigned int)PAGE_SIZE - offset);
3156
3157 buf = kmap(page) + offset;
3158
3159 bytes -= count;
3160 qc->curbytes += count;
3161 qc->cursg_ofs += count;
3162
32529e01 3163 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3164 qc->cursg++;
3165 qc->cursg_ofs = 0;
3166 }
3167
3168 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3169
3170 /* do the actual data transfer */
3171 ata_data_xfer(ap, buf, count, do_write);
3172
3173 kunmap(page);
3174
563a6e1f 3175 if (bytes)
1da177e4 3176 goto next_sg;
1da177e4
LT		 3177}
3178
6ae4cfb5
AL		 3179/**
3180 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3181 * @qc: Command on going
3182 *
3183 * Transfer Transfer data from/to the ATAPI device.
3184 *
3185 * LOCKING:
3186 * Inherited from caller.
6ae4cfb5
AL		 3187 */
3188
1da177e4
LT		 3189static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3190{
3191 struct ata_port *ap = qc->ap;
3192 struct ata_device *dev = qc->dev;
3193 unsigned int ireason, bc_lo, bc_hi, bytes;
3194 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3195
3196 ap->ops->tf_read(ap, &qc->tf);
3197 ireason = qc->tf.nsect;
3198 bc_lo = qc->tf.lbam;
3199 bc_hi = qc->tf.lbah;
3200 bytes = (bc_hi << 8) | bc_lo;
3201
3202 /* shall be cleared to zero, indicating xfer of data */
3203 if (ireason & (1 << 0))
3204 goto err_out;
3205
3206 /* make sure transfer direction matches expected */
3207 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3208 if (do_write != i_write)
3209 goto err_out;
3210
3211 __atapi_pio_bytes(qc, bytes);
3212
3213 return;
3214
3215err_out:
3216 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3217 ap->id, dev->devno);
1c848984 3218 qc->err_mask |= AC_ERR_ATA_BUS;
14be71f4 3219 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3220}
3221
3222/**
6f0ef4fa
RD		 3223 * ata_pio_block - start PIO on a block
3224 * @ap: the target ata_port
1da177e4
LT		 3225 *
3226 * LOCKING:
0cba632b 3227 * None. (executing in kernel thread context)
1da177e4
LT		 3228 */
3229
3230static void ata_pio_block(struct ata_port *ap)
3231{
3232 struct ata_queued_cmd *qc;
3233 u8 status;
3234
3235 /*
6f0ef4fa 3236 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3237 * Sometimes when we enter, BSY will be cleared in
3238 * a chk-status or two. If not, the drive is probably seeking
3239 * or something. Snooze for a couple msecs, then
3240 * chk-status again. If still busy, fall back to
14be71f4 3241 * HSM_ST_POLL state.
1da177e4
LT		 3242 */
3243 status = ata_busy_wait(ap, ATA_BUSY, 5);
3244 if (status & ATA_BUSY) {
3245 msleep(2);
3246 status = ata_busy_wait(ap, ATA_BUSY, 10);
3247 if (status & ATA_BUSY) {
14be71f4 3248 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3249 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3250 return;
3251 }
3252 }
3253
3254 qc = ata_qc_from_tag(ap, ap->active_tag);
3255 assert(qc != NULL);
3256
fe79e683
AL		 3257 /* check error */
3258 if (status & (ATA_ERR | ATA_DF)) {
3259 qc->err_mask |= AC_ERR_DEV;
3260 ap->hsm_task_state = HSM_ST_ERR;
3261 return;
3262 }
3263
3264 /* transfer data if any */
1da177e4 3265 if (is_atapi_taskfile(&qc->tf)) {
fe79e683 3266 /* DRQ=0 means no more data to transfer */
1da177e4 3267 if ((status & ATA_DRQ) == 0) {
14be71f4 3268 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3269 return;
3270 }
3271
3272 atapi_pio_bytes(qc);
3273 } else {
3274 /* handle BSY=0, DRQ=0 as error */
3275 if ((status & ATA_DRQ) == 0) {
1c848984 3276 qc->err_mask |= AC_ERR_ATA_BUS;
14be71f4 3277 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3278 return;
3279 }
3280
3281 ata_pio_sector(qc);
3282 }
3283}
3284
3285static void ata_pio_error(struct ata_port *ap)
3286{
3287 struct ata_queued_cmd *qc;
a7dac447
JG		 3288
3289 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
1da177e4
LT		 3290
3291 qc = ata_qc_from_tag(ap, ap->active_tag);
3292 assert(qc != NULL);
3293
1c848984
AL		 3294 /* make sure qc->err_mask is available to
3295 * know what's wrong and recover
3296 */
3297 assert(qc->err_mask);
3298
14be71f4 3299 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3300
a22e2eb0 3301 ata_poll_qc_complete(qc);
1da177e4
LT		 3302}
3303
3304static void ata_pio_task(void *_data)
3305{
3306 struct ata_port *ap = _data;
7fb6ec28
JG		 3307 unsigned long timeout;
3308 int qc_completed;
3309
3310fsm_start:
3311 timeout = 0;
3312 qc_completed = 0;
1da177e4 3313
14be71f4
AL		 3314 switch (ap->hsm_task_state) {
3315 case HSM_ST_IDLE:
1da177e4
LT		 3316 return;
3317
14be71f4 3318 case HSM_ST:
1da177e4
LT		 3319 ata_pio_block(ap);
3320 break;
3321
14be71f4 3322 case HSM_ST_LAST:
7fb6ec28 3323 qc_completed = ata_pio_complete(ap);
1da177e4
LT		 3324 break;
3325
14be71f4
AL		 3326 case HSM_ST_POLL:
3327 case HSM_ST_LAST_POLL:
1da177e4
LT		 3328 timeout = ata_pio_poll(ap);
3329 break;
3330
14be71f4
AL		 3331 case HSM_ST_TMOUT:
3332 case HSM_ST_ERR:
1da177e4
LT		 3333 ata_pio_error(ap);
3334 return;
3335 }
3336
3337 if (timeout)
7fb6ec28
JG		 3338 queue_delayed_work(ata_wq, &ap->pio_task, timeout);
3339 else if (!qc_completed)
3340 goto fsm_start;
1da177e4
LT		 3341}
3342
1da177e4
LT		 3343/**
3344 * ata_qc_timeout - Handle timeout of queued command
3345 * @qc: Command that timed out
3346 *
3347 * Some part of the kernel (currently, only the SCSI layer)
3348 * has noticed that the active command on port @ap has not
3349 * completed after a specified length of time. Handle this
3350 * condition by disabling DMA (if necessary) and completing
3351 * transactions, with error if necessary.
3352 *
3353 * This also handles the case of the "lost interrupt", where
3354 * for some reason (possibly hardware bug, possibly driver bug)
3355 * an interrupt was not delivered to the driver, even though the
3356 * transaction completed successfully.
3357 *
3358 * LOCKING:
0cba632b 3359 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3360 */
3361
3362static void ata_qc_timeout(struct ata_queued_cmd *qc)
3363{
3364 struct ata_port *ap = qc->ap;
b8f6153e 3365 struct ata_host_set *host_set = ap->host_set;
1da177e4 3366 u8 host_stat = 0, drv_stat;
b8f6153e 3367 unsigned long flags;
1da177e4
LT		 3368
3369 DPRINTK("ENTER\n");
3370
b8f6153e
JG		 3371 spin_lock_irqsave(&host_set->lock, flags);
3372
1da177e4
LT		 3373 /* hack alert! We cannot use the supplied completion
3374 * function from inside the ->eh_strategy_handler() thread.
3375 * libata is the only user of ->eh_strategy_handler() in
3376 * any kernel, so the default scsi_done() assumes it is
3377 * not being called from the SCSI EH.
3378 */
3379 qc->scsidone = scsi_finish_command;
3380
3381 switch (qc->tf.protocol) {
3382
3383 case ATA_PROT_DMA:
3384 case ATA_PROT_ATAPI_DMA:
3385 host_stat = ap->ops->bmdma_status(ap);
3386
3387 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3388 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3389
3390 /* fall through */
3391
3392 default:
3393 ata_altstatus(ap);
3394 drv_stat = ata_chk_status(ap);
3395
3396 /* ack bmdma irq events */
3397 ap->ops->irq_clear(ap);
3398
3399 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3400 ap->id, qc->tf.command, drv_stat, host_stat);
3401
3402 /* complete taskfile transaction */
a22e2eb0
AL		 3403 qc->err_mask |= ac_err_mask(drv_stat);
3404 ata_qc_complete(qc);
1da177e4
LT		 3405 break;
3406 }
b8f6153e
JG		 3407
3408 spin_unlock_irqrestore(&host_set->lock, flags);
3409
1da177e4
LT		 3410 DPRINTK("EXIT\n");
3411}
3412
3413/**
3414 * ata_eng_timeout - Handle timeout of queued command
3415 * @ap: Port on which timed-out command is active
3416 *
3417 * Some part of the kernel (currently, only the SCSI layer)
3418 * has noticed that the active command on port @ap has not
3419 * completed after a specified length of time. Handle this
3420 * condition by disabling DMA (if necessary) and completing
3421 * transactions, with error if necessary.
3422 *
3423 * This also handles the case of the "lost interrupt", where
3424 * for some reason (possibly hardware bug, possibly driver bug)
3425 * an interrupt was not delivered to the driver, even though the
3426 * transaction completed successfully.
3427 *
3428 * LOCKING:
3429 * Inherited from SCSI layer (none, can sleep)
3430 */
3431
3432void ata_eng_timeout(struct ata_port *ap)
3433{
3434 struct ata_queued_cmd *qc;
3435
3436 DPRINTK("ENTER\n");
3437
3438 qc = ata_qc_from_tag(ap, ap->active_tag);
e12669e7
JG		 3439 if (qc)
3440 ata_qc_timeout(qc);
3441 else {
1da177e4
LT		 3442 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
3443 ap->id);
3444 goto out;
3445 }
3446
1da177e4
LT		 3447out:
3448 DPRINTK("EXIT\n");
3449}
3450
3451/**
3452 * ata_qc_new - Request an available ATA command, for queueing
3453 * @ap: Port associated with device @dev
3454 * @dev: Device from whom we request an available command structure
3455 *
3456 * LOCKING:
0cba632b 3457 * None.
1da177e4
LT		 3458 */
3459
3460static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3461{
3462 struct ata_queued_cmd *qc = NULL;
3463 unsigned int i;
3464
3465 for (i = 0; i < ATA_MAX_QUEUE; i++)
3466 if (!test_and_set_bit(i, &ap->qactive)) {
3467 qc = ata_qc_from_tag(ap, i);
3468 break;
3469 }
3470
3471 if (qc)
3472 qc->tag = i;
3473
3474 return qc;
3475}
3476
3477/**
3478 * ata_qc_new_init - Request an available ATA command, and initialize it
3479 * @ap: Port associated with device @dev
3480 * @dev: Device from whom we request an available command structure
3481 *
3482 * LOCKING:
0cba632b 3483 * None.
1da177e4
LT		 3484 */
3485
3486struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3487 struct ata_device *dev)
3488{
3489 struct ata_queued_cmd *qc;
3490
3491 qc = ata_qc_new(ap);
3492 if (qc) {
1da177e4
LT		 3493 qc->scsicmd = NULL;
3494 qc->ap = ap;
3495 qc->dev = dev;
1da177e4 3496
2c13b7ce 3497 ata_qc_reinit(qc);
1da177e4
LT		 3498 }
3499
3500 return qc;
3501}
3502
1da177e4
LT		 3503static void __ata_qc_complete(struct ata_queued_cmd *qc)
3504{
3505 struct ata_port *ap = qc->ap;
b5632303 3506 unsigned int tag;
1da177e4
LT		 3507
3508 qc->flags = 0;
3509 tag = qc->tag;
3510 if (likely(ata_tag_valid(tag))) {
3511 if (tag == ap->active_tag)
3512 ap->active_tag = ATA_TAG_POISON;
3513 qc->tag = ATA_TAG_POISON;
1da177e4 3514 clear_bit(tag, &ap->qactive);
b5632303 3515 }
1da177e4
LT		 3516}
3517
3518/**
3519 * ata_qc_free - free unused ata_queued_cmd
3520 * @qc: Command to complete
3521 *
3522 * Designed to free unused ata_queued_cmd object
3523 * in case something prevents using it.
3524 *
3525 * LOCKING:
0cba632b 3526 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3527 */
3528void ata_qc_free(struct ata_queued_cmd *qc)
3529{
3530 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4
LT		 3531
3532 __ata_qc_complete(qc);
3533}
3534
3535/**
3536 * ata_qc_complete - Complete an active ATA command
3537 * @qc: Command to complete
8e8b77dd 3538 * @err_mask: ATA Status register contents
0cba632b
JG		 3539 *
3540 * Indicate to the mid and upper layers that an ATA
3541 * command has completed, with either an ok or not-ok status.
1da177e4
LT		 3542 *
3543 * LOCKING:
0cba632b 3544 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3545 */
3546
a22e2eb0 3547void ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4
LT		 3548{
3549 int rc;
3550
3551 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3552 assert(qc->flags & ATA_QCFLAG_ACTIVE);
3553
3554 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3555 ata_sg_clean(qc);
3556
3f3791d3
AL		 3557 /* atapi: mark qc as inactive to prevent the interrupt handler
3558 * from completing the command twice later, before the error handler
3559 * is called. (when rc != 0 and atapi request sense is needed)
3560 */
3561 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3562
1da177e4 3563 /* call completion callback */
a22e2eb0 3564 rc = qc->complete_fn(qc);
1da177e4
LT		 3565
3566 /* if callback indicates not to complete command (non-zero),
3567 * return immediately
3568 */
3569 if (rc != 0)
3570 return;
3571
3572 __ata_qc_complete(qc);
3573
3574 VPRINTK("EXIT\n");
3575}
3576
3577static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3578{
3579 struct ata_port *ap = qc->ap;
3580
3581 switch (qc->tf.protocol) {
3582 case ATA_PROT_DMA:
3583 case ATA_PROT_ATAPI_DMA:
3584 return 1;
3585
3586 case ATA_PROT_ATAPI:
3587 case ATA_PROT_PIO:
3588 case ATA_PROT_PIO_MULT:
3589 if (ap->flags & ATA_FLAG_PIO_DMA)
3590 return 1;
3591
3592 /* fall through */
3593
3594 default:
3595 return 0;
3596 }
3597
3598 /* never reached */
3599}
3600
3601/**
3602 * ata_qc_issue - issue taskfile to device
3603 * @qc: command to issue to device
3604 *
3605 * Prepare an ATA command to submission to device.
3606 * This includes mapping the data into a DMA-able
3607 * area, filling in the S/G table, and finally
3608 * writing the taskfile to hardware, starting the command.
3609 *
3610 * LOCKING:
3611 * spin_lock_irqsave(host_set lock)
3612 *
3613 * RETURNS:
3614 * Zero on success, negative on error.
3615 */
3616
3617int ata_qc_issue(struct ata_queued_cmd *qc)
3618{
3619 struct ata_port *ap = qc->ap;
3620
3621 if (ata_should_dma_map(qc)) {
3622 if (qc->flags & ATA_QCFLAG_SG) {
3623 if (ata_sg_setup(qc))
3624 goto err_out;
3625 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3626 if (ata_sg_setup_one(qc))
3627 goto err_out;
3628 }
3629 } else {
3630 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3631 }
3632
3633 ap->ops->qc_prep(qc);
3634
3635 qc->ap->active_tag = qc->tag;
3636 qc->flags |= ATA_QCFLAG_ACTIVE;
3637
3638 return ap->ops->qc_issue(qc);
3639
3640err_out:
3641 return -1;
3642}
3643
0baab86b 3644
1da177e4
LT		 3645/**
3646 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3647 * @qc: command to issue to device
3648 *
3649 * Using various libata functions and hooks, this function
3650 * starts an ATA command. ATA commands are grouped into
3651 * classes called "protocols", and issuing each type of protocol
3652 * is slightly different.
3653 *
0baab86b
EF		 3654 * May be used as the qc_issue() entry in ata_port_operations.
3655 *
1da177e4
LT		 3656 * LOCKING:
3657 * spin_lock_irqsave(host_set lock)
3658 *
3659 * RETURNS:
3660 * Zero on success, negative on error.
3661 */
3662
3663int ata_qc_issue_prot(struct ata_queued_cmd *qc)
3664{
3665 struct ata_port *ap = qc->ap;
3666
3667 ata_dev_select(ap, qc->dev->devno, 1, 0);
3668
3669 switch (qc->tf.protocol) {
3670 case ATA_PROT_NODATA:
e5338254 3671 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3672 break;
3673
3674 case ATA_PROT_DMA:
3675 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3676 ap->ops->bmdma_setup(qc); /* set up bmdma */
3677 ap->ops->bmdma_start(qc); /* initiate bmdma */
3678 break;
3679
3680 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
3681 ata_qc_set_polling(qc);
e5338254 3682 ata_tf_to_host(ap, &qc->tf);
14be71f4 3683 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 3684 queue_work(ata_wq, &ap->pio_task);
3685 break;
3686
3687 case ATA_PROT_ATAPI:
3688 ata_qc_set_polling(qc);
e5338254 3689 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3690 queue_work(ata_wq, &ap->packet_task);
3691 break;
3692
3693 case ATA_PROT_ATAPI_NODATA:
c1389503 3694 ap->flags |= ATA_FLAG_NOINTR;
e5338254 3695 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3696 queue_work(ata_wq, &ap->packet_task);
3697 break;
3698
3699 case ATA_PROT_ATAPI_DMA:
c1389503 3700 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT		 3701 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3702 ap->ops->bmdma_setup(qc); /* set up bmdma */
3703 queue_work(ata_wq, &ap->packet_task);
3704 break;
3705
3706 default:
3707 WARN_ON(1);
3708 return -1;
3709 }
3710
3711 return 0;
3712}
3713
3714/**
0baab86b 3715 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 3716 * @qc: Info associated with this ATA transaction.
3717 *
3718 * LOCKING:
3719 * spin_lock_irqsave(host_set lock)
3720 */
3721
3722static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
3723{
3724 struct ata_port *ap = qc->ap;
3725 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3726 u8 dmactl;
3727 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3728
3729 /* load PRD table addr. */
3730 mb(); /* make sure PRD table writes are visible to controller */
3731 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
3732
3733 /* specify data direction, triple-check start bit is clear */
3734 dmactl = readb(mmio + ATA_DMA_CMD);
3735 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3736 if (!rw)
3737 dmactl |= ATA_DMA_WR;
3738 writeb(dmactl, mmio + ATA_DMA_CMD);
3739
3740 /* issue r/w command */
3741 ap->ops->exec_command(ap, &qc->tf);
3742}
3743
3744/**
b73fc89f 3745 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 3746 * @qc: Info associated with this ATA transaction.
3747 *
3748 * LOCKING:
3749 * spin_lock_irqsave(host_set lock)
3750 */
3751
3752static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
3753{
3754 struct ata_port *ap = qc->ap;
3755 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3756 u8 dmactl;
3757
3758 /* start host DMA transaction */
3759 dmactl = readb(mmio + ATA_DMA_CMD);
3760 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
3761
3762 /* Strictly, one may wish to issue a readb() here, to
3763 * flush the mmio write. However, control also passes
3764 * to the hardware at this point, and it will interrupt
3765 * us when we are to resume control. So, in effect,
3766 * we don't care when the mmio write flushes.
3767 * Further, a read of the DMA status register _immediately_
3768 * following the write may not be what certain flaky hardware
3769 * is expected, so I think it is best to not add a readb()
3770 * without first all the MMIO ATA cards/mobos.
3771 * Or maybe I'm just being paranoid.
3772 */
3773}
3774
3775/**
3776 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
3777 * @qc: Info associated with this ATA transaction.
3778 *
3779 * LOCKING:
3780 * spin_lock_irqsave(host_set lock)
3781 */
3782
3783static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
3784{
3785 struct ata_port *ap = qc->ap;
3786 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3787 u8 dmactl;
3788
3789 /* load PRD table addr. */
3790 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3791
3792 /* specify data direction, triple-check start bit is clear */
3793 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3794 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3795 if (!rw)
3796 dmactl |= ATA_DMA_WR;
3797 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3798
3799 /* issue r/w command */
3800 ap->ops->exec_command(ap, &qc->tf);
3801}
3802
3803/**
3804 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
3805 * @qc: Info associated with this ATA transaction.
3806 *
3807 * LOCKING:
3808 * spin_lock_irqsave(host_set lock)
3809 */
3810
3811static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
3812{
3813 struct ata_port *ap = qc->ap;
3814 u8 dmactl;
3815
3816 /* start host DMA transaction */
3817 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3818 outb(dmactl | ATA_DMA_START,
3819 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3820}
3821
0baab86b
EF		 3822
3823/**
3824 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3825 * @qc: Info associated with this ATA transaction.
3826 *
3827 * Writes the ATA_DMA_START flag to the DMA command register.
3828 *
3829 * May be used as the bmdma_start() entry in ata_port_operations.
3830 *
3831 * LOCKING:
3832 * spin_lock_irqsave(host_set lock)
3833 */
1da177e4
LT		 3834void ata_bmdma_start(struct ata_queued_cmd *qc)
3835{
3836 if (qc->ap->flags & ATA_FLAG_MMIO)
3837 ata_bmdma_start_mmio(qc);
3838 else
3839 ata_bmdma_start_pio(qc);
3840}
3841
0baab86b
EF		 3842
3843/**
3844 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3845 * @qc: Info associated with this ATA transaction.
3846 *
3847 * Writes address of PRD table to device's PRD Table Address
3848 * register, sets the DMA control register, and calls
3849 * ops->exec_command() to start the transfer.
3850 *
3851 * May be used as the bmdma_setup() entry in ata_port_operations.
3852 *
3853 * LOCKING:
3854 * spin_lock_irqsave(host_set lock)
3855 */
1da177e4
LT		 3856void ata_bmdma_setup(struct ata_queued_cmd *qc)
3857{
3858 if (qc->ap->flags & ATA_FLAG_MMIO)
3859 ata_bmdma_setup_mmio(qc);
3860 else
3861 ata_bmdma_setup_pio(qc);
3862}
3863
0baab86b
EF		 3864
3865/**
3866 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 3867 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3868 *
3869 * Clear interrupt and error flags in DMA status register.
3870 *
3871 * May be used as the irq_clear() entry in ata_port_operations.
3872 *
3873 * LOCKING:
3874 * spin_lock_irqsave(host_set lock)
3875 */
3876
1da177e4
LT		 3877void ata_bmdma_irq_clear(struct ata_port *ap)
3878{
3879 if (ap->flags & ATA_FLAG_MMIO) {
3880 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
3881 writeb(readb(mmio), mmio);
3882 } else {
3883 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
3884 outb(inb(addr), addr);
3885 }
3886
3887}
3888
0baab86b
EF		 3889
3890/**
3891 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 3892 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3893 *
3894 * Read and return BMDMA status register.
3895 *
3896 * May be used as the bmdma_status() entry in ata_port_operations.
3897 *
3898 * LOCKING:
3899 * spin_lock_irqsave(host_set lock)
3900 */
3901
1da177e4
LT		 3902u8 ata_bmdma_status(struct ata_port *ap)
3903{
3904 u8 host_stat;
3905 if (ap->flags & ATA_FLAG_MMIO) {
3906 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3907 host_stat = readb(mmio + ATA_DMA_STATUS);
3908 } else
ee500aab 3909 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 3910 return host_stat;
3911}
3912
0baab86b
EF		 3913
3914/**
3915 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 3916 * @qc: Command we are ending DMA for
0baab86b
EF		 3917 *
3918 * Clears the ATA_DMA_START flag in the dma control register
3919 *
3920 * May be used as the bmdma_stop() entry in ata_port_operations.
3921 *
3922 * LOCKING:
3923 * spin_lock_irqsave(host_set lock)
3924 */
3925
b73fc89f 3926void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 3927{
b73fc89f 3928 struct ata_port *ap = qc->ap;
1da177e4
LT		 3929 if (ap->flags & ATA_FLAG_MMIO) {
3930 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3931
3932 /* clear start/stop bit */
3933 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3934 mmio + ATA_DMA_CMD);
3935 } else {
3936 /* clear start/stop bit */
3937 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
3938 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3939 }
3940
3941 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3942 ata_altstatus(ap); /* dummy read */
3943}
3944
3945/**
3946 * ata_host_intr - Handle host interrupt for given (port, task)
3947 * @ap: Port on which interrupt arrived (possibly...)
3948 * @qc: Taskfile currently active in engine
3949 *
3950 * Handle host interrupt for given queued command. Currently,
3951 * only DMA interrupts are handled. All other commands are
3952 * handled via polling with interrupts disabled (nIEN bit).
3953 *
3954 * LOCKING:
3955 * spin_lock_irqsave(host_set lock)
3956 *
3957 * RETURNS:
3958 * One if interrupt was handled, zero if not (shared irq).
3959 */
3960
3961inline unsigned int ata_host_intr (struct ata_port *ap,
3962 struct ata_queued_cmd *qc)
3963{
3964 u8 status, host_stat;
3965
3966 switch (qc->tf.protocol) {
3967
3968 case ATA_PROT_DMA:
3969 case ATA_PROT_ATAPI_DMA:
3970 case ATA_PROT_ATAPI:
3971 /* check status of DMA engine */
3972 host_stat = ap->ops->bmdma_status(ap);
3973 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
3974
3975 /* if it's not our irq... */
3976 if (!(host_stat & ATA_DMA_INTR))
3977 goto idle_irq;
3978
3979 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3980 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3981
3982 /* fall through */
3983
3984 case ATA_PROT_ATAPI_NODATA:
3985 case ATA_PROT_NODATA:
3986 /* check altstatus */
3987 status = ata_altstatus(ap);
3988 if (status & ATA_BUSY)
3989 goto idle_irq;
3990
3991 /* check main status, clearing INTRQ */
3992 status = ata_chk_status(ap);
3993 if (unlikely(status & ATA_BUSY))
3994 goto idle_irq;
3995 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
3996 ap->id, qc->tf.protocol, status);
3997
3998 /* ack bmdma irq events */
3999 ap->ops->irq_clear(ap);
4000
4001 /* complete taskfile transaction */
a22e2eb0
AL		 4002 qc->err_mask |= ac_err_mask(status);
4003 ata_qc_complete(qc);
1da177e4
LT		 4004 break;
4005
4006 default:
4007 goto idle_irq;
4008 }
4009
4010 return 1; /* irq handled */
4011
4012idle_irq:
4013 ap->stats.idle_irq++;
4014
4015#ifdef ATA_IRQ_TRAP
4016 if ((ap->stats.idle_irq % 1000) == 0) {
4017 handled = 1;
4018 ata_irq_ack(ap, 0); /* debug trap */
4019 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
4020 }
4021#endif
4022 return 0; /* irq not handled */
4023}
4024
4025/**
4026 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4027 * @irq: irq line (unused)
4028 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4029 * @regs: unused
4030 *
0cba632b
JG		 4031 * Default interrupt handler for PCI IDE devices. Calls
4032 * ata_host_intr() for each port that is not disabled.
4033 *
1da177e4 4034 * LOCKING:
0cba632b 4035 * Obtains host_set lock during operation.
1da177e4
LT		 4036 *
4037 * RETURNS:
0cba632b 4038 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4039 */
4040
4041irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4042{
4043 struct ata_host_set *host_set = dev_instance;
4044 unsigned int i;
4045 unsigned int handled = 0;
4046 unsigned long flags;
4047
4048 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4049 spin_lock_irqsave(&host_set->lock, flags);
4050
4051 for (i = 0; i < host_set->n_ports; i++) {
4052 struct ata_port *ap;
4053
4054 ap = host_set->ports[i];
c1389503
TH		 4055 if (ap &&
4056 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 4057 struct ata_queued_cmd *qc;
4058
4059 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL		 4060 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
4061 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4062 handled |= ata_host_intr(ap, qc);
4063 }
4064 }
4065
4066 spin_unlock_irqrestore(&host_set->lock, flags);
4067
4068 return IRQ_RETVAL(handled);
4069}
4070
4071/**
4072 * atapi_packet_task - Write CDB bytes to hardware
4073 * @_data: Port to which ATAPI device is attached.
4074 *
4075 * When device has indicated its readiness to accept
4076 * a CDB, this function is called. Send the CDB.
4077 * If DMA is to be performed, exit immediately.
4078 * Otherwise, we are in polling mode, so poll
4079 * status under operation succeeds or fails.
4080 *
4081 * LOCKING:
4082 * Kernel thread context (may sleep)
4083 */
4084
4085static void atapi_packet_task(void *_data)
4086{
4087 struct ata_port *ap = _data;
4088 struct ata_queued_cmd *qc;
4089 u8 status;
4090
4091 qc = ata_qc_from_tag(ap, ap->active_tag);
4092 assert(qc != NULL);
4093 assert(qc->flags & ATA_QCFLAG_ACTIVE);
4094
4095 /* sleep-wait for BSY to clear */
4096 DPRINTK("busy wait\n");
d8fe452b
AL		 4097 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB)) {
4098 qc->err_mask |= AC_ERR_ATA_BUS;
4099 goto err_out;
4100 }
1da177e4
LT		 4101
4102 /* make sure DRQ is set */
4103 status = ata_chk_status(ap);
d8fe452b
AL		 4104 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ) {
4105 qc->err_mask |= AC_ERR_ATA_BUS;
1da177e4 4106 goto err_out;
d8fe452b 4107 }
1da177e4
LT		 4108
4109 /* send SCSI cdb */
4110 DPRINTK("send cdb\n");
4111 assert(ap->cdb_len >= 12);
1da177e4 4112
c1389503
TH		 4113 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
4114 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
4115 unsigned long flags;
1da177e4 4116
c1389503
TH		 4117 /* Once we're done issuing command and kicking bmdma,
4118 * irq handler takes over. To not lose irq, we need
4119 * to clear NOINTR flag before sending cdb, but
4120 * interrupt handler shouldn't be invoked before we're
4121 * finished. Hence, the following locking.
4122 */
4123 spin_lock_irqsave(&ap->host_set->lock, flags);
4124 ap->flags &= ~ATA_FLAG_NOINTR;
4125 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
4126 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
4127 ap->ops->bmdma_start(qc); /* initiate bmdma */
4128 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4129 } else {
4130 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
1da177e4 4131
c1389503 4132 /* PIO commands are handled by polling */
14be71f4 4133 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 4134 queue_work(ata_wq, &ap->pio_task);
4135 }
4136
4137 return;
4138
4139err_out:
a22e2eb0 4140 ata_poll_qc_complete(qc);
1da177e4
LT		 4141}
4142
0baab86b
EF		 4143
4144/**
4145 * ata_port_start - Set port up for dma.
4146 * @ap: Port to initialize
4147 *
4148 * Called just after data structures for each port are
4149 * initialized. Allocates space for PRD table.
4150 *
4151 * May be used as the port_start() entry in ata_port_operations.
4152 *
4153 * LOCKING:
6f0ef4fa 4154 * Inherited from caller.
0baab86b
EF		 4155 */
4156
1da177e4
LT		 4157int ata_port_start (struct ata_port *ap)
4158{
4159 struct device *dev = ap->host_set->dev;
6037d6bb 4160 int rc;
1da177e4
LT		 4161
4162 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4163 if (!ap->prd)
4164 return -ENOMEM;
4165
6037d6bb
JG		 4166 rc = ata_pad_alloc(ap, dev);
4167 if (rc) {
cedc9a47 4168 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4169 return rc;
cedc9a47
JG		 4170 }
4171
1da177e4
LT		 4172 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4173
4174 return 0;
4175}
4176
0baab86b
EF		 4177
4178/**
4179 * ata_port_stop - Undo ata_port_start()
4180 * @ap: Port to shut down
4181 *
4182 * Frees the PRD table.
4183 *
4184 * May be used as the port_stop() entry in ata_port_operations.
4185 *
4186 * LOCKING:
6f0ef4fa 4187 * Inherited from caller.
0baab86b
EF		 4188 */
4189
1da177e4
LT		 4190void ata_port_stop (struct ata_port *ap)
4191{
4192 struct device *dev = ap->host_set->dev;
4193
4194 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4195 ata_pad_free(ap, dev);
1da177e4
LT		 4196}
4197
aa8f0dc6
JG		 4198void ata_host_stop (struct ata_host_set *host_set)
4199{
4200 if (host_set->mmio_base)
4201 iounmap(host_set->mmio_base);
4202}
4203
4204
1da177e4
LT		 4205/**
4206 * ata_host_remove - Unregister SCSI host structure with upper layers
4207 * @ap: Port to unregister
4208 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4209 *
4210 * LOCKING:
6f0ef4fa 4211 * Inherited from caller.
1da177e4
LT		 4212 */
4213
4214static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4215{
4216 struct Scsi_Host *sh = ap->host;
4217
4218 DPRINTK("ENTER\n");
4219
4220 if (do_unregister)
4221 scsi_remove_host(sh);
4222
4223 ap->ops->port_stop(ap);
4224}
4225
4226/**
4227 * ata_host_init - Initialize an ata_port structure
4228 * @ap: Structure to initialize
4229 * @host: associated SCSI mid-layer structure
4230 * @host_set: Collection of hosts to which @ap belongs
4231 * @ent: Probe information provided by low-level driver
4232 * @port_no: Port number associated with this ata_port
4233 *
0cba632b
JG		 4234 * Initialize a new ata_port structure, and its associated
4235 * scsi_host.
4236 *
1da177e4 4237 * LOCKING:
0cba632b 4238 * Inherited from caller.
1da177e4
LT		 4239 */
4240
4241static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4242 struct ata_host_set *host_set,
057ace5e 4243 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4244{
4245 unsigned int i;
4246
4247 host->max_id = 16;
4248 host->max_lun = 1;
4249 host->max_channel = 1;
4250 host->unique_id = ata_unique_id++;
4251 host->max_cmd_len = 12;
12413197 4252
1da177e4
LT		 4253 ap->flags = ATA_FLAG_PORT_DISABLED;
4254 ap->id = host->unique_id;
4255 ap->host = host;
4256 ap->ctl = ATA_DEVCTL_OBS;
4257 ap->host_set = host_set;
4258 ap->port_no = port_no;
4259 ap->hard_port_no =
4260 ent->legacy_mode ? ent->hard_port_no : port_no;
4261 ap->pio_mask = ent->pio_mask;
4262 ap->mwdma_mask = ent->mwdma_mask;
4263 ap->udma_mask = ent->udma_mask;
4264 ap->flags |= ent->host_flags;
4265 ap->ops = ent->port_ops;
4266 ap->cbl = ATA_CBL_NONE;
4267 ap->active_tag = ATA_TAG_POISON;
4268 ap->last_ctl = 0xFF;
4269
4270 INIT_WORK(&ap->packet_task, atapi_packet_task, ap);
4271 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
4272
4273 for (i = 0; i < ATA_MAX_DEVICES; i++)
4274 ap->device[i].devno = i;
4275
4276#ifdef ATA_IRQ_TRAP
4277 ap->stats.unhandled_irq = 1;
4278 ap->stats.idle_irq = 1;
4279#endif
4280
4281 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4282}
4283
4284/**
4285 * ata_host_add - Attach low-level ATA driver to system
4286 * @ent: Information provided by low-level driver
4287 * @host_set: Collections of ports to which we add
4288 * @port_no: Port number associated with this host
4289 *
0cba632b
JG		 4290 * Attach low-level ATA driver to system.
4291 *
1da177e4 4292 * LOCKING:
0cba632b 4293 * PCI/etc. bus probe sem.
1da177e4
LT		 4294 *
4295 * RETURNS:
0cba632b 4296 * New ata_port on success, for NULL on error.
1da177e4
LT		 4297 */
4298
057ace5e 4299static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4300 struct ata_host_set *host_set,
4301 unsigned int port_no)
4302{
4303 struct Scsi_Host *host;
4304 struct ata_port *ap;
4305 int rc;
4306
4307 DPRINTK("ENTER\n");
4308 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4309 if (!host)
4310 return NULL;
4311
4312 ap = (struct ata_port *) &host->hostdata[0];
4313
4314 ata_host_init(ap, host, host_set, ent, port_no);
4315
4316 rc = ap->ops->port_start(ap);
4317 if (rc)
4318 goto err_out;
4319
4320 return ap;
4321
4322err_out:
4323 scsi_host_put(host);
4324 return NULL;
4325}
4326
4327/**
0cba632b
JG		 4328 * ata_device_add - Register hardware device with ATA and SCSI layers
4329 * @ent: Probe information describing hardware device to be registered
4330 *
4331 * This function processes the information provided in the probe
4332 * information struct @ent, allocates the necessary ATA and SCSI
4333 * host information structures, initializes them, and registers
4334 * everything with requisite kernel subsystems.
4335 *
4336 * This function requests irqs, probes the ATA bus, and probes
4337 * the SCSI bus.
1da177e4
LT		 4338 *
4339 * LOCKING:
0cba632b 4340 * PCI/etc. bus probe sem.
1da177e4
LT		 4341 *
4342 * RETURNS:
0cba632b 4343 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4344 */
4345
057ace5e 4346int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4347{
4348 unsigned int count = 0, i;
4349 struct device *dev = ent->dev;
4350 struct ata_host_set *host_set;
4351
4352 DPRINTK("ENTER\n");
4353 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4354 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4355 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4356 if (!host_set)
4357 return 0;
1da177e4
LT		 4358 spin_lock_init(&host_set->lock);
4359
4360 host_set->dev = dev;
4361 host_set->n_ports = ent->n_ports;
4362 host_set->irq = ent->irq;
4363 host_set->mmio_base = ent->mmio_base;
4364 host_set->private_data = ent->private_data;
4365 host_set->ops = ent->port_ops;
4366
4367 /* register each port bound to this device */
4368 for (i = 0; i < ent->n_ports; i++) {
4369 struct ata_port *ap;
4370 unsigned long xfer_mode_mask;
4371
4372 ap = ata_host_add(ent, host_set, i);
4373 if (!ap)
4374 goto err_out;
4375
4376 host_set->ports[i] = ap;
4377 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4378 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4379 (ap->pio_mask << ATA_SHIFT_PIO);
4380
4381 /* print per-port info to dmesg */
4382 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4383 "bmdma 0x%lX irq %lu\n",
4384 ap->id,
4385 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4386 ata_mode_string(xfer_mode_mask),
4387 ap->ioaddr.cmd_addr,
4388 ap->ioaddr.ctl_addr,
4389 ap->ioaddr.bmdma_addr,
4390 ent->irq);
4391
4392 ata_chk_status(ap);
4393 host_set->ops->irq_clear(ap);
4394 count++;
4395 }
4396
57f3bda8
RD		 4397 if (!count)
4398 goto err_free_ret;
1da177e4
LT		 4399
4400 /* obtain irq, that is shared between channels */
4401 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4402 DRV_NAME, host_set))
4403 goto err_out;
4404
4405 /* perform each probe synchronously */
4406 DPRINTK("probe begin\n");
4407 for (i = 0; i < count; i++) {
4408 struct ata_port *ap;
4409 int rc;
4410
4411 ap = host_set->ports[i];
4412
4413 DPRINTK("ata%u: probe begin\n", ap->id);
4414 rc = ata_bus_probe(ap);
4415 DPRINTK("ata%u: probe end\n", ap->id);
4416
4417 if (rc) {
4418 /* FIXME: do something useful here?
4419 * Current libata behavior will
4420 * tear down everything when
4421 * the module is removed
4422 * or the h/w is unplugged.
4423 */
4424 }
4425
4426 rc = scsi_add_host(ap->host, dev);
4427 if (rc) {
4428 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4429 ap->id);
4430 /* FIXME: do something useful here */
4431 /* FIXME: handle unconditional calls to
4432 * scsi_scan_host and ata_host_remove, below,
4433 * at the very least
4434 */
4435 }
4436 }
4437
4438 /* probes are done, now scan each port's disk(s) */
4439 DPRINTK("probe begin\n");
4440 for (i = 0; i < count; i++) {
4441 struct ata_port *ap = host_set->ports[i];
4442
644dd0cc 4443 ata_scsi_scan_host(ap);
1da177e4
LT		 4444 }
4445
4446 dev_set_drvdata(dev, host_set);
4447
4448 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4449 return ent->n_ports; /* success */
4450
4451err_out:
4452 for (i = 0; i < count; i++) {
4453 ata_host_remove(host_set->ports[i], 1);
4454 scsi_host_put(host_set->ports[i]->host);
4455 }
57f3bda8 4456err_free_ret:
1da177e4
LT		 4457 kfree(host_set);
4458 VPRINTK("EXIT, returning 0\n");
4459 return 0;
4460}
4461
17b14451
AC		 4462/**
4463 * ata_host_set_remove - PCI layer callback for device removal
4464 * @host_set: ATA host set that was removed
4465 *
4466 * Unregister all objects associated with this host set. Free those
4467 * objects.
4468 *
4469 * LOCKING:
4470 * Inherited from calling layer (may sleep).
4471 */
4472
17b14451
AC		 4473void ata_host_set_remove(struct ata_host_set *host_set)
4474{
4475 struct ata_port *ap;
4476 unsigned int i;
4477
4478 for (i = 0; i < host_set->n_ports; i++) {
4479 ap = host_set->ports[i];
4480 scsi_remove_host(ap->host);
4481 }
4482
4483 free_irq(host_set->irq, host_set);
4484
4485 for (i = 0; i < host_set->n_ports; i++) {
4486 ap = host_set->ports[i];
4487
4488 ata_scsi_release(ap->host);
4489
4490 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4491 struct ata_ioports *ioaddr = &ap->ioaddr;
4492
4493 if (ioaddr->cmd_addr == 0x1f0)
4494 release_region(0x1f0, 8);
4495 else if (ioaddr->cmd_addr == 0x170)
4496 release_region(0x170, 8);
4497 }
4498
4499 scsi_host_put(ap->host);
4500 }
4501
4502 if (host_set->ops->host_stop)
4503 host_set->ops->host_stop(host_set);
4504
4505 kfree(host_set);
4506}
4507
1da177e4
LT		 4508/**
4509 * ata_scsi_release - SCSI layer callback hook for host unload
4510 * @host: libata host to be unloaded
4511 *
4512 * Performs all duties necessary to shut down a libata port...
4513 * Kill port kthread, disable port, and release resources.
4514 *
4515 * LOCKING:
4516 * Inherited from SCSI layer.
4517 *
4518 * RETURNS:
4519 * One.
4520 */
4521
4522int ata_scsi_release(struct Scsi_Host *host)
4523{
4524 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
4525
4526 DPRINTK("ENTER\n");
4527
4528 ap->ops->port_disable(ap);
4529 ata_host_remove(ap, 0);
4530
4531 DPRINTK("EXIT\n");
4532 return 1;
4533}
4534
4535/**
4536 * ata_std_ports - initialize ioaddr with standard port offsets.
4537 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4538 *
4539 * Utility function which initializes data_addr, error_addr,
4540 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4541 * device_addr, status_addr, and command_addr to standard offsets
4542 * relative to cmd_addr.
4543 *
4544 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4545 */
0baab86b 4546
1da177e4
LT		 4547void ata_std_ports(struct ata_ioports *ioaddr)
4548{
4549 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4550 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4551 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4552 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4553 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4554 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4555 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4556 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4557 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4558 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4559}
4560
4561static struct ata_probe_ent *
057ace5e 4562ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
1da177e4
LT		 4563{
4564 struct ata_probe_ent *probe_ent;
4565
57f3bda8 4566 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1da177e4
LT		 4567 if (!probe_ent) {
4568 printk(KERN_ERR DRV_NAME "(%s): out of memory\n",
4569 kobject_name(&(dev->kobj)));
4570 return NULL;
4571 }
4572
1da177e4
LT		 4573 INIT_LIST_HEAD(&probe_ent->node);
4574 probe_ent->dev = dev;
4575
4576 probe_ent->sht = port->sht;
4577 probe_ent->host_flags = port->host_flags;
4578 probe_ent->pio_mask = port->pio_mask;
4579 probe_ent->mwdma_mask = port->mwdma_mask;
4580 probe_ent->udma_mask = port->udma_mask;
4581 probe_ent->port_ops = port->port_ops;
4582
4583 return probe_ent;
4584}
4585
0baab86b
EF		 4586
4587
374b1873
JG		 4588#ifdef CONFIG_PCI
4589
4590void ata_pci_host_stop (struct ata_host_set *host_set)
4591{
4592 struct pci_dev *pdev = to_pci_dev(host_set->dev);
4593
4594 pci_iounmap(pdev, host_set->mmio_base);
4595}
4596
0baab86b
EF		 4597/**
4598 * ata_pci_init_native_mode - Initialize native-mode driver
4599 * @pdev: pci device to be initialized
4600 * @port: array[2] of pointers to port info structures.
47a86593 4601 * @ports: bitmap of ports present
0baab86b
EF		 4602 *
4603 * Utility function which allocates and initializes an
4604 * ata_probe_ent structure for a standard dual-port
4605 * PIO-based IDE controller. The returned ata_probe_ent
4606 * structure can be passed to ata_device_add(). The returned
4607 * ata_probe_ent structure should then be freed with kfree().
47a86593
AC		 4608 *
4609 * The caller need only pass the address of the primary port, the
4610 * secondary will be deduced automatically. If the device has non
4611 * standard secondary port mappings this function can be called twice,
4612 * once for each interface.
0baab86b
EF		 4613 */
4614
1da177e4 4615struct ata_probe_ent *
47a86593 4616ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports)
1da177e4
LT		 4617{
4618 struct ata_probe_ent *probe_ent =
4619 ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
47a86593
AC		 4620 int p = 0;
4621
1da177e4
LT		 4622 if (!probe_ent)
4623 return NULL;
4624
1da177e4
LT		 4625 probe_ent->irq = pdev->irq;
4626 probe_ent->irq_flags = SA_SHIRQ;
e99f8b5e 4627 probe_ent->private_data = port[0]->private_data;
1da177e4 4628
47a86593
AC		 4629 if (ports & ATA_PORT_PRIMARY) {
4630 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0);
4631 probe_ent->port[p].altstatus_addr =
4632 probe_ent->port[p].ctl_addr =
4633 pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
4634 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4);
4635 ata_std_ports(&probe_ent->port[p]);
4636 p++;
4637 }
1da177e4 4638
47a86593
AC		 4639 if (ports & ATA_PORT_SECONDARY) {
4640 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2);
4641 probe_ent->port[p].altstatus_addr =
4642 probe_ent->port[p].ctl_addr =
4643 pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
4644 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4) + 8;
4645 ata_std_ports(&probe_ent->port[p]);
4646 p++;
4647 }
1da177e4 4648
47a86593 4649 probe_ent->n_ports = p;
1da177e4
LT		 4650 return probe_ent;
4651}
4652
0f0d5192 4653static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, struct ata_port_info *port, int port_num)
1da177e4 4654{
47a86593 4655 struct ata_probe_ent *probe_ent;
1da177e4 4656
0f0d5192 4657 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port);
1da177e4
LT		 4658 if (!probe_ent)
4659 return NULL;
1da177e4 4660
1da177e4 4661 probe_ent->legacy_mode = 1;
47a86593
AC		 4662 probe_ent->n_ports = 1;
4663 probe_ent->hard_port_no = port_num;
e99f8b5e 4664 probe_ent->private_data = port->private_data;
47a86593
AC		 4665
4666 switch(port_num)
4667 {
4668 case 0:
4669 probe_ent->irq = 14;
4670 probe_ent->port[0].cmd_addr = 0x1f0;
4671 probe_ent->port[0].altstatus_addr =
4672 probe_ent->port[0].ctl_addr = 0x3f6;
4673 break;
4674 case 1:
4675 probe_ent->irq = 15;
4676 probe_ent->port[0].cmd_addr = 0x170;
4677 probe_ent->port[0].altstatus_addr =
4678 probe_ent->port[0].ctl_addr = 0x376;
4679 break;
4680 }
4681 probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4) + 8 * port_num;
1da177e4 4682 ata_std_ports(&probe_ent->port[0]);
1da177e4
LT		 4683 return probe_ent;
4684}
4685
4686/**
4687 * ata_pci_init_one - Initialize/register PCI IDE host controller
4688 * @pdev: Controller to be initialized
4689 * @port_info: Information from low-level host driver
4690 * @n_ports: Number of ports attached to host controller
4691 *
0baab86b
EF		 4692 * This is a helper function which can be called from a driver's
4693 * xxx_init_one() probe function if the hardware uses traditional
4694 * IDE taskfile registers.
4695 *
4696 * This function calls pci_enable_device(), reserves its register
4697 * regions, sets the dma mask, enables bus master mode, and calls
4698 * ata_device_add()
4699 *
1da177e4
LT		 4700 * LOCKING:
4701 * Inherited from PCI layer (may sleep).
4702 *
4703 * RETURNS:
0cba632b 4704 * Zero on success, negative on errno-based value on error.
1da177e4
LT		 4705 */
4706
4707int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info,
4708 unsigned int n_ports)
4709{
47a86593 4710 struct ata_probe_ent *probe_ent = NULL, *probe_ent2 = NULL;
1da177e4
LT		 4711 struct ata_port_info *port[2];
4712 u8 tmp8, mask;
4713 unsigned int legacy_mode = 0;
4714 int disable_dev_on_err = 1;
4715 int rc;
4716
4717 DPRINTK("ENTER\n");
4718
4719 port[0] = port_info[0];
4720 if (n_ports > 1)
4721 port[1] = port_info[1];
4722 else
4723 port[1] = port[0];
4724
4725 if ((port[0]->host_flags & ATA_FLAG_NO_LEGACY) == 0
4726 && (pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
47a86593 4727 /* TODO: What if one channel is in native mode ... */
1da177e4
LT		 4728 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
4729 mask = (1 << 2) | (1 << 0);
4730 if ((tmp8 & mask) != mask)
4731 legacy_mode = (1 << 3);
4732 }
4733
4734 /* FIXME... */
47a86593
AC		 4735 if ((!legacy_mode) && (n_ports > 2)) {
4736 printk(KERN_ERR "ata: BUG: native mode, n_ports > 2\n");
4737 n_ports = 2;
4738 /* For now */
1da177e4
LT		 4739 }
4740
47a86593
AC		 4741 /* FIXME: Really for ATA it isn't safe because the device may be
4742 multi-purpose and we want to leave it alone if it was already
4743 enabled. Secondly for shared use as Arjan says we want refcounting
4744
4745 Checking dev->is_enabled is insufficient as this is not set at
4746 boot for the primary video which is BIOS enabled
4747 */
4748
1da177e4
LT		 4749 rc = pci_enable_device(pdev);
4750 if (rc)
4751 return rc;
4752
4753 rc = pci_request_regions(pdev, DRV_NAME);
4754 if (rc) {
4755 disable_dev_on_err = 0;
4756 goto err_out;
4757 }
4758
47a86593 4759 /* FIXME: Should use platform specific mappers for legacy port ranges */
1da177e4
LT		 4760 if (legacy_mode) {
4761 if (!request_region(0x1f0, 8, "libata")) {
4762 struct resource *conflict, res;
4763 res.start = 0x1f0;
4764 res.end = 0x1f0 + 8 - 1;
4765 conflict = ____request_resource(&ioport_resource, &res);
4766 if (!strcmp(conflict->name, "libata"))
4767 legacy_mode |= (1 << 0);
4768 else {
4769 disable_dev_on_err = 0;
4770 printk(KERN_WARNING "ata: 0x1f0 IDE port busy\n");
4771 }
4772 } else
4773 legacy_mode |= (1 << 0);
4774
4775 if (!request_region(0x170, 8, "libata")) {
4776 struct resource *conflict, res;
4777 res.start = 0x170;
4778 res.end = 0x170 + 8 - 1;
4779 conflict = ____request_resource(&ioport_resource, &res);
4780 if (!strcmp(conflict->name, "libata"))
4781 legacy_mode |= (1 << 1);
4782 else {
4783 disable_dev_on_err = 0;
4784 printk(KERN_WARNING "ata: 0x170 IDE port busy\n");
4785 }
4786 } else
4787 legacy_mode |= (1 << 1);
4788 }
4789
4790 /* we have legacy mode, but all ports are unavailable */
4791 if (legacy_mode == (1 << 3)) {
4792 rc = -EBUSY;
4793 goto err_out_regions;
4794 }
4795
4796 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
4797 if (rc)
4798 goto err_out_regions;
4799 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
4800 if (rc)
4801 goto err_out_regions;
4802
4803 if (legacy_mode) {
47a86593 4804 if (legacy_mode & (1 << 0))
0f0d5192 4805 probe_ent = ata_pci_init_legacy_port(pdev, port[0], 0);
47a86593 4806 if (legacy_mode & (1 << 1))
0f0d5192 4807 probe_ent2 = ata_pci_init_legacy_port(pdev, port[1], 1);
47a86593
AC		 4808 } else {
4809 if (n_ports == 2)
4810 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
4811 else
4812 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY);
4813 }
4814 if (!probe_ent && !probe_ent2) {
1da177e4
LT		 4815 rc = -ENOMEM;
4816 goto err_out_regions;
4817 }
4818
4819 pci_set_master(pdev);
4820
4821 /* FIXME: check ata_device_add return */
4822 if (legacy_mode) {
4823 if (legacy_mode & (1 << 0))
4824 ata_device_add(probe_ent);
4825 if (legacy_mode & (1 << 1))
4826 ata_device_add(probe_ent2);
4827 } else
4828 ata_device_add(probe_ent);
4829
4830 kfree(probe_ent);
4831 kfree(probe_ent2);
4832
4833 return 0;
4834
4835err_out_regions:
4836 if (legacy_mode & (1 << 0))
4837 release_region(0x1f0, 8);
4838 if (legacy_mode & (1 << 1))
4839 release_region(0x170, 8);
4840 pci_release_regions(pdev);
4841err_out:
4842 if (disable_dev_on_err)
4843 pci_disable_device(pdev);
4844 return rc;
4845}
4846
4847/**
4848 * ata_pci_remove_one - PCI layer callback for device removal
4849 * @pdev: PCI device that was removed
4850 *
4851 * PCI layer indicates to libata via this hook that
6f0ef4fa 4852 * hot-unplug or module unload event has occurred.
1da177e4
LT		 4853 * Handle this by unregistering all objects associated
4854 * with this PCI device. Free those objects. Then finally
4855 * release PCI resources and disable device.
4856 *
4857 * LOCKING:
4858 * Inherited from PCI layer (may sleep).
4859 */
4860
4861void ata_pci_remove_one (struct pci_dev *pdev)
4862{
4863 struct device *dev = pci_dev_to_dev(pdev);
4864 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 4865
17b14451 4866 ata_host_set_remove(host_set);
1da177e4
LT		 4867 pci_release_regions(pdev);
4868 pci_disable_device(pdev);
4869 dev_set_drvdata(dev, NULL);
4870}
4871
4872/* move to PCI subsystem */
057ace5e 4873int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 4874{
4875 unsigned long tmp = 0;
4876
4877 switch (bits->width) {
4878 case 1: {
4879 u8 tmp8 = 0;
4880 pci_read_config_byte(pdev, bits->reg, &tmp8);
4881 tmp = tmp8;
4882 break;
4883 }
4884 case 2: {
4885 u16 tmp16 = 0;
4886 pci_read_config_word(pdev, bits->reg, &tmp16);
4887 tmp = tmp16;
4888 break;
4889 }
4890 case 4: {
4891 u32 tmp32 = 0;
4892 pci_read_config_dword(pdev, bits->reg, &tmp32);
4893 tmp = tmp32;
4894 break;
4895 }
4896
4897 default:
4898 return -EINVAL;
4899 }
4900
4901 tmp &= bits->mask;
4902
4903 return (tmp == bits->val) ? 1 : 0;
4904}
4905#endif /* CONFIG_PCI */
4906
4907
1da177e4
LT		 4908static int __init ata_init(void)
4909{
4910 ata_wq = create_workqueue("ata");
4911 if (!ata_wq)
4912 return -ENOMEM;
4913
4914 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
4915 return 0;
4916}
4917
4918static void __exit ata_exit(void)
4919{
4920 destroy_workqueue(ata_wq);
4921}
4922
4923module_init(ata_init);
4924module_exit(ata_exit);
4925
67846b30
JG		 4926static unsigned long ratelimit_time;
4927static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
4928
4929int ata_ratelimit(void)
4930{
4931 int rc;
4932 unsigned long flags;
4933
4934 spin_lock_irqsave(&ata_ratelimit_lock, flags);
4935
4936 if (time_after(jiffies, ratelimit_time)) {
4937 rc = 1;
4938 ratelimit_time = jiffies + (HZ/5);
4939 } else
4940 rc = 0;
4941
4942 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
4943
4944 return rc;
4945}
4946
1da177e4
LT		 4947/*
4948 * libata is essentially a library of internal helper functions for
4949 * low-level ATA host controller drivers. As such, the API/ABI is
4950 * likely to change as new drivers are added and updated.
4951 * Do not depend on ABI/API stability.
4952 */
4953
4954EXPORT_SYMBOL_GPL(ata_std_bios_param);
4955EXPORT_SYMBOL_GPL(ata_std_ports);
4956EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 4957EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 4958EXPORT_SYMBOL_GPL(ata_sg_init);
4959EXPORT_SYMBOL_GPL(ata_sg_init_one);
4960EXPORT_SYMBOL_GPL(ata_qc_complete);
4961EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
4962EXPORT_SYMBOL_GPL(ata_eng_timeout);
4963EXPORT_SYMBOL_GPL(ata_tf_load);
4964EXPORT_SYMBOL_GPL(ata_tf_read);
4965EXPORT_SYMBOL_GPL(ata_noop_dev_select);
4966EXPORT_SYMBOL_GPL(ata_std_dev_select);
4967EXPORT_SYMBOL_GPL(ata_tf_to_fis);
4968EXPORT_SYMBOL_GPL(ata_tf_from_fis);
4969EXPORT_SYMBOL_GPL(ata_check_status);
4970EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 4971EXPORT_SYMBOL_GPL(ata_exec_command);
4972EXPORT_SYMBOL_GPL(ata_port_start);
4973EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 4974EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 4975EXPORT_SYMBOL_GPL(ata_interrupt);
4976EXPORT_SYMBOL_GPL(ata_qc_prep);
4977EXPORT_SYMBOL_GPL(ata_bmdma_setup);
4978EXPORT_SYMBOL_GPL(ata_bmdma_start);
4979EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
4980EXPORT_SYMBOL_GPL(ata_bmdma_status);
4981EXPORT_SYMBOL_GPL(ata_bmdma_stop);
4982EXPORT_SYMBOL_GPL(ata_port_probe);
4983EXPORT_SYMBOL_GPL(sata_phy_reset);
4984EXPORT_SYMBOL_GPL(__sata_phy_reset);
4985EXPORT_SYMBOL_GPL(ata_bus_reset);
4986EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 4987EXPORT_SYMBOL_GPL(ata_ratelimit);
1da177e4
LT		 4988EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
4989EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
4990EXPORT_SYMBOL_GPL(ata_scsi_error);
4991EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
4992EXPORT_SYMBOL_GPL(ata_scsi_release);
4993EXPORT_SYMBOL_GPL(ata_host_intr);
4994EXPORT_SYMBOL_GPL(ata_dev_classify);
4995EXPORT_SYMBOL_GPL(ata_dev_id_string);
6f2f3812 4996EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4
LT		 4997EXPORT_SYMBOL_GPL(ata_scsi_simulate);
4998
452503f9
AC		 4999EXPORT_SYMBOL_GPL(ata_timing_compute);
5000EXPORT_SYMBOL_GPL(ata_timing_merge);
5001
1da177e4
LT		 5002#ifdef CONFIG_PCI
5003EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 5004EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 5005EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
5006EXPORT_SYMBOL_GPL(ata_pci_init_one);
5007EXPORT_SYMBOL_GPL(ata_pci_remove_one);
5008#endif /* CONFIG_PCI */
kernel source for telekom puls (alcatel/mediatek)