projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] ipr: define new offsets to registers for the next generation chip
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT		 1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
fa195afe 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
1da177e4
LT		 23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <linux/types.h>
30#include <linux/completion.h>
35a39691 31#include <linux/libata.h>
1da177e4
LT		 32#include <linux/list.h>
33#include <linux/kref.h>
34#include <scsi/scsi.h>
35#include <scsi/scsi_cmnd.h>
36
37/*
38 * Literals
39 */
95fecd90
WB		 40#define IPR_DRIVER_VERSION "2.4.3"
41#define IPR_DRIVER_DATE "(June 10, 2009)"
1da177e4 42
1da177e4
LT		 43/*
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
47 */
48#define IPR_MAX_CMD_PER_LUN 6
b5145d25 49#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT		 50
51/*
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
54 */
55#define IPR_NUM_BASE_CMD_BLKS 100
56
60e7486b 57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
185eb31c 58#define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A
60e7486b 59
1da177e4
LT		 60#define IPR_SUBS_DEV_ID_2780 0x0264
61#define IPR_SUBS_DEV_ID_5702 0x0266
62#define IPR_SUBS_DEV_ID_5703 0x0278
63#define IPR_SUBS_DEV_ID_572E 0x028D
64#define IPR_SUBS_DEV_ID_573E 0x02D3
65#define IPR_SUBS_DEV_ID_573D 0x02D4
66#define IPR_SUBS_DEV_ID_571A 0x02C0
67#define IPR_SUBS_DEV_ID_571B 0x02BE
68#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436
BK		 69#define IPR_SUBS_DEV_ID_571F 0x02D5
70#define IPR_SUBS_DEV_ID_572A 0x02C1
71#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 72#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c
BK		 73#define IPR_SUBS_DEV_ID_574D 0x030B
74#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 75#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 76#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c
BK		 77#define IPR_SUBS_DEV_ID_575D 0x033E
78#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK		 79#define IPR_SUBS_DEV_ID_57B7 0x0360
80#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4
LT		 81
82#define IPR_NAME "ipr"
83
84/*
85 * Return codes
86 */
87#define IPR_RC_JOB_CONTINUE 1
88#define IPR_RC_JOB_RETURN 2
89
90/*
91 * IOASCs
92 */
93#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 94#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT		 95#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
96#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
97#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
98#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
99#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
100#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 101#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 102#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb
BK		 103#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
104#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT		 105#define IPR_IOASC_BUS_WAS_RESET 0x06290000
106#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
107#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
108
109#define IPR_FIRST_DRIVER_IOASC 0x10000000
110#define IPR_IOASC_IOA_WAS_RESET 0x10000001
111#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
112
5469cb5b
BK		 113/* Driver data flags */
114#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
463fc696 115#define IPR_USE_PCI_WARM_RESET 0x00000002
5469cb5b 116
ac719aba 117#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT		 118#define IPR_NUM_LOG_HCAMS 2
119#define IPR_NUM_CFG_CHG_HCAMS 2
120#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
d71a8b0c 121#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT		 122#define IPR_MAX_NUM_LUNS_PER_TARGET 256
123#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
124#define IPR_VSET_BUS 0xff
125#define IPR_IOA_BUS 0xff
126#define IPR_IOA_TARGET 0xff
127#define IPR_IOA_LUN 0xff
b5145d25 128#define IPR_MAX_NUM_BUSES 16
1da177e4
LT		 129#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
130
131#define IPR_NUM_RESET_RELOAD_RETRIES 3
132
133/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
134#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
135 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
136
137#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
138#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
139 IPR_NUM_INTERNAL_CMD_BLKS)
140
141#define IPR_MAX_PHYSICAL_DEVS 192
142
143#define IPR_MAX_SGLIST 64
144#define IPR_IOA_MAX_SECTORS 32767
145#define IPR_VSET_MAX_SECTORS 512
146#define IPR_MAX_CDB_LEN 16
3feeb89d 147#define IPR_MAX_HRRQ_RETRIES 3
1da177e4
LT		 148
149#define IPR_DEFAULT_BUS_WIDTH 16
150#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
151#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
152#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
153#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
154
155#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 156#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT		 157#define IPR_IOA_RES_ADDR 0x00ffffff
158
159/*
160 * Adapter Commands
161 */
162#define IPR_QUERY_RSRC_STATE 0xC2
163#define IPR_RESET_DEVICE 0xC3
164#define IPR_RESET_TYPE_SELECT 0x80
165#define IPR_LUN_RESET 0x40
166#define IPR_TARGET_RESET 0x20
167#define IPR_BUS_RESET 0x10
b5145d25 168#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT		 169#define IPR_ID_HOST_RR_Q 0xC4
170#define IPR_QUERY_IOA_CONFIG 0xC5
171#define IPR_CANCEL_ALL_REQUESTS 0xCE
172#define IPR_HOST_CONTROLLED_ASYNC 0xCF
173#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
174#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
175#define IPR_SET_SUPPORTED_DEVICES 0xFB
176#define IPR_IOA_SHUTDOWN 0xF7
177#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
178
179/*
180 * Timeouts
181 */
182#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
183#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
184#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
ac09c349 185#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
1da177e4
LT		 186#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
187#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
188#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
189#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
190#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
191#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
192#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
193#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 194#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT		 195#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
196#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
197#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
463fc696 198#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
1da177e4
LT		 199#define IPR_DUMP_TIMEOUT (15 * HZ)
200
201/*
202 * SCSI Literals
203 */
204#define IPR_VENDOR_ID_LEN 8
205#define IPR_PROD_ID_LEN 16
206#define IPR_SERIAL_NUM_LEN 8
207
208/*
209 * Hardware literals
210 */
211#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
212#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
213#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
214#define IPR_GET_FMT2_BAR_SEL(mbx) \
215(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
216#define IPR_SDT_FMT2_BAR0_SEL 0x0
217#define IPR_SDT_FMT2_BAR1_SEL 0x1
218#define IPR_SDT_FMT2_BAR2_SEL 0x2
219#define IPR_SDT_FMT2_BAR3_SEL 0x3
220#define IPR_SDT_FMT2_BAR4_SEL 0x4
221#define IPR_SDT_FMT2_BAR5_SEL 0x5
222#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
223#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
224#define IPR_DOORBELL 0x82800000
3d1d0da6 225#define IPR_RUNTIME_RESET 0x40000000
1da177e4
LT		 226
227#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
228#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
229#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
230#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
231#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
232#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
233#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
234#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
235#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
236#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
237#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
238
239#define IPR_PCII_ERROR_INTERRUPTS \
240(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
241IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
242
243#define IPR_PCII_OPER_INTERRUPTS \
244(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
245
246#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
247#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
248
249#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
250#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
251
252/*
253 * Dump literals
254 */
255#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
256#define IPR_NUM_SDT_ENTRIES 511
257#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
258
259/*
260 * Misc literals
261 */
262#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
263
264/*
265 * Adapter interface types
266 */
267
268struct ipr_res_addr {
269 u8 reserved;
270 u8 bus;
271 u8 target;
272 u8 lun;
273#define IPR_GET_PHYS_LOC(res_addr) \
274 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
275}__attribute__((packed, aligned (4)));
276
277struct ipr_std_inq_vpids {
278 u8 vendor_id[IPR_VENDOR_ID_LEN];
279 u8 product_id[IPR_PROD_ID_LEN];
280}__attribute__((packed));
281
cfc32139
BK		 282struct ipr_vpd {
283 struct ipr_std_inq_vpids vpids;
284 u8 sn[IPR_SERIAL_NUM_LEN];
285}__attribute__((packed));
286
ee0f05b8
BK		 287struct ipr_ext_vpd {
288 struct ipr_vpd vpd;
289 __be32 wwid[2];
290}__attribute__((packed));
291
1da177e4
LT		 292struct ipr_std_inq_data {
293 u8 peri_qual_dev_type;
294#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
295#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
296
297 u8 removeable_medium_rsvd;
298#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
299
300#define IPR_IS_DASD_DEVICE(std_inq) \
301((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
302!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
303
304#define IPR_IS_SES_DEVICE(std_inq) \
305(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
306
307 u8 version;
308 u8 aen_naca_fmt;
309 u8 additional_len;
310 u8 sccs_rsvd;
311 u8 bq_enc_multi;
312 u8 sync_cmdq_flags;
313
314 struct ipr_std_inq_vpids vpids;
315
316 u8 ros_rsvd_ram_rsvd[4];
317
318 u8 serial_num[IPR_SERIAL_NUM_LEN];
319}__attribute__ ((packed));
320
321struct ipr_config_table_entry {
b5145d25
BK		 322 u8 proto;
323#define IPR_PROTO_SATA 0x02
324#define IPR_PROTO_SATA_ATAPI 0x03
325#define IPR_PROTO_SAS_STP 0x06
326#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT		 327 u8 array_id;
328 u8 flags;
329#define IPR_IS_IOA_RESOURCE 0x80
330#define IPR_IS_ARRAY_MEMBER 0x20
331#define IPR_IS_HOT_SPARE 0x10
332
333 u8 rsvd_subtype;
334#define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f)
335#define IPR_SUBTYPE_AF_DASD 0
336#define IPR_SUBTYPE_GENERIC_SCSI 1
337#define IPR_SUBTYPE_VOLUME_SET 2
b5145d25 338#define IPR_SUBTYPE_GENERIC_ATA 4
1da177e4 339
ee0a90fa
BK		 340#define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4)
341#define IPR_QUEUE_FROZEN_MODEL 0
342#define IPR_QUEUE_NACA_MODEL 1
343
1da177e4
LT		 344 struct ipr_res_addr res_addr;
345 __be32 res_handle;
346 __be32 reserved4[2];
347 struct ipr_std_inq_data std_inq_data;
348}__attribute__ ((packed, aligned (4)));
349
350struct ipr_config_table_hdr {
351 u8 num_entries;
352 u8 flags;
353#define IPR_UCODE_DOWNLOAD_REQ 0x10
354 __be16 reserved;
355}__attribute__((packed, aligned (4)));
356
357struct ipr_config_table {
358 struct ipr_config_table_hdr hdr;
359 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS];
360}__attribute__((packed, aligned (4)));
361
362struct ipr_hostrcb_cfg_ch_not {
363 struct ipr_config_table_entry cfgte;
364 u8 reserved[936];
365}__attribute__((packed, aligned (4)));
366
367struct ipr_supported_device {
368 __be16 data_length;
369 u8 reserved;
370 u8 num_records;
371 struct ipr_std_inq_vpids vpids;
372 u8 reserved2[16];
373}__attribute__((packed, aligned (4)));
374
375/* Command packet structure */
376struct ipr_cmd_pkt {
377 __be16 reserved; /* Reserved by IOA */
378 u8 request_type;
379#define IPR_RQTYPE_SCSICDB 0x00
380#define IPR_RQTYPE_IOACMD 0x01
381#define IPR_RQTYPE_HCAM 0x02
b5145d25 382#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4 383
a32c055f 384 u8 reserved2;
1da177e4
LT		 385
386 u8 flags_hi;
387#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
388#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
389#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
390#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
391#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
392
393 u8 flags_lo;
394#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
395#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
396#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
397#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
398#define IPR_FLAGS_LO_ORDERED_TASK 0x04
399#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
400#define IPR_FLAGS_LO_ACA_TASK 0x08
401
402 u8 cdb[16];
403 __be16 timeout;
404}__attribute__ ((packed, aligned(4)));
405
a32c055f 406struct ipr_ioarcb_ata_regs { /* 22 bytes */
b5145d25
BK		 407 u8 flags;
408#define IPR_ATA_FLAG_PACKET_CMD 0x80
409#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
410#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
411 u8 reserved[3];
412
413 __be16 data;
414 u8 feature;
415 u8 nsect;
416 u8 lbal;
417 u8 lbam;
418 u8 lbah;
419 u8 device;
420 u8 command;
421 u8 reserved2[3];
422 u8 hob_feature;
423 u8 hob_nsect;
424 u8 hob_lbal;
425 u8 hob_lbam;
426 u8 hob_lbah;
427 u8 ctl;
428}__attribute__ ((packed, aligned(4)));
429
51b1c7e1
BK		 430struct ipr_ioadl_desc {
431 __be32 flags_and_data_len;
432#define IPR_IOADL_FLAGS_MASK 0xff000000
433#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
434#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
435#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
436#define IPR_IOADL_FLAGS_READ 0x48000000
437#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
438#define IPR_IOADL_FLAGS_WRITE 0x68000000
439#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
440#define IPR_IOADL_FLAGS_LAST 0x01000000
441
442 __be32 address;
443}__attribute__((packed, aligned (8)));
444
a32c055f
WB		 445struct ipr_ioadl64_desc {
446 __be32 flags;
447 __be32 data_len;
448 __be64 address;
449}__attribute__((packed, aligned (16)));
450
451struct ipr_ata64_ioadl {
452 struct ipr_ioarcb_ata_regs regs;
453 u16 reserved[5];
454 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
455}__attribute__((packed, aligned (16)));
456
b5145d25
BK		 457struct ipr_ioarcb_add_data {
458 union {
459 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 460 struct ipr_ioadl_desc ioadl[5];
b5145d25 461 __be32 add_cmd_parms[10];
a32c055f
WB		 462 } u;
463}__attribute__ ((packed, aligned (4)));
464
465struct ipr_ioarcb_sis64_add_addr_ecb {
466 __be64 ioasa_host_pci_addr;
467 __be64 data_ioadl_addr;
468 __be64 reserved;
469 __be32 ext_control_buf[4];
470}__attribute__((packed, aligned (8)));
b5145d25 471
1da177e4
LT		 472/* IOA Request Control Block 128 bytes */
473struct ipr_ioarcb {
a32c055f
WB		 474 union {
475 __be32 ioarcb_host_pci_addr;
476 __be64 ioarcb_host_pci_addr64;
477 } a;
1da177e4
LT		 478 __be32 res_handle;
479 __be32 host_response_handle;
480 __be32 reserved1;
481 __be32 reserved2;
482 __be32 reserved3;
483
a32c055f 484 __be32 data_transfer_length;
1da177e4
LT		 485 __be32 read_data_transfer_length;
486 __be32 write_ioadl_addr;
a32c055f 487 __be32 ioadl_len;
1da177e4
LT		 488 __be32 read_ioadl_addr;
489 __be32 read_ioadl_len;
490
491 __be32 ioasa_host_pci_addr;
492 __be16 ioasa_len;
493 __be16 reserved4;
494
495 struct ipr_cmd_pkt cmd_pkt;
496
a32c055f
WB		 497 __be16 add_cmd_parms_offset;
498 __be16 add_cmd_parms_len;
499
500 union {
501 struct ipr_ioarcb_add_data add_data;
502 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
503 } u;
504
1da177e4
LT		 505}__attribute__((packed, aligned (4)));
506
1da177e4
LT		 507struct ipr_ioasa_vset {
508 __be32 failing_lba_hi;
509 __be32 failing_lba_lo;
c8f74892 510 __be32 reserved;
1da177e4
LT		 511}__attribute__((packed, aligned (4)));
512
513struct ipr_ioasa_af_dasd {
514 __be32 failing_lba;
c8f74892 515 __be32 reserved[2];
1da177e4
LT		 516}__attribute__((packed, aligned (4)));
517
518struct ipr_ioasa_gpdd {
519 u8 end_state;
520 u8 bus_phase;
521 __be16 reserved;
c8f74892 522 __be32 ioa_data[2];
1da177e4
LT		 523}__attribute__((packed, aligned (4)));
524
b5145d25
BK		 525struct ipr_ioasa_gata {
526 u8 error;
527 u8 nsect; /* Interrupt reason */
528 u8 lbal;
529 u8 lbam;
530 u8 lbah;
531 u8 device;
532 u8 status;
533 u8 alt_status; /* ATA CTL */
534 u8 hob_nsect;
535 u8 hob_lbal;
536 u8 hob_lbam;
537 u8 hob_lbah;
538}__attribute__((packed, aligned (4)));
539
c8f74892
BK		 540struct ipr_auto_sense {
541 __be16 auto_sense_len;
542 __be16 ioa_data_len;
543 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
544};
1da177e4
LT		 545
546struct ipr_ioasa {
547 __be32 ioasc;
548#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
549#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
550#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
551#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
552
553 __be16 ret_stat_len; /* Length of the returned IOASA */
554
555 __be16 avail_stat_len; /* Total Length of status available. */
556
557 __be32 residual_data_len; /* number of bytes in the host data */
558 /* buffers that were not used by the IOARCB command. */
559
560 __be32 ilid;
561#define IPR_NO_ILID 0
562#define IPR_DRIVER_ILID 0xffffffff
563
564 __be32 fd_ioasc;
565
566 __be32 fd_phys_locator;
567
568 __be32 fd_res_handle;
569
570 __be32 ioasc_specific; /* status code specific field */
c8f74892
BK		 571#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
572#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 573#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT		 574#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
575#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
576#define IPR_FIELD_POINTER_MASK 0x0000ffff
577
578 union {
579 struct ipr_ioasa_vset vset;
580 struct ipr_ioasa_af_dasd dasd;
581 struct ipr_ioasa_gpdd gpdd;
b5145d25 582 struct ipr_ioasa_gata gata;
1da177e4 583 } u;
c8f74892
BK		 584
585 struct ipr_auto_sense auto_sense;
1da177e4
LT		 586}__attribute__((packed, aligned (4)));
587
588struct ipr_mode_parm_hdr {
589 u8 length;
590 u8 medium_type;
591 u8 device_spec_parms;
592 u8 block_desc_len;
593}__attribute__((packed));
594
595struct ipr_mode_pages {
596 struct ipr_mode_parm_hdr hdr;
597 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
598}__attribute__((packed));
599
600struct ipr_mode_page_hdr {
601 u8 ps_page_code;
602#define IPR_MODE_PAGE_PS 0x80
603#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
604 u8 page_length;
605}__attribute__ ((packed));
606
607struct ipr_dev_bus_entry {
608 struct ipr_res_addr res_addr;
609 u8 flags;
610#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
611#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
612#define IPR_SCSI_ATTR_QAS_MASK 0xC0
613#define IPR_SCSI_ATTR_ENABLE_TM 0x20
614#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
615#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
616#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
617
618 u8 scsi_id;
619 u8 bus_width;
620 u8 extended_reset_delay;
621#define IPR_EXTENDED_RESET_DELAY 7
622
623 __be32 max_xfer_rate;
624
625 u8 spinup_delay;
626 u8 reserved3;
627 __be16 reserved4;
628}__attribute__((packed, aligned (4)));
629
630struct ipr_mode_page28 {
631 struct ipr_mode_page_hdr hdr;
632 u8 num_entries;
633 u8 entry_length;
634 struct ipr_dev_bus_entry bus[0];
635}__attribute__((packed));
636
ac09c349
BK		 637struct ipr_mode_page24 {
638 struct ipr_mode_page_hdr hdr;
639 u8 flags;
640#define IPR_ENABLE_DUAL_IOA_AF 0x80
641}__attribute__((packed));
642
1da177e4
LT		 643struct ipr_ioa_vpd {
644 struct ipr_std_inq_data std_inq_data;
645 u8 ascii_part_num[12];
646 u8 reserved[40];
647 u8 ascii_plant_code[4];
648}__attribute__((packed));
649
650struct ipr_inquiry_page3 {
651 u8 peri_qual_dev_type;
652 u8 page_code;
653 u8 reserved1;
654 u8 page_length;
655 u8 ascii_len;
656 u8 reserved2[3];
657 u8 load_id[4];
658 u8 major_release;
659 u8 card_type;
660 u8 minor_release[2];
661 u8 ptf_number[4];
662 u8 patch_number[4];
663}__attribute__((packed));
664
ac09c349
BK		 665struct ipr_inquiry_cap {
666 u8 peri_qual_dev_type;
667 u8 page_code;
668 u8 reserved1;
669 u8 page_length;
670 u8 ascii_len;
671 u8 reserved2;
672 u8 sis_version[2];
673 u8 cap;
674#define IPR_CAP_DUAL_IOA_RAID 0x80
675 u8 reserved3[15];
676}__attribute__((packed));
677
62275040
BK		 678#define IPR_INQUIRY_PAGE0_ENTRIES 20
679struct ipr_inquiry_page0 {
680 u8 peri_qual_dev_type;
681 u8 page_code;
682 u8 reserved1;
683 u8 len;
684 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
685}__attribute__((packed));
686
1da177e4 687struct ipr_hostrcb_device_data_entry {
cfc32139 688 struct ipr_vpd vpd;
1da177e4 689 struct ipr_res_addr dev_res_addr;
cfc32139
BK		 690 struct ipr_vpd new_vpd;
691 struct ipr_vpd ioa_last_with_dev_vpd;
692 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT		 693 __be32 ioa_data[5];
694}__attribute__((packed, aligned (4)));
695
ee0f05b8
BK		 696struct ipr_hostrcb_device_data_entry_enhanced {
697 struct ipr_ext_vpd vpd;
698 u8 ccin[4];
699 struct ipr_res_addr dev_res_addr;
700 struct ipr_ext_vpd new_vpd;
701 u8 new_ccin[4];
702 struct ipr_ext_vpd ioa_last_with_dev_vpd;
703 struct ipr_ext_vpd cfc_last_with_dev_vpd;
704}__attribute__((packed, aligned (4)));
705
1da177e4 706struct ipr_hostrcb_array_data_entry {
cfc32139 707 struct ipr_vpd vpd;
1da177e4
LT		 708 struct ipr_res_addr expected_dev_res_addr;
709 struct ipr_res_addr dev_res_addr;
710}__attribute__((packed, aligned (4)));
711
ee0f05b8
BK		 712struct ipr_hostrcb_array_data_entry_enhanced {
713 struct ipr_ext_vpd vpd;
714 u8 ccin[4];
715 struct ipr_res_addr expected_dev_res_addr;
716 struct ipr_res_addr dev_res_addr;
717}__attribute__((packed, aligned (4)));
718
1da177e4 719struct ipr_hostrcb_type_ff_error {
ee0f05b8 720 __be32 ioa_data[502];
1da177e4
LT		 721}__attribute__((packed, aligned (4)));
722
723struct ipr_hostrcb_type_01_error {
724 __be32 seek_counter;
725 __be32 read_counter;
726 u8 sense_data[32];
727 __be32 ioa_data[236];
728}__attribute__((packed, aligned (4)));
729
730struct ipr_hostrcb_type_02_error {
cfc32139
BK		 731 struct ipr_vpd ioa_vpd;
732 struct ipr_vpd cfc_vpd;
733 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
734 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 735 __be32 ioa_data[3];
1da177e4
LT		 736}__attribute__((packed, aligned (4)));
737
ee0f05b8
BK		 738struct ipr_hostrcb_type_12_error {
739 struct ipr_ext_vpd ioa_vpd;
740 struct ipr_ext_vpd cfc_vpd;
741 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
742 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
743 __be32 ioa_data[3];
744}__attribute__((packed, aligned (4)));
745
1da177e4 746struct ipr_hostrcb_type_03_error {
cfc32139
BK		 747 struct ipr_vpd ioa_vpd;
748 struct ipr_vpd cfc_vpd;
1da177e4
LT		 749 __be32 errors_detected;
750 __be32 errors_logged;
751 u8 ioa_data[12];
cfc32139 752 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT		 753}__attribute__((packed, aligned (4)));
754
ee0f05b8
BK		 755struct ipr_hostrcb_type_13_error {
756 struct ipr_ext_vpd ioa_vpd;
757 struct ipr_ext_vpd cfc_vpd;
758 __be32 errors_detected;
759 __be32 errors_logged;
760 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
761}__attribute__((packed, aligned (4)));
762
1da177e4 763struct ipr_hostrcb_type_04_error {
cfc32139
BK		 764 struct ipr_vpd ioa_vpd;
765 struct ipr_vpd cfc_vpd;
1da177e4
LT		 766 u8 ioa_data[12];
767 struct ipr_hostrcb_array_data_entry array_member[10];
768 __be32 exposed_mode_adn;
769 __be32 array_id;
cfc32139 770 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT		 771 __be32 ioa_data2;
772 struct ipr_hostrcb_array_data_entry array_member2[8];
773 struct ipr_res_addr last_func_vset_res_addr;
774 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
775 u8 protection_level[8];
1da177e4
LT		 776}__attribute__((packed, aligned (4)));
777
ee0f05b8
BK		 778struct ipr_hostrcb_type_14_error {
779 struct ipr_ext_vpd ioa_vpd;
780 struct ipr_ext_vpd cfc_vpd;
781 __be32 exposed_mode_adn;
782 __be32 array_id;
783 struct ipr_res_addr last_func_vset_res_addr;
784 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
785 u8 protection_level[8];
786 __be32 num_entries;
787 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
788}__attribute__((packed, aligned (4)));
789
b0df54bb
BK		 790struct ipr_hostrcb_type_07_error {
791 u8 failure_reason[64];
792 struct ipr_vpd vpd;
793 u32 data[222];
794}__attribute__((packed, aligned (4)));
795
ee0f05b8
BK		 796struct ipr_hostrcb_type_17_error {
797 u8 failure_reason[64];
798 struct ipr_ext_vpd vpd;
799 u32 data[476];
800}__attribute__((packed, aligned (4)));
801
49dc6a18
BK		 802struct ipr_hostrcb_config_element {
803 u8 type_status;
804#define IPR_PATH_CFG_TYPE_MASK 0xF0
805#define IPR_PATH_CFG_NOT_EXIST 0x00
806#define IPR_PATH_CFG_IOA_PORT 0x10
807#define IPR_PATH_CFG_EXP_PORT 0x20
808#define IPR_PATH_CFG_DEVICE_PORT 0x30
809#define IPR_PATH_CFG_DEVICE_LUN 0x40
810
811#define IPR_PATH_CFG_STATUS_MASK 0x0F
812#define IPR_PATH_CFG_NO_PROB 0x00
813#define IPR_PATH_CFG_DEGRADED 0x01
814#define IPR_PATH_CFG_FAILED 0x02
815#define IPR_PATH_CFG_SUSPECT 0x03
816#define IPR_PATH_NOT_DETECTED 0x04
817#define IPR_PATH_INCORRECT_CONN 0x05
818
819 u8 cascaded_expander;
820 u8 phy;
821 u8 link_rate;
822#define IPR_PHY_LINK_RATE_MASK 0x0F
823
824 __be32 wwid[2];
825}__attribute__((packed, aligned (4)));
826
827struct ipr_hostrcb_fabric_desc {
828 __be16 length;
829 u8 ioa_port;
830 u8 cascaded_expander;
831 u8 phy;
832 u8 path_state;
833#define IPR_PATH_ACTIVE_MASK 0xC0
834#define IPR_PATH_NO_INFO 0x00
835#define IPR_PATH_ACTIVE 0x40
836#define IPR_PATH_NOT_ACTIVE 0x80
837
838#define IPR_PATH_STATE_MASK 0x0F
839#define IPR_PATH_STATE_NO_INFO 0x00
840#define IPR_PATH_HEALTHY 0x01
841#define IPR_PATH_DEGRADED 0x02
842#define IPR_PATH_FAILED 0x03
843
844 __be16 num_entries;
845 struct ipr_hostrcb_config_element elem[1];
846}__attribute__((packed, aligned (4)));
847
848#define for_each_fabric_cfg(fabric, cfg) \
849 for (cfg = (fabric)->elem; \
850 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
851 cfg++)
852
853struct ipr_hostrcb_type_20_error {
854 u8 failure_reason[64];
855 u8 reserved[3];
856 u8 num_entries;
857 struct ipr_hostrcb_fabric_desc desc[1];
858}__attribute__((packed, aligned (4)));
859
1da177e4
LT		 860struct ipr_hostrcb_error {
861 __be32 failing_dev_ioasc;
862 struct ipr_res_addr failing_dev_res_addr;
863 __be32 failing_dev_res_handle;
864 __be32 prc;
865 union {
866 struct ipr_hostrcb_type_ff_error type_ff_error;
867 struct ipr_hostrcb_type_01_error type_01_error;
868 struct ipr_hostrcb_type_02_error type_02_error;
869 struct ipr_hostrcb_type_03_error type_03_error;
870 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 871 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8
BK		 872 struct ipr_hostrcb_type_12_error type_12_error;
873 struct ipr_hostrcb_type_13_error type_13_error;
874 struct ipr_hostrcb_type_14_error type_14_error;
875 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 876 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT		 877 } u;
878}__attribute__((packed, aligned (4)));
879
880struct ipr_hostrcb_raw {
881 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
882}__attribute__((packed, aligned (4)));
883
884struct ipr_hcam {
885 u8 op_code;
886#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
887#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
888
889 u8 notify_type;
890#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
891#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
892#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
893#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
894#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
895
896 u8 notifications_lost;
897#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
898#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
899
900 u8 flags;
901#define IPR_HOSTRCB_INTERNAL_OPER 0x80
902#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
903
904 u8 overlay_id;
905#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
906#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
907#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
908#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
909#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 910#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8
BK		 911#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
912#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
913#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
914#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
915#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 916#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1da177e4
LT		 917#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
918
919 u8 reserved1[3];
920 __be32 ilid;
921 __be32 time_since_last_ioa_reset;
922 __be32 reserved2;
923 __be32 length;
924
925 union {
926 struct ipr_hostrcb_error error;
927 struct ipr_hostrcb_cfg_ch_not ccn;
928 struct ipr_hostrcb_raw raw;
929 } u;
930}__attribute__((packed, aligned (4)));
931
932struct ipr_hostrcb {
933 struct ipr_hcam hcam;
934 dma_addr_t hostrcb_dma;
935 struct list_head queue;
49dc6a18 936 struct ipr_ioa_cfg *ioa_cfg;
1da177e4
LT		 937};
938
939/* IPR smart dump table structures */
940struct ipr_sdt_entry {
941 __be32 bar_str_offset;
942 __be32 end_offset;
943 u8 entry_byte;
944 u8 reserved[3];
945
946 u8 flags;
947#define IPR_SDT_ENDIAN 0x80
948#define IPR_SDT_VALID_ENTRY 0x20
949
950 u8 resv;
951 __be16 priority;
952}__attribute__((packed, aligned (4)));
953
954struct ipr_sdt_header {
955 __be32 state;
956 __be32 num_entries;
957 __be32 num_entries_used;
958 __be32 dump_size;
959}__attribute__((packed, aligned (4)));
960
961struct ipr_sdt {
962 struct ipr_sdt_header hdr;
963 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
964}__attribute__((packed, aligned (4)));
965
966struct ipr_uc_sdt {
967 struct ipr_sdt_header hdr;
968 struct ipr_sdt_entry entry[1];
969}__attribute__((packed, aligned (4)));
970
971/*
972 * Driver types
973 */
974struct ipr_bus_attributes {
975 u8 bus;
976 u8 qas_enabled;
977 u8 bus_width;
978 u8 reserved;
979 u32 max_xfer_rate;
980};
981
35a39691
BK		 982struct ipr_sata_port {
983 struct ipr_ioa_cfg *ioa_cfg;
984 struct ata_port *ap;
985 struct ipr_resource_entry *res;
986 struct ipr_ioasa_gata ioasa;
987};
988
1da177e4
LT		 989struct ipr_resource_entry {
990 struct ipr_config_table_entry cfgte;
991 u8 needs_sync_complete:1;
992 u8 in_erp:1;
993 u8 add_to_ml:1;
994 u8 del_from_ml:1;
995 u8 resetting_device:1;
996
997 struct scsi_device *sdev;
35a39691 998 struct ipr_sata_port *sata_port;
1da177e4
LT		 999 struct list_head queue;
1000};
1001
1002struct ipr_resource_hdr {
1003 u16 num_entries;
1004 u16 reserved;
1005};
1006
1007struct ipr_resource_table {
1008 struct ipr_resource_hdr hdr;
1009 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
1010};
1011
1012struct ipr_misc_cbs {
1013 struct ipr_ioa_vpd ioa_vpd;
62275040 1014 struct ipr_inquiry_page0 page0_data;
1da177e4 1015 struct ipr_inquiry_page3 page3_data;
ac09c349 1016 struct ipr_inquiry_cap cap;
1da177e4
LT		 1017 struct ipr_mode_pages mode_pages;
1018 struct ipr_supported_device supp_dev;
1019};
1020
1021struct ipr_interrupt_offsets {
1022 unsigned long set_interrupt_mask_reg;
1023 unsigned long clr_interrupt_mask_reg;
1024 unsigned long sense_interrupt_mask_reg;
1025 unsigned long clr_interrupt_reg;
1026
1027 unsigned long sense_interrupt_reg;
1028 unsigned long ioarrin_reg;
1029 unsigned long sense_uproc_interrupt_reg;
1030 unsigned long set_uproc_interrupt_reg;
1031 unsigned long clr_uproc_interrupt_reg;
1032};
1033
1034struct ipr_interrupts {
1035 void __iomem *set_interrupt_mask_reg;
1036 void __iomem *clr_interrupt_mask_reg;
1037 void __iomem *sense_interrupt_mask_reg;
1038 void __iomem *clr_interrupt_reg;
1039
1040 void __iomem *sense_interrupt_reg;
1041 void __iomem *ioarrin_reg;
1042 void __iomem *sense_uproc_interrupt_reg;
1043 void __iomem *set_uproc_interrupt_reg;
1044 void __iomem *clr_uproc_interrupt_reg;
1045};
1046
1047struct ipr_chip_cfg_t {
1048 u32 mailbox;
1049 u8 cache_line_size;
1050 struct ipr_interrupt_offsets regs;
1051};
1052
1053struct ipr_chip_t {
1054 u16 vendor;
1055 u16 device;
1be7bd82
WB		 1056 u16 intr_type;
1057#define IPR_USE_LSI 0x00
1058#define IPR_USE_MSI 0x01
a32c055f
WB		 1059 u16 sis_type;
1060#define IPR_SIS32 0x00
1061#define IPR_SIS64 0x01
1da177e4
LT		 1062 const struct ipr_chip_cfg_t *cfg;
1063};
1064
1065enum ipr_shutdown_type {
1066 IPR_SHUTDOWN_NORMAL = 0x00,
1067 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1068 IPR_SHUTDOWN_ABBREV = 0x80,
1069 IPR_SHUTDOWN_NONE = 0x100
1070};
1071
1072struct ipr_trace_entry {
1073 u32 time;
1074
1075 u8 op_code;
35a39691 1076 u8 ata_op_code;
1da177e4
LT		 1077 u8 type;
1078#define IPR_TRACE_START 0x00
1079#define IPR_TRACE_FINISH 0xff
35a39691 1080 u8 cmd_index;
1da177e4
LT		 1081
1082 __be32 res_handle;
1083 union {
1084 u32 ioasc;
1085 u32 add_data;
1086 u32 res_addr;
1087 } u;
1088};
1089
1090struct ipr_sglist {
1091 u32 order;
1092 u32 num_sg;
12baa420 1093 u32 num_dma_sg;
1da177e4
LT		 1094 u32 buffer_len;
1095 struct scatterlist scatterlist[1];
1096};
1097
1098enum ipr_sdt_state {
1099 INACTIVE,
1100 WAIT_FOR_DUMP,
1101 GET_DUMP,
1102 ABORT_DUMP,
1103 DUMP_OBTAINED
1104};
1105
62275040
BK		 1106enum ipr_cache_state {
1107 CACHE_NONE,
1108 CACHE_DISABLED,
1109 CACHE_ENABLED,
1110 CACHE_INVALID
1111};
1112
1da177e4
LT		 1113/* Per-controller data */
1114struct ipr_ioa_cfg {
1115 char eye_catcher[8];
1116#define IPR_EYECATCHER "iprcfg"
1117
1118 struct list_head queue;
1119
1120 u8 allow_interrupts:1;
1121 u8 in_reset_reload:1;
1122 u8 in_ioa_bringdown:1;
1123 u8 ioa_unit_checked:1;
1124 u8 ioa_is_dead:1;
1125 u8 dump_taken:1;
1126 u8 allow_cmds:1;
1127 u8 allow_ml_add_del:1;
ce155cce 1128 u8 needs_hard_reset:1;
ac09c349 1129 u8 dual_raid:1;
463fc696 1130 u8 needs_warm_reset:1;
95fecd90 1131 u8 msi_received:1;
a32c055f 1132 u8 sis64:1;
463fc696
BK		 1133
1134 u8 revid;
1da177e4 1135
62275040 1136 enum ipr_cache_state cache_state;
1da177e4
LT		 1137 u16 type; /* CCIN of the card */
1138
1139 u8 log_level;
1140#define IPR_MAX_LOG_LEVEL 4
1141#define IPR_DEFAULT_LOG_LEVEL 2
1142
1143#define IPR_NUM_TRACE_INDEX_BITS 8
1144#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1145#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1146 char trace_start[8];
1147#define IPR_TRACE_START_LABEL "trace"
1148 struct ipr_trace_entry *trace;
1149 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1150
1151 /*
1152 * Queue for free command blocks
1153 */
1154 char ipr_free_label[8];
1155#define IPR_FREEQ_LABEL "free-q"
1156 struct list_head free_q;
1157
1158 /*
1159 * Queue for command blocks outstanding to the adapter
1160 */
1161 char ipr_pending_label[8];
1162#define IPR_PENDQ_LABEL "pend-q"
1163 struct list_head pending_q;
1164
1165 char cfg_table_start[8];
1166#define IPR_CFG_TBL_START "cfg"
1167 struct ipr_config_table *cfg_table;
1168 dma_addr_t cfg_table_dma;
1169
1170 char resource_table_label[8];
1171#define IPR_RES_TABLE_LABEL "res_tbl"
1172 struct ipr_resource_entry *res_entries;
1173 struct list_head free_res_q;
1174 struct list_head used_res_q;
1175
1176 char ipr_hcam_label[8];
1177#define IPR_HCAM_LABEL "hcams"
1178 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1179 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1180 struct list_head hostrcb_free_q;
1181 struct list_head hostrcb_pending_q;
1182
1183 __be32 *host_rrq;
1184 dma_addr_t host_rrq_dma;
1185#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1186#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1187#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1188#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1189 volatile __be32 *hrrq_start;
1190 volatile __be32 *hrrq_end;
1191 volatile __be32 *hrrq_curr;
1192 volatile u32 toggle_bit;
1193
1194 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1195
5469cb5b 1196 unsigned int transop_timeout;
1da177e4 1197 const struct ipr_chip_cfg_t *chip_cfg;
1be7bd82 1198 const struct ipr_chip_t *ipr_chip;
1da177e4
LT		 1199
1200 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1201 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1202 void __iomem *ioa_mailbox;
1203 struct ipr_interrupts regs;
1204
1205 u16 saved_pcix_cmd_reg;
1206 u16 reset_retries;
1207
1208 u32 errors_logged;
3d1d0da6 1209 u32 doorbell;
1da177e4
LT		 1210
1211 struct Scsi_Host *host;
1212 struct pci_dev *pdev;
1213 struct ipr_sglist *ucode_sglist;
1da177e4
LT		 1214 u8 saved_mode_page_len;
1215
1216 struct work_struct work_q;
1217
1218 wait_queue_head_t reset_wait_q;
95fecd90 1219 wait_queue_head_t msi_wait_q;
1da177e4
LT		 1220
1221 struct ipr_dump *dump;
1222 enum ipr_sdt_state sdt_state;
1223
1224 struct ipr_misc_cbs *vpd_cbs;
1225 dma_addr_t vpd_cbs_dma;
1226
1227 struct pci_pool *ipr_cmd_pool;
1228
1229 struct ipr_cmnd *reset_cmd;
463fc696 1230 int (*reset) (struct ipr_cmnd *);
1da177e4 1231
35a39691 1232 struct ata_host ata_host;
1da177e4 1233 char ipr_cmd_label[8];
0124ca9d 1234#define IPR_CMD_LABEL "ipr_cmd"
1da177e4 1235 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
a32c055f 1236 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1da177e4
LT		 1237};
1238
1239struct ipr_cmnd {
1240 struct ipr_ioarcb ioarcb;
a32c055f
WB		 1241 union {
1242 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1243 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1244 struct ipr_ata64_ioadl ata_ioadl;
1245 } i;
1da177e4 1246 struct ipr_ioasa ioasa;
1da177e4
LT		 1247 struct list_head queue;
1248 struct scsi_cmnd *scsi_cmd;
35a39691 1249 struct ata_queued_cmd *qc;
1da177e4
LT		 1250 struct completion completion;
1251 struct timer_list timer;
1252 void (*done) (struct ipr_cmnd *);
1253 int (*job_step) (struct ipr_cmnd *);
dfed823e 1254 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT		 1255 u16 cmd_index;
1256 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1257 dma_addr_t sense_buffer_dma;
1258 unsigned short dma_use_sg;
a32c055f 1259 dma_addr_t dma_addr;
1da177e4
LT		 1260 struct ipr_cmnd *sibling;
1261 union {
1262 enum ipr_shutdown_type shutdown_type;
1263 struct ipr_hostrcb *hostrcb;
1264 unsigned long time_left;
1265 unsigned long scratch;
1266 struct ipr_resource_entry *res;
1267 struct scsi_device *sdev;
1268 } u;
1269
1270 struct ipr_ioa_cfg *ioa_cfg;
1271};
1272
1273struct ipr_ses_table_entry {
1274 char product_id[17];
1275 char compare_product_id_byte[17];
1276 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1277};
1278
1279struct ipr_dump_header {
1280 u32 eye_catcher;
1281#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1282 u32 len;
1283 u32 num_entries;
1284 u32 first_entry_offset;
1285 u32 status;
1286#define IPR_DUMP_STATUS_SUCCESS 0
1287#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1288#define IPR_DUMP_STATUS_FAILED 0xffffffff
1289 u32 os;
1290#define IPR_DUMP_OS_LINUX 0x4C4E5558
1291 u32 driver_name;
1292#define IPR_DUMP_DRIVER_NAME 0x49505232
1293}__attribute__((packed, aligned (4)));
1294
1295struct ipr_dump_entry_header {
1296 u32 eye_catcher;
1297#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1298 u32 len;
1299 u32 num_elems;
1300 u32 offset;
1301 u32 data_type;
1302#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1303#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1304 u32 id;
1305#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1306#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1307#define IPR_DUMP_TRACE_ID 0x54524143
1308#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1309#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1310#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1311#define IPR_DUMP_PEND_OPS 0x414F5053
1312 u32 status;
1313}__attribute__((packed, aligned (4)));
1314
1315struct ipr_dump_location_entry {
1316 struct ipr_dump_entry_header hdr;
71610f55 1317 u8 location[20];
1da177e4
LT		 1318}__attribute__((packed));
1319
1320struct ipr_dump_trace_entry {
1321 struct ipr_dump_entry_header hdr;
1322 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1323}__attribute__((packed, aligned (4)));
1324
1325struct ipr_dump_version_entry {
1326 struct ipr_dump_entry_header hdr;
1327 u8 version[sizeof(IPR_DRIVER_VERSION)];
1328};
1329
1330struct ipr_dump_ioa_type_entry {
1331 struct ipr_dump_entry_header hdr;
1332 u32 type;
1333 u32 fw_version;
1334};
1335
1336struct ipr_driver_dump {
1337 struct ipr_dump_header hdr;
1338 struct ipr_dump_version_entry version_entry;
1339 struct ipr_dump_location_entry location_entry;
1340 struct ipr_dump_ioa_type_entry ioa_type_entry;
1341 struct ipr_dump_trace_entry trace_entry;
1342}__attribute__((packed));
1343
1344struct ipr_ioa_dump {
1345 struct ipr_dump_entry_header hdr;
1346 struct ipr_sdt sdt;
1347 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1348 u32 reserved;
1349 u32 next_page_index;
1350 u32 page_offset;
1351 u32 format;
1352#define IPR_SDT_FMT2 2
1353#define IPR_SDT_UNKNOWN 3
1354}__attribute__((packed, aligned (4)));
1355
1356struct ipr_dump {
1357 struct kref kref;
1358 struct ipr_ioa_cfg *ioa_cfg;
1359 struct ipr_driver_dump driver_dump;
1360 struct ipr_ioa_dump ioa_dump;
1361};
1362
1363struct ipr_error_table_t {
1364 u32 ioasc;
1365 int log_ioasa;
1366 int log_hcam;
1367 char *error;
1368};
1369
1370struct ipr_software_inq_lid_info {
1371 __be32 load_id;
1372 __be32 timestamp[3];
1373}__attribute__((packed, aligned (4)));
1374
1375struct ipr_ucode_image_header {
1376 __be32 header_length;
1377 __be32 lid_table_offset;
1378 u8 major_release;
1379 u8 card_type;
1380 u8 minor_release[2];
1381 u8 reserved[20];
1382 char eyecatcher[16];
1383 __be32 num_lids;
1384 struct ipr_software_inq_lid_info lid[1];
1385}__attribute__((packed, aligned (4)));
1386
1387/*
1388 * Macros
1389 */
d3c74871 1390#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT		 1391
1392#ifdef CONFIG_SCSI_IPR_TRACE
1393#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1394#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1395#else
1396#define ipr_create_trace_file(kobj, attr) 0
1397#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1398#endif
1399
1400#ifdef CONFIG_SCSI_IPR_DUMP
1401#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1402#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1403#else
1404#define ipr_create_dump_file(kobj, attr) 0
1405#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1406#endif
1407
1408/*
1409 * Error logging macros
1410 */
1411#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1412#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT		 1413#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1414
fb3ed3cb
BK		 1415#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1416 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1417 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1418
fb3ed3cb
BK		 1419#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1420 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4
LT		 1421
1422#define ipr_res_err(ioa_cfg, res, fmt, ...) \
fb3ed3cb 1423 ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__)
1da177e4 1424
fa15b1f6
BK		 1425#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1426{ \
1427 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1428 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1429 } else { \
1430 ipr_err(fmt": %d:%d:%d:%d\n", \
1431 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1432 (res).bus, (res).target, (res).lun); \
1433 } \
1434}
1435
49dc6a18
BK		 1436#define ipr_hcam_err(hostrcb, fmt, ...) \
1437{ \
1438 if (ipr_is_device(&(hostrcb)->hcam.u.error.failing_dev_res_addr)) { \
1439 ipr_ra_err((hostrcb)->ioa_cfg, \
1440 (hostrcb)->hcam.u.error.failing_dev_res_addr, \
1441 fmt, ##__VA_ARGS__); \
1442 } else { \
1443 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, ##__VA_ARGS__); \
1444 } \
1445}
1446
1da177e4 1447#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
cadbd4a5 1448 __FILE__, __func__, __LINE__)
1da177e4 1449
cadbd4a5
HH		 1450#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1451#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1da177e4
LT		 1452
1453#define ipr_err_separator \
1454ipr_err("----------------------------------------------------------\n")
1455
1456
1457/*
1458 * Inlines
1459 */
1460
1461/**
1462 * ipr_is_ioa_resource - Determine if a resource is the IOA
1463 * @res: resource entry struct
1464 *
1465 * Return value:
1466 * 1 if IOA / 0 if not IOA
1467 **/
1468static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1469{
1470 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0;
1471}
1472
1473/**
1474 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1475 * @res: resource entry struct
1476 *
1477 * Return value:
1478 * 1 if AF DASD / 0 if not AF DASD
1479 **/
1480static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1481{
1482 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1483 !ipr_is_ioa_resource(res) &&
1484 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
1485 return 1;
1486 else
1487 return 0;
1488}
1489
1490/**
1491 * ipr_is_vset_device - Determine if a resource is a VSET
1492 * @res: resource entry struct
1493 *
1494 * Return value:
1495 * 1 if VSET / 0 if not VSET
1496 **/
1497static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1498{
1499 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1500 !ipr_is_ioa_resource(res) &&
1501 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
1502 return 1;
1503 else
1504 return 0;
1505}
1506
1507/**
1508 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1509 * @res: resource entry struct
1510 *
1511 * Return value:
1512 * 1 if GSCSI / 0 if not GSCSI
1513 **/
1514static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1515{
1516 if (!ipr_is_ioa_resource(res) &&
1517 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
1518 return 1;
1519 else
1520 return 0;
1521}
1522
e4fbf44e
BK		 1523/**
1524 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1525 * @res: resource entry struct
1526 *
1527 * Return value:
1528 * 1 if SCSI disk / 0 if not SCSI disk
1529 **/
1530static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1531{
1532 if (ipr_is_af_dasd_device(res) ||
1533 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data)))
1534 return 1;
1535 else
1536 return 0;
1537}
1538
b5145d25
BK		 1539/**
1540 * ipr_is_gata - Determine if a resource is a generic ATA resource
1541 * @res: resource entry struct
1542 *
1543 * Return value:
1544 * 1 if GATA / 0 if not GATA
1545 **/
1546static inline int ipr_is_gata(struct ipr_resource_entry *res)
1547{
1548 if (!ipr_is_ioa_resource(res) &&
1549 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_ATA)
1550 return 1;
1551 else
1552 return 0;
1553}
1554
ee0a90fa
BK		 1555/**
1556 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1557 * @res: resource entry struct
1558 *
1559 * Return value:
1560 * 1 if NACA queueing model / 0 if not NACA queueing model
1561 **/
1562static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1563{
1564 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL)
1565 return 1;
1566 return 0;
1567}
1568
1da177e4
LT		 1569/**
1570 * ipr_is_device - Determine if resource address is that of a device
1571 * @res_addr: resource address struct
1572 *
1573 * Return value:
1574 * 1 if AF / 0 if not AF
1575 **/
1576static inline int ipr_is_device(struct ipr_res_addr *res_addr)
1577{
1578 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
d71a8b0c 1579 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1da177e4
LT		 1580 return 1;
1581
1582 return 0;
1583}
1584
1585/**
1586 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1587 * @sdt_word: SDT address
1588 *
1589 * Return value:
1590 * 1 if format 2 / 0 if not
1591 **/
1592static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1593{
1594 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1595
1596 switch (bar_sel) {
1597 case IPR_SDT_FMT2_BAR0_SEL:
1598 case IPR_SDT_FMT2_BAR1_SEL:
1599 case IPR_SDT_FMT2_BAR2_SEL:
1600 case IPR_SDT_FMT2_BAR3_SEL:
1601 case IPR_SDT_FMT2_BAR4_SEL:
1602 case IPR_SDT_FMT2_BAR5_SEL:
1603 case IPR_SDT_FMT2_EXP_ROM_SEL:
1604 return 1;
1605 };
1606
1607 return 0;
1608}
1609
1610#endif