[SCSI] ipr: Handler ID memory allocation failure at module load time
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT
1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
fa195afe 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
1da177e4
LT
23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
46d74563 29#include <asm/unaligned.h>
1da177e4
LT
30#include <linux/types.h>
31#include <linux/completion.h>
35a39691 32#include <linux/libata.h>
1da177e4
LT
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <scsi/scsi.h>
36#include <scsi/scsi_cmnd.h>
37
38/*
39 * Literals
40 */
b5e5ddcd
BK
41#define IPR_DRIVER_VERSION "2.5.4"
42#define IPR_DRIVER_DATE "(July 11, 2012)"
1da177e4 43
1da177e4
LT
44/*
45 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
46 * ops per device for devices not running tagged command queuing.
47 * This can be adjusted at runtime through sysfs device attributes.
48 */
49#define IPR_MAX_CMD_PER_LUN 6
b5145d25 50#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT
51
52/*
53 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
54 * ops the mid-layer can send to the adapter.
55 */
89aad428 56#define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
1da177e4 57
60e7486b 58#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
d7b4627f
WB
59
60#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
cd9b3d04 61#define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
60e7486b 62
1da177e4
LT
63#define IPR_SUBS_DEV_ID_2780 0x0264
64#define IPR_SUBS_DEV_ID_5702 0x0266
65#define IPR_SUBS_DEV_ID_5703 0x0278
b0f56d3d
WB
66#define IPR_SUBS_DEV_ID_572E 0x028D
67#define IPR_SUBS_DEV_ID_573E 0x02D3
68#define IPR_SUBS_DEV_ID_573D 0x02D4
1da177e4
LT
69#define IPR_SUBS_DEV_ID_571A 0x02C0
70#define IPR_SUBS_DEV_ID_571B 0x02BE
b0f56d3d 71#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436
BK
72#define IPR_SUBS_DEV_ID_571F 0x02D5
73#define IPR_SUBS_DEV_ID_572A 0x02C1
74#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 75#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c 76#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 77#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 78#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c 79#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK
80#define IPR_SUBS_DEV_ID_57B7 0x0360
81#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4 82
d7b4627f
WB
83#define IPR_SUBS_DEV_ID_57B4 0x033B
84#define IPR_SUBS_DEV_ID_57B2 0x035F
b8d5d568 85#define IPR_SUBS_DEV_ID_57C0 0x0352
5a918353 86#define IPR_SUBS_DEV_ID_57C3 0x0353
32622bde 87#define IPR_SUBS_DEV_ID_57C4 0x0354
d7b4627f 88#define IPR_SUBS_DEV_ID_57C6 0x0357
b0f56d3d 89#define IPR_SUBS_DEV_ID_57CC 0x035C
d7b4627f
WB
90
91#define IPR_SUBS_DEV_ID_57B5 0x033C
92#define IPR_SUBS_DEV_ID_57CE 0x035E
93#define IPR_SUBS_DEV_ID_57B1 0x0355
94
95#define IPR_SUBS_DEV_ID_574D 0x0356
cd9b3d04 96#define IPR_SUBS_DEV_ID_57C8 0x035D
d7b4627f 97
b8d5d568 98#define IPR_SUBS_DEV_ID_57D5 0x03FB
99#define IPR_SUBS_DEV_ID_57D6 0x03FC
100#define IPR_SUBS_DEV_ID_57D7 0x03FF
101#define IPR_SUBS_DEV_ID_57D8 0x03FE
1da177e4
LT
102#define IPR_NAME "ipr"
103
104/*
105 * Return codes
106 */
107#define IPR_RC_JOB_CONTINUE 1
108#define IPR_RC_JOB_RETURN 2
109
110/*
111 * IOASCs
112 */
113#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 114#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT
115#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
116#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
117#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
118#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
119#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
120#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 121#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 122#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb
BK
123#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
124#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT
125#define IPR_IOASC_BUS_WAS_RESET 0x06290000
126#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
127#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
128
129#define IPR_FIRST_DRIVER_IOASC 0x10000000
130#define IPR_IOASC_IOA_WAS_RESET 0x10000001
131#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
132
5469cb5b
BK
133/* Driver data flags */
134#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
463fc696 135#define IPR_USE_PCI_WARM_RESET 0x00000002
5469cb5b 136
ac719aba 137#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT
138#define IPR_NUM_LOG_HCAMS 2
139#define IPR_NUM_CFG_CHG_HCAMS 2
140#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
3e7ebdfa
WB
141
142#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
143#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
144
d71a8b0c 145#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT
146#define IPR_MAX_NUM_LUNS_PER_TARGET 256
147#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
148#define IPR_VSET_BUS 0xff
149#define IPR_IOA_BUS 0xff
150#define IPR_IOA_TARGET 0xff
151#define IPR_IOA_LUN 0xff
b5145d25 152#define IPR_MAX_NUM_BUSES 16
1da177e4
LT
153#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
154
155#define IPR_NUM_RESET_RELOAD_RETRIES 3
156
157/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
158#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
f72919ec 159 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
1da177e4 160
89aad428 161#define IPR_MAX_COMMANDS 100
1da177e4
LT
162#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
163 IPR_NUM_INTERNAL_CMD_BLKS)
164
165#define IPR_MAX_PHYSICAL_DEVS 192
3e7ebdfa
WB
166#define IPR_DEFAULT_SIS64_DEVS 1024
167#define IPR_MAX_SIS64_DEVS 4096
1da177e4
LT
168
169#define IPR_MAX_SGLIST 64
170#define IPR_IOA_MAX_SECTORS 32767
171#define IPR_VSET_MAX_SECTORS 512
172#define IPR_MAX_CDB_LEN 16
3feeb89d 173#define IPR_MAX_HRRQ_RETRIES 3
1da177e4
LT
174
175#define IPR_DEFAULT_BUS_WIDTH 16
176#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
177#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
178#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
179#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
180
181#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 182#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT
183#define IPR_IOA_RES_ADDR 0x00ffffff
184
185/*
186 * Adapter Commands
187 */
188#define IPR_QUERY_RSRC_STATE 0xC2
189#define IPR_RESET_DEVICE 0xC3
190#define IPR_RESET_TYPE_SELECT 0x80
191#define IPR_LUN_RESET 0x40
192#define IPR_TARGET_RESET 0x20
193#define IPR_BUS_RESET 0x10
b5145d25 194#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT
195#define IPR_ID_HOST_RR_Q 0xC4
196#define IPR_QUERY_IOA_CONFIG 0xC5
197#define IPR_CANCEL_ALL_REQUESTS 0xCE
198#define IPR_HOST_CONTROLLED_ASYNC 0xCF
199#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
200#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
201#define IPR_SET_SUPPORTED_DEVICES 0xFB
3e7ebdfa 202#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
1da177e4
LT
203#define IPR_IOA_SHUTDOWN 0xF7
204#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
205
206/*
207 * Timeouts
208 */
209#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
210#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
211#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
ac09c349 212#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
1da177e4
LT
213#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
214#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
215#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
216#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
14ed9cc7 217#define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
1da177e4
LT
218#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
219#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
220#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 221#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT
222#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
223#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
224#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
463fc696 225#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
4d4dd706
KSS
226#define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
227#define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
110def85
WB
228#define IPR_DUMP_DELAY_SECONDS 4
229#define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
1da177e4
LT
230
231/*
232 * SCSI Literals
233 */
234#define IPR_VENDOR_ID_LEN 8
235#define IPR_PROD_ID_LEN 16
236#define IPR_SERIAL_NUM_LEN 8
237
238/*
239 * Hardware literals
240 */
241#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
242#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
243#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
244#define IPR_GET_FMT2_BAR_SEL(mbx) \
245(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
246#define IPR_SDT_FMT2_BAR0_SEL 0x0
247#define IPR_SDT_FMT2_BAR1_SEL 0x1
248#define IPR_SDT_FMT2_BAR2_SEL 0x2
249#define IPR_SDT_FMT2_BAR3_SEL 0x3
250#define IPR_SDT_FMT2_BAR4_SEL 0x4
251#define IPR_SDT_FMT2_BAR5_SEL 0x5
252#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
253#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
dcbad00e 254#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
1da177e4 255#define IPR_DOORBELL 0x82800000
3d1d0da6 256#define IPR_RUNTIME_RESET 0x40000000
1da177e4 257
214777ba 258#define IPR_IPL_INIT_MIN_STAGE_TIME 5
438b0331 259#define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
214777ba
WB
260#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
261#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
262#define IPR_IPL_INIT_STAGE_MASK 0xff000000
263#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
264#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
265
1da177e4
LT
266#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
267#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
268#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
269#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
270#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
271#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
272#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
273#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
274#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
275#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
276#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
277
278#define IPR_PCII_ERROR_INTERRUPTS \
279(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
280IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
281
282#define IPR_PCII_OPER_INTERRUPTS \
283(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
284
285#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
286#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
cb237ef7 287#define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
1da177e4
LT
288
289#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
290#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
291
292/*
293 * Dump literals
294 */
4d4dd706
KSS
295#define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
296#define IPR_FMT3_MAX_IOA_DUMP_SIZE (32 * 1024 * 1024)
297#define IPR_FMT2_NUM_SDT_ENTRIES 511
298#define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
299#define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
300#define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
1da177e4
LT
301
302/*
303 * Misc literals
304 */
305#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
306
307/*
308 * Adapter interface types
309 */
310
311struct ipr_res_addr {
312 u8 reserved;
313 u8 bus;
314 u8 target;
315 u8 lun;
316#define IPR_GET_PHYS_LOC(res_addr) \
317 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
318}__attribute__((packed, aligned (4)));
319
320struct ipr_std_inq_vpids {
321 u8 vendor_id[IPR_VENDOR_ID_LEN];
322 u8 product_id[IPR_PROD_ID_LEN];
323}__attribute__((packed));
324
cfc32139
BK
325struct ipr_vpd {
326 struct ipr_std_inq_vpids vpids;
327 u8 sn[IPR_SERIAL_NUM_LEN];
328}__attribute__((packed));
329
ee0f05b8
BK
330struct ipr_ext_vpd {
331 struct ipr_vpd vpd;
332 __be32 wwid[2];
333}__attribute__((packed));
334
7262026f
WB
335struct ipr_ext_vpd64 {
336 struct ipr_vpd vpd;
337 __be32 wwid[4];
338}__attribute__((packed));
339
1da177e4
LT
340struct ipr_std_inq_data {
341 u8 peri_qual_dev_type;
342#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
343#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
344
345 u8 removeable_medium_rsvd;
346#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
347
348#define IPR_IS_DASD_DEVICE(std_inq) \
349((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
350!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
351
352#define IPR_IS_SES_DEVICE(std_inq) \
353(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
354
355 u8 version;
356 u8 aen_naca_fmt;
357 u8 additional_len;
358 u8 sccs_rsvd;
359 u8 bq_enc_multi;
360 u8 sync_cmdq_flags;
361
362 struct ipr_std_inq_vpids vpids;
363
364 u8 ros_rsvd_ram_rsvd[4];
365
366 u8 serial_num[IPR_SERIAL_NUM_LEN];
367}__attribute__ ((packed));
368
3e7ebdfa
WB
369#define IPR_RES_TYPE_AF_DASD 0x00
370#define IPR_RES_TYPE_GENERIC_SCSI 0x01
371#define IPR_RES_TYPE_VOLUME_SET 0x02
372#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
373#define IPR_RES_TYPE_GENERIC_ATA 0x04
374#define IPR_RES_TYPE_ARRAY 0x05
375#define IPR_RES_TYPE_IOAFP 0xff
376
1da177e4 377struct ipr_config_table_entry {
b5145d25
BK
378 u8 proto;
379#define IPR_PROTO_SATA 0x02
380#define IPR_PROTO_SATA_ATAPI 0x03
381#define IPR_PROTO_SAS_STP 0x06
3e7ebdfa 382#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT
383 u8 array_id;
384 u8 flags;
3e7ebdfa 385#define IPR_IS_IOA_RESOURCE 0x80
1da177e4 386 u8 rsvd_subtype;
3e7ebdfa
WB
387
388#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
389#define IPR_QUEUE_FROZEN_MODEL 0
ee0a90fa
BK
390#define IPR_QUEUE_NACA_MODEL 1
391
1da177e4
LT
392 struct ipr_res_addr res_addr;
393 __be32 res_handle;
46d74563 394 __be32 lun_wwn[2];
1da177e4
LT
395 struct ipr_std_inq_data std_inq_data;
396}__attribute__ ((packed, aligned (4)));
397
3e7ebdfa
WB
398struct ipr_config_table_entry64 {
399 u8 res_type;
400 u8 proto;
401 u8 vset_num;
402 u8 array_id;
403 __be16 flags;
404 __be16 res_flags;
405#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
406 __be32 res_handle;
407 u8 dev_id_type;
408 u8 reserved[3];
409 __be64 dev_id;
410 __be64 lun;
411 __be64 lun_wwn[2];
412#define IPR_MAX_RES_PATH_LENGTH 24
413 __be64 res_path;
414 struct ipr_std_inq_data std_inq_data;
415 u8 reserved2[4];
7262026f 416 __be64 reserved3[2];
3e7ebdfa
WB
417 u8 reserved4[8];
418}__attribute__ ((packed, aligned (8)));
419
1da177e4
LT
420struct ipr_config_table_hdr {
421 u8 num_entries;
422 u8 flags;
423#define IPR_UCODE_DOWNLOAD_REQ 0x10
424 __be16 reserved;
425}__attribute__((packed, aligned (4)));
426
3e7ebdfa
WB
427struct ipr_config_table_hdr64 {
428 __be16 num_entries;
429 __be16 reserved;
430 u8 flags;
431 u8 reserved2[11];
432}__attribute__((packed, aligned (4)));
433
1da177e4
LT
434struct ipr_config_table {
435 struct ipr_config_table_hdr hdr;
3e7ebdfa 436 struct ipr_config_table_entry dev[0];
1da177e4
LT
437}__attribute__((packed, aligned (4)));
438
3e7ebdfa
WB
439struct ipr_config_table64 {
440 struct ipr_config_table_hdr64 hdr64;
441 struct ipr_config_table_entry64 dev[0];
442}__attribute__((packed, aligned (8)));
443
444struct ipr_config_table_entry_wrapper {
445 union {
446 struct ipr_config_table_entry *cfgte;
447 struct ipr_config_table_entry64 *cfgte64;
448 } u;
449};
450
1da177e4 451struct ipr_hostrcb_cfg_ch_not {
3e7ebdfa
WB
452 union {
453 struct ipr_config_table_entry cfgte;
454 struct ipr_config_table_entry64 cfgte64;
455 } u;
1da177e4
LT
456 u8 reserved[936];
457}__attribute__((packed, aligned (4)));
458
459struct ipr_supported_device {
460 __be16 data_length;
461 u8 reserved;
462 u8 num_records;
463 struct ipr_std_inq_vpids vpids;
464 u8 reserved2[16];
465}__attribute__((packed, aligned (4)));
466
467/* Command packet structure */
468struct ipr_cmd_pkt {
469 __be16 reserved; /* Reserved by IOA */
470 u8 request_type;
471#define IPR_RQTYPE_SCSICDB 0x00
472#define IPR_RQTYPE_IOACMD 0x01
473#define IPR_RQTYPE_HCAM 0x02
b5145d25 474#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4 475
a32c055f 476 u8 reserved2;
1da177e4
LT
477
478 u8 flags_hi;
479#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
480#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
481#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
482#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
483#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
484
485 u8 flags_lo;
486#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
ab6c10b1 487#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
1da177e4
LT
488#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
489#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
490#define IPR_FLAGS_LO_ORDERED_TASK 0x04
491#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
492#define IPR_FLAGS_LO_ACA_TASK 0x08
493
494 u8 cdb[16];
495 __be16 timeout;
496}__attribute__ ((packed, aligned(4)));
497
a32c055f 498struct ipr_ioarcb_ata_regs { /* 22 bytes */
b5145d25
BK
499 u8 flags;
500#define IPR_ATA_FLAG_PACKET_CMD 0x80
501#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
502#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
503 u8 reserved[3];
504
505 __be16 data;
506 u8 feature;
507 u8 nsect;
508 u8 lbal;
509 u8 lbam;
510 u8 lbah;
511 u8 device;
512 u8 command;
513 u8 reserved2[3];
514 u8 hob_feature;
515 u8 hob_nsect;
516 u8 hob_lbal;
517 u8 hob_lbam;
518 u8 hob_lbah;
519 u8 ctl;
520}__attribute__ ((packed, aligned(4)));
521
51b1c7e1
BK
522struct ipr_ioadl_desc {
523 __be32 flags_and_data_len;
524#define IPR_IOADL_FLAGS_MASK 0xff000000
525#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
526#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
527#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
528#define IPR_IOADL_FLAGS_READ 0x48000000
529#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
530#define IPR_IOADL_FLAGS_WRITE 0x68000000
531#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
532#define IPR_IOADL_FLAGS_LAST 0x01000000
533
534 __be32 address;
535}__attribute__((packed, aligned (8)));
536
a32c055f
WB
537struct ipr_ioadl64_desc {
538 __be32 flags;
539 __be32 data_len;
540 __be64 address;
541}__attribute__((packed, aligned (16)));
542
543struct ipr_ata64_ioadl {
544 struct ipr_ioarcb_ata_regs regs;
545 u16 reserved[5];
546 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
547}__attribute__((packed, aligned (16)));
548
b5145d25
BK
549struct ipr_ioarcb_add_data {
550 union {
551 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 552 struct ipr_ioadl_desc ioadl[5];
b5145d25 553 __be32 add_cmd_parms[10];
a32c055f
WB
554 } u;
555}__attribute__ ((packed, aligned (4)));
556
557struct ipr_ioarcb_sis64_add_addr_ecb {
558 __be64 ioasa_host_pci_addr;
559 __be64 data_ioadl_addr;
560 __be64 reserved;
561 __be32 ext_control_buf[4];
562}__attribute__((packed, aligned (8)));
b5145d25 563
1da177e4
LT
564/* IOA Request Control Block 128 bytes */
565struct ipr_ioarcb {
a32c055f
WB
566 union {
567 __be32 ioarcb_host_pci_addr;
568 __be64 ioarcb_host_pci_addr64;
569 } a;
1da177e4
LT
570 __be32 res_handle;
571 __be32 host_response_handle;
572 __be32 reserved1;
573 __be32 reserved2;
574 __be32 reserved3;
575
a32c055f 576 __be32 data_transfer_length;
1da177e4
LT
577 __be32 read_data_transfer_length;
578 __be32 write_ioadl_addr;
a32c055f 579 __be32 ioadl_len;
1da177e4
LT
580 __be32 read_ioadl_addr;
581 __be32 read_ioadl_len;
582
583 __be32 ioasa_host_pci_addr;
584 __be16 ioasa_len;
585 __be16 reserved4;
586
587 struct ipr_cmd_pkt cmd_pkt;
588
a32c055f
WB
589 __be16 add_cmd_parms_offset;
590 __be16 add_cmd_parms_len;
591
592 union {
593 struct ipr_ioarcb_add_data add_data;
594 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
595 } u;
596
1da177e4
LT
597}__attribute__((packed, aligned (4)));
598
1da177e4
LT
599struct ipr_ioasa_vset {
600 __be32 failing_lba_hi;
601 __be32 failing_lba_lo;
c8f74892 602 __be32 reserved;
1da177e4
LT
603}__attribute__((packed, aligned (4)));
604
605struct ipr_ioasa_af_dasd {
606 __be32 failing_lba;
c8f74892 607 __be32 reserved[2];
1da177e4
LT
608}__attribute__((packed, aligned (4)));
609
610struct ipr_ioasa_gpdd {
611 u8 end_state;
612 u8 bus_phase;
613 __be16 reserved;
c8f74892 614 __be32 ioa_data[2];
1da177e4
LT
615}__attribute__((packed, aligned (4)));
616
b5145d25
BK
617struct ipr_ioasa_gata {
618 u8 error;
619 u8 nsect; /* Interrupt reason */
620 u8 lbal;
621 u8 lbam;
622 u8 lbah;
623 u8 device;
624 u8 status;
625 u8 alt_status; /* ATA CTL */
626 u8 hob_nsect;
627 u8 hob_lbal;
628 u8 hob_lbam;
629 u8 hob_lbah;
630}__attribute__((packed, aligned (4)));
631
c8f74892
BK
632struct ipr_auto_sense {
633 __be16 auto_sense_len;
634 __be16 ioa_data_len;
635 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
636};
1da177e4 637
96d21f00 638struct ipr_ioasa_hdr {
1da177e4
LT
639 __be32 ioasc;
640#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
641#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
642#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
643#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
644
645 __be16 ret_stat_len; /* Length of the returned IOASA */
646
647 __be16 avail_stat_len; /* Total Length of status available. */
648
649 __be32 residual_data_len; /* number of bytes in the host data */
650 /* buffers that were not used by the IOARCB command. */
651
652 __be32 ilid;
653#define IPR_NO_ILID 0
654#define IPR_DRIVER_ILID 0xffffffff
655
656 __be32 fd_ioasc;
657
658 __be32 fd_phys_locator;
659
660 __be32 fd_res_handle;
661
662 __be32 ioasc_specific; /* status code specific field */
c8f74892
BK
663#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
664#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 665#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT
666#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
667#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
668#define IPR_FIELD_POINTER_MASK 0x0000ffff
669
96d21f00
WB
670}__attribute__((packed, aligned (4)));
671
672struct ipr_ioasa {
673 struct ipr_ioasa_hdr hdr;
674
675 union {
676 struct ipr_ioasa_vset vset;
677 struct ipr_ioasa_af_dasd dasd;
678 struct ipr_ioasa_gpdd gpdd;
679 struct ipr_ioasa_gata gata;
680 } u;
681
682 struct ipr_auto_sense auto_sense;
683}__attribute__((packed, aligned (4)));
684
685struct ipr_ioasa64 {
686 struct ipr_ioasa_hdr hdr;
687 u8 fd_res_path[8];
688
1da177e4
LT
689 union {
690 struct ipr_ioasa_vset vset;
691 struct ipr_ioasa_af_dasd dasd;
692 struct ipr_ioasa_gpdd gpdd;
b5145d25 693 struct ipr_ioasa_gata gata;
1da177e4 694 } u;
c8f74892
BK
695
696 struct ipr_auto_sense auto_sense;
1da177e4
LT
697}__attribute__((packed, aligned (4)));
698
699struct ipr_mode_parm_hdr {
700 u8 length;
701 u8 medium_type;
702 u8 device_spec_parms;
703 u8 block_desc_len;
704}__attribute__((packed));
705
706struct ipr_mode_pages {
707 struct ipr_mode_parm_hdr hdr;
708 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
709}__attribute__((packed));
710
711struct ipr_mode_page_hdr {
712 u8 ps_page_code;
713#define IPR_MODE_PAGE_PS 0x80
714#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
715 u8 page_length;
716}__attribute__ ((packed));
717
718struct ipr_dev_bus_entry {
719 struct ipr_res_addr res_addr;
720 u8 flags;
721#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
722#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
723#define IPR_SCSI_ATTR_QAS_MASK 0xC0
724#define IPR_SCSI_ATTR_ENABLE_TM 0x20
725#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
726#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
727#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
728
729 u8 scsi_id;
730 u8 bus_width;
731 u8 extended_reset_delay;
732#define IPR_EXTENDED_RESET_DELAY 7
733
734 __be32 max_xfer_rate;
735
736 u8 spinup_delay;
737 u8 reserved3;
738 __be16 reserved4;
739}__attribute__((packed, aligned (4)));
740
741struct ipr_mode_page28 {
742 struct ipr_mode_page_hdr hdr;
743 u8 num_entries;
744 u8 entry_length;
745 struct ipr_dev_bus_entry bus[0];
746}__attribute__((packed));
747
ac09c349
BK
748struct ipr_mode_page24 {
749 struct ipr_mode_page_hdr hdr;
750 u8 flags;
751#define IPR_ENABLE_DUAL_IOA_AF 0x80
752}__attribute__((packed));
753
1da177e4
LT
754struct ipr_ioa_vpd {
755 struct ipr_std_inq_data std_inq_data;
756 u8 ascii_part_num[12];
757 u8 reserved[40];
758 u8 ascii_plant_code[4];
759}__attribute__((packed));
760
761struct ipr_inquiry_page3 {
762 u8 peri_qual_dev_type;
763 u8 page_code;
764 u8 reserved1;
765 u8 page_length;
766 u8 ascii_len;
767 u8 reserved2[3];
768 u8 load_id[4];
769 u8 major_release;
770 u8 card_type;
771 u8 minor_release[2];
772 u8 ptf_number[4];
773 u8 patch_number[4];
774}__attribute__((packed));
775
ac09c349
BK
776struct ipr_inquiry_cap {
777 u8 peri_qual_dev_type;
778 u8 page_code;
779 u8 reserved1;
780 u8 page_length;
781 u8 ascii_len;
782 u8 reserved2;
783 u8 sis_version[2];
784 u8 cap;
785#define IPR_CAP_DUAL_IOA_RAID 0x80
786 u8 reserved3[15];
787}__attribute__((packed));
788
62275040
BK
789#define IPR_INQUIRY_PAGE0_ENTRIES 20
790struct ipr_inquiry_page0 {
791 u8 peri_qual_dev_type;
792 u8 page_code;
793 u8 reserved1;
794 u8 len;
795 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
796}__attribute__((packed));
797
1da177e4 798struct ipr_hostrcb_device_data_entry {
cfc32139 799 struct ipr_vpd vpd;
1da177e4 800 struct ipr_res_addr dev_res_addr;
cfc32139
BK
801 struct ipr_vpd new_vpd;
802 struct ipr_vpd ioa_last_with_dev_vpd;
803 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT
804 __be32 ioa_data[5];
805}__attribute__((packed, aligned (4)));
806
ee0f05b8
BK
807struct ipr_hostrcb_device_data_entry_enhanced {
808 struct ipr_ext_vpd vpd;
809 u8 ccin[4];
810 struct ipr_res_addr dev_res_addr;
811 struct ipr_ext_vpd new_vpd;
812 u8 new_ccin[4];
813 struct ipr_ext_vpd ioa_last_with_dev_vpd;
814 struct ipr_ext_vpd cfc_last_with_dev_vpd;
815}__attribute__((packed, aligned (4)));
816
4565e370
WB
817struct ipr_hostrcb64_device_data_entry_enhanced {
818 struct ipr_ext_vpd vpd;
819 u8 ccin[4];
820 u8 res_path[8];
821 struct ipr_ext_vpd new_vpd;
822 u8 new_ccin[4];
823 struct ipr_ext_vpd ioa_last_with_dev_vpd;
824 struct ipr_ext_vpd cfc_last_with_dev_vpd;
825}__attribute__((packed, aligned (4)));
826
1da177e4 827struct ipr_hostrcb_array_data_entry {
cfc32139 828 struct ipr_vpd vpd;
1da177e4
LT
829 struct ipr_res_addr expected_dev_res_addr;
830 struct ipr_res_addr dev_res_addr;
831}__attribute__((packed, aligned (4)));
832
4565e370
WB
833struct ipr_hostrcb64_array_data_entry {
834 struct ipr_ext_vpd vpd;
835 u8 ccin[4];
836 u8 expected_res_path[8];
837 u8 res_path[8];
838}__attribute__((packed, aligned (4)));
839
ee0f05b8
BK
840struct ipr_hostrcb_array_data_entry_enhanced {
841 struct ipr_ext_vpd vpd;
842 u8 ccin[4];
843 struct ipr_res_addr expected_dev_res_addr;
844 struct ipr_res_addr dev_res_addr;
845}__attribute__((packed, aligned (4)));
846
1da177e4 847struct ipr_hostrcb_type_ff_error {
438b0331 848 __be32 ioa_data[758];
1da177e4
LT
849}__attribute__((packed, aligned (4)));
850
851struct ipr_hostrcb_type_01_error {
852 __be32 seek_counter;
853 __be32 read_counter;
854 u8 sense_data[32];
855 __be32 ioa_data[236];
856}__attribute__((packed, aligned (4)));
857
858struct ipr_hostrcb_type_02_error {
cfc32139
BK
859 struct ipr_vpd ioa_vpd;
860 struct ipr_vpd cfc_vpd;
861 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
862 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 863 __be32 ioa_data[3];
1da177e4
LT
864}__attribute__((packed, aligned (4)));
865
ee0f05b8
BK
866struct ipr_hostrcb_type_12_error {
867 struct ipr_ext_vpd ioa_vpd;
868 struct ipr_ext_vpd cfc_vpd;
869 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
870 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
871 __be32 ioa_data[3];
872}__attribute__((packed, aligned (4)));
873
1da177e4 874struct ipr_hostrcb_type_03_error {
cfc32139
BK
875 struct ipr_vpd ioa_vpd;
876 struct ipr_vpd cfc_vpd;
1da177e4
LT
877 __be32 errors_detected;
878 __be32 errors_logged;
879 u8 ioa_data[12];
cfc32139 880 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT
881}__attribute__((packed, aligned (4)));
882
ee0f05b8
BK
883struct ipr_hostrcb_type_13_error {
884 struct ipr_ext_vpd ioa_vpd;
885 struct ipr_ext_vpd cfc_vpd;
886 __be32 errors_detected;
887 __be32 errors_logged;
888 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
889}__attribute__((packed, aligned (4)));
890
4565e370
WB
891struct ipr_hostrcb_type_23_error {
892 struct ipr_ext_vpd ioa_vpd;
893 struct ipr_ext_vpd cfc_vpd;
894 __be32 errors_detected;
895 __be32 errors_logged;
896 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
897}__attribute__((packed, aligned (4)));
898
1da177e4 899struct ipr_hostrcb_type_04_error {
cfc32139
BK
900 struct ipr_vpd ioa_vpd;
901 struct ipr_vpd cfc_vpd;
1da177e4
LT
902 u8 ioa_data[12];
903 struct ipr_hostrcb_array_data_entry array_member[10];
904 __be32 exposed_mode_adn;
905 __be32 array_id;
cfc32139 906 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT
907 __be32 ioa_data2;
908 struct ipr_hostrcb_array_data_entry array_member2[8];
909 struct ipr_res_addr last_func_vset_res_addr;
910 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
911 u8 protection_level[8];
1da177e4
LT
912}__attribute__((packed, aligned (4)));
913
ee0f05b8
BK
914struct ipr_hostrcb_type_14_error {
915 struct ipr_ext_vpd ioa_vpd;
916 struct ipr_ext_vpd cfc_vpd;
917 __be32 exposed_mode_adn;
918 __be32 array_id;
919 struct ipr_res_addr last_func_vset_res_addr;
920 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
921 u8 protection_level[8];
922 __be32 num_entries;
923 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
924}__attribute__((packed, aligned (4)));
925
4565e370
WB
926struct ipr_hostrcb_type_24_error {
927 struct ipr_ext_vpd ioa_vpd;
928 struct ipr_ext_vpd cfc_vpd;
929 u8 reserved[2];
930 u8 exposed_mode_adn;
931#define IPR_INVALID_ARRAY_DEV_NUM 0xff
932 u8 array_id;
933 u8 last_res_path[8];
934 u8 protection_level[8];
7262026f 935 struct ipr_ext_vpd64 array_vpd;
4565e370
WB
936 u8 description[16];
937 u8 reserved2[3];
938 u8 num_entries;
939 struct ipr_hostrcb64_array_data_entry array_member[32];
940}__attribute__((packed, aligned (4)));
941
b0df54bb
BK
942struct ipr_hostrcb_type_07_error {
943 u8 failure_reason[64];
944 struct ipr_vpd vpd;
945 u32 data[222];
946}__attribute__((packed, aligned (4)));
947
ee0f05b8
BK
948struct ipr_hostrcb_type_17_error {
949 u8 failure_reason[64];
950 struct ipr_ext_vpd vpd;
951 u32 data[476];
952}__attribute__((packed, aligned (4)));
953
49dc6a18
BK
954struct ipr_hostrcb_config_element {
955 u8 type_status;
956#define IPR_PATH_CFG_TYPE_MASK 0xF0
957#define IPR_PATH_CFG_NOT_EXIST 0x00
958#define IPR_PATH_CFG_IOA_PORT 0x10
959#define IPR_PATH_CFG_EXP_PORT 0x20
960#define IPR_PATH_CFG_DEVICE_PORT 0x30
961#define IPR_PATH_CFG_DEVICE_LUN 0x40
962
963#define IPR_PATH_CFG_STATUS_MASK 0x0F
964#define IPR_PATH_CFG_NO_PROB 0x00
965#define IPR_PATH_CFG_DEGRADED 0x01
966#define IPR_PATH_CFG_FAILED 0x02
967#define IPR_PATH_CFG_SUSPECT 0x03
968#define IPR_PATH_NOT_DETECTED 0x04
969#define IPR_PATH_INCORRECT_CONN 0x05
970
971 u8 cascaded_expander;
972 u8 phy;
973 u8 link_rate;
974#define IPR_PHY_LINK_RATE_MASK 0x0F
975
976 __be32 wwid[2];
977}__attribute__((packed, aligned (4)));
978
4565e370
WB
979struct ipr_hostrcb64_config_element {
980 __be16 length;
981 u8 descriptor_id;
982#define IPR_DESCRIPTOR_MASK 0xC0
983#define IPR_DESCRIPTOR_SIS64 0x00
984
985 u8 reserved;
986 u8 type_status;
987
988 u8 reserved2[2];
989 u8 link_rate;
990
991 u8 res_path[8];
992 __be32 wwid[2];
993}__attribute__((packed, aligned (8)));
994
49dc6a18
BK
995struct ipr_hostrcb_fabric_desc {
996 __be16 length;
997 u8 ioa_port;
998 u8 cascaded_expander;
999 u8 phy;
1000 u8 path_state;
1001#define IPR_PATH_ACTIVE_MASK 0xC0
1002#define IPR_PATH_NO_INFO 0x00
1003#define IPR_PATH_ACTIVE 0x40
1004#define IPR_PATH_NOT_ACTIVE 0x80
1005
1006#define IPR_PATH_STATE_MASK 0x0F
1007#define IPR_PATH_STATE_NO_INFO 0x00
1008#define IPR_PATH_HEALTHY 0x01
1009#define IPR_PATH_DEGRADED 0x02
1010#define IPR_PATH_FAILED 0x03
1011
1012 __be16 num_entries;
1013 struct ipr_hostrcb_config_element elem[1];
1014}__attribute__((packed, aligned (4)));
1015
4565e370
WB
1016struct ipr_hostrcb64_fabric_desc {
1017 __be16 length;
1018 u8 descriptor_id;
1019
8701f185 1020 u8 reserved[2];
4565e370
WB
1021 u8 path_state;
1022
1023 u8 reserved2[2];
1024 u8 res_path[8];
1025 u8 reserved3[6];
1026 __be16 num_entries;
1027 struct ipr_hostrcb64_config_element elem[1];
1028}__attribute__((packed, aligned (8)));
1029
49dc6a18
BK
1030#define for_each_fabric_cfg(fabric, cfg) \
1031 for (cfg = (fabric)->elem; \
1032 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1033 cfg++)
1034
1035struct ipr_hostrcb_type_20_error {
1036 u8 failure_reason[64];
1037 u8 reserved[3];
1038 u8 num_entries;
1039 struct ipr_hostrcb_fabric_desc desc[1];
1040}__attribute__((packed, aligned (4)));
1041
4565e370
WB
1042struct ipr_hostrcb_type_30_error {
1043 u8 failure_reason[64];
1044 u8 reserved[3];
1045 u8 num_entries;
1046 struct ipr_hostrcb64_fabric_desc desc[1];
1047}__attribute__((packed, aligned (4)));
1048
1da177e4 1049struct ipr_hostrcb_error {
4565e370
WB
1050 __be32 fd_ioasc;
1051 struct ipr_res_addr fd_res_addr;
1052 __be32 fd_res_handle;
1da177e4
LT
1053 __be32 prc;
1054 union {
1055 struct ipr_hostrcb_type_ff_error type_ff_error;
1056 struct ipr_hostrcb_type_01_error type_01_error;
1057 struct ipr_hostrcb_type_02_error type_02_error;
1058 struct ipr_hostrcb_type_03_error type_03_error;
1059 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 1060 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8
BK
1061 struct ipr_hostrcb_type_12_error type_12_error;
1062 struct ipr_hostrcb_type_13_error type_13_error;
1063 struct ipr_hostrcb_type_14_error type_14_error;
1064 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 1065 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT
1066 } u;
1067}__attribute__((packed, aligned (4)));
1068
4565e370
WB
1069struct ipr_hostrcb64_error {
1070 __be32 fd_ioasc;
1071 __be32 ioa_fw_level;
1072 __be32 fd_res_handle;
1073 __be32 prc;
1074 __be64 fd_dev_id;
1075 __be64 fd_lun;
1076 u8 fd_res_path[8];
1077 __be64 time_stamp;
8701f185 1078 u8 reserved[16];
4565e370
WB
1079 union {
1080 struct ipr_hostrcb_type_ff_error type_ff_error;
1081 struct ipr_hostrcb_type_12_error type_12_error;
1082 struct ipr_hostrcb_type_17_error type_17_error;
1083 struct ipr_hostrcb_type_23_error type_23_error;
1084 struct ipr_hostrcb_type_24_error type_24_error;
1085 struct ipr_hostrcb_type_30_error type_30_error;
1086 } u;
1087}__attribute__((packed, aligned (8)));
1088
1da177e4
LT
1089struct ipr_hostrcb_raw {
1090 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1091}__attribute__((packed, aligned (4)));
1092
1093struct ipr_hcam {
1094 u8 op_code;
1095#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1096#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1097
1098 u8 notify_type;
1099#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1100#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1101#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1102#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1103#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1104
1105 u8 notifications_lost;
1106#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1107#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1108
1109 u8 flags;
1110#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1111#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1112
1113 u8 overlay_id;
1114#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1115#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1116#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1117#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1118#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 1119#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8
BK
1120#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1121#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1122#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1123#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1124#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 1125#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
4565e370
WB
1126#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1127#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1128#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1129#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1130#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1da177e4
LT
1131
1132 u8 reserved1[3];
1133 __be32 ilid;
1134 __be32 time_since_last_ioa_reset;
1135 __be32 reserved2;
1136 __be32 length;
1137
1138 union {
1139 struct ipr_hostrcb_error error;
4565e370 1140 struct ipr_hostrcb64_error error64;
1da177e4
LT
1141 struct ipr_hostrcb_cfg_ch_not ccn;
1142 struct ipr_hostrcb_raw raw;
1143 } u;
1144}__attribute__((packed, aligned (4)));
1145
1146struct ipr_hostrcb {
1147 struct ipr_hcam hcam;
1148 dma_addr_t hostrcb_dma;
1149 struct list_head queue;
49dc6a18 1150 struct ipr_ioa_cfg *ioa_cfg;
4565e370 1151 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1da177e4
LT
1152};
1153
1154/* IPR smart dump table structures */
1155struct ipr_sdt_entry {
dcbad00e
WB
1156 __be32 start_token;
1157 __be32 end_token;
1158 u8 reserved[4];
1da177e4
LT
1159
1160 u8 flags;
1161#define IPR_SDT_ENDIAN 0x80
1162#define IPR_SDT_VALID_ENTRY 0x20
1163
1164 u8 resv;
1165 __be16 priority;
1166}__attribute__((packed, aligned (4)));
1167
1168struct ipr_sdt_header {
1169 __be32 state;
1170 __be32 num_entries;
1171 __be32 num_entries_used;
1172 __be32 dump_size;
1173}__attribute__((packed, aligned (4)));
1174
1175struct ipr_sdt {
1176 struct ipr_sdt_header hdr;
4d4dd706 1177 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1da177e4
LT
1178}__attribute__((packed, aligned (4)));
1179
1180struct ipr_uc_sdt {
1181 struct ipr_sdt_header hdr;
1182 struct ipr_sdt_entry entry[1];
1183}__attribute__((packed, aligned (4)));
1184
1185/*
1186 * Driver types
1187 */
1188struct ipr_bus_attributes {
1189 u8 bus;
1190 u8 qas_enabled;
1191 u8 bus_width;
1192 u8 reserved;
1193 u32 max_xfer_rate;
1194};
1195
35a39691
BK
1196struct ipr_sata_port {
1197 struct ipr_ioa_cfg *ioa_cfg;
1198 struct ata_port *ap;
1199 struct ipr_resource_entry *res;
1200 struct ipr_ioasa_gata ioasa;
1201};
1202
1da177e4 1203struct ipr_resource_entry {
1da177e4
LT
1204 u8 needs_sync_complete:1;
1205 u8 in_erp:1;
1206 u8 add_to_ml:1;
1207 u8 del_from_ml:1;
1208 u8 resetting_device:1;
1209
3e7ebdfa
WB
1210 u32 bus; /* AKA channel */
1211 u32 target; /* AKA id */
1212 u32 lun;
1213#define IPR_ARRAY_VIRTUAL_BUS 0x1
1214#define IPR_VSET_VIRTUAL_BUS 0x2
1215#define IPR_IOAFP_VIRTUAL_BUS 0x3
1216
1217#define IPR_GET_RES_PHYS_LOC(res) \
1218 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1219
1220 u8 ata_class;
1221
1222 u8 flags;
1223 __be16 res_flags;
1224
7be96900 1225 u8 type;
3e7ebdfa
WB
1226
1227 u8 qmodel;
1228 struct ipr_std_inq_data std_inq_data;
1229
1230 __be32 res_handle;
1231 __be64 dev_id;
46d74563 1232 __be64 lun_wwn;
3e7ebdfa
WB
1233 struct scsi_lun dev_lun;
1234 u8 res_path[8];
1235
1236 struct ipr_ioa_cfg *ioa_cfg;
1da177e4 1237 struct scsi_device *sdev;
35a39691 1238 struct ipr_sata_port *sata_port;
1da177e4 1239 struct list_head queue;
3e7ebdfa 1240}; /* struct ipr_resource_entry */
1da177e4
LT
1241
1242struct ipr_resource_hdr {
1243 u16 num_entries;
1244 u16 reserved;
1245};
1246
1da177e4
LT
1247struct ipr_misc_cbs {
1248 struct ipr_ioa_vpd ioa_vpd;
62275040 1249 struct ipr_inquiry_page0 page0_data;
1da177e4 1250 struct ipr_inquiry_page3 page3_data;
ac09c349 1251 struct ipr_inquiry_cap cap;
1da177e4
LT
1252 struct ipr_mode_pages mode_pages;
1253 struct ipr_supported_device supp_dev;
1254};
1255
1256struct ipr_interrupt_offsets {
1257 unsigned long set_interrupt_mask_reg;
1258 unsigned long clr_interrupt_mask_reg;
214777ba 1259 unsigned long clr_interrupt_mask_reg32;
1da177e4 1260 unsigned long sense_interrupt_mask_reg;
214777ba 1261 unsigned long sense_interrupt_mask_reg32;
1da177e4 1262 unsigned long clr_interrupt_reg;
214777ba 1263 unsigned long clr_interrupt_reg32;
1da177e4
LT
1264
1265 unsigned long sense_interrupt_reg;
214777ba 1266 unsigned long sense_interrupt_reg32;
1da177e4
LT
1267 unsigned long ioarrin_reg;
1268 unsigned long sense_uproc_interrupt_reg;
214777ba 1269 unsigned long sense_uproc_interrupt_reg32;
1da177e4 1270 unsigned long set_uproc_interrupt_reg;
214777ba 1271 unsigned long set_uproc_interrupt_reg32;
1da177e4 1272 unsigned long clr_uproc_interrupt_reg;
214777ba
WB
1273 unsigned long clr_uproc_interrupt_reg32;
1274
1275 unsigned long init_feedback_reg;
dcbad00e
WB
1276
1277 unsigned long dump_addr_reg;
1278 unsigned long dump_data_reg;
8701f185 1279
4289a086 1280#define IPR_ENDIAN_SWAP_KEY 0x00080800
8701f185 1281 unsigned long endian_swap_reg;
1da177e4
LT
1282};
1283
1284struct ipr_interrupts {
1285 void __iomem *set_interrupt_mask_reg;
1286 void __iomem *clr_interrupt_mask_reg;
214777ba 1287 void __iomem *clr_interrupt_mask_reg32;
1da177e4 1288 void __iomem *sense_interrupt_mask_reg;
214777ba 1289 void __iomem *sense_interrupt_mask_reg32;
1da177e4 1290 void __iomem *clr_interrupt_reg;
214777ba 1291 void __iomem *clr_interrupt_reg32;
1da177e4
LT
1292
1293 void __iomem *sense_interrupt_reg;
214777ba 1294 void __iomem *sense_interrupt_reg32;
1da177e4
LT
1295 void __iomem *ioarrin_reg;
1296 void __iomem *sense_uproc_interrupt_reg;
214777ba 1297 void __iomem *sense_uproc_interrupt_reg32;
1da177e4 1298 void __iomem *set_uproc_interrupt_reg;
214777ba 1299 void __iomem *set_uproc_interrupt_reg32;
1da177e4 1300 void __iomem *clr_uproc_interrupt_reg;
214777ba
WB
1301 void __iomem *clr_uproc_interrupt_reg32;
1302
1303 void __iomem *init_feedback_reg;
dcbad00e
WB
1304
1305 void __iomem *dump_addr_reg;
1306 void __iomem *dump_data_reg;
8701f185
WB
1307
1308 void __iomem *endian_swap_reg;
1da177e4
LT
1309};
1310
1311struct ipr_chip_cfg_t {
1312 u32 mailbox;
89aad428 1313 u16 max_cmds;
1da177e4 1314 u8 cache_line_size;
7dd21308 1315 u8 clear_isr;
1da177e4
LT
1316 struct ipr_interrupt_offsets regs;
1317};
1318
1319struct ipr_chip_t {
1320 u16 vendor;
1321 u16 device;
1be7bd82
WB
1322 u16 intr_type;
1323#define IPR_USE_LSI 0x00
1324#define IPR_USE_MSI 0x01
a32c055f
WB
1325 u16 sis_type;
1326#define IPR_SIS32 0x00
1327#define IPR_SIS64 0x01
cb237ef7
WB
1328 u16 bist_method;
1329#define IPR_PCI_CFG 0x00
1330#define IPR_MMIO 0x01
1da177e4
LT
1331 const struct ipr_chip_cfg_t *cfg;
1332};
1333
1334enum ipr_shutdown_type {
1335 IPR_SHUTDOWN_NORMAL = 0x00,
1336 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1337 IPR_SHUTDOWN_ABBREV = 0x80,
1338 IPR_SHUTDOWN_NONE = 0x100
1339};
1340
1341struct ipr_trace_entry {
1342 u32 time;
1343
1344 u8 op_code;
35a39691 1345 u8 ata_op_code;
1da177e4
LT
1346 u8 type;
1347#define IPR_TRACE_START 0x00
1348#define IPR_TRACE_FINISH 0xff
35a39691 1349 u8 cmd_index;
1da177e4
LT
1350
1351 __be32 res_handle;
1352 union {
1353 u32 ioasc;
1354 u32 add_data;
1355 u32 res_addr;
1356 } u;
1357};
1358
1359struct ipr_sglist {
1360 u32 order;
1361 u32 num_sg;
12baa420 1362 u32 num_dma_sg;
1da177e4
LT
1363 u32 buffer_len;
1364 struct scatterlist scatterlist[1];
1365};
1366
1367enum ipr_sdt_state {
1368 INACTIVE,
1369 WAIT_FOR_DUMP,
1370 GET_DUMP,
41e9a696 1371 READ_DUMP,
1da177e4
LT
1372 ABORT_DUMP,
1373 DUMP_OBTAINED
1374};
1375
1376/* Per-controller data */
1377struct ipr_ioa_cfg {
1378 char eye_catcher[8];
1379#define IPR_EYECATCHER "iprcfg"
1380
1381 struct list_head queue;
1382
1383 u8 allow_interrupts:1;
1384 u8 in_reset_reload:1;
1385 u8 in_ioa_bringdown:1;
1386 u8 ioa_unit_checked:1;
1387 u8 ioa_is_dead:1;
1388 u8 dump_taken:1;
1389 u8 allow_cmds:1;
1390 u8 allow_ml_add_del:1;
ce155cce 1391 u8 needs_hard_reset:1;
ac09c349 1392 u8 dual_raid:1;
463fc696 1393 u8 needs_warm_reset:1;
95fecd90 1394 u8 msi_received:1;
a32c055f 1395 u8 sis64:1;
4c647e90 1396 u8 dump_timeout:1;
fb51ccbf 1397 u8 cfg_locked:1;
7dd21308 1398 u8 clear_isr:1;
463fc696
BK
1399
1400 u8 revid;
1da177e4 1401
3e7ebdfa
WB
1402 /*
1403 * Bitmaps for SIS64 generated target values
1404 */
1405 unsigned long *target_ids;
1406 unsigned long *array_ids;
1407 unsigned long *vset_ids;
1408
1da177e4
LT
1409 u16 type; /* CCIN of the card */
1410
1411 u8 log_level;
1412#define IPR_MAX_LOG_LEVEL 4
1413#define IPR_DEFAULT_LOG_LEVEL 2
1414
1415#define IPR_NUM_TRACE_INDEX_BITS 8
1416#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1417#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1418 char trace_start[8];
1419#define IPR_TRACE_START_LABEL "trace"
1420 struct ipr_trace_entry *trace;
1421 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1422
1423 /*
1424 * Queue for free command blocks
1425 */
1426 char ipr_free_label[8];
1427#define IPR_FREEQ_LABEL "free-q"
1428 struct list_head free_q;
1429
1430 /*
1431 * Queue for command blocks outstanding to the adapter
1432 */
1433 char ipr_pending_label[8];
1434#define IPR_PENDQ_LABEL "pend-q"
1435 struct list_head pending_q;
1436
1437 char cfg_table_start[8];
1438#define IPR_CFG_TBL_START "cfg"
3e7ebdfa
WB
1439 union {
1440 struct ipr_config_table *cfg_table;
1441 struct ipr_config_table64 *cfg_table64;
1442 } u;
1da177e4 1443 dma_addr_t cfg_table_dma;
3e7ebdfa
WB
1444 u32 cfg_table_size;
1445 u32 max_devs_supported;
1da177e4
LT
1446
1447 char resource_table_label[8];
1448#define IPR_RES_TABLE_LABEL "res_tbl"
1449 struct ipr_resource_entry *res_entries;
1450 struct list_head free_res_q;
1451 struct list_head used_res_q;
1452
1453 char ipr_hcam_label[8];
1454#define IPR_HCAM_LABEL "hcams"
1455 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1456 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1457 struct list_head hostrcb_free_q;
1458 struct list_head hostrcb_pending_q;
1459
1460 __be32 *host_rrq;
1461 dma_addr_t host_rrq_dma;
1462#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1463#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1464#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1465#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1466 volatile __be32 *hrrq_start;
1467 volatile __be32 *hrrq_end;
1468 volatile __be32 *hrrq_curr;
1469 volatile u32 toggle_bit;
1470
1471 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1472
5469cb5b 1473 unsigned int transop_timeout;
1da177e4 1474 const struct ipr_chip_cfg_t *chip_cfg;
1be7bd82 1475 const struct ipr_chip_t *ipr_chip;
1da177e4
LT
1476
1477 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1478 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1479 void __iomem *ioa_mailbox;
1480 struct ipr_interrupts regs;
1481
1482 u16 saved_pcix_cmd_reg;
1483 u16 reset_retries;
1484
1485 u32 errors_logged;
3d1d0da6 1486 u32 doorbell;
1da177e4
LT
1487
1488 struct Scsi_Host *host;
1489 struct pci_dev *pdev;
1490 struct ipr_sglist *ucode_sglist;
1da177e4
LT
1491 u8 saved_mode_page_len;
1492
1493 struct work_struct work_q;
1494
1495 wait_queue_head_t reset_wait_q;
95fecd90 1496 wait_queue_head_t msi_wait_q;
1da177e4
LT
1497
1498 struct ipr_dump *dump;
1499 enum ipr_sdt_state sdt_state;
1500
1501 struct ipr_misc_cbs *vpd_cbs;
1502 dma_addr_t vpd_cbs_dma;
1503
1504 struct pci_pool *ipr_cmd_pool;
1505
1506 struct ipr_cmnd *reset_cmd;
463fc696 1507 int (*reset) (struct ipr_cmnd *);
1da177e4 1508
35a39691 1509 struct ata_host ata_host;
1da177e4 1510 char ipr_cmd_label[8];
0124ca9d 1511#define IPR_CMD_LABEL "ipr_cmd"
89aad428
BK
1512 u32 max_cmds;
1513 struct ipr_cmnd **ipr_cmnd_list;
1514 dma_addr_t *ipr_cmnd_list_dma;
3e7ebdfa 1515}; /* struct ipr_ioa_cfg */
1da177e4
LT
1516
1517struct ipr_cmnd {
1518 struct ipr_ioarcb ioarcb;
a32c055f
WB
1519 union {
1520 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1521 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1522 struct ipr_ata64_ioadl ata_ioadl;
1523 } i;
96d21f00
WB
1524 union {
1525 struct ipr_ioasa ioasa;
1526 struct ipr_ioasa64 ioasa64;
1527 } s;
1da177e4
LT
1528 struct list_head queue;
1529 struct scsi_cmnd *scsi_cmd;
35a39691 1530 struct ata_queued_cmd *qc;
1da177e4
LT
1531 struct completion completion;
1532 struct timer_list timer;
172cd6e1 1533 void (*fast_done) (struct ipr_cmnd *);
1da177e4
LT
1534 void (*done) (struct ipr_cmnd *);
1535 int (*job_step) (struct ipr_cmnd *);
dfed823e 1536 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT
1537 u16 cmd_index;
1538 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1539 dma_addr_t sense_buffer_dma;
1540 unsigned short dma_use_sg;
a32c055f 1541 dma_addr_t dma_addr;
1da177e4
LT
1542 struct ipr_cmnd *sibling;
1543 union {
1544 enum ipr_shutdown_type shutdown_type;
1545 struct ipr_hostrcb *hostrcb;
1546 unsigned long time_left;
1547 unsigned long scratch;
1548 struct ipr_resource_entry *res;
1549 struct scsi_device *sdev;
1550 } u;
1551
1552 struct ipr_ioa_cfg *ioa_cfg;
1553};
1554
1555struct ipr_ses_table_entry {
1556 char product_id[17];
1557 char compare_product_id_byte[17];
1558 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1559};
1560
1561struct ipr_dump_header {
1562 u32 eye_catcher;
1563#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1564 u32 len;
1565 u32 num_entries;
1566 u32 first_entry_offset;
1567 u32 status;
1568#define IPR_DUMP_STATUS_SUCCESS 0
1569#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1570#define IPR_DUMP_STATUS_FAILED 0xffffffff
1571 u32 os;
1572#define IPR_DUMP_OS_LINUX 0x4C4E5558
1573 u32 driver_name;
1574#define IPR_DUMP_DRIVER_NAME 0x49505232
1575}__attribute__((packed, aligned (4)));
1576
1577struct ipr_dump_entry_header {
1578 u32 eye_catcher;
1579#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1580 u32 len;
1581 u32 num_elems;
1582 u32 offset;
1583 u32 data_type;
1584#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1585#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1586 u32 id;
1587#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1588#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1589#define IPR_DUMP_TRACE_ID 0x54524143
1590#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1591#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1592#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1593#define IPR_DUMP_PEND_OPS 0x414F5053
1594 u32 status;
1595}__attribute__((packed, aligned (4)));
1596
1597struct ipr_dump_location_entry {
1598 struct ipr_dump_entry_header hdr;
71610f55 1599 u8 location[20];
1da177e4
LT
1600}__attribute__((packed));
1601
1602struct ipr_dump_trace_entry {
1603 struct ipr_dump_entry_header hdr;
1604 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1605}__attribute__((packed, aligned (4)));
1606
1607struct ipr_dump_version_entry {
1608 struct ipr_dump_entry_header hdr;
1609 u8 version[sizeof(IPR_DRIVER_VERSION)];
1610};
1611
1612struct ipr_dump_ioa_type_entry {
1613 struct ipr_dump_entry_header hdr;
1614 u32 type;
1615 u32 fw_version;
1616};
1617
1618struct ipr_driver_dump {
1619 struct ipr_dump_header hdr;
1620 struct ipr_dump_version_entry version_entry;
1621 struct ipr_dump_location_entry location_entry;
1622 struct ipr_dump_ioa_type_entry ioa_type_entry;
1623 struct ipr_dump_trace_entry trace_entry;
1624}__attribute__((packed));
1625
1626struct ipr_ioa_dump {
1627 struct ipr_dump_entry_header hdr;
1628 struct ipr_sdt sdt;
4d4dd706 1629 __be32 **ioa_data;
1da177e4
LT
1630 u32 reserved;
1631 u32 next_page_index;
1632 u32 page_offset;
1633 u32 format;
1da177e4
LT
1634}__attribute__((packed, aligned (4)));
1635
1636struct ipr_dump {
1637 struct kref kref;
1638 struct ipr_ioa_cfg *ioa_cfg;
1639 struct ipr_driver_dump driver_dump;
1640 struct ipr_ioa_dump ioa_dump;
1641};
1642
1643struct ipr_error_table_t {
1644 u32 ioasc;
1645 int log_ioasa;
1646 int log_hcam;
1647 char *error;
1648};
1649
1650struct ipr_software_inq_lid_info {
1651 __be32 load_id;
1652 __be32 timestamp[3];
1653}__attribute__((packed, aligned (4)));
1654
1655struct ipr_ucode_image_header {
1656 __be32 header_length;
1657 __be32 lid_table_offset;
1658 u8 major_release;
1659 u8 card_type;
1660 u8 minor_release[2];
1661 u8 reserved[20];
1662 char eyecatcher[16];
1663 __be32 num_lids;
1664 struct ipr_software_inq_lid_info lid[1];
1665}__attribute__((packed, aligned (4)));
1666
1667/*
1668 * Macros
1669 */
d3c74871 1670#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT
1671
1672#ifdef CONFIG_SCSI_IPR_TRACE
1673#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1674#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1675#else
1676#define ipr_create_trace_file(kobj, attr) 0
1677#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1678#endif
1679
1680#ifdef CONFIG_SCSI_IPR_DUMP
1681#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1682#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1683#else
1684#define ipr_create_dump_file(kobj, attr) 0
1685#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1686#endif
1687
1688/*
1689 * Error logging macros
1690 */
1691#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1692#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT
1693#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1694
3e7ebdfa
WB
1695#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1696 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1697 bus, target, lun, ##__VA_ARGS__)
1698
1699#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1700 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1701
fb3ed3cb
BK
1702#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1703 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1704 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1705
fb3ed3cb
BK
1706#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1707 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4 1708
fa15b1f6
BK
1709#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1710{ \
1711 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1712 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1713 } else { \
1714 ipr_err(fmt": %d:%d:%d:%d\n", \
1715 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1716 (res).bus, (res).target, (res).lun); \
1717 } \
1718}
1719
49dc6a18 1720#define ipr_hcam_err(hostrcb, fmt, ...) \
4565e370
WB
1721{ \
1722 if (ipr_is_device(hostrcb)) { \
1723 if ((hostrcb)->ioa_cfg->sis64) { \
1724 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
5adcbeb3
WB
1725 ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1726 hostrcb->rp_buffer, \
1727 sizeof(hostrcb->rp_buffer)), \
4565e370
WB
1728 __VA_ARGS__); \
1729 } else { \
1730 ipr_ra_err((hostrcb)->ioa_cfg, \
1731 (hostrcb)->hcam.u.error.fd_res_addr, \
1732 fmt, __VA_ARGS__); \
1733 } \
1734 } else { \
1735 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1736 } \
49dc6a18
BK
1737}
1738
1da177e4 1739#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
cadbd4a5 1740 __FILE__, __func__, __LINE__)
1da177e4 1741
cadbd4a5
HH
1742#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1743#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1da177e4
LT
1744
1745#define ipr_err_separator \
1746ipr_err("----------------------------------------------------------\n")
1747
1748
1749/*
1750 * Inlines
1751 */
1752
1753/**
1754 * ipr_is_ioa_resource - Determine if a resource is the IOA
1755 * @res: resource entry struct
1756 *
1757 * Return value:
1758 * 1 if IOA / 0 if not IOA
1759 **/
1760static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1761{
3e7ebdfa 1762 return res->type == IPR_RES_TYPE_IOAFP;
1da177e4
LT
1763}
1764
1765/**
1766 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1767 * @res: resource entry struct
1768 *
1769 * Return value:
1770 * 1 if AF DASD / 0 if not AF DASD
1771 **/
1772static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1773{
3e7ebdfa
WB
1774 return res->type == IPR_RES_TYPE_AF_DASD ||
1775 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1da177e4
LT
1776}
1777
1778/**
1779 * ipr_is_vset_device - Determine if a resource is a VSET
1780 * @res: resource entry struct
1781 *
1782 * Return value:
1783 * 1 if VSET / 0 if not VSET
1784 **/
1785static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1786{
3e7ebdfa 1787 return res->type == IPR_RES_TYPE_VOLUME_SET;
1da177e4
LT
1788}
1789
1790/**
1791 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1792 * @res: resource entry struct
1793 *
1794 * Return value:
1795 * 1 if GSCSI / 0 if not GSCSI
1796 **/
1797static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1798{
3e7ebdfa 1799 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1da177e4
LT
1800}
1801
e4fbf44e
BK
1802/**
1803 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1804 * @res: resource entry struct
1805 *
1806 * Return value:
1807 * 1 if SCSI disk / 0 if not SCSI disk
1808 **/
1809static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1810{
1811 if (ipr_is_af_dasd_device(res) ||
3e7ebdfa 1812 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
e4fbf44e
BK
1813 return 1;
1814 else
1815 return 0;
1816}
1817
b5145d25
BK
1818/**
1819 * ipr_is_gata - Determine if a resource is a generic ATA resource
1820 * @res: resource entry struct
1821 *
1822 * Return value:
1823 * 1 if GATA / 0 if not GATA
1824 **/
1825static inline int ipr_is_gata(struct ipr_resource_entry *res)
1826{
3e7ebdfa 1827 return res->type == IPR_RES_TYPE_GENERIC_ATA;
b5145d25
BK
1828}
1829
ee0a90fa
BK
1830/**
1831 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1832 * @res: resource entry struct
1833 *
1834 * Return value:
1835 * 1 if NACA queueing model / 0 if not NACA queueing model
1836 **/
1837static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1838{
3e7ebdfa 1839 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
ee0a90fa
BK
1840 return 1;
1841 return 0;
1842}
1843
1da177e4 1844/**
4565e370
WB
1845 * ipr_is_device - Determine if the hostrcb structure is related to a device
1846 * @hostrcb: host resource control blocks struct
1da177e4
LT
1847 *
1848 * Return value:
1849 * 1 if AF / 0 if not AF
1850 **/
4565e370 1851static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1da177e4 1852{
4565e370
WB
1853 struct ipr_res_addr *res_addr;
1854 u8 *res_path;
1855
1856 if (hostrcb->ioa_cfg->sis64) {
1857 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1858 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1859 res_path[0] == 0x81) && res_path[2] != 0xFF)
1860 return 1;
1861 } else {
1862 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1863
1864 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1865 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1866 return 1;
1867 }
1da177e4
LT
1868 return 0;
1869}
1870
1871/**
1872 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1873 * @sdt_word: SDT address
1874 *
1875 * Return value:
1876 * 1 if format 2 / 0 if not
1877 **/
1878static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1879{
1880 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1881
1882 switch (bar_sel) {
1883 case IPR_SDT_FMT2_BAR0_SEL:
1884 case IPR_SDT_FMT2_BAR1_SEL:
1885 case IPR_SDT_FMT2_BAR2_SEL:
1886 case IPR_SDT_FMT2_BAR3_SEL:
1887 case IPR_SDT_FMT2_BAR4_SEL:
1888 case IPR_SDT_FMT2_BAR5_SEL:
1889 case IPR_SDT_FMT2_EXP_ROM_SEL:
1890 return 1;
1891 };
1892
1893 return 0;
1894}
1895
c5f10187
WB
1896#ifndef writeq
1897static inline void writeq(u64 val, void __iomem *addr)
1898{
1899 writel(((u32) (val >> 32)), addr);
1900 writel(((u32) (val)), (addr + 4));
1901}
1da177e4 1902#endif
c5f10187
WB
1903
1904#endif /* _IPR_H */