projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] ipr: Improved dual adapter errors
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT		 1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@redhat.com> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <linux/types.h>
30#include <linux/completion.h>
35a39691 31#include <linux/libata.h>
1da177e4
LT		 32#include <linux/list.h>
33#include <linux/kref.h>
34#include <scsi/scsi.h>
35#include <scsi/scsi_cmnd.h>
36
37/*
38 * Literals
39 */
aa2e07b4
BK		 40#define IPR_DRIVER_VERSION "2.3.2"
41#define IPR_DRIVER_DATE "(March 23, 2007)"
1da177e4 42
1da177e4
LT		 43/*
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
47 */
48#define IPR_MAX_CMD_PER_LUN 6
b5145d25 49#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT		 50
51/*
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
54 */
55#define IPR_NUM_BASE_CMD_BLKS 100
56
60e7486b 57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
185eb31c 58#define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A
60e7486b 59
1da177e4
LT		 60#define IPR_SUBS_DEV_ID_2780 0x0264
61#define IPR_SUBS_DEV_ID_5702 0x0266
62#define IPR_SUBS_DEV_ID_5703 0x0278
63#define IPR_SUBS_DEV_ID_572E 0x028D
64#define IPR_SUBS_DEV_ID_573E 0x02D3
65#define IPR_SUBS_DEV_ID_573D 0x02D4
66#define IPR_SUBS_DEV_ID_571A 0x02C0
67#define IPR_SUBS_DEV_ID_571B 0x02BE
68#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436
BK		 69#define IPR_SUBS_DEV_ID_571F 0x02D5
70#define IPR_SUBS_DEV_ID_572A 0x02C1
71#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 72#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c
BK		 73#define IPR_SUBS_DEV_ID_574D 0x030B
74#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 75#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 76#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c
BK		 77#define IPR_SUBS_DEV_ID_575D 0x033E
78#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK		 79#define IPR_SUBS_DEV_ID_57B7 0x0360
80#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4
LT		 81
82#define IPR_NAME "ipr"
83
84/*
85 * Return codes
86 */
87#define IPR_RC_JOB_CONTINUE 1
88#define IPR_RC_JOB_RETURN 2
89
90/*
91 * IOASCs
92 */
93#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 94#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT		 95#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
96#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
97#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
98#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
99#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
100#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 101#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 102#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb
BK		 103#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
104#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT		 105#define IPR_IOASC_BUS_WAS_RESET 0x06290000
106#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
107#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
108
109#define IPR_FIRST_DRIVER_IOASC 0x10000000
110#define IPR_IOASC_IOA_WAS_RESET 0x10000001
111#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
112
5469cb5b
BK		 113/* Driver data flags */
114#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
115
ac719aba 116#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT		 117#define IPR_NUM_LOG_HCAMS 2
118#define IPR_NUM_CFG_CHG_HCAMS 2
119#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
d71a8b0c 120#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT		 121#define IPR_MAX_NUM_LUNS_PER_TARGET 256
122#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
123#define IPR_VSET_BUS 0xff
124#define IPR_IOA_BUS 0xff
125#define IPR_IOA_TARGET 0xff
126#define IPR_IOA_LUN 0xff
b5145d25 127#define IPR_MAX_NUM_BUSES 16
1da177e4
LT		 128#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
129
130#define IPR_NUM_RESET_RELOAD_RETRIES 3
131
132/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
133#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
134 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
135
136#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
137#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
138 IPR_NUM_INTERNAL_CMD_BLKS)
139
140#define IPR_MAX_PHYSICAL_DEVS 192
141
142#define IPR_MAX_SGLIST 64
143#define IPR_IOA_MAX_SECTORS 32767
144#define IPR_VSET_MAX_SECTORS 512
145#define IPR_MAX_CDB_LEN 16
146
147#define IPR_DEFAULT_BUS_WIDTH 16
148#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
149#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
150#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
151#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
152
153#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 154#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT		 155#define IPR_IOA_RES_ADDR 0x00ffffff
156
157/*
158 * Adapter Commands
159 */
160#define IPR_QUERY_RSRC_STATE 0xC2
161#define IPR_RESET_DEVICE 0xC3
162#define IPR_RESET_TYPE_SELECT 0x80
163#define IPR_LUN_RESET 0x40
164#define IPR_TARGET_RESET 0x20
165#define IPR_BUS_RESET 0x10
b5145d25 166#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT		 167#define IPR_ID_HOST_RR_Q 0xC4
168#define IPR_QUERY_IOA_CONFIG 0xC5
169#define IPR_CANCEL_ALL_REQUESTS 0xCE
170#define IPR_HOST_CONTROLLED_ASYNC 0xCF
171#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
172#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
173#define IPR_SET_SUPPORTED_DEVICES 0xFB
174#define IPR_IOA_SHUTDOWN 0xF7
175#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
176
177/*
178 * Timeouts
179 */
180#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
181#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
182#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
183#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
184#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
185#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
186#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
187#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
188#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
189#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
190#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 191#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT		 192#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
193#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
194#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
195#define IPR_DUMP_TIMEOUT (15 * HZ)
196
197/*
198 * SCSI Literals
199 */
200#define IPR_VENDOR_ID_LEN 8
201#define IPR_PROD_ID_LEN 16
202#define IPR_SERIAL_NUM_LEN 8
203
204/*
205 * Hardware literals
206 */
207#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
208#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
209#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
210#define IPR_GET_FMT2_BAR_SEL(mbx) \
211(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
212#define IPR_SDT_FMT2_BAR0_SEL 0x0
213#define IPR_SDT_FMT2_BAR1_SEL 0x1
214#define IPR_SDT_FMT2_BAR2_SEL 0x2
215#define IPR_SDT_FMT2_BAR3_SEL 0x3
216#define IPR_SDT_FMT2_BAR4_SEL 0x4
217#define IPR_SDT_FMT2_BAR5_SEL 0x5
218#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
219#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
220#define IPR_DOORBELL 0x82800000
3d1d0da6 221#define IPR_RUNTIME_RESET 0x40000000
1da177e4
LT		 222
223#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
224#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
225#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
226#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
227#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
228#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
229#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
230#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
231#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
232#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
233#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
234
235#define IPR_PCII_ERROR_INTERRUPTS \
236(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
237IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
238
239#define IPR_PCII_OPER_INTERRUPTS \
240(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
241
242#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
243#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
244
245#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
246#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
247
248/*
249 * Dump literals
250 */
251#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
252#define IPR_NUM_SDT_ENTRIES 511
253#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
254
255/*
256 * Misc literals
257 */
258#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
259
260/*
261 * Adapter interface types
262 */
263
264struct ipr_res_addr {
265 u8 reserved;
266 u8 bus;
267 u8 target;
268 u8 lun;
269#define IPR_GET_PHYS_LOC(res_addr) \
270 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
271}__attribute__((packed, aligned (4)));
272
273struct ipr_std_inq_vpids {
274 u8 vendor_id[IPR_VENDOR_ID_LEN];
275 u8 product_id[IPR_PROD_ID_LEN];
276}__attribute__((packed));
277
cfc32139
BK		 278struct ipr_vpd {
279 struct ipr_std_inq_vpids vpids;
280 u8 sn[IPR_SERIAL_NUM_LEN];
281}__attribute__((packed));
282
ee0f05b8
BK		 283struct ipr_ext_vpd {
284 struct ipr_vpd vpd;
285 __be32 wwid[2];
286}__attribute__((packed));
287
1da177e4
LT		 288struct ipr_std_inq_data {
289 u8 peri_qual_dev_type;
290#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
291#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
292
293 u8 removeable_medium_rsvd;
294#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
295
296#define IPR_IS_DASD_DEVICE(std_inq) \
297((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
298!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
299
300#define IPR_IS_SES_DEVICE(std_inq) \
301(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
302
303 u8 version;
304 u8 aen_naca_fmt;
305 u8 additional_len;
306 u8 sccs_rsvd;
307 u8 bq_enc_multi;
308 u8 sync_cmdq_flags;
309
310 struct ipr_std_inq_vpids vpids;
311
312 u8 ros_rsvd_ram_rsvd[4];
313
314 u8 serial_num[IPR_SERIAL_NUM_LEN];
315}__attribute__ ((packed));
316
317struct ipr_config_table_entry {
b5145d25
BK		 318 u8 proto;
319#define IPR_PROTO_SATA 0x02
320#define IPR_PROTO_SATA_ATAPI 0x03
321#define IPR_PROTO_SAS_STP 0x06
322#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT		 323 u8 array_id;
324 u8 flags;
325#define IPR_IS_IOA_RESOURCE 0x80
326#define IPR_IS_ARRAY_MEMBER 0x20
327#define IPR_IS_HOT_SPARE 0x10
328
329 u8 rsvd_subtype;
330#define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f)
331#define IPR_SUBTYPE_AF_DASD 0
332#define IPR_SUBTYPE_GENERIC_SCSI 1
333#define IPR_SUBTYPE_VOLUME_SET 2
b5145d25 334#define IPR_SUBTYPE_GENERIC_ATA 4
1da177e4 335
ee0a90fa
BK		 336#define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4)
337#define IPR_QUEUE_FROZEN_MODEL 0
338#define IPR_QUEUE_NACA_MODEL 1
339
1da177e4
LT		 340 struct ipr_res_addr res_addr;
341 __be32 res_handle;
342 __be32 reserved4[2];
343 struct ipr_std_inq_data std_inq_data;
344}__attribute__ ((packed, aligned (4)));
345
346struct ipr_config_table_hdr {
347 u8 num_entries;
348 u8 flags;
349#define IPR_UCODE_DOWNLOAD_REQ 0x10
350 __be16 reserved;
351}__attribute__((packed, aligned (4)));
352
353struct ipr_config_table {
354 struct ipr_config_table_hdr hdr;
355 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS];
356}__attribute__((packed, aligned (4)));
357
358struct ipr_hostrcb_cfg_ch_not {
359 struct ipr_config_table_entry cfgte;
360 u8 reserved[936];
361}__attribute__((packed, aligned (4)));
362
363struct ipr_supported_device {
364 __be16 data_length;
365 u8 reserved;
366 u8 num_records;
367 struct ipr_std_inq_vpids vpids;
368 u8 reserved2[16];
369}__attribute__((packed, aligned (4)));
370
371/* Command packet structure */
372struct ipr_cmd_pkt {
373 __be16 reserved; /* Reserved by IOA */
374 u8 request_type;
375#define IPR_RQTYPE_SCSICDB 0x00
376#define IPR_RQTYPE_IOACMD 0x01
377#define IPR_RQTYPE_HCAM 0x02
b5145d25 378#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4
LT		 379
380 u8 luntar_luntrn;
381
382 u8 flags_hi;
383#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
384#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
385#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
386#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
387#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
388
389 u8 flags_lo;
390#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
391#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
392#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
393#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
394#define IPR_FLAGS_LO_ORDERED_TASK 0x04
395#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
396#define IPR_FLAGS_LO_ACA_TASK 0x08
397
398 u8 cdb[16];
399 __be16 timeout;
400}__attribute__ ((packed, aligned(4)));
401
b5145d25
BK		 402struct ipr_ioarcb_ata_regs {
403 u8 flags;
404#define IPR_ATA_FLAG_PACKET_CMD 0x80
405#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
406#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
407 u8 reserved[3];
408
409 __be16 data;
410 u8 feature;
411 u8 nsect;
412 u8 lbal;
413 u8 lbam;
414 u8 lbah;
415 u8 device;
416 u8 command;
417 u8 reserved2[3];
418 u8 hob_feature;
419 u8 hob_nsect;
420 u8 hob_lbal;
421 u8 hob_lbam;
422 u8 hob_lbah;
423 u8 ctl;
424}__attribute__ ((packed, aligned(4)));
425
51b1c7e1
BK		 426struct ipr_ioadl_desc {
427 __be32 flags_and_data_len;
428#define IPR_IOADL_FLAGS_MASK 0xff000000
429#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
430#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
431#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
432#define IPR_IOADL_FLAGS_READ 0x48000000
433#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
434#define IPR_IOADL_FLAGS_WRITE 0x68000000
435#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
436#define IPR_IOADL_FLAGS_LAST 0x01000000
437
438 __be32 address;
439}__attribute__((packed, aligned (8)));
440
b5145d25
BK		 441struct ipr_ioarcb_add_data {
442 union {
443 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 444 struct ipr_ioadl_desc ioadl[5];
b5145d25
BK		 445 __be32 add_cmd_parms[10];
446 }u;
447}__attribute__ ((packed, aligned(4)));
448
1da177e4
LT		 449/* IOA Request Control Block 128 bytes */
450struct ipr_ioarcb {
451 __be32 ioarcb_host_pci_addr;
452 __be32 reserved;
453 __be32 res_handle;
454 __be32 host_response_handle;
455 __be32 reserved1;
456 __be32 reserved2;
457 __be32 reserved3;
458
459 __be32 write_data_transfer_length;
460 __be32 read_data_transfer_length;
461 __be32 write_ioadl_addr;
462 __be32 write_ioadl_len;
463 __be32 read_ioadl_addr;
464 __be32 read_ioadl_len;
465
466 __be32 ioasa_host_pci_addr;
467 __be16 ioasa_len;
468 __be16 reserved4;
469
470 struct ipr_cmd_pkt cmd_pkt;
471
472 __be32 add_cmd_parms_len;
b5145d25 473 struct ipr_ioarcb_add_data add_data;
1da177e4
LT		 474}__attribute__((packed, aligned (4)));
475
1da177e4
LT		 476struct ipr_ioasa_vset {
477 __be32 failing_lba_hi;
478 __be32 failing_lba_lo;
c8f74892 479 __be32 reserved;
1da177e4
LT		 480}__attribute__((packed, aligned (4)));
481
482struct ipr_ioasa_af_dasd {
483 __be32 failing_lba;
c8f74892 484 __be32 reserved[2];
1da177e4
LT		 485}__attribute__((packed, aligned (4)));
486
487struct ipr_ioasa_gpdd {
488 u8 end_state;
489 u8 bus_phase;
490 __be16 reserved;
c8f74892 491 __be32 ioa_data[2];
1da177e4
LT		 492}__attribute__((packed, aligned (4)));
493
b5145d25
BK		 494struct ipr_ioasa_gata {
495 u8 error;
496 u8 nsect; /* Interrupt reason */
497 u8 lbal;
498 u8 lbam;
499 u8 lbah;
500 u8 device;
501 u8 status;
502 u8 alt_status; /* ATA CTL */
503 u8 hob_nsect;
504 u8 hob_lbal;
505 u8 hob_lbam;
506 u8 hob_lbah;
507}__attribute__((packed, aligned (4)));
508
c8f74892
BK		 509struct ipr_auto_sense {
510 __be16 auto_sense_len;
511 __be16 ioa_data_len;
512 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
513};
1da177e4
LT		 514
515struct ipr_ioasa {
516 __be32 ioasc;
517#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
518#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
519#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
520#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
521
522 __be16 ret_stat_len; /* Length of the returned IOASA */
523
524 __be16 avail_stat_len; /* Total Length of status available. */
525
526 __be32 residual_data_len; /* number of bytes in the host data */
527 /* buffers that were not used by the IOARCB command. */
528
529 __be32 ilid;
530#define IPR_NO_ILID 0
531#define IPR_DRIVER_ILID 0xffffffff
532
533 __be32 fd_ioasc;
534
535 __be32 fd_phys_locator;
536
537 __be32 fd_res_handle;
538
539 __be32 ioasc_specific; /* status code specific field */
c8f74892
BK		 540#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
541#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 542#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT		 543#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
544#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
545#define IPR_FIELD_POINTER_MASK 0x0000ffff
546
547 union {
548 struct ipr_ioasa_vset vset;
549 struct ipr_ioasa_af_dasd dasd;
550 struct ipr_ioasa_gpdd gpdd;
b5145d25 551 struct ipr_ioasa_gata gata;
1da177e4 552 } u;
c8f74892
BK		 553
554 struct ipr_auto_sense auto_sense;
1da177e4
LT		 555}__attribute__((packed, aligned (4)));
556
557struct ipr_mode_parm_hdr {
558 u8 length;
559 u8 medium_type;
560 u8 device_spec_parms;
561 u8 block_desc_len;
562}__attribute__((packed));
563
564struct ipr_mode_pages {
565 struct ipr_mode_parm_hdr hdr;
566 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
567}__attribute__((packed));
568
569struct ipr_mode_page_hdr {
570 u8 ps_page_code;
571#define IPR_MODE_PAGE_PS 0x80
572#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
573 u8 page_length;
574}__attribute__ ((packed));
575
576struct ipr_dev_bus_entry {
577 struct ipr_res_addr res_addr;
578 u8 flags;
579#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
580#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
581#define IPR_SCSI_ATTR_QAS_MASK 0xC0
582#define IPR_SCSI_ATTR_ENABLE_TM 0x20
583#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
584#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
585#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
586
587 u8 scsi_id;
588 u8 bus_width;
589 u8 extended_reset_delay;
590#define IPR_EXTENDED_RESET_DELAY 7
591
592 __be32 max_xfer_rate;
593
594 u8 spinup_delay;
595 u8 reserved3;
596 __be16 reserved4;
597}__attribute__((packed, aligned (4)));
598
599struct ipr_mode_page28 {
600 struct ipr_mode_page_hdr hdr;
601 u8 num_entries;
602 u8 entry_length;
603 struct ipr_dev_bus_entry bus[0];
604}__attribute__((packed));
605
606struct ipr_ioa_vpd {
607 struct ipr_std_inq_data std_inq_data;
608 u8 ascii_part_num[12];
609 u8 reserved[40];
610 u8 ascii_plant_code[4];
611}__attribute__((packed));
612
613struct ipr_inquiry_page3 {
614 u8 peri_qual_dev_type;
615 u8 page_code;
616 u8 reserved1;
617 u8 page_length;
618 u8 ascii_len;
619 u8 reserved2[3];
620 u8 load_id[4];
621 u8 major_release;
622 u8 card_type;
623 u8 minor_release[2];
624 u8 ptf_number[4];
625 u8 patch_number[4];
626}__attribute__((packed));
627
62275040
BK		 628#define IPR_INQUIRY_PAGE0_ENTRIES 20
629struct ipr_inquiry_page0 {
630 u8 peri_qual_dev_type;
631 u8 page_code;
632 u8 reserved1;
633 u8 len;
634 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
635}__attribute__((packed));
636
1da177e4 637struct ipr_hostrcb_device_data_entry {
cfc32139 638 struct ipr_vpd vpd;
1da177e4 639 struct ipr_res_addr dev_res_addr;
cfc32139
BK		 640 struct ipr_vpd new_vpd;
641 struct ipr_vpd ioa_last_with_dev_vpd;
642 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT		 643 __be32 ioa_data[5];
644}__attribute__((packed, aligned (4)));
645
ee0f05b8
BK		 646struct ipr_hostrcb_device_data_entry_enhanced {
647 struct ipr_ext_vpd vpd;
648 u8 ccin[4];
649 struct ipr_res_addr dev_res_addr;
650 struct ipr_ext_vpd new_vpd;
651 u8 new_ccin[4];
652 struct ipr_ext_vpd ioa_last_with_dev_vpd;
653 struct ipr_ext_vpd cfc_last_with_dev_vpd;
654}__attribute__((packed, aligned (4)));
655
1da177e4 656struct ipr_hostrcb_array_data_entry {
cfc32139 657 struct ipr_vpd vpd;
1da177e4
LT		 658 struct ipr_res_addr expected_dev_res_addr;
659 struct ipr_res_addr dev_res_addr;
660}__attribute__((packed, aligned (4)));
661
ee0f05b8
BK		 662struct ipr_hostrcb_array_data_entry_enhanced {
663 struct ipr_ext_vpd vpd;
664 u8 ccin[4];
665 struct ipr_res_addr expected_dev_res_addr;
666 struct ipr_res_addr dev_res_addr;
667}__attribute__((packed, aligned (4)));
668
1da177e4 669struct ipr_hostrcb_type_ff_error {
ee0f05b8 670 __be32 ioa_data[502];
1da177e4
LT		 671}__attribute__((packed, aligned (4)));
672
673struct ipr_hostrcb_type_01_error {
674 __be32 seek_counter;
675 __be32 read_counter;
676 u8 sense_data[32];
677 __be32 ioa_data[236];
678}__attribute__((packed, aligned (4)));
679
680struct ipr_hostrcb_type_02_error {
cfc32139
BK		 681 struct ipr_vpd ioa_vpd;
682 struct ipr_vpd cfc_vpd;
683 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
684 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 685 __be32 ioa_data[3];
1da177e4
LT		 686}__attribute__((packed, aligned (4)));
687
ee0f05b8
BK		 688struct ipr_hostrcb_type_12_error {
689 struct ipr_ext_vpd ioa_vpd;
690 struct ipr_ext_vpd cfc_vpd;
691 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
692 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
693 __be32 ioa_data[3];
694}__attribute__((packed, aligned (4)));
695
1da177e4 696struct ipr_hostrcb_type_03_error {
cfc32139
BK		 697 struct ipr_vpd ioa_vpd;
698 struct ipr_vpd cfc_vpd;
1da177e4
LT		 699 __be32 errors_detected;
700 __be32 errors_logged;
701 u8 ioa_data[12];
cfc32139 702 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT		 703}__attribute__((packed, aligned (4)));
704
ee0f05b8
BK		 705struct ipr_hostrcb_type_13_error {
706 struct ipr_ext_vpd ioa_vpd;
707 struct ipr_ext_vpd cfc_vpd;
708 __be32 errors_detected;
709 __be32 errors_logged;
710 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
711}__attribute__((packed, aligned (4)));
712
1da177e4 713struct ipr_hostrcb_type_04_error {
cfc32139
BK		 714 struct ipr_vpd ioa_vpd;
715 struct ipr_vpd cfc_vpd;
1da177e4
LT		 716 u8 ioa_data[12];
717 struct ipr_hostrcb_array_data_entry array_member[10];
718 __be32 exposed_mode_adn;
719 __be32 array_id;
cfc32139 720 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT		 721 __be32 ioa_data2;
722 struct ipr_hostrcb_array_data_entry array_member2[8];
723 struct ipr_res_addr last_func_vset_res_addr;
724 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
725 u8 protection_level[8];
1da177e4
LT		 726}__attribute__((packed, aligned (4)));
727
ee0f05b8
BK		 728struct ipr_hostrcb_type_14_error {
729 struct ipr_ext_vpd ioa_vpd;
730 struct ipr_ext_vpd cfc_vpd;
731 __be32 exposed_mode_adn;
732 __be32 array_id;
733 struct ipr_res_addr last_func_vset_res_addr;
734 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
735 u8 protection_level[8];
736 __be32 num_entries;
737 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
738}__attribute__((packed, aligned (4)));
739
b0df54bb
BK		 740struct ipr_hostrcb_type_07_error {
741 u8 failure_reason[64];
742 struct ipr_vpd vpd;
743 u32 data[222];
744}__attribute__((packed, aligned (4)));
745
ee0f05b8
BK		 746struct ipr_hostrcb_type_17_error {
747 u8 failure_reason[64];
748 struct ipr_ext_vpd vpd;
749 u32 data[476];
750}__attribute__((packed, aligned (4)));
751
49dc6a18
BK		 752struct ipr_hostrcb_config_element {
753 u8 type_status;
754#define IPR_PATH_CFG_TYPE_MASK 0xF0
755#define IPR_PATH_CFG_NOT_EXIST 0x00
756#define IPR_PATH_CFG_IOA_PORT 0x10
757#define IPR_PATH_CFG_EXP_PORT 0x20
758#define IPR_PATH_CFG_DEVICE_PORT 0x30
759#define IPR_PATH_CFG_DEVICE_LUN 0x40
760
761#define IPR_PATH_CFG_STATUS_MASK 0x0F
762#define IPR_PATH_CFG_NO_PROB 0x00
763#define IPR_PATH_CFG_DEGRADED 0x01
764#define IPR_PATH_CFG_FAILED 0x02
765#define IPR_PATH_CFG_SUSPECT 0x03
766#define IPR_PATH_NOT_DETECTED 0x04
767#define IPR_PATH_INCORRECT_CONN 0x05
768
769 u8 cascaded_expander;
770 u8 phy;
771 u8 link_rate;
772#define IPR_PHY_LINK_RATE_MASK 0x0F
773
774 __be32 wwid[2];
775}__attribute__((packed, aligned (4)));
776
777struct ipr_hostrcb_fabric_desc {
778 __be16 length;
779 u8 ioa_port;
780 u8 cascaded_expander;
781 u8 phy;
782 u8 path_state;
783#define IPR_PATH_ACTIVE_MASK 0xC0
784#define IPR_PATH_NO_INFO 0x00
785#define IPR_PATH_ACTIVE 0x40
786#define IPR_PATH_NOT_ACTIVE 0x80
787
788#define IPR_PATH_STATE_MASK 0x0F
789#define IPR_PATH_STATE_NO_INFO 0x00
790#define IPR_PATH_HEALTHY 0x01
791#define IPR_PATH_DEGRADED 0x02
792#define IPR_PATH_FAILED 0x03
793
794 __be16 num_entries;
795 struct ipr_hostrcb_config_element elem[1];
796}__attribute__((packed, aligned (4)));
797
798#define for_each_fabric_cfg(fabric, cfg) \
799 for (cfg = (fabric)->elem; \
800 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
801 cfg++)
802
803struct ipr_hostrcb_type_20_error {
804 u8 failure_reason[64];
805 u8 reserved[3];
806 u8 num_entries;
807 struct ipr_hostrcb_fabric_desc desc[1];
808}__attribute__((packed, aligned (4)));
809
1da177e4
LT		 810struct ipr_hostrcb_error {
811 __be32 failing_dev_ioasc;
812 struct ipr_res_addr failing_dev_res_addr;
813 __be32 failing_dev_res_handle;
814 __be32 prc;
815 union {
816 struct ipr_hostrcb_type_ff_error type_ff_error;
817 struct ipr_hostrcb_type_01_error type_01_error;
818 struct ipr_hostrcb_type_02_error type_02_error;
819 struct ipr_hostrcb_type_03_error type_03_error;
820 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 821 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8
BK		 822 struct ipr_hostrcb_type_12_error type_12_error;
823 struct ipr_hostrcb_type_13_error type_13_error;
824 struct ipr_hostrcb_type_14_error type_14_error;
825 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 826 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT		 827 } u;
828}__attribute__((packed, aligned (4)));
829
830struct ipr_hostrcb_raw {
831 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
832}__attribute__((packed, aligned (4)));
833
834struct ipr_hcam {
835 u8 op_code;
836#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
837#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
838
839 u8 notify_type;
840#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
841#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
842#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
843#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
844#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
845
846 u8 notifications_lost;
847#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
848#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
849
850 u8 flags;
851#define IPR_HOSTRCB_INTERNAL_OPER 0x80
852#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
853
854 u8 overlay_id;
855#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
856#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
857#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
858#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
859#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 860#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8
BK		 861#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
862#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
863#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
864#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
865#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 866#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1da177e4
LT		 867#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
868
869 u8 reserved1[3];
870 __be32 ilid;
871 __be32 time_since_last_ioa_reset;
872 __be32 reserved2;
873 __be32 length;
874
875 union {
876 struct ipr_hostrcb_error error;
877 struct ipr_hostrcb_cfg_ch_not ccn;
878 struct ipr_hostrcb_raw raw;
879 } u;
880}__attribute__((packed, aligned (4)));
881
882struct ipr_hostrcb {
883 struct ipr_hcam hcam;
884 dma_addr_t hostrcb_dma;
885 struct list_head queue;
49dc6a18 886 struct ipr_ioa_cfg *ioa_cfg;
1da177e4
LT		 887};
888
889/* IPR smart dump table structures */
890struct ipr_sdt_entry {
891 __be32 bar_str_offset;
892 __be32 end_offset;
893 u8 entry_byte;
894 u8 reserved[3];
895
896 u8 flags;
897#define IPR_SDT_ENDIAN 0x80
898#define IPR_SDT_VALID_ENTRY 0x20
899
900 u8 resv;
901 __be16 priority;
902}__attribute__((packed, aligned (4)));
903
904struct ipr_sdt_header {
905 __be32 state;
906 __be32 num_entries;
907 __be32 num_entries_used;
908 __be32 dump_size;
909}__attribute__((packed, aligned (4)));
910
911struct ipr_sdt {
912 struct ipr_sdt_header hdr;
913 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
914}__attribute__((packed, aligned (4)));
915
916struct ipr_uc_sdt {
917 struct ipr_sdt_header hdr;
918 struct ipr_sdt_entry entry[1];
919}__attribute__((packed, aligned (4)));
920
921/*
922 * Driver types
923 */
924struct ipr_bus_attributes {
925 u8 bus;
926 u8 qas_enabled;
927 u8 bus_width;
928 u8 reserved;
929 u32 max_xfer_rate;
930};
931
35a39691
BK		 932struct ipr_sata_port {
933 struct ipr_ioa_cfg *ioa_cfg;
934 struct ata_port *ap;
935 struct ipr_resource_entry *res;
936 struct ipr_ioasa_gata ioasa;
937};
938
1da177e4
LT		 939struct ipr_resource_entry {
940 struct ipr_config_table_entry cfgte;
941 u8 needs_sync_complete:1;
942 u8 in_erp:1;
943 u8 add_to_ml:1;
944 u8 del_from_ml:1;
945 u8 resetting_device:1;
946
947 struct scsi_device *sdev;
35a39691 948 struct ipr_sata_port *sata_port;
1da177e4
LT		 949 struct list_head queue;
950};
951
952struct ipr_resource_hdr {
953 u16 num_entries;
954 u16 reserved;
955};
956
957struct ipr_resource_table {
958 struct ipr_resource_hdr hdr;
959 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
960};
961
962struct ipr_misc_cbs {
963 struct ipr_ioa_vpd ioa_vpd;
62275040 964 struct ipr_inquiry_page0 page0_data;
1da177e4
LT		 965 struct ipr_inquiry_page3 page3_data;
966 struct ipr_mode_pages mode_pages;
967 struct ipr_supported_device supp_dev;
968};
969
970struct ipr_interrupt_offsets {
971 unsigned long set_interrupt_mask_reg;
972 unsigned long clr_interrupt_mask_reg;
973 unsigned long sense_interrupt_mask_reg;
974 unsigned long clr_interrupt_reg;
975
976 unsigned long sense_interrupt_reg;
977 unsigned long ioarrin_reg;
978 unsigned long sense_uproc_interrupt_reg;
979 unsigned long set_uproc_interrupt_reg;
980 unsigned long clr_uproc_interrupt_reg;
981};
982
983struct ipr_interrupts {
984 void __iomem *set_interrupt_mask_reg;
985 void __iomem *clr_interrupt_mask_reg;
986 void __iomem *sense_interrupt_mask_reg;
987 void __iomem *clr_interrupt_reg;
988
989 void __iomem *sense_interrupt_reg;
990 void __iomem *ioarrin_reg;
991 void __iomem *sense_uproc_interrupt_reg;
992 void __iomem *set_uproc_interrupt_reg;
993 void __iomem *clr_uproc_interrupt_reg;
994};
995
996struct ipr_chip_cfg_t {
997 u32 mailbox;
998 u8 cache_line_size;
999 struct ipr_interrupt_offsets regs;
1000};
1001
1002struct ipr_chip_t {
1003 u16 vendor;
1004 u16 device;
1005 const struct ipr_chip_cfg_t *cfg;
1006};
1007
1008enum ipr_shutdown_type {
1009 IPR_SHUTDOWN_NORMAL = 0x00,
1010 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1011 IPR_SHUTDOWN_ABBREV = 0x80,
1012 IPR_SHUTDOWN_NONE = 0x100
1013};
1014
1015struct ipr_trace_entry {
1016 u32 time;
1017
1018 u8 op_code;
35a39691 1019 u8 ata_op_code;
1da177e4
LT		 1020 u8 type;
1021#define IPR_TRACE_START 0x00
1022#define IPR_TRACE_FINISH 0xff
35a39691 1023 u8 cmd_index;
1da177e4
LT		 1024
1025 __be32 res_handle;
1026 union {
1027 u32 ioasc;
1028 u32 add_data;
1029 u32 res_addr;
1030 } u;
1031};
1032
1033struct ipr_sglist {
1034 u32 order;
1035 u32 num_sg;
12baa420 1036 u32 num_dma_sg;
1da177e4
LT		 1037 u32 buffer_len;
1038 struct scatterlist scatterlist[1];
1039};
1040
1041enum ipr_sdt_state {
1042 INACTIVE,
1043 WAIT_FOR_DUMP,
1044 GET_DUMP,
1045 ABORT_DUMP,
1046 DUMP_OBTAINED
1047};
1048
62275040
BK		 1049enum ipr_cache_state {
1050 CACHE_NONE,
1051 CACHE_DISABLED,
1052 CACHE_ENABLED,
1053 CACHE_INVALID
1054};
1055
1da177e4
LT		 1056/* Per-controller data */
1057struct ipr_ioa_cfg {
1058 char eye_catcher[8];
1059#define IPR_EYECATCHER "iprcfg"
1060
1061 struct list_head queue;
1062
1063 u8 allow_interrupts:1;
1064 u8 in_reset_reload:1;
1065 u8 in_ioa_bringdown:1;
1066 u8 ioa_unit_checked:1;
1067 u8 ioa_is_dead:1;
1068 u8 dump_taken:1;
1069 u8 allow_cmds:1;
1070 u8 allow_ml_add_del:1;
ce155cce 1071 u8 needs_hard_reset:1;
1da177e4 1072
62275040 1073 enum ipr_cache_state cache_state;
1da177e4
LT		 1074 u16 type; /* CCIN of the card */
1075
1076 u8 log_level;
1077#define IPR_MAX_LOG_LEVEL 4
1078#define IPR_DEFAULT_LOG_LEVEL 2
1079
1080#define IPR_NUM_TRACE_INDEX_BITS 8
1081#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1082#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1083 char trace_start[8];
1084#define IPR_TRACE_START_LABEL "trace"
1085 struct ipr_trace_entry *trace;
1086 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1087
1088 /*
1089 * Queue for free command blocks
1090 */
1091 char ipr_free_label[8];
1092#define IPR_FREEQ_LABEL "free-q"
1093 struct list_head free_q;
1094
1095 /*
1096 * Queue for command blocks outstanding to the adapter
1097 */
1098 char ipr_pending_label[8];
1099#define IPR_PENDQ_LABEL "pend-q"
1100 struct list_head pending_q;
1101
1102 char cfg_table_start[8];
1103#define IPR_CFG_TBL_START "cfg"
1104 struct ipr_config_table *cfg_table;
1105 dma_addr_t cfg_table_dma;
1106
1107 char resource_table_label[8];
1108#define IPR_RES_TABLE_LABEL "res_tbl"
1109 struct ipr_resource_entry *res_entries;
1110 struct list_head free_res_q;
1111 struct list_head used_res_q;
1112
1113 char ipr_hcam_label[8];
1114#define IPR_HCAM_LABEL "hcams"
1115 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1116 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1117 struct list_head hostrcb_free_q;
1118 struct list_head hostrcb_pending_q;
1119
1120 __be32 *host_rrq;
1121 dma_addr_t host_rrq_dma;
1122#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1123#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1124#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1125#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1126 volatile __be32 *hrrq_start;
1127 volatile __be32 *hrrq_end;
1128 volatile __be32 *hrrq_curr;
1129 volatile u32 toggle_bit;
1130
1131 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1132
5469cb5b 1133 unsigned int transop_timeout;
1da177e4
LT		 1134 const struct ipr_chip_cfg_t *chip_cfg;
1135
1136 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1137 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1138 void __iomem *ioa_mailbox;
1139 struct ipr_interrupts regs;
1140
1141 u16 saved_pcix_cmd_reg;
1142 u16 reset_retries;
1143
1144 u32 errors_logged;
3d1d0da6 1145 u32 doorbell;
1da177e4
LT		 1146
1147 struct Scsi_Host *host;
1148 struct pci_dev *pdev;
1149 struct ipr_sglist *ucode_sglist;
1da177e4
LT		 1150 u8 saved_mode_page_len;
1151
1152 struct work_struct work_q;
1153
1154 wait_queue_head_t reset_wait_q;
1155
1156 struct ipr_dump *dump;
1157 enum ipr_sdt_state sdt_state;
1158
1159 struct ipr_misc_cbs *vpd_cbs;
1160 dma_addr_t vpd_cbs_dma;
1161
1162 struct pci_pool *ipr_cmd_pool;
1163
1164 struct ipr_cmnd *reset_cmd;
1165
35a39691 1166 struct ata_host ata_host;
1da177e4
LT		 1167 char ipr_cmd_label[8];
1168#define IPR_CMD_LABEL "ipr_cmnd"
1169 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1170 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1171};
1172
1173struct ipr_cmnd {
1174 struct ipr_ioarcb ioarcb;
1175 struct ipr_ioasa ioasa;
1176 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1177 struct list_head queue;
1178 struct scsi_cmnd *scsi_cmd;
35a39691 1179 struct ata_queued_cmd *qc;
1da177e4
LT		 1180 struct completion completion;
1181 struct timer_list timer;
1182 void (*done) (struct ipr_cmnd *);
1183 int (*job_step) (struct ipr_cmnd *);
dfed823e 1184 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT		 1185 u16 cmd_index;
1186 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1187 dma_addr_t sense_buffer_dma;
1188 unsigned short dma_use_sg;
1189 dma_addr_t dma_handle;
1190 struct ipr_cmnd *sibling;
1191 union {
1192 enum ipr_shutdown_type shutdown_type;
1193 struct ipr_hostrcb *hostrcb;
1194 unsigned long time_left;
1195 unsigned long scratch;
1196 struct ipr_resource_entry *res;
1197 struct scsi_device *sdev;
1198 } u;
1199
1200 struct ipr_ioa_cfg *ioa_cfg;
1201};
1202
1203struct ipr_ses_table_entry {
1204 char product_id[17];
1205 char compare_product_id_byte[17];
1206 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1207};
1208
1209struct ipr_dump_header {
1210 u32 eye_catcher;
1211#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1212 u32 len;
1213 u32 num_entries;
1214 u32 first_entry_offset;
1215 u32 status;
1216#define IPR_DUMP_STATUS_SUCCESS 0
1217#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1218#define IPR_DUMP_STATUS_FAILED 0xffffffff
1219 u32 os;
1220#define IPR_DUMP_OS_LINUX 0x4C4E5558
1221 u32 driver_name;
1222#define IPR_DUMP_DRIVER_NAME 0x49505232
1223}__attribute__((packed, aligned (4)));
1224
1225struct ipr_dump_entry_header {
1226 u32 eye_catcher;
1227#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1228 u32 len;
1229 u32 num_elems;
1230 u32 offset;
1231 u32 data_type;
1232#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1233#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1234 u32 id;
1235#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1236#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1237#define IPR_DUMP_TRACE_ID 0x54524143
1238#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1239#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1240#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1241#define IPR_DUMP_PEND_OPS 0x414F5053
1242 u32 status;
1243}__attribute__((packed, aligned (4)));
1244
1245struct ipr_dump_location_entry {
1246 struct ipr_dump_entry_header hdr;
1247 u8 location[BUS_ID_SIZE];
1248}__attribute__((packed));
1249
1250struct ipr_dump_trace_entry {
1251 struct ipr_dump_entry_header hdr;
1252 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1253}__attribute__((packed, aligned (4)));
1254
1255struct ipr_dump_version_entry {
1256 struct ipr_dump_entry_header hdr;
1257 u8 version[sizeof(IPR_DRIVER_VERSION)];
1258};
1259
1260struct ipr_dump_ioa_type_entry {
1261 struct ipr_dump_entry_header hdr;
1262 u32 type;
1263 u32 fw_version;
1264};
1265
1266struct ipr_driver_dump {
1267 struct ipr_dump_header hdr;
1268 struct ipr_dump_version_entry version_entry;
1269 struct ipr_dump_location_entry location_entry;
1270 struct ipr_dump_ioa_type_entry ioa_type_entry;
1271 struct ipr_dump_trace_entry trace_entry;
1272}__attribute__((packed));
1273
1274struct ipr_ioa_dump {
1275 struct ipr_dump_entry_header hdr;
1276 struct ipr_sdt sdt;
1277 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1278 u32 reserved;
1279 u32 next_page_index;
1280 u32 page_offset;
1281 u32 format;
1282#define IPR_SDT_FMT2 2
1283#define IPR_SDT_UNKNOWN 3
1284}__attribute__((packed, aligned (4)));
1285
1286struct ipr_dump {
1287 struct kref kref;
1288 struct ipr_ioa_cfg *ioa_cfg;
1289 struct ipr_driver_dump driver_dump;
1290 struct ipr_ioa_dump ioa_dump;
1291};
1292
1293struct ipr_error_table_t {
1294 u32 ioasc;
1295 int log_ioasa;
1296 int log_hcam;
1297 char *error;
1298};
1299
1300struct ipr_software_inq_lid_info {
1301 __be32 load_id;
1302 __be32 timestamp[3];
1303}__attribute__((packed, aligned (4)));
1304
1305struct ipr_ucode_image_header {
1306 __be32 header_length;
1307 __be32 lid_table_offset;
1308 u8 major_release;
1309 u8 card_type;
1310 u8 minor_release[2];
1311 u8 reserved[20];
1312 char eyecatcher[16];
1313 __be32 num_lids;
1314 struct ipr_software_inq_lid_info lid[1];
1315}__attribute__((packed, aligned (4)));
1316
1317/*
1318 * Macros
1319 */
d3c74871 1320#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT		 1321
1322#ifdef CONFIG_SCSI_IPR_TRACE
1323#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1324#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1325#else
1326#define ipr_create_trace_file(kobj, attr) 0
1327#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1328#endif
1329
1330#ifdef CONFIG_SCSI_IPR_DUMP
1331#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1332#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1333#else
1334#define ipr_create_dump_file(kobj, attr) 0
1335#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1336#endif
1337
1338/*
1339 * Error logging macros
1340 */
1341#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1342#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT		 1343#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1344
fb3ed3cb
BK		 1345#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1346 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1347 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1348
fb3ed3cb
BK		 1349#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1350 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4
LT		 1351
1352#define ipr_res_err(ioa_cfg, res, fmt, ...) \
fb3ed3cb 1353 ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__)
1da177e4 1354
fa15b1f6
BK		 1355#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1356{ \
1357 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1358 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1359 } else { \
1360 ipr_err(fmt": %d:%d:%d:%d\n", \
1361 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1362 (res).bus, (res).target, (res).lun); \
1363 } \
1364}
1365
49dc6a18
BK		 1366#define ipr_hcam_err(hostrcb, fmt, ...) \
1367{ \
1368 if (ipr_is_device(&(hostrcb)->hcam.u.error.failing_dev_res_addr)) { \
1369 ipr_ra_err((hostrcb)->ioa_cfg, \
1370 (hostrcb)->hcam.u.error.failing_dev_res_addr, \
1371 fmt, ##__VA_ARGS__); \
1372 } else { \
1373 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, ##__VA_ARGS__); \
1374 } \
1375}
1376
1da177e4
LT		 1377#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1378 __FILE__, __FUNCTION__, __LINE__)
1379
d3c74871
BK		 1380#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __FUNCTION__))
1381#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __FUNCTION__))
1da177e4
LT		 1382
1383#define ipr_err_separator \
1384ipr_err("----------------------------------------------------------\n")
1385
1386
1387/*
1388 * Inlines
1389 */
1390
1391/**
1392 * ipr_is_ioa_resource - Determine if a resource is the IOA
1393 * @res: resource entry struct
1394 *
1395 * Return value:
1396 * 1 if IOA / 0 if not IOA
1397 **/
1398static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1399{
1400 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0;
1401}
1402
1403/**
1404 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1405 * @res: resource entry struct
1406 *
1407 * Return value:
1408 * 1 if AF DASD / 0 if not AF DASD
1409 **/
1410static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1411{
1412 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1413 !ipr_is_ioa_resource(res) &&
1414 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
1415 return 1;
1416 else
1417 return 0;
1418}
1419
1420/**
1421 * ipr_is_vset_device - Determine if a resource is a VSET
1422 * @res: resource entry struct
1423 *
1424 * Return value:
1425 * 1 if VSET / 0 if not VSET
1426 **/
1427static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1428{
1429 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1430 !ipr_is_ioa_resource(res) &&
1431 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
1432 return 1;
1433 else
1434 return 0;
1435}
1436
1437/**
1438 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1439 * @res: resource entry struct
1440 *
1441 * Return value:
1442 * 1 if GSCSI / 0 if not GSCSI
1443 **/
1444static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1445{
1446 if (!ipr_is_ioa_resource(res) &&
1447 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
1448 return 1;
1449 else
1450 return 0;
1451}
1452
e4fbf44e
BK		 1453/**
1454 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1455 * @res: resource entry struct
1456 *
1457 * Return value:
1458 * 1 if SCSI disk / 0 if not SCSI disk
1459 **/
1460static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1461{
1462 if (ipr_is_af_dasd_device(res) ||
1463 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data)))
1464 return 1;
1465 else
1466 return 0;
1467}
1468
b5145d25
BK		 1469/**
1470 * ipr_is_gata - Determine if a resource is a generic ATA resource
1471 * @res: resource entry struct
1472 *
1473 * Return value:
1474 * 1 if GATA / 0 if not GATA
1475 **/
1476static inline int ipr_is_gata(struct ipr_resource_entry *res)
1477{
1478 if (!ipr_is_ioa_resource(res) &&
1479 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_ATA)
1480 return 1;
1481 else
1482 return 0;
1483}
1484
ee0a90fa
BK		 1485/**
1486 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1487 * @res: resource entry struct
1488 *
1489 * Return value:
1490 * 1 if NACA queueing model / 0 if not NACA queueing model
1491 **/
1492static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1493{
1494 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL)
1495 return 1;
1496 return 0;
1497}
1498
1da177e4
LT		 1499/**
1500 * ipr_is_device - Determine if resource address is that of a device
1501 * @res_addr: resource address struct
1502 *
1503 * Return value:
1504 * 1 if AF / 0 if not AF
1505 **/
1506static inline int ipr_is_device(struct ipr_res_addr *res_addr)
1507{
1508 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
d71a8b0c 1509 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1da177e4
LT		 1510 return 1;
1511
1512 return 0;
1513}
1514
1515/**
1516 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1517 * @sdt_word: SDT address
1518 *
1519 * Return value:
1520 * 1 if format 2 / 0 if not
1521 **/
1522static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1523{
1524 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1525
1526 switch (bar_sel) {
1527 case IPR_SDT_FMT2_BAR0_SEL:
1528 case IPR_SDT_FMT2_BAR1_SEL:
1529 case IPR_SDT_FMT2_BAR2_SEL:
1530 case IPR_SDT_FMT2_BAR3_SEL:
1531 case IPR_SDT_FMT2_BAR4_SEL:
1532 case IPR_SDT_FMT2_BAR5_SEL:
1533 case IPR_SDT_FMT2_EXP_ROM_SEL:
1534 return 1;
1535 };
1536
1537 return 0;
1538}
1539
1540#endif