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[SCSI] gdth: Setup proper per-command private data
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / gdth.c
CommitLineData
1da177e4
LT		 1/************************************************************************
2 * Linux driver for *
3 * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
4 * Intel Corporation: Storage RAID Controllers *
5 * *
6 * gdth.c *
cbd5f69b 7 * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
1da177e4 8 * Copyright (C) 2002-04 Intel Corporation *
cbd5f69b 9 * Copyright (C) 2003-06 Adaptec Inc. *
1da177e4
LT		 10 * <achim_leubner@adaptec.com> *
11 * *
12 * Additions/Fixes: *
13 * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
14 * Johannes Dinner <johannes_dinner@adaptec.com> *
15 * *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published *
18 * by the Free Software Foundation; either version 2 of the License, *
19 * or (at your option) any later version. *
20 * *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
25 * *
26 * You should have received a copy of the GNU General Public License *
27 * along with this kernel; if not, write to the Free Software *
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
29 * *
8d7a5da4 30 * Linux kernel 2.6.x supported *
1da177e4 31 * *
1da177e4
LT		 32 ************************************************************************/
33
34/* All GDT Disk Array Controllers are fully supported by this driver.
35 * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
36 * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
37 * list of all controller types.
38 *
39 * If you have one or more GDT3000/3020 EISA controllers with
40 * controller BIOS disabled, you have to set the IRQ values with the
41 * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
42 * the IRQ values for the EISA controllers.
43 *
44 * After the optional list of IRQ values, other possible
45 * command line options are:
46 * disable:Y disable driver
47 * disable:N enable driver
48 * reserve_mode:0 reserve no drives for the raw service
49 * reserve_mode:1 reserve all not init., removable drives
50 * reserve_mode:2 reserve all not init. drives
51 * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
52 * h- controller no., b- channel no.,
53 * t- target ID, l- LUN
54 * reverse_scan:Y reverse scan order for PCI controllers
55 * reverse_scan:N scan PCI controllers like BIOS
56 * max_ids:x x - target ID count per channel (1..MAXID)
57 * rescan:Y rescan all channels/IDs
58 * rescan:N use all devices found until now
1da177e4
LT		 59 * hdr_channel:x x - number of virtual bus for host drives
60 * shared_access:Y disable driver reserve/release protocol to
61 * access a shared resource from several nodes,
575c9687 62 * appropriate controller firmware required
1da177e4
LT		 63 * shared_access:N enable driver reserve/release protocol
64 * probe_eisa_isa:Y scan for EISA/ISA controllers
65 * probe_eisa_isa:N do not scan for EISA/ISA controllers
66 * force_dma32:Y use only 32 bit DMA mode
67 * force_dma32:N use 64 bit DMA mode, if supported
68 *
69 * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
52759e6a 70 * max_ids:127,rescan:N,hdr_channel:0,
1da177e4
LT		 71 * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
72 * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
73 *
74 * When loading the gdth driver as a module, the same options are available.
75 * You can set the IRQs with "IRQ=...". However, the syntax to specify the
76 * options changes slightly. You must replace all ',' between options
77 * with ' ' and all ':' with '=' and you must use
78 * '1' in place of 'Y' and '0' in place of 'N'.
79 *
80 * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
52759e6a 81 * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
1da177e4
LT		 82 * probe_eisa_isa=0 force_dma32=0"
83 * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
84 */
85
86/* The meaning of the Scsi_Pointer members in this driver is as follows:
87 * ptr: Chaining
88 * this_residual: Command priority
3058d5de
BH		 89 * buffer: unused
90 * dma_handle: will drop in !use_sg patch.
1da177e4
LT		 91 * buffers_residual: Timeout value
92 * Status: Command status (gdth_do_cmd()), DMA mem. mappings
93 * Message: Additional info (gdth_do_cmd()), DMA direction
94 * have_data_in: Flag for gdth_wait_completion()
95 * sent_command: Opcode special command
96 * phase: Service/parameter/return code special command
97 */
98
99
100/* interrupt coalescing */
101/* #define INT_COAL */
102
103/* statistics */
104#define GDTH_STATISTICS
105
106#include <linux/module.h>
107
108#include <linux/version.h>
109#include <linux/kernel.h>
110#include <linux/types.h>
111#include <linux/pci.h>
112#include <linux/string.h>
113#include <linux/ctype.h>
114#include <linux/ioport.h>
115#include <linux/delay.h>
1da177e4
LT		 116#include <linux/interrupt.h>
117#include <linux/in.h>
118#include <linux/proc_fs.h>
119#include <linux/time.h>
120#include <linux/timer.h>
910638ae 121#include <linux/dma-mapping.h>
835cc24a 122#include <linux/list.h>
cbd5f69b 123
1da177e4
LT		 124#ifdef GDTH_RTC
125#include <linux/mc146818rtc.h>
126#endif
127#include <linux/reboot.h>
128
129#include <asm/dma.h>
130#include <asm/system.h>
131#include <asm/io.h>
132#include <asm/uaccess.h>
133#include <linux/spinlock.h>
1da177e4 134#include <linux/blkdev.h>
1da177e4
LT		 135
136#include "scsi.h"
137#include <scsi/scsi_host.h>
cbd5f69b 138#include "gdth.h"
1da177e4
LT		 139
140static void gdth_delay(int milliseconds);
141static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
7d12e780 142static irqreturn_t gdth_interrupt(int irq, void *dev_id);
10e1b4bc
BH		 143static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
144 int gdth_from_wait, int* pIndex);
45f1a41b
BH		 145static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
146 Scsi_Cmnd *scp);
147static int gdth_async_event(gdth_ha_str *ha);
1da177e4
LT		 148static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
149
45f1a41b
BH		 150static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
151static void gdth_next(gdth_ha_str *ha);
152static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
153static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
1da177e4
LT		 154static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
155 ushort idx, gdth_evt_data *evt);
156static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
157static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
158 gdth_evt_str *estr);
159static void gdth_clear_events(void);
160
45f1a41b 161static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
1da177e4 162 char *buffer,ushort count);
45f1a41b
BH		 163static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
164static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
1da177e4 165
45f1a41b 166static void gdth_enable_int(gdth_ha_str *ha);
10e1b4bc 167static unchar gdth_get_status(gdth_ha_str *ha, int irq);
45f1a41b
BH		 168static int gdth_test_busy(gdth_ha_str *ha);
169static int gdth_get_cmd_index(gdth_ha_str *ha);
170static void gdth_release_event(gdth_ha_str *ha);
171static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
172static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
173 ulong32 p1, ulong64 p2,ulong64 p3);
174static int gdth_search_drives(gdth_ha_str *ha);
175static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
1da177e4 176
45f1a41b 177static const char *gdth_ctr_name(gdth_ha_str *ha);
1da177e4
LT		 178
179static int gdth_open(struct inode *inode, struct file *filep);
180static int gdth_close(struct inode *inode, struct file *filep);
181static int gdth_ioctl(struct inode *inode, struct file *filep,
182 unsigned int cmd, unsigned long arg);
183
45f1a41b 184static void gdth_flush(gdth_ha_str *ha);
1da177e4 185static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
cbd5f69b 186static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
3058d5de
BH		 187static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
188 struct gdth_cmndinfo *cmndinfo);
cbd5f69b 189static void gdth_scsi_done(struct scsi_cmnd *scp);
1da177e4
LT		 190
191#ifdef DEBUG_GDTH
192static unchar DebugState = DEBUG_GDTH;
193
194#ifdef __SERIAL__
195#define MAX_SERBUF 160
196static void ser_init(void);
197static void ser_puts(char *str);
198static void ser_putc(char c);
199static int ser_printk(const char *fmt, ...);
200static char strbuf[MAX_SERBUF+1];
201#ifdef __COM2__
202#define COM_BASE 0x2f8
203#else
204#define COM_BASE 0x3f8
205#endif
206static void ser_init()
207{
208 unsigned port=COM_BASE;
209
210 outb(0x80,port+3);
211 outb(0,port+1);
212 /* 19200 Baud, if 9600: outb(12,port) */
213 outb(6, port);
214 outb(3,port+3);
215 outb(0,port+1);
216 /*
217 ser_putc('I');
218 ser_putc(' ');
219 */
220}
221
222static void ser_puts(char *str)
223{
224 char *ptr;
225
226 ser_init();
227 for (ptr=str;*ptr;++ptr)
228 ser_putc(*ptr);
229}
230
231static void ser_putc(char c)
232{
233 unsigned port=COM_BASE;
234
235 while ((inb(port+5) & 0x20)==0);
236 outb(c,port);
237 if (c==0x0a)
238 {
239 while ((inb(port+5) & 0x20)==0);
240 outb(0x0d,port);
241 }
242}
243
244static int ser_printk(const char *fmt, ...)
245{
246 va_list args;
247 int i;
248
249 va_start(args,fmt);
250 i = vsprintf(strbuf,fmt,args);
251 ser_puts(strbuf);
252 va_end(args);
253 return i;
254}
255
256#define TRACE(a) {if (DebugState==1) {ser_printk a;}}
257#define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
258#define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
259
260#else /* !__SERIAL__ */
261#define TRACE(a) {if (DebugState==1) {printk a;}}
262#define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
263#define TRACE3(a) {if (DebugState!=0) {printk a;}}
264#endif
265
266#else /* !DEBUG */
267#define TRACE(a)
268#define TRACE2(a)
269#define TRACE3(a)
270#endif
271
272#ifdef GDTH_STATISTICS
273static ulong32 max_rq=0, max_index=0, max_sg=0;
274#ifdef INT_COAL
275static ulong32 max_int_coal=0;
276#endif
277static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
278static struct timer_list gdth_timer;
279#endif
280
281#define PTR2USHORT(a) (ushort)(ulong)(a)
6391a113
TK		 282#define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
283#define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
1da177e4 284
1da177e4
LT		 285#define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
286
aed91cb5 287#ifdef CONFIG_ISA
1da177e4 288static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
aed91cb5 289#endif
706a5d45 290#ifdef CONFIG_EISA
1da177e4 291static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
706a5d45 292#endif
1da177e4 293static unchar gdth_polling; /* polling if TRUE */
1da177e4 294static int gdth_ctr_count = 0; /* controller count */
884f7fba 295static LIST_HEAD(gdth_instances); /* controller list */
1da177e4
LT		 296static unchar gdth_write_through = FALSE; /* write through */
297static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
298static int elastidx;
299static int eoldidx;
300static int major;
301
302#define DIN 1 /* IN data direction */
303#define DOU 2 /* OUT data direction */
304#define DNO DIN /* no data transfer */
305#define DUN DIN /* unknown data direction */
306static unchar gdth_direction_tab[0x100] = {
307 DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
308 DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
309 DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
310 DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
311 DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
312 DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
313 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
314 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
315 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
316 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
317 DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
318 DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
319 DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
320 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
321 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
322 DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
323};
324
325/* LILO and modprobe/insmod parameters */
326/* IRQ list for GDT3000/3020 EISA controllers */
327static int irq[MAXHA] __initdata =
328{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
329 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
330/* disable driver flag */
331static int disable __initdata = 0;
332/* reserve flag */
333static int reserve_mode = 1;
334/* reserve list */
335static int reserve_list[MAX_RES_ARGS] =
336{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
337 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
338 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
339/* scan order for PCI controllers */
340static int reverse_scan = 0;
341/* virtual channel for the host drives */
342static int hdr_channel = 0;
343/* max. IDs per channel */
344static int max_ids = MAXID;
345/* rescan all IDs */
346static int rescan = 0;
1da177e4
LT		 347/* shared access */
348static int shared_access = 1;
349/* enable support for EISA and ISA controllers */
350static int probe_eisa_isa = 0;
351/* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
352static int force_dma32 = 0;
353
354/* parameters for modprobe/insmod */
355module_param_array(irq, int, NULL, 0);
356module_param(disable, int, 0);
357module_param(reserve_mode, int, 0);
358module_param_array(reserve_list, int, NULL, 0);
359module_param(reverse_scan, int, 0);
360module_param(hdr_channel, int, 0);
361module_param(max_ids, int, 0);
362module_param(rescan, int, 0);
1da177e4
LT		 363module_param(shared_access, int, 0);
364module_param(probe_eisa_isa, int, 0);
365module_param(force_dma32, int, 0);
366MODULE_AUTHOR("Achim Leubner");
367MODULE_LICENSE("GPL");
368
369/* ioctl interface */
00977a59 370static const struct file_operations gdth_fops = {
1da177e4
LT		 371 .ioctl = gdth_ioctl,
372 .open = gdth_open,
373 .release = gdth_close,
374};
375
376#include "gdth_proc.h"
377#include "gdth_proc.c"
378
379/* notifier block to get a notify on system shutdown/halt/reboot */
380static struct notifier_block gdth_notifier = {
381 gdth_halt, NULL, 0
382};
e041c683 383static int notifier_disabled = 0;
1da177e4 384
884f7fba
BH		 385static gdth_ha_str *gdth_find_ha(int hanum)
386{
387 gdth_ha_str *ha;
388
389 list_for_each_entry(ha, &gdth_instances, list)
390 if (hanum == ha->hanum)
391 return ha;
392
393 return NULL;
394}
395
3058d5de
BH		 396static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
397{
398 struct gdth_cmndinfo *priv = NULL;
399 ulong flags;
400 int i;
401
402 spin_lock_irqsave(&ha->smp_lock, flags);
403
404 for (i=0; i<GDTH_MAXCMDS; ++i) {
405 if (ha->cmndinfo[i].index == 0) {
406 priv = &ha->cmndinfo[i];
407 priv->index = i+1;
408 memset(priv, 0, sizeof(*priv));
409 break;
410 }
411 }
412
413 spin_unlock_irqrestore(&ha->smp_lock, flags);
414
415 return priv;
416}
417
418static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
419{
420 BUG_ON(!priv);
421 priv->index = 0;
422}
423
1da177e4
LT		 424static void gdth_delay(int milliseconds)
425{
426 if (milliseconds == 0) {
427 udelay(1);
428 } else {
429 mdelay(milliseconds);
430 }
431}
432
cbd5f69b
LA		 433static void gdth_scsi_done(struct scsi_cmnd *scp)
434{
3058d5de
BH		 435 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
436 int internal_command = cmndinfo->internal_command;
437
b8bff2ae 438 TRACE2(("gdth_scsi_done()\n"));
cbd5f69b 439
3058d5de
BH		 440 gdth_put_cmndinfo(cmndinfo);
441 scp->host_scribble = NULL;
442
443 if (internal_command)
b8bff2ae
MW		 444 complete((struct completion *)scp->request);
445 else
446 scp->scsi_done(scp);
cbd5f69b
LA		 447}
448
449int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
450 int timeout, u32 *info)
451{
3058d5de 452 gdth_ha_str *ha = shost_priv(sdev->host);
cbd5f69b 453 Scsi_Cmnd *scp;
3058d5de 454 struct gdth_cmndinfo cmndinfo;
6e9a4738 455 DECLARE_COMPLETION_ONSTACK(wait);
cbd5f69b
LA		 456 int rval;
457
bbfbbbc1 458 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
cbd5f69b
LA		 459 if (!scp)
460 return -ENOMEM;
bbfbbbc1 461
cbd5f69b 462 scp->device = sdev;
3058d5de
BH		 463 memset(&cmndinfo, 0, sizeof(cmndinfo));
464
beb40487
CH		 465 /* use request field to save the ptr. to completion struct. */
466 scp->request = (struct request *)&wait;
cbd5f69b
LA		 467 scp->timeout_per_command = timeout*HZ;
468 scp->request_buffer = gdtcmd;
469 scp->cmd_len = 12;
470 memcpy(scp->cmnd, cmnd, 12);
471 scp->SCp.this_residual = IOCTL_PRI; /* priority */
3058d5de
BH		 472 cmndinfo.internal_command = 1;
473
474 TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
475 __gdth_queuecommand(ha, scp, &cmndinfo);
476
cbd5f69b
LA		 477 wait_for_completion(&wait);
478
479 rval = scp->SCp.Status;
480 if (info)
481 *info = scp->SCp.Message;
482 kfree(scp);
483 return rval;
484}
cbd5f69b
LA		 485
486int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
487 int timeout, u32 *info)
488{
489 struct scsi_device *sdev = scsi_get_host_dev(shost);
490 int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
491
492 scsi_free_host_dev(sdev);
493 return rval;
494}
495
1da177e4
LT		 496static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
497{
498 *cyls = size /HEADS/SECS;
499 if (*cyls <= MAXCYLS) {
500 *heads = HEADS;
501 *secs = SECS;
502 } else { /* too high for 64*32 */
503 *cyls = size /MEDHEADS/MEDSECS;
504 if (*cyls <= MAXCYLS) {
505 *heads = MEDHEADS;
506 *secs = MEDSECS;
507 } else { /* too high for 127*63 */
508 *cyls = size /BIGHEADS/BIGSECS;
509 *heads = BIGHEADS;
510 *secs = BIGSECS;
511 }
512 }
513}
514
515/* controller search and initialization functions */
706a5d45 516#ifdef CONFIG_EISA
1da177e4
LT		 517static int __init gdth_search_eisa(ushort eisa_adr)
518{
519 ulong32 id;
520
521 TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
522 id = inl(eisa_adr+ID0REG);
523 if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
524 if ((inb(eisa_adr+EISAREG) & 8) == 0)
525 return 0; /* not EISA configured */
526 return 1;
527 }
528 if (id == GDT3_ID) /* GDT3000 */
529 return 1;
530
531 return 0;
532}
706a5d45 533#endif /* CONFIG_EISA */
1da177e4 534
aed91cb5 535#ifdef CONFIG_ISA
1da177e4
LT		 536static int __init gdth_search_isa(ulong32 bios_adr)
537{
538 void __iomem *addr;
539 ulong32 id;
540
541 TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
542 if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
a52667f3 543 id = readl(addr);
1da177e4
LT		 544 iounmap(addr);
545 if (id == GDT2_ID) /* GDT2000 */
546 return 1;
547 }
548 return 0;
549}
aed91cb5 550#endif /* CONFIG_ISA */
1da177e4 551
8514ef27
CH		 552#ifdef CONFIG_PCI
553static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
554 ushort vendor, ushort dev);
555
1da177e4
LT		 556static int __init gdth_search_pci(gdth_pci_str *pcistr)
557{
558 ushort device, cnt;
559
560 TRACE(("gdth_search_pci()\n"));
561
562 cnt = 0;
563 for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
564 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
565 for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
566 device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
567 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
568 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
569 PCI_DEVICE_ID_VORTEX_GDTNEWRX);
570 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
571 PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
572 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
573 PCI_DEVICE_ID_INTEL_SRC);
574 gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
575 PCI_DEVICE_ID_INTEL_SRC_XSCALE);
576 return cnt;
577}
578
579/* Vortex only makes RAID controllers.
580 * We do not really want to specify all 550 ids here, so wildcard match.
581 */
6c4b7e4f 582static struct pci_device_id gdthtable[] __maybe_unused = {
1da177e4
LT		 583 {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
584 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
585 {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
586 {0}
587};
588MODULE_DEVICE_TABLE(pci,gdthtable);
589
590static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
cbd5f69b 591 ushort vendor, ushort device)
1da177e4
LT		 592{
593 ulong base0, base1, base2;
594 struct pci_dev *pdev;
595
596 TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
597 *cnt, vendor, device));
598
599 pdev = NULL;
600 while ((pdev = pci_find_device(vendor, device, pdev))
601 != NULL) {
602 if (pci_enable_device(pdev))
603 continue;
604 if (*cnt >= MAXHA)
605 return;
606 /* GDT PCI controller found, resources are already in pdev */
607 pcistr[*cnt].pdev = pdev;
1da177e4
LT		 608 pcistr[*cnt].irq = pdev->irq;
609 base0 = pci_resource_flags(pdev, 0);
610 base1 = pci_resource_flags(pdev, 1);
611 base2 = pci_resource_flags(pdev, 2);
612 if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
613 device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
614 if (!(base0 & IORESOURCE_MEM))
615 continue;
616 pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
617 } else { /* GDT6110, GDT6120, .. */
618 if (!(base0 & IORESOURCE_MEM) ||
619 !(base2 & IORESOURCE_MEM) ||
620 !(base1 & IORESOURCE_IO))
621 continue;
622 pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
623 pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
624 pcistr[*cnt].io = pci_resource_start(pdev, 1);
625 }
626 TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
8e9a8a0d
JG		 627 pcistr[*cnt].pdev->bus->number,
628 PCI_SLOT(pcistr[*cnt].pdev->devfn),
1da177e4
LT		 629 pcistr[*cnt].irq, pcistr[*cnt].dpmem));
630 (*cnt)++;
631 }
632}
633
1da177e4
LT		 634static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
635{
636 gdth_pci_str temp;
637 int i, changed;
638
639 TRACE(("gdth_sort_pci() cnt %d\n",cnt));
640 if (cnt == 0)
641 return;
642
643 do {
644 changed = FALSE;
645 for (i = 0; i < cnt-1; ++i) {
646 if (!reverse_scan) {
8e9a8a0d
JG		 647 if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
648 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
649 PCI_SLOT(pcistr[i].pdev->devfn) >
650 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
1da177e4
LT		 651 temp = pcistr[i];
652 pcistr[i] = pcistr[i+1];
653 pcistr[i+1] = temp;
654 changed = TRUE;
655 }
656 } else {
8e9a8a0d
JG		 657 if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
658 (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
659 PCI_SLOT(pcistr[i].pdev->devfn) <
660 PCI_SLOT(pcistr[i+1].pdev->devfn))) {
1da177e4
LT		 661 temp = pcistr[i];
662 pcistr[i] = pcistr[i+1];
663 pcistr[i+1] = temp;
664 changed = TRUE;
665 }
666 }
667 }
668 } while (changed);
669}
8514ef27 670#endif /* CONFIG_PCI */
1da177e4 671
706a5d45 672#ifdef CONFIG_EISA
1da177e4
LT		 673static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
674{
675 ulong32 retries,id;
676 unchar prot_ver,eisacf,i,irq_found;
677
678 TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
679
680 /* disable board interrupts, deinitialize services */
681 outb(0xff,eisa_adr+EDOORREG);
682 outb(0x00,eisa_adr+EDENABREG);
683 outb(0x00,eisa_adr+EINTENABREG);
684
685 outb(0xff,eisa_adr+LDOORREG);
686 retries = INIT_RETRIES;
687 gdth_delay(20);
688 while (inb(eisa_adr+EDOORREG) != 0xff) {
689 if (--retries == 0) {
690 printk("GDT-EISA: Initialization error (DEINIT failed)\n");
691 return 0;
692 }
693 gdth_delay(1);
694 TRACE2(("wait for DEINIT: retries=%d\n",retries));
695 }
696 prot_ver = inb(eisa_adr+MAILBOXREG);
697 outb(0xff,eisa_adr+EDOORREG);
698 if (prot_ver != PROTOCOL_VERSION) {
699 printk("GDT-EISA: Illegal protocol version\n");
700 return 0;
701 }
702 ha->bmic = eisa_adr;
703 ha->brd_phys = (ulong32)eisa_adr >> 12;
704
705 outl(0,eisa_adr+MAILBOXREG);
706 outl(0,eisa_adr+MAILBOXREG+4);
707 outl(0,eisa_adr+MAILBOXREG+8);
708 outl(0,eisa_adr+MAILBOXREG+12);
709
710 /* detect IRQ */
711 if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
712 ha->oem_id = OEM_ID_ICP;
713 ha->type = GDT_EISA;
714 ha->stype = id;
715 outl(1,eisa_adr+MAILBOXREG+8);
716 outb(0xfe,eisa_adr+LDOORREG);
717 retries = INIT_RETRIES;
718 gdth_delay(20);
719 while (inb(eisa_adr+EDOORREG) != 0xfe) {
720 if (--retries == 0) {
721 printk("GDT-EISA: Initialization error (get IRQ failed)\n");
722 return 0;
723 }
724 gdth_delay(1);
725 }
726 ha->irq = inb(eisa_adr+MAILBOXREG);
727 outb(0xff,eisa_adr+EDOORREG);
728 TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
729 /* check the result */
730 if (ha->irq == 0) {
731 TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
732 for (i = 0, irq_found = FALSE;
733 i < MAXHA && irq[i] != 0xff; ++i) {
734 if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
735 irq_found = TRUE;
736 break;
737 }
738 }
739 if (irq_found) {
740 ha->irq = irq[i];
741 irq[i] = 0;
742 printk("GDT-EISA: Can not detect controller IRQ,\n");
743 printk("Use IRQ setting from command line (IRQ = %d)\n",
744 ha->irq);
745 } else {
746 printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
747 printk("the controller BIOS or use command line parameters\n");
748 return 0;
749 }
750 }
751 } else {
752 eisacf = inb(eisa_adr+EISAREG) & 7;
753 if (eisacf > 4) /* level triggered */
754 eisacf -= 4;
755 ha->irq = gdth_irq_tab[eisacf];
756 ha->oem_id = OEM_ID_ICP;
757 ha->type = GDT_EISA;
758 ha->stype = id;
759 }
760
761 ha->dma64_support = 0;
762 return 1;
763}
706a5d45 764#endif /* CONFIG_EISA */
1da177e4 765
aed91cb5 766#ifdef CONFIG_ISA
1da177e4
LT		 767static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
768{
769 register gdt2_dpram_str __iomem *dp2_ptr;
770 int i;
771 unchar irq_drq,prot_ver;
772 ulong32 retries;
773
774 TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
775
776 ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
777 if (ha->brd == NULL) {
778 printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
779 return 0;
780 }
781 dp2_ptr = ha->brd;
a52667f3 782 writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
1da177e4
LT		 783 /* reset interface area */
784 memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
a52667f3 785 if (readl(&dp2_ptr->u) != 0) {
1da177e4
LT		 786 printk("GDT-ISA: Initialization error (DPMEM write error)\n");
787 iounmap(ha->brd);
788 return 0;
789 }
790
791 /* disable board interrupts, read DRQ and IRQ */
a52667f3
JG		 792 writeb(0xff, &dp2_ptr->io.irqdel);
793 writeb(0x00, &dp2_ptr->io.irqen);
794 writeb(0x00, &dp2_ptr->u.ic.S_Status);
795 writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
1da177e4 796
a52667f3 797 irq_drq = readb(&dp2_ptr->io.rq);
1da177e4
LT		 798 for (i=0; i<3; ++i) {
799 if ((irq_drq & 1)==0)
800 break;
801 irq_drq >>= 1;
802 }
803 ha->drq = gdth_drq_tab[i];
804
a52667f3 805 irq_drq = readb(&dp2_ptr->io.rq) >> 3;
1da177e4
LT		 806 for (i=1; i<5; ++i) {
807 if ((irq_drq & 1)==0)
808 break;
809 irq_drq >>= 1;
810 }
811 ha->irq = gdth_irq_tab[i];
812
813 /* deinitialize services */
a52667f3
JG		 814 writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
815 writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
816 writeb(0, &dp2_ptr->io.event);
1da177e4
LT		 817 retries = INIT_RETRIES;
818 gdth_delay(20);
a52667f3 819 while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
1da177e4
LT		 820 if (--retries == 0) {
821 printk("GDT-ISA: Initialization error (DEINIT failed)\n");
822 iounmap(ha->brd);
823 return 0;
824 }
825 gdth_delay(1);
826 }
a52667f3
JG		 827 prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
828 writeb(0, &dp2_ptr->u.ic.Status);
829 writeb(0xff, &dp2_ptr->io.irqdel);
1da177e4
LT		 830 if (prot_ver != PROTOCOL_VERSION) {
831 printk("GDT-ISA: Illegal protocol version\n");
832 iounmap(ha->brd);
833 return 0;
834 }
835
836 ha->oem_id = OEM_ID_ICP;
837 ha->type = GDT_ISA;
838 ha->ic_all_size = sizeof(dp2_ptr->u);
839 ha->stype= GDT2_ID;
840 ha->brd_phys = bios_adr >> 4;
841
842 /* special request to controller BIOS */
a52667f3
JG		 843 writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
844 writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
845 writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
846 writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
847 writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
848 writeb(0, &dp2_ptr->io.event);
1da177e4
LT		 849 retries = INIT_RETRIES;
850 gdth_delay(20);
a52667f3 851 while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
1da177e4
LT		 852 if (--retries == 0) {
853 printk("GDT-ISA: Initialization error\n");
854 iounmap(ha->brd);
855 return 0;
856 }
857 gdth_delay(1);
858 }
a52667f3
JG		 859 writeb(0, &dp2_ptr->u.ic.Status);
860 writeb(0xff, &dp2_ptr->io.irqdel);
1da177e4
LT		 861
862 ha->dma64_support = 0;
863 return 1;
864}
aed91cb5 865#endif /* CONFIG_ISA */
1da177e4 866
8514ef27 867#ifdef CONFIG_PCI
1da177e4
LT		 868static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
869{
870 register gdt6_dpram_str __iomem *dp6_ptr;
871 register gdt6c_dpram_str __iomem *dp6c_ptr;
872 register gdt6m_dpram_str __iomem *dp6m_ptr;
873 ulong32 retries;
874 unchar prot_ver;
875 ushort command;
876 int i, found = FALSE;
877
878 TRACE(("gdth_init_pci()\n"));
879
8e9a8a0d 880 if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
1da177e4
LT		 881 ha->oem_id = OEM_ID_INTEL;
882 else
883 ha->oem_id = OEM_ID_ICP;
8e9a8a0d
JG		 884 ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
885 ha->stype = (ulong32)pcistr->pdev->device;
1da177e4
LT		 886 ha->irq = pcistr->irq;
887 ha->pdev = pcistr->pdev;
888
8e9a8a0d 889 if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
1da177e4
LT		 890 TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
891 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
892 if (ha->brd == NULL) {
893 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
894 return 0;
895 }
896 /* check and reset interface area */
897 dp6_ptr = ha->brd;
a52667f3
JG		 898 writel(DPMEM_MAGIC, &dp6_ptr->u);
899 if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
1da177e4
LT		 900 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
901 pcistr->dpmem);
902 found = FALSE;
903 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
904 iounmap(ha->brd);
905 ha->brd = ioremap(i, sizeof(ushort));
906 if (ha->brd == NULL) {
907 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
908 return 0;
909 }
a52667f3 910 if (readw(ha->brd) != 0xffff) {
1da177e4
LT		 911 TRACE2(("init_pci_old() address 0x%x busy\n", i));
912 continue;
913 }
914 iounmap(ha->brd);
915 pci_write_config_dword(pcistr->pdev,
916 PCI_BASE_ADDRESS_0, i);
917 ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
918 if (ha->brd == NULL) {
919 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
920 return 0;
921 }
922 dp6_ptr = ha->brd;
a52667f3
JG		 923 writel(DPMEM_MAGIC, &dp6_ptr->u);
924 if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
1da177e4
LT		 925 printk("GDT-PCI: Use free address at 0x%x\n", i);
926 found = TRUE;
927 break;
928 }
929 }
930 if (!found) {
931 printk("GDT-PCI: No free address found!\n");
932 iounmap(ha->brd);
933 return 0;
934 }
935 }
936 memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
a52667f3 937 if (readl(&dp6_ptr->u) != 0) {
1da177e4
LT		 938 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
939 iounmap(ha->brd);
940 return 0;
941 }
942
943 /* disable board interrupts, deinit services */
a52667f3
JG		 944 writeb(0xff, &dp6_ptr->io.irqdel);
945 writeb(0x00, &dp6_ptr->io.irqen);
946 writeb(0x00, &dp6_ptr->u.ic.S_Status);
947 writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
948
949 writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
950 writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
951 writeb(0, &dp6_ptr->io.event);
1da177e4
LT		 952 retries = INIT_RETRIES;
953 gdth_delay(20);
a52667f3 954 while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
1da177e4
LT		 955 if (--retries == 0) {
956 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
957 iounmap(ha->brd);
958 return 0;
959 }
960 gdth_delay(1);
961 }
a52667f3
JG		 962 prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
963 writeb(0, &dp6_ptr->u.ic.S_Status);
964 writeb(0xff, &dp6_ptr->io.irqdel);
1da177e4
LT		 965 if (prot_ver != PROTOCOL_VERSION) {
966 printk("GDT-PCI: Illegal protocol version\n");
967 iounmap(ha->brd);
968 return 0;
969 }
970
971 ha->type = GDT_PCI;
972 ha->ic_all_size = sizeof(dp6_ptr->u);
973
974 /* special command to controller BIOS */
a52667f3
JG		 975 writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
976 writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
977 writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
978 writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
979 writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
980 writeb(0, &dp6_ptr->io.event);
1da177e4
LT		 981 retries = INIT_RETRIES;
982 gdth_delay(20);
a52667f3 983 while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
1da177e4
LT		 984 if (--retries == 0) {
985 printk("GDT-PCI: Initialization error\n");
986 iounmap(ha->brd);
987 return 0;
988 }
989 gdth_delay(1);
990 }
a52667f3
JG		 991 writeb(0, &dp6_ptr->u.ic.S_Status);
992 writeb(0xff, &dp6_ptr->io.irqdel);
1da177e4
LT		 993
994 ha->dma64_support = 0;
995
8e9a8a0d 996 } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
1da177e4
LT		 997 ha->plx = (gdt6c_plx_regs *)pcistr->io;
998 TRACE2(("init_pci_new() dpmem %lx irq %d\n",
999 pcistr->dpmem,ha->irq));
1000 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
1001 if (ha->brd == NULL) {
1002 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1003 iounmap(ha->brd);
1004 return 0;
1005 }
1006 /* check and reset interface area */
1007 dp6c_ptr = ha->brd;
a52667f3
JG		 1008 writel(DPMEM_MAGIC, &dp6c_ptr->u);
1009 if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
1da177e4
LT		 1010 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1011 pcistr->dpmem);
1012 found = FALSE;
1013 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1014 iounmap(ha->brd);
1015 ha->brd = ioremap(i, sizeof(ushort));
1016 if (ha->brd == NULL) {
1017 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1018 return 0;
1019 }
a52667f3 1020 if (readw(ha->brd) != 0xffff) {
1da177e4
LT		 1021 TRACE2(("init_pci_plx() address 0x%x busy\n", i));
1022 continue;
1023 }
1024 iounmap(ha->brd);
1025 pci_write_config_dword(pcistr->pdev,
1026 PCI_BASE_ADDRESS_2, i);
1027 ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
1028 if (ha->brd == NULL) {
1029 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1030 return 0;
1031 }
1032 dp6c_ptr = ha->brd;
a52667f3
JG		 1033 writel(DPMEM_MAGIC, &dp6c_ptr->u);
1034 if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
1da177e4
LT		 1035 printk("GDT-PCI: Use free address at 0x%x\n", i);
1036 found = TRUE;
1037 break;
1038 }
1039 }
1040 if (!found) {
1041 printk("GDT-PCI: No free address found!\n");
1042 iounmap(ha->brd);
1043 return 0;
1044 }
1045 }
1046 memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
a52667f3 1047 if (readl(&dp6c_ptr->u) != 0) {
1da177e4
LT		 1048 printk("GDT-PCI: Initialization error (DPMEM write error)\n");
1049 iounmap(ha->brd);
1050 return 0;
1051 }
1052
1053 /* disable board interrupts, deinit services */
1054 outb(0x00,PTR2USHORT(&ha->plx->control1));
1055 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
1056
a52667f3
JG		 1057 writeb(0x00, &dp6c_ptr->u.ic.S_Status);
1058 writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
1da177e4 1059
a52667f3
JG		 1060 writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
1061 writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
1da177e4
LT		 1062
1063 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1064
1065 retries = INIT_RETRIES;
1066 gdth_delay(20);
a52667f3 1067 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
1da177e4
LT		 1068 if (--retries == 0) {
1069 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1070 iounmap(ha->brd);
1071 return 0;
1072 }
1073 gdth_delay(1);
1074 }
a52667f3
JG		 1075 prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
1076 writeb(0, &dp6c_ptr->u.ic.Status);
1da177e4
LT		 1077 if (prot_ver != PROTOCOL_VERSION) {
1078 printk("GDT-PCI: Illegal protocol version\n");
1079 iounmap(ha->brd);
1080 return 0;
1081 }
1082
1083 ha->type = GDT_PCINEW;
1084 ha->ic_all_size = sizeof(dp6c_ptr->u);
1085
1086 /* special command to controller BIOS */
a52667f3
JG		 1087 writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
1088 writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
1089 writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
1090 writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
1091 writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
1da177e4
LT		 1092
1093 outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
1094
1095 retries = INIT_RETRIES;
1096 gdth_delay(20);
a52667f3 1097 while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
1da177e4
LT		 1098 if (--retries == 0) {
1099 printk("GDT-PCI: Initialization error\n");
1100 iounmap(ha->brd);
1101 return 0;
1102 }
1103 gdth_delay(1);
1104 }
a52667f3 1105 writeb(0, &dp6c_ptr->u.ic.S_Status);
1da177e4
LT		 1106
1107 ha->dma64_support = 0;
1108
1109 } else { /* MPR */
1110 TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
1111 ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
1112 if (ha->brd == NULL) {
1113 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1114 return 0;
1115 }
1116
1117 /* manipulate config. space to enable DPMEM, start RP controller */
1118 pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
1119 command |= 6;
1120 pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
1121 if (pci_resource_start(pcistr->pdev, 8) == 1UL)
1122 pci_resource_start(pcistr->pdev, 8) = 0UL;
1123 i = 0xFEFF0001UL;
1124 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
1125 gdth_delay(1);
1126 pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
1127 pci_resource_start(pcistr->pdev, 8));
1128
1129 dp6m_ptr = ha->brd;
1130
1131 /* Ensure that it is safe to access the non HW portions of DPMEM.
1132 * Aditional check needed for Xscale based RAID controllers */
a52667f3 1133 while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
1da177e4
LT		 1134 gdth_delay(1);
1135
1136 /* check and reset interface area */
a52667f3
JG		 1137 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1138 if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
1da177e4
LT		 1139 printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
1140 pcistr->dpmem);
1141 found = FALSE;
1142 for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
1143 iounmap(ha->brd);
1144 ha->brd = ioremap(i, sizeof(ushort));
1145 if (ha->brd == NULL) {
1146 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1147 return 0;
1148 }
a52667f3 1149 if (readw(ha->brd) != 0xffff) {
1da177e4
LT		 1150 TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
1151 continue;
1152 }
1153 iounmap(ha->brd);
1154 pci_write_config_dword(pcistr->pdev,
1155 PCI_BASE_ADDRESS_0, i);
1156 ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
1157 if (ha->brd == NULL) {
1158 printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
1159 return 0;
1160 }
1161 dp6m_ptr = ha->brd;
a52667f3
JG		 1162 writel(DPMEM_MAGIC, &dp6m_ptr->u);
1163 if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
1da177e4
LT		 1164 printk("GDT-PCI: Use free address at 0x%x\n", i);
1165 found = TRUE;
1166 break;
1167 }
1168 }
1169 if (!found) {
1170 printk("GDT-PCI: No free address found!\n");
1171 iounmap(ha->brd);
1172 return 0;
1173 }
1174 }
1175 memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
1176
1177 /* disable board interrupts, deinit services */
a52667f3 1178 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
1da177e4 1179 &dp6m_ptr->i960r.edoor_en_reg);
a52667f3
JG		 1180 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1181 writeb(0x00, &dp6m_ptr->u.ic.S_Status);
1182 writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
1da177e4 1183
a52667f3
JG		 1184 writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
1185 writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
1186 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1da177e4
LT		 1187 retries = INIT_RETRIES;
1188 gdth_delay(20);
a52667f3 1189 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
1da177e4
LT		 1190 if (--retries == 0) {
1191 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1192 iounmap(ha->brd);
1193 return 0;
1194 }
1195 gdth_delay(1);
1196 }
a52667f3
JG		 1197 prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
1198 writeb(0, &dp6m_ptr->u.ic.S_Status);
1da177e4
LT		 1199 if (prot_ver != PROTOCOL_VERSION) {
1200 printk("GDT-PCI: Illegal protocol version\n");
1201 iounmap(ha->brd);
1202 return 0;
1203 }
1204
1205 ha->type = GDT_PCIMPR;
1206 ha->ic_all_size = sizeof(dp6m_ptr->u);
1207
1208 /* special command to controller BIOS */
a52667f3
JG		 1209 writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
1210 writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
1211 writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
1212 writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
1213 writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
1214 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1da177e4
LT		 1215 retries = INIT_RETRIES;
1216 gdth_delay(20);
a52667f3 1217 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
1da177e4
LT		 1218 if (--retries == 0) {
1219 printk("GDT-PCI: Initialization error\n");
1220 iounmap(ha->brd);
1221 return 0;
1222 }
1223 gdth_delay(1);
1224 }
a52667f3 1225 writeb(0, &dp6m_ptr->u.ic.S_Status);
1da177e4
LT		 1226
1227 /* read FW version to detect 64-bit DMA support */
a52667f3
JG		 1228 writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
1229 writeb(1, &dp6m_ptr->i960r.ldoor_reg);
1da177e4
LT		 1230 retries = INIT_RETRIES;
1231 gdth_delay(20);
a52667f3 1232 while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
1da177e4
LT		 1233 if (--retries == 0) {
1234 printk("GDT-PCI: Initialization error (DEINIT failed)\n");
1235 iounmap(ha->brd);
1236 return 0;
1237 }
1238 gdth_delay(1);
1239 }
a52667f3
JG		 1240 prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
1241 writeb(0, &dp6m_ptr->u.ic.S_Status);
1da177e4
LT		 1242 if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
1243 ha->dma64_support = 0;
1244 else
1245 ha->dma64_support = 1;
1246 }
1247
1248 return 1;
1249}
8514ef27 1250#endif /* CONFIG_PCI */
1da177e4
LT		 1251
1252/* controller protocol functions */
1253
45f1a41b 1254static void __init gdth_enable_int(gdth_ha_str *ha)
1da177e4 1255{
1da177e4
LT		 1256 ulong flags;
1257 gdt2_dpram_str __iomem *dp2_ptr;
1258 gdt6_dpram_str __iomem *dp6_ptr;
1259 gdt6m_dpram_str __iomem *dp6m_ptr;
1260
45f1a41b 1261 TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
1da177e4
LT		 1262 spin_lock_irqsave(&ha->smp_lock, flags);
1263
1264 if (ha->type == GDT_EISA) {
1265 outb(0xff, ha->bmic + EDOORREG);
1266 outb(0xff, ha->bmic + EDENABREG);
1267 outb(0x01, ha->bmic + EINTENABREG);
1268 } else if (ha->type == GDT_ISA) {
1269 dp2_ptr = ha->brd;
a52667f3
JG		 1270 writeb(1, &dp2_ptr->io.irqdel);
1271 writeb(0, &dp2_ptr->u.ic.Cmd_Index);
1272 writeb(1, &dp2_ptr->io.irqen);
1da177e4
LT		 1273 } else if (ha->type == GDT_PCI) {
1274 dp6_ptr = ha->brd;
a52667f3
JG		 1275 writeb(1, &dp6_ptr->io.irqdel);
1276 writeb(0, &dp6_ptr->u.ic.Cmd_Index);
1277 writeb(1, &dp6_ptr->io.irqen);
1da177e4
LT		 1278 } else if (ha->type == GDT_PCINEW) {
1279 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
1280 outb(0x03, PTR2USHORT(&ha->plx->control1));
1281 } else if (ha->type == GDT_PCIMPR) {
1282 dp6m_ptr = ha->brd;
a52667f3
JG		 1283 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
1284 writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
1da177e4
LT		 1285 &dp6m_ptr->i960r.edoor_en_reg);
1286 }
1287 spin_unlock_irqrestore(&ha->smp_lock, flags);
1288}
1289
10e1b4bc
BH		 1290/* return IStatus if interrupt was from this card else 0 */
1291static unchar gdth_get_status(gdth_ha_str *ha, int irq)
1da177e4 1292{
10e1b4bc
BH		 1293 unchar IStatus = 0;
1294
1295 TRACE(("gdth_get_status() irq %d ctr_count %d\n", irq, gdth_ctr_count));
1da177e4 1296
1da177e4 1297 if (ha->irq != (unchar)irq) /* check IRQ */
10e1b4bc 1298 return false;
1da177e4 1299 if (ha->type == GDT_EISA)
10e1b4bc 1300 IStatus = inb((ushort)ha->bmic + EDOORREG);
1da177e4 1301 else if (ha->type == GDT_ISA)
10e1b4bc 1302 IStatus =
a52667f3 1303 readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1da177e4 1304 else if (ha->type == GDT_PCI)
10e1b4bc 1305 IStatus =
a52667f3 1306 readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
1da177e4 1307 else if (ha->type == GDT_PCINEW)
10e1b4bc 1308 IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
1da177e4 1309 else if (ha->type == GDT_PCIMPR)
10e1b4bc 1310 IStatus =
a52667f3 1311 readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
10e1b4bc
BH		 1312
1313 return IStatus;
1da177e4 1314}
10e1b4bc 1315
45f1a41b 1316static int gdth_test_busy(gdth_ha_str *ha)
1da177e4 1317{
1da177e4
LT		 1318 register int gdtsema0 = 0;
1319
45f1a41b
BH		 1320 TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
1321
1da177e4
LT		 1322 if (ha->type == GDT_EISA)
1323 gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
1324 else if (ha->type == GDT_ISA)
a52667f3 1325 gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1da177e4 1326 else if (ha->type == GDT_PCI)
a52667f3 1327 gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1da177e4
LT		 1328 else if (ha->type == GDT_PCINEW)
1329 gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
1330 else if (ha->type == GDT_PCIMPR)
1331 gdtsema0 =
a52667f3 1332 (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1da177e4
LT		 1333
1334 return (gdtsema0 & 1);
1335}
1336
1337
45f1a41b 1338static int gdth_get_cmd_index(gdth_ha_str *ha)
1da177e4 1339{
1da177e4
LT		 1340 int i;
1341
45f1a41b 1342 TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
1da177e4 1343
1da177e4
LT		 1344 for (i=0; i<GDTH_MAXCMDS; ++i) {
1345 if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
1346 ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
1347 ha->cmd_tab[i].service = ha->pccb->Service;
1348 ha->pccb->CommandIndex = (ulong32)i+2;
1349 return (i+2);
1350 }
1351 }
1352 return 0;
1353}
1354
1355
45f1a41b 1356static void gdth_set_sema0(gdth_ha_str *ha)
1da177e4 1357{
45f1a41b 1358 TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
1da177e4 1359
1da177e4
LT		 1360 if (ha->type == GDT_EISA) {
1361 outb(1, ha->bmic + SEMA0REG);
1362 } else if (ha->type == GDT_ISA) {
a52667f3 1363 writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1da177e4 1364 } else if (ha->type == GDT_PCI) {
a52667f3 1365 writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
1da177e4
LT		 1366 } else if (ha->type == GDT_PCINEW) {
1367 outb(1, PTR2USHORT(&ha->plx->sema0_reg));
1368 } else if (ha->type == GDT_PCIMPR) {
a52667f3 1369 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
1da177e4
LT		 1370 }
1371}
1372
1373
45f1a41b 1374static void gdth_copy_command(gdth_ha_str *ha)
1da177e4 1375{
1da177e4
LT		 1376 register gdth_cmd_str *cmd_ptr;
1377 register gdt6m_dpram_str __iomem *dp6m_ptr;
1378 register gdt6c_dpram_str __iomem *dp6c_ptr;
1379 gdt6_dpram_str __iomem *dp6_ptr;
1380 gdt2_dpram_str __iomem *dp2_ptr;
1381 ushort cp_count,dp_offset,cmd_no;
1382
45f1a41b 1383 TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
1da177e4 1384
1da177e4
LT		 1385 cp_count = ha->cmd_len;
1386 dp_offset= ha->cmd_offs_dpmem;
1387 cmd_no = ha->cmd_cnt;
1388 cmd_ptr = ha->pccb;
1389
1390 ++ha->cmd_cnt;
1391 if (ha->type == GDT_EISA)
1392 return; /* no DPMEM, no copy */
1393
1394 /* set cpcount dword aligned */
1395 if (cp_count & 3)
1396 cp_count += (4 - (cp_count & 3));
1397
1398 ha->cmd_offs_dpmem += cp_count;
1399
1400 /* set offset and service, copy command to DPMEM */
1401 if (ha->type == GDT_ISA) {
1402 dp2_ptr = ha->brd;
a52667f3 1403 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1da177e4 1404 &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
a52667f3 1405 writew((ushort)cmd_ptr->Service,
1da177e4
LT		 1406 &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
1407 memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1408 } else if (ha->type == GDT_PCI) {
1409 dp6_ptr = ha->brd;
a52667f3 1410 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1da177e4 1411 &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
a52667f3 1412 writew((ushort)cmd_ptr->Service,
1da177e4
LT		 1413 &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
1414 memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1415 } else if (ha->type == GDT_PCINEW) {
1416 dp6c_ptr = ha->brd;
a52667f3 1417 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1da177e4 1418 &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
a52667f3 1419 writew((ushort)cmd_ptr->Service,
1da177e4
LT		 1420 &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
1421 memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1422 } else if (ha->type == GDT_PCIMPR) {
1423 dp6m_ptr = ha->brd;
a52667f3 1424 writew(dp_offset + DPMEM_COMMAND_OFFSET,
1da177e4 1425 &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
a52667f3 1426 writew((ushort)cmd_ptr->Service,
1da177e4
LT		 1427 &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
1428 memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
1429 }
1430}
1431
1432
45f1a41b 1433static void gdth_release_event(gdth_ha_str *ha)
1da177e4 1434{
45f1a41b 1435 TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
1da177e4
LT		 1436
1437#ifdef GDTH_STATISTICS
1438 {
1439 ulong32 i,j;
1440 for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
1441 if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
1442 ++i;
1443 }
1444 if (max_index < i) {
1445 max_index = i;
1446 TRACE3(("GDT: max_index = %d\n",(ushort)i));
1447 }
1448 }
1449#endif
1450
1451 if (ha->pccb->OpCode == GDT_INIT)
1452 ha->pccb->Service |= 0x80;
1453
1454 if (ha->type == GDT_EISA) {
1455 if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
1456 outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
1457 outb(ha->pccb->Service, ha->bmic + LDOORREG);
1458 } else if (ha->type == GDT_ISA) {
a52667f3 1459 writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
1da177e4 1460 } else if (ha->type == GDT_PCI) {
a52667f3 1461 writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
1da177e4
LT		 1462 } else if (ha->type == GDT_PCINEW) {
1463 outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
1464 } else if (ha->type == GDT_PCIMPR) {
a52667f3 1465 writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
1da177e4
LT		 1466 }
1467}
1468
45f1a41b 1469static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
1da177e4 1470{
1da177e4 1471 int answer_found = FALSE;
10e1b4bc 1472 int wait_index = 0;
1da177e4 1473
45f1a41b 1474 TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
1da177e4 1475
1da177e4
LT		 1476 if (index == 0)
1477 return 1; /* no wait required */
1478
1da177e4 1479 do {
10e1b4bc
BH		 1480 __gdth_interrupt(ha, (int)ha->irq, true, &wait_index);
1481 if (wait_index == index) {
1da177e4
LT		 1482 answer_found = TRUE;
1483 break;
1484 }
1485 gdth_delay(1);
1486 } while (--time);
45f1a41b
BH		 1487
1488 while (gdth_test_busy(ha))
1da177e4
LT		 1489 gdth_delay(0);
1490
1491 return (answer_found);
1492}
1493
1494
45f1a41b
BH		 1495static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
1496 ulong32 p1, ulong64 p2, ulong64 p3)
1da177e4 1497{
1da177e4
LT		 1498 register gdth_cmd_str *cmd_ptr;
1499 int retries,index;
1500
1501 TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
1502
1da177e4
LT		 1503 cmd_ptr = ha->pccb;
1504 memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
1505
1506 /* make command */
1507 for (retries = INIT_RETRIES;;) {
1508 cmd_ptr->Service = service;
1509 cmd_ptr->RequestBuffer = INTERNAL_CMND;
45f1a41b 1510 if (!(index=gdth_get_cmd_index(ha))) {
1da177e4
LT		 1511 TRACE(("GDT: No free command index found\n"));
1512 return 0;
1513 }
45f1a41b 1514 gdth_set_sema0(ha);
1da177e4
LT		 1515 cmd_ptr->OpCode = opcode;
1516 cmd_ptr->BoardNode = LOCALBOARD;
1517 if (service == CACHESERVICE) {
1518 if (opcode == GDT_IOCTL) {
1519 cmd_ptr->u.ioctl.subfunc = p1;
1520 cmd_ptr->u.ioctl.channel = (ulong32)p2;
1521 cmd_ptr->u.ioctl.param_size = (ushort)p3;
1522 cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
1523 } else {
1524 if (ha->cache_feat & GDT_64BIT) {
1525 cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
1526 cmd_ptr->u.cache64.BlockNo = p2;
1527 } else {
1528 cmd_ptr->u.cache.DeviceNo = (ushort)p1;
1529 cmd_ptr->u.cache.BlockNo = (ulong32)p2;
1530 }
1531 }
1532 } else if (service == SCSIRAWSERVICE) {
1533 if (ha->raw_feat & GDT_64BIT) {
1534 cmd_ptr->u.raw64.direction = p1;
1535 cmd_ptr->u.raw64.bus = (unchar)p2;
1536 cmd_ptr->u.raw64.target = (unchar)p3;
1537 cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
1538 } else {
1539 cmd_ptr->u.raw.direction = p1;
1540 cmd_ptr->u.raw.bus = (unchar)p2;
1541 cmd_ptr->u.raw.target = (unchar)p3;
1542 cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
1543 }
1544 } else if (service == SCREENSERVICE) {
1545 if (opcode == GDT_REALTIME) {
1546 *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
1547 *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
1548 *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
1549 }
1550 }
1551 ha->cmd_len = sizeof(gdth_cmd_str);
1552 ha->cmd_offs_dpmem = 0;
1553 ha->cmd_cnt = 0;
45f1a41b
BH		 1554 gdth_copy_command(ha);
1555 gdth_release_event(ha);
1da177e4 1556 gdth_delay(20);
45f1a41b 1557 if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
1da177e4
LT		 1558 printk("GDT: Initialization error (timeout service %d)\n",service);
1559 return 0;
1560 }
1561 if (ha->status != S_BSY || --retries == 0)
1562 break;
1563 gdth_delay(1);
1564 }
1565
1566 return (ha->status != S_OK ? 0:1);
1567}
1568
1569
1570/* search for devices */
1571
45f1a41b 1572static int __init gdth_search_drives(gdth_ha_str *ha)
1da177e4 1573{
1da177e4
LT		 1574 ushort cdev_cnt, i;
1575 int ok;
1576 ulong32 bus_no, drv_cnt, drv_no, j;
1577 gdth_getch_str *chn;
1578 gdth_drlist_str *drl;
1579 gdth_iochan_str *ioc;
1580 gdth_raw_iochan_str *iocr;
1581 gdth_arcdl_str *alst;
1582 gdth_alist_str *alst2;
1583 gdth_oem_str_ioctl *oemstr;
1584#ifdef INT_COAL
1585 gdth_perf_modes *pmod;
1586#endif
1587
1588#ifdef GDTH_RTC
1589 unchar rtc[12];
1590 ulong flags;
1591#endif
1592
45f1a41b 1593 TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
1da177e4
LT		 1594 ok = 0;
1595
1596 /* initialize controller services, at first: screen service */
1597 ha->screen_feat = 0;
1598 if (!force_dma32) {
45f1a41b 1599 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
1da177e4
LT		 1600 if (ok)
1601 ha->screen_feat = GDT_64BIT;
1602 }
1603 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
45f1a41b 1604 ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
1da177e4
LT		 1605 if (!ok) {
1606 printk("GDT-HA %d: Initialization error screen service (code %d)\n",
45f1a41b 1607 ha->hanum, ha->status);
1da177e4
LT		 1608 return 0;
1609 }
1610 TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
1611
1612#ifdef GDTH_RTC
1613 /* read realtime clock info, send to controller */
1614 /* 1. wait for the falling edge of update flag */
1615 spin_lock_irqsave(&rtc_lock, flags);
1616 for (j = 0; j < 1000000; ++j)
1617 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
1618 break;
1619 for (j = 0; j < 1000000; ++j)
1620 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
1621 break;
1622 /* 2. read info */
1623 do {
1624 for (j = 0; j < 12; ++j)
1625 rtc[j] = CMOS_READ(j);
1626 } while (rtc[0] != CMOS_READ(0));
7a960b76 1627 spin_unlock_irqrestore(&rtc_lock, flags);
1da177e4
LT		 1628 TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
1629 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
1630 /* 3. send to controller firmware */
45f1a41b 1631 gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
1da177e4
LT		 1632 *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
1633#endif
1634
1635 /* unfreeze all IOs */
45f1a41b 1636 gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
1da177e4
LT		 1637
1638 /* initialize cache service */
1639 ha->cache_feat = 0;
1640 if (!force_dma32) {
45f1a41b
BH		 1641 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
1642 0, 0);
1da177e4
LT		 1643 if (ok)
1644 ha->cache_feat = GDT_64BIT;
1645 }
1646 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
45f1a41b 1647 ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
1da177e4
LT		 1648 if (!ok) {
1649 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
45f1a41b 1650 ha->hanum, ha->status);
1da177e4
LT		 1651 return 0;
1652 }
1653 TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
1654 cdev_cnt = (ushort)ha->info;
1655 ha->fw_vers = ha->service;
1656
1657#ifdef INT_COAL
1658 if (ha->type == GDT_PCIMPR) {
1659 /* set perf. modes */
1660 pmod = (gdth_perf_modes *)ha->pscratch;
1661 pmod->version = 1;
1662 pmod->st_mode = 1; /* enable one status buffer */
1663 *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
1664 pmod->st_buff_indx1 = COALINDEX;
1665 pmod->st_buff_addr2 = 0;
1666 pmod->st_buff_u_addr2 = 0;
1667 pmod->st_buff_indx2 = 0;
1668 pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
1669 pmod->cmd_mode = 0; // disable all cmd buffers
1670 pmod->cmd_buff_addr1 = 0;
1671 pmod->cmd_buff_u_addr1 = 0;
1672 pmod->cmd_buff_indx1 = 0;
1673 pmod->cmd_buff_addr2 = 0;
1674 pmod->cmd_buff_u_addr2 = 0;
1675 pmod->cmd_buff_indx2 = 0;
1676 pmod->cmd_buff_size = 0;
1677 pmod->reserved1 = 0;
1678 pmod->reserved2 = 0;
45f1a41b 1679 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
1da177e4 1680 INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
45f1a41b 1681 printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
1da177e4
LT		 1682 }
1683 }
1684#endif
1685
1686 /* detect number of buses - try new IOCTL */
1687 iocr = (gdth_raw_iochan_str *)ha->pscratch;
1688 iocr->hdr.version = 0xffffffff;
1689 iocr->hdr.list_entries = MAXBUS;
1690 iocr->hdr.first_chan = 0;
1691 iocr->hdr.last_chan = MAXBUS-1;
1692 iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
45f1a41b 1693 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
1da177e4
LT		 1694 INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
1695 TRACE2(("IOCHAN_RAW_DESC supported!\n"));
1696 ha->bus_cnt = iocr->hdr.chan_count;
1697 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1698 if (iocr->list[bus_no].proc_id < MAXID)
1699 ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
1700 else
1701 ha->bus_id[bus_no] = 0xff;
1702 }
1703 } else {
1704 /* old method */
1705 chn = (gdth_getch_str *)ha->pscratch;
1706 for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
1707 chn->channel_no = bus_no;
45f1a41b 1708 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1da177e4
LT		 1709 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1710 IO_CHANNEL | INVALID_CHANNEL,
1711 sizeof(gdth_getch_str))) {
1712 if (bus_no == 0) {
1713 printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
45f1a41b 1714 ha->hanum, ha->status);
1da177e4
LT		 1715 return 0;
1716 }
1717 break;
1718 }
1719 if (chn->siop_id < MAXID)
1720 ha->bus_id[bus_no] = chn->siop_id;
1721 else
1722 ha->bus_id[bus_no] = 0xff;
1723 }
1724 ha->bus_cnt = (unchar)bus_no;
1725 }
1726 TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
1727
1728 /* read cache configuration */
45f1a41b 1729 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
1da177e4
LT		 1730 INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
1731 printk("GDT-HA %d: Initialization error cache service (code %d)\n",
45f1a41b 1732 ha->hanum, ha->status);
1da177e4
LT		 1733 return 0;
1734 }
1735 ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
1736 TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
1737 ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
1738 ha->cpar.write_back,ha->cpar.block_size));
1739
1740 /* read board info and features */
1741 ha->more_proc = FALSE;
45f1a41b 1742 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
1da177e4
LT		 1743 INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
1744 memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
1745 sizeof(gdth_binfo_str));
45f1a41b 1746 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
1da177e4
LT		 1747 INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
1748 TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
1749 ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
1750 ha->more_proc = TRUE;
1751 }
1752 } else {
1753 TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
45f1a41b 1754 strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
1da177e4
LT		 1755 }
1756 TRACE2(("Controller name: %s\n",ha->binfo.type_string));
1757
1758 /* read more informations */
1759 if (ha->more_proc) {
1760 /* physical drives, channel addresses */
1761 ioc = (gdth_iochan_str *)ha->pscratch;
1762 ioc->hdr.version = 0xffffffff;
1763 ioc->hdr.list_entries = MAXBUS;
1764 ioc->hdr.first_chan = 0;
1765 ioc->hdr.last_chan = MAXBUS-1;
1766 ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
45f1a41b 1767 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
1da177e4
LT		 1768 INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
1769 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1770 ha->raw[bus_no].address = ioc->list[bus_no].address;
1771 ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
1772 }
1773 } else {
1774 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1775 ha->raw[bus_no].address = IO_CHANNEL;
1776 ha->raw[bus_no].local_no = bus_no;
1777 }
1778 }
1779 for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
1780 chn = (gdth_getch_str *)ha->pscratch;
1781 chn->channel_no = ha->raw[bus_no].local_no;
45f1a41b 1782 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1da177e4
LT		 1783 SCSI_CHAN_CNT | L_CTRL_PATTERN,
1784 ha->raw[bus_no].address | INVALID_CHANNEL,
1785 sizeof(gdth_getch_str))) {
1786 ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
1787 TRACE2(("Channel %d: %d phys. drives\n",
1788 bus_no,chn->drive_cnt));
1789 }
1790 if (ha->raw[bus_no].pdev_cnt > 0) {
1791 drl = (gdth_drlist_str *)ha->pscratch;
1792 drl->sc_no = ha->raw[bus_no].local_no;
1793 drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
45f1a41b 1794 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1da177e4
LT		 1795 SCSI_DR_LIST | L_CTRL_PATTERN,
1796 ha->raw[bus_no].address | INVALID_CHANNEL,
1797 sizeof(gdth_drlist_str))) {
1798 for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
1799 ha->raw[bus_no].id_list[j] = drl->sc_list[j];
1800 } else {
1801 ha->raw[bus_no].pdev_cnt = 0;
1802 }
1803 }
1804 }
1805
1806 /* logical drives */
45f1a41b 1807 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
1da177e4
LT		 1808 INVALID_CHANNEL,sizeof(ulong32))) {
1809 drv_cnt = *(ulong32 *)ha->pscratch;
45f1a41b 1810 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
1da177e4
LT		 1811 INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
1812 for (j = 0; j < drv_cnt; ++j) {
1813 drv_no = ((ulong32 *)ha->pscratch)[j];
1814 if (drv_no < MAX_LDRIVES) {
1815 ha->hdr[drv_no].is_logdrv = TRUE;
1816 TRACE2(("Drive %d is log. drive\n",drv_no));
1817 }
1818 }
1819 }
1820 alst = (gdth_arcdl_str *)ha->pscratch;
1821 alst->entries_avail = MAX_LDRIVES;
1822 alst->first_entry = 0;
1823 alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
45f1a41b 1824 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1da177e4
LT		 1825 ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
1826 INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
1827 (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
1828 for (j = 0; j < alst->entries_init; ++j) {
1829 ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
1830 ha->hdr[j].is_master = alst->list[j].is_master;
1831 ha->hdr[j].is_parity = alst->list[j].is_parity;
1832 ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
1833 ha->hdr[j].master_no = alst->list[j].cd_handle;
1834 }
45f1a41b 1835 } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1da177e4
LT		 1836 ARRAY_DRV_LIST | LA_CTRL_PATTERN,
1837 0, 35 * sizeof(gdth_alist_str))) {
1838 for (j = 0; j < 35; ++j) {
1839 alst2 = &((gdth_alist_str *)ha->pscratch)[j];
1840 ha->hdr[j].is_arraydrv = alst2->is_arrayd;
1841 ha->hdr[j].is_master = alst2->is_master;
1842 ha->hdr[j].is_parity = alst2->is_parity;
1843 ha->hdr[j].is_hotfix = alst2->is_hotfix;
1844 ha->hdr[j].master_no = alst2->cd_handle;
1845 }
1846 }
1847 }
1848 }
1849
1850 /* initialize raw service */
1851 ha->raw_feat = 0;
1852 if (!force_dma32) {
45f1a41b 1853 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
1da177e4
LT		 1854 if (ok)
1855 ha->raw_feat = GDT_64BIT;
1856 }
1857 if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
45f1a41b 1858 ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
1da177e4
LT		 1859 if (!ok) {
1860 printk("GDT-HA %d: Initialization error raw service (code %d)\n",
45f1a41b 1861 ha->hanum, ha->status);
1da177e4
LT		 1862 return 0;
1863 }
1864 TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
1865
1866 /* set/get features raw service (scatter/gather) */
45f1a41b
BH		 1867 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
1868 0, 0)) {
1da177e4 1869 TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
45f1a41b 1870 if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1da177e4
LT		 1871 TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
1872 ha->info));
1873 ha->raw_feat |= (ushort)ha->info;
1874 }
1875 }
1876
1877 /* set/get features cache service (equal to raw service) */
45f1a41b 1878 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
1da177e4
LT		 1879 SCATTER_GATHER,0)) {
1880 TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
45f1a41b 1881 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
1da177e4
LT		 1882 TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
1883 ha->info));
1884 ha->cache_feat |= (ushort)ha->info;
1885 }
1886 }
1887
1888 /* reserve drives for raw service */
1889 if (reserve_mode != 0) {
45f1a41b 1890 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
1da177e4
LT		 1891 reserve_mode == 1 ? 1 : 3, 0, 0);
1892 TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
1893 ha->status));
1894 }
1895 for (i = 0; i < MAX_RES_ARGS; i += 4) {
45f1a41b 1896 if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
1da177e4
LT		 1897 reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
1898 TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
1899 reserve_list[i], reserve_list[i+1],
1900 reserve_list[i+2], reserve_list[i+3]));
45f1a41b 1901 if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
1da177e4
LT		 1902 reserve_list[i+1], reserve_list[i+2] |
1903 (reserve_list[i+3] << 8))) {
1904 printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
45f1a41b 1905 ha->hanum, ha->status);
1da177e4
LT		 1906 }
1907 }
1908 }
1909
1910 /* Determine OEM string using IOCTL */
1911 oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
1912 oemstr->params.ctl_version = 0x01;
1913 oemstr->params.buffer_size = sizeof(oemstr->text);
45f1a41b 1914 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
1da177e4
LT		 1915 CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
1916 sizeof(gdth_oem_str_ioctl))) {
1917 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
1918 printk("GDT-HA %d: Vendor: %s Name: %s\n",
45f1a41b 1919 ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
1da177e4 1920 /* Save the Host Drive inquiry data */
1da177e4
LT		 1921 strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
1922 sizeof(ha->oem_name));
1da177e4
LT		 1923 } else {
1924 /* Old method, based on PCI ID */
1925 TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
1926 printk("GDT-HA %d: Name: %s\n",
45f1a41b 1927 ha->hanum, ha->binfo.type_string);
1da177e4
LT		 1928 if (ha->oem_id == OEM_ID_INTEL)
1929 strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
1930 else
1931 strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
1da177e4
LT		 1932 }
1933
1934 /* scanning for host drives */
1935 for (i = 0; i < cdev_cnt; ++i)
45f1a41b 1936 gdth_analyse_hdrive(ha, i);
1da177e4
LT		 1937
1938 TRACE(("gdth_search_drives() OK\n"));
1939 return 1;
1940}
1941
45f1a41b 1942static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
1da177e4 1943{
1da177e4
LT		 1944 ulong32 drv_cyls;
1945 int drv_hds, drv_secs;
1946
45f1a41b 1947 TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
1da177e4
LT		 1948 if (hdrive >= MAX_HDRIVES)
1949 return 0;
1da177e4 1950
45f1a41b 1951 if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
1da177e4
LT		 1952 return 0;
1953 ha->hdr[hdrive].present = TRUE;
1954 ha->hdr[hdrive].size = ha->info;
1955
1956 /* evaluate mapping (sectors per head, heads per cylinder) */
1957 ha->hdr[hdrive].size &= ~SECS32;
1958 if (ha->info2 == 0) {
1959 gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
1960 } else {
1961 drv_hds = ha->info2 & 0xff;
1962 drv_secs = (ha->info2 >> 8) & 0xff;
1963 drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
1964 }
1965 ha->hdr[hdrive].heads = (unchar)drv_hds;
1966 ha->hdr[hdrive].secs = (unchar)drv_secs;
1967 /* round size */
1968 ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
1969
1970 if (ha->cache_feat & GDT_64BIT) {
45f1a41b 1971 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
1da177e4
LT		 1972 && ha->info2 != 0) {
1973 ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
1974 }
1975 }
1976 TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
1977 hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
1978
1979 /* get informations about device */
45f1a41b 1980 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
1da177e4
LT		 1981 TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
1982 hdrive,ha->info));
1983 ha->hdr[hdrive].devtype = (ushort)ha->info;
1984 }
1985
1986 /* cluster info */
45f1a41b 1987 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
1da177e4
LT		 1988 TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
1989 hdrive,ha->info));
1990 if (!shared_access)
1991 ha->hdr[hdrive].cluster_type = (unchar)ha->info;
1992 }
1993
1994 /* R/W attributes */
45f1a41b 1995 if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
1da177e4
LT		 1996 TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
1997 hdrive,ha->info));
1998 ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
1999 }
2000
2001 return 1;
2002}
2003
2004
2005/* command queueing/sending functions */
2006
45f1a41b 2007static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
1da177e4 2008{
3058d5de 2009 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
1da177e4
LT		 2010 register Scsi_Cmnd *pscp;
2011 register Scsi_Cmnd *nscp;
2012 ulong flags;
2013 unchar b, t;
2014
2015 TRACE(("gdth_putq() priority %d\n",priority));
1da177e4
LT		 2016 spin_lock_irqsave(&ha->smp_lock, flags);
2017
3058d5de 2018 if (!cmndinfo->internal_command) {
cbd5f69b 2019 scp->SCp.this_residual = (int)priority;
52759e6a 2020 b = scp->device->channel;
cbd5f69b
LA		 2021 t = scp->device->id;
2022 if (priority >= DEFAULT_PRI) {
2023 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2024 (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
2025 TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
45f1a41b 2026 scp->SCp.buffers_residual = gdth_update_timeout(scp, 0);
cbd5f69b 2027 }
1da177e4
LT		 2028 }
2029 }
2030
2031 if (ha->req_first==NULL) {
2032 ha->req_first = scp; /* queue was empty */
2033 scp->SCp.ptr = NULL;
2034 } else { /* queue not empty */
2035 pscp = ha->req_first;
2036 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2037 /* priority: 0-highest,..,0xff-lowest */
2038 while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
2039 pscp = nscp;
2040 nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
2041 }
2042 pscp->SCp.ptr = (char *)scp;
2043 scp->SCp.ptr = (char *)nscp;
2044 }
2045 spin_unlock_irqrestore(&ha->smp_lock, flags);
2046
2047#ifdef GDTH_STATISTICS
2048 flags = 0;
2049 for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
2050 ++flags;
2051 if (max_rq < flags) {
2052 max_rq = flags;
2053 TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
2054 }
2055#endif
2056}
2057
45f1a41b 2058static void gdth_next(gdth_ha_str *ha)
1da177e4 2059{
1da177e4
LT		 2060 register Scsi_Cmnd *pscp;
2061 register Scsi_Cmnd *nscp;
2062 unchar b, t, l, firsttime;
2063 unchar this_cmd, next_cmd;
2064 ulong flags = 0;
2065 int cmd_index;
2066
45f1a41b 2067 TRACE(("gdth_next() hanum %d\n", ha->hanum));
1da177e4
LT		 2068 if (!gdth_polling)
2069 spin_lock_irqsave(&ha->smp_lock, flags);
2070
2071 ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
2072 this_cmd = firsttime = TRUE;
2073 next_cmd = gdth_polling ? FALSE:TRUE;
2074 cmd_index = 0;
2075
2076 for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
2077 if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
2078 pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
3058d5de 2079 if (!gdth_cmnd_priv(nscp)->internal_command) {
52759e6a 2080 b = nscp->device->channel;
cbd5f69b
LA		 2081 t = nscp->device->id;
2082 l = nscp->device->lun;
2083 if (nscp->SCp.this_residual >= DEFAULT_PRI) {
2084 if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
2085 (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
2086 continue;
2087 }
2088 } else
2089 b = t = l = 0;
1da177e4
LT		 2090
2091 if (firsttime) {
45f1a41b
BH		 2092 if (gdth_test_busy(ha)) { /* controller busy ? */
2093 TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
1da177e4
LT		 2094 if (!gdth_polling) {
2095 spin_unlock_irqrestore(&ha->smp_lock, flags);
2096 return;
2097 }
45f1a41b 2098 while (gdth_test_busy(ha))
1da177e4
LT		 2099 gdth_delay(1);
2100 }
2101 firsttime = FALSE;
2102 }
2103
3058d5de 2104 if (!gdth_cmnd_priv(nscp)->internal_command) {
1da177e4
LT		 2105 if (nscp->SCp.phase == -1) {
2106 nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
2107 if (nscp->cmnd[0] == TEST_UNIT_READY) {
2108 TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
2109 b, t, l));
2110 /* TEST_UNIT_READY -> set scan mode */
2111 if ((ha->scan_mode & 0x0f) == 0) {
2112 if (b == 0 && t == 0 && l == 0) {
2113 ha->scan_mode |= 1;
2114 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2115 }
2116 } else if ((ha->scan_mode & 0x0f) == 1) {
2117 if (b == 0 && ((t == 0 && l == 1) ||
2118 (t == 1 && l == 0))) {
2119 nscp->SCp.sent_command = GDT_SCAN_START;
2120 nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
2121 | SCSIRAWSERVICE;
2122 ha->scan_mode = 0x12;
2123 TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
2124 ha->scan_mode));
2125 } else {
2126 ha->scan_mode &= 0x10;
2127 TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
2128 }
2129 } else if (ha->scan_mode == 0x12) {
2130 if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
2131 nscp->SCp.phase = SCSIRAWSERVICE;
2132 nscp->SCp.sent_command = GDT_SCAN_END;
2133 ha->scan_mode &= 0x10;
2134 TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
2135 ha->scan_mode));
2136 }
2137 }
2138 }
2139 if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
2140 nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
2141 (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
2142 /* always GDT_CLUST_INFO! */
2143 nscp->SCp.sent_command = GDT_CLUST_INFO;
2144 }
2145 }
2146 }
2147
2148 if (nscp->SCp.sent_command != -1) {
2149 if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
45f1a41b 2150 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
1da177e4
LT		 2151 this_cmd = FALSE;
2152 next_cmd = FALSE;
2153 } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
45f1a41b 2154 if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
1da177e4
LT		 2155 this_cmd = FALSE;
2156 next_cmd = FALSE;
2157 } else {
2158 memset((char*)nscp->sense_buffer,0,16);
2159 nscp->sense_buffer[0] = 0x70;
2160 nscp->sense_buffer[2] = NOT_READY;
2161 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2162 if (!nscp->SCp.have_data_in)
2163 nscp->SCp.have_data_in++;
2164 else
b8bff2ae 2165 gdth_scsi_done(nscp);
1da177e4 2166 }
3058d5de 2167 } else if (gdth_cmnd_priv(nscp)->internal_command) {
45f1a41b 2168 if (!(cmd_index=gdth_special_cmd(ha, nscp)))
1da177e4
LT		 2169 this_cmd = FALSE;
2170 next_cmd = FALSE;
2171 } else if (b != ha->virt_bus) {
2172 if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
45f1a41b 2173 !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
1da177e4
LT		 2174 this_cmd = FALSE;
2175 else
2176 ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
2177 } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
2178 TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
2179 nscp->cmnd[0], b, t, l));
2180 nscp->result = DID_BAD_TARGET << 16;
2181 if (!nscp->SCp.have_data_in)
2182 nscp->SCp.have_data_in++;
2183 else
b8bff2ae 2184 gdth_scsi_done(nscp);
1da177e4
LT		 2185 } else {
2186 switch (nscp->cmnd[0]) {
2187 case TEST_UNIT_READY:
2188 case INQUIRY:
2189 case REQUEST_SENSE:
2190 case READ_CAPACITY:
2191 case VERIFY:
2192 case START_STOP:
2193 case MODE_SENSE:
2194 case SERVICE_ACTION_IN:
2195 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2196 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2197 nscp->cmnd[4],nscp->cmnd[5]));
2198 if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
2199 /* return UNIT_ATTENTION */
2200 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2201 nscp->cmnd[0], t));
2202 ha->hdr[t].media_changed = FALSE;
2203 memset((char*)nscp->sense_buffer,0,16);
2204 nscp->sense_buffer[0] = 0x70;
2205 nscp->sense_buffer[2] = UNIT_ATTENTION;
2206 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2207 if (!nscp->SCp.have_data_in)
2208 nscp->SCp.have_data_in++;
2209 else
b8bff2ae 2210 gdth_scsi_done(nscp);
45f1a41b 2211 } else if (gdth_internal_cache_cmd(ha, nscp))
b8bff2ae 2212 gdth_scsi_done(nscp);
1da177e4
LT		 2213 break;
2214
2215 case ALLOW_MEDIUM_REMOVAL:
2216 TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
2217 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2218 nscp->cmnd[4],nscp->cmnd[5]));
2219 if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
2220 TRACE(("Prevent r. nonremov. drive->do nothing\n"));
2221 nscp->result = DID_OK << 16;
2222 nscp->sense_buffer[0] = 0;
2223 if (!nscp->SCp.have_data_in)
2224 nscp->SCp.have_data_in++;
2225 else
b8bff2ae 2226 gdth_scsi_done(nscp);
1da177e4
LT		 2227 } else {
2228 nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
2229 TRACE(("Prevent/allow r. %d rem. drive %d\n",
2230 nscp->cmnd[4],nscp->cmnd[3]));
45f1a41b 2231 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
1da177e4
LT		 2232 this_cmd = FALSE;
2233 }
2234 break;
2235
2236 case RESERVE:
2237 case RELEASE:
2238 TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
2239 "RESERVE" : "RELEASE"));
45f1a41b 2240 if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
1da177e4
LT		 2241 this_cmd = FALSE;
2242 break;
2243
2244 case READ_6:
2245 case WRITE_6:
2246 case READ_10:
2247 case WRITE_10:
2248 case READ_16:
2249 case WRITE_16:
2250 if (ha->hdr[t].media_changed) {
2251 /* return UNIT_ATTENTION */
2252 TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
2253 nscp->cmnd[0], t));
2254 ha->hdr[t].media_changed = FALSE;
2255 memset((char*)nscp->sense_buffer,0,16);
2256 nscp->sense_buffer[0] = 0x70;
2257 nscp->sense_buffer[2] = UNIT_ATTENTION;
2258 nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
2259 if (!nscp->SCp.have_data_in)
2260 nscp->SCp.have_data_in++;
2261 else
b8bff2ae 2262 gdth_scsi_done(nscp);
45f1a41b 2263 } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
1da177e4
LT		 2264 this_cmd = FALSE;
2265 break;
2266
2267 default:
2268 TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
2269 nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
2270 nscp->cmnd[4],nscp->cmnd[5]));
2271 printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
45f1a41b 2272 ha->hanum, nscp->cmnd[0]);
1da177e4
LT		 2273 nscp->result = DID_ABORT << 16;
2274 if (!nscp->SCp.have_data_in)
2275 nscp->SCp.have_data_in++;
2276 else
b8bff2ae 2277 gdth_scsi_done(nscp);
1da177e4
LT		 2278 break;
2279 }
2280 }
2281
2282 if (!this_cmd)
2283 break;
2284 if (nscp == ha->req_first)
2285 ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
2286 else
2287 pscp->SCp.ptr = nscp->SCp.ptr;
2288 if (!next_cmd)
2289 break;
2290 }
2291
2292 if (ha->cmd_cnt > 0) {
45f1a41b 2293 gdth_release_event(ha);
1da177e4
LT		 2294 }
2295
2296 if (!gdth_polling)
2297 spin_unlock_irqrestore(&ha->smp_lock, flags);
2298
2299 if (gdth_polling && ha->cmd_cnt > 0) {
45f1a41b 2300 if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
1da177e4 2301 printk("GDT-HA %d: Command %d timed out !\n",
45f1a41b 2302 ha->hanum, cmd_index);
1da177e4
LT		 2303 }
2304}
2305
45f1a41b 2306static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
1da177e4
LT		 2307 char *buffer,ushort count)
2308{
2309 ushort cpcount,i;
2310 ushort cpsum,cpnow;
2311 struct scatterlist *sl;
1da177e4
LT		 2312 char *address;
2313
5d5ff44f 2314 cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
1da177e4
LT		 2315
2316 if (scp->use_sg) {
2317 sl = (struct scatterlist *)scp->request_buffer;
2318 for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
cbd5f69b 2319 unsigned long flags;
1da177e4
LT		 2320 cpnow = (ushort)sl->length;
2321 TRACE(("copy_internal() now %d sum %d count %d %d\n",
2322 cpnow,cpsum,cpcount,(ushort)scp->bufflen));
2323 if (cpsum+cpnow > cpcount)
2324 cpnow = cpcount - cpsum;
2325 cpsum += cpnow;
2326 if (!sl->page) {
2327 printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
45f1a41b 2328 ha->hanum);
1da177e4
LT		 2329 return;
2330 }
cbd5f69b 2331 local_irq_save(flags);
cbd5f69b
LA		 2332 address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
2333 memcpy(address,buffer,cpnow);
2334 flush_dcache_page(sl->page);
2335 kunmap_atomic(address, KM_BIO_SRC_IRQ);
cbd5f69b 2336 local_irq_restore(flags);
1da177e4
LT		 2337 if (cpsum == cpcount)
2338 break;
2339 buffer += cpnow;
2340 }
2341 } else {
2342 TRACE(("copy_internal() count %d\n",cpcount));
2343 memcpy((char*)scp->request_buffer,buffer,cpcount);
2344 }
2345}
2346
45f1a41b 2347static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
1da177e4 2348{
1da177e4
LT		 2349 unchar t;
2350 gdth_inq_data inq;
2351 gdth_rdcap_data rdc;
2352 gdth_sense_data sd;
2353 gdth_modep_data mpd;
2354
1da177e4
LT		 2355 t = scp->device->id;
2356 TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
2357 scp->cmnd[0],t));
2358
2359 scp->result = DID_OK << 16;
2360 scp->sense_buffer[0] = 0;
2361
2362 switch (scp->cmnd[0]) {
2363 case TEST_UNIT_READY:
2364 case VERIFY:
2365 case START_STOP:
2366 TRACE2(("Test/Verify/Start hdrive %d\n",t));
2367 break;
2368
2369 case INQUIRY:
2370 TRACE2(("Inquiry hdrive %d devtype %d\n",
2371 t,ha->hdr[t].devtype));
2372 inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
2373 /* you can here set all disks to removable, if you want to do
2374 a flush using the ALLOW_MEDIUM_REMOVAL command */
2375 inq.modif_rmb = 0x00;
2376 if ((ha->hdr[t].devtype & 1) ||
2377 (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
2378 inq.modif_rmb = 0x80;
2379 inq.version = 2;
2380 inq.resp_aenc = 2;
2381 inq.add_length= 32;
2382 strcpy(inq.vendor,ha->oem_name);
2383 sprintf(inq.product,"Host Drive #%02d",t);
2384 strcpy(inq.revision," ");
45f1a41b 2385 gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
1da177e4
LT		 2386 break;
2387
2388 case REQUEST_SENSE:
2389 TRACE2(("Request sense hdrive %d\n",t));
2390 sd.errorcode = 0x70;
2391 sd.segno = 0x00;
2392 sd.key = NO_SENSE;
2393 sd.info = 0;
2394 sd.add_length= 0;
45f1a41b 2395 gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
1da177e4
LT		 2396 break;
2397
2398 case MODE_SENSE:
2399 TRACE2(("Mode sense hdrive %d\n",t));
2400 memset((char*)&mpd,0,sizeof(gdth_modep_data));
2401 mpd.hd.data_length = sizeof(gdth_modep_data);
2402 mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
2403 mpd.hd.bd_length = sizeof(mpd.bd);
2404 mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
2405 mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
2406 mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
45f1a41b 2407 gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
1da177e4
LT		 2408 break;
2409
2410 case READ_CAPACITY:
2411 TRACE2(("Read capacity hdrive %d\n",t));
2412 if (ha->hdr[t].size > (ulong64)0xffffffff)
2413 rdc.last_block_no = 0xffffffff;
2414 else
2415 rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
2416 rdc.block_length = cpu_to_be32(SECTOR_SIZE);
45f1a41b 2417 gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
1da177e4
LT		 2418 break;
2419
2420 case SERVICE_ACTION_IN:
2421 if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
2422 (ha->cache_feat & GDT_64BIT)) {
2423 gdth_rdcap16_data rdc16;
2424
2425 TRACE2(("Read capacity (16) hdrive %d\n",t));
2426 rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
2427 rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
45f1a41b
BH		 2428 gdth_copy_internal_data(ha, scp, (char*)&rdc16,
2429 sizeof(gdth_rdcap16_data));
1da177e4
LT		 2430 } else {
2431 scp->result = DID_ABORT << 16;
2432 }
2433 break;
2434
2435 default:
2436 TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
2437 break;
2438 }
2439
2440 if (!scp->SCp.have_data_in)
2441 scp->SCp.have_data_in++;
2442 else
2443 return 1;
2444
2445 return 0;
2446}
45f1a41b
BH		 2447
2448static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
1da177e4 2449{
1da177e4
LT		 2450 register gdth_cmd_str *cmdp;
2451 struct scatterlist *sl;
2452 ulong32 cnt, blockcnt;
2453 ulong64 no, blockno;
2454 dma_addr_t phys_addr;
2455 int i, cmd_index, read_write, sgcnt, mode64;
2456 struct page *page;
2457 ulong offset;
2458
1da177e4
LT		 2459 cmdp = ha->pccb;
2460 TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
2461 scp->cmnd[0],scp->cmd_len,hdrive));
2462
2463 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2464 return 0;
2465
2466 mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
2467 /* test for READ_16, WRITE_16 if !mode64 ? ---
2468 not required, should not occur due to error return on
2469 READ_CAPACITY_16 */
2470
2471 cmdp->Service = CACHESERVICE;
2472 cmdp->RequestBuffer = scp;
2473 /* search free command index */
45f1a41b 2474 if (!(cmd_index=gdth_get_cmd_index(ha))) {
1da177e4
LT		 2475 TRACE(("GDT: No free command index found\n"));
2476 return 0;
2477 }
2478 /* if it's the first command, set command semaphore */
2479 if (ha->cmd_cnt == 0)
45f1a41b 2480 gdth_set_sema0(ha);
1da177e4
LT		 2481
2482 /* fill command */
2483 read_write = 0;
2484 if (scp->SCp.sent_command != -1)
2485 cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
2486 else if (scp->cmnd[0] == RESERVE)
2487 cmdp->OpCode = GDT_RESERVE_DRV;
2488 else if (scp->cmnd[0] == RELEASE)
2489 cmdp->OpCode = GDT_RELEASE_DRV;
2490 else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
2491 if (scp->cmnd[4] & 1) /* prevent ? */
2492 cmdp->OpCode = GDT_MOUNT;
2493 else if (scp->cmnd[3] & 1) /* removable drive ? */
2494 cmdp->OpCode = GDT_UNMOUNT;
2495 else
2496 cmdp->OpCode = GDT_FLUSH;
2497 } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
2498 scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
2499 ) {
2500 read_write = 1;
2501 if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
2502 (ha->cache_feat & GDT_WR_THROUGH)))
2503 cmdp->OpCode = GDT_WRITE_THR;
2504 else
2505 cmdp->OpCode = GDT_WRITE;
2506 } else {
2507 read_write = 2;
2508 cmdp->OpCode = GDT_READ;
2509 }
2510
2511 cmdp->BoardNode = LOCALBOARD;
2512 if (mode64) {
2513 cmdp->u.cache64.DeviceNo = hdrive;
2514 cmdp->u.cache64.BlockNo = 1;
2515 cmdp->u.cache64.sg_canz = 0;
2516 } else {
2517 cmdp->u.cache.DeviceNo = hdrive;
2518 cmdp->u.cache.BlockNo = 1;
2519 cmdp->u.cache.sg_canz = 0;
2520 }
2521
2522 if (read_write) {
2523 if (scp->cmd_len == 16) {
2524 memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
2525 blockno = be64_to_cpu(no);
2526 memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
2527 blockcnt = be32_to_cpu(cnt);
2528 } else if (scp->cmd_len == 10) {
2529 memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
2530 blockno = be32_to_cpu(no);
2531 memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
2532 blockcnt = be16_to_cpu(cnt);
2533 } else {
2534 memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
2535 blockno = be32_to_cpu(no) & 0x001fffffUL;
2536 blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
2537 }
2538 if (mode64) {
2539 cmdp->u.cache64.BlockNo = blockno;
2540 cmdp->u.cache64.BlockCnt = blockcnt;
2541 } else {
2542 cmdp->u.cache.BlockNo = (ulong32)blockno;
2543 cmdp->u.cache.BlockCnt = blockcnt;
2544 }
2545
2546 if (scp->use_sg) {
2547 sl = (struct scatterlist *)scp->request_buffer;
2548 sgcnt = scp->use_sg;
2549 scp->SCp.Status = GDTH_MAP_SG;
2550 scp->SCp.Message = (read_write == 1 ?
2551 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2552 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2553 if (mode64) {
2554 cmdp->u.cache64.DestAddr= (ulong64)-1;
2555 cmdp->u.cache64.sg_canz = sgcnt;
2556 for (i=0; i<sgcnt; ++i,++sl) {
2557 cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2558#ifdef GDTH_DMA_STATISTICS
2559 if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2560 ha->dma64_cnt++;
2561 else
2562 ha->dma32_cnt++;
2563#endif
2564 cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
2565 }
2566 } else {
2567 cmdp->u.cache.DestAddr= 0xffffffff;
2568 cmdp->u.cache.sg_canz = sgcnt;
2569 for (i=0; i<sgcnt; ++i,++sl) {
2570 cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
2571#ifdef GDTH_DMA_STATISTICS
2572 ha->dma32_cnt++;
2573#endif
2574 cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
2575 }
2576 }
2577
2578#ifdef GDTH_STATISTICS
2579 if (max_sg < (ulong32)sgcnt) {
2580 max_sg = (ulong32)sgcnt;
2581 TRACE3(("GDT: max_sg = %d\n",max_sg));
2582 }
2583#endif
2584
40cdc840 2585 } else if (scp->request_bufflen) {
1da177e4
LT		 2586 scp->SCp.Status = GDTH_MAP_SINGLE;
2587 scp->SCp.Message = (read_write == 1 ?
2588 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
2589 page = virt_to_page(scp->request_buffer);
2590 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2591 phys_addr = pci_map_page(ha->pdev,page,offset,
2592 scp->request_bufflen,scp->SCp.Message);
2593 scp->SCp.dma_handle = phys_addr;
2594 if (mode64) {
2595 if (ha->cache_feat & SCATTER_GATHER) {
2596 cmdp->u.cache64.DestAddr = (ulong64)-1;
2597 cmdp->u.cache64.sg_canz = 1;
2598 cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
2599 cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
2600 cmdp->u.cache64.sg_lst[1].sg_len = 0;
2601 } else {
2602 cmdp->u.cache64.DestAddr = phys_addr;
2603 cmdp->u.cache64.sg_canz= 0;
2604 }
2605 } else {
2606 if (ha->cache_feat & SCATTER_GATHER) {
2607 cmdp->u.cache.DestAddr = 0xffffffff;
2608 cmdp->u.cache.sg_canz = 1;
2609 cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
2610 cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
2611 cmdp->u.cache.sg_lst[1].sg_len = 0;
2612 } else {
2613 cmdp->u.cache.DestAddr = phys_addr;
2614 cmdp->u.cache.sg_canz= 0;
2615 }
2616 }
2617 }
2618 }
2619 /* evaluate command size, check space */
2620 if (mode64) {
2621 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2622 cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
2623 cmdp->u.cache64.sg_lst[0].sg_ptr,
2624 cmdp->u.cache64.sg_lst[0].sg_len));
2625 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2626 cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
2627 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
2628 (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
2629 } else {
2630 TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2631 cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
2632 cmdp->u.cache.sg_lst[0].sg_ptr,
2633 cmdp->u.cache.sg_lst[0].sg_len));
2634 TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
2635 cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
2636 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
2637 (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
2638 }
2639 if (ha->cmd_len & 3)
2640 ha->cmd_len += (4 - (ha->cmd_len & 3));
2641
2642 if (ha->cmd_cnt > 0) {
2643 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2644 ha->ic_all_size) {
2645 TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
2646 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2647 return 0;
2648 }
2649 }
2650
2651 /* copy command */
45f1a41b 2652 gdth_copy_command(ha);
1da177e4
LT		 2653 return cmd_index;
2654}
2655
45f1a41b 2656static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
1da177e4 2657{
1da177e4
LT		 2658 register gdth_cmd_str *cmdp;
2659 struct scatterlist *sl;
2660 ushort i;
2661 dma_addr_t phys_addr, sense_paddr;
2662 int cmd_index, sgcnt, mode64;
2663 unchar t,l;
2664 struct page *page;
2665 ulong offset;
3058d5de 2666 struct gdth_cmndinfo *cmndinfo;
1da177e4 2667
1da177e4
LT		 2668 t = scp->device->id;
2669 l = scp->device->lun;
2670 cmdp = ha->pccb;
2671 TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
2672 scp->cmnd[0],b,t,l));
2673
2674 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2675 return 0;
2676
2677 mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
2678
2679 cmdp->Service = SCSIRAWSERVICE;
2680 cmdp->RequestBuffer = scp;
2681 /* search free command index */
45f1a41b 2682 if (!(cmd_index=gdth_get_cmd_index(ha))) {
1da177e4
LT		 2683 TRACE(("GDT: No free command index found\n"));
2684 return 0;
2685 }
2686 /* if it's the first command, set command semaphore */
2687 if (ha->cmd_cnt == 0)
45f1a41b 2688 gdth_set_sema0(ha);
1da177e4 2689
3058d5de 2690 cmndinfo = gdth_cmnd_priv(scp);
1da177e4
LT		 2691 /* fill command */
2692 if (scp->SCp.sent_command != -1) {
2693 cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
2694 cmdp->BoardNode = LOCALBOARD;
2695 if (mode64) {
2696 cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
2697 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2698 cmdp->OpCode, cmdp->u.raw64.direction));
2699 /* evaluate command size */
2700 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
2701 } else {
2702 cmdp->u.raw.direction = (scp->SCp.phase >> 8);
2703 TRACE2(("special raw cmd 0x%x param 0x%x\n",
2704 cmdp->OpCode, cmdp->u.raw.direction));
2705 /* evaluate command size */
2706 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
2707 }
2708
2709 } else {
2710 page = virt_to_page(scp->sense_buffer);
2711 offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
2712 sense_paddr = pci_map_page(ha->pdev,page,offset,
2713 16,PCI_DMA_FROMDEVICE);
3058d5de
BH		 2714
2715 cmndinfo->sense_paddr = sense_paddr;
1da177e4
LT		 2716 cmdp->OpCode = GDT_WRITE; /* always */
2717 cmdp->BoardNode = LOCALBOARD;
2718 if (mode64) {
2719 cmdp->u.raw64.reserved = 0;
2720 cmdp->u.raw64.mdisc_time = 0;
2721 cmdp->u.raw64.mcon_time = 0;
2722 cmdp->u.raw64.clen = scp->cmd_len;
2723 cmdp->u.raw64.target = t;
2724 cmdp->u.raw64.lun = l;
2725 cmdp->u.raw64.bus = b;
2726 cmdp->u.raw64.priority = 0;
2727 cmdp->u.raw64.sdlen = scp->request_bufflen;
2728 cmdp->u.raw64.sense_len = 16;
2729 cmdp->u.raw64.sense_data = sense_paddr;
2730 cmdp->u.raw64.direction =
2731 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2732 memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
bb9ba31c 2733 cmdp->u.raw64.sg_ranz = 0;
1da177e4
LT		 2734 } else {
2735 cmdp->u.raw.reserved = 0;
2736 cmdp->u.raw.mdisc_time = 0;
2737 cmdp->u.raw.mcon_time = 0;
2738 cmdp->u.raw.clen = scp->cmd_len;
2739 cmdp->u.raw.target = t;
2740 cmdp->u.raw.lun = l;
2741 cmdp->u.raw.bus = b;
2742 cmdp->u.raw.priority = 0;
2743 cmdp->u.raw.link_p = 0;
2744 cmdp->u.raw.sdlen = scp->request_bufflen;
2745 cmdp->u.raw.sense_len = 16;
2746 cmdp->u.raw.sense_data = sense_paddr;
2747 cmdp->u.raw.direction =
2748 gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
2749 memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
bb9ba31c 2750 cmdp->u.raw.sg_ranz = 0;
1da177e4
LT		 2751 }
2752
2753 if (scp->use_sg) {
2754 sl = (struct scatterlist *)scp->request_buffer;
2755 sgcnt = scp->use_sg;
2756 scp->SCp.Status = GDTH_MAP_SG;
2757 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
2758 sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
2759 if (mode64) {
2760 cmdp->u.raw64.sdata = (ulong64)-1;
2761 cmdp->u.raw64.sg_ranz = sgcnt;
2762 for (i=0; i<sgcnt; ++i,++sl) {
2763 cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
2764#ifdef GDTH_DMA_STATISTICS
2765 if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
2766 ha->dma64_cnt++;
2767 else
2768 ha->dma32_cnt++;
2769#endif
2770 cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
2771 }
2772 } else {
2773 cmdp->u.raw.sdata = 0xffffffff;
2774 cmdp->u.raw.sg_ranz = sgcnt;
2775 for (i=0; i<sgcnt; ++i,++sl) {
2776 cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
2777#ifdef GDTH_DMA_STATISTICS
2778 ha->dma32_cnt++;
2779#endif
2780 cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
2781 }
2782 }
2783
2784#ifdef GDTH_STATISTICS
2785 if (max_sg < sgcnt) {
2786 max_sg = sgcnt;
2787 TRACE3(("GDT: max_sg = %d\n",sgcnt));
2788 }
2789#endif
2790
cbd5f69b 2791 } else if (scp->request_bufflen) {
1da177e4
LT		 2792 scp->SCp.Status = GDTH_MAP_SINGLE;
2793 scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
2794 page = virt_to_page(scp->request_buffer);
2795 offset = (ulong)scp->request_buffer & ~PAGE_MASK;
2796 phys_addr = pci_map_page(ha->pdev,page,offset,
2797 scp->request_bufflen,scp->SCp.Message);
2798 scp->SCp.dma_handle = phys_addr;
2799
2800 if (mode64) {
2801 if (ha->raw_feat & SCATTER_GATHER) {
2802 cmdp->u.raw64.sdata = (ulong64)-1;
2803 cmdp->u.raw64.sg_ranz= 1;
2804 cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
2805 cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
2806 cmdp->u.raw64.sg_lst[1].sg_len = 0;
2807 } else {
2808 cmdp->u.raw64.sdata = phys_addr;
2809 cmdp->u.raw64.sg_ranz= 0;
2810 }
2811 } else {
2812 if (ha->raw_feat & SCATTER_GATHER) {
2813 cmdp->u.raw.sdata = 0xffffffff;
2814 cmdp->u.raw.sg_ranz= 1;
2815 cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
2816 cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
2817 cmdp->u.raw.sg_lst[1].sg_len = 0;
2818 } else {
2819 cmdp->u.raw.sdata = phys_addr;
2820 cmdp->u.raw.sg_ranz= 0;
2821 }
2822 }
2823 }
2824 if (mode64) {
2825 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2826 cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
2827 cmdp->u.raw64.sg_lst[0].sg_ptr,
2828 cmdp->u.raw64.sg_lst[0].sg_len));
2829 /* evaluate command size */
2830 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
2831 (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
2832 } else {
2833 TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
2834 cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
2835 cmdp->u.raw.sg_lst[0].sg_ptr,
2836 cmdp->u.raw.sg_lst[0].sg_len));
2837 /* evaluate command size */
2838 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
2839 (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
2840 }
2841 }
2842 /* check space */
2843 if (ha->cmd_len & 3)
2844 ha->cmd_len += (4 - (ha->cmd_len & 3));
2845
2846 if (ha->cmd_cnt > 0) {
2847 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2848 ha->ic_all_size) {
2849 TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
2850 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2851 return 0;
2852 }
2853 }
2854
2855 /* copy command */
45f1a41b 2856 gdth_copy_command(ha);
1da177e4
LT		 2857 return cmd_index;
2858}
2859
45f1a41b 2860static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
1da177e4 2861{
1da177e4
LT		 2862 register gdth_cmd_str *cmdp;
2863 int cmd_index;
2864
1da177e4
LT		 2865 cmdp= ha->pccb;
2866 TRACE2(("gdth_special_cmd(): "));
2867
2868 if (ha->type==GDT_EISA && ha->cmd_cnt>0)
2869 return 0;
2870
2871 memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
2872 cmdp->RequestBuffer = scp;
2873
2874 /* search free command index */
45f1a41b 2875 if (!(cmd_index=gdth_get_cmd_index(ha))) {
1da177e4
LT		 2876 TRACE(("GDT: No free command index found\n"));
2877 return 0;
2878 }
2879
2880 /* if it's the first command, set command semaphore */
2881 if (ha->cmd_cnt == 0)
45f1a41b 2882 gdth_set_sema0(ha);
1da177e4
LT		 2883
2884 /* evaluate command size, check space */
2885 if (cmdp->OpCode == GDT_IOCTL) {
2886 TRACE2(("IOCTL\n"));
2887 ha->cmd_len =
2888 GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
2889 } else if (cmdp->Service == CACHESERVICE) {
2890 TRACE2(("cache command %d\n",cmdp->OpCode));
2891 if (ha->cache_feat & GDT_64BIT)
2892 ha->cmd_len =
2893 GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
2894 else
2895 ha->cmd_len =
2896 GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
2897 } else if (cmdp->Service == SCSIRAWSERVICE) {
2898 TRACE2(("raw command %d\n",cmdp->OpCode));
2899 if (ha->raw_feat & GDT_64BIT)
2900 ha->cmd_len =
2901 GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
2902 else
2903 ha->cmd_len =
2904 GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
2905 }
2906
2907 if (ha->cmd_len & 3)
2908 ha->cmd_len += (4 - (ha->cmd_len & 3));
2909
2910 if (ha->cmd_cnt > 0) {
2911 if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
2912 ha->ic_all_size) {
2913 TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
2914 ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
2915 return 0;
2916 }
2917 }
2918
2919 /* copy command */
45f1a41b 2920 gdth_copy_command(ha);
1da177e4
LT		 2921 return cmd_index;
2922}
2923
2924
2925/* Controller event handling functions */
2926static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
2927 ushort idx, gdth_evt_data *evt)
2928{
2929 gdth_evt_str *e;
2930 struct timeval tv;
2931
2932 /* no GDTH_LOCK_HA() ! */
2933 TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
2934 if (source == 0) /* no source -> no event */
2935 return NULL;
2936
2937 if (ebuffer[elastidx].event_source == source &&
2938 ebuffer[elastidx].event_idx == idx &&
2939 ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
2940 !memcmp((char *)&ebuffer[elastidx].event_data.eu,
2941 (char *)&evt->eu, evt->size)) ||
2942 (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
2943 !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
2944 (char *)&evt->event_string)))) {
2945 e = &ebuffer[elastidx];
2946 do_gettimeofday(&tv);
2947 e->last_stamp = tv.tv_sec;
2948 ++e->same_count;
2949 } else {
2950 if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
2951 ++elastidx;
2952 if (elastidx == MAX_EVENTS)
2953 elastidx = 0;
2954 if (elastidx == eoldidx) { /* reached mark ? */
2955 ++eoldidx;
2956 if (eoldidx == MAX_EVENTS)
2957 eoldidx = 0;
2958 }
2959 }
2960 e = &ebuffer[elastidx];
2961 e->event_source = source;
2962 e->event_idx = idx;
2963 do_gettimeofday(&tv);
2964 e->first_stamp = e->last_stamp = tv.tv_sec;
2965 e->same_count = 1;
2966 e->event_data = *evt;
2967 e->application = 0;
2968 }
2969 return e;
2970}
2971
2972static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
2973{
2974 gdth_evt_str *e;
2975 int eindex;
2976 ulong flags;
2977
2978 TRACE2(("gdth_read_event() handle %d\n", handle));
2979 spin_lock_irqsave(&ha->smp_lock, flags);
2980 if (handle == -1)
2981 eindex = eoldidx;
2982 else
2983 eindex = handle;
2984 estr->event_source = 0;
2985
2986 if (eindex >= MAX_EVENTS) {
2987 spin_unlock_irqrestore(&ha->smp_lock, flags);
2988 return eindex;
2989 }
2990 e = &ebuffer[eindex];
2991 if (e->event_source != 0) {
2992 if (eindex != elastidx) {
2993 if (++eindex == MAX_EVENTS)
2994 eindex = 0;
2995 } else {
2996 eindex = -1;
2997 }
2998 memcpy(estr, e, sizeof(gdth_evt_str));
2999 }
3000 spin_unlock_irqrestore(&ha->smp_lock, flags);
3001 return eindex;
3002}
3003
3004static void gdth_readapp_event(gdth_ha_str *ha,
3005 unchar application, gdth_evt_str *estr)
3006{
3007 gdth_evt_str *e;
3008 int eindex;
3009 ulong flags;
3010 unchar found = FALSE;
3011
3012 TRACE2(("gdth_readapp_event() app. %d\n", application));
3013 spin_lock_irqsave(&ha->smp_lock, flags);
3014 eindex = eoldidx;
3015 for (;;) {
3016 e = &ebuffer[eindex];
3017 if (e->event_source == 0)
3018 break;
3019 if ((e->application & application) == 0) {
3020 e->application |= application;
3021 found = TRUE;
3022 break;
3023 }
3024 if (eindex == elastidx)
3025 break;
3026 if (++eindex == MAX_EVENTS)
3027 eindex = 0;
3028 }
3029 if (found)
3030 memcpy(estr, e, sizeof(gdth_evt_str));
3031 else
3032 estr->event_source = 0;
3033 spin_unlock_irqrestore(&ha->smp_lock, flags);
3034}
3035
3036static void gdth_clear_events(void)
3037{
3038 TRACE(("gdth_clear_events()"));
3039
3040 eoldidx = elastidx = 0;
3041 ebuffer[0].event_source = 0;
3042}
3043
3044
3045/* SCSI interface functions */
3046
10e1b4bc
BH		 3047static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
3048 int gdth_from_wait, int* pIndex)
1da177e4 3049{
1da177e4
LT		 3050 gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
3051 gdt6_dpram_str __iomem *dp6_ptr;
3052 gdt2_dpram_str __iomem *dp2_ptr;
3053 Scsi_Cmnd *scp;
10e1b4bc 3054 int rval, i;
1da177e4
LT		 3055 unchar IStatus;
3056 ushort Service;
3057 ulong flags = 0;
3058#ifdef INT_COAL
3059 int coalesced = FALSE;
3060 int next = FALSE;
3061 gdth_coal_status *pcs = NULL;
3062 int act_int_coal = 0;
3063#endif
3064
3065 TRACE(("gdth_interrupt() IRQ %d\n",irq));
3066
3067 /* if polling and not from gdth_wait() -> return */
3068 if (gdth_polling) {
3069 if (!gdth_from_wait) {
3070 return IRQ_HANDLED;
3071 }
3072 }
3073
3074 if (!gdth_polling)
10e1b4bc 3075 spin_lock_irqsave(&ha->smp_lock, flags);
1da177e4
LT		 3076
3077 /* search controller */
10e1b4bc 3078 if (0 == (IStatus = gdth_get_status(ha, irq))) {
1da177e4
LT		 3079 /* spurious interrupt */
3080 if (!gdth_polling)
10e1b4bc
BH		 3081 spin_unlock_irqrestore(&ha->smp_lock, flags);
3082 return IRQ_HANDLED;
1da177e4 3083 }
1da177e4
LT		 3084
3085#ifdef GDTH_STATISTICS
3086 ++act_ints;
3087#endif
3088
3089#ifdef INT_COAL
3090 /* See if the fw is returning coalesced status */
3091 if (IStatus == COALINDEX) {
3092 /* Coalesced status. Setup the initial status
3093 buffer pointer and flags */
3094 pcs = ha->coal_stat;
3095 coalesced = TRUE;
3096 next = TRUE;
3097 }
3098
3099 do {
3100 if (coalesced) {
3101 /* For coalesced requests all status
3102 information is found in the status buffer */
3103 IStatus = (unchar)(pcs->status & 0xff);
3104 }
3105#endif
3106
3107 if (ha->type == GDT_EISA) {
3108 if (IStatus & 0x80) { /* error flag */
3109 IStatus &= ~0x80;
3110 ha->status = inw(ha->bmic + MAILBOXREG+8);
3111 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3112 } else /* no error */
3113 ha->status = S_OK;
3114 ha->info = inl(ha->bmic + MAILBOXREG+12);
3115 ha->service = inw(ha->bmic + MAILBOXREG+10);
3116 ha->info2 = inl(ha->bmic + MAILBOXREG+4);
3117
3118 outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
3119 outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
3120 } else if (ha->type == GDT_ISA) {
3121 dp2_ptr = ha->brd;
3122 if (IStatus & 0x80) { /* error flag */
3123 IStatus &= ~0x80;
a52667f3 3124 ha->status = readw(&dp2_ptr->u.ic.Status);
1da177e4
LT		 3125 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3126 } else /* no error */
3127 ha->status = S_OK;
a52667f3
JG		 3128 ha->info = readl(&dp2_ptr->u.ic.Info[0]);
3129 ha->service = readw(&dp2_ptr->u.ic.Service);
3130 ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
1da177e4 3131
a52667f3
JG		 3132 writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
3133 writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
3134 writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
1da177e4
LT		 3135 } else if (ha->type == GDT_PCI) {
3136 dp6_ptr = ha->brd;
3137 if (IStatus & 0x80) { /* error flag */
3138 IStatus &= ~0x80;
a52667f3 3139 ha->status = readw(&dp6_ptr->u.ic.Status);
1da177e4
LT		 3140 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3141 } else /* no error */
3142 ha->status = S_OK;
a52667f3
JG		 3143 ha->info = readl(&dp6_ptr->u.ic.Info[0]);
3144 ha->service = readw(&dp6_ptr->u.ic.Service);
3145 ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
1da177e4 3146
a52667f3
JG		 3147 writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
3148 writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
3149 writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
1da177e4
LT		 3150 } else if (ha->type == GDT_PCINEW) {
3151 if (IStatus & 0x80) { /* error flag */
3152 IStatus &= ~0x80;
3153 ha->status = inw(PTR2USHORT(&ha->plx->status));
3154 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3155 } else
3156 ha->status = S_OK;
3157 ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
3158 ha->service = inw(PTR2USHORT(&ha->plx->service));
3159 ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
3160
3161 outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
3162 outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
3163 } else if (ha->type == GDT_PCIMPR) {
3164 dp6m_ptr = ha->brd;
3165 if (IStatus & 0x80) { /* error flag */
3166 IStatus &= ~0x80;
3167#ifdef INT_COAL
3168 if (coalesced)
107e716b 3169 ha->status = pcs->ext_status & 0xffff;
1da177e4
LT		 3170 else
3171#endif
a52667f3 3172 ha->status = readw(&dp6m_ptr->i960r.status);
1da177e4
LT		 3173 TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
3174 } else /* no error */
3175 ha->status = S_OK;
3176#ifdef INT_COAL
3177 /* get information */
3178 if (coalesced) {
3179 ha->info = pcs->info0;
3180 ha->info2 = pcs->info1;
107e716b 3181 ha->service = (pcs->ext_status >> 16) & 0xffff;
1da177e4
LT		 3182 } else
3183#endif
3184 {
a52667f3
JG		 3185 ha->info = readl(&dp6m_ptr->i960r.info[0]);
3186 ha->service = readw(&dp6m_ptr->i960r.service);
3187 ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
1da177e4
LT		 3188 }
3189 /* event string */
3190 if (IStatus == ASYNCINDEX) {
3191 if (ha->service != SCREENSERVICE &&
3192 (ha->fw_vers & 0xff) >= 0x1a) {
a52667f3 3193 ha->dvr.severity = readb
1da177e4
LT		 3194 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
3195 for (i = 0; i < 256; ++i) {
a52667f3 3196 ha->dvr.event_string[i] = readb
1da177e4
LT		 3197 (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
3198 if (ha->dvr.event_string[i] == 0)
3199 break;
3200 }
3201 }
3202 }
3203#ifdef INT_COAL
3204 /* Make sure that non coalesced interrupts get cleared
3205 before being handled by gdth_async_event/gdth_sync_event */
3206 if (!coalesced)
3207#endif
3208 {
a52667f3
JG		 3209 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3210 writeb(0, &dp6m_ptr->i960r.sema1_reg);
1da177e4
LT		 3211 }
3212 } else {
3213 TRACE2(("gdth_interrupt() unknown controller type\n"));
3214 if (!gdth_polling)
10e1b4bc 3215 spin_unlock_irqrestore(&ha->smp_lock, flags);
1da177e4
LT		 3216 return IRQ_HANDLED;
3217 }
3218
3219 TRACE(("gdth_interrupt() index %d stat %d info %d\n",
3220 IStatus,ha->status,ha->info));
3221
3222 if (gdth_from_wait) {
10e1b4bc 3223 *pIndex = (int)IStatus;
1da177e4
LT		 3224 }
3225
3226 if (IStatus == ASYNCINDEX) {
3227 TRACE2(("gdth_interrupt() async. event\n"));
45f1a41b 3228 gdth_async_event(ha);
1da177e4 3229 if (!gdth_polling)
10e1b4bc 3230 spin_unlock_irqrestore(&ha->smp_lock, flags);
45f1a41b 3231 gdth_next(ha);
1da177e4
LT		 3232 return IRQ_HANDLED;
3233 }
3234
3235 if (IStatus == SPEZINDEX) {
3236 TRACE2(("Service unknown or not initialized !\n"));
3237 ha->dvr.size = sizeof(ha->dvr.eu.driver);
10e1b4bc 3238 ha->dvr.eu.driver.ionode = ha->hanum;
1da177e4
LT		 3239 gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
3240 if (!gdth_polling)
10e1b4bc 3241 spin_unlock_irqrestore(&ha->smp_lock, flags);
1da177e4
LT		 3242 return IRQ_HANDLED;
3243 }
3244 scp = ha->cmd_tab[IStatus-2].cmnd;
3245 Service = ha->cmd_tab[IStatus-2].service;
3246 ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
3247 if (scp == UNUSED_CMND) {
3248 TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
3249 ha->dvr.size = sizeof(ha->dvr.eu.driver);
10e1b4bc 3250 ha->dvr.eu.driver.ionode = ha->hanum;
1da177e4
LT		 3251 ha->dvr.eu.driver.index = IStatus;
3252 gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
3253 if (!gdth_polling)
10e1b4bc 3254 spin_unlock_irqrestore(&ha->smp_lock, flags);
1da177e4
LT		 3255 return IRQ_HANDLED;
3256 }
3257 if (scp == INTERNAL_CMND) {
3258 TRACE(("gdth_interrupt() answer to internal command\n"));
3259 if (!gdth_polling)
10e1b4bc 3260 spin_unlock_irqrestore(&ha->smp_lock, flags);
1da177e4
LT		 3261 return IRQ_HANDLED;
3262 }
3263
3264 TRACE(("gdth_interrupt() sync. status\n"));
45f1a41b 3265 rval = gdth_sync_event(ha,Service,IStatus,scp);
1da177e4 3266 if (!gdth_polling)
10e1b4bc 3267 spin_unlock_irqrestore(&ha->smp_lock, flags);
1da177e4 3268 if (rval == 2) {
45f1a41b 3269 gdth_putq(ha, scp,scp->SCp.this_residual);
1da177e4 3270 } else if (rval == 1) {
b8bff2ae 3271 gdth_scsi_done(scp);
1da177e4
LT		 3272 }
3273
3274#ifdef INT_COAL
3275 if (coalesced) {
3276 /* go to the next status in the status buffer */
3277 ++pcs;
3278#ifdef GDTH_STATISTICS
3279 ++act_int_coal;
3280 if (act_int_coal > max_int_coal) {
3281 max_int_coal = act_int_coal;
3282 printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
3283 }
3284#endif
3285 /* see if there is another status */
3286 if (pcs->status == 0)
3287 /* Stop the coalesce loop */
3288 next = FALSE;
3289 }
3290 } while (next);
3291
3292 /* coalescing only for new GDT_PCIMPR controllers available */
3293 if (ha->type == GDT_PCIMPR && coalesced) {
a52667f3
JG		 3294 writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
3295 writeb(0, &dp6m_ptr->i960r.sema1_reg);
1da177e4
LT		 3296 }
3297#endif
3298
45f1a41b 3299 gdth_next(ha);
1da177e4
LT		 3300 return IRQ_HANDLED;
3301}
3302
10e1b4bc
BH		 3303static irqreturn_t gdth_interrupt(int irq, void *dev_id)
3304{
3305 gdth_ha_str *ha = (gdth_ha_str *)dev_id;
3306
3307 return __gdth_interrupt(ha, irq, false, NULL);
3308}
3309
45f1a41b
BH		 3310static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
3311 Scsi_Cmnd *scp)
1da177e4 3312{
1da177e4
LT		 3313 gdth_msg_str *msg;
3314 gdth_cmd_str *cmdp;
3315 unchar b, t;
3058d5de 3316 struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
1da177e4 3317
1da177e4
LT		 3318 cmdp = ha->pccb;
3319 TRACE(("gdth_sync_event() serv %d status %d\n",
3320 service,ha->status));
3321
3322 if (service == SCREENSERVICE) {
3323 msg = ha->pmsg;
3324 TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
3325 msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
3326 if (msg->msg_len > MSGLEN+1)
3327 msg->msg_len = MSGLEN+1;
3328 if (msg->msg_len)
3329 if (!(msg->msg_answer && msg->msg_ext)) {
3330 msg->msg_text[msg->msg_len] = '\0';
3331 printk("%s",msg->msg_text);
3332 }
3333
3334 if (msg->msg_ext && !msg->msg_answer) {
45f1a41b 3335 while (gdth_test_busy(ha))
1da177e4
LT		 3336 gdth_delay(0);
3337 cmdp->Service = SCREENSERVICE;
3338 cmdp->RequestBuffer = SCREEN_CMND;
45f1a41b
BH		 3339 gdth_get_cmd_index(ha);
3340 gdth_set_sema0(ha);
1da177e4
LT		 3341 cmdp->OpCode = GDT_READ;
3342 cmdp->BoardNode = LOCALBOARD;
3343 cmdp->u.screen.reserved = 0;
3344 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3345 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3346 ha->cmd_offs_dpmem = 0;
3347 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3348 + sizeof(ulong64);
3349 ha->cmd_cnt = 0;
45f1a41b
BH		 3350 gdth_copy_command(ha);
3351 gdth_release_event(ha);
1da177e4
LT		 3352 return 0;
3353 }
3354
3355 if (msg->msg_answer && msg->msg_alen) {
3356 /* default answers (getchar() not possible) */
3357 if (msg->msg_alen == 1) {
3358 msg->msg_alen = 0;
3359 msg->msg_len = 1;
3360 msg->msg_text[0] = 0;
3361 } else {
3362 msg->msg_alen -= 2;
3363 msg->msg_len = 2;
3364 msg->msg_text[0] = 1;
3365 msg->msg_text[1] = 0;
3366 }
3367 msg->msg_ext = 0;
3368 msg->msg_answer = 0;
45f1a41b 3369 while (gdth_test_busy(ha))
1da177e4
LT		 3370 gdth_delay(0);
3371 cmdp->Service = SCREENSERVICE;
3372 cmdp->RequestBuffer = SCREEN_CMND;
45f1a41b
BH		 3373 gdth_get_cmd_index(ha);
3374 gdth_set_sema0(ha);
1da177e4
LT		 3375 cmdp->OpCode = GDT_WRITE;
3376 cmdp->BoardNode = LOCALBOARD;
3377 cmdp->u.screen.reserved = 0;
3378 cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
3379 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3380 ha->cmd_offs_dpmem = 0;
3381 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3382 + sizeof(ulong64);
3383 ha->cmd_cnt = 0;
45f1a41b
BH		 3384 gdth_copy_command(ha);
3385 gdth_release_event(ha);
1da177e4
LT		 3386 return 0;
3387 }
3388 printk("\n");
3389
3390 } else {
52759e6a 3391 b = scp->device->channel;
1da177e4
LT		 3392 t = scp->device->id;
3393 if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
3394 ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
3395 }
3396 /* cache or raw service */
3397 if (ha->status == S_BSY) {
3398 TRACE2(("Controller busy -> retry !\n"));
3399 if (scp->SCp.sent_command == GDT_MOUNT)
3400 scp->SCp.sent_command = GDT_CLUST_INFO;
3401 /* retry */
3402 return 2;
3403 }
3404 if (scp->SCp.Status == GDTH_MAP_SG)
3405 pci_unmap_sg(ha->pdev,scp->request_buffer,
3406 scp->use_sg,scp->SCp.Message);
3407 else if (scp->SCp.Status == GDTH_MAP_SINGLE)
3408 pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
3409 scp->request_bufflen,scp->SCp.Message);
3058d5de
BH		 3410 if (cmndinfo->sense_paddr)
3411 pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
3412 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3413
3414 if (ha->status == S_OK) {
3415 scp->SCp.Status = S_OK;
3416 scp->SCp.Message = ha->info;
3417 if (scp->SCp.sent_command != -1) {
3418 TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
3419 scp->SCp.sent_command));
3420 /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
3421 if (scp->SCp.sent_command == GDT_CLUST_INFO) {
3422 ha->hdr[t].cluster_type = (unchar)ha->info;
3423 if (!(ha->hdr[t].cluster_type &
3424 CLUSTER_MOUNTED)) {
3425 /* NOT MOUNTED -> MOUNT */
3426 scp->SCp.sent_command = GDT_MOUNT;
3427 if (ha->hdr[t].cluster_type &
3428 CLUSTER_RESERVED) {
3429 /* cluster drive RESERVED (on the other node) */
3430 scp->SCp.phase = -2; /* reservation conflict */
3431 }
3432 } else {
3433 scp->SCp.sent_command = -1;
3434 }
3435 } else {
3436 if (scp->SCp.sent_command == GDT_MOUNT) {
3437 ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
3438 ha->hdr[t].media_changed = TRUE;
3439 } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
3440 ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
3441 ha->hdr[t].media_changed = TRUE;
3442 }
3443 scp->SCp.sent_command = -1;
3444 }
3445 /* retry */
3446 scp->SCp.this_residual = HIGH_PRI;
3447 return 2;
3448 } else {
3449 /* RESERVE/RELEASE ? */
3450 if (scp->cmnd[0] == RESERVE) {
3451 ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
3452 } else if (scp->cmnd[0] == RELEASE) {
3453 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3454 }
3455 scp->result = DID_OK << 16;
3456 scp->sense_buffer[0] = 0;
3457 }
3458 } else {
3459 scp->SCp.Status = ha->status;
3460 scp->SCp.Message = ha->info;
3461
3462 if (scp->SCp.sent_command != -1) {
3463 TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
3464 scp->SCp.sent_command, ha->status));
3465 if (scp->SCp.sent_command == GDT_SCAN_START ||
3466 scp->SCp.sent_command == GDT_SCAN_END) {
3467 scp->SCp.sent_command = -1;
3468 /* retry */
3469 scp->SCp.this_residual = HIGH_PRI;
3470 return 2;
3471 }
3472 memset((char*)scp->sense_buffer,0,16);
3473 scp->sense_buffer[0] = 0x70;
3474 scp->sense_buffer[2] = NOT_READY;
3475 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3476 } else if (service == CACHESERVICE) {
3477 if (ha->status == S_CACHE_UNKNOWN &&
3478 (ha->hdr[t].cluster_type &
3479 CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
3480 /* bus reset -> force GDT_CLUST_INFO */
3481 ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
3482 }
3483 memset((char*)scp->sense_buffer,0,16);
3484 if (ha->status == (ushort)S_CACHE_RESERV) {
3485 scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
3486 } else {
3487 scp->sense_buffer[0] = 0x70;
3488 scp->sense_buffer[2] = NOT_READY;
3489 scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
3490 }
3058d5de 3491 if (!cmndinfo->internal_command) {
1da177e4 3492 ha->dvr.size = sizeof(ha->dvr.eu.sync);
45f1a41b 3493 ha->dvr.eu.sync.ionode = ha->hanum;
1da177e4
LT		 3494 ha->dvr.eu.sync.service = service;
3495 ha->dvr.eu.sync.status = ha->status;
3496 ha->dvr.eu.sync.info = ha->info;
3497 ha->dvr.eu.sync.hostdrive = t;
3498 if (ha->status >= 0x8000)
3499 gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
3500 else
3501 gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
3502 }
3503 } else {
3504 /* sense buffer filled from controller firmware (DMA) */
3505 if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
3506 scp->result = DID_BAD_TARGET << 16;
3507 } else {
3508 scp->result = (DID_OK << 16) | ha->info;
3509 }
3510 }
3511 }
3512 if (!scp->SCp.have_data_in)
3513 scp->SCp.have_data_in++;
3514 else
3515 return 1;
3516 }
3517
3518 return 0;
3519}
3520
3521static char *async_cache_tab[] = {
3522/* 0*/ "\011\000\002\002\002\004\002\006\004"
3523 "GDT HA %u, service %u, async. status %u/%lu unknown",
3524/* 1*/ "\011\000\002\002\002\004\002\006\004"
3525 "GDT HA %u, service %u, async. status %u/%lu unknown",
3526/* 2*/ "\005\000\002\006\004"
3527 "GDT HA %u, Host Drive %lu not ready",
3528/* 3*/ "\005\000\002\006\004"
3529 "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3530/* 4*/ "\005\000\002\006\004"
3531 "GDT HA %u, mirror update on Host Drive %lu failed",
3532/* 5*/ "\005\000\002\006\004"
3533 "GDT HA %u, Mirror Drive %lu failed",
3534/* 6*/ "\005\000\002\006\004"
3535 "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
3536/* 7*/ "\005\000\002\006\004"
3537 "GDT HA %u, Host Drive %lu write protected",
3538/* 8*/ "\005\000\002\006\004"
3539 "GDT HA %u, media changed in Host Drive %lu",
3540/* 9*/ "\005\000\002\006\004"
3541 "GDT HA %u, Host Drive %lu is offline",
3542/*10*/ "\005\000\002\006\004"
3543 "GDT HA %u, media change of Mirror Drive %lu",
3544/*11*/ "\005\000\002\006\004"
3545 "GDT HA %u, Mirror Drive %lu is write protected",
3546/*12*/ "\005\000\002\006\004"
3547 "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
3548/*13*/ "\007\000\002\006\002\010\002"
3549 "GDT HA %u, Array Drive %u: Cache Drive %u failed",
3550/*14*/ "\005\000\002\006\002"
3551 "GDT HA %u, Array Drive %u: FAIL state entered",
3552/*15*/ "\005\000\002\006\002"
3553 "GDT HA %u, Array Drive %u: error",
3554/*16*/ "\007\000\002\006\002\010\002"
3555 "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
3556/*17*/ "\005\000\002\006\002"
3557 "GDT HA %u, Array Drive %u: parity build failed",
3558/*18*/ "\005\000\002\006\002"
3559 "GDT HA %u, Array Drive %u: drive rebuild failed",
3560/*19*/ "\005\000\002\010\002"
3561 "GDT HA %u, Test of Hot Fix %u failed",
3562/*20*/ "\005\000\002\006\002"
3563 "GDT HA %u, Array Drive %u: drive build finished successfully",
3564/*21*/ "\005\000\002\006\002"
3565 "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
3566/*22*/ "\007\000\002\006\002\010\002"
3567 "GDT HA %u, Array Drive %u: Hot Fix %u activated",
3568/*23*/ "\005\000\002\006\002"
3569 "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
3570/*24*/ "\005\000\002\010\002"
3571 "GDT HA %u, mirror update on Cache Drive %u completed",
3572/*25*/ "\005\000\002\010\002"
3573 "GDT HA %u, mirror update on Cache Drive %lu failed",
3574/*26*/ "\005\000\002\006\002"
3575 "GDT HA %u, Array Drive %u: drive rebuild started",
3576/*27*/ "\005\000\002\012\001"
3577 "GDT HA %u, Fault bus %u: SHELF OK detected",
3578/*28*/ "\005\000\002\012\001"
3579 "GDT HA %u, Fault bus %u: SHELF not OK detected",
3580/*29*/ "\007\000\002\012\001\013\001"
3581 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
3582/*30*/ "\007\000\002\012\001\013\001"
3583 "GDT HA %u, Fault bus %u, ID %u: new disk detected",
3584/*31*/ "\007\000\002\012\001\013\001"
3585 "GDT HA %u, Fault bus %u, ID %u: old disk detected",
3586/*32*/ "\007\000\002\012\001\013\001"
3587 "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
3588/*33*/ "\007\000\002\012\001\013\001"
3589 "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
3590/*34*/ "\011\000\002\012\001\013\001\006\004"
3591 "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
3592/*35*/ "\007\000\002\012\001\013\001"
3593 "GDT HA %u, Fault bus %u, ID %u: disk write protected",
3594/*36*/ "\007\000\002\012\001\013\001"
3595 "GDT HA %u, Fault bus %u, ID %u: disk not available",
3596/*37*/ "\007\000\002\012\001\006\004"
3597 "GDT HA %u, Fault bus %u: swap detected (%lu)",
3598/*38*/ "\007\000\002\012\001\013\001"
3599 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
3600/*39*/ "\007\000\002\012\001\013\001"
3601 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
3602/*40*/ "\007\000\002\012\001\013\001"
3603 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
3604/*41*/ "\007\000\002\012\001\013\001"
3605 "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
3606/*42*/ "\005\000\002\006\002"
3607 "GDT HA %u, Array Drive %u: drive build started",
3608/*43*/ "\003\000\002"
3609 "GDT HA %u, DRAM parity error detected",
3610/*44*/ "\005\000\002\006\002"
3611 "GDT HA %u, Mirror Drive %u: update started",
3612/*45*/ "\007\000\002\006\002\010\002"
3613 "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
3614/*46*/ "\005\000\002\006\002"
3615 "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
3616/*47*/ "\005\000\002\006\002"
3617 "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
3618/*48*/ "\005\000\002\006\002"
3619 "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
3620/*49*/ "\005\000\002\006\002"
3621 "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
3622/*50*/ "\007\000\002\012\001\013\001"
3623 "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
3624/*51*/ "\005\000\002\006\002"
3625 "GDT HA %u, Array Drive %u: expand started",
3626/*52*/ "\005\000\002\006\002"
3627 "GDT HA %u, Array Drive %u: expand finished successfully",
3628/*53*/ "\005\000\002\006\002"
3629 "GDT HA %u, Array Drive %u: expand failed",
3630/*54*/ "\003\000\002"
3631 "GDT HA %u, CPU temperature critical",
3632/*55*/ "\003\000\002"
3633 "GDT HA %u, CPU temperature OK",
3634/*56*/ "\005\000\002\006\004"
3635 "GDT HA %u, Host drive %lu created",
3636/*57*/ "\005\000\002\006\002"
3637 "GDT HA %u, Array Drive %u: expand restarted",
3638/*58*/ "\005\000\002\006\002"
3639 "GDT HA %u, Array Drive %u: expand stopped",
3640/*59*/ "\005\000\002\010\002"
3641 "GDT HA %u, Mirror Drive %u: drive build quited",
3642/*60*/ "\005\000\002\006\002"
3643 "GDT HA %u, Array Drive %u: parity build quited",
3644/*61*/ "\005\000\002\006\002"
3645 "GDT HA %u, Array Drive %u: drive rebuild quited",
3646/*62*/ "\005\000\002\006\002"
3647 "GDT HA %u, Array Drive %u: parity verify started",
3648/*63*/ "\005\000\002\006\002"
3649 "GDT HA %u, Array Drive %u: parity verify done",
3650/*64*/ "\005\000\002\006\002"
3651 "GDT HA %u, Array Drive %u: parity verify failed",
3652/*65*/ "\005\000\002\006\002"
3653 "GDT HA %u, Array Drive %u: parity error detected",
3654/*66*/ "\005\000\002\006\002"
3655 "GDT HA %u, Array Drive %u: parity verify quited",
3656/*67*/ "\005\000\002\006\002"
3657 "GDT HA %u, Host Drive %u reserved",
3658/*68*/ "\005\000\002\006\002"
3659 "GDT HA %u, Host Drive %u mounted and released",
3660/*69*/ "\005\000\002\006\002"
3661 "GDT HA %u, Host Drive %u released",
3662/*70*/ "\003\000\002"
3663 "GDT HA %u, DRAM error detected and corrected with ECC",
3664/*71*/ "\003\000\002"
3665 "GDT HA %u, Uncorrectable DRAM error detected with ECC",
3666/*72*/ "\011\000\002\012\001\013\001\014\001"
3667 "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
3668/*73*/ "\005\000\002\006\002"
3669 "GDT HA %u, Host drive %u resetted locally",
3670/*74*/ "\005\000\002\006\002"
3671 "GDT HA %u, Host drive %u resetted remotely",
3672/*75*/ "\003\000\002"
3673 "GDT HA %u, async. status 75 unknown",
3674};
3675
3676
45f1a41b 3677static int gdth_async_event(gdth_ha_str *ha)
1da177e4 3678{
1da177e4
LT		 3679 gdth_cmd_str *cmdp;
3680 int cmd_index;
3681
1da177e4
LT		 3682 cmdp= ha->pccb;
3683 TRACE2(("gdth_async_event() ha %d serv %d\n",
45f1a41b 3684 ha->hanum, ha->service));
1da177e4
LT		 3685
3686 if (ha->service == SCREENSERVICE) {
3687 if (ha->status == MSG_REQUEST) {
45f1a41b 3688 while (gdth_test_busy(ha))
1da177e4
LT		 3689 gdth_delay(0);
3690 cmdp->Service = SCREENSERVICE;
3691 cmdp->RequestBuffer = SCREEN_CMND;
45f1a41b
BH		 3692 cmd_index = gdth_get_cmd_index(ha);
3693 gdth_set_sema0(ha);
1da177e4
LT		 3694 cmdp->OpCode = GDT_READ;
3695 cmdp->BoardNode = LOCALBOARD;
3696 cmdp->u.screen.reserved = 0;
3697 cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
3698 cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
3699 ha->cmd_offs_dpmem = 0;
3700 ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
3701 + sizeof(ulong64);
3702 ha->cmd_cnt = 0;
45f1a41b 3703 gdth_copy_command(ha);
1da177e4
LT		 3704 if (ha->type == GDT_EISA)
3705 printk("[EISA slot %d] ",(ushort)ha->brd_phys);
3706 else if (ha->type == GDT_ISA)
3707 printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
3708 else
3709 printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
3710 (ushort)((ha->brd_phys>>3)&0x1f));
45f1a41b 3711 gdth_release_event(ha);
1da177e4
LT		 3712 }
3713
3714 } else {
3715 if (ha->type == GDT_PCIMPR &&
3716 (ha->fw_vers & 0xff) >= 0x1a) {
3717 ha->dvr.size = 0;
45f1a41b 3718 ha->dvr.eu.async.ionode = ha->hanum;
1da177e4
LT		 3719 ha->dvr.eu.async.status = ha->status;
3720 /* severity and event_string already set! */
3721 } else {
3722 ha->dvr.size = sizeof(ha->dvr.eu.async);
45f1a41b 3723 ha->dvr.eu.async.ionode = ha->hanum;
1da177e4
LT		 3724 ha->dvr.eu.async.service = ha->service;
3725 ha->dvr.eu.async.status = ha->status;
3726 ha->dvr.eu.async.info = ha->info;
3727 *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
3728 }
3729 gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
3730 gdth_log_event( &ha->dvr, NULL );
3731
3732 /* new host drive from expand? */
3733 if (ha->service == CACHESERVICE && ha->status == 56) {
3734 TRACE2(("gdth_async_event(): new host drive %d created\n",
3735 (ushort)ha->info));
3736 /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
3737 }
3738 }
3739 return 1;
3740}
3741
3742static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
3743{
3744 gdth_stackframe stack;
3745 char *f = NULL;
3746 int i,j;
3747
3748 TRACE2(("gdth_log_event()\n"));
3749 if (dvr->size == 0) {
3750 if (buffer == NULL) {
3751 printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
3752 } else {
3753 sprintf(buffer,"Adapter %d: %s\n",
3754 dvr->eu.async.ionode,dvr->event_string);
3755 }
3756 } else if (dvr->eu.async.service == CACHESERVICE &&
3757 INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
3758 TRACE2(("GDT: Async. event cache service, event no.: %d\n",
3759 dvr->eu.async.status));
3760
3761 f = async_cache_tab[dvr->eu.async.status];
3762
3763 /* i: parameter to push, j: stack element to fill */
3764 for (j=0,i=1; i < f[0]; i+=2) {
3765 switch (f[i+1]) {
3766 case 4:
3767 stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
3768 break;
3769 case 2:
3770 stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
3771 break;
3772 case 1:
3773 stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
3774 break;
3775 default:
3776 break;
3777 }
3778 }
3779
3780 if (buffer == NULL) {
3781 printk(&f[(int)f[0]],stack);
3782 printk("\n");
3783 } else {
3784 sprintf(buffer,&f[(int)f[0]],stack);
3785 }
3786
3787 } else {
3788 if (buffer == NULL) {
3789 printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
3790 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3791 } else {
3792 sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
3793 dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
3794 }
3795 }
3796}
3797
3798#ifdef GDTH_STATISTICS
8e879041 3799static void gdth_timeout(ulong data)
1da177e4
LT		 3800{
3801 ulong32 i;
3802 Scsi_Cmnd *nscp;
3803 gdth_ha_str *ha;
3804 ulong flags;
1da177e4 3805
884f7fba 3806 ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
1da177e4
LT		 3807 spin_lock_irqsave(&ha->smp_lock, flags);
3808
3809 for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
3810 if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
3811 ++act_stats;
3812
3813 for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
3814 ++act_rq;
3815
3816 TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
3817 act_ints, act_ios, act_stats, act_rq));
3818 act_ints = act_ios = 0;
3819
3820 gdth_timer.expires = jiffies + 30 * HZ;
3821 add_timer(&gdth_timer);
3822 spin_unlock_irqrestore(&ha->smp_lock, flags);
3823}
3824#endif
3825
8e879041 3826static void __init internal_setup(char *str,int *ints)
1da177e4
LT		 3827{
3828 int i, argc;
3829 char *cur_str, *argv;
3830
3831 TRACE2(("internal_setup() str %s ints[0] %d\n",
3832 str ? str:"NULL", ints ? ints[0]:0));
3833
3834 /* read irq[] from ints[] */
3835 if (ints) {
3836 argc = ints[0];
3837 if (argc > 0) {
3838 if (argc > MAXHA)
3839 argc = MAXHA;
3840 for (i = 0; i < argc; ++i)
3841 irq[i] = ints[i+1];
3842 }
3843 }
3844
3845 /* analyse string */
3846 argv = str;
3847 while (argv && (cur_str = strchr(argv, ':'))) {
3848 int val = 0, c = *++cur_str;
3849
3850 if (c == 'n' || c == 'N')
3851 val = 0;
3852 else if (c == 'y' || c == 'Y')
3853 val = 1;
3854 else
3855 val = (int)simple_strtoul(cur_str, NULL, 0);
3856
3857 if (!strncmp(argv, "disable:", 8))
3858 disable = val;
3859 else if (!strncmp(argv, "reserve_mode:", 13))
3860 reserve_mode = val;
3861 else if (!strncmp(argv, "reverse_scan:", 13))
3862 reverse_scan = val;
3863 else if (!strncmp(argv, "hdr_channel:", 12))
3864 hdr_channel = val;
3865 else if (!strncmp(argv, "max_ids:", 8))
3866 max_ids = val;
3867 else if (!strncmp(argv, "rescan:", 7))
3868 rescan = val;
1da177e4
LT		 3869 else if (!strncmp(argv, "shared_access:", 14))
3870 shared_access = val;
3871 else if (!strncmp(argv, "probe_eisa_isa:", 15))
3872 probe_eisa_isa = val;
3873 else if (!strncmp(argv, "reserve_list:", 13)) {
3874 reserve_list[0] = val;
3875 for (i = 1; i < MAX_RES_ARGS; i++) {
3876 cur_str = strchr(cur_str, ',');
3877 if (!cur_str)
3878 break;
3879 if (!isdigit((int)*++cur_str)) {
3880 --cur_str;
3881 break;
3882 }
3883 reserve_list[i] =
3884 (int)simple_strtoul(cur_str, NULL, 0);
3885 }
3886 if (!cur_str)
3887 break;
3888 argv = ++cur_str;
3889 continue;
3890 }
3891
3892 if ((argv = strchr(argv, ',')))
3893 ++argv;
3894 }
3895}
3896
3897int __init option_setup(char *str)
3898{
3899 int ints[MAXHA];
3900 char *cur = str;
3901 int i = 1;
3902
3903 TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
3904
3905 while (cur && isdigit(*cur) && i <= MAXHA) {
3906 ints[i++] = simple_strtoul(cur, NULL, 0);
3907 if ((cur = strchr(cur, ',')) != NULL) cur++;
3908 }
3909
3910 ints[0] = i - 1;
3911 internal_setup(cur, ints);
3912 return 1;
3913}
3914
45f1a41b 3915static const char *gdth_ctr_name(gdth_ha_str *ha)
1da177e4 3916{
1da177e4
LT		 3917 TRACE2(("gdth_ctr_name()\n"));
3918
1da177e4
LT		 3919 if (ha->type == GDT_EISA) {
3920 switch (ha->stype) {
3921 case GDT3_ID:
3922 return("GDT3000/3020");
3923 case GDT3A_ID:
3924 return("GDT3000A/3020A/3050A");
3925 case GDT3B_ID:
3926 return("GDT3000B/3010A");
3927 }
3928 } else if (ha->type == GDT_ISA) {
3929 return("GDT2000/2020");
3930 } else if (ha->type == GDT_PCI) {
8e9a8a0d 3931 switch (ha->pdev->device) {
1da177e4
LT		 3932 case PCI_DEVICE_ID_VORTEX_GDT60x0:
3933 return("GDT6000/6020/6050");
3934 case PCI_DEVICE_ID_VORTEX_GDT6000B:
3935 return("GDT6000B/6010");
3936 }
3937 }
3938 /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
3939
3940 return("");
3941}
3942
8e879041 3943static const char *gdth_info(struct Scsi_Host *shp)
1da177e4 3944{
45f1a41b 3945 gdth_ha_str *ha = shost_priv(shp);
1da177e4
LT		 3946
3947 TRACE2(("gdth_info()\n"));
1da177e4
LT		 3948 return ((const char *)ha->binfo.type_string);
3949}
3950
8e879041 3951static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
1da177e4 3952{
45f1a41b
BH		 3953 gdth_ha_str *ha = shost_priv(scp->device->host);
3954 int i;
1da177e4
LT		 3955 ulong flags;
3956 Scsi_Cmnd *cmnd;
3957 unchar b;
3958
3959 TRACE2(("gdth_eh_bus_reset()\n"));
3960
52759e6a 3961 b = scp->device->channel;
1da177e4
LT		 3962
3963 /* clear command tab */
3964 spin_lock_irqsave(&ha->smp_lock, flags);
3965 for (i = 0; i < GDTH_MAXCMDS; ++i) {
3966 cmnd = ha->cmd_tab[i].cmnd;
3967 if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
3968 ha->cmd_tab[i].cmnd = UNUSED_CMND;
3969 }
3970 spin_unlock_irqrestore(&ha->smp_lock, flags);
3971
3972 if (b == ha->virt_bus) {
3973 /* host drives */
3974 for (i = 0; i < MAX_HDRIVES; ++i) {
3975 if (ha->hdr[i].present) {
3976 spin_lock_irqsave(&ha->smp_lock, flags);
3977 gdth_polling = TRUE;
45f1a41b 3978 while (gdth_test_busy(ha))
1da177e4 3979 gdth_delay(0);
45f1a41b 3980 if (gdth_internal_cmd(ha, CACHESERVICE,
1da177e4
LT		 3981 GDT_CLUST_RESET, i, 0, 0))
3982 ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
3983 gdth_polling = FALSE;
3984 spin_unlock_irqrestore(&ha->smp_lock, flags);
3985 }
3986 }
3987 } else {
3988 /* raw devices */
3989 spin_lock_irqsave(&ha->smp_lock, flags);
3990 for (i = 0; i < MAXID; ++i)
3991 ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
3992 gdth_polling = TRUE;
45f1a41b 3993 while (gdth_test_busy(ha))
1da177e4 3994 gdth_delay(0);
45f1a41b 3995 gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
1da177e4
LT		 3996 BUS_L2P(ha,b), 0, 0);
3997 gdth_polling = FALSE;
cbd5f69b 3998 spin_unlock_irqrestore(&ha->smp_lock, flags);
1da177e4
LT		 3999 }
4000 return SUCCESS;
4001}
4002
8e879041 4003static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
1da177e4
LT		 4004{
4005 unchar b, t;
45f1a41b 4006 gdth_ha_str *ha = shost_priv(sdev->host);
1da177e4
LT		 4007 struct scsi_device *sd;
4008 unsigned capacity;
4009
1da177e4
LT		 4010 sd = sdev;
4011 capacity = cap;
52759e6a 4012 b = sd->channel;
1da177e4 4013 t = sd->id;
45f1a41b 4014 TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
1da177e4
LT		 4015
4016 if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
4017 /* raw device or host drive without mapping information */
4018 TRACE2(("Evaluate mapping\n"));
4019 gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
4020 } else {
4021 ip[0] = ha->hdr[t].heads;
4022 ip[1] = ha->hdr[t].secs;
4023 ip[2] = capacity / ip[0] / ip[1];
4024 }
4025
4026 TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
4027 ip[0],ip[1],ip[2]));
4028 return 0;
4029}
4030
4031
b8bff2ae
MW		 4032static int gdth_queuecommand(struct scsi_cmnd *scp,
4033 void (*done)(struct scsi_cmnd *))
1da177e4 4034{
45f1a41b 4035 gdth_ha_str *ha = shost_priv(scp->device->host);
3058d5de 4036 struct gdth_cmndinfo *cmndinfo;
1da177e4
LT		 4037
4038 TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
3058d5de
BH		 4039
4040 cmndinfo = gdth_get_cmndinfo(ha);
4041 BUG_ON(!cmndinfo);
4042
b8bff2ae 4043 scp->scsi_done = done;
3058d5de
BH		 4044 gdth_update_timeout(scp, scp->timeout_per_command * 6);
4045 scp->SCp.this_residual = DEFAULT_PRI;
4046 return __gdth_queuecommand(ha, scp, cmndinfo);
4047}
4048
4049static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
4050 struct gdth_cmndinfo *cmndinfo)
4051{
4052 scp->host_scribble = (unsigned char *)cmndinfo;
1da177e4
LT		 4053 scp->SCp.have_data_in = 1;
4054 scp->SCp.phase = -1;
4055 scp->SCp.sent_command = -1;
4056 scp->SCp.Status = GDTH_MAP_NONE;
1da177e4 4057
1da177e4
LT		 4058#ifdef GDTH_STATISTICS
4059 ++act_ios;
4060#endif
4061
3058d5de 4062 gdth_putq(ha, scp, scp->SCp.this_residual);
45f1a41b 4063 gdth_next(ha);
1da177e4
LT		 4064 return 0;
4065}
4066
4067
4068static int gdth_open(struct inode *inode, struct file *filep)
4069{
4070 gdth_ha_str *ha;
1da177e4 4071
884f7fba 4072 list_for_each_entry(ha, &gdth_instances, list) {
1da177e4 4073 if (!ha->sdev)
884f7fba 4074 ha->sdev = scsi_get_host_dev(ha->shost);
1da177e4
LT		 4075 }
4076
4077 TRACE(("gdth_open()\n"));
4078 return 0;
4079}
4080
4081static int gdth_close(struct inode *inode, struct file *filep)
4082{
4083 TRACE(("gdth_close()\n"));
4084 return 0;
4085}
4086
4087static int ioc_event(void __user *arg)
4088{
4089 gdth_ioctl_event evt;
4090 gdth_ha_str *ha;
4091 ulong flags;
4092
884f7fba
BH		 4093 if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
4094 return -EFAULT;
4095 ha = gdth_find_ha(evt.ionode);
4096 if (!ha)
1da177e4 4097 return -EFAULT;
1da177e4
LT		 4098
4099 if (evt.erase == 0xff) {
4100 if (evt.event.event_source == ES_TEST)
4101 evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
4102 else if (evt.event.event_source == ES_DRIVER)
4103 evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
4104 else if (evt.event.event_source == ES_SYNC)
4105 evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
4106 else
4107 evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
4108 spin_lock_irqsave(&ha->smp_lock, flags);
4109 gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
4110 &evt.event.event_data);
4111 spin_unlock_irqrestore(&ha->smp_lock, flags);
4112 } else if (evt.erase == 0xfe) {
4113 gdth_clear_events();
4114 } else if (evt.erase == 0) {
4115 evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
4116 } else {
4117 gdth_readapp_event(ha, evt.erase, &evt.event);
4118 }
4119 if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
4120 return -EFAULT;
4121 return 0;
4122}
4123
4124static int ioc_lockdrv(void __user *arg)
4125{
4126 gdth_ioctl_lockdrv ldrv;
4127 unchar i, j;
4128 ulong flags;
4129 gdth_ha_str *ha;
4130
884f7fba 4131 if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
1da177e4 4132 return -EFAULT;
884f7fba
BH		 4133 ha = gdth_find_ha(ldrv.ionode);
4134 if (!ha)
4135 return -EFAULT;
4136
1da177e4
LT		 4137 for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
4138 j = ldrv.drives[i];
4139 if (j >= MAX_HDRIVES || !ha->hdr[j].present)
4140 continue;
4141 if (ldrv.lock) {
4142 spin_lock_irqsave(&ha->smp_lock, flags);
4143 ha->hdr[j].lock = 1;
4144 spin_unlock_irqrestore(&ha->smp_lock, flags);
45f1a41b
BH		 4145 gdth_wait_completion(ha, ha->bus_cnt, j);
4146 gdth_stop_timeout(ha, ha->bus_cnt, j);
1da177e4
LT		 4147 } else {
4148 spin_lock_irqsave(&ha->smp_lock, flags);
4149 ha->hdr[j].lock = 0;
4150 spin_unlock_irqrestore(&ha->smp_lock, flags);
45f1a41b
BH		 4151 gdth_start_timeout(ha, ha->bus_cnt, j);
4152 gdth_next(ha);
1da177e4
LT		 4153 }
4154 }
4155 return 0;
4156}
4157
4158static int ioc_resetdrv(void __user *arg, char *cmnd)
4159{
4160 gdth_ioctl_reset res;
4161 gdth_cmd_str cmd;
1da177e4 4162 gdth_ha_str *ha;
cbd5f69b 4163 int rval;
1da177e4
LT		 4164
4165 if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
884f7fba
BH		 4166 res.number >= MAX_HDRIVES)
4167 return -EFAULT;
4168 ha = gdth_find_ha(res.ionode);
4169 if (!ha)
1da177e4 4170 return -EFAULT;
45f1a41b 4171
1da177e4
LT		 4172 if (!ha->hdr[res.number].present)
4173 return 0;
4174 memset(&cmd, 0, sizeof(gdth_cmd_str));
4175 cmd.Service = CACHESERVICE;
4176 cmd.OpCode = GDT_CLUST_RESET;
4177 if (ha->cache_feat & GDT_64BIT)
4178 cmd.u.cache64.DeviceNo = res.number;
4179 else
4180 cmd.u.cache.DeviceNo = res.number;
cbd5f69b
LA		 4181
4182 rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
4183 if (rval < 0)
4184 return rval;
4185 res.status = rval;
1da177e4
LT		 4186
4187 if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
4188 return -EFAULT;
4189 return 0;
4190}
4191
4192static int ioc_general(void __user *arg, char *cmnd)
4193{
4194 gdth_ioctl_general gen;
4195 char *buf = NULL;
4196 ulong64 paddr;
cbd5f69b
LA		 4197 gdth_ha_str *ha;
4198 int rval;
884f7fba
BH		 4199
4200 if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
4201 return -EFAULT;
4202 ha = gdth_find_ha(gen.ionode);
4203 if (!ha)
1da177e4 4204 return -EFAULT;
1da177e4 4205 if (gen.data_len + gen.sense_len != 0) {
45f1a41b 4206 if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
1da177e4
LT		 4207 FALSE, &paddr)))
4208 return -EFAULT;
4209 if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
4210 gen.data_len + gen.sense_len)) {
45f1a41b 4211 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
1da177e4
LT		 4212 return -EFAULT;
4213 }
4214
4215 if (gen.command.OpCode == GDT_IOCTL) {
4216 gen.command.u.ioctl.p_param = paddr;
4217 } else if (gen.command.Service == CACHESERVICE) {
4218 if (ha->cache_feat & GDT_64BIT) {
4219 /* copy elements from 32-bit IOCTL structure */
4220 gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
4221 gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
4222 gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
4223 /* addresses */
4224 if (ha->cache_feat & SCATTER_GATHER) {
4225 gen.command.u.cache64.DestAddr = (ulong64)-1;
4226 gen.command.u.cache64.sg_canz = 1;
4227 gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
4228 gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
4229 gen.command.u.cache64.sg_lst[1].sg_len = 0;
4230 } else {
4231 gen.command.u.cache64.DestAddr = paddr;
4232 gen.command.u.cache64.sg_canz = 0;
4233 }
4234 } else {
4235 if (ha->cache_feat & SCATTER_GATHER) {
4236 gen.command.u.cache.DestAddr = 0xffffffff;
4237 gen.command.u.cache.sg_canz = 1;
4238 gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
4239 gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
4240 gen.command.u.cache.sg_lst[1].sg_len = 0;
4241 } else {
4242 gen.command.u.cache.DestAddr = paddr;
4243 gen.command.u.cache.sg_canz = 0;
4244 }
4245 }
4246 } else if (gen.command.Service == SCSIRAWSERVICE) {
4247 if (ha->raw_feat & GDT_64BIT) {
4248 /* copy elements from 32-bit IOCTL structure */
4249 char cmd[16];
4250 gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
4251 gen.command.u.raw64.bus = gen.command.u.raw.bus;
4252 gen.command.u.raw64.lun = gen.command.u.raw.lun;
4253 gen.command.u.raw64.target = gen.command.u.raw.target;
4254 memcpy(cmd, gen.command.u.raw.cmd, 16);
4255 memcpy(gen.command.u.raw64.cmd, cmd, 16);
4256 gen.command.u.raw64.clen = gen.command.u.raw.clen;
4257 gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
4258 gen.command.u.raw64.direction = gen.command.u.raw.direction;
4259 /* addresses */
4260 if (ha->raw_feat & SCATTER_GATHER) {
4261 gen.command.u.raw64.sdata = (ulong64)-1;
4262 gen.command.u.raw64.sg_ranz = 1;
4263 gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
4264 gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
4265 gen.command.u.raw64.sg_lst[1].sg_len = 0;
4266 } else {
4267 gen.command.u.raw64.sdata = paddr;
4268 gen.command.u.raw64.sg_ranz = 0;
4269 }
4270 gen.command.u.raw64.sense_data = paddr + gen.data_len;
4271 } else {
4272 if (ha->raw_feat & SCATTER_GATHER) {
4273 gen.command.u.raw.sdata = 0xffffffff;
4274 gen.command.u.raw.sg_ranz = 1;
4275 gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
4276 gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
4277 gen.command.u.raw.sg_lst[1].sg_len = 0;
4278 } else {
4279 gen.command.u.raw.sdata = paddr;
4280 gen.command.u.raw.sg_ranz = 0;
4281 }
4282 gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
4283 }
4284 } else {
45f1a41b 4285 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
1da177e4
LT		 4286 return -EFAULT;
4287 }
4288 }
4289
cbd5f69b
LA		 4290 rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
4291 if (rval < 0)
4292 return rval;
4293 gen.status = rval;
1da177e4
LT		 4294
4295 if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
4296 gen.data_len + gen.sense_len)) {
45f1a41b 4297 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
1da177e4
LT		 4298 return -EFAULT;
4299 }
4300 if (copy_to_user(arg, &gen,
4301 sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
45f1a41b 4302 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
1da177e4
LT		 4303 return -EFAULT;
4304 }
45f1a41b 4305 gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
1da177e4
LT		 4306 return 0;
4307}
4308
4309static int ioc_hdrlist(void __user *arg, char *cmnd)
4310{
4311 gdth_ioctl_rescan *rsc;
4312 gdth_cmd_str *cmd;
4313 gdth_ha_str *ha;
4314 unchar i;
45f1a41b 4315 int rc = -ENOMEM;
cbd5f69b
LA		 4316 u32 cluster_type = 0;
4317
1da177e4
LT		 4318 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4319 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4320 if (!rsc || !cmd)
cbd5f69b 4321 goto free_fail;
1da177e4
LT		 4322
4323 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
884f7fba 4324 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
1da177e4 4325 rc = -EFAULT;
cbd5f69b 4326 goto free_fail;
1da177e4 4327 }
1da177e4
LT		 4328 memset(cmd, 0, sizeof(gdth_cmd_str));
4329
1da177e4
LT		 4330 for (i = 0; i < MAX_HDRIVES; ++i) {
4331 if (!ha->hdr[i].present) {
4332 rsc->hdr_list[i].bus = 0xff;
4333 continue;
4334 }
4335 rsc->hdr_list[i].bus = ha->virt_bus;
4336 rsc->hdr_list[i].target = i;
4337 rsc->hdr_list[i].lun = 0;
4338 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4339 if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
4340 cmd->Service = CACHESERVICE;
4341 cmd->OpCode = GDT_CLUST_INFO;
4342 if (ha->cache_feat & GDT_64BIT)
4343 cmd->u.cache64.DeviceNo = i;
4344 else
4345 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4346 if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
4347 rsc->hdr_list[i].cluster_type = cluster_type;
1da177e4
LT		 4348 }
4349 }
cbd5f69b 4350
1da177e4
LT		 4351 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4352 rc = -EFAULT;
4353 else
cbd5f69b 4354 rc = 0;
1da177e4
LT		 4355
4356free_fail:
4357 kfree(rsc);
4358 kfree(cmd);
4359 return rc;
4360}
4361
4362static int ioc_rescan(void __user *arg, char *cmnd)
4363{
4364 gdth_ioctl_rescan *rsc;
4365 gdth_cmd_str *cmd;
4366 ushort i, status, hdr_cnt;
4367 ulong32 info;
45f1a41b 4368 int cyls, hds, secs;
1da177e4
LT		 4369 int rc = -ENOMEM;
4370 ulong flags;
4371 gdth_ha_str *ha;
1da177e4
LT		 4372
4373 rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
4374 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
4375 if (!cmd || !rsc)
cbd5f69b 4376 goto free_fail;
1da177e4
LT		 4377
4378 if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
884f7fba 4379 (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
cbd5f69b
LA		 4380 rc = -EFAULT;
4381 goto free_fail;
1da177e4 4382 }
1da177e4
LT		 4383 memset(cmd, 0, sizeof(gdth_cmd_str));
4384
1da177e4
LT		 4385 if (rsc->flag == 0) {
4386 /* old method: re-init. cache service */
4387 cmd->Service = CACHESERVICE;
4388 if (ha->cache_feat & GDT_64BIT) {
4389 cmd->OpCode = GDT_X_INIT_HOST;
4390 cmd->u.cache64.DeviceNo = LINUX_OS;
4391 } else {
4392 cmd->OpCode = GDT_INIT;
4393 cmd->u.cache.DeviceNo = LINUX_OS;
4394 }
cbd5f69b
LA		 4395
4396 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
1da177e4
LT		 4397 i = 0;
4398 hdr_cnt = (status == S_OK ? (ushort)info : 0);
4399 } else {
4400 i = rsc->hdr_no;
4401 hdr_cnt = i + 1;
4402 }
4403
4404 for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
4405 cmd->Service = CACHESERVICE;
4406 cmd->OpCode = GDT_INFO;
4407 if (ha->cache_feat & GDT_64BIT)
4408 cmd->u.cache64.DeviceNo = i;
4409 else
4410 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4411
4412 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4413
1da177e4
LT		 4414 spin_lock_irqsave(&ha->smp_lock, flags);
4415 rsc->hdr_list[i].bus = ha->virt_bus;
4416 rsc->hdr_list[i].target = i;
4417 rsc->hdr_list[i].lun = 0;
4418 if (status != S_OK) {
4419 ha->hdr[i].present = FALSE;
4420 } else {
4421 ha->hdr[i].present = TRUE;
4422 ha->hdr[i].size = info;
4423 /* evaluate mapping */
4424 ha->hdr[i].size &= ~SECS32;
4425 gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
4426 ha->hdr[i].heads = hds;
4427 ha->hdr[i].secs = secs;
4428 /* round size */
4429 ha->hdr[i].size = cyls * hds * secs;
4430 }
4431 spin_unlock_irqrestore(&ha->smp_lock, flags);
4432 if (status != S_OK)
4433 continue;
4434
4435 /* extended info, if GDT_64BIT, for drives > 2 TB */
4436 /* but we need ha->info2, not yet stored in scp->SCp */
4437
4438 /* devtype, cluster info, R/W attribs */
4439 cmd->Service = CACHESERVICE;
4440 cmd->OpCode = GDT_DEVTYPE;
4441 if (ha->cache_feat & GDT_64BIT)
4442 cmd->u.cache64.DeviceNo = i;
4443 else
4444 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4445
4446 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4447
1da177e4
LT		 4448 spin_lock_irqsave(&ha->smp_lock, flags);
4449 ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
4450 spin_unlock_irqrestore(&ha->smp_lock, flags);
4451
4452 cmd->Service = CACHESERVICE;
4453 cmd->OpCode = GDT_CLUST_INFO;
4454 if (ha->cache_feat & GDT_64BIT)
4455 cmd->u.cache64.DeviceNo = i;
4456 else
4457 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4458
4459 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4460
1da177e4
LT		 4461 spin_lock_irqsave(&ha->smp_lock, flags);
4462 ha->hdr[i].cluster_type =
4463 ((status == S_OK && !shared_access) ? (ushort)info : 0);
4464 spin_unlock_irqrestore(&ha->smp_lock, flags);
4465 rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
4466
4467 cmd->Service = CACHESERVICE;
4468 cmd->OpCode = GDT_RW_ATTRIBS;
4469 if (ha->cache_feat & GDT_64BIT)
4470 cmd->u.cache64.DeviceNo = i;
4471 else
4472 cmd->u.cache.DeviceNo = i;
cbd5f69b
LA		 4473
4474 status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
4475
1da177e4
LT		 4476 spin_lock_irqsave(&ha->smp_lock, flags);
4477 ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
4478 spin_unlock_irqrestore(&ha->smp_lock, flags);
4479 }
1da177e4
LT		 4480
4481 if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
4482 rc = -EFAULT;
4483 else
cbd5f69b 4484 rc = 0;
1da177e4
LT		 4485
4486free_fail:
4487 kfree(rsc);
4488 kfree(cmd);
4489 return rc;
4490}
4491
4492static int gdth_ioctl(struct inode *inode, struct file *filep,
4493 unsigned int cmd, unsigned long arg)
4494{
4495 gdth_ha_str *ha;
4496 Scsi_Cmnd *scp;
4497 ulong flags;
4498 char cmnd[MAX_COMMAND_SIZE];
4499 void __user *argp = (void __user *)arg;
4500
4501 memset(cmnd, 0xff, 12);
4502
4503 TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
4504
4505 switch (cmd) {
4506 case GDTIOCTL_CTRCNT:
4507 {
4508 int cnt = gdth_ctr_count;
4509 if (put_user(cnt, (int __user *)argp))
4510 return -EFAULT;
4511 break;
4512 }
4513
4514 case GDTIOCTL_DRVERS:
4515 {
4516 int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
4517 if (put_user(ver, (int __user *)argp))
4518 return -EFAULT;
4519 break;
4520 }
4521
4522 case GDTIOCTL_OSVERS:
4523 {
4524 gdth_ioctl_osvers osv;
4525
4526 osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
4527 osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
4528 osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
4529 if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
4530 return -EFAULT;
4531 break;
4532 }
4533
4534 case GDTIOCTL_CTRTYPE:
4535 {
4536 gdth_ioctl_ctrtype ctrt;
4537
4538 if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
884f7fba 4539 (NULL == (ha = gdth_find_ha(ctrt.ionode))))
1da177e4 4540 return -EFAULT;
884f7fba 4541
1da177e4
LT		 4542 if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
4543 ctrt.type = (unchar)((ha->stype>>20) - 0x10);
4544 } else {
4545 if (ha->type != GDT_PCIMPR) {
4546 ctrt.type = (unchar)((ha->stype<<4) + 6);
4547 } else {
4548 ctrt.type =
4549 (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
4550 if (ha->stype >= 0x300)
8e9a8a0d 4551 ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
1da177e4
LT		 4552 else
4553 ctrt.ext_type = 0x6000 | ha->stype;
4554 }
8e9a8a0d
JG		 4555 ctrt.device_id = ha->pdev->device;
4556 ctrt.sub_device_id = ha->pdev->subsystem_device;
1da177e4
LT		 4557 }
4558 ctrt.info = ha->brd_phys;
4559 ctrt.oem_id = ha->oem_id;
4560 if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
4561 return -EFAULT;
4562 break;
4563 }
4564
4565 case GDTIOCTL_GENERAL:
4566 return ioc_general(argp, cmnd);
4567
4568 case GDTIOCTL_EVENT:
4569 return ioc_event(argp);
4570
4571 case GDTIOCTL_LOCKDRV:
4572 return ioc_lockdrv(argp);
4573
4574 case GDTIOCTL_LOCKCHN:
4575 {
4576 gdth_ioctl_lockchn lchn;
4577 unchar i, j;
4578
4579 if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
884f7fba 4580 (NULL == (ha = gdth_find_ha(lchn.ionode))))
1da177e4 4581 return -EFAULT;
884f7fba 4582
1da177e4
LT		 4583 i = lchn.channel;
4584 if (i < ha->bus_cnt) {
4585 if (lchn.lock) {
4586 spin_lock_irqsave(&ha->smp_lock, flags);
4587 ha->raw[i].lock = 1;
4588 spin_unlock_irqrestore(&ha->smp_lock, flags);
4589 for (j = 0; j < ha->tid_cnt; ++j) {
45f1a41b
BH		 4590 gdth_wait_completion(ha, i, j);
4591 gdth_stop_timeout(ha, i, j);
1da177e4
LT		 4592 }
4593 } else {
4594 spin_lock_irqsave(&ha->smp_lock, flags);
4595 ha->raw[i].lock = 0;
4596 spin_unlock_irqrestore(&ha->smp_lock, flags);
4597 for (j = 0; j < ha->tid_cnt; ++j) {
45f1a41b
BH		 4598 gdth_start_timeout(ha, i, j);
4599 gdth_next(ha);
1da177e4
LT		 4600 }
4601 }
4602 }
4603 break;
4604 }
4605
4606 case GDTIOCTL_RESCAN:
4607 return ioc_rescan(argp, cmnd);
4608
4609 case GDTIOCTL_HDRLIST:
4610 return ioc_hdrlist(argp, cmnd);
4611
4612 case GDTIOCTL_RESET_BUS:
4613 {
4614 gdth_ioctl_reset res;
45f1a41b 4615 int rval;
1da177e4
LT		 4616
4617 if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
884f7fba 4618 (NULL == (ha = gdth_find_ha(res.ionode))))
1da177e4 4619 return -EFAULT;
1da177e4 4620
bbfbbbc1 4621 scp = kzalloc(sizeof(*scp), GFP_KERNEL);
1da177e4
LT		 4622 if (!scp)
4623 return -ENOMEM;
cbd5f69b 4624 scp->device = ha->sdev;
1da177e4
LT		 4625 scp->cmd_len = 12;
4626 scp->use_sg = 0;
52759e6a 4627 scp->device->channel = res.number;
1da177e4
LT		 4628 rval = gdth_eh_bus_reset(scp);
4629 res.status = (rval == SUCCESS ? S_OK : S_GENERR);
cbd5f69b 4630 kfree(scp);
8d7a5da4 4631
1da177e4
LT		 4632 if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
4633 return -EFAULT;
4634 break;
4635 }
4636
4637 case GDTIOCTL_RESET_DRV:
4638 return ioc_resetdrv(argp, cmnd);
4639
4640 default:
4641 break;
4642 }
4643 return 0;
4644}
4645
4646
4647/* flush routine */
45f1a41b 4648static void gdth_flush(gdth_ha_str *ha)
1da177e4
LT		 4649{
4650 int i;
1da177e4 4651 gdth_cmd_str gdtcmd;
1da177e4
LT		 4652 char cmnd[MAX_COMMAND_SIZE];
4653 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4654
45f1a41b 4655 TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
1da177e4 4656
1da177e4
LT		 4657 for (i = 0; i < MAX_HDRIVES; ++i) {
4658 if (ha->hdr[i].present) {
4659 gdtcmd.BoardNode = LOCALBOARD;
4660 gdtcmd.Service = CACHESERVICE;
4661 gdtcmd.OpCode = GDT_FLUSH;
4662 if (ha->cache_feat & GDT_64BIT) {
4663 gdtcmd.u.cache64.DeviceNo = i;
4664 gdtcmd.u.cache64.BlockNo = 1;
4665 gdtcmd.u.cache64.sg_canz = 0;
4666 } else {
4667 gdtcmd.u.cache.DeviceNo = i;
4668 gdtcmd.u.cache.BlockNo = 1;
4669 gdtcmd.u.cache.sg_canz = 0;
4670 }
45f1a41b 4671 TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
cbd5f69b 4672
45f1a41b 4673 gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
1da177e4
LT		 4674 }
4675 }
1da177e4
LT		 4676}
4677
4678/* shutdown routine */
4679static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
4680{
884f7fba 4681 gdth_ha_str *ha;
1da177e4
LT		 4682#ifndef __alpha__
4683 gdth_cmd_str gdtcmd;
1da177e4
LT		 4684 char cmnd[MAX_COMMAND_SIZE];
4685#endif
4686
e041c683 4687 if (notifier_disabled)
cbd5f69b 4688 return NOTIFY_OK;
e041c683 4689
1da177e4
LT		 4690 TRACE2(("gdth_halt() event %d\n",(int)event));
4691 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
4692 return NOTIFY_DONE;
4693
e041c683 4694 notifier_disabled = 1;
1da177e4 4695 printk("GDT-HA: Flushing all host drives .. ");
884f7fba 4696 list_for_each_entry(ha, &gdth_instances, list) {
45f1a41b 4697 gdth_flush(ha);
1da177e4
LT		 4698
4699#ifndef __alpha__
4700 /* controller reset */
4701 memset(cmnd, 0xff, MAX_COMMAND_SIZE);
4702 gdtcmd.BoardNode = LOCALBOARD;
4703 gdtcmd.Service = CACHESERVICE;
4704 gdtcmd.OpCode = GDT_RESET;
45f1a41b
BH		 4705 TRACE2(("gdth_halt(): reset controller %d\n", ha->hanum));
4706 gdth_execute(ha->shost, &gdtcmd, cmnd, 10, NULL);
1da177e4
LT		 4707#endif
4708 }
4709 printk("Done.\n");
4710
4711#ifdef GDTH_STATISTICS
4712 del_timer(&gdth_timer);
4713#endif
1da177e4
LT		 4714 return NOTIFY_OK;
4715}
4716
cbd5f69b
LA		 4717/* configure lun */
4718static int gdth_slave_configure(struct scsi_device *sdev)
4719{
4720 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4721 sdev->skip_ms_page_3f = 1;
4722 sdev->skip_ms_page_8 = 1;
4723 return 0;
4724}
cbd5f69b 4725
835cc24a 4726static struct scsi_host_template gdth_template = {
1da177e4 4727 .name = "GDT SCSI Disk Array Controller",
1da177e4
LT		 4728 .info = gdth_info,
4729 .queuecommand = gdth_queuecommand,
1da177e4 4730 .eh_bus_reset_handler = gdth_eh_bus_reset,
69916b7c 4731 .slave_configure = gdth_slave_configure,
1da177e4 4732 .bios_param = gdth_bios_param,
69916b7c
JG		 4733 .proc_info = gdth_proc_info,
4734 .proc_name = "gdth",
1da177e4
LT		 4735 .can_queue = GDTH_MAXCMDS,
4736 .this_id = -1,
4737 .sg_tablesize = GDTH_MAXSG,
4738 .cmd_per_lun = GDTH_MAXC_P_L,
4739 .unchecked_isa_dma = 1,
4740 .use_clustering = ENABLE_CLUSTERING,
1da177e4
LT		 4741};
4742
aed91cb5 4743#ifdef CONFIG_ISA
835cc24a 4744static int gdth_isa_probe_one(ulong32 isa_bios)
aed91cb5
CH		 4745{
4746 struct Scsi_Host *shp;
4747 gdth_ha_str *ha;
4748 dma_addr_t scratch_dma_handle = 0;
884f7fba 4749 int error, i;
aed91cb5
CH		 4750
4751 if (!gdth_search_isa(isa_bios))
4752 return -ENXIO;
4753
835cc24a 4754 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
aed91cb5
CH		 4755 if (!shp)
4756 return -ENOMEM;
45f1a41b 4757 ha = shost_priv(shp);
aed91cb5
CH		 4758
4759 error = -ENODEV;
4760 if (!gdth_init_isa(isa_bios,ha))
4761 goto out_host_put;
4762
4763 /* controller found and initialized */
4764 printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
4765 isa_bios, ha->irq, ha->drq);
4766
4767 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4768 if (error) {
4769 printk("GDT-ISA: Unable to allocate IRQ\n");
4770 goto out_host_put;
4771 }
4772
4773 error = request_dma(ha->drq, "gdth");
4774 if (error) {
4775 printk("GDT-ISA: Unable to allocate DMA channel\n");
4776 goto out_free_irq;
4777 }
4778
4779 set_dma_mode(ha->drq,DMA_MODE_CASCADE);
4780 enable_dma(ha->drq);
4781 shp->unchecked_isa_dma = 1;
4782 shp->irq = ha->irq;
4783 shp->dma_channel = ha->drq;
aed91cb5 4784
884f7fba 4785 ha->hanum = gdth_ctr_count++;
45f1a41b 4786 ha->shost = shp;
aed91cb5 4787
45f1a41b 4788 ha->pccb = &ha->cmdext;
aed91cb5
CH		 4789 ha->ccb_phys = 0L;
4790 ha->pdev = NULL;
4791
4792 error = -ENOMEM;
4793
4794 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4795 &scratch_dma_handle);
4796 if (!ha->pscratch)
4797 goto out_dec_counters;
4798 ha->scratch_phys = scratch_dma_handle;
4799
4800 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4801 &scratch_dma_handle);
4802 if (!ha->pmsg)
4803 goto out_free_pscratch;
4804 ha->msg_phys = scratch_dma_handle;
4805
4806#ifdef INT_COAL
4807 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4808 sizeof(gdth_coal_status) * MAXOFFSETS,
4809 &scratch_dma_handle);
4810 if (!ha->coal_stat)
4811 goto out_free_pmsg;
4812 ha->coal_stat_phys = scratch_dma_handle;
4813#endif
4814
4815 ha->scratch_busy = FALSE;
4816 ha->req_first = NULL;
4817 ha->tid_cnt = MAX_HDRIVES;
4818 if (max_ids > 0 && max_ids < ha->tid_cnt)
4819 ha->tid_cnt = max_ids;
4820 for (i = 0; i < GDTH_MAXCMDS; ++i)
4821 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4822 ha->scan_mode = rescan ? 0x10 : 0;
4823
4824 error = -ENODEV;
45f1a41b 4825 if (!gdth_search_drives(ha)) {
aed91cb5
CH		 4826 printk("GDT-ISA: Error during device scan\n");
4827 goto out_free_coal_stat;
4828 }
4829
4830 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4831 hdr_channel = ha->bus_cnt;
4832 ha->virt_bus = hdr_channel;
4833
4834 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4835 shp->max_cmd_len = 16;
4836
4837 shp->max_id = ha->tid_cnt;
4838 shp->max_lun = MAXLUN;
52759e6a 4839 shp->max_channel = ha->bus_cnt;
aed91cb5
CH		 4840
4841 spin_lock_init(&ha->smp_lock);
45f1a41b 4842 gdth_enable_int(ha);
aed91cb5 4843
835cc24a
CH		 4844 error = scsi_add_host(shp, NULL);
4845 if (error)
4846 goto out_free_coal_stat;
4847 list_add_tail(&ha->list, &gdth_instances);
aed91cb5
CH		 4848 return 0;
4849
4850 out_free_coal_stat:
4851#ifdef INT_COAL
4852 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4853 ha->coal_stat, ha->coal_stat_phys);
4854 out_free_pmsg:
4855#endif
4856 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4857 ha->pmsg, ha->msg_phys);
4858 out_free_pscratch:
4859 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4860 ha->pscratch, ha->scratch_phys);
4861 out_dec_counters:
4862 gdth_ctr_count--;
aed91cb5
CH		 4863 out_free_irq:
4864 free_irq(ha->irq, ha);
4865 out_host_put:
835cc24a 4866 scsi_host_put(shp);
aed91cb5
CH		 4867 return error;
4868}
4869#endif /* CONFIG_ISA */
4870
706a5d45 4871#ifdef CONFIG_EISA
835cc24a 4872static int gdth_eisa_probe_one(ushort eisa_slot)
706a5d45
CH		 4873{
4874 struct Scsi_Host *shp;
4875 gdth_ha_str *ha;
4876 dma_addr_t scratch_dma_handle = 0;
884f7fba 4877 int error, i;
706a5d45
CH		 4878
4879 if (!gdth_search_eisa(eisa_slot))
4880 return -ENXIO;
4881
835cc24a 4882 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
706a5d45
CH		 4883 if (!shp)
4884 return -ENOMEM;
45f1a41b 4885 ha = shost_priv(shp);
706a5d45
CH		 4886
4887 error = -ENODEV;
4888 if (!gdth_init_eisa(eisa_slot,ha))
4889 goto out_host_put;
4890
4891 /* controller found and initialized */
4892 printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
4893 eisa_slot >> 12, ha->irq);
4894
4895 error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
4896 if (error) {
4897 printk("GDT-EISA: Unable to allocate IRQ\n");
4898 goto out_host_put;
4899 }
4900
4901 shp->unchecked_isa_dma = 0;
4902 shp->irq = ha->irq;
4903 shp->dma_channel = 0xff;
706a5d45 4904
884f7fba 4905 ha->hanum = gdth_ctr_count++;
45f1a41b
BH		 4906 ha->shost = shp;
4907
4908 TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
706a5d45 4909
45f1a41b 4910 ha->pccb = &ha->cmdext;
706a5d45
CH		 4911 ha->ccb_phys = 0L;
4912
4913 error = -ENOMEM;
4914
4915 ha->pdev = NULL;
4916 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
4917 &scratch_dma_handle);
4918 if (!ha->pscratch)
4919 goto out_free_irq;
4920 ha->scratch_phys = scratch_dma_handle;
4921
4922 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
4923 &scratch_dma_handle);
4924 if (!ha->pmsg)
4925 goto out_free_pscratch;
4926 ha->msg_phys = scratch_dma_handle;
4927
4928#ifdef INT_COAL
4929 ha->coal_stat = pci_alloc_consistent(ha->pdev,
4930 sizeof(gdth_coal_status) * MAXOFFSETS,
4931 &scratch_dma_handle);
4932 if (!ha->coal_stat)
4933 goto out_free_pmsg;
4934 ha->coal_stat_phys = scratch_dma_handle;
4935#endif
4936
4937 ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
4938 sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
4939 if (!ha->ccb_phys)
4940 goto out_free_coal_stat;
4941
4942 ha->scratch_busy = FALSE;
4943 ha->req_first = NULL;
4944 ha->tid_cnt = MAX_HDRIVES;
4945 if (max_ids > 0 && max_ids < ha->tid_cnt)
4946 ha->tid_cnt = max_ids;
4947 for (i = 0; i < GDTH_MAXCMDS; ++i)
4948 ha->cmd_tab[i].cmnd = UNUSED_CMND;
4949 ha->scan_mode = rescan ? 0x10 : 0;
4950
45f1a41b 4951 if (!gdth_search_drives(ha)) {
706a5d45
CH		 4952 printk("GDT-EISA: Error during device scan\n");
4953 error = -ENODEV;
4954 goto out_free_ccb_phys;
4955 }
4956
4957 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
4958 hdr_channel = ha->bus_cnt;
4959 ha->virt_bus = hdr_channel;
4960
4961 if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
4962 shp->max_cmd_len = 16;
4963
4964 shp->max_id = ha->tid_cnt;
4965 shp->max_lun = MAXLUN;
52759e6a 4966 shp->max_channel = ha->bus_cnt;
706a5d45
CH		 4967
4968 spin_lock_init(&ha->smp_lock);
45f1a41b 4969 gdth_enable_int(ha);
835cc24a
CH		 4970
4971 error = scsi_add_host(shp, NULL);
4972 if (error)
4973 goto out_free_coal_stat;
4974 list_add_tail(&ha->list, &gdth_instances);
706a5d45
CH		 4975 return 0;
4976
4977 out_free_ccb_phys:
4978 pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
4979 PCI_DMA_BIDIRECTIONAL);
4980 out_free_coal_stat:
4981#ifdef INT_COAL
4982 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
4983 ha->coal_stat, ha->coal_stat_phys);
4984 out_free_pmsg:
4985#endif
4986 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
4987 ha->pmsg, ha->msg_phys);
4988 out_free_pscratch:
4989 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
4990 ha->pscratch, ha->scratch_phys);
4991 out_free_irq:
4992 free_irq(ha->irq, ha);
4993 gdth_ctr_count--;
706a5d45 4994 out_host_put:
835cc24a 4995 scsi_host_put(shp);
706a5d45
CH		 4996 return error;
4997}
4998#endif /* CONFIG_EISA */
aed91cb5 4999
8514ef27 5000#ifdef CONFIG_PCI
835cc24a 5001static int gdth_pci_probe_one(gdth_pci_str *pcistr, int ctr)
8514ef27
CH		 5002{
5003 struct Scsi_Host *shp;
5004 gdth_ha_str *ha;
5005 dma_addr_t scratch_dma_handle = 0;
884f7fba 5006 int error, i;
8514ef27 5007
835cc24a 5008 shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
8514ef27
CH		 5009 if (!shp)
5010 return -ENOMEM;
45f1a41b 5011 ha = shost_priv(shp);
8514ef27
CH		 5012
5013 error = -ENODEV;
5014 if (!gdth_init_pci(&pcistr[ctr],ha))
5015 goto out_host_put;
5016
5017 /* controller found and initialized */
5018 printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
5019 pcistr[ctr].pdev->bus->number,
5020 PCI_SLOT(pcistr[ctr].pdev->devfn),
5021 ha->irq);
5022
5023 error = request_irq(ha->irq, gdth_interrupt,
5024 IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
5025 if (error) {
5026 printk("GDT-PCI: Unable to allocate IRQ\n");
5027 goto out_host_put;
5028 }
5029
5030 shp->unchecked_isa_dma = 0;
5031 shp->irq = ha->irq;
5032 shp->dma_channel = 0xff;
8514ef27 5033
884f7fba 5034 ha->hanum = gdth_ctr_count++;
45f1a41b 5035 ha->shost = shp;
8514ef27 5036
45f1a41b 5037 ha->pccb = &ha->cmdext;
8514ef27
CH		 5038 ha->ccb_phys = 0L;
5039
5040 error = -ENOMEM;
5041
5042 ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
5043 &scratch_dma_handle);
5044 if (!ha->pscratch)
5045 goto out_free_irq;
5046 ha->scratch_phys = scratch_dma_handle;
5047
5048 ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
5049 &scratch_dma_handle);
5050 if (!ha->pmsg)
5051 goto out_free_pscratch;
5052 ha->msg_phys = scratch_dma_handle;
5053
5054#ifdef INT_COAL
5055 ha->coal_stat = pci_alloc_consistent(ha->pdev,
5056 sizeof(gdth_coal_status) * MAXOFFSETS,
5057 &scratch_dma_handle);
5058 if (!ha->coal_stat)
5059 goto out_free_pmsg;
5060 ha->coal_stat_phys = scratch_dma_handle;
5061#endif
5062
5063 ha->scratch_busy = FALSE;
5064 ha->req_first = NULL;
5065 ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
5066 if (max_ids > 0 && max_ids < ha->tid_cnt)
5067 ha->tid_cnt = max_ids;
5068 for (i = 0; i < GDTH_MAXCMDS; ++i)
5069 ha->cmd_tab[i].cmnd = UNUSED_CMND;
5070 ha->scan_mode = rescan ? 0x10 : 0;
5071
5072 error = -ENODEV;
45f1a41b
BH		 5073 if (!gdth_search_drives(ha)) {
5074 printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
8514ef27
CH		 5075 goto out_free_coal_stat;
5076 }
5077
5078 if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
5079 hdr_channel = ha->bus_cnt;
5080 ha->virt_bus = hdr_channel;
5081
5082 /* 64-bit DMA only supported from FW >= x.43 */
5083 if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
5084 !ha->dma64_support) {
5085 if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
5086 printk(KERN_WARNING "GDT-PCI %d: "
45f1a41b 5087 "Unable to set 32-bit DMA\n", ha->hanum);
8514ef27
CH		 5088 goto out_free_coal_stat;
5089 }
5090 } else {
5091 shp->max_cmd_len = 16;
5092 if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
45f1a41b 5093 printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
8514ef27
CH		 5094 } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
5095 printk(KERN_WARNING "GDT-PCI %d: "
45f1a41b 5096 "Unable to set 64/32-bit DMA\n", ha->hanum);
8514ef27
CH		 5097 goto out_free_coal_stat;
5098 }
5099 }
5100
5101 shp->max_id = ha->tid_cnt;
5102 shp->max_lun = MAXLUN;
52759e6a 5103 shp->max_channel = ha->bus_cnt;
8514ef27
CH		 5104
5105 spin_lock_init(&ha->smp_lock);
45f1a41b 5106 gdth_enable_int(ha);
835cc24a
CH		 5107
5108 error = scsi_add_host(shp, &pcistr[ctr].pdev->dev);
5109 if (error)
5110 goto out_free_coal_stat;
5111 list_add_tail(&ha->list, &gdth_instances);
8514ef27
CH		 5112 return 0;
5113
5114 out_free_coal_stat:
5115#ifdef INT_COAL
5116 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
5117 ha->coal_stat, ha->coal_stat_phys);
5118 out_free_pmsg:
5119#endif
5120 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5121 ha->pmsg, ha->msg_phys);
5122 out_free_pscratch:
5123 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5124 ha->pscratch, ha->scratch_phys);
5125 out_free_irq:
5126 free_irq(ha->irq, ha);
5127 gdth_ctr_count--;
8514ef27 5128 out_host_put:
835cc24a 5129 scsi_host_put(shp);
8514ef27
CH		 5130 return error;
5131}
5132#endif /* CONFIG_PCI */
5133
835cc24a
CH		 5134static void gdth_remove_one(gdth_ha_str *ha)
5135{
5136 struct Scsi_Host *shp = ha->shost;
5137
5138 TRACE2(("gdth_remove_one()\n"));
5139
5140 scsi_remove_host(shp);
5141
5142 if (ha->sdev) {
5143 scsi_free_host_dev(ha->sdev);
5144 ha->sdev = NULL;
5145 }
5146
5147 gdth_flush(ha);
5148
5149 if (shp->irq)
5150 free_irq(shp->irq,ha);
5151
5152#ifdef CONFIG_ISA
5153 if (shp->dma_channel != 0xff)
5154 free_dma(shp->dma_channel);
5155#endif
5156#ifdef INT_COAL
5157 if (ha->coal_stat)
5158 pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
5159 MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
5160#endif
5161 if (ha->pscratch)
5162 pci_free_consistent(ha->pdev, GDTH_SCRATCH,
5163 ha->pscratch, ha->scratch_phys);
5164 if (ha->pmsg)
5165 pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
5166 ha->pmsg, ha->msg_phys);
5167 if (ha->ccb_phys)
5168 pci_unmap_single(ha->pdev,ha->ccb_phys,
5169 sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
5170
5171 scsi_host_put(shp);
5172}
5173
5174static int __init gdth_init(void)
5175{
5176 if (disable) {
5177 printk("GDT-HA: Controller driver disabled from"
5178 " command line !\n");
5179 return 0;
5180 }
5181
5182 printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
5183 GDTH_VERSION_STR);
5184
5185 /* initializations */
5186 gdth_polling = TRUE;
5187 gdth_clear_events();
5188
5189 /* As default we do not probe for EISA or ISA controllers */
5190 if (probe_eisa_isa) {
5191 /* scanning for controllers, at first: ISA controller */
5192#ifdef CONFIG_ISA
5193 ulong32 isa_bios;
5194 for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
884f7fba 5195 isa_bios += 0x8000UL)
835cc24a 5196 gdth_isa_probe_one(isa_bios);
835cc24a
CH		 5197#endif
5198#ifdef CONFIG_EISA
5199 {
5200 ushort eisa_slot;
5201 for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
884f7fba 5202 eisa_slot += 0x1000)
835cc24a 5203 gdth_eisa_probe_one(eisa_slot);
835cc24a
CH		 5204 }
5205#endif
5206 }
5207
5208#ifdef CONFIG_PCI
5209 /* scanning for PCI controllers */
5210 {
5211 gdth_pci_str pcistr[MAXHA];
5212 int cnt,ctr;
5213
5214 cnt = gdth_search_pci(pcistr);
5215 printk("GDT-HA: Found %d PCI Storage RAID Controllers\n", cnt);
5216 gdth_sort_pci(pcistr,cnt);
884f7fba 5217 for (ctr = 0; ctr < cnt; ++ctr)
835cc24a 5218 gdth_pci_probe_one(pcistr, ctr);
835cc24a
CH		 5219 }
5220#endif /* CONFIG_PCI */
5221
5222 TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
5223#ifdef GDTH_STATISTICS
5224 TRACE2(("gdth_detect(): Initializing timer !\n"));
5225 init_timer(&gdth_timer);
5226 gdth_timer.expires = jiffies + HZ;
5227 gdth_timer.data = 0L;
5228 gdth_timer.function = gdth_timeout;
5229 add_timer(&gdth_timer);
5230#endif
5231 major = register_chrdev(0,"gdth", &gdth_fops);
5232 notifier_disabled = 0;
5233 register_reboot_notifier(&gdth_notifier);
5234 gdth_polling = FALSE;
5235 return 0;
5236}
5237
5238static void __exit gdth_exit(void)
5239{
5240 gdth_ha_str *ha;
5241
5242 list_for_each_entry(ha, &gdth_instances, list)
5243 gdth_remove_one(ha);
5244
5245#ifdef GDTH_STATISTICS
5246 del_timer(&gdth_timer);
5247#endif
5248 unregister_chrdev(major,"gdth");
5249 unregister_reboot_notifier(&gdth_notifier);
5250}
5251
5252module_init(gdth_init);
5253module_exit(gdth_exit);
5254
1da177e4
LT		 5255#ifndef MODULE
5256__setup("gdth=", option_setup);
5257#endif
kernel source for telekom puls (alcatel/mediatek)