projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / csiostor / csio_hw.h
CommitLineData
a3667aae
NKI		 1/*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef __CSIO_HW_H__
36#define __CSIO_HW_H__
37
38#include <linux/kernel.h>
39#include <linux/pci.h>
40#include <linux/device.h>
41#include <linux/workqueue.h>
42#include <linux/compiler.h>
43#include <linux/cdev.h>
44#include <linux/list.h>
45#include <linux/mempool.h>
46#include <linux/io.h>
47#include <linux/spinlock_types.h>
48#include <scsi/scsi_device.h>
49#include <scsi/scsi_transport_fc.h>
50
51#include "csio_wr.h"
52#include "csio_mb.h"
53#include "csio_scsi.h"
54#include "csio_defs.h"
55#include "t4_regs.h"
56#include "t4_msg.h"
57
58/*
59 * An error value used by host. Should not clash with FW defined return values.
60 */
61#define FW_HOSTERROR 255
62
63#define CSIO_FW_FNAME "cxgb4/t4fw.bin"
64#define CSIO_CF_FNAME "cxgb4/t4-config.txt"
65
66#define FW_VERSION_MAJOR 1
67#define FW_VERSION_MINOR 2
68#define FW_VERSION_MICRO 8
69
70#define CSIO_HW_NAME "Chelsio FCoE Adapter"
71#define CSIO_MAX_PFN 8
72#define CSIO_MAX_PPORTS 4
73
74#define CSIO_MAX_LUN 0xFFFF
75#define CSIO_MAX_QUEUE 2048
76#define CSIO_MAX_CMD_PER_LUN 32
77#define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024)
78#define CSIO_MAX_SECTOR_SIZE 128
79
80/* Interrupts */
81#define CSIO_EXTRA_MSI_IQS 2 /* Extra iqs for INTX/MSI mode
82 * (Forward intr iq + fw iq) */
83#define CSIO_EXTRA_VECS 2 /* non-data + FW evt */
84#define CSIO_MAX_SCSI_CPU 128
85#define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS)
86#define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS)
87
88/* Queues */
89enum {
90 CSIO_INTR_WRSIZE = 128,
91 CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE),
92 CSIO_FWEVT_WRSIZE = 128,
93 CSIO_FWEVT_IQLEN = 128,
94 CSIO_FWEVT_FLBUFS = 64,
95 CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN),
96 CSIO_HW_NIQ = 1,
97 CSIO_HW_NFLQ = 1,
98 CSIO_HW_NEQ = 1,
99 CSIO_HW_NINTXQ = 1,
100};
101
102struct csio_msix_entries {
103 unsigned short vector; /* Vector assigned by pci_enable_msix */
104 void *dev_id; /* Priv object associated w/ this msix*/
105 char desc[24]; /* Description of this vector */
106};
107
108struct csio_scsi_qset {
109 int iq_idx; /* Ingress index */
110 int eq_idx; /* Egress index */
111 uint32_t intr_idx; /* MSIX Vector index */
112};
113
114struct csio_scsi_cpu_info {
115 int16_t max_cpus;
116};
117
118extern int csio_dbg_level;
119extern int csio_force_master;
120extern unsigned int csio_port_mask;
121extern int csio_msi;
122
123#define CSIO_VENDOR_ID 0x1425
124#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
125#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
126#define CSIO_FPGA 0xA000
127#define CSIO_T4_FCOE_ASIC 0x4600
128
129#define CSIO_GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
130 EDC1 | LE | TP | MA | PM_TX | PM_RX | \
131 ULP_RX | CPL_SWITCH | SGE | \
132 ULP_TX | SF)
133
134/*
135 * Hard parameters used to initialize the card in the absence of a
136 * configuration file.
137 */
138enum {
139 /* General */
140 CSIO_SGE_DBFIFO_INT_THRESH = 10,
141
142 CSIO_SGE_RX_DMA_OFFSET = 2,
143
144 CSIO_SGE_FLBUF_SIZE1 = 65536,
145 CSIO_SGE_FLBUF_SIZE2 = 1536,
146 CSIO_SGE_FLBUF_SIZE3 = 9024,
147 CSIO_SGE_FLBUF_SIZE4 = 9216,
148 CSIO_SGE_FLBUF_SIZE5 = 2048,
149 CSIO_SGE_FLBUF_SIZE6 = 128,
150 CSIO_SGE_FLBUF_SIZE7 = 8192,
151 CSIO_SGE_FLBUF_SIZE8 = 16384,
152
153 CSIO_SGE_TIMER_VAL_0 = 5,
154 CSIO_SGE_TIMER_VAL_1 = 10,
155 CSIO_SGE_TIMER_VAL_2 = 20,
156 CSIO_SGE_TIMER_VAL_3 = 50,
157 CSIO_SGE_TIMER_VAL_4 = 100,
158 CSIO_SGE_TIMER_VAL_5 = 200,
159
160 CSIO_SGE_INT_CNT_VAL_0 = 1,
161 CSIO_SGE_INT_CNT_VAL_1 = 4,
162 CSIO_SGE_INT_CNT_VAL_2 = 8,
163 CSIO_SGE_INT_CNT_VAL_3 = 16,
164
165 /* Storage specific - used by FW_PFVF_CMD */
166 CSIO_WX_CAPS = FW_CMD_CAP_PF, /* w/x all */
167 CSIO_R_CAPS = FW_CMD_CAP_PF, /* r all */
168 CSIO_NVI = 4,
169 CSIO_NIQ_FLINT = 34,
170 CSIO_NETH_CTRL = 32,
171 CSIO_NEQ = 66,
172 CSIO_NEXACTF = 32,
173 CSIO_CMASK = FW_PFVF_CMD_CMASK_MASK,
174 CSIO_PMASK = FW_PFVF_CMD_PMASK_MASK,
175};
176
177/* Slowpath events */
178enum csio_evt {
179 CSIO_EVT_FW = 0, /* FW event */
180 CSIO_EVT_MBX, /* MBX event */
181 CSIO_EVT_SCN, /* State change notification */
182 CSIO_EVT_DEV_LOSS, /* Device loss event */
183 CSIO_EVT_MAX, /* Max supported event */
184};
185
186#define CSIO_EVT_MSG_SIZE 512
187#define CSIO_EVTQ_SIZE 512
188
189/* Event msg */
190struct csio_evt_msg {
191 struct list_head list; /* evt queue*/
192 enum csio_evt type;
193 uint8_t data[CSIO_EVT_MSG_SIZE];
194};
195
196enum {
197 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
198 SERNUM_LEN = 16, /* Serial # length */
199 EC_LEN = 16, /* E/C length */
200 ID_LEN = 16, /* ID length */
201 TRACE_LEN = 112, /* length of trace data and mask */
202};
203
204enum {
205 SF_PAGE_SIZE = 256, /* serial flash page size */
206 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
207 SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
208};
209
210enum { MEM_EDC0, MEM_EDC1, MEM_MC };
211
212enum {
213 MEMWIN0_APERTURE = 2048,
214 MEMWIN0_BASE = 0x1b800,
215 MEMWIN1_APERTURE = 32768,
216 MEMWIN1_BASE = 0x28000,
217 MEMWIN2_APERTURE = 65536,
218 MEMWIN2_BASE = 0x30000,
219};
220
221/* serial flash and firmware constants */
222enum {
223 SF_ATTEMPTS = 10, /* max retries for SF operations */
224
225 /* flash command opcodes */
226 SF_PROG_PAGE = 2, /* program page */
227 SF_WR_DISABLE = 4, /* disable writes */
228 SF_RD_STATUS = 5, /* read status register */
229 SF_WR_ENABLE = 6, /* enable writes */
230 SF_RD_DATA_FAST = 0xb, /* read flash */
231 SF_RD_ID = 0x9f, /* read ID */
232 SF_ERASE_SECTOR = 0xd8, /* erase sector */
233
234 FW_START_SEC = 8, /* first flash sector for FW */
235 FW_END_SEC = 15, /* last flash sector for FW */
236 FW_IMG_START = FW_START_SEC * SF_SEC_SIZE,
237 FW_MAX_SIZE = (FW_END_SEC - FW_START_SEC + 1) * SF_SEC_SIZE,
238
239 FLASH_CFG_MAX_SIZE = 0x10000 , /* max size of the flash config file*/
240 FLASH_CFG_OFFSET = 0x1f0000,
241 FLASH_CFG_START_SEC = FLASH_CFG_OFFSET / SF_SEC_SIZE,
242 FPGA_FLASH_CFG_OFFSET = 0xf0000 , /* if FPGA mode, then cfg file is
243 * at 1MB - 64KB */
244 FPGA_FLASH_CFG_START_SEC = FPGA_FLASH_CFG_OFFSET / SF_SEC_SIZE,
245};
246
247/*
248 * Flash layout.
249 */
250#define FLASH_START(start) ((start) * SF_SEC_SIZE)
251#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
252
253enum {
254 /*
255 * Location of firmware image in FLASH.
256 */
257 FLASH_FW_START_SEC = 8,
258 FLASH_FW_NSECS = 8,
259 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
260 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
261
262};
263
264#undef FLASH_START
265#undef FLASH_MAX_SIZE
266
267/* Management module */
268enum {
269 CSIO_MGMT_EQ_WRSIZE = 512,
270 CSIO_MGMT_IQ_WRSIZE = 128,
271 CSIO_MGMT_EQLEN = 64,
272 CSIO_MGMT_IQLEN = 64,
273};
274
275#define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE)
276#define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE)
277
278/* mgmt module stats */
279struct csio_mgmtm_stats {
280 uint32_t n_abort_req; /* Total abort request */
281 uint32_t n_abort_rsp; /* Total abort response */
282 uint32_t n_close_req; /* Total close request */
283 uint32_t n_close_rsp; /* Total close response */
284 uint32_t n_err; /* Total Errors */
285 uint32_t n_drop; /* Total request dropped */
286 uint32_t n_active; /* Count of active_q */
287 uint32_t n_cbfn; /* Count of cbfn_q */
288};
289
290/* MGMT module */
291struct csio_mgmtm {
292 struct csio_hw *hw; /* Pointer to HW moduel */
293 int eq_idx; /* Egress queue index */
294 int iq_idx; /* Ingress queue index */
295 int msi_vec; /* MSI vector */
296 struct list_head active_q; /* Outstanding ELS/CT */
297 struct list_head abort_q; /* Outstanding abort req */
298 struct list_head cbfn_q; /* Completion queue */
299 struct list_head mgmt_req_freelist; /* Free poll of reqs */
300 /* ELSCT request freelist*/
301 struct timer_list mgmt_timer; /* MGMT timer */
302 struct csio_mgmtm_stats stats; /* ELS/CT stats */
303};
304
305struct csio_adap_desc {
306 char model_no[16];
307 char description[32];
308};
309
310struct pci_params {
311 uint16_t vendor_id;
312 uint16_t device_id;
313 uint32_t vpd_cap_addr;
314 uint16_t speed;
315 uint8_t width;
316};
317
318/* User configurable hw parameters */
319struct csio_hw_params {
320 uint32_t sf_size; /* serial flash
321 * size in bytes
322 */
323 uint32_t sf_nsec; /* # of flash sectors */
324 struct pci_params pci;
325 uint32_t log_level; /* Module-level for
326 * debug log.
327 */
328};
329
330struct csio_vpd {
331 uint32_t cclk;
332 uint8_t ec[EC_LEN + 1];
333 uint8_t sn[SERNUM_LEN + 1];
334 uint8_t id[ID_LEN + 1];
335};
336
337struct csio_pport {
338 uint16_t pcap;
339 uint8_t portid;
340 uint8_t link_status;
341 uint16_t link_speed;
342 uint8_t mac[6];
343 uint8_t mod_type;
344 uint8_t rsvd1;
345 uint8_t rsvd2;
346 uint8_t rsvd3;
347};
348
349/* fcoe resource information */
350struct csio_fcoe_res_info {
351 uint16_t e_d_tov;
352 uint16_t r_a_tov_seq;
353 uint16_t r_a_tov_els;
354 uint16_t r_r_tov;
355 uint32_t max_xchgs;
356 uint32_t max_ssns;
357 uint32_t used_xchgs;
358 uint32_t used_ssns;
359 uint32_t max_fcfs;
360 uint32_t max_vnps;
361 uint32_t used_fcfs;
362 uint32_t used_vnps;
363};
364
365/* HW State machine Events */
366enum csio_hw_ev {
367 CSIO_HWE_CFG = (uint32_t)1, /* Starts off the State machine */
368 CSIO_HWE_INIT, /* Config done, start Init */
369 CSIO_HWE_INIT_DONE, /* Init Mailboxes sent, HW ready */
370 CSIO_HWE_FATAL, /* Fatal error during initialization */
371 CSIO_HWE_PCIERR_DETECTED,/* PCI error recovery detetced */
372 CSIO_HWE_PCIERR_SLOT_RESET, /* Slot reset after PCI recoviery */
373 CSIO_HWE_PCIERR_RESUME, /* Resume after PCI error recovery */
374 CSIO_HWE_QUIESCED, /* HBA quiesced */
375 CSIO_HWE_HBA_RESET, /* HBA reset requested */
376 CSIO_HWE_HBA_RESET_DONE, /* HBA reset completed */
377 CSIO_HWE_FW_DLOAD, /* FW download requested */
378 CSIO_HWE_PCI_REMOVE, /* PCI de-instantiation */
379 CSIO_HWE_SUSPEND, /* HW suspend for Online(hot) replacement */
380 CSIO_HWE_RESUME, /* HW resume for Online(hot) replacement */
381 CSIO_HWE_MAX, /* Max HW event */
382};
383
384/* hw stats */
385struct csio_hw_stats {
386 uint32_t n_evt_activeq; /* Number of event in active Q */
387 uint32_t n_evt_freeq; /* Number of event in free Q */
388 uint32_t n_evt_drop; /* Number of event droped */
389 uint32_t n_evt_unexp; /* Number of unexpected events */
390 uint32_t n_pcich_offline;/* Number of pci channel offline */
391 uint32_t n_lnlkup_miss; /* Number of lnode lookup miss */
392 uint32_t n_cpl_fw6_msg; /* Number of cpl fw6 message*/
393 uint32_t n_cpl_fw6_pld; /* Number of cpl fw6 payload*/
394 uint32_t n_cpl_unexp; /* Number of unexpected cpl */
395 uint32_t n_mbint_unexp; /* Number of unexpected mbox */
396 /* interrupt */
397 uint32_t n_plint_unexp; /* Number of unexpected PL */
398 /* interrupt */
399 uint32_t n_plint_cnt; /* Number of PL interrupt */
400 uint32_t n_int_stray; /* Number of stray interrupt */
401 uint32_t n_err; /* Number of hw errors */
402 uint32_t n_err_fatal; /* Number of fatal errors */
403 uint32_t n_err_nomem; /* Number of memory alloc failure */
404 uint32_t n_err_io; /* Number of IO failure */
405 enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX]; /* Number of sm events */
406 uint64_t n_reset_start; /* Start time after the reset */
407 uint32_t rsvd1;
408};
409
410/* Defines for hw->flags */
411#define CSIO_HWF_MASTER 0x00000001 /* This is the Master
412 * function for the
413 * card.
414 */
415#define CSIO_HWF_HW_INTR_ENABLED 0x00000002 /* Are HW Interrupt
416 * enable bit set?
417 */
418#define CSIO_HWF_FWEVT_PENDING 0x00000004 /* FW events pending */
419#define CSIO_HWF_Q_MEM_ALLOCED 0x00000008 /* Queues have been
420 * allocated memory.
421 */
422#define CSIO_HWF_Q_FW_ALLOCED 0x00000010 /* Queues have been
423 * allocated in FW.
424 */
425#define CSIO_HWF_VPD_VALID 0x00000020 /* Valid VPD copied */
426#define CSIO_HWF_DEVID_CACHED 0X00000040 /* PCI vendor & device
427 * id cached */
428#define CSIO_HWF_FWEVT_STOP 0x00000080 /* Stop processing
429 * FW events
430 */
431#define CSIO_HWF_USING_SOFT_PARAMS 0x00000100 /* Using FW config
432 * params
433 */
434#define CSIO_HWF_HOST_INTR_ENABLED 0x00000200 /* Are host interrupts
435 * enabled?
436 */
437
438#define csio_is_hw_intr_enabled(__hw) \
439 ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
440#define csio_is_host_intr_enabled(__hw) \
441 ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED)
442#define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER)
443#define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID)
444#define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED)
445#define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID)
446#define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED)
447
448/* Defines for intr_mode */
449enum csio_intr_mode {
450 CSIO_IM_NONE = 0,
451 CSIO_IM_INTX = 1,
452 CSIO_IM_MSI = 2,
453 CSIO_IM_MSIX = 3,
454};
455
456/* Master HW structure: One per function */
457struct csio_hw {
458 struct csio_sm sm; /* State machine: should
459 * be the 1st member.
460 */
461 spinlock_t lock; /* Lock for hw */
462
463 struct csio_scsim scsim; /* SCSI module*/
464 struct csio_wrm wrm; /* Work request module*/
465 struct pci_dev *pdev; /* PCI device */
466
467 void __iomem *regstart; /* Virtual address of
468 * register map
469 */
470 /* SCSI queue sets */
471 uint32_t num_sqsets; /* Number of SCSI
472 * queue sets */
473 uint32_t num_scsi_msix_cpus; /* Number of CPUs that
474 * will be used
475 * for ingress
476 * processing.
477 */
478
479 struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU];
480 struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS];
481
482 uint32_t evtflag; /* Event flag */
483 uint32_t flags; /* HW flags */
484
485 struct csio_mgmtm mgmtm; /* management module */
486 struct csio_mbm mbm; /* Mailbox module */
487
488 /* Lnodes */
489 uint32_t num_lns; /* Number of lnodes */
490 struct csio_lnode *rln; /* Root lnode */
491 struct list_head sln_head; /* Sibling node list
492 * list
493 */
494 int intr_iq_idx; /* Forward interrupt
495 * queue.
496 */
497 int fwevt_iq_idx; /* FW evt queue */
498 struct work_struct evtq_work; /* Worker thread for
499 * HW events.
500 */
501 struct list_head evt_free_q; /* freelist of evt
502 * elements
503 */
504 struct list_head evt_active_q; /* active evt queue*/
505
506 /* board related info */
507 char name[32];
508 char hw_ver[16];
509 char model_desc[32];
510 char drv_version[32];
511 char fwrev_str[32];
512 uint32_t optrom_ver;
513 uint32_t fwrev;
514 uint32_t tp_vers;
515 char chip_ver;
516 uint32_t cfg_finiver;
517 uint32_t cfg_finicsum;
518 uint32_t cfg_cfcsum;
519 uint8_t cfg_csum_status;
520 uint8_t cfg_store;
521 enum csio_dev_state fw_state;
522 struct csio_vpd vpd;
523
524 uint8_t pfn; /* Physical Function
525 * number
526 */
527 uint32_t port_vec; /* Port vector */
528 uint8_t num_pports; /* Number of physical
529 * ports.
530 */
531 uint8_t rst_retries; /* Reset retries */
532 uint8_t cur_evt; /* current s/m evt */
533 uint8_t prev_evt; /* Previous s/m evt */
534 uint32_t dev_num; /* device number */
535 struct csio_pport pport[CSIO_MAX_PPORTS]; /* Ports (XGMACs) */
536 struct csio_hw_params params; /* Hw parameters */
537
538 struct pci_pool *scsi_pci_pool; /* PCI pool for SCSI */
539 mempool_t *mb_mempool; /* Mailbox memory pool*/
540 mempool_t *rnode_mempool; /* rnode memory pool */
541
542 /* Interrupt */
543 enum csio_intr_mode intr_mode; /* INTx, MSI, MSIX */
544 uint32_t fwevt_intr_idx; /* FW evt MSIX/interrupt
545 * index
546 */
547 uint32_t nondata_intr_idx; /* nondata MSIX/intr
548 * idx
549 */
550
551 uint8_t cfg_neq; /* FW configured no of
552 * egress queues
553 */
554 uint8_t cfg_niq; /* FW configured no of
555 * iq queues.
556 */
557
558 struct csio_fcoe_res_info fres_info; /* Fcoe resource info */
559
560 /* MSIX vectors */
561 struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
562
563 struct dentry *debugfs_root; /* Debug FS */
564 struct csio_hw_stats stats; /* Hw statistics */
565};
566
567/* Register access macros */
568#define csio_reg(_b, _r) ((_b) + (_r))
569
570#define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r)))
571#define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r)))
572#define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r)))
573#define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r)))
574
575#define csio_wr_reg8(_h, _v, _r) writeb((_v), \
576 csio_reg((_h)->regstart, (_r)))
577#define csio_wr_reg16(_h, _v, _r) writew((_v), \
578 csio_reg((_h)->regstart, (_r)))
579#define csio_wr_reg32(_h, _v, _r) writel((_v), \
580 csio_reg((_h)->regstart, (_r)))
581#define csio_wr_reg64(_h, _v, _r) writeq((_v), \
582 csio_reg((_h)->regstart, (_r)))
583
584void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t);
585
586/* Core clocks <==> uSecs */
587static inline uint32_t
588csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks)
589{
590 /* add Core Clock / 2 to round ticks to nearest uS */
591 return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk;
592}
593
594static inline uint32_t
595csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
596{
597 return (us * hw->vpd.cclk) / 1000;
598}
599
600/* Easy access macros */
601#define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm))
602#define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm))
603#define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim))
604#define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm))
605
606#define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number)
607#define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn))
608#define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn))
609
610#define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i))
611#define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx)
612#define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i))
613#define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx)
614
615/* Printing/logging */
616#define CSIO_DEVID(__dev) ((__dev)->dev_num)
617#define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF)
618#define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF)
619
620#define csio_info(__hw, __fmt, ...) \
621 dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
622
623#define csio_fatal(__hw, __fmt, ...) \
624 dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
625
626#define csio_err(__hw, __fmt, ...) \
627 dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
628
629#define csio_warn(__hw, __fmt, ...) \
630 dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
631
632#ifdef __CSIO_DEBUG__
633#define csio_dbg(__hw, __fmt, ...) \
634 csio_info((__hw), __fmt, ##__VA_ARGS__);
635#else
636#define csio_dbg(__hw, __fmt, ...)
637#endif
638
639int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
640void csio_hw_intr_disable(struct csio_hw *);
641int csio_hw_slow_intr_handler(struct csio_hw *hw);
642int csio_hw_start(struct csio_hw *);
643int csio_hw_stop(struct csio_hw *);
644int csio_hw_reset(struct csio_hw *);
645int csio_is_hw_ready(struct csio_hw *);
646int csio_is_hw_removing(struct csio_hw *);
647
648int csio_fwevtq_handler(struct csio_hw *);
649void csio_evtq_worker(struct work_struct *);
650int csio_enqueue_evt(struct csio_hw *hw, enum csio_evt type,
651 void *evt_msg, uint16_t len);
652void csio_evtq_flush(struct csio_hw *hw);
653
654int csio_request_irqs(struct csio_hw *);
655void csio_intr_enable(struct csio_hw *);
656void csio_intr_disable(struct csio_hw *, bool);
657
658struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
659int csio_config_queues(struct csio_hw *);
660
5036f0a0
NKI		 661int csio_hw_mc_read(struct csio_hw *, uint32_t, __be32 *, uint64_t *);
662int csio_hw_edc_read(struct csio_hw *, int, uint32_t, __be32 *, uint64_t *);
a3667aae
NKI		 663int csio_hw_init(struct csio_hw *);
664void csio_hw_exit(struct csio_hw *);
665#endif /* ifndef __CSIO_HW_H__ */
kernel source for telekom puls (alcatel/mediatek)