[GitHub/LineageOS/android_kernel_samsung_universal7580.git] / drivers / scsi / ata_piix.c

/*
 *    ata_piix.c - Intel PATA/SATA controllers
 *
 *    Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *
 *	Copyright 2003-2005 Red Hat Inc
 *	Copyright 2003-2005 Jeff Garzik
 *
 *
 *	Copyright header from piix.c:
 *
 *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
 *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available at http://developer.intel.com/
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"ata_piix"
#define DRV_VERSION	"1.04"

enum {
	PIIX_IOCFG		= 0x54, /* IDE I/O configuration register */
	ICH5_PMR		= 0x90, /* port mapping register */
	ICH5_PCS		= 0x92,	/* port control and status */
	PIIX_SCC		= 0x0A, /* sub-class code register */

	PIIX_FLAG_AHCI		= (1 << 28), /* AHCI possible */
	PIIX_FLAG_CHECKINTR	= (1 << 29), /* make sure PCI INTx enabled */
	PIIX_FLAG_COMBINED	= (1 << 30), /* combined mode possible */

	/* combined mode.  if set, PATA is channel 0.
	 * if clear, PATA is channel 1.
	 */
	PIIX_COMB_PATA_P0	= (1 << 1),
	PIIX_COMB		= (1 << 2), /* combined mode enabled? */

	PIIX_PORT_ENABLED	= (1 << 0),
	PIIX_PORT_PRESENT	= (1 << 4),

	PIIX_80C_PRI		= (1 << 5) | (1 << 4),
	PIIX_80C_SEC		= (1 << 7) | (1 << 6),

	ich5_pata		= 0,
	ich5_sata		= 1,
	piix4_pata		= 2,
	ich6_sata		= 3,
	ich6_sata_rm		= 4,
	ich7_sata		= 5,
	esb2_sata		= 6,

	PIIX_AHCI_DEVICE	= 6,
};

static int piix_init_one (struct pci_dev *pdev,
				    const struct pci_device_id *ent);

static void piix_pata_phy_reset(struct ata_port *ap);
static void piix_sata_phy_reset(struct ata_port *ap);
static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);

static unsigned int in_module_init = 1;

static struct pci_device_id piix_pci_tbl[] = {
#ifdef ATA_ENABLE_PATA
	{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
	{ 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
	{ 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
#endif

	/* NOTE: The following PCI ids must be kept in sync with the
	 * list in drivers/pci/quirks.c.
	 */

	{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
	{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
	{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
	{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
	{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
	{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
	{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
	{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
	{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb2_sata },

	{ }	/* terminate list */
};

static struct pci_driver piix_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= piix_pci_tbl,
	.probe			= piix_init_one,
	.remove			= ata_pci_remove_one,
};

static Scsi_Host_Template piix_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.eh_strategy_handler	= ata_scsi_error,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
	.ordered_flush		= 1,
};

static const struct ata_port_operations piix_pata_ops = {
	.port_disable		= ata_port_disable,
	.set_piomode		= piix_set_piomode,
	.set_dmamode		= piix_set_dmamode,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.phy_reset		= piix_pata_phy_reset,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,

	.eng_timeout		= ata_eng_timeout,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,

	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_host_stop,
};

static const struct ata_port_operations piix_sata_ops = {
	.port_disable		= ata_port_disable,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.phy_reset		= piix_sata_phy_reset,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,

	.eng_timeout		= ata_eng_timeout,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,

	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_host_stop,
};

static struct ata_port_info piix_port_info[] = {
	/* ich5_pata */
	{
		.sht		= &piix_sht,
		.host_flags	= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
				  PIIX_FLAG_CHECKINTR,
		.pio_mask	= 0x1f,	/* pio0-4 */
#if 0
		.mwdma_mask	= 0x06, /* mwdma1-2 */
#else
		.mwdma_mask	= 0x00, /* mwdma broken */
#endif
		.udma_mask	= 0x3f, /* udma0-5 */
		.port_ops	= &piix_pata_ops,
	},

	/* ich5_sata */
	{
		.sht		= &piix_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_SRST |
				  PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f,	/* udma0-6 */
		.port_ops	= &piix_sata_ops,
	},

	/* piix4_pata */
	{
		.sht		= &piix_sht,
		.host_flags	= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask	= 0x1f,	/* pio0-4 */
#if 0
		.mwdma_mask	= 0x06, /* mwdma1-2 */
#else
		.mwdma_mask	= 0x00, /* mwdma broken */
#endif
		.udma_mask	= ATA_UDMA_MASK_40C,
		.port_ops	= &piix_pata_ops,
	},

	/* ich6_sata */
	{
		.sht		= &piix_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_SRST |
				  PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
				  ATA_FLAG_SLAVE_POSS,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f,	/* udma0-6 */
		.port_ops	= &piix_sata_ops,
	},

	/* ich6_sata_rm */
	{
		.sht		= &piix_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_SRST |
				  PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
				  ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f,	/* udma0-6 */
		.port_ops	= &piix_sata_ops,
	},

	/* ich7_sata */
	{
		.sht		= &piix_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_SRST |
				  PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
				  ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f,	/* udma0-6 */
		.port_ops	= &piix_sata_ops,
	},

	/* esb2_sata */
	{
		.sht		= &piix_sht,
		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_SRST |
				  PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
				  ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f,	/* udma0-6 */
		.port_ops	= &piix_sata_ops,
	},
};

static struct pci_bits piix_enable_bits[] = {
	{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
	{ 0x43U, 1U, 0x80UL, 0x80UL },	/* port 1 */
};

MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
MODULE_VERSION(DRV_VERSION);

/**
 *	piix_pata_cbl_detect - Probe host controller cable detect info
 *	@ap: Port for which cable detect info is desired
 *
 *	Read 80c cable indicator from ATA PCI device's PCI config
 *	register.  This register is normally set by firmware (BIOS).
 *
 *	LOCKING:
 *	None (inherited from caller).
 */
static void piix_pata_cbl_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	u8 tmp, mask;

	/* no 80c support in host controller? */
	if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
		goto cbl40;

	/* check BIOS cable detect results */
	mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
	pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
	if ((tmp & mask) == 0)
		goto cbl40;

	ap->cbl = ATA_CBL_PATA80;
	return;

cbl40:
	ap->cbl = ATA_CBL_PATA40;
	ap->udma_mask &= ATA_UDMA_MASK_40C;
}

/**
 *	piix_pata_phy_reset - Probe specified port on PATA host controller
 *	@ap: Port to probe
 *
 *	Probe PATA phy.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void piix_pata_phy_reset(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);

	if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
		ata_port_disable(ap);
		printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
		return;
	}

	piix_pata_cbl_detect(ap);

	ata_port_probe(ap);

	ata_bus_reset(ap);
}

/**
 *	piix_sata_probe - Probe PCI device for present SATA devices
 *	@ap: Port associated with the PCI device we wish to probe
 *
 *	Reads SATA PCI device's PCI config register Port Configuration
 *	and Status (PCS) to determine port and device availability.
 *
 *	LOCKING:
 *	None (inherited from caller).
 *
 *	RETURNS:
 *	Non-zero if port is enabled, it may or may not have a device
 *	attached in that case (PRESENT bit would only be set if BIOS probe
 *	was done). Zero is returned if port is disabled.
 */
static int piix_sata_probe (struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
	int orig_mask, mask, i;
	u8 pcs;

	mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
	       (PIIX_PORT_ENABLED << ap->hard_port_no);

	pci_read_config_byte(pdev, ICH5_PCS, &pcs);
	orig_mask = (int) pcs & 0xff;

	/* TODO: this is vaguely wrong for ICH6 combined mode,
	 * where only two of the four SATA ports are mapped
	 * onto a single ATA channel.  It is also vaguely inaccurate
	 * for ICH5, which has only two ports.  However, this is ok,
	 * as further device presence detection code will handle
	 * any false positives produced here.
	 */

	for (i = 0; i < 4; i++) {
		mask = (PIIX_PORT_ENABLED << i);

		if ((orig_mask & mask) == mask)
			if (combined || (i == ap->hard_port_no))
				return 1;
	}

	return 0;
}

/**
 *	piix_sata_phy_reset - Probe specified port on SATA host controller
 *	@ap: Port to probe
 *
 *	Probe SATA phy.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void piix_sata_phy_reset(struct ata_port *ap)
{
	if (!piix_sata_probe(ap)) {
		ata_port_disable(ap);
		printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
		return;
	}

	ap->cbl = ATA_CBL_SATA;

	ata_port_probe(ap);

	ata_bus_reset(ap);
}

/**
 *	piix_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: um
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *dev	= to_pci_dev(ap->host_set->dev);
	unsigned int is_slave	= (adev->devno != 0);
	unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
	unsigned int slave_port	= 0x44;
	u16 master_data;
	u8 slave_data;

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	pci_read_config_word(dev, master_port, &master_data);
	if (is_slave) {
		master_data |= 0x4000;
		/* enable PPE, IE and TIME */
		master_data |= 0x0070;
		pci_read_config_byte(dev, slave_port, &slave_data);
		slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
		slave_data |=
			(timings[pio][0] << 2) |
			(timings[pio][1] << (ap->hard_port_no ? 4 : 0));
	} else {
		master_data &= 0xccf8;
		/* enable PPE, IE and TIME */
		master_data |= 0x0007;
		master_data |=
			(timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	}
	pci_write_config_word(dev, master_port, master_data);
	if (is_slave)
		pci_write_config_byte(dev, slave_port, slave_data);
}

/**
 *	piix_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: um
 *	@udma: udma mode, 0 - 6
 *
 *	Set UDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int udma	= adev->dma_mode; /* FIXME: MWDMA too */
	struct pci_dev *dev	= to_pci_dev(ap->host_set->dev);
	u8 maslave		= ap->hard_port_no ? 0x42 : 0x40;
	u8 speed		= udma;
	unsigned int drive_dn	= (ap->hard_port_no ? 2 : 0) + adev->devno;
	int a_speed		= 3 << (drive_dn * 4);
	int u_flag		= 1 << drive_dn;
	int v_flag		= 0x01 << drive_dn;
	int w_flag		= 0x10 << drive_dn;
	int u_speed		= 0;
	int			sitre;
	u16			reg4042, reg4a;
	u8			reg48, reg54, reg55;

	pci_read_config_word(dev, maslave, &reg4042);
	DPRINTK("reg4042 = 0x%04x\n", reg4042);
	sitre = (reg4042 & 0x4000) ? 1 : 0;
	pci_read_config_byte(dev, 0x48, &reg48);
	pci_read_config_word(dev, 0x4a, &reg4a);
	pci_read_config_byte(dev, 0x54, &reg54);
	pci_read_config_byte(dev, 0x55, &reg55);

	switch(speed) {
		case XFER_UDMA_4:
		case XFER_UDMA_2:	u_speed = 2 << (drive_dn * 4); break;
		case XFER_UDMA_6:
		case XFER_UDMA_5:
		case XFER_UDMA_3:
		case XFER_UDMA_1:	u_speed = 1 << (drive_dn * 4); break;
		case XFER_UDMA_0:	u_speed = 0 << (drive_dn * 4); break;
		case XFER_MW_DMA_2:
		case XFER_MW_DMA_1:	break;
		default:
			BUG();
			return;
	}

	if (speed >= XFER_UDMA_0) {
		if (!(reg48 & u_flag))
			pci_write_config_byte(dev, 0x48, reg48 | u_flag);
		if (speed == XFER_UDMA_5) {
			pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
		} else {
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
		}
		if ((reg4a & a_speed) != u_speed)
			pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
		if (speed > XFER_UDMA_2) {
			if (!(reg54 & v_flag))
				pci_write_config_byte(dev, 0x54, reg54 | v_flag);
		} else
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
	} else {
		if (reg48 & u_flag)
			pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
		if (reg4a & a_speed)
			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
		if (reg54 & v_flag)
			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
		if (reg55 & w_flag)
			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
	}
}

#define AHCI_PCI_BAR 5
#define AHCI_GLOBAL_CTL 0x04
#define AHCI_ENABLE (1 << 31)
static int piix_disable_ahci(struct pci_dev *pdev)
{
	void __iomem *mmio;
	u32 tmp;
	int rc = 0;

	/* BUG: pci_enable_device has not yet been called.  This
	 * works because this device is usually set up by BIOS.
	 */

	if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
	    !pci_resource_len(pdev, AHCI_PCI_BAR))
		return 0;

	mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
	if (!mmio)
		return -ENOMEM;

	tmp = readl(mmio + AHCI_GLOBAL_CTL);
	if (tmp & AHCI_ENABLE) {
		tmp &= ~AHCI_ENABLE;
		writel(tmp, mmio + AHCI_GLOBAL_CTL);

		tmp = readl(mmio + AHCI_GLOBAL_CTL);
		if (tmp & AHCI_ENABLE)
			rc = -EIO;
	}

	pci_iounmap(pdev, mmio);
	return rc;
}

/**
 *	piix_init_one - Register PIIX ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in piix_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.  We probe for combined mode (sigh),
 *	and then hand over control to libata, for it to do the rest.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_port_info *port_info[2];
	unsigned int combined = 0;
	unsigned int pata_chan = 0, sata_chan = 0;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "version " DRV_VERSION "\n");

	/* no hotplugging support (FIXME) */
	if (!in_module_init)
		return -ENODEV;

	port_info[0] = &piix_port_info[ent->driver_data];
	port_info[1] = &piix_port_info[ent->driver_data];

	if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
		u8 tmp;
		pci_read_config_byte(pdev, PIIX_SCC, &tmp);
		if (tmp == PIIX_AHCI_DEVICE) {
			int rc = piix_disable_ahci(pdev);
			if (rc)
				return rc;
		}
	}

	if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
		u8 tmp;
		pci_read_config_byte(pdev, ICH5_PMR, &tmp);

		if (tmp & PIIX_COMB) {
			combined = 1;
			if (tmp & PIIX_COMB_PATA_P0)
				sata_chan = 1;
			else
				pata_chan = 1;
		}
	}

	/* On ICH5, some BIOSen disable the interrupt using the
	 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
	 * On ICH6, this bit has the same effect, but only when
	 * MSI is disabled (and it is disabled, as we don't use
	 * message-signalled interrupts currently).
	 */
	if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
		pci_intx(pdev, 1);

	if (combined) {
		port_info[sata_chan] = &piix_port_info[ent->driver_data];
		port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
		port_info[pata_chan] = &piix_port_info[ich5_pata];

		dev_printk(KERN_WARNING, &pdev->dev,
			   "combined mode detected (p=%u, s=%u)\n",
			   pata_chan, sata_chan);
	}

	return ata_pci_init_one(pdev, port_info, 2);
}

static int __init piix_init(void)
{
	int rc;

	DPRINTK("pci_module_init\n");
	rc = pci_module_init(&piix_pci_driver);
	if (rc)
		return rc;

	in_module_init = 0;

	DPRINTK("done\n");
	return 0;
}

static void __exit piix_exit(void)
{
	pci_unregister_driver(&piix_pci_driver);
}

module_init(piix_init);
module_exit(piix_exit);
Commit	Line	Data
1da177e4	1	/*
af36d7f0 JG	2	* ata_piix.c - Intel PATA/SATA controllers
	3	*
	4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	*
	9	* Copyright 2003-2005 Red Hat Inc
	10	* Copyright 2003-2005 Jeff Garzik
	11	*
	12	*
	13	* Copyright header from piix.c:
	14	*
	15	* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
	16	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	17	* Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
	18	*
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License as published by
	22	* the Free Software Foundation; either version 2, or (at your option)
	23	* any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; see the file COPYING. If not, write to
	32	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	33	*
	34	*
	35	* libata documentation is available via 'make {ps\|pdf}docs',
	36	* as Documentation/DocBook/libata.*
	37	*
	38	* Hardware documentation available at http://developer.intel.com/
	39	*
1da177e4 LT	40	*/
	41
	42	#include <linux/kernel.h>
	43	#include <linux/module.h>
	44	#include <linux/pci.h>
	45	#include <linux/init.h>
	46	#include <linux/blkdev.h>
	47	#include <linux/delay.h>
6248e647	48	#include <linux/device.h>
1da177e4 LT	49	#include "scsi.h"
	50	#include <scsi/scsi_host.h>
	51	#include <linux/libata.h>
	52
	53	#define DRV_NAME "ata_piix"
6885433c	54	#define DRV_VERSION "1.04"
1da177e4 LT	55
	56	enum {
	57	PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
	58	ICH5_PMR = 0x90, /* port mapping register */
	59	ICH5_PCS = 0x92, /* port control and status */
7b6dbd68	60	PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 LT	61
	62	PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
	63	PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
	64	PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
	65
	66	/* combined mode. if set, PATA is channel 0.
	67	* if clear, PATA is channel 1.
	68	*/
	69	PIIX_COMB_PATA_P0 = (1 << 1),
	70	PIIX_COMB = (1 << 2), /* combined mode enabled? */
	71
6a690df5 HR	72	PIIX_PORT_ENABLED = (1 << 0),
6a690df5 HR	73	PIIX_PORT_PRESENT = (1 << 4),
1da177e4 LT	74
	75	PIIX_80C_PRI = (1 << 5) \| (1 << 4),
	76	PIIX_80C_SEC = (1 << 7) \| (1 << 6),
	77
	78	ich5_pata = 0,
	79	ich5_sata = 1,
	80	piix4_pata = 2,
	81	ich6_sata = 3,
	82	ich6_sata_rm = 4,
	83	ich7_sata = 5,
c368ca4e	84	esb2_sata = 6,
7b6dbd68 GF	85
7b6dbd68 GF	86	PIIX_AHCI_DEVICE = 6,
1da177e4 LT	87	};
	88
	89	static int piix_init_one (struct pci_dev *pdev,
	90	const struct pci_device_id *ent);
	91
	92	static void piix_pata_phy_reset(struct ata_port *ap);
	93	static void piix_sata_phy_reset(struct ata_port *ap);
	94	static void piix_set_piomode (struct ata_port ap, struct ata_device adev);
	95	static void piix_set_dmamode (struct ata_port ap, struct ata_device adev);
	96
	97	static unsigned int in_module_init = 1;
	98
	99	static struct pci_device_id piix_pci_tbl[] = {
	100	#ifdef ATA_ENABLE_PATA
	101	{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
	102	{ 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
	103	{ 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
	104	#endif
	105
	106	/* NOTE: The following PCI ids must be kept in sync with the
	107	* list in drivers/pci/quirks.c.
	108	*/
	109
	110	{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
	111	{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
	112	{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
	113	{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
	114	{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
	115	{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
	116	{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
	117	{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
	118	{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
c368ca4e	119	{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb2_sata },
1da177e4 LT	120
	121	{ } /* terminate list */
	122	};
	123
	124	static struct pci_driver piix_pci_driver = {
	125	.name = DRV_NAME,
	126	.id_table = piix_pci_tbl,
	127	.probe = piix_init_one,
	128	.remove = ata_pci_remove_one,
	129	};
	130
	131	static Scsi_Host_Template piix_sht = {
	132	.module = THIS_MODULE,
	133	.name = DRV_NAME,
	134	.ioctl = ata_scsi_ioctl,
	135	.queuecommand = ata_scsi_queuecmd,
	136	.eh_strategy_handler = ata_scsi_error,
	137	.can_queue = ATA_DEF_QUEUE,
	138	.this_id = ATA_SHT_THIS_ID,
	139	.sg_tablesize = LIBATA_MAX_PRD,
	140	.max_sectors = ATA_MAX_SECTORS,
	141	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	142	.emulated = ATA_SHT_EMULATED,
	143	.use_clustering = ATA_SHT_USE_CLUSTERING,
	144	.proc_name = DRV_NAME,
	145	.dma_boundary = ATA_DMA_BOUNDARY,
	146	.slave_configure = ata_scsi_slave_config,
	147	.bios_param = ata_std_bios_param,
	148	.ordered_flush = 1,
	149	};
	150
057ace5e	151	static const struct ata_port_operations piix_pata_ops = {
1da177e4 LT	152	.port_disable = ata_port_disable,
	153	.set_piomode = piix_set_piomode,
	154	.set_dmamode = piix_set_dmamode,
	155
	156	.tf_load = ata_tf_load,
	157	.tf_read = ata_tf_read,
	158	.check_status = ata_check_status,
	159	.exec_command = ata_exec_command,
	160	.dev_select = ata_std_dev_select,
	161
	162	.phy_reset = piix_pata_phy_reset,
	163
	164	.bmdma_setup = ata_bmdma_setup,
	165	.bmdma_start = ata_bmdma_start,
	166	.bmdma_stop = ata_bmdma_stop,
	167	.bmdma_status = ata_bmdma_status,
	168	.qc_prep = ata_qc_prep,
	169	.qc_issue = ata_qc_issue_prot,
	170
	171	.eng_timeout = ata_eng_timeout,
	172
	173	.irq_handler = ata_interrupt,
	174	.irq_clear = ata_bmdma_irq_clear,
	175
	176	.port_start = ata_port_start,
	177	.port_stop = ata_port_stop,
aa8f0dc6	178	.host_stop = ata_host_stop,
1da177e4 LT	179	};
1da177e4 LT	180
057ace5e	181	static const struct ata_port_operations piix_sata_ops = {
1da177e4 LT	182	.port_disable = ata_port_disable,
	183
	184	.tf_load = ata_tf_load,
	185	.tf_read = ata_tf_read,
	186	.check_status = ata_check_status,
	187	.exec_command = ata_exec_command,
	188	.dev_select = ata_std_dev_select,
	189
	190	.phy_reset = piix_sata_phy_reset,
	191
	192	.bmdma_setup = ata_bmdma_setup,
	193	.bmdma_start = ata_bmdma_start,
	194	.bmdma_stop = ata_bmdma_stop,
	195	.bmdma_status = ata_bmdma_status,
	196	.qc_prep = ata_qc_prep,
	197	.qc_issue = ata_qc_issue_prot,
	198
	199	.eng_timeout = ata_eng_timeout,
	200
	201	.irq_handler = ata_interrupt,
	202	.irq_clear = ata_bmdma_irq_clear,
	203
	204	.port_start = ata_port_start,
	205	.port_stop = ata_port_stop,
aa8f0dc6	206	.host_stop = ata_host_stop,
1da177e4 LT	207	};
	208
	209	static struct ata_port_info piix_port_info[] = {
	210	/* ich5_pata */
	211	{
	212	.sht = &piix_sht,
	213	.host_flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST \|
	214	PIIX_FLAG_CHECKINTR,
	215	.pio_mask = 0x1f, /* pio0-4 */
	216	#if 0
	217	.mwdma_mask = 0x06, /* mwdma1-2 */
	218	#else
	219	.mwdma_mask = 0x00, /* mwdma broken */
	220	#endif
	221	.udma_mask = 0x3f, /* udma0-5 */
	222	.port_ops = &piix_pata_ops,
	223	},
	224
	225	/* ich5_sata */
	226	{
	227	.sht = &piix_sht,
	228	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_SRST \|
	229	PIIX_FLAG_COMBINED \| PIIX_FLAG_CHECKINTR,
	230	.pio_mask = 0x1f, /* pio0-4 */
	231	.mwdma_mask = 0x07, /* mwdma0-2 */
	232	.udma_mask = 0x7f, /* udma0-6 */
	233	.port_ops = &piix_sata_ops,
	234	},
	235
	236	/* piix4_pata */
	237	{
	238	.sht = &piix_sht,
	239	.host_flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	240	.pio_mask = 0x1f, /* pio0-4 */
	241	#if 0
	242	.mwdma_mask = 0x06, /* mwdma1-2 */
	243	#else
	244	.mwdma_mask = 0x00, /* mwdma broken */
	245	#endif
	246	.udma_mask = ATA_UDMA_MASK_40C,
	247	.port_ops = &piix_pata_ops,
	248	},
	249
	250	/* ich6_sata */
	251	{
	252	.sht = &piix_sht,
	253	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_SRST \|
	254	PIIX_FLAG_COMBINED \| PIIX_FLAG_CHECKINTR \|
	255	ATA_FLAG_SLAVE_POSS,
	256	.pio_mask = 0x1f, /* pio0-4 */
	257	.mwdma_mask = 0x07, /* mwdma0-2 */
	258	.udma_mask = 0x7f, /* udma0-6 */
	259	.port_ops = &piix_sata_ops,
	260	},
	261
	262	/* ich6_sata_rm */
	263	{
	264	.sht = &piix_sht,
	265	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_SRST \|
	266	PIIX_FLAG_COMBINED \| PIIX_FLAG_CHECKINTR \|
	267	ATA_FLAG_SLAVE_POSS \| PIIX_FLAG_AHCI,
	268	.pio_mask = 0x1f, /* pio0-4 */
	269	.mwdma_mask = 0x07, /* mwdma0-2 */
	270	.udma_mask = 0x7f, /* udma0-6 */
271	.port_ops = &piix_sata_ops,
272	},
273
274	/* ich7_sata */
275	{
276	.sht = &piix_sht,
277	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_SRST \|
278	PIIX_FLAG_COMBINED \| PIIX_FLAG_CHECKINTR \|
279	ATA_FLAG_SLAVE_POSS \| PIIX_FLAG_AHCI,
280	.pio_mask = 0x1f, /* pio0-4 */
281	.mwdma_mask = 0x07, /* mwdma0-2 */
282	.udma_mask = 0x7f, /* udma0-6 */
283	.port_ops = &piix_sata_ops,
284	},
c368ca4e JG	285
	286	/* esb2_sata */
	287	{
	288	.sht = &piix_sht,
	289	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_SRST \|
	290	PIIX_FLAG_COMBINED \| PIIX_FLAG_CHECKINTR \|
	291	ATA_FLAG_SLAVE_POSS \| PIIX_FLAG_AHCI,
	292	.pio_mask = 0x1f, /* pio0-4 */
	293	.mwdma_mask = 0x07, /* mwdma0-2 */
	294	.udma_mask = 0x7f, /* udma0-6 */
	295	.port_ops = &piix_sata_ops,
	296	},
1da177e4 LT	297	};
	298
	299	static struct pci_bits piix_enable_bits[] = {
	300	{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
	301	{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
	302	};
	303
	304	MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
	305	MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
	306	MODULE_LICENSE("GPL");
	307	MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
	308	MODULE_VERSION(DRV_VERSION);
	309
	310	/**
	311	* piix_pata_cbl_detect - Probe host controller cable detect info
	312	* @ap: Port for which cable detect info is desired
	313	*
	314	* Read 80c cable indicator from ATA PCI device's PCI config
	315	* register. This register is normally set by firmware (BIOS).
	316	*
	317	* LOCKING:
	318	* None (inherited from caller).
	319	*/
	320	static void piix_pata_cbl_detect(struct ata_port *ap)
	321	{
	322	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	323	u8 tmp, mask;
	324
	325	/* no 80c support in host controller? */
	326	if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
	327	goto cbl40;
	328
	329	/* check BIOS cable detect results */
	330	mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
	331	pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
	332	if ((tmp & mask) == 0)
	333	goto cbl40;
	334
	335	ap->cbl = ATA_CBL_PATA80;
	336	return;
	337
	338	cbl40:
	339	ap->cbl = ATA_CBL_PATA40;
	340	ap->udma_mask &= ATA_UDMA_MASK_40C;
	341	}
	342
	343	/**
	344	* piix_pata_phy_reset - Probe specified port on PATA host controller
	345	* @ap: Port to probe
	346	*
	347	* Probe PATA phy.
	348	*
	349	* LOCKING:
	350	* None (inherited from caller).
	351	*/
	352
	353	static void piix_pata_phy_reset(struct ata_port *ap)
	354	{
	355	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	356
	357	if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
	358	ata_port_disable(ap);
	359	printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
	360	return;
361	}
362
363	piix_pata_cbl_detect(ap);
364
365	ata_port_probe(ap);
366
367	ata_bus_reset(ap);
368	}
369
370	/**
371	* piix_sata_probe - Probe PCI device for present SATA devices
372	* @ap: Port associated with the PCI device we wish to probe
373	*
374	* Reads SATA PCI device's PCI config register Port Configuration
375	* and Status (PCS) to determine port and device availability.
376	*
377	* LOCKING:
378	* None (inherited from caller).
379	*
380	* RETURNS:
6a690df5 HR	381	* Non-zero if port is enabled, it may or may not have a device
	382	* attached in that case (PRESENT bit would only be set if BIOS probe
	383	* was done). Zero is returned if port is disabled.
1da177e4 LT	384	*/
	385	static int piix_sata_probe (struct ata_port *ap)
	386	{
	387	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	388	int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
	389	int orig_mask, mask, i;
	390	u8 pcs;
	391
	392	mask = (PIIX_PORT_PRESENT << ap->hard_port_no) \|
	393	(PIIX_PORT_ENABLED << ap->hard_port_no);
	394
	395	pci_read_config_byte(pdev, ICH5_PCS, &pcs);
	396	orig_mask = (int) pcs & 0xff;
	397
	398	/* TODO: this is vaguely wrong for ICH6 combined mode,
	399	* where only two of the four SATA ports are mapped
	400	* onto a single ATA channel. It is also vaguely inaccurate
	401	* for ICH5, which has only two ports. However, this is ok,
	402	* as further device presence detection code will handle
	403	* any false positives produced here.
	404	*/
	405
	406	for (i = 0; i < 4; i++) {
6a690df5	407	mask = (PIIX_PORT_ENABLED << i);
1da177e4 LT	408
	409	if ((orig_mask & mask) == mask)
	410	if (combined \|\| (i == ap->hard_port_no))
	411	return 1;
	412	}
	413
	414	return 0;
	415	}
	416
	417	/**
	418	* piix_sata_phy_reset - Probe specified port on SATA host controller
	419	* @ap: Port to probe
	420	*
	421	* Probe SATA phy.
	422	*
	423	* LOCKING:
	424	* None (inherited from caller).
	425	*/
	426
	427	static void piix_sata_phy_reset(struct ata_port *ap)
	428	{
	429	if (!piix_sata_probe(ap)) {
	430	ata_port_disable(ap);
	431	printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
	432	return;
	433	}
	434
	435	ap->cbl = ATA_CBL_SATA;
	436
	437	ata_port_probe(ap);
	438
	439	ata_bus_reset(ap);
	440	}
	441
	442	/**
	443	* piix_set_piomode - Initialize host controller PATA PIO timings
	444	* @ap: Port whose timings we are configuring
	445	* @adev: um
1da177e4 LT	446	*
	447	* Set PIO mode for device, in host controller PCI config space.
	448	*
	449	* LOCKING:
	450	* None (inherited from caller).
	451	*/
	452
	453	static void piix_set_piomode (struct ata_port ap, struct ata_device adev)
	454	{
	455	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	456	struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
	457	unsigned int is_slave = (adev->devno != 0);
	458	unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
	459	unsigned int slave_port = 0x44;
	460	u16 master_data;
	461	u8 slave_data;
	462
	463	static const /* ISP RTC */
	464	u8 timings[][2] = { { 0, 0 },
	465	{ 0, 0 },
	466	{ 1, 0 },
	467	{ 2, 1 },
	468	{ 2, 3 }, };
	469
	470	pci_read_config_word(dev, master_port, &master_data);
	471	if (is_slave) {
	472	master_data \|= 0x4000;
	473	/* enable PPE, IE and TIME */
	474	master_data \|= 0x0070;
	475	pci_read_config_byte(dev, slave_port, &slave_data);
	476	slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
	477	slave_data \|=
	478	(timings[pio][0] << 2) \|
	479	(timings[pio][1] << (ap->hard_port_no ? 4 : 0));
	480	} else {
	481	master_data &= 0xccf8;
	482	/* enable PPE, IE and TIME */
	483	master_data \|= 0x0007;
	484	master_data \|=
	485	(timings[pio][0] << 12) \|
	486	(timings[pio][1] << 8);
	487	}
	488	pci_write_config_word(dev, master_port, master_data);
	489	if (is_slave)
	490	pci_write_config_byte(dev, slave_port, slave_data);
	491	}
	492
	493	/**
	494	* piix_set_dmamode - Initialize host controller PATA PIO timings
	495	* @ap: Port whose timings we are configuring
	496	* @adev: um
	497	* @udma: udma mode, 0 - 6
	498	*
	499	* Set UDMA mode for device, in host controller PCI config space.
	500	*
	501	* LOCKING:
	502	* None (inherited from caller).
	503	*/
	504
	505	static void piix_set_dmamode (struct ata_port ap, struct ata_device adev)
	506	{
	507	unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
	508	struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
	509	u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
510	u8 speed = udma;
511	unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
512	int a_speed = 3 << (drive_dn * 4);
513	int u_flag = 1 << drive_dn;
514	int v_flag = 0x01 << drive_dn;
515	int w_flag = 0x10 << drive_dn;
516	int u_speed = 0;
517	int sitre;
518	u16 reg4042, reg4a;
519	u8 reg48, reg54, reg55;
520
521	pci_read_config_word(dev, maslave, &reg4042);
522	DPRINTK("reg4042 = 0x%04x\n", reg4042);
523	sitre = (reg4042 & 0x4000) ? 1 : 0;
524	pci_read_config_byte(dev, 0x48, &reg48);
525	pci_read_config_word(dev, 0x4a, &reg4a);
526	pci_read_config_byte(dev, 0x54, &reg54);
527	pci_read_config_byte(dev, 0x55, &reg55);
528
529	switch(speed) {
530	case XFER_UDMA_4:
531	case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
532	case XFER_UDMA_6:
533	case XFER_UDMA_5:
534	case XFER_UDMA_3:
535	case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
536	case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
537	case XFER_MW_DMA_2:
538	case XFER_MW_DMA_1: break;
539	default:
540	BUG();
541	return;
542	}
543
544	if (speed >= XFER_UDMA_0) {
545	if (!(reg48 & u_flag))
546	pci_write_config_byte(dev, 0x48, reg48 \| u_flag);
547	if (speed == XFER_UDMA_5) {
548	pci_write_config_byte(dev, 0x55, (u8) reg55\|w_flag);
549	} else {
550	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
551	}
552	if ((reg4a & a_speed) != u_speed)
553	pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) \| u_speed);
554	if (speed > XFER_UDMA_2) {
555	if (!(reg54 & v_flag))
556	pci_write_config_byte(dev, 0x54, reg54 \| v_flag);
557	} else
558	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
559	} else {
560	if (reg48 & u_flag)
561	pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
562	if (reg4a & a_speed)
563	pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
564	if (reg54 & v_flag)
565	pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
566	if (reg55 & w_flag)
567	pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
568	}
569	}
570
1da177e4 LT	571	#define AHCI_PCI_BAR 5
	572	#define AHCI_GLOBAL_CTL 0x04
	573	#define AHCI_ENABLE (1 << 31)
	574	static int piix_disable_ahci(struct pci_dev *pdev)
	575	{
ea6ba10b	576	void __iomem *mmio;
1da177e4 LT	577	u32 tmp;
	578	int rc = 0;
	579
	580	/* BUG: pci_enable_device has not yet been called. This
	581	* works because this device is usually set up by BIOS.
	582	*/
	583
374b1873 JG	584	if (!pci_resource_start(pdev, AHCI_PCI_BAR) \|\|
374b1873 JG	585	!pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4	586	return 0;
7b6dbd68	587
374b1873	588	mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4 LT	589	if (!mmio)
1da177e4 LT	590	return -ENOMEM;
7b6dbd68	591
1da177e4 LT	592	tmp = readl(mmio + AHCI_GLOBAL_CTL);
	593	if (tmp & AHCI_ENABLE) {
	594	tmp &= ~AHCI_ENABLE;
	595	writel(tmp, mmio + AHCI_GLOBAL_CTL);
	596
	597	tmp = readl(mmio + AHCI_GLOBAL_CTL);
	598	if (tmp & AHCI_ENABLE)
	599	rc = -EIO;
	600	}
7b6dbd68	601
374b1873	602	pci_iounmap(pdev, mmio);
1da177e4 LT	603	return rc;
	604	}
	605
	606	/**
	607	* piix_init_one - Register PIIX ATA PCI device with kernel services
	608	* @pdev: PCI device to register
	609	* @ent: Entry in piix_pci_tbl matching with @pdev
	610	*
	611	* Called from kernel PCI layer. We probe for combined mode (sigh),
	612	* and then hand over control to libata, for it to do the rest.
	613	*
	614	* LOCKING:
	615	* Inherited from PCI layer (may sleep).
	616	*
	617	* RETURNS:
	618	* Zero on success, or -ERRNO value.
	619	*/
	620
	621	static int piix_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	622	{
	623	static int printed_version;
	624	struct ata_port_info *port_info[2];
fbf30fba	625	unsigned int combined = 0;
1da177e4 LT	626	unsigned int pata_chan = 0, sata_chan = 0;
	627
	628	if (!printed_version++)
6248e647 JG	629	dev_printk(KERN_DEBUG, &pdev->dev,
6248e647 JG	630	"version " DRV_VERSION "\n");
1da177e4 LT	631
	632	/* no hotplugging support (FIXME) */
	633	if (!in_module_init)
	634	return -ENODEV;
	635
	636	port_info[0] = &piix_port_info[ent->driver_data];
fbf30fba	637	port_info[1] = &piix_port_info[ent->driver_data];
1da177e4 LT	638
1da177e4 LT	639	if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
8a60a071 JG	640	u8 tmp;
	641	pci_read_config_byte(pdev, PIIX_SCC, &tmp);
	642	if (tmp == PIIX_AHCI_DEVICE) {
	643	int rc = piix_disable_ahci(pdev);
	644	if (rc)
	645	return rc;
	646	}
1da177e4 LT	647	}
	648
	649	if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
	650	u8 tmp;
	651	pci_read_config_byte(pdev, ICH5_PMR, &tmp);
	652
	653	if (tmp & PIIX_COMB) {
	654	combined = 1;
	655	if (tmp & PIIX_COMB_PATA_P0)
	656	sata_chan = 1;
	657	else
	658	pata_chan = 1;
	659	}
	660	}
	661
	662	/* On ICH5, some BIOSen disable the interrupt using the
	663	* PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
	664	* On ICH6, this bit has the same effect, but only when
	665	* MSI is disabled (and it is disabled, as we don't use
	666	* message-signalled interrupts currently).
	667	*/
	668	if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff	669	pci_intx(pdev, 1);
1da177e4 LT	670
	671	if (combined) {
	672	port_info[sata_chan] = &piix_port_info[ent->driver_data];
	673	port_info[sata_chan]->host_flags \|= ATA_FLAG_SLAVE_POSS;
	674	port_info[pata_chan] = &piix_port_info[ich5_pata];
1da177e4	675
6248e647 JG	676	dev_printk(KERN_WARNING, &pdev->dev,
	677	"combined mode detected (p=%u, s=%u)\n",
	678	pata_chan, sata_chan);
1da177e4 LT	679	}
1da177e4 LT	680
fbf30fba	681	return ata_pci_init_one(pdev, port_info, 2);
1da177e4 LT	682	}
1da177e4 LT	683
1da177e4 LT	684	static int __init piix_init(void)
	685	{
	686	int rc;
	687
	688	DPRINTK("pci_module_init\n");
	689	rc = pci_module_init(&piix_pci_driver);
	690	if (rc)
	691	return rc;
	692
	693	in_module_init = 0;
	694
	695	DPRINTK("done\n");
	696	return 0;
	697	}
	698
1da177e4 LT	699	static void __exit piix_exit(void)
	700	{
	701	pci_unregister_driver(&piix_pci_driver);
	702	}
	703
	704	module_init(piix_init);
	705	module_exit(piix_exit);
	706