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Linux v2.6.13-rc7
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / ata_piix.c
CommitLineData
1da177e4
LT		 1/*
2
3 ata_piix.c - Intel PATA/SATA controllers
4
5 Maintained by: Jeff Garzik <jgarzik@pobox.com>
6 Please ALWAYS copy linux-ide@vger.kernel.org
7 on emails.
8
9
10 Copyright 2003-2004 Red Hat Inc
11 Copyright 2003-2004 Jeff Garzik
12
13
14 Copyright header from piix.c:
15
16 Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
17 Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
18 Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
19
20 May be copied or modified under the terms of the GNU General Public License
21
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/init.h>
28#include <linux/blkdev.h>
29#include <linux/delay.h>
30#include "scsi.h"
31#include <scsi/scsi_host.h>
32#include <linux/libata.h>
33
34#define DRV_NAME "ata_piix"
6885433c 35#define DRV_VERSION "1.04"
1da177e4
LT		 36
37enum {
38 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
39 ICH5_PMR = 0x90, /* port mapping register */
40 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 41 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4
LT		 42
43 PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
44 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
45 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
46
47 /* combined mode. if set, PATA is channel 0.
48 * if clear, PATA is channel 1.
49 */
50 PIIX_COMB_PATA_P0 = (1 << 1),
51 PIIX_COMB = (1 << 2), /* combined mode enabled? */
52
53 PIIX_PORT_PRESENT = (1 << 0),
54 PIIX_PORT_ENABLED = (1 << 4),
55
56 PIIX_80C_PRI = (1 << 5) | (1 << 4),
57 PIIX_80C_SEC = (1 << 7) | (1 << 6),
58
59 ich5_pata = 0,
60 ich5_sata = 1,
61 piix4_pata = 2,
62 ich6_sata = 3,
63 ich6_sata_rm = 4,
64 ich7_sata = 5,
c368ca4e 65 esb2_sata = 6,
7b6dbd68
GF		 66
67 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 68};
69
70static int piix_init_one (struct pci_dev *pdev,
71 const struct pci_device_id *ent);
72
73static void piix_pata_phy_reset(struct ata_port *ap);
74static void piix_sata_phy_reset(struct ata_port *ap);
75static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
76static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
77
78static unsigned int in_module_init = 1;
79
80static struct pci_device_id piix_pci_tbl[] = {
81#ifdef ATA_ENABLE_PATA
82 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
83 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
84 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
85#endif
86
87 /* NOTE: The following PCI ids must be kept in sync with the
88 * list in drivers/pci/quirks.c.
89 */
90
91 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
92 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
93 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
94 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
95 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
96 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
97 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
98 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
99 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
c368ca4e 100 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb2_sata },
1da177e4
LT		 101
102 { } /* terminate list */
103};
104
105static struct pci_driver piix_pci_driver = {
106 .name = DRV_NAME,
107 .id_table = piix_pci_tbl,
108 .probe = piix_init_one,
109 .remove = ata_pci_remove_one,
110};
111
112static Scsi_Host_Template piix_sht = {
113 .module = THIS_MODULE,
114 .name = DRV_NAME,
115 .ioctl = ata_scsi_ioctl,
116 .queuecommand = ata_scsi_queuecmd,
117 .eh_strategy_handler = ata_scsi_error,
118 .can_queue = ATA_DEF_QUEUE,
119 .this_id = ATA_SHT_THIS_ID,
120 .sg_tablesize = LIBATA_MAX_PRD,
121 .max_sectors = ATA_MAX_SECTORS,
122 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
123 .emulated = ATA_SHT_EMULATED,
124 .use_clustering = ATA_SHT_USE_CLUSTERING,
125 .proc_name = DRV_NAME,
126 .dma_boundary = ATA_DMA_BOUNDARY,
127 .slave_configure = ata_scsi_slave_config,
128 .bios_param = ata_std_bios_param,
129 .ordered_flush = 1,
130};
131
132static struct ata_port_operations piix_pata_ops = {
133 .port_disable = ata_port_disable,
134 .set_piomode = piix_set_piomode,
135 .set_dmamode = piix_set_dmamode,
136
137 .tf_load = ata_tf_load,
138 .tf_read = ata_tf_read,
139 .check_status = ata_check_status,
140 .exec_command = ata_exec_command,
141 .dev_select = ata_std_dev_select,
142
143 .phy_reset = piix_pata_phy_reset,
144
145 .bmdma_setup = ata_bmdma_setup,
146 .bmdma_start = ata_bmdma_start,
147 .bmdma_stop = ata_bmdma_stop,
148 .bmdma_status = ata_bmdma_status,
149 .qc_prep = ata_qc_prep,
150 .qc_issue = ata_qc_issue_prot,
151
152 .eng_timeout = ata_eng_timeout,
153
154 .irq_handler = ata_interrupt,
155 .irq_clear = ata_bmdma_irq_clear,
156
157 .port_start = ata_port_start,
158 .port_stop = ata_port_stop,
aa8f0dc6 159 .host_stop = ata_host_stop,
1da177e4
LT		 160};
161
162static struct ata_port_operations piix_sata_ops = {
163 .port_disable = ata_port_disable,
164
165 .tf_load = ata_tf_load,
166 .tf_read = ata_tf_read,
167 .check_status = ata_check_status,
168 .exec_command = ata_exec_command,
169 .dev_select = ata_std_dev_select,
170
171 .phy_reset = piix_sata_phy_reset,
172
173 .bmdma_setup = ata_bmdma_setup,
174 .bmdma_start = ata_bmdma_start,
175 .bmdma_stop = ata_bmdma_stop,
176 .bmdma_status = ata_bmdma_status,
177 .qc_prep = ata_qc_prep,
178 .qc_issue = ata_qc_issue_prot,
179
180 .eng_timeout = ata_eng_timeout,
181
182 .irq_handler = ata_interrupt,
183 .irq_clear = ata_bmdma_irq_clear,
184
185 .port_start = ata_port_start,
186 .port_stop = ata_port_stop,
aa8f0dc6 187 .host_stop = ata_host_stop,
1da177e4
LT		 188};
189
190static struct ata_port_info piix_port_info[] = {
191 /* ich5_pata */
192 {
193 .sht = &piix_sht,
194 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
195 PIIX_FLAG_CHECKINTR,
196 .pio_mask = 0x1f, /* pio0-4 */
197#if 0
198 .mwdma_mask = 0x06, /* mwdma1-2 */
199#else
200 .mwdma_mask = 0x00, /* mwdma broken */
201#endif
202 .udma_mask = 0x3f, /* udma0-5 */
203 .port_ops = &piix_pata_ops,
204 },
205
206 /* ich5_sata */
207 {
208 .sht = &piix_sht,
209 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
210 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
211 .pio_mask = 0x1f, /* pio0-4 */
212 .mwdma_mask = 0x07, /* mwdma0-2 */
213 .udma_mask = 0x7f, /* udma0-6 */
214 .port_ops = &piix_sata_ops,
215 },
216
217 /* piix4_pata */
218 {
219 .sht = &piix_sht,
220 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
221 .pio_mask = 0x1f, /* pio0-4 */
222#if 0
223 .mwdma_mask = 0x06, /* mwdma1-2 */
224#else
225 .mwdma_mask = 0x00, /* mwdma broken */
226#endif
227 .udma_mask = ATA_UDMA_MASK_40C,
228 .port_ops = &piix_pata_ops,
229 },
230
231 /* ich6_sata */
232 {
233 .sht = &piix_sht,
234 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
235 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
236 ATA_FLAG_SLAVE_POSS,
237 .pio_mask = 0x1f, /* pio0-4 */
238 .mwdma_mask = 0x07, /* mwdma0-2 */
239 .udma_mask = 0x7f, /* udma0-6 */
240 .port_ops = &piix_sata_ops,
241 },
242
243 /* ich6_sata_rm */
244 {
245 .sht = &piix_sht,
246 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
247 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
248 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
249 .pio_mask = 0x1f, /* pio0-4 */
250 .mwdma_mask = 0x07, /* mwdma0-2 */
251 .udma_mask = 0x7f, /* udma0-6 */
252 .port_ops = &piix_sata_ops,
253 },
254
255 /* ich7_sata */
256 {
257 .sht = &piix_sht,
258 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
259 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
260 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
261 .pio_mask = 0x1f, /* pio0-4 */
262 .mwdma_mask = 0x07, /* mwdma0-2 */
263 .udma_mask = 0x7f, /* udma0-6 */
264 .port_ops = &piix_sata_ops,
265 },
c368ca4e
JG		 266
267 /* esb2_sata */
268 {
269 .sht = &piix_sht,
270 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
271 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
272 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
273 .pio_mask = 0x1f, /* pio0-4 */
274 .mwdma_mask = 0x07, /* mwdma0-2 */
275 .udma_mask = 0x7f, /* udma0-6 */
276 .port_ops = &piix_sata_ops,
277 },
1da177e4
LT		 278};
279
280static struct pci_bits piix_enable_bits[] = {
281 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
282 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
283};
284
285MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
286MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
287MODULE_LICENSE("GPL");
288MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
289MODULE_VERSION(DRV_VERSION);
290
291/**
292 * piix_pata_cbl_detect - Probe host controller cable detect info
293 * @ap: Port for which cable detect info is desired
294 *
295 * Read 80c cable indicator from ATA PCI device's PCI config
296 * register. This register is normally set by firmware (BIOS).
297 *
298 * LOCKING:
299 * None (inherited from caller).
300 */
301static void piix_pata_cbl_detect(struct ata_port *ap)
302{
303 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
304 u8 tmp, mask;
305
306 /* no 80c support in host controller? */
307 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
308 goto cbl40;
309
310 /* check BIOS cable detect results */
311 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
312 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
313 if ((tmp & mask) == 0)
314 goto cbl40;
315
316 ap->cbl = ATA_CBL_PATA80;
317 return;
318
319cbl40:
320 ap->cbl = ATA_CBL_PATA40;
321 ap->udma_mask &= ATA_UDMA_MASK_40C;
322}
323
324/**
325 * piix_pata_phy_reset - Probe specified port on PATA host controller
326 * @ap: Port to probe
327 *
328 * Probe PATA phy.
329 *
330 * LOCKING:
331 * None (inherited from caller).
332 */
333
334static void piix_pata_phy_reset(struct ata_port *ap)
335{
336 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
337
338 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
339 ata_port_disable(ap);
340 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
341 return;
342 }
343
344 piix_pata_cbl_detect(ap);
345
346 ata_port_probe(ap);
347
348 ata_bus_reset(ap);
349}
350
351/**
352 * piix_sata_probe - Probe PCI device for present SATA devices
353 * @ap: Port associated with the PCI device we wish to probe
354 *
355 * Reads SATA PCI device's PCI config register Port Configuration
356 * and Status (PCS) to determine port and device availability.
357 *
358 * LOCKING:
359 * None (inherited from caller).
360 *
361 * RETURNS:
362 * Non-zero if device detected, zero otherwise.
363 */
364static int piix_sata_probe (struct ata_port *ap)
365{
366 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
367 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
368 int orig_mask, mask, i;
369 u8 pcs;
370
371 mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
372 (PIIX_PORT_ENABLED << ap->hard_port_no);
373
374 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
375 orig_mask = (int) pcs & 0xff;
376
377 /* TODO: this is vaguely wrong for ICH6 combined mode,
378 * where only two of the four SATA ports are mapped
379 * onto a single ATA channel. It is also vaguely inaccurate
380 * for ICH5, which has only two ports. However, this is ok,
381 * as further device presence detection code will handle
382 * any false positives produced here.
383 */
384
385 for (i = 0; i < 4; i++) {
386 mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i);
387
388 if ((orig_mask & mask) == mask)
389 if (combined || (i == ap->hard_port_no))
390 return 1;
391 }
392
393 return 0;
394}
395
396/**
397 * piix_sata_phy_reset - Probe specified port on SATA host controller
398 * @ap: Port to probe
399 *
400 * Probe SATA phy.
401 *
402 * LOCKING:
403 * None (inherited from caller).
404 */
405
406static void piix_sata_phy_reset(struct ata_port *ap)
407{
408 if (!piix_sata_probe(ap)) {
409 ata_port_disable(ap);
410 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
411 return;
412 }
413
414 ap->cbl = ATA_CBL_SATA;
415
416 ata_port_probe(ap);
417
418 ata_bus_reset(ap);
419}
420
421/**
422 * piix_set_piomode - Initialize host controller PATA PIO timings
423 * @ap: Port whose timings we are configuring
424 * @adev: um
425 * @pio: PIO mode, 0 - 4
426 *
427 * Set PIO mode for device, in host controller PCI config space.
428 *
429 * LOCKING:
430 * None (inherited from caller).
431 */
432
433static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
434{
435 unsigned int pio = adev->pio_mode - XFER_PIO_0;
436 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
437 unsigned int is_slave = (adev->devno != 0);
438 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
439 unsigned int slave_port = 0x44;
440 u16 master_data;
441 u8 slave_data;
442
443 static const /* ISP RTC */
444 u8 timings[][2] = { { 0, 0 },
445 { 0, 0 },
446 { 1, 0 },
447 { 2, 1 },
448 { 2, 3 }, };
449
450 pci_read_config_word(dev, master_port, &master_data);
451 if (is_slave) {
452 master_data |= 0x4000;
453 /* enable PPE, IE and TIME */
454 master_data |= 0x0070;
455 pci_read_config_byte(dev, slave_port, &slave_data);
456 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
457 slave_data |=
458 (timings[pio][0] << 2) |
459 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
460 } else {
461 master_data &= 0xccf8;
462 /* enable PPE, IE and TIME */
463 master_data |= 0x0007;
464 master_data |=
465 (timings[pio][0] << 12) |
466 (timings[pio][1] << 8);
467 }
468 pci_write_config_word(dev, master_port, master_data);
469 if (is_slave)
470 pci_write_config_byte(dev, slave_port, slave_data);
471}
472
473/**
474 * piix_set_dmamode - Initialize host controller PATA PIO timings
475 * @ap: Port whose timings we are configuring
476 * @adev: um
477 * @udma: udma mode, 0 - 6
478 *
479 * Set UDMA mode for device, in host controller PCI config space.
480 *
481 * LOCKING:
482 * None (inherited from caller).
483 */
484
485static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
486{
487 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
488 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
489 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
490 u8 speed = udma;
491 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
492 int a_speed = 3 << (drive_dn * 4);
493 int u_flag = 1 << drive_dn;
494 int v_flag = 0x01 << drive_dn;
495 int w_flag = 0x10 << drive_dn;
496 int u_speed = 0;
497 int sitre;
498 u16 reg4042, reg4a;
499 u8 reg48, reg54, reg55;
500
501 pci_read_config_word(dev, maslave, &reg4042);
502 DPRINTK("reg4042 = 0x%04x\n", reg4042);
503 sitre = (reg4042 & 0x4000) ? 1 : 0;
504 pci_read_config_byte(dev, 0x48, &reg48);
505 pci_read_config_word(dev, 0x4a, &reg4a);
506 pci_read_config_byte(dev, 0x54, &reg54);
507 pci_read_config_byte(dev, 0x55, &reg55);
508
509 switch(speed) {
510 case XFER_UDMA_4:
511 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
512 case XFER_UDMA_6:
513 case XFER_UDMA_5:
514 case XFER_UDMA_3:
515 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
516 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
517 case XFER_MW_DMA_2:
518 case XFER_MW_DMA_1: break;
519 default:
520 BUG();
521 return;
522 }
523
524 if (speed >= XFER_UDMA_0) {
525 if (!(reg48 & u_flag))
526 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
527 if (speed == XFER_UDMA_5) {
528 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
529 } else {
530 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
531 }
532 if ((reg4a & a_speed) != u_speed)
533 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
534 if (speed > XFER_UDMA_2) {
535 if (!(reg54 & v_flag))
536 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
537 } else
538 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
539 } else {
540 if (reg48 & u_flag)
541 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
542 if (reg4a & a_speed)
543 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
544 if (reg54 & v_flag)
545 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
546 if (reg55 & w_flag)
547 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
548 }
549}
550
551/* move to PCI layer, integrate w/ MSI stuff */
552static void pci_enable_intx(struct pci_dev *pdev)
553{
554 u16 pci_command;
555
556 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
557 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
558 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
559 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
560 }
561}
562
563#define AHCI_PCI_BAR 5
564#define AHCI_GLOBAL_CTL 0x04
565#define AHCI_ENABLE (1 << 31)
566static int piix_disable_ahci(struct pci_dev *pdev)
567{
568 void *mmio;
569 unsigned long addr;
570 u32 tmp;
571 int rc = 0;
572
573 /* BUG: pci_enable_device has not yet been called. This
574 * works because this device is usually set up by BIOS.
575 */
576
577 addr = pci_resource_start(pdev, AHCI_PCI_BAR);
578 if (!addr || !pci_resource_len(pdev, AHCI_PCI_BAR))
579 return 0;
7b6dbd68 580
1da177e4
LT		 581 mmio = ioremap(addr, 64);
582 if (!mmio)
583 return -ENOMEM;
7b6dbd68 584
1da177e4
LT		 585 tmp = readl(mmio + AHCI_GLOBAL_CTL);
586 if (tmp & AHCI_ENABLE) {
587 tmp &= ~AHCI_ENABLE;
588 writel(tmp, mmio + AHCI_GLOBAL_CTL);
589
590 tmp = readl(mmio + AHCI_GLOBAL_CTL);
591 if (tmp & AHCI_ENABLE)
592 rc = -EIO;
593 }
7b6dbd68 594
1da177e4
LT		 595 iounmap(mmio);
596 return rc;
597}
598
599/**
600 * piix_init_one - Register PIIX ATA PCI device with kernel services
601 * @pdev: PCI device to register
602 * @ent: Entry in piix_pci_tbl matching with @pdev
603 *
604 * Called from kernel PCI layer. We probe for combined mode (sigh),
605 * and then hand over control to libata, for it to do the rest.
606 *
607 * LOCKING:
608 * Inherited from PCI layer (may sleep).
609 *
610 * RETURNS:
611 * Zero on success, or -ERRNO value.
612 */
613
614static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
615{
616 static int printed_version;
617 struct ata_port_info *port_info[2];
618 unsigned int combined = 0, n_ports = 1;
619 unsigned int pata_chan = 0, sata_chan = 0;
620
621 if (!printed_version++)
622 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
623
624 /* no hotplugging support (FIXME) */
625 if (!in_module_init)
626 return -ENODEV;
627
628 port_info[0] = &piix_port_info[ent->driver_data];
629 port_info[1] = NULL;
630
631 if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
7b6dbd68
GF		 632 u8 tmp;
633 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
634 if (tmp == PIIX_AHCI_DEVICE) {
635 int rc = piix_disable_ahci(pdev);
636 if (rc)
637 return rc;
638 }
1da177e4
LT		 639 }
640
641 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
642 u8 tmp;
643 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
644
645 if (tmp & PIIX_COMB) {
646 combined = 1;
647 if (tmp & PIIX_COMB_PATA_P0)
648 sata_chan = 1;
649 else
650 pata_chan = 1;
651 }
652 }
653
654 /* On ICH5, some BIOSen disable the interrupt using the
655 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
656 * On ICH6, this bit has the same effect, but only when
657 * MSI is disabled (and it is disabled, as we don't use
658 * message-signalled interrupts currently).
659 */
660 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
661 pci_enable_intx(pdev);
662
663 if (combined) {
664 port_info[sata_chan] = &piix_port_info[ent->driver_data];
665 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
666 port_info[pata_chan] = &piix_port_info[ich5_pata];
667 n_ports++;
668
669 printk(KERN_WARNING DRV_NAME ": combined mode detected\n");
670 }
671
672 return ata_pci_init_one(pdev, port_info, n_ports);
673}
674
1da177e4
LT		 675static int __init piix_init(void)
676{
677 int rc;
678
679 DPRINTK("pci_module_init\n");
680 rc = pci_module_init(&piix_pci_driver);
681 if (rc)
682 return rc;
683
684 in_module_init = 0;
685
686 DPRINTK("done\n");
687 return 0;
688}
689
1da177e4
LT		 690static void __exit piix_exit(void)
691{
692 pci_unregister_driver(&piix_pci_driver);
693}
694
695module_init(piix_init);
696module_exit(piix_exit);
697
kernel source for telekom puls (alcatel/mediatek)