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[libata ahci] minor remove/unplug path cleanup
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
1da177e4
LT		 44#include "scsi.h"
45#include <scsi/scsi_host.h>
46#include <linux/libata.h>
47#include <asm/io.h>
48
49#define DRV_NAME "ahci"
ead5de99 50#define DRV_VERSION "1.01"
1da177e4
LT		 51
52
53enum {
54 AHCI_PCI_BAR = 5,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
58 AHCI_CMD_SLOT_SZ = 32 * 32,
59 AHCI_RX_FIS_SZ = 256,
60 AHCI_CMD_TBL_HDR = 0x80,
a0ea7328 61 AHCI_CMD_TBL_CDB = 0x40,
1da177e4
LT		 62 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
63 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
64 AHCI_RX_FIS_SZ,
65 AHCI_IRQ_ON_SG = (1 << 31),
66 AHCI_CMD_ATAPI = (1 << 5),
67 AHCI_CMD_WRITE = (1 << 6),
68
69 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
70
71 board_ahci = 0,
72
73 /* global controller registers */
74 HOST_CAP = 0x00, /* host capabilities */
75 HOST_CTL = 0x04, /* global host control */
76 HOST_IRQ_STAT = 0x08, /* interrupt status */
77 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
78 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
79
80 /* HOST_CTL bits */
81 HOST_RESET = (1 << 0), /* reset controller; self-clear */
82 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
83 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
84
85 /* HOST_CAP bits */
86 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
87
88 /* registers for each SATA port */
89 PORT_LST_ADDR = 0x00, /* command list DMA addr */
90 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
91 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
92 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
93 PORT_IRQ_STAT = 0x10, /* interrupt status */
94 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
95 PORT_CMD = 0x18, /* port command */
96 PORT_TFDATA = 0x20, /* taskfile data */
97 PORT_SIG = 0x24, /* device TF signature */
98 PORT_CMD_ISSUE = 0x38, /* command issue */
99 PORT_SCR = 0x28, /* SATA phy register block */
100 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
101 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
102 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
103 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
104
105 /* PORT_IRQ_{STAT,MASK} bits */
106 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
107 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
108 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
109 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
110 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
111 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
112 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
113 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
114
115 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
116 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
117 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
118 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
119 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
120 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
121 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
122 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
123 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
124
125 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
126 PORT_IRQ_HBUS_ERR |
127 PORT_IRQ_HBUS_DATA_ERR |
128 PORT_IRQ_IF_ERR,
129 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
130 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
131 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
132 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
133 PORT_IRQ_D2H_REG_FIS,
134
135 /* PORT_CMD bits */
136 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
137 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
138 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
139 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
140 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
141 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
142
143 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
144 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
145 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 146
147 /* hpriv->flags bits */
148 AHCI_FLAG_MSI = (1 << 0),
1da177e4
LT		 149};
150
151struct ahci_cmd_hdr {
152 u32 opts;
153 u32 status;
154 u32 tbl_addr;
155 u32 tbl_addr_hi;
156 u32 reserved[4];
157};
158
159struct ahci_sg {
160 u32 addr;
161 u32 addr_hi;
162 u32 reserved;
163 u32 flags_size;
164};
165
166struct ahci_host_priv {
167 unsigned long flags;
168 u32 cap; /* cache of HOST_CAP register */
169 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
170};
171
172struct ahci_port_priv {
173 struct ahci_cmd_hdr *cmd_slot;
174 dma_addr_t cmd_slot_dma;
175 void *cmd_tbl;
176 dma_addr_t cmd_tbl_dma;
177 struct ahci_sg *cmd_tbl_sg;
178 void *rx_fis;
179 dma_addr_t rx_fis_dma;
180};
181
182static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
183static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
184static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
185static int ahci_qc_issue(struct ata_queued_cmd *qc);
186static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
187static void ahci_phy_reset(struct ata_port *ap);
188static void ahci_irq_clear(struct ata_port *ap);
189static void ahci_eng_timeout(struct ata_port *ap);
190static int ahci_port_start(struct ata_port *ap);
191static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 192static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
193static void ahci_qc_prep(struct ata_queued_cmd *qc);
194static u8 ahci_check_status(struct ata_port *ap);
195static u8 ahci_check_err(struct ata_port *ap);
196static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
907f4678 197static void ahci_remove_one (struct pci_dev *pdev);
1da177e4
LT		 198
199static Scsi_Host_Template ahci_sht = {
200 .module = THIS_MODULE,
201 .name = DRV_NAME,
202 .ioctl = ata_scsi_ioctl,
203 .queuecommand = ata_scsi_queuecmd,
204 .eh_strategy_handler = ata_scsi_error,
205 .can_queue = ATA_DEF_QUEUE,
206 .this_id = ATA_SHT_THIS_ID,
207 .sg_tablesize = AHCI_MAX_SG,
208 .max_sectors = ATA_MAX_SECTORS,
209 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
210 .emulated = ATA_SHT_EMULATED,
211 .use_clustering = AHCI_USE_CLUSTERING,
212 .proc_name = DRV_NAME,
213 .dma_boundary = AHCI_DMA_BOUNDARY,
214 .slave_configure = ata_scsi_slave_config,
215 .bios_param = ata_std_bios_param,
216 .ordered_flush = 1,
217};
218
219static struct ata_port_operations ahci_ops = {
220 .port_disable = ata_port_disable,
221
222 .check_status = ahci_check_status,
223 .check_altstatus = ahci_check_status,
224 .check_err = ahci_check_err,
225 .dev_select = ata_noop_dev_select,
226
227 .tf_read = ahci_tf_read,
228
229 .phy_reset = ahci_phy_reset,
230
231 .qc_prep = ahci_qc_prep,
232 .qc_issue = ahci_qc_issue,
233
234 .eng_timeout = ahci_eng_timeout,
235
236 .irq_handler = ahci_interrupt,
237 .irq_clear = ahci_irq_clear,
238
239 .scr_read = ahci_scr_read,
240 .scr_write = ahci_scr_write,
241
242 .port_start = ahci_port_start,
243 .port_stop = ahci_port_stop,
1da177e4
LT		 244};
245
246static struct ata_port_info ahci_port_info[] = {
247 /* board_ahci */
248 {
249 .sht = &ahci_sht,
250 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
251 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
252 ATA_FLAG_PIO_DMA,
253 .pio_mask = 0x03, /* pio3-4 */
254 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
255 .port_ops = &ahci_ops,
256 },
257};
258
259static struct pci_device_id ahci_pci_tbl[] = {
260 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ICH6 */
262 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH6M */
264 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH7 */
266 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7M */
268 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7R */
270 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ULi M5288 */
680d3235
JG		 272 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ESB2 */
274 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
3db368f7
JG		 278 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ICH7-M DH */
1da177e4
LT		 280 { } /* terminate list */
281};
282
283
284static struct pci_driver ahci_pci_driver = {
285 .name = DRV_NAME,
286 .id_table = ahci_pci_tbl,
287 .probe = ahci_init_one,
907f4678 288 .remove = ahci_remove_one,
1da177e4
LT		 289};
290
291
292static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
293{
294 return base + 0x100 + (port * 0x80);
295}
296
297static inline void *ahci_port_base (void *base, unsigned int port)
298{
299 return (void *) ahci_port_base_ul((unsigned long)base, port);
300}
301
1da177e4
LT		 302static int ahci_port_start(struct ata_port *ap)
303{
304 struct device *dev = ap->host_set->dev;
305 struct ahci_host_priv *hpriv = ap->host_set->private_data;
306 struct ahci_port_priv *pp;
1da177e4
LT		 307 void *mem, *mmio = ap->host_set->mmio_base;
308 void *port_mmio = ahci_port_base(mmio, ap->port_no);
309 dma_addr_t mem_dma;
310
1da177e4 311 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
0a139e79
TH		 312 if (!pp)
313 return -ENOMEM;
1da177e4
LT		 314 memset(pp, 0, sizeof(*pp));
315
316 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
317 if (!mem) {
0a139e79
TH		 318 kfree(pp);
319 return -ENOMEM;
1da177e4
LT		 320 }
321 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
322
323 /*
324 * First item in chunk of DMA memory: 32-slot command table,
325 * 32 bytes each in size
326 */
327 pp->cmd_slot = mem;
328 pp->cmd_slot_dma = mem_dma;
329
330 mem += AHCI_CMD_SLOT_SZ;
331 mem_dma += AHCI_CMD_SLOT_SZ;
332
333 /*
334 * Second item: Received-FIS area
335 */
336 pp->rx_fis = mem;
337 pp->rx_fis_dma = mem_dma;
338
339 mem += AHCI_RX_FIS_SZ;
340 mem_dma += AHCI_RX_FIS_SZ;
341
342 /*
343 * Third item: data area for storing a single command
344 * and its scatter-gather table
345 */
346 pp->cmd_tbl = mem;
347 pp->cmd_tbl_dma = mem_dma;
348
349 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
350
351 ap->private_data = pp;
352
353 if (hpriv->cap & HOST_CAP_64)
354 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
355 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
356 readl(port_mmio + PORT_LST_ADDR); /* flush */
357
358 if (hpriv->cap & HOST_CAP_64)
359 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
360 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
361 readl(port_mmio + PORT_FIS_ADDR); /* flush */
362
363 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
364 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
365 PORT_CMD_START, port_mmio + PORT_CMD);
366 readl(port_mmio + PORT_CMD); /* flush */
367
368 return 0;
1da177e4
LT		 369}
370
371
372static void ahci_port_stop(struct ata_port *ap)
373{
374 struct device *dev = ap->host_set->dev;
375 struct ahci_port_priv *pp = ap->private_data;
376 void *mmio = ap->host_set->mmio_base;
377 void *port_mmio = ahci_port_base(mmio, ap->port_no);
378 u32 tmp;
379
380 tmp = readl(port_mmio + PORT_CMD);
381 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
382 writel(tmp, port_mmio + PORT_CMD);
383 readl(port_mmio + PORT_CMD); /* flush */
384
385 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
386 * this is slightly incorrect.
387 */
388 msleep(500);
389
390 ap->private_data = NULL;
391 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
392 pp->cmd_slot, pp->cmd_slot_dma);
393 kfree(pp);
1da177e4
LT		 394}
395
396static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
397{
398 unsigned int sc_reg;
399
400 switch (sc_reg_in) {
401 case SCR_STATUS: sc_reg = 0; break;
402 case SCR_CONTROL: sc_reg = 1; break;
403 case SCR_ERROR: sc_reg = 2; break;
404 case SCR_ACTIVE: sc_reg = 3; break;
405 default:
406 return 0xffffffffU;
407 }
408
409 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
410}
411
412
413static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
414 u32 val)
415{
416 unsigned int sc_reg;
417
418 switch (sc_reg_in) {
419 case SCR_STATUS: sc_reg = 0; break;
420 case SCR_CONTROL: sc_reg = 1; break;
421 case SCR_ERROR: sc_reg = 2; break;
422 case SCR_ACTIVE: sc_reg = 3; break;
423 default:
424 return;
425 }
426
427 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
428}
429
430static void ahci_phy_reset(struct ata_port *ap)
431{
432 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
433 struct ata_taskfile tf;
434 struct ata_device *dev = &ap->device[0];
435 u32 tmp;
436
437 __sata_phy_reset(ap);
438
439 if (ap->flags & ATA_FLAG_PORT_DISABLED)
440 return;
441
442 tmp = readl(port_mmio + PORT_SIG);
443 tf.lbah = (tmp >> 24) & 0xff;
444 tf.lbam = (tmp >> 16) & 0xff;
445 tf.lbal = (tmp >> 8) & 0xff;
446 tf.nsect = (tmp) & 0xff;
447
448 dev->class = ata_dev_classify(&tf);
449 if (!ata_dev_present(dev))
450 ata_port_disable(ap);
451}
452
453static u8 ahci_check_status(struct ata_port *ap)
454{
455 void *mmio = (void *) ap->ioaddr.cmd_addr;
456
457 return readl(mmio + PORT_TFDATA) & 0xFF;
458}
459
460static u8 ahci_check_err(struct ata_port *ap)
461{
462 void *mmio = (void *) ap->ioaddr.cmd_addr;
463
464 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
465}
466
467static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
468{
469 struct ahci_port_priv *pp = ap->private_data;
470 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
471
472 ata_tf_from_fis(d2h_fis, tf);
473}
474
475static void ahci_fill_sg(struct ata_queued_cmd *qc)
476{
477 struct ahci_port_priv *pp = qc->ap->private_data;
478 unsigned int i;
479
480 VPRINTK("ENTER\n");
481
482 /*
483 * Next, the S/G list.
484 */
485 for (i = 0; i < qc->n_elem; i++) {
486 u32 sg_len;
487 dma_addr_t addr;
488
489 addr = sg_dma_address(&qc->sg[i]);
490 sg_len = sg_dma_len(&qc->sg[i]);
491
492 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
493 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
494 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
495 }
496}
497
498static void ahci_qc_prep(struct ata_queued_cmd *qc)
499{
a0ea7328
JG		 500 struct ata_port *ap = qc->ap;
501 struct ahci_port_priv *pp = ap->private_data;
1da177e4
LT		 502 u32 opts;
503 const u32 cmd_fis_len = 5; /* five dwords */
504
505 /*
506 * Fill in command slot information (currently only one slot,
507 * slot 0, is currently since we don't do queueing)
508 */
509
510 opts = (qc->n_elem << 16) | cmd_fis_len;
511 if (qc->tf.flags & ATA_TFLAG_WRITE)
512 opts |= AHCI_CMD_WRITE;
a0ea7328 513 if (is_atapi_taskfile(&qc->tf))
1da177e4 514 opts |= AHCI_CMD_ATAPI;
1da177e4
LT		 515
516 pp->cmd_slot[0].opts = cpu_to_le32(opts);
517 pp->cmd_slot[0].status = 0;
518 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
519 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
520
521 /*
522 * Fill in command table information. First, the header,
523 * a SATA Register - Host to Device command FIS.
524 */
525 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
a0ea7328
JG		 526 if (opts & AHCI_CMD_ATAPI) {
527 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
528 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
529 }
1da177e4
LT		 530
531 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
532 return;
533
534 ahci_fill_sg(qc);
535}
536
537static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
538{
539 void *mmio = ap->host_set->mmio_base;
540 void *port_mmio = ahci_port_base(mmio, ap->port_no);
541 u32 tmp;
542 int work;
543
544 /* stop DMA */
545 tmp = readl(port_mmio + PORT_CMD);
546 tmp &= ~PORT_CMD_START;
547 writel(tmp, port_mmio + PORT_CMD);
548
549 /* wait for engine to stop. TODO: this could be
550 * as long as 500 msec
551 */
552 work = 1000;
553 while (work-- > 0) {
554 tmp = readl(port_mmio + PORT_CMD);
555 if ((tmp & PORT_CMD_LIST_ON) == 0)
556 break;
557 udelay(10);
558 }
559
560 /* clear SATA phy error, if any */
561 tmp = readl(port_mmio + PORT_SCR_ERR);
562 writel(tmp, port_mmio + PORT_SCR_ERR);
563
564 /* if DRQ/BSY is set, device needs to be reset.
565 * if so, issue COMRESET
566 */
567 tmp = readl(port_mmio + PORT_TFDATA);
568 if (tmp & (ATA_BUSY | ATA_DRQ)) {
569 writel(0x301, port_mmio + PORT_SCR_CTL);
570 readl(port_mmio + PORT_SCR_CTL); /* flush */
571 udelay(10);
572 writel(0x300, port_mmio + PORT_SCR_CTL);
573 readl(port_mmio + PORT_SCR_CTL); /* flush */
574 }
575
576 /* re-start DMA */
577 tmp = readl(port_mmio + PORT_CMD);
578 tmp |= PORT_CMD_START;
579 writel(tmp, port_mmio + PORT_CMD);
580 readl(port_mmio + PORT_CMD); /* flush */
581
582 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
583}
584
585static void ahci_eng_timeout(struct ata_port *ap)
586{
b8f6153e
JG		 587 struct ata_host_set *host_set = ap->host_set;
588 void *mmio = host_set->mmio_base;
1da177e4
LT		 589 void *port_mmio = ahci_port_base(mmio, ap->port_no);
590 struct ata_queued_cmd *qc;
b8f6153e 591 unsigned long flags;
1da177e4
LT		 592
593 DPRINTK("ENTER\n");
594
b8f6153e
JG		 595 spin_lock_irqsave(&host_set->lock, flags);
596
1da177e4
LT		 597 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
598
599 qc = ata_qc_from_tag(ap, ap->active_tag);
600 if (!qc) {
601 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
602 ap->id);
603 } else {
604 /* hack alert! We cannot use the supplied completion
605 * function from inside the ->eh_strategy_handler() thread.
606 * libata is the only user of ->eh_strategy_handler() in
607 * any kernel, so the default scsi_done() assumes it is
608 * not being called from the SCSI EH.
609 */
610 qc->scsidone = scsi_finish_command;
611 ata_qc_complete(qc, ATA_ERR);
612 }
613
b8f6153e 614 spin_unlock_irqrestore(&host_set->lock, flags);
1da177e4
LT		 615}
616
617static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
618{
619 void *mmio = ap->host_set->mmio_base;
620 void *port_mmio = ahci_port_base(mmio, ap->port_no);
621 u32 status, serr, ci;
622
623 serr = readl(port_mmio + PORT_SCR_ERR);
624 writel(serr, port_mmio + PORT_SCR_ERR);
625
626 status = readl(port_mmio + PORT_IRQ_STAT);
627 writel(status, port_mmio + PORT_IRQ_STAT);
628
629 ci = readl(port_mmio + PORT_CMD_ISSUE);
630 if (likely((ci & 0x1) == 0)) {
631 if (qc) {
632 ata_qc_complete(qc, 0);
633 qc = NULL;
634 }
635 }
636
637 if (status & PORT_IRQ_FATAL) {
638 ahci_intr_error(ap, status);
639 if (qc)
640 ata_qc_complete(qc, ATA_ERR);
641 }
642
643 return 1;
644}
645
646static void ahci_irq_clear(struct ata_port *ap)
647{
648 /* TODO */
649}
650
651static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
652{
653 struct ata_host_set *host_set = dev_instance;
654 struct ahci_host_priv *hpriv;
655 unsigned int i, handled = 0;
656 void *mmio;
657 u32 irq_stat, irq_ack = 0;
658
659 VPRINTK("ENTER\n");
660
661 hpriv = host_set->private_data;
662 mmio = host_set->mmio_base;
663
664 /* sigh. 0xffffffff is a valid return from h/w */
665 irq_stat = readl(mmio + HOST_IRQ_STAT);
666 irq_stat &= hpriv->port_map;
667 if (!irq_stat)
668 return IRQ_NONE;
669
670 spin_lock(&host_set->lock);
671
672 for (i = 0; i < host_set->n_ports; i++) {
673 struct ata_port *ap;
674 u32 tmp;
675
676 VPRINTK("port %u\n", i);
677 ap = host_set->ports[i];
678 tmp = irq_stat & (1 << i);
679 if (tmp && ap) {
680 struct ata_queued_cmd *qc;
681 qc = ata_qc_from_tag(ap, ap->active_tag);
682 if (ahci_host_intr(ap, qc))
683 irq_ack |= (1 << i);
684 }
685 }
686
687 if (irq_ack) {
688 writel(irq_ack, mmio + HOST_IRQ_STAT);
689 handled = 1;
690 }
691
692 spin_unlock(&host_set->lock);
693
694 VPRINTK("EXIT\n");
695
696 return IRQ_RETVAL(handled);
697}
698
699static int ahci_qc_issue(struct ata_queued_cmd *qc)
700{
701 struct ata_port *ap = qc->ap;
702 void *port_mmio = (void *) ap->ioaddr.cmd_addr;
703
1da177e4
LT		 704 writel(1, port_mmio + PORT_CMD_ISSUE);
705 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
706
707 return 0;
708}
709
710static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
711 unsigned int port_idx)
712{
713 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
714 base = ahci_port_base_ul(base, port_idx);
715 VPRINTK("base now==0x%lx\n", base);
716
717 port->cmd_addr = base;
718 port->scr_addr = base + PORT_SCR;
719
720 VPRINTK("EXIT\n");
721}
722
723static int ahci_host_init(struct ata_probe_ent *probe_ent)
724{
725 struct ahci_host_priv *hpriv = probe_ent->private_data;
726 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
727 void __iomem *mmio = probe_ent->mmio_base;
728 u32 tmp, cap_save;
729 u16 tmp16;
730 unsigned int i, j, using_dac;
731 int rc;
732 void __iomem *port_mmio;
733
734 cap_save = readl(mmio + HOST_CAP);
735 cap_save &= ( (1<<28) | (1<<17) );
736 cap_save |= (1 << 27);
737
738 /* global controller reset */
739 tmp = readl(mmio + HOST_CTL);
740 if ((tmp & HOST_RESET) == 0) {
741 writel(tmp | HOST_RESET, mmio + HOST_CTL);
742 readl(mmio + HOST_CTL); /* flush */
743 }
744
745 /* reset must complete within 1 second, or
746 * the hardware should be considered fried.
747 */
748 ssleep(1);
749
750 tmp = readl(mmio + HOST_CTL);
751 if (tmp & HOST_RESET) {
752 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
753 pci_name(pdev), tmp);
754 return -EIO;
755 }
756
757 writel(HOST_AHCI_EN, mmio + HOST_CTL);
758 (void) readl(mmio + HOST_CTL); /* flush */
759 writel(cap_save, mmio + HOST_CAP);
760 writel(0xf, mmio + HOST_PORTS_IMPL);
761 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
762
763 pci_read_config_word(pdev, 0x92, &tmp16);
764 tmp16 |= 0xf;
765 pci_write_config_word(pdev, 0x92, tmp16);
766
767 hpriv->cap = readl(mmio + HOST_CAP);
768 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
769 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
770
771 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
772 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
773
774 using_dac = hpriv->cap & HOST_CAP_64;
775 if (using_dac &&
776 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
777 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
778 if (rc) {
779 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
780 if (rc) {
781 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
782 pci_name(pdev));
783 return rc;
784 }
785 }
1da177e4
LT		 786 } else {
787 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
788 if (rc) {
789 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
790 pci_name(pdev));
791 return rc;
792 }
793 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
794 if (rc) {
795 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
796 pci_name(pdev));
797 return rc;
798 }
799 }
800
801 for (i = 0; i < probe_ent->n_ports; i++) {
802#if 0 /* BIOSen initialize this incorrectly */
803 if (!(hpriv->port_map & (1 << i)))
804 continue;
805#endif
806
807 port_mmio = ahci_port_base(mmio, i);
808 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
809
810 ahci_setup_port(&probe_ent->port[i],
811 (unsigned long) mmio, i);
812
813 /* make sure port is not active */
814 tmp = readl(port_mmio + PORT_CMD);
815 VPRINTK("PORT_CMD 0x%x\n", tmp);
816 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
817 PORT_CMD_FIS_RX | PORT_CMD_START)) {
818 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
819 PORT_CMD_FIS_RX | PORT_CMD_START);
820 writel(tmp, port_mmio + PORT_CMD);
821 readl(port_mmio + PORT_CMD); /* flush */
822
823 /* spec says 500 msecs for each bit, so
824 * this is slightly incorrect.
825 */
826 msleep(500);
827 }
828
829 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
830
831 j = 0;
832 while (j < 100) {
833 msleep(10);
834 tmp = readl(port_mmio + PORT_SCR_STAT);
835 if ((tmp & 0xf) == 0x3)
836 break;
837 j++;
838 }
839
840 tmp = readl(port_mmio + PORT_SCR_ERR);
841 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
842 writel(tmp, port_mmio + PORT_SCR_ERR);
843
844 /* ack any pending irq events for this port */
845 tmp = readl(port_mmio + PORT_IRQ_STAT);
846 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
847 if (tmp)
848 writel(tmp, port_mmio + PORT_IRQ_STAT);
849
850 writel(1 << i, mmio + HOST_IRQ_STAT);
851
852 /* set irq mask (enables interrupts) */
853 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
854 }
855
856 tmp = readl(mmio + HOST_CTL);
857 VPRINTK("HOST_CTL 0x%x\n", tmp);
858 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
859 tmp = readl(mmio + HOST_CTL);
860 VPRINTK("HOST_CTL 0x%x\n", tmp);
861
862 pci_set_master(pdev);
863
864 return 0;
865}
866
867/* move to PCI layer, integrate w/ MSI stuff */
907f4678 868static void pci_intx(struct pci_dev *pdev, int enable)
1da177e4 869{
907f4678 870 u16 pci_command, new;
1da177e4
LT		 871
872 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
907f4678
JG		 873
874 if (enable)
875 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
876 else
877 new = pci_command | PCI_COMMAND_INTX_DISABLE;
878
879 if (new != pci_command)
1da177e4 880 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
1da177e4
LT		 881}
882
883static void ahci_print_info(struct ata_probe_ent *probe_ent)
884{
885 struct ahci_host_priv *hpriv = probe_ent->private_data;
886 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
887 void *mmio = probe_ent->mmio_base;
888 u32 vers, cap, impl, speed;
889 const char *speed_s;
890 u16 cc;
891 const char *scc_s;
892
893 vers = readl(mmio + HOST_VERSION);
894 cap = hpriv->cap;
895 impl = hpriv->port_map;
896
897 speed = (cap >> 20) & 0xf;
898 if (speed == 1)
899 speed_s = "1.5";
900 else if (speed == 2)
901 speed_s = "3";
902 else
903 speed_s = "?";
904
905 pci_read_config_word(pdev, 0x0a, &cc);
906 if (cc == 0x0101)
907 scc_s = "IDE";
908 else if (cc == 0x0106)
909 scc_s = "SATA";
910 else if (cc == 0x0104)
911 scc_s = "RAID";
912 else
913 scc_s = "unknown";
914
915 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
916 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
917 ,
918 pci_name(pdev),
919
920 (vers >> 24) & 0xff,
921 (vers >> 16) & 0xff,
922 (vers >> 8) & 0xff,
923 vers & 0xff,
924
925 ((cap >> 8) & 0x1f) + 1,
926 (cap & 0x1f) + 1,
927 speed_s,
928 impl,
929 scc_s);
930
931 printk(KERN_INFO DRV_NAME "(%s) flags: "
932 "%s%s%s%s%s%s"
933 "%s%s%s%s%s%s%s\n"
934 ,
935 pci_name(pdev),
936
937 cap & (1 << 31) ? "64bit " : "",
938 cap & (1 << 30) ? "ncq " : "",
939 cap & (1 << 28) ? "ilck " : "",
940 cap & (1 << 27) ? "stag " : "",
941 cap & (1 << 26) ? "pm " : "",
942 cap & (1 << 25) ? "led " : "",
943
944 cap & (1 << 24) ? "clo " : "",
945 cap & (1 << 19) ? "nz " : "",
946 cap & (1 << 18) ? "only " : "",
947 cap & (1 << 17) ? "pmp " : "",
948 cap & (1 << 15) ? "pio " : "",
949 cap & (1 << 14) ? "slum " : "",
950 cap & (1 << 13) ? "part " : ""
951 );
952}
953
954static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
955{
956 static int printed_version;
957 struct ata_probe_ent *probe_ent = NULL;
958 struct ahci_host_priv *hpriv;
959 unsigned long base;
960 void *mmio_base;
961 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 962 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 963 int rc;
964
965 VPRINTK("ENTER\n");
966
967 if (!printed_version++)
968 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
969
970 rc = pci_enable_device(pdev);
971 if (rc)
972 return rc;
973
974 rc = pci_request_regions(pdev, DRV_NAME);
975 if (rc) {
976 pci_dev_busy = 1;
977 goto err_out;
978 }
979
907f4678
JG		 980 if (pci_enable_msi(pdev) == 0)
981 have_msi = 1;
982 else {
983 pci_intx(pdev, 1);
984 have_msi = 0;
985 }
1da177e4
LT		 986
987 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
988 if (probe_ent == NULL) {
989 rc = -ENOMEM;
907f4678 990 goto err_out_msi;
1da177e4
LT		 991 }
992
993 memset(probe_ent, 0, sizeof(*probe_ent));
994 probe_ent->dev = pci_dev_to_dev(pdev);
995 INIT_LIST_HEAD(&probe_ent->node);
996
997 mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR),
998 pci_resource_len(pdev, AHCI_PCI_BAR));
999 if (mmio_base == NULL) {
1000 rc = -ENOMEM;
1001 goto err_out_free_ent;
1002 }
1003 base = (unsigned long) mmio_base;
1004
1005 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1006 if (!hpriv) {
1007 rc = -ENOMEM;
1008 goto err_out_iounmap;
1009 }
1010 memset(hpriv, 0, sizeof(*hpriv));
1011
1012 probe_ent->sht = ahci_port_info[board_idx].sht;
1013 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1014 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1015 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1016 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1017
1018 probe_ent->irq = pdev->irq;
1019 probe_ent->irq_flags = SA_SHIRQ;
1020 probe_ent->mmio_base = mmio_base;
1021 probe_ent->private_data = hpriv;
1022
4b0060f4
JG		 1023 if (have_msi)
1024 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1025
1da177e4
LT		 1026 /* initialize adapter */
1027 rc = ahci_host_init(probe_ent);
1028 if (rc)
1029 goto err_out_hpriv;
1030
1031 ahci_print_info(probe_ent);
1032
1033 /* FIXME: check ata_device_add return value */
1034 ata_device_add(probe_ent);
1035 kfree(probe_ent);
1036
1037 return 0;
1038
1039err_out_hpriv:
1040 kfree(hpriv);
1041err_out_iounmap:
1042 iounmap(mmio_base);
1043err_out_free_ent:
1044 kfree(probe_ent);
907f4678
JG		 1045err_out_msi:
1046 if (have_msi)
1047 pci_disable_msi(pdev);
1048 else
1049 pci_intx(pdev, 0);
1da177e4
LT		 1050 pci_release_regions(pdev);
1051err_out:
1052 if (!pci_dev_busy)
1053 pci_disable_device(pdev);
1054 return rc;
1055}
1056
907f4678
JG		 1057static void ahci_remove_one (struct pci_dev *pdev)
1058{
1059 struct device *dev = pci_dev_to_dev(pdev);
1060 struct ata_host_set *host_set = dev_get_drvdata(dev);
1061 struct ahci_host_priv *hpriv = host_set->private_data;
1062 struct ata_port *ap;
1063 unsigned int i;
1064 int have_msi;
1065
1066 for (i = 0; i < host_set->n_ports; i++) {
1067 ap = host_set->ports[i];
1068
1069 scsi_remove_host(ap->host);
1070 }
1071
4b0060f4 1072 have_msi = hpriv->flags & AHCI_FLAG_MSI;
907f4678 1073 free_irq(host_set->irq, host_set);
907f4678
JG		 1074
1075 for (i = 0; i < host_set->n_ports; i++) {
1076 ap = host_set->ports[i];
1077
1078 ata_scsi_release(ap->host);
1079 scsi_host_put(ap->host);
1080 }
1081
e005f01d
JG		 1082 kfree(hpriv);
1083 iounmap(host_set->mmio_base);
ead5de99
JG		 1084 kfree(host_set);
1085
907f4678
JG		 1086 if (have_msi)
1087 pci_disable_msi(pdev);
1088 else
1089 pci_intx(pdev, 0);
1090 pci_release_regions(pdev);
907f4678
JG		 1091 pci_disable_device(pdev);
1092 dev_set_drvdata(dev, NULL);
1093}
1da177e4
LT		 1094
1095static int __init ahci_init(void)
1096{
1097 return pci_module_init(&ahci_pci_driver);
1098}
1099
1da177e4
LT		 1100static void __exit ahci_exit(void)
1101{
1102 pci_unregister_driver(&ahci_pci_driver);
1103}
1104
1105
1106MODULE_AUTHOR("Jeff Garzik");
1107MODULE_DESCRIPTION("AHCI SATA low-level driver");
1108MODULE_LICENSE("GPL");
1109MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1110MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1111
1112module_init(ahci_init);
1113module_exit(ahci_exit);
kernel source for telekom puls (alcatel/mediatek)