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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/sched.h> | |
87507cfd | 43 | #include <linux/dma-mapping.h> |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
47 | #include <linux/libata.h> |
48 | #include <asm/io.h> | |
49 | ||
50 | #define DRV_NAME "ahci" | |
7bdd7208 | 51 | #define DRV_VERSION "1.2" |
1da177e4 LT |
52 | |
53 | ||
54 | enum { | |
55 | AHCI_PCI_BAR = 5, | |
56 | AHCI_MAX_SG = 168, /* hardware max is 64K */ | |
57 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
58 | AHCI_USE_CLUSTERING = 0, | |
59 | AHCI_CMD_SLOT_SZ = 32 * 32, | |
60 | AHCI_RX_FIS_SZ = 256, | |
61 | AHCI_CMD_TBL_HDR = 0x80, | |
a0ea7328 | 62 | AHCI_CMD_TBL_CDB = 0x40, |
1da177e4 LT |
63 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16), |
64 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ + | |
65 | AHCI_RX_FIS_SZ, | |
66 | AHCI_IRQ_ON_SG = (1 << 31), | |
67 | AHCI_CMD_ATAPI = (1 << 5), | |
68 | AHCI_CMD_WRITE = (1 << 6), | |
69 | ||
70 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
71 | ||
72 | board_ahci = 0, | |
73 | ||
74 | /* global controller registers */ | |
75 | HOST_CAP = 0x00, /* host capabilities */ | |
76 | HOST_CTL = 0x04, /* global host control */ | |
77 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
78 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
79 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
80 | ||
81 | /* HOST_CTL bits */ | |
82 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
83 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
84 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
85 | ||
86 | /* HOST_CAP bits */ | |
87 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ | |
88 | ||
89 | /* registers for each SATA port */ | |
90 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
91 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
92 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
93 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
94 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
95 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
96 | PORT_CMD = 0x18, /* port command */ | |
97 | PORT_TFDATA = 0x20, /* taskfile data */ | |
98 | PORT_SIG = 0x24, /* device TF signature */ | |
99 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
100 | PORT_SCR = 0x28, /* SATA phy register block */ | |
101 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ | |
102 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
103 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
104 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
105 | ||
106 | /* PORT_IRQ_{STAT,MASK} bits */ | |
107 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
108 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
109 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
110 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
111 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
112 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
113 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
114 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
115 | ||
116 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
117 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
118 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
119 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
120 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
121 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
122 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
123 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
124 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
125 | ||
126 | PORT_IRQ_FATAL = PORT_IRQ_TF_ERR | | |
127 | PORT_IRQ_HBUS_ERR | | |
128 | PORT_IRQ_HBUS_DATA_ERR | | |
129 | PORT_IRQ_IF_ERR, | |
130 | DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY | | |
131 | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE | | |
132 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS | | |
133 | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS | | |
134 | PORT_IRQ_D2H_REG_FIS, | |
135 | ||
136 | /* PORT_CMD bits */ | |
02eaa666 | 137 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
1da177e4 LT |
138 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
139 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
140 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
141 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ | |
142 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
143 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
144 | ||
145 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ | |
146 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
147 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 JG |
148 | |
149 | /* hpriv->flags bits */ | |
150 | AHCI_FLAG_MSI = (1 << 0), | |
1da177e4 LT |
151 | }; |
152 | ||
153 | struct ahci_cmd_hdr { | |
154 | u32 opts; | |
155 | u32 status; | |
156 | u32 tbl_addr; | |
157 | u32 tbl_addr_hi; | |
158 | u32 reserved[4]; | |
159 | }; | |
160 | ||
161 | struct ahci_sg { | |
162 | u32 addr; | |
163 | u32 addr_hi; | |
164 | u32 reserved; | |
165 | u32 flags_size; | |
166 | }; | |
167 | ||
168 | struct ahci_host_priv { | |
169 | unsigned long flags; | |
170 | u32 cap; /* cache of HOST_CAP register */ | |
171 | u32 port_map; /* cache of HOST_PORTS_IMPL reg */ | |
172 | }; | |
173 | ||
174 | struct ahci_port_priv { | |
175 | struct ahci_cmd_hdr *cmd_slot; | |
176 | dma_addr_t cmd_slot_dma; | |
177 | void *cmd_tbl; | |
178 | dma_addr_t cmd_tbl_dma; | |
179 | struct ahci_sg *cmd_tbl_sg; | |
180 | void *rx_fis; | |
181 | dma_addr_t rx_fis_dma; | |
182 | }; | |
183 | ||
184 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
185 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
186 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
187 | static int ahci_qc_issue(struct ata_queued_cmd *qc); | |
188 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs); | |
189 | static void ahci_phy_reset(struct ata_port *ap); | |
190 | static void ahci_irq_clear(struct ata_port *ap); | |
191 | static void ahci_eng_timeout(struct ata_port *ap); | |
192 | static int ahci_port_start(struct ata_port *ap); | |
193 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
194 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
195 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
196 | static u8 ahci_check_status(struct ata_port *ap); | |
1da177e4 | 197 | static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc); |
907f4678 | 198 | static void ahci_remove_one (struct pci_dev *pdev); |
1da177e4 | 199 | |
193515d5 | 200 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
201 | .module = THIS_MODULE, |
202 | .name = DRV_NAME, | |
203 | .ioctl = ata_scsi_ioctl, | |
204 | .queuecommand = ata_scsi_queuecmd, | |
205 | .eh_strategy_handler = ata_scsi_error, | |
206 | .can_queue = ATA_DEF_QUEUE, | |
207 | .this_id = ATA_SHT_THIS_ID, | |
208 | .sg_tablesize = AHCI_MAX_SG, | |
209 | .max_sectors = ATA_MAX_SECTORS, | |
210 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
211 | .emulated = ATA_SHT_EMULATED, | |
212 | .use_clustering = AHCI_USE_CLUSTERING, | |
213 | .proc_name = DRV_NAME, | |
214 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
215 | .slave_configure = ata_scsi_slave_config, | |
216 | .bios_param = ata_std_bios_param, | |
217 | .ordered_flush = 1, | |
218 | }; | |
219 | ||
057ace5e | 220 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
221 | .port_disable = ata_port_disable, |
222 | ||
223 | .check_status = ahci_check_status, | |
224 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
225 | .dev_select = ata_noop_dev_select, |
226 | ||
227 | .tf_read = ahci_tf_read, | |
228 | ||
229 | .phy_reset = ahci_phy_reset, | |
230 | ||
231 | .qc_prep = ahci_qc_prep, | |
232 | .qc_issue = ahci_qc_issue, | |
233 | ||
234 | .eng_timeout = ahci_eng_timeout, | |
235 | ||
236 | .irq_handler = ahci_interrupt, | |
237 | .irq_clear = ahci_irq_clear, | |
238 | ||
239 | .scr_read = ahci_scr_read, | |
240 | .scr_write = ahci_scr_write, | |
241 | ||
242 | .port_start = ahci_port_start, | |
243 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
244 | }; |
245 | ||
98ac62de | 246 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
247 | /* board_ahci */ |
248 | { | |
249 | .sht = &ahci_sht, | |
250 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
251 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | | |
252 | ATA_FLAG_PIO_DMA, | |
7da79312 | 253 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 LT |
254 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
255 | .port_ops = &ahci_ops, | |
256 | }, | |
257 | }; | |
258 | ||
3b7d697d | 259 | static const struct pci_device_id ahci_pci_tbl[] = { |
1da177e4 LT |
260 | { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
261 | board_ahci }, /* ICH6 */ | |
262 | { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
263 | board_ahci }, /* ICH6M */ | |
264 | { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
265 | board_ahci }, /* ICH7 */ | |
266 | { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
267 | board_ahci }, /* ICH7M */ | |
268 | { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
269 | board_ahci }, /* ICH7R */ | |
270 | { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
271 | board_ahci }, /* ULi M5288 */ | |
680d3235 JG |
272 | { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
273 | board_ahci }, /* ESB2 */ | |
274 | { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
275 | board_ahci }, /* ESB2 */ | |
276 | { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
277 | board_ahci }, /* ESB2 */ | |
3db368f7 JG |
278 | { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
279 | board_ahci }, /* ICH7-M DH */ | |
1da177e4 LT |
280 | { } /* terminate list */ |
281 | }; | |
282 | ||
283 | ||
284 | static struct pci_driver ahci_pci_driver = { | |
285 | .name = DRV_NAME, | |
286 | .id_table = ahci_pci_tbl, | |
287 | .probe = ahci_init_one, | |
907f4678 | 288 | .remove = ahci_remove_one, |
1da177e4 LT |
289 | }; |
290 | ||
291 | ||
292 | static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port) | |
293 | { | |
294 | return base + 0x100 + (port * 0x80); | |
295 | } | |
296 | ||
ea6ba10b | 297 | static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port) |
1da177e4 | 298 | { |
ea6ba10b | 299 | return (void __iomem *) ahci_port_base_ul((unsigned long)base, port); |
1da177e4 LT |
300 | } |
301 | ||
1da177e4 LT |
302 | static int ahci_port_start(struct ata_port *ap) |
303 | { | |
304 | struct device *dev = ap->host_set->dev; | |
305 | struct ahci_host_priv *hpriv = ap->host_set->private_data; | |
306 | struct ahci_port_priv *pp; | |
ea6ba10b JG |
307 | void __iomem *mmio = ap->host_set->mmio_base; |
308 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
309 | void *mem; | |
1da177e4 | 310 | dma_addr_t mem_dma; |
6037d6bb | 311 | int rc; |
1da177e4 | 312 | |
1da177e4 | 313 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); |
0a139e79 TH |
314 | if (!pp) |
315 | return -ENOMEM; | |
1da177e4 LT |
316 | memset(pp, 0, sizeof(*pp)); |
317 | ||
6037d6bb JG |
318 | rc = ata_pad_alloc(ap, dev); |
319 | if (rc) { | |
cedc9a47 | 320 | kfree(pp); |
6037d6bb | 321 | return rc; |
cedc9a47 JG |
322 | } |
323 | ||
1da177e4 LT |
324 | mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); |
325 | if (!mem) { | |
6037d6bb | 326 | ata_pad_free(ap, dev); |
0a139e79 TH |
327 | kfree(pp); |
328 | return -ENOMEM; | |
1da177e4 LT |
329 | } |
330 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
331 | ||
332 | /* | |
333 | * First item in chunk of DMA memory: 32-slot command table, | |
334 | * 32 bytes each in size | |
335 | */ | |
336 | pp->cmd_slot = mem; | |
337 | pp->cmd_slot_dma = mem_dma; | |
338 | ||
339 | mem += AHCI_CMD_SLOT_SZ; | |
340 | mem_dma += AHCI_CMD_SLOT_SZ; | |
341 | ||
342 | /* | |
343 | * Second item: Received-FIS area | |
344 | */ | |
345 | pp->rx_fis = mem; | |
346 | pp->rx_fis_dma = mem_dma; | |
347 | ||
348 | mem += AHCI_RX_FIS_SZ; | |
349 | mem_dma += AHCI_RX_FIS_SZ; | |
350 | ||
351 | /* | |
352 | * Third item: data area for storing a single command | |
353 | * and its scatter-gather table | |
354 | */ | |
355 | pp->cmd_tbl = mem; | |
356 | pp->cmd_tbl_dma = mem_dma; | |
357 | ||
358 | pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR; | |
359 | ||
360 | ap->private_data = pp; | |
361 | ||
362 | if (hpriv->cap & HOST_CAP_64) | |
363 | writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); | |
364 | writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
365 | readl(port_mmio + PORT_LST_ADDR); /* flush */ | |
366 | ||
367 | if (hpriv->cap & HOST_CAP_64) | |
368 | writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); | |
369 | writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
370 | readl(port_mmio + PORT_FIS_ADDR); /* flush */ | |
371 | ||
372 | writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | | |
373 | PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | | |
374 | PORT_CMD_START, port_mmio + PORT_CMD); | |
375 | readl(port_mmio + PORT_CMD); /* flush */ | |
376 | ||
377 | return 0; | |
1da177e4 LT |
378 | } |
379 | ||
380 | ||
381 | static void ahci_port_stop(struct ata_port *ap) | |
382 | { | |
383 | struct device *dev = ap->host_set->dev; | |
384 | struct ahci_port_priv *pp = ap->private_data; | |
ea6ba10b JG |
385 | void __iomem *mmio = ap->host_set->mmio_base; |
386 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1da177e4 LT |
387 | u32 tmp; |
388 | ||
389 | tmp = readl(port_mmio + PORT_CMD); | |
390 | tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX); | |
391 | writel(tmp, port_mmio + PORT_CMD); | |
392 | readl(port_mmio + PORT_CMD); /* flush */ | |
393 | ||
394 | /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so | |
395 | * this is slightly incorrect. | |
396 | */ | |
397 | msleep(500); | |
398 | ||
399 | ap->private_data = NULL; | |
400 | dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, | |
401 | pp->cmd_slot, pp->cmd_slot_dma); | |
6037d6bb | 402 | ata_pad_free(ap, dev); |
1da177e4 | 403 | kfree(pp); |
1da177e4 LT |
404 | } |
405 | ||
406 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) | |
407 | { | |
408 | unsigned int sc_reg; | |
409 | ||
410 | switch (sc_reg_in) { | |
411 | case SCR_STATUS: sc_reg = 0; break; | |
412 | case SCR_CONTROL: sc_reg = 1; break; | |
413 | case SCR_ERROR: sc_reg = 2; break; | |
414 | case SCR_ACTIVE: sc_reg = 3; break; | |
415 | default: | |
416 | return 0xffffffffU; | |
417 | } | |
418 | ||
1e4f2a96 | 419 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
420 | } |
421 | ||
422 | ||
423 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, | |
424 | u32 val) | |
425 | { | |
426 | unsigned int sc_reg; | |
427 | ||
428 | switch (sc_reg_in) { | |
429 | case SCR_STATUS: sc_reg = 0; break; | |
430 | case SCR_CONTROL: sc_reg = 1; break; | |
431 | case SCR_ERROR: sc_reg = 2; break; | |
432 | case SCR_ACTIVE: sc_reg = 3; break; | |
433 | default: | |
434 | return; | |
435 | } | |
436 | ||
1e4f2a96 | 437 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
438 | } |
439 | ||
440 | static void ahci_phy_reset(struct ata_port *ap) | |
441 | { | |
442 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
443 | struct ata_taskfile tf; | |
444 | struct ata_device *dev = &ap->device[0]; | |
02eaa666 | 445 | u32 new_tmp, tmp; |
1da177e4 LT |
446 | |
447 | __sata_phy_reset(ap); | |
448 | ||
449 | if (ap->flags & ATA_FLAG_PORT_DISABLED) | |
450 | return; | |
451 | ||
452 | tmp = readl(port_mmio + PORT_SIG); | |
453 | tf.lbah = (tmp >> 24) & 0xff; | |
454 | tf.lbam = (tmp >> 16) & 0xff; | |
455 | tf.lbal = (tmp >> 8) & 0xff; | |
456 | tf.nsect = (tmp) & 0xff; | |
457 | ||
458 | dev->class = ata_dev_classify(&tf); | |
02eaa666 | 459 | if (!ata_dev_present(dev)) { |
1da177e4 | 460 | ata_port_disable(ap); |
02eaa666 JG |
461 | return; |
462 | } | |
463 | ||
464 | /* Make sure port's ATAPI bit is set appropriately */ | |
465 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
466 | if (dev->class == ATA_DEV_ATAPI) | |
467 | new_tmp |= PORT_CMD_ATAPI; | |
468 | else | |
469 | new_tmp &= ~PORT_CMD_ATAPI; | |
470 | if (new_tmp != tmp) { | |
471 | writel(new_tmp, port_mmio + PORT_CMD); | |
472 | readl(port_mmio + PORT_CMD); /* flush */ | |
473 | } | |
1da177e4 LT |
474 | } |
475 | ||
476 | static u8 ahci_check_status(struct ata_port *ap) | |
477 | { | |
1e4f2a96 | 478 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
1da177e4 LT |
479 | |
480 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
481 | } | |
482 | ||
1da177e4 LT |
483 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
484 | { | |
485 | struct ahci_port_priv *pp = ap->private_data; | |
486 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
487 | ||
488 | ata_tf_from_fis(d2h_fis, tf); | |
489 | } | |
490 | ||
828d09de | 491 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc) |
1da177e4 LT |
492 | { |
493 | struct ahci_port_priv *pp = qc->ap->private_data; | |
cedc9a47 JG |
494 | struct scatterlist *sg; |
495 | struct ahci_sg *ahci_sg; | |
828d09de | 496 | unsigned int n_sg = 0; |
1da177e4 LT |
497 | |
498 | VPRINTK("ENTER\n"); | |
499 | ||
500 | /* | |
501 | * Next, the S/G list. | |
502 | */ | |
cedc9a47 JG |
503 | ahci_sg = pp->cmd_tbl_sg; |
504 | ata_for_each_sg(sg, qc) { | |
505 | dma_addr_t addr = sg_dma_address(sg); | |
506 | u32 sg_len = sg_dma_len(sg); | |
507 | ||
508 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
509 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
510 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 511 | |
cedc9a47 | 512 | ahci_sg++; |
828d09de | 513 | n_sg++; |
1da177e4 | 514 | } |
828d09de JG |
515 | |
516 | return n_sg; | |
1da177e4 LT |
517 | } |
518 | ||
519 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
520 | { | |
a0ea7328 JG |
521 | struct ata_port *ap = qc->ap; |
522 | struct ahci_port_priv *pp = ap->private_data; | |
1da177e4 LT |
523 | u32 opts; |
524 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 525 | unsigned int n_elem; |
1da177e4 LT |
526 | |
527 | /* | |
528 | * Fill in command slot information (currently only one slot, | |
529 | * slot 0, is currently since we don't do queueing) | |
530 | */ | |
531 | ||
828d09de | 532 | opts = cmd_fis_len; |
1da177e4 LT |
533 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
534 | opts |= AHCI_CMD_WRITE; | |
a0ea7328 | 535 | if (is_atapi_taskfile(&qc->tf)) |
1da177e4 | 536 | opts |= AHCI_CMD_ATAPI; |
1da177e4 LT |
537 | |
538 | pp->cmd_slot[0].opts = cpu_to_le32(opts); | |
539 | pp->cmd_slot[0].status = 0; | |
540 | pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff); | |
541 | pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16); | |
542 | ||
543 | /* | |
544 | * Fill in command table information. First, the header, | |
545 | * a SATA Register - Host to Device command FIS. | |
546 | */ | |
547 | ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0); | |
a0ea7328 JG |
548 | if (opts & AHCI_CMD_ATAPI) { |
549 | memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); | |
550 | memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len); | |
551 | } | |
1da177e4 LT |
552 | |
553 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
554 | return; | |
555 | ||
828d09de JG |
556 | n_elem = ahci_fill_sg(qc); |
557 | ||
558 | pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16); | |
1da177e4 LT |
559 | } |
560 | ||
c2cd76ff | 561 | static void ahci_restart_port(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 562 | { |
ea6ba10b JG |
563 | void __iomem *mmio = ap->host_set->mmio_base; |
564 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1da177e4 LT |
565 | u32 tmp; |
566 | int work; | |
567 | ||
c2cd76ff JG |
568 | if ((ap->device[0].class != ATA_DEV_ATAPI) || |
569 | ((irq_stat & PORT_IRQ_TF_ERR) == 0)) | |
570 | printk(KERN_WARNING "ata%u: port reset, " | |
571 | "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n", | |
572 | ap->id, | |
573 | irq_stat, | |
574 | readl(mmio + HOST_IRQ_STAT), | |
575 | readl(port_mmio + PORT_IRQ_STAT), | |
576 | readl(port_mmio + PORT_CMD), | |
577 | readl(port_mmio + PORT_TFDATA), | |
578 | readl(port_mmio + PORT_SCR_STAT), | |
579 | readl(port_mmio + PORT_SCR_ERR)); | |
9f68a248 | 580 | |
1da177e4 LT |
581 | /* stop DMA */ |
582 | tmp = readl(port_mmio + PORT_CMD); | |
583 | tmp &= ~PORT_CMD_START; | |
584 | writel(tmp, port_mmio + PORT_CMD); | |
585 | ||
586 | /* wait for engine to stop. TODO: this could be | |
587 | * as long as 500 msec | |
588 | */ | |
589 | work = 1000; | |
590 | while (work-- > 0) { | |
591 | tmp = readl(port_mmio + PORT_CMD); | |
592 | if ((tmp & PORT_CMD_LIST_ON) == 0) | |
593 | break; | |
594 | udelay(10); | |
595 | } | |
596 | ||
597 | /* clear SATA phy error, if any */ | |
598 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
599 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
600 | ||
601 | /* if DRQ/BSY is set, device needs to be reset. | |
602 | * if so, issue COMRESET | |
603 | */ | |
604 | tmp = readl(port_mmio + PORT_TFDATA); | |
605 | if (tmp & (ATA_BUSY | ATA_DRQ)) { | |
606 | writel(0x301, port_mmio + PORT_SCR_CTL); | |
607 | readl(port_mmio + PORT_SCR_CTL); /* flush */ | |
608 | udelay(10); | |
609 | writel(0x300, port_mmio + PORT_SCR_CTL); | |
610 | readl(port_mmio + PORT_SCR_CTL); /* flush */ | |
611 | } | |
612 | ||
613 | /* re-start DMA */ | |
614 | tmp = readl(port_mmio + PORT_CMD); | |
615 | tmp |= PORT_CMD_START; | |
616 | writel(tmp, port_mmio + PORT_CMD); | |
617 | readl(port_mmio + PORT_CMD); /* flush */ | |
1da177e4 LT |
618 | } |
619 | ||
620 | static void ahci_eng_timeout(struct ata_port *ap) | |
621 | { | |
b8f6153e | 622 | struct ata_host_set *host_set = ap->host_set; |
ea6ba10b JG |
623 | void __iomem *mmio = host_set->mmio_base; |
624 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1da177e4 | 625 | struct ata_queued_cmd *qc; |
b8f6153e | 626 | unsigned long flags; |
1da177e4 | 627 | |
9f68a248 | 628 | printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id); |
1da177e4 | 629 | |
b8f6153e JG |
630 | spin_lock_irqsave(&host_set->lock, flags); |
631 | ||
1da177e4 LT |
632 | qc = ata_qc_from_tag(ap, ap->active_tag); |
633 | if (!qc) { | |
634 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", | |
635 | ap->id); | |
636 | } else { | |
c2cd76ff | 637 | ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT)); |
ad36d1a5 | 638 | |
1da177e4 LT |
639 | /* hack alert! We cannot use the supplied completion |
640 | * function from inside the ->eh_strategy_handler() thread. | |
641 | * libata is the only user of ->eh_strategy_handler() in | |
642 | * any kernel, so the default scsi_done() assumes it is | |
643 | * not being called from the SCSI EH. | |
644 | */ | |
645 | qc->scsidone = scsi_finish_command; | |
a22e2eb0 AL |
646 | qc->err_mask |= AC_ERR_OTHER; |
647 | ata_qc_complete(qc); | |
1da177e4 LT |
648 | } |
649 | ||
b8f6153e | 650 | spin_unlock_irqrestore(&host_set->lock, flags); |
1da177e4 LT |
651 | } |
652 | ||
653 | static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc) | |
654 | { | |
ea6ba10b JG |
655 | void __iomem *mmio = ap->host_set->mmio_base; |
656 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1da177e4 LT |
657 | u32 status, serr, ci; |
658 | ||
659 | serr = readl(port_mmio + PORT_SCR_ERR); | |
660 | writel(serr, port_mmio + PORT_SCR_ERR); | |
661 | ||
662 | status = readl(port_mmio + PORT_IRQ_STAT); | |
663 | writel(status, port_mmio + PORT_IRQ_STAT); | |
664 | ||
665 | ci = readl(port_mmio + PORT_CMD_ISSUE); | |
666 | if (likely((ci & 0x1) == 0)) { | |
667 | if (qc) { | |
a22e2eb0 AL |
668 | assert(qc->err_mask == 0); |
669 | ata_qc_complete(qc); | |
1da177e4 LT |
670 | qc = NULL; |
671 | } | |
672 | } | |
673 | ||
674 | if (status & PORT_IRQ_FATAL) { | |
ad36d1a5 JG |
675 | unsigned int err_mask; |
676 | if (status & PORT_IRQ_TF_ERR) | |
677 | err_mask = AC_ERR_DEV; | |
678 | else if (status & PORT_IRQ_IF_ERR) | |
679 | err_mask = AC_ERR_ATA_BUS; | |
680 | else | |
681 | err_mask = AC_ERR_HOST_BUS; | |
682 | ||
9f68a248 | 683 | /* command processing has stopped due to error; restart */ |
c2cd76ff | 684 | ahci_restart_port(ap, status); |
9f68a248 | 685 | |
a22e2eb0 AL |
686 | if (qc) { |
687 | qc->err_mask |= AC_ERR_OTHER; | |
688 | ata_qc_complete(qc); | |
689 | } | |
1da177e4 LT |
690 | } |
691 | ||
692 | return 1; | |
693 | } | |
694 | ||
695 | static void ahci_irq_clear(struct ata_port *ap) | |
696 | { | |
697 | /* TODO */ | |
698 | } | |
699 | ||
700 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs) | |
701 | { | |
702 | struct ata_host_set *host_set = dev_instance; | |
703 | struct ahci_host_priv *hpriv; | |
704 | unsigned int i, handled = 0; | |
ea6ba10b | 705 | void __iomem *mmio; |
1da177e4 LT |
706 | u32 irq_stat, irq_ack = 0; |
707 | ||
708 | VPRINTK("ENTER\n"); | |
709 | ||
710 | hpriv = host_set->private_data; | |
711 | mmio = host_set->mmio_base; | |
712 | ||
713 | /* sigh. 0xffffffff is a valid return from h/w */ | |
714 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
715 | irq_stat &= hpriv->port_map; | |
716 | if (!irq_stat) | |
717 | return IRQ_NONE; | |
718 | ||
719 | spin_lock(&host_set->lock); | |
720 | ||
721 | for (i = 0; i < host_set->n_ports; i++) { | |
722 | struct ata_port *ap; | |
1da177e4 | 723 | |
67846b30 JG |
724 | if (!(irq_stat & (1 << i))) |
725 | continue; | |
726 | ||
1da177e4 | 727 | ap = host_set->ports[i]; |
67846b30 | 728 | if (ap) { |
1da177e4 LT |
729 | struct ata_queued_cmd *qc; |
730 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
67846b30 JG |
731 | if (!ahci_host_intr(ap, qc)) |
732 | if (ata_ratelimit()) { | |
733 | struct pci_dev *pdev = | |
a9524a76 JG |
734 | to_pci_dev(ap->host_set->dev); |
735 | dev_printk(KERN_WARNING, &pdev->dev, | |
736 | "unhandled interrupt on port %u\n", | |
737 | i); | |
67846b30 JG |
738 | } |
739 | ||
740 | VPRINTK("port %u\n", i); | |
741 | } else { | |
742 | VPRINTK("port %u (no irq)\n", i); | |
743 | if (ata_ratelimit()) { | |
744 | struct pci_dev *pdev = | |
a9524a76 JG |
745 | to_pci_dev(ap->host_set->dev); |
746 | dev_printk(KERN_WARNING, &pdev->dev, | |
747 | "interrupt on disabled port %u\n", i); | |
67846b30 | 748 | } |
1da177e4 | 749 | } |
67846b30 JG |
750 | |
751 | irq_ack |= (1 << i); | |
1da177e4 LT |
752 | } |
753 | ||
754 | if (irq_ack) { | |
755 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
756 | handled = 1; | |
757 | } | |
758 | ||
759 | spin_unlock(&host_set->lock); | |
760 | ||
761 | VPRINTK("EXIT\n"); | |
762 | ||
763 | return IRQ_RETVAL(handled); | |
764 | } | |
765 | ||
766 | static int ahci_qc_issue(struct ata_queued_cmd *qc) | |
767 | { | |
768 | struct ata_port *ap = qc->ap; | |
ea6ba10b | 769 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
1da177e4 | 770 | |
1da177e4 LT |
771 | writel(1, port_mmio + PORT_CMD_ISSUE); |
772 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
777 | static void ahci_setup_port(struct ata_ioports *port, unsigned long base, | |
778 | unsigned int port_idx) | |
779 | { | |
780 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); | |
781 | base = ahci_port_base_ul(base, port_idx); | |
782 | VPRINTK("base now==0x%lx\n", base); | |
783 | ||
784 | port->cmd_addr = base; | |
785 | port->scr_addr = base + PORT_SCR; | |
786 | ||
787 | VPRINTK("EXIT\n"); | |
788 | } | |
789 | ||
790 | static int ahci_host_init(struct ata_probe_ent *probe_ent) | |
791 | { | |
792 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
793 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
794 | void __iomem *mmio = probe_ent->mmio_base; | |
795 | u32 tmp, cap_save; | |
796 | u16 tmp16; | |
797 | unsigned int i, j, using_dac; | |
798 | int rc; | |
799 | void __iomem *port_mmio; | |
800 | ||
801 | cap_save = readl(mmio + HOST_CAP); | |
802 | cap_save &= ( (1<<28) | (1<<17) ); | |
803 | cap_save |= (1 << 27); | |
804 | ||
805 | /* global controller reset */ | |
806 | tmp = readl(mmio + HOST_CTL); | |
807 | if ((tmp & HOST_RESET) == 0) { | |
808 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
809 | readl(mmio + HOST_CTL); /* flush */ | |
810 | } | |
811 | ||
812 | /* reset must complete within 1 second, or | |
813 | * the hardware should be considered fried. | |
814 | */ | |
815 | ssleep(1); | |
816 | ||
817 | tmp = readl(mmio + HOST_CTL); | |
818 | if (tmp & HOST_RESET) { | |
a9524a76 JG |
819 | dev_printk(KERN_ERR, &pdev->dev, |
820 | "controller reset failed (0x%x)\n", tmp); | |
1da177e4 LT |
821 | return -EIO; |
822 | } | |
823 | ||
824 | writel(HOST_AHCI_EN, mmio + HOST_CTL); | |
825 | (void) readl(mmio + HOST_CTL); /* flush */ | |
826 | writel(cap_save, mmio + HOST_CAP); | |
827 | writel(0xf, mmio + HOST_PORTS_IMPL); | |
828 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ | |
829 | ||
830 | pci_read_config_word(pdev, 0x92, &tmp16); | |
831 | tmp16 |= 0xf; | |
832 | pci_write_config_word(pdev, 0x92, tmp16); | |
833 | ||
834 | hpriv->cap = readl(mmio + HOST_CAP); | |
835 | hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); | |
836 | probe_ent->n_ports = (hpriv->cap & 0x1f) + 1; | |
837 | ||
838 | VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", | |
839 | hpriv->cap, hpriv->port_map, probe_ent->n_ports); | |
840 | ||
841 | using_dac = hpriv->cap & HOST_CAP_64; | |
842 | if (using_dac && | |
843 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
844 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
845 | if (rc) { | |
846 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
847 | if (rc) { | |
a9524a76 JG |
848 | dev_printk(KERN_ERR, &pdev->dev, |
849 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
850 | return rc; |
851 | } | |
852 | } | |
1da177e4 LT |
853 | } else { |
854 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
855 | if (rc) { | |
a9524a76 JG |
856 | dev_printk(KERN_ERR, &pdev->dev, |
857 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
858 | return rc; |
859 | } | |
860 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
861 | if (rc) { | |
a9524a76 JG |
862 | dev_printk(KERN_ERR, &pdev->dev, |
863 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
864 | return rc; |
865 | } | |
866 | } | |
867 | ||
868 | for (i = 0; i < probe_ent->n_ports; i++) { | |
869 | #if 0 /* BIOSen initialize this incorrectly */ | |
870 | if (!(hpriv->port_map & (1 << i))) | |
871 | continue; | |
872 | #endif | |
873 | ||
874 | port_mmio = ahci_port_base(mmio, i); | |
875 | VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio); | |
876 | ||
877 | ahci_setup_port(&probe_ent->port[i], | |
878 | (unsigned long) mmio, i); | |
879 | ||
880 | /* make sure port is not active */ | |
881 | tmp = readl(port_mmio + PORT_CMD); | |
882 | VPRINTK("PORT_CMD 0x%x\n", tmp); | |
883 | if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
884 | PORT_CMD_FIS_RX | PORT_CMD_START)) { | |
885 | tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | | |
886 | PORT_CMD_FIS_RX | PORT_CMD_START); | |
887 | writel(tmp, port_mmio + PORT_CMD); | |
888 | readl(port_mmio + PORT_CMD); /* flush */ | |
889 | ||
890 | /* spec says 500 msecs for each bit, so | |
891 | * this is slightly incorrect. | |
892 | */ | |
893 | msleep(500); | |
894 | } | |
895 | ||
896 | writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD); | |
897 | ||
898 | j = 0; | |
899 | while (j < 100) { | |
900 | msleep(10); | |
901 | tmp = readl(port_mmio + PORT_SCR_STAT); | |
902 | if ((tmp & 0xf) == 0x3) | |
903 | break; | |
904 | j++; | |
905 | } | |
906 | ||
907 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
908 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
909 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
910 | ||
911 | /* ack any pending irq events for this port */ | |
912 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
913 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
914 | if (tmp) | |
915 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
916 | ||
917 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
918 | ||
919 | /* set irq mask (enables interrupts) */ | |
920 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
921 | } | |
922 | ||
923 | tmp = readl(mmio + HOST_CTL); | |
924 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
925 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
926 | tmp = readl(mmio + HOST_CTL); | |
927 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
928 | ||
929 | pci_set_master(pdev); | |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
1da177e4 LT |
934 | static void ahci_print_info(struct ata_probe_ent *probe_ent) |
935 | { | |
936 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
937 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
ea6ba10b | 938 | void __iomem *mmio = probe_ent->mmio_base; |
1da177e4 LT |
939 | u32 vers, cap, impl, speed; |
940 | const char *speed_s; | |
941 | u16 cc; | |
942 | const char *scc_s; | |
943 | ||
944 | vers = readl(mmio + HOST_VERSION); | |
945 | cap = hpriv->cap; | |
946 | impl = hpriv->port_map; | |
947 | ||
948 | speed = (cap >> 20) & 0xf; | |
949 | if (speed == 1) | |
950 | speed_s = "1.5"; | |
951 | else if (speed == 2) | |
952 | speed_s = "3"; | |
953 | else | |
954 | speed_s = "?"; | |
955 | ||
956 | pci_read_config_word(pdev, 0x0a, &cc); | |
957 | if (cc == 0x0101) | |
958 | scc_s = "IDE"; | |
959 | else if (cc == 0x0106) | |
960 | scc_s = "SATA"; | |
961 | else if (cc == 0x0104) | |
962 | scc_s = "RAID"; | |
963 | else | |
964 | scc_s = "unknown"; | |
965 | ||
a9524a76 JG |
966 | dev_printk(KERN_INFO, &pdev->dev, |
967 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 LT |
968 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
969 | , | |
1da177e4 LT |
970 | |
971 | (vers >> 24) & 0xff, | |
972 | (vers >> 16) & 0xff, | |
973 | (vers >> 8) & 0xff, | |
974 | vers & 0xff, | |
975 | ||
976 | ((cap >> 8) & 0x1f) + 1, | |
977 | (cap & 0x1f) + 1, | |
978 | speed_s, | |
979 | impl, | |
980 | scc_s); | |
981 | ||
a9524a76 JG |
982 | dev_printk(KERN_INFO, &pdev->dev, |
983 | "flags: " | |
1da177e4 LT |
984 | "%s%s%s%s%s%s" |
985 | "%s%s%s%s%s%s%s\n" | |
986 | , | |
1da177e4 LT |
987 | |
988 | cap & (1 << 31) ? "64bit " : "", | |
989 | cap & (1 << 30) ? "ncq " : "", | |
990 | cap & (1 << 28) ? "ilck " : "", | |
991 | cap & (1 << 27) ? "stag " : "", | |
992 | cap & (1 << 26) ? "pm " : "", | |
993 | cap & (1 << 25) ? "led " : "", | |
994 | ||
995 | cap & (1 << 24) ? "clo " : "", | |
996 | cap & (1 << 19) ? "nz " : "", | |
997 | cap & (1 << 18) ? "only " : "", | |
998 | cap & (1 << 17) ? "pmp " : "", | |
999 | cap & (1 << 15) ? "pio " : "", | |
1000 | cap & (1 << 14) ? "slum " : "", | |
1001 | cap & (1 << 13) ? "part " : "" | |
1002 | ); | |
1003 | } | |
1004 | ||
1005 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1006 | { | |
1007 | static int printed_version; | |
1008 | struct ata_probe_ent *probe_ent = NULL; | |
1009 | struct ahci_host_priv *hpriv; | |
1010 | unsigned long base; | |
ea6ba10b | 1011 | void __iomem *mmio_base; |
1da177e4 | 1012 | unsigned int board_idx = (unsigned int) ent->driver_data; |
907f4678 | 1013 | int have_msi, pci_dev_busy = 0; |
1da177e4 LT |
1014 | int rc; |
1015 | ||
1016 | VPRINTK("ENTER\n"); | |
1017 | ||
1018 | if (!printed_version++) | |
a9524a76 | 1019 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
1020 | |
1021 | rc = pci_enable_device(pdev); | |
1022 | if (rc) | |
1023 | return rc; | |
1024 | ||
1025 | rc = pci_request_regions(pdev, DRV_NAME); | |
1026 | if (rc) { | |
1027 | pci_dev_busy = 1; | |
1028 | goto err_out; | |
1029 | } | |
1030 | ||
907f4678 JG |
1031 | if (pci_enable_msi(pdev) == 0) |
1032 | have_msi = 1; | |
1033 | else { | |
1034 | pci_intx(pdev, 1); | |
1035 | have_msi = 0; | |
1036 | } | |
1da177e4 LT |
1037 | |
1038 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
1039 | if (probe_ent == NULL) { | |
1040 | rc = -ENOMEM; | |
907f4678 | 1041 | goto err_out_msi; |
1da177e4 LT |
1042 | } |
1043 | ||
1044 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
1045 | probe_ent->dev = pci_dev_to_dev(pdev); | |
1046 | INIT_LIST_HEAD(&probe_ent->node); | |
1047 | ||
374b1873 | 1048 | mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0); |
1da177e4 LT |
1049 | if (mmio_base == NULL) { |
1050 | rc = -ENOMEM; | |
1051 | goto err_out_free_ent; | |
1052 | } | |
1053 | base = (unsigned long) mmio_base; | |
1054 | ||
1055 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
1056 | if (!hpriv) { | |
1057 | rc = -ENOMEM; | |
1058 | goto err_out_iounmap; | |
1059 | } | |
1060 | memset(hpriv, 0, sizeof(*hpriv)); | |
1061 | ||
1062 | probe_ent->sht = ahci_port_info[board_idx].sht; | |
1063 | probe_ent->host_flags = ahci_port_info[board_idx].host_flags; | |
1064 | probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; | |
1065 | probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; | |
1066 | probe_ent->port_ops = ahci_port_info[board_idx].port_ops; | |
1067 | ||
1068 | probe_ent->irq = pdev->irq; | |
1069 | probe_ent->irq_flags = SA_SHIRQ; | |
1070 | probe_ent->mmio_base = mmio_base; | |
1071 | probe_ent->private_data = hpriv; | |
1072 | ||
4b0060f4 JG |
1073 | if (have_msi) |
1074 | hpriv->flags |= AHCI_FLAG_MSI; | |
907f4678 | 1075 | |
1da177e4 LT |
1076 | /* initialize adapter */ |
1077 | rc = ahci_host_init(probe_ent); | |
1078 | if (rc) | |
1079 | goto err_out_hpriv; | |
1080 | ||
1081 | ahci_print_info(probe_ent); | |
1082 | ||
1083 | /* FIXME: check ata_device_add return value */ | |
1084 | ata_device_add(probe_ent); | |
1085 | kfree(probe_ent); | |
1086 | ||
1087 | return 0; | |
1088 | ||
1089 | err_out_hpriv: | |
1090 | kfree(hpriv); | |
1091 | err_out_iounmap: | |
374b1873 | 1092 | pci_iounmap(pdev, mmio_base); |
1da177e4 LT |
1093 | err_out_free_ent: |
1094 | kfree(probe_ent); | |
907f4678 JG |
1095 | err_out_msi: |
1096 | if (have_msi) | |
1097 | pci_disable_msi(pdev); | |
1098 | else | |
1099 | pci_intx(pdev, 0); | |
1da177e4 LT |
1100 | pci_release_regions(pdev); |
1101 | err_out: | |
1102 | if (!pci_dev_busy) | |
1103 | pci_disable_device(pdev); | |
1104 | return rc; | |
1105 | } | |
1106 | ||
907f4678 JG |
1107 | static void ahci_remove_one (struct pci_dev *pdev) |
1108 | { | |
1109 | struct device *dev = pci_dev_to_dev(pdev); | |
1110 | struct ata_host_set *host_set = dev_get_drvdata(dev); | |
1111 | struct ahci_host_priv *hpriv = host_set->private_data; | |
1112 | struct ata_port *ap; | |
1113 | unsigned int i; | |
1114 | int have_msi; | |
1115 | ||
1116 | for (i = 0; i < host_set->n_ports; i++) { | |
1117 | ap = host_set->ports[i]; | |
1118 | ||
1119 | scsi_remove_host(ap->host); | |
1120 | } | |
1121 | ||
4b0060f4 | 1122 | have_msi = hpriv->flags & AHCI_FLAG_MSI; |
907f4678 | 1123 | free_irq(host_set->irq, host_set); |
907f4678 JG |
1124 | |
1125 | for (i = 0; i < host_set->n_ports; i++) { | |
1126 | ap = host_set->ports[i]; | |
1127 | ||
1128 | ata_scsi_release(ap->host); | |
1129 | scsi_host_put(ap->host); | |
1130 | } | |
1131 | ||
e005f01d | 1132 | kfree(hpriv); |
374b1873 | 1133 | pci_iounmap(pdev, host_set->mmio_base); |
ead5de99 JG |
1134 | kfree(host_set); |
1135 | ||
907f4678 JG |
1136 | if (have_msi) |
1137 | pci_disable_msi(pdev); | |
1138 | else | |
1139 | pci_intx(pdev, 0); | |
1140 | pci_release_regions(pdev); | |
907f4678 JG |
1141 | pci_disable_device(pdev); |
1142 | dev_set_drvdata(dev, NULL); | |
1143 | } | |
1da177e4 LT |
1144 | |
1145 | static int __init ahci_init(void) | |
1146 | { | |
1147 | return pci_module_init(&ahci_pci_driver); | |
1148 | } | |
1149 | ||
1da177e4 LT |
1150 | static void __exit ahci_exit(void) |
1151 | { | |
1152 | pci_unregister_driver(&ahci_pci_driver); | |
1153 | } | |
1154 | ||
1155 | ||
1156 | MODULE_AUTHOR("Jeff Garzik"); | |
1157 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1158 | MODULE_LICENSE("GPL"); | |
1159 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1160 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
1161 | |
1162 | module_init(ahci_init); | |
1163 | module_exit(ahci_exit); |